VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 91297

Last change on this file since 91297 was 91297, checked in by vboxsync, 3 years ago

VMM/CPUM,++: Moved the nested VT-X VMCS allocation into CPUMCTX. bugref:10093
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 91297 2021-09-17 11:51:23Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_EPT_VIOLATION
177 * VMX_EXIT_EPT_MISCONFIG
178 * VMX_EXIT_INVEPT
179 * VMX_EXIT_RDRAND
180 * VMX_EXIT_VMFUNC
181 * VMX_EXIT_ENCLS
182 * VMX_EXIT_RDSEED
183 * VMX_EXIT_PML_FULL
184 * VMX_EXIT_XSAVES
185 * VMX_EXIT_XRSTORS
186 */
187/**
188 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
189 *
190 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
191 * second dimension is the Index, see VMXVMCSFIELD.
192 */
193uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
194{
195 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
196 {
197 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
198 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
199 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
200 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
201 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 27 */ UINT16_MAX,
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 26-27 */ UINT16_MAX, UINT16_MAX
227 },
228 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
233 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
234 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
235 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
236 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
237 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
239 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
240 },
241 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
242 {
243 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
244 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
245 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
246 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
247 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
248 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
249 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
250 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
251 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
252 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
253 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
254 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
255 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
256 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
257 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
258 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
259 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
260 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
261 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
262 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
263 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
264 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
265 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
266 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
267 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
268 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
269 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
270 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
271 },
272 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
273 {
274 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
275 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
276 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
277 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
278 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
279 },
280 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
281 {
282 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
283 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
284 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
285 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
286 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
287 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
288 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
289 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
290 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
291 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
292 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
293 /* 11 */ UINT16_MAX,
294 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
295 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
296 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
297 },
298 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
299 {
300 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
301 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
302 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
303 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
304 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
307 },
308 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
309 {
310 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
311 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
312 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
313 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
314 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
315 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
316 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
317 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
318 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
319 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
320 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
321 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
322 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
323 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
324 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
325 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
326 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
327 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
328 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
329 /* 26-27 */ UINT16_MAX, UINT16_MAX
330 },
331 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
332 {
333 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
334 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
335 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
336 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
337 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
338 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
339 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
340 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
341 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
342 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
343 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
344 },
345 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
346 {
347 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
348 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
349 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
350 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
351 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
352 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
353 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
354 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
355 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
356 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
357 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
358 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
359 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
360 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
361 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
362 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
363 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
364 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
365 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
366 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
367 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
368 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
369 /* 22 */ UINT16_MAX,
370 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
371 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
376 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
377 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
378 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
379 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
380 },
381 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
382 {
383 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
384 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
385 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
386 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
387 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
388 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
389 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
390 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
391 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
392 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
393 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
394 },
395 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
396 {
397 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
398 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
399 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
400 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
401 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
402 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
403 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
404 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
405 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
406 },
407 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
408 {
409 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
410 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
411 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
412 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
413 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
414 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
415 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
416 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
417 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
418 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
419 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
420 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
421 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
422 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
423 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
424 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
425 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
426 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
427 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
428 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
429 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
430 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
431 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
432 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
433 },
434 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
435 {
436 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
437 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
438 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
439 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
440 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
441 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
442 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
443 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
444 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
445 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
446 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
447 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
448 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
449 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
450 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
451 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
452 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
453 }
454};
455
456
457/**
458 * Gets a host selector from the VMCS.
459 *
460 * @param pVmcs Pointer to the virtual VMCS.
461 * @param iSelReg The index of the segment register (X86_SREG_XXX).
462 */
463DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
464{
465 Assert(iSegReg < X86_SREG_COUNT);
466 RTSEL HostSel;
467 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
468 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
469 uint8_t const uWidthType = (uWidth << 2) | uType;
470 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
471 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
472 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
473 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
474 uint8_t const *pbField = pbVmcs + offField;
475 HostSel = *(uint16_t *)pbField;
476 return HostSel;
477}
478
479
480/**
481 * Sets a guest segment register in the VMCS.
482 *
483 * @param pVmcs Pointer to the virtual VMCS.
484 * @param iSegReg The index of the segment register (X86_SREG_XXX).
485 * @param pSelReg Pointer to the segment register.
486 */
487IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
488{
489 Assert(pSelReg);
490 Assert(iSegReg < X86_SREG_COUNT);
491
492 /* Selector. */
493 {
494 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
495 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
496 uint8_t const uWidthType = (uWidth << 2) | uType;
497 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
498 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
499 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
500 uint8_t *pbVmcs = (uint8_t *)pVmcs;
501 uint8_t *pbField = pbVmcs + offField;
502 *(uint16_t *)pbField = pSelReg->Sel;
503 }
504
505 /* Limit. */
506 {
507 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
508 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
509 uint8_t const uWidthType = (uWidth << 2) | uType;
510 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
511 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
512 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
513 uint8_t *pbVmcs = (uint8_t *)pVmcs;
514 uint8_t *pbField = pbVmcs + offField;
515 *(uint32_t *)pbField = pSelReg->u32Limit;
516 }
517
518 /* Base. */
519 {
520 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
521 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
522 uint8_t const uWidthType = (uWidth << 2) | uType;
523 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
524 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
525 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
526 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
527 uint8_t const *pbField = pbVmcs + offField;
528 *(uint64_t *)pbField = pSelReg->u64Base;
529 }
530
531 /* Attributes. */
532 {
533 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
534 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
535 | X86DESCATTR_UNUSABLE;
536 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
537 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
538 uint8_t const uWidthType = (uWidth << 2) | uType;
539 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
540 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
541 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
542 uint8_t *pbVmcs = (uint8_t *)pVmcs;
543 uint8_t *pbField = pbVmcs + offField;
544 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
545 }
546}
547
548
549/**
550 * Gets a guest segment register from the VMCS.
551 *
552 * @returns VBox status code.
553 * @param pVmcs Pointer to the virtual VMCS.
554 * @param iSegReg The index of the segment register (X86_SREG_XXX).
555 * @param pSelReg Where to store the segment register (only updated when
556 * VINF_SUCCESS is returned).
557 *
558 * @remarks Warning! This does not validate the contents of the retrieved segment
559 * register.
560 */
561IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
562{
563 Assert(pSelReg);
564 Assert(iSegReg < X86_SREG_COUNT);
565
566 /* Selector. */
567 uint16_t u16Sel;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u16Sel = *(uint16_t *)pbField;
578 }
579
580 /* Limit. */
581 uint32_t u32Limit;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u32Limit = *(uint32_t *)pbField;
592 }
593
594 /* Base. */
595 uint64_t u64Base;
596 {
597 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
598 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
599 uint8_t const uWidthType = (uWidth << 2) | uType;
600 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
601 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
602 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
603 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
604 uint8_t const *pbField = pbVmcs + offField;
605 u64Base = *(uint64_t *)pbField;
606 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
607 }
608
609 /* Attributes. */
610 uint32_t u32Attr;
611 {
612 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
613 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
614 uint8_t const uWidthType = (uWidth << 2) | uType;
615 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
616 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
617 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
618 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
619 uint8_t const *pbField = pbVmcs + offField;
620 u32Attr = *(uint32_t *)pbField;
621 }
622
623 pSelReg->Sel = u16Sel;
624 pSelReg->ValidSel = u16Sel;
625 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
626 pSelReg->u32Limit = u32Limit;
627 pSelReg->u64Base = u64Base;
628 pSelReg->Attr.u = u32Attr;
629 return VINF_SUCCESS;
630}
631
632
633/**
634 * Converts an IEM exception event type to a VMX event type.
635 *
636 * @returns The VMX event type.
637 * @param uVector The interrupt / exception vector.
638 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
639 */
640DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
641{
642 /* Paranoia (callers may use these interchangeably). */
643 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
644 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
645 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
646 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
647 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
648 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
649 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
650 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
651 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
652 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
653 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
654 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
655
656 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
657 {
658 if (uVector == X86_XCPT_NMI)
659 return VMX_EXIT_INT_INFO_TYPE_NMI;
660 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
661 }
662
663 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
664 {
665 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
666 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
667 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
668 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
669 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
670 }
671
672 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
673 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
674}
675
676
677/**
678 * Sets the Exit qualification VMCS field.
679 *
680 * @param pVCpu The cross context virtual CPU structure.
681 * @param u64ExitQual The Exit qualification.
682 */
683DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
684{
685 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
686}
687
688
689/**
690 * Sets the VM-exit interruption information field.
691 *
692 * @param pVCpu The cross context virtual CPU structure.
693 * @param uExitIntInfo The VM-exit interruption information.
694 */
695DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
696{
697 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
698}
699
700
701/**
702 * Sets the VM-exit interruption error code.
703 *
704 * @param pVCpu The cross context virtual CPU structure.
705 * @param uErrCode The error code.
706 */
707DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
708{
709 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
710}
711
712
713/**
714 * Sets the IDT-vectoring information field.
715 *
716 * @param pVCpu The cross context virtual CPU structure.
717 * @param uIdtVectorInfo The IDT-vectoring information.
718 */
719DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
720{
721 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
722}
723
724
725/**
726 * Sets the IDT-vectoring error code field.
727 *
728 * @param pVCpu The cross context virtual CPU structure.
729 * @param uErrCode The error code.
730 */
731DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
732{
733 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
734}
735
736
737/**
738 * Sets the VM-exit guest-linear address VMCS field.
739 *
740 * @param pVCpu The cross context virtual CPU structure.
741 * @param uGuestLinearAddr The VM-exit guest-linear address.
742 */
743DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
744{
745 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
746}
747
748
749/**
750 * Sets the VM-exit guest-physical address VMCS field.
751 *
752 * @param pVCpu The cross context virtual CPU structure.
753 * @param uGuestPhysAddr The VM-exit guest-physical address.
754 */
755DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
756{
757 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
758}
759
760
761/**
762 * Sets the VM-exit instruction length VMCS field.
763 *
764 * @param pVCpu The cross context virtual CPU structure.
765 * @param cbInstr The VM-exit instruction length in bytes.
766 *
767 * @remarks Callers may clear this field to 0. Hence, this function does not check
768 * the validity of the instruction length.
769 */
770DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
771{
772 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
773}
774
775
776/**
777 * Sets the VM-exit instruction info. VMCS field.
778 *
779 * @param pVCpu The cross context virtual CPU structure.
780 * @param uExitInstrInfo The VM-exit instruction information.
781 */
782DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
783{
784 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
785}
786
787
788/**
789 * Sets the guest pending-debug exceptions field.
790 *
791 * @param pVCpu The cross context virtual CPU structure.
792 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
793 */
794DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
795{
796 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
797 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
798}
799
800
801/**
802 * Implements VMSucceed for VMX instruction success.
803 *
804 * @param pVCpu The cross context virtual CPU structure.
805 */
806DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
807{
808 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
809}
810
811
812/**
813 * Implements VMFailInvalid for VMX instruction failure.
814 *
815 * @param pVCpu The cross context virtual CPU structure.
816 */
817DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
818{
819 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
820}
821
822
823/**
824 * Implements VMFail for VMX instruction failure.
825 *
826 * @param pVCpu The cross context virtual CPU structure.
827 * @param enmInsErr The VM instruction error.
828 */
829DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
830{
831 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
832}
833
834
835/**
836 * Checks if the given auto-load/store MSR area count is valid for the
837 * implementation.
838 *
839 * @returns @c true if it's within the valid limit, @c false otherwise.
840 * @param pVCpu The cross context virtual CPU structure.
841 * @param uMsrCount The MSR area count to check.
842 */
843DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
844{
845 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
846 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
847 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
848 if (uMsrCount <= cMaxSupportedMsrs)
849 return true;
850 return false;
851}
852
853
854/**
855 * Flushes the current VMCS contents back to guest memory.
856 *
857 * @returns VBox status code.
858 * @param pVCpu The cross context virtual CPU structure.
859 */
860DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
861{
862 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
863 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
864 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
865 return rc;
866}
867
868
869/**
870 * Populates the current VMCS contents from guest memory.
871 *
872 * @returns VBox status code.
873 * @param pVCpu The cross context virtual CPU structure.
874 */
875DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
876{
877 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
879 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
880 return rc;
881}
882
883
884/**
885 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
886 *
887 * @param pVCpu The cross context virtual CPU structure.
888 */
889DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
890{
891 iemVmxVmSucceed(pVCpu);
892 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
893}
894
895
896/**
897 * Gets the instruction diagnostic for segment base checks during VM-entry of a
898 * nested-guest.
899 *
900 * @param iSegReg The segment index (X86_SREG_XXX).
901 */
902IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
903{
904 switch (iSegReg)
905 {
906 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
907 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
908 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
909 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
910 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
911 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
912 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
913 }
914}
915
916
917/**
918 * Gets the instruction diagnostic for segment base checks during VM-entry of a
919 * nested-guest that is in Virtual-8086 mode.
920 *
921 * @param iSegReg The segment index (X86_SREG_XXX).
922 */
923IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
924{
925 switch (iSegReg)
926 {
927 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
928 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
929 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
930 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
931 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
932 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
933 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
934 }
935}
936
937
938/**
939 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
940 * nested-guest that is in Virtual-8086 mode.
941 *
942 * @param iSegReg The segment index (X86_SREG_XXX).
943 */
944IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
945{
946 switch (iSegReg)
947 {
948 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
949 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
950 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
951 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
952 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
953 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
954 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
955 }
956}
957
958
959/**
960 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
961 * nested-guest that is in Virtual-8086 mode.
962 *
963 * @param iSegReg The segment index (X86_SREG_XXX).
964 */
965IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
966{
967 switch (iSegReg)
968 {
969 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
970 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
971 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
972 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
973 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
974 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
975 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
976 }
977}
978
979
980/**
981 * Gets the instruction diagnostic for segment attributes reserved bits failure
982 * during VM-entry of a nested-guest.
983 *
984 * @param iSegReg The segment index (X86_SREG_XXX).
985 */
986IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
987{
988 switch (iSegReg)
989 {
990 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
991 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
992 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
993 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
994 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
995 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
996 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
997 }
998}
999
1000
1001/**
1002 * Gets the instruction diagnostic for segment attributes descriptor-type
1003 * (code/segment or system) failure during VM-entry of a nested-guest.
1004 *
1005 * @param iSegReg The segment index (X86_SREG_XXX).
1006 */
1007IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1008{
1009 switch (iSegReg)
1010 {
1011 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1012 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1013 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1014 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1015 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1016 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1017 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1018 }
1019}
1020
1021
1022/**
1023 * Gets the instruction diagnostic for segment attributes descriptor-type
1024 * (code/segment or system) failure during VM-entry of a nested-guest.
1025 *
1026 * @param iSegReg The segment index (X86_SREG_XXX).
1027 */
1028IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1029{
1030 switch (iSegReg)
1031 {
1032 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1033 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1034 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1035 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1036 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1037 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1038 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1039 }
1040}
1041
1042
1043/**
1044 * Gets the instruction diagnostic for segment attribute granularity failure during
1045 * VM-entry of a nested-guest.
1046 *
1047 * @param iSegReg The segment index (X86_SREG_XXX).
1048 */
1049IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1050{
1051 switch (iSegReg)
1052 {
1053 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1054 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1055 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1056 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1057 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1058 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1059 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1060 }
1061}
1062
1063/**
1064 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1065 * VM-entry of a nested-guest.
1066 *
1067 * @param iSegReg The segment index (X86_SREG_XXX).
1068 */
1069IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1070{
1071 switch (iSegReg)
1072 {
1073 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1074 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1075 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1076 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1077 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1078 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1079 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1080 }
1081}
1082
1083
1084/**
1085 * Gets the instruction diagnostic for segment attribute type accessed failure
1086 * during VM-entry of a nested-guest.
1087 *
1088 * @param iSegReg The segment index (X86_SREG_XXX).
1089 */
1090IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1091{
1092 switch (iSegReg)
1093 {
1094 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1095 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1096 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1097 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1098 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1099 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1100 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1101 }
1102}
1103
1104
1105/**
1106 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1107 * failure during VM-entry of a nested-guest.
1108 *
1109 * @param iSegReg The PDPTE entry index.
1110 */
1111IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1112{
1113 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1114 switch (iPdpte)
1115 {
1116 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1117 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1118 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1119 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1120 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1121 }
1122}
1123
1124
1125/**
1126 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1127 * failure during VM-exit of a nested-guest.
1128 *
1129 * @param iSegReg The PDPTE entry index.
1130 */
1131IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1132{
1133 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1134 switch (iPdpte)
1135 {
1136 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1137 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1138 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1139 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1140 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1141 }
1142}
1143
1144
1145/**
1146 * Saves the guest control registers, debug registers and some MSRs are part of
1147 * VM-exit.
1148 *
1149 * @param pVCpu The cross context virtual CPU structure.
1150 */
1151IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1152{
1153 /*
1154 * Saves the guest control registers, debug registers and some MSRs.
1155 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1156 */
1157 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1158
1159 /* Save control registers. */
1160 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1161 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1162 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1163
1164 /* Save SYSENTER CS, ESP, EIP. */
1165 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1166 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1167 {
1168 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1169 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1170 }
1171 else
1172 {
1173 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1174 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1175 }
1176
1177 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1178 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1179 {
1180 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1181 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1182 }
1183
1184 /* Save PAT MSR. */
1185 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1186 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1187
1188 /* Save EFER MSR. */
1189 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1190 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1191
1192 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1193 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1194
1195 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1196}
1197
1198
1199/**
1200 * Saves the guest force-flags in preparation of entering the nested-guest.
1201 *
1202 * @param pVCpu The cross context virtual CPU structure.
1203 */
1204IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1205{
1206 /* We shouldn't be called multiple times during VM-entry. */
1207 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1208
1209 /* MTF should not be set outside VMX non-root mode. */
1210 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1211
1212 /*
1213 * Preserve the required force-flags.
1214 *
1215 * We cache and clear force-flags that would affect the execution of the
1216 * nested-guest. Cached flags are then restored while returning to the guest
1217 * if necessary.
1218 *
1219 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1220 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1221 * instruction. Interrupt inhibition for any nested-guest instruction
1222 * is supplied by the guest-interruptibility state VMCS field and will
1223 * be set up as part of loading the guest state.
1224 *
1225 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1226 * successful VM-entry (due to invalid guest-state) need to continue
1227 * blocking NMIs if it was in effect before VM-entry.
1228 *
1229 * - MTF need not be preserved as it's used only in VMX non-root mode and
1230 * is supplied through the VM-execution controls.
1231 *
1232 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1233 * we will be able to generate interrupts that may cause VM-exits for
1234 * the nested-guest.
1235 */
1236 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1237}
1238
1239
1240/**
1241 * Restores the guest force-flags in preparation of exiting the nested-guest.
1242 *
1243 * @param pVCpu The cross context virtual CPU structure.
1244 */
1245IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1246{
1247 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1248 {
1249 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1250 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1251 }
1252}
1253
1254
1255/**
1256 * Perform a VMX transition updated PGM, IEM and CPUM.
1257 *
1258 * @param pVCpu The cross context virtual CPU structure.
1259 */
1260IEM_STATIC int iemVmxWorldSwitch(PVMCPUCC pVCpu)
1261{
1262 /*
1263 * Inform PGM about paging mode changes.
1264 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1265 * see comment in iemMemPageTranslateAndCheckAccess().
1266 */
1267 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1268# ifdef IN_RING3
1269 Assert(rc != VINF_PGM_CHANGE_MODE);
1270# endif
1271 AssertRCReturn(rc, rc);
1272
1273 /* Inform CPUM (recompiler), can later be removed. */
1274 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1275
1276 /*
1277 * Flush the TLB with new CR3. This is required in case the PGM mode change
1278 * above doesn't actually change anything.
1279 */
1280 if (rc == VINF_SUCCESS)
1281 {
1282 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1283 AssertRCReturn(rc, rc);
1284 }
1285
1286 /* Re-initialize IEM cache/state after the drastic mode switch. */
1287 iemReInitExec(pVCpu);
1288 return rc;
1289}
1290
1291
1292/**
1293 * Calculates the current VMX-preemption timer value.
1294 *
1295 * @returns The current VMX-preemption timer value.
1296 * @param pVCpu The cross context virtual CPU structure.
1297 */
1298IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1299{
1300 /*
1301 * Assume the following:
1302 * PreemptTimerShift = 5
1303 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1304 * EntryTick = 50000 (TSC at time of VM-entry)
1305 *
1306 * CurTick Delta PreemptTimerVal
1307 * ----------------------------------
1308 * 60000 10000 2
1309 * 80000 30000 1
1310 * 90000 40000 0 -> VM-exit.
1311 *
1312 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1313 * The saved VMX-preemption timer value is calculated as follows:
1314 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1315 * E.g.:
1316 * Delta = 10000
1317 * Tmp = 10000 / (2 * 10000) = 0.5
1318 * NewPt = 2 - 0.5 = 2
1319 * Delta = 30000
1320 * Tmp = 30000 / (2 * 10000) = 1.5
1321 * NewPt = 2 - 1.5 = 1
1322 * Delta = 40000
1323 * Tmp = 40000 / 20000 = 2
1324 * NewPt = 2 - 2 = 0
1325 */
1326 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1327 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1328 if (uVmcsPreemptVal > 0)
1329 {
1330 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1331 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1332 uint64_t const uDelta = uCurTick - uEntryTick;
1333 uint32_t const uPreemptTimer = uVmcsPreemptVal
1334 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1335 return uPreemptTimer;
1336 }
1337 return 0;
1338}
1339
1340
1341/**
1342 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1343 *
1344 * @param pVCpu The cross context virtual CPU structure.
1345 */
1346IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1347{
1348 /*
1349 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1350 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1351 */
1352 /* CS, SS, ES, DS, FS, GS. */
1353 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1354 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1355 {
1356 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1357 if (!pSelReg->Attr.n.u1Unusable)
1358 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1359 else
1360 {
1361 /*
1362 * For unusable segments the attributes are undefined except for CS and SS.
1363 * For the rest we don't bother preserving anything but the unusable bit.
1364 */
1365 switch (iSegReg)
1366 {
1367 case X86_SREG_CS:
1368 pVmcs->GuestCs = pSelReg->Sel;
1369 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1370 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1371 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1372 | X86DESCATTR_UNUSABLE);
1373 break;
1374
1375 case X86_SREG_SS:
1376 pVmcs->GuestSs = pSelReg->Sel;
1377 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1378 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1379 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1380 break;
1381
1382 case X86_SREG_DS:
1383 pVmcs->GuestDs = pSelReg->Sel;
1384 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1385 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1386 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1387 break;
1388
1389 case X86_SREG_ES:
1390 pVmcs->GuestEs = pSelReg->Sel;
1391 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1392 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1393 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1394 break;
1395
1396 case X86_SREG_FS:
1397 pVmcs->GuestFs = pSelReg->Sel;
1398 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1399 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1400 break;
1401
1402 case X86_SREG_GS:
1403 pVmcs->GuestGs = pSelReg->Sel;
1404 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1405 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1406 break;
1407 }
1408 }
1409 }
1410
1411 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1412 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1413 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1414 | X86DESCATTR_UNUSABLE;
1415 /* LDTR. */
1416 {
1417 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1418 pVmcs->GuestLdtr = pSelReg->Sel;
1419 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1420 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1421 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1422 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1423 }
1424
1425 /* TR. */
1426 {
1427 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1428 pVmcs->GuestTr = pSelReg->Sel;
1429 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1430 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1431 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1432 }
1433
1434 /* GDTR. */
1435 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1436 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1437
1438 /* IDTR. */
1439 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1440 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1441}
1442
1443
1444/**
1445 * Saves guest non-register state as part of VM-exit.
1446 *
1447 * @param pVCpu The cross context virtual CPU structure.
1448 * @param uExitReason The VM-exit reason.
1449 */
1450IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1451{
1452 /*
1453 * Save guest non-register state.
1454 * See Intel spec. 27.3.4 "Saving Non-Register State".
1455 */
1456 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1457
1458 /*
1459 * Activity state.
1460 * Most VM-exits will occur in the active state. However, if the first instruction
1461 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1462 * the VM-exit will be from the HLT activity state.
1463 *
1464 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1465 */
1466 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1467 * not? */
1468 EMSTATE const enmActivityState = EMGetState(pVCpu);
1469 switch (enmActivityState)
1470 {
1471 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1472 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1473 }
1474
1475 /*
1476 * Interruptibility-state.
1477 */
1478 /* NMI. */
1479 pVmcs->u32GuestIntrState = 0;
1480 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1481 {
1482 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1483 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1484 }
1485 else
1486 {
1487 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1488 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1489 }
1490
1491 /* Blocking-by-STI. */
1492 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1493 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1494 {
1495 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1496 * currently. */
1497 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1498 }
1499 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1500
1501 /*
1502 * Pending debug exceptions.
1503 *
1504 * For VM-exits where it is not applicable, we can safely zero out the field.
1505 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1506 */
1507 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1508 && uExitReason != VMX_EXIT_SMI
1509 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1510 && !VMXIsVmexitTrapLike(uExitReason))
1511 {
1512 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1513 * block-by-MovSS is in effect. */
1514 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1515 }
1516
1517 /*
1518 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1519 *
1520 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1521 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1522 */
1523 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1524 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1525 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1526
1527 /* PDPTEs. */
1528 /* We don't support EPT yet. */
1529 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1530 pVmcs->u64GuestPdpte0.u = 0;
1531 pVmcs->u64GuestPdpte1.u = 0;
1532 pVmcs->u64GuestPdpte2.u = 0;
1533 pVmcs->u64GuestPdpte3.u = 0;
1534}
1535
1536
1537/**
1538 * Saves the guest-state as part of VM-exit.
1539 *
1540 * @returns VBox status code.
1541 * @param pVCpu The cross context virtual CPU structure.
1542 * @param uExitReason The VM-exit reason.
1543 */
1544IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1545{
1546 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1547 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1548
1549 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1550 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1551 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1552
1553 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1554}
1555
1556
1557/**
1558 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1559 *
1560 * @returns VBox status code.
1561 * @param pVCpu The cross context virtual CPU structure.
1562 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1563 */
1564IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1565{
1566 /*
1567 * Save guest MSRs.
1568 * See Intel spec. 27.4 "Saving MSRs".
1569 */
1570 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1571 const char * const pszFailure = "VMX-abort";
1572
1573 /*
1574 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1575 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1576 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1577 */
1578 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1579 if (!cMsrs)
1580 return VINF_SUCCESS;
1581
1582 /*
1583 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1584 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1585 * implementation causes a VMX-abort followed by a triple-fault.
1586 */
1587 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1588 if (fIsMsrCountValid)
1589 { /* likely */ }
1590 else
1591 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1592
1593 /*
1594 * Optimization if the nested hypervisor is using the same guest-physical page for both
1595 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1596 */
1597 PVMXAUTOMSR pMsrArea;
1598 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1599 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1600 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1601 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
1602 else
1603 {
1604 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea),
1605 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1606 if (RT_SUCCESS(rc))
1607 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea);
1608 else
1609 {
1610 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1611 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1612 }
1613 }
1614
1615 /*
1616 * Update VM-exit MSR store area.
1617 */
1618 PVMXAUTOMSR pMsr = pMsrArea;
1619 Assert(pMsr);
1620 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1621 {
1622 if ( !pMsr->u32Reserved
1623 && pMsr->u32Msr != MSR_IA32_SMBASE
1624 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1625 {
1626 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1627 if (rcStrict == VINF_SUCCESS)
1628 continue;
1629
1630 /*
1631 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1632 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1633 * recording the MSR index in the auxiliary info. field and indicated further by our
1634 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1635 * if possible, or come up with a better, generic solution.
1636 */
1637 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1638 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1639 ? kVmxVDiag_Vmexit_MsrStoreRing3
1640 : kVmxVDiag_Vmexit_MsrStore;
1641 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1642 }
1643 else
1644 {
1645 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1646 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1647 }
1648 }
1649
1650 /*
1651 * Commit the VM-exit MSR store are to guest memory.
1652 */
1653 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1654 if (RT_SUCCESS(rc))
1655 return VINF_SUCCESS;
1656
1657 NOREF(uExitReason);
1658 NOREF(pszFailure);
1659
1660 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1661 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1662}
1663
1664
1665/**
1666 * Performs a VMX abort (due to an fatal error during VM-exit).
1667 *
1668 * @returns Strict VBox status code.
1669 * @param pVCpu The cross context virtual CPU structure.
1670 * @param enmAbort The VMX abort reason.
1671 */
1672IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1673{
1674 /*
1675 * Perform the VMX abort.
1676 * See Intel spec. 27.7 "VMX Aborts".
1677 */
1678 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1679
1680 /* We don't support SMX yet. */
1681 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1682 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1683 {
1684 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1685 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1686 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1687 }
1688
1689 return VINF_EM_TRIPLE_FAULT;
1690}
1691
1692
1693/**
1694 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1695 *
1696 * @param pVCpu The cross context virtual CPU structure.
1697 */
1698IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1699{
1700 /*
1701 * Load host control registers, debug registers and MSRs.
1702 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1703 */
1704 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1705 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1706
1707 /* CR0. */
1708 {
1709 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1710 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1711 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1712 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1713 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1714 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1715 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1716
1717 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1718 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1719 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1720 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1721 }
1722
1723 /* CR4. */
1724 {
1725 /* CR4 fixed bits are not modified. */
1726 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1727 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1728 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1729 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1730 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1731 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1732 if (fHostInLongMode)
1733 uValidHostCr4 |= X86_CR4_PAE;
1734 else
1735 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1736
1737 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1738 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1739 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1740 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1741 }
1742
1743 /* CR3 (host value validated while checking host-state during VM-entry). */
1744 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1745
1746 /* DR7. */
1747 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1748
1749 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1750
1751 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1752 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1753 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1754 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1755
1756 /* FS, GS bases are loaded later while we load host segment registers. */
1757
1758 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1759 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1760 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1761 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1762 {
1763 if (fHostInLongMode)
1764 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1765 else
1766 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1767 }
1768
1769 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1770
1771 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1772 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1773 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1774
1775 /* We don't support IA32_BNDCFGS MSR yet. */
1776}
1777
1778
1779/**
1780 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1781 *
1782 * @param pVCpu The cross context virtual CPU structure.
1783 */
1784IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1785{
1786 /*
1787 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1788 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1789 *
1790 * Warning! Be careful to not touch fields that are reserved by VT-x,
1791 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1792 */
1793 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1794 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1795
1796 /* CS, SS, ES, DS, FS, GS. */
1797 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1798 {
1799 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1800 bool const fUnusable = RT_BOOL(HostSel == 0);
1801 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1802
1803 /* Selector. */
1804 pSelReg->Sel = HostSel;
1805 pSelReg->ValidSel = HostSel;
1806 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1807
1808 /* Limit. */
1809 pSelReg->u32Limit = 0xffffffff;
1810
1811 /* Base. */
1812 pSelReg->u64Base = 0;
1813
1814 /* Attributes. */
1815 if (iSegReg == X86_SREG_CS)
1816 {
1817 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1818 pSelReg->Attr.n.u1DescType = 1;
1819 pSelReg->Attr.n.u2Dpl = 0;
1820 pSelReg->Attr.n.u1Present = 1;
1821 pSelReg->Attr.n.u1Long = fHostInLongMode;
1822 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1823 pSelReg->Attr.n.u1Granularity = 1;
1824 Assert(!pSelReg->Attr.n.u1Unusable);
1825 Assert(!fUnusable);
1826 }
1827 else
1828 {
1829 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1830 pSelReg->Attr.n.u1DescType = 1;
1831 pSelReg->Attr.n.u2Dpl = 0;
1832 pSelReg->Attr.n.u1Present = 1;
1833 pSelReg->Attr.n.u1DefBig = 1;
1834 pSelReg->Attr.n.u1Granularity = 1;
1835 pSelReg->Attr.n.u1Unusable = fUnusable;
1836 }
1837 }
1838
1839 /* FS base. */
1840 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1841 || fHostInLongMode)
1842 {
1843 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1844 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1845 }
1846
1847 /* GS base. */
1848 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1849 || fHostInLongMode)
1850 {
1851 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1852 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1853 }
1854
1855 /* TR. */
1856 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1857 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1858 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1859 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1860 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1861 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1862 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1863 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1864 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1865 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1866 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1867 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1868 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1869
1870 /* LDTR (Warning! do not touch the base and limits here). */
1871 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1872 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1873 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1874 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1875
1876 /* GDTR. */
1877 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1878 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1879 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1880
1881 /* IDTR.*/
1882 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1883 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1884 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1885}
1886
1887
1888/**
1889 * Checks host PDPTes as part of VM-exit.
1890 *
1891 * @param pVCpu The cross context virtual CPU structure.
1892 * @param uExitReason The VM-exit reason (for logging purposes).
1893 */
1894IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPUCC pVCpu, uint32_t uExitReason)
1895{
1896 /*
1897 * Check host PDPTEs.
1898 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1899 */
1900 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1901 const char * const pszFailure = "VMX-abort";
1902 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1903
1904 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1905 && !fHostInLongMode)
1906 {
1907 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
1908 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
1909 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
1910 if (RT_SUCCESS(rc))
1911 {
1912 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
1913 {
1914 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
1915 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
1916 { /* likely */ }
1917 else
1918 {
1919 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
1920 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1921 }
1922 }
1923 }
1924 else
1925 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
1926 }
1927
1928 NOREF(pszFailure);
1929 NOREF(uExitReason);
1930 return VINF_SUCCESS;
1931}
1932
1933
1934/**
1935 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1936 *
1937 * @returns VBox status code.
1938 * @param pVCpu The cross context virtual CPU structure.
1939 * @param pszInstr The VMX instruction name (for logging purposes).
1940 */
1941IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1942{
1943 /*
1944 * Load host MSRs.
1945 * See Intel spec. 27.6 "Loading MSRs".
1946 */
1947 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1948 const char * const pszFailure = "VMX-abort";
1949
1950 /*
1951 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1952 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1953 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1954 */
1955 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
1956 if (!cMsrs)
1957 return VINF_SUCCESS;
1958
1959 /*
1960 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1961 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1962 * implementation causes a VMX-abort followed by a triple-fault.
1963 */
1964 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1965 if (fIsMsrCountValid)
1966 { /* likely */ }
1967 else
1968 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1969
1970 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1971 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea),
1972 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1973 if (RT_SUCCESS(rc))
1974 {
1975 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea);
1976 Assert(pMsr);
1977 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1978 {
1979 if ( !pMsr->u32Reserved
1980 && pMsr->u32Msr != MSR_K8_FS_BASE
1981 && pMsr->u32Msr != MSR_K8_GS_BASE
1982 && pMsr->u32Msr != MSR_K6_EFER
1983 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1984 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1985 {
1986 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1987 if (rcStrict == VINF_SUCCESS)
1988 continue;
1989
1990 /*
1991 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1992 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1993 * recording the MSR index in the auxiliary info. field and indicated further by our
1994 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1995 * if possible, or come up with a better, generic solution.
1996 */
1997 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1998 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1999 ? kVmxVDiag_Vmexit_MsrLoadRing3
2000 : kVmxVDiag_Vmexit_MsrLoad;
2001 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2002 }
2003 else
2004 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2005 }
2006 }
2007 else
2008 {
2009 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2010 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2011 }
2012
2013 NOREF(uExitReason);
2014 NOREF(pszFailure);
2015 return VINF_SUCCESS;
2016}
2017
2018
2019/**
2020 * Loads the host state as part of VM-exit.
2021 *
2022 * @returns Strict VBox status code.
2023 * @param pVCpu The cross context virtual CPU structure.
2024 * @param uExitReason The VM-exit reason (for logging purposes).
2025 */
2026IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
2027{
2028 /*
2029 * Load host state.
2030 * See Intel spec. 27.5 "Loading Host State".
2031 */
2032 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2033 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2034
2035 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2036 if ( CPUMIsGuestInLongMode(pVCpu)
2037 && !fHostInLongMode)
2038 {
2039 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2040 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2041 }
2042
2043 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2044 iemVmxVmexitLoadHostSegRegs(pVCpu);
2045
2046 /*
2047 * Load host RIP, RSP and RFLAGS.
2048 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2049 */
2050 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2051 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2052 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2053
2054 /* Clear address range monitoring. */
2055 EMMonitorWaitClear(pVCpu);
2056
2057 /* Perform the VMX transition (PGM updates). */
2058 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2059 if (rcStrict == VINF_SUCCESS)
2060 {
2061 /* Check host PDPTEs (only when we've fully switched page tables_. */
2062 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2063 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2064 if (RT_FAILURE(rc))
2065 {
2066 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2067 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2068 }
2069 }
2070 else if (RT_SUCCESS(rcStrict))
2071 {
2072 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2073 uExitReason));
2074 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2075 }
2076 else
2077 {
2078 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2079 return VBOXSTRICTRC_VAL(rcStrict);
2080 }
2081
2082 Assert(rcStrict == VINF_SUCCESS);
2083
2084 /* Load MSRs from the VM-exit auto-load MSR area. */
2085 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2086 if (RT_FAILURE(rc))
2087 {
2088 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2089 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2090 }
2091 return VINF_SUCCESS;
2092}
2093
2094
2095/**
2096 * Gets VM-exit instruction information along with any displacement for an
2097 * instruction VM-exit.
2098 *
2099 * @returns The VM-exit instruction information.
2100 * @param pVCpu The cross context virtual CPU structure.
2101 * @param uExitReason The VM-exit reason.
2102 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2103 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2104 * NULL.
2105 */
2106IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2107{
2108 RTGCPTR GCPtrDisp;
2109 VMXEXITINSTRINFO ExitInstrInfo;
2110 ExitInstrInfo.u = 0;
2111
2112 /*
2113 * Get and parse the ModR/M byte from our decoded opcodes.
2114 */
2115 uint8_t bRm;
2116 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2117 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2118 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2119 {
2120 /*
2121 * ModR/M indicates register addressing.
2122 *
2123 * The primary/secondary register operands are reported in the iReg1 or iReg2
2124 * fields depending on whether it is a read/write form.
2125 */
2126 uint8_t idxReg1;
2127 uint8_t idxReg2;
2128 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2129 {
2130 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2131 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2132 }
2133 else
2134 {
2135 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2136 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2137 }
2138 ExitInstrInfo.All.u2Scaling = 0;
2139 ExitInstrInfo.All.iReg1 = idxReg1;
2140 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2141 ExitInstrInfo.All.fIsRegOperand = 1;
2142 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2143 ExitInstrInfo.All.iSegReg = 0;
2144 ExitInstrInfo.All.iIdxReg = 0;
2145 ExitInstrInfo.All.fIdxRegInvalid = 1;
2146 ExitInstrInfo.All.iBaseReg = 0;
2147 ExitInstrInfo.All.fBaseRegInvalid = 1;
2148 ExitInstrInfo.All.iReg2 = idxReg2;
2149
2150 /* Displacement not applicable for register addressing. */
2151 GCPtrDisp = 0;
2152 }
2153 else
2154 {
2155 /*
2156 * ModR/M indicates memory addressing.
2157 */
2158 uint8_t uScale = 0;
2159 bool fBaseRegValid = false;
2160 bool fIdxRegValid = false;
2161 uint8_t iBaseReg = 0;
2162 uint8_t iIdxReg = 0;
2163 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2164 {
2165 /*
2166 * Parse the ModR/M, displacement for 16-bit addressing mode.
2167 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2168 */
2169 uint16_t u16Disp = 0;
2170 uint8_t const offDisp = offModRm + sizeof(bRm);
2171 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2172 {
2173 /* Displacement without any registers. */
2174 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2175 }
2176 else
2177 {
2178 /* Register (index and base). */
2179 switch (bRm & X86_MODRM_RM_MASK)
2180 {
2181 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2182 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2183 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2184 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2185 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2186 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2187 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2188 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2189 }
2190
2191 /* Register + displacement. */
2192 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2193 {
2194 case 0: break;
2195 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2196 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2197 default:
2198 {
2199 /* Register addressing, handled at the beginning. */
2200 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2201 break;
2202 }
2203 }
2204 }
2205
2206 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2207 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2208 }
2209 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2210 {
2211 /*
2212 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2213 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2214 */
2215 uint32_t u32Disp = 0;
2216 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2217 {
2218 /* Displacement without any registers. */
2219 uint8_t const offDisp = offModRm + sizeof(bRm);
2220 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2221 }
2222 else
2223 {
2224 /* Register (and perhaps scale, index and base). */
2225 uint8_t offDisp = offModRm + sizeof(bRm);
2226 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2227 if (iBaseReg == 4)
2228 {
2229 /* An SIB byte follows the ModR/M byte, parse it. */
2230 uint8_t bSib;
2231 uint8_t const offSib = offModRm + sizeof(bRm);
2232 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2233
2234 /* A displacement may follow SIB, update its offset. */
2235 offDisp += sizeof(bSib);
2236
2237 /* Get the scale. */
2238 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2239
2240 /* Get the index register. */
2241 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2242 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2243
2244 /* Get the base register. */
2245 iBaseReg = bSib & X86_SIB_BASE_MASK;
2246 fBaseRegValid = true;
2247 if (iBaseReg == 5)
2248 {
2249 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2250 {
2251 /* Mod is 0 implies a 32-bit displacement with no base. */
2252 fBaseRegValid = false;
2253 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2254 }
2255 else
2256 {
2257 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2258 iBaseReg = X86_GREG_xBP;
2259 }
2260 }
2261 }
2262
2263 /* Register + displacement. */
2264 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2265 {
2266 case 0: /* Handled above */ break;
2267 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2268 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2269 default:
2270 {
2271 /* Register addressing, handled at the beginning. */
2272 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2273 break;
2274 }
2275 }
2276 }
2277
2278 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2279 }
2280 else
2281 {
2282 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2283
2284 /*
2285 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2286 * See Intel instruction spec. 2.2 "IA-32e Mode".
2287 */
2288 uint64_t u64Disp = 0;
2289 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2290 if (fRipRelativeAddr)
2291 {
2292 /*
2293 * RIP-relative addressing mode.
2294 *
2295 * The displacement is 32-bit signed implying an offset range of +/-2G.
2296 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2297 */
2298 uint8_t const offDisp = offModRm + sizeof(bRm);
2299 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2300 }
2301 else
2302 {
2303 uint8_t offDisp = offModRm + sizeof(bRm);
2304
2305 /*
2306 * Register (and perhaps scale, index and base).
2307 *
2308 * REX.B extends the most-significant bit of the base register. However, REX.B
2309 * is ignored while determining whether an SIB follows the opcode. Hence, we
2310 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2311 *
2312 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2313 */
2314 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2315 if (iBaseReg == 4)
2316 {
2317 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2318 uint8_t bSib;
2319 uint8_t const offSib = offModRm + sizeof(bRm);
2320 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2321
2322 /* Displacement may follow SIB, update its offset. */
2323 offDisp += sizeof(bSib);
2324
2325 /* Get the scale. */
2326 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2327
2328 /* Get the index. */
2329 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2330 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2331
2332 /* Get the base. */
2333 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2334 fBaseRegValid = true;
2335 if (iBaseReg == 5)
2336 {
2337 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2338 {
2339 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2340 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2341 }
2342 else
2343 {
2344 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2345 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2346 }
2347 }
2348 }
2349 iBaseReg |= pVCpu->iem.s.uRexB;
2350
2351 /* Register + displacement. */
2352 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2353 {
2354 case 0: /* Handled above */ break;
2355 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2356 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2357 default:
2358 {
2359 /* Register addressing, handled at the beginning. */
2360 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2361 break;
2362 }
2363 }
2364 }
2365
2366 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2367 }
2368
2369 /*
2370 * The primary or secondary register operand is reported in iReg2 depending
2371 * on whether the primary operand is in read/write form.
2372 */
2373 uint8_t idxReg2;
2374 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2375 {
2376 idxReg2 = bRm & X86_MODRM_RM_MASK;
2377 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2378 idxReg2 |= pVCpu->iem.s.uRexB;
2379 }
2380 else
2381 {
2382 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2383 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2384 idxReg2 |= pVCpu->iem.s.uRexReg;
2385 }
2386 ExitInstrInfo.All.u2Scaling = uScale;
2387 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2388 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2389 ExitInstrInfo.All.fIsRegOperand = 0;
2390 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2391 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2392 ExitInstrInfo.All.iIdxReg = iIdxReg;
2393 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2394 ExitInstrInfo.All.iBaseReg = iBaseReg;
2395 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2396 ExitInstrInfo.All.iReg2 = idxReg2;
2397 }
2398
2399 /*
2400 * Handle exceptions to the norm for certain instructions.
2401 * (e.g. some instructions convey an instruction identity in place of iReg2).
2402 */
2403 switch (uExitReason)
2404 {
2405 case VMX_EXIT_GDTR_IDTR_ACCESS:
2406 {
2407 Assert(VMXINSTRID_IS_VALID(uInstrId));
2408 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2409 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2410 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2411 break;
2412 }
2413
2414 case VMX_EXIT_LDTR_TR_ACCESS:
2415 {
2416 Assert(VMXINSTRID_IS_VALID(uInstrId));
2417 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2418 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2419 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2420 break;
2421 }
2422
2423 case VMX_EXIT_RDRAND:
2424 case VMX_EXIT_RDSEED:
2425 {
2426 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2427 break;
2428 }
2429 }
2430
2431 /* Update displacement and return the constructed VM-exit instruction information field. */
2432 if (pGCPtrDisp)
2433 *pGCPtrDisp = GCPtrDisp;
2434
2435 return ExitInstrInfo.u;
2436}
2437
2438
2439/**
2440 * VMX VM-exit handler.
2441 *
2442 * @returns Strict VBox status code.
2443 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2444 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2445 * triple-fault.
2446 *
2447 * @param pVCpu The cross context virtual CPU structure.
2448 * @param uExitReason The VM-exit reason.
2449 * @param u64ExitQual The Exit qualification.
2450 */
2451IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2452{
2453# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2454 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2455 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2456 return VERR_IEM_IPE_7;
2457# else
2458 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2459
2460 /*
2461 * Import all the guest-CPU state.
2462 *
2463 * HM on returning to guest execution would have to reset up a whole lot of state
2464 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2465 * the state and flag reloading the entire state on re-entry. So import the entire
2466 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2467 */
2468 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2469
2470 /*
2471 * Ensure VM-entry interruption information valid bit is cleared.
2472 *
2473 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2474 * by invalid-guest state or machine-check exceptions) also clear this bit.
2475 *
2476 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2477 */
2478 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2479 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2480
2481 /*
2482 * Update the VM-exit reason and Exit qualification.
2483 * Other VMCS read-only data fields are expected to be updated by the caller already.
2484 */
2485 pVmcs->u32RoExitReason = uExitReason;
2486 pVmcs->u64RoExitQual.u = u64ExitQual;
2487
2488 Log3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2489 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2490 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2491
2492 /*
2493 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2494 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2495 */
2496 {
2497 uint8_t uVector;
2498 uint32_t fFlags;
2499 uint32_t uErrCode;
2500 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2501 if (fInEventDelivery)
2502 {
2503 /*
2504 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2505 * caused by a triple-fault or the original event results in a double-fault that
2506 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2507 * original event information into the IDT-vectoring information fields.
2508 *
2509 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2510 */
2511 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2512 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2513 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2514 {
2515 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2516 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2517 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2518 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2519 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2520 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2521 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2522 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2523 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2524 pVCpu->cpum.GstCtx.cr2));
2525 }
2526 }
2527 }
2528
2529 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2530 Assert(pVmcs->u64RoIoRcx.u == 0);
2531 Assert(pVmcs->u64RoIoRsi.u == 0);
2532 Assert(pVmcs->u64RoIoRdi.u == 0);
2533 Assert(pVmcs->u64RoIoRip.u == 0);
2534
2535 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2536 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2537 {
2538 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2539 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2540 }
2541
2542 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2543 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2544
2545 /*
2546 * Save the guest state back into the VMCS.
2547 * We only need to save the state when the VM-entry was successful.
2548 */
2549 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2550 if (!fVmentryFailed)
2551 {
2552 /*
2553 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2554 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2555 *
2556 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2557 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2558 * as guest-CPU state would not been modified. Hence for now, we do this only when
2559 * the VM-entry succeeded.
2560 */
2561 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2562 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2563 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2564 {
2565 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2566 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2567 else
2568 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2569 }
2570
2571 /*
2572 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2573 * occurs in enclave mode/SMM which we don't support yet.
2574 *
2575 * If we ever add support for it, we can pass just the lower bits to the functions
2576 * below, till then an assert should suffice.
2577 */
2578 Assert(!RT_HI_U16(uExitReason));
2579
2580 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2581 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2582 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2583 if (RT_SUCCESS(rc))
2584 { /* likely */ }
2585 else
2586 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2587
2588 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2589 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2590 }
2591 else
2592 {
2593 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2594 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2595 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2596 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2597 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2598 }
2599
2600 /*
2601 * Stop any running VMX-preemption timer if necessary.
2602 */
2603 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2604 CPUMStopGuestVmxPremptTimer(pVCpu);
2605
2606 /*
2607 * Clear any pending VMX nested-guest force-flags.
2608 * These force-flags have no effect on (outer) guest execution and will
2609 * be re-evaluated and setup on the next nested-guest VM-entry.
2610 */
2611 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2612
2613 /* Restore the host (outer guest) state. */
2614 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2615 if (RT_SUCCESS(rcStrict))
2616 {
2617 Assert(rcStrict == VINF_SUCCESS);
2618 rcStrict = VINF_VMX_VMEXIT;
2619 }
2620 else
2621 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2622
2623 /* We're no longer in nested-guest execution mode. */
2624 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2625
2626 /* Notify HM that the current VMCS fields have been modified. */
2627 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2628
2629 /* Notify HM that we've completed the VM-exit. */
2630 HMNotifyVmxNstGstVmexit(pVCpu);
2631
2632# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2633 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2634 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2635 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2636 if (rcSched != VINF_SUCCESS)
2637 iemSetPassUpStatus(pVCpu, rcSched);
2638# endif
2639 return rcStrict;
2640# endif
2641}
2642
2643
2644/**
2645 * VMX VM-exit handler for VM-exits due to instruction execution.
2646 *
2647 * This is intended for instructions where the caller provides all the relevant
2648 * VM-exit information.
2649 *
2650 * @returns Strict VBox status code.
2651 * @param pVCpu The cross context virtual CPU structure.
2652 * @param pExitInfo Pointer to the VM-exit information.
2653 */
2654IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2655{
2656 /*
2657 * For instructions where any of the following fields are not applicable:
2658 * - Exit qualification must be cleared.
2659 * - VM-exit instruction info. is undefined.
2660 * - Guest-linear address is undefined.
2661 * - Guest-physical address is undefined.
2662 *
2663 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2664 * instruction execution. For VM-exits that are not due to instruction execution this
2665 * field is undefined.
2666 *
2667 * In our implementation in IEM, all undefined fields are generally cleared. However,
2668 * if the caller supplies information (from say the physical CPU directly) it is
2669 * then possible that the undefined fields are not cleared.
2670 *
2671 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2672 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2673 */
2674 Assert(pExitInfo);
2675 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2676 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2677 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2678
2679 /* Update all the relevant fields from the VM-exit instruction information struct. */
2680 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2681 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2682 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2683 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2684
2685 /* Perform the VM-exit. */
2686 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2687}
2688
2689
2690/**
2691 * VMX VM-exit handler for VM-exits due to instruction execution.
2692 *
2693 * This is intended for instructions that only provide the VM-exit instruction
2694 * length.
2695 *
2696 * @param pVCpu The cross context virtual CPU structure.
2697 * @param uExitReason The VM-exit reason.
2698 * @param cbInstr The instruction length in bytes.
2699 */
2700IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2701{
2702 VMXVEXITINFO ExitInfo;
2703 RT_ZERO(ExitInfo);
2704 ExitInfo.uReason = uExitReason;
2705 ExitInfo.cbInstr = cbInstr;
2706
2707#ifdef VBOX_STRICT
2708 /*
2709 * To prevent us from shooting ourselves in the foot.
2710 * The follow instructions should convey more than just the instruction length.
2711 */
2712 switch (uExitReason)
2713 {
2714 case VMX_EXIT_INVEPT:
2715 case VMX_EXIT_INVPCID:
2716 case VMX_EXIT_INVVPID:
2717 case VMX_EXIT_LDTR_TR_ACCESS:
2718 case VMX_EXIT_GDTR_IDTR_ACCESS:
2719 case VMX_EXIT_VMCLEAR:
2720 case VMX_EXIT_VMPTRLD:
2721 case VMX_EXIT_VMPTRST:
2722 case VMX_EXIT_VMREAD:
2723 case VMX_EXIT_VMWRITE:
2724 case VMX_EXIT_VMXON:
2725 case VMX_EXIT_XRSTORS:
2726 case VMX_EXIT_XSAVES:
2727 case VMX_EXIT_RDRAND:
2728 case VMX_EXIT_RDSEED:
2729 case VMX_EXIT_IO_INSTR:
2730 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2731 break;
2732 }
2733#endif
2734
2735 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2736}
2737
2738
2739/**
2740 * VMX VM-exit handler for VM-exits due to instruction execution.
2741 *
2742 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2743 * instruction information and Exit qualification fields.
2744 *
2745 * @param pVCpu The cross context virtual CPU structure.
2746 * @param uExitReason The VM-exit reason.
2747 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2748 * @param cbInstr The instruction length in bytes.
2749 *
2750 * @remarks Do not use this for INS/OUTS instruction.
2751 */
2752IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2753{
2754 VMXVEXITINFO ExitInfo;
2755 RT_ZERO(ExitInfo);
2756 ExitInfo.uReason = uExitReason;
2757 ExitInfo.cbInstr = cbInstr;
2758
2759 /*
2760 * Update the Exit qualification field with displacement bytes.
2761 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2762 */
2763 switch (uExitReason)
2764 {
2765 case VMX_EXIT_INVEPT:
2766 case VMX_EXIT_INVPCID:
2767 case VMX_EXIT_INVVPID:
2768 case VMX_EXIT_LDTR_TR_ACCESS:
2769 case VMX_EXIT_GDTR_IDTR_ACCESS:
2770 case VMX_EXIT_VMCLEAR:
2771 case VMX_EXIT_VMPTRLD:
2772 case VMX_EXIT_VMPTRST:
2773 case VMX_EXIT_VMREAD:
2774 case VMX_EXIT_VMWRITE:
2775 case VMX_EXIT_VMXON:
2776 case VMX_EXIT_XRSTORS:
2777 case VMX_EXIT_XSAVES:
2778 case VMX_EXIT_RDRAND:
2779 case VMX_EXIT_RDSEED:
2780 {
2781 /* Construct the VM-exit instruction information. */
2782 RTGCPTR GCPtrDisp;
2783 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2784
2785 /* Update the VM-exit instruction information. */
2786 ExitInfo.InstrInfo.u = uInstrInfo;
2787
2788 /* Update the Exit qualification. */
2789 ExitInfo.u64Qual = GCPtrDisp;
2790 break;
2791 }
2792
2793 default:
2794 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2795 break;
2796 }
2797
2798 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2799}
2800
2801
2802/**
2803 * VMX VM-exit handler for VM-exits due to INVLPG.
2804 *
2805 * @returns Strict VBox status code.
2806 * @param pVCpu The cross context virtual CPU structure.
2807 * @param GCPtrPage The guest-linear address of the page being invalidated.
2808 * @param cbInstr The instruction length in bytes.
2809 */
2810IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2811{
2812 VMXVEXITINFO ExitInfo;
2813 RT_ZERO(ExitInfo);
2814 ExitInfo.uReason = VMX_EXIT_INVLPG;
2815 ExitInfo.cbInstr = cbInstr;
2816 ExitInfo.u64Qual = GCPtrPage;
2817 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2818
2819 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2820}
2821
2822
2823/**
2824 * VMX VM-exit handler for VM-exits due to LMSW.
2825 *
2826 * @returns Strict VBox status code.
2827 * @param pVCpu The cross context virtual CPU structure.
2828 * @param uGuestCr0 The current guest CR0.
2829 * @param pu16NewMsw The machine-status word specified in LMSW's source
2830 * operand. This will be updated depending on the VMX
2831 * guest/host CR0 mask if LMSW is not intercepted.
2832 * @param GCPtrEffDst The guest-linear address of the source operand in case
2833 * of a memory operand. For register operand, pass
2834 * NIL_RTGCPTR.
2835 * @param cbInstr The instruction length in bytes.
2836 */
2837IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2838 uint8_t cbInstr)
2839{
2840 Assert(pu16NewMsw);
2841
2842 uint16_t const uNewMsw = *pu16NewMsw;
2843 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2844 {
2845 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2846
2847 VMXVEXITINFO ExitInfo;
2848 RT_ZERO(ExitInfo);
2849 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2850 ExitInfo.cbInstr = cbInstr;
2851
2852 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2853 if (fMemOperand)
2854 {
2855 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2856 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2857 }
2858
2859 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2860 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2861 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2862 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2863
2864 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2865 }
2866
2867 /*
2868 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2869 * CR0 guest/host mask must be left unmodified.
2870 *
2871 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2872 */
2873 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2874 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2875 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2876
2877 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2878}
2879
2880
2881/**
2882 * VMX VM-exit handler for VM-exits due to CLTS.
2883 *
2884 * @returns Strict VBox status code.
2885 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2886 * VM-exit but must not modify the guest CR0.TS bit.
2887 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2888 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2889 * CR0 fixed bits in VMX operation).
2890 * @param pVCpu The cross context virtual CPU structure.
2891 * @param cbInstr The instruction length in bytes.
2892 */
2893IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2894{
2895 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2896 uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2897
2898 /*
2899 * If CR0.TS is owned by the host:
2900 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2901 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2902 * CLTS instruction completes without clearing CR0.TS.
2903 *
2904 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2905 */
2906 if (fGstHostMask & X86_CR0_TS)
2907 {
2908 if (fReadShadow & X86_CR0_TS)
2909 {
2910 Log2(("clts: Guest intercept -> VM-exit\n"));
2911
2912 VMXVEXITINFO ExitInfo;
2913 RT_ZERO(ExitInfo);
2914 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2915 ExitInfo.cbInstr = cbInstr;
2916 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2917 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2918 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2919 }
2920
2921 return VINF_VMX_MODIFIES_BEHAVIOR;
2922 }
2923
2924 /*
2925 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2926 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2927 */
2928 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2929}
2930
2931
2932/**
2933 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2934 * (CR0/CR4 write).
2935 *
2936 * @returns Strict VBox status code.
2937 * @param pVCpu The cross context virtual CPU structure.
2938 * @param iCrReg The control register (either CR0 or CR4).
2939 * @param uGuestCrX The current guest CR0/CR4.
2940 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2941 * VM-exit is caused.
2942 * @param iGReg The general register from which the CR0/CR4 value is being
2943 * loaded.
2944 * @param cbInstr The instruction length in bytes.
2945 */
2946IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2947 uint8_t cbInstr)
2948{
2949 Assert(puNewCrX);
2950 Assert(iCrReg == 0 || iCrReg == 4);
2951 Assert(iGReg < X86_GREG_COUNT);
2952
2953 uint64_t const uNewCrX = *puNewCrX;
2954 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2955 {
2956 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2957
2958 VMXVEXITINFO ExitInfo;
2959 RT_ZERO(ExitInfo);
2960 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2961 ExitInfo.cbInstr = cbInstr;
2962 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2963 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2964 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2965 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2966 }
2967
2968 /*
2969 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2970 * must not be modified the instruction.
2971 *
2972 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2973 */
2974 uint64_t uGuestCrX;
2975 uint64_t fGstHostMask;
2976 if (iCrReg == 0)
2977 {
2978 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2979 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2980 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2981 }
2982 else
2983 {
2984 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2985 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2986 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2987 }
2988
2989 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2990 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2991}
2992
2993
2994/**
2995 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2996 *
2997 * @returns VBox strict status code.
2998 * @param pVCpu The cross context virtual CPU structure.
2999 * @param iGReg The general register to which the CR3 value is being stored.
3000 * @param cbInstr The instruction length in bytes.
3001 */
3002IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3003{
3004 Assert(iGReg < X86_GREG_COUNT);
3005 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3006
3007 /*
3008 * If the CR3-store exiting control is set, we must cause a VM-exit.
3009 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3010 */
3011 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3012 {
3013 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3014
3015 VMXVEXITINFO ExitInfo;
3016 RT_ZERO(ExitInfo);
3017 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3018 ExitInfo.cbInstr = cbInstr;
3019 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3020 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3021 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3022 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3023 }
3024
3025 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3026}
3027
3028
3029/**
3030 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3031 *
3032 * @returns VBox strict status code.
3033 * @param pVCpu The cross context virtual CPU structure.
3034 * @param uNewCr3 The new CR3 value.
3035 * @param iGReg The general register from which the CR3 value is being
3036 * loaded.
3037 * @param cbInstr The instruction length in bytes.
3038 */
3039IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3040{
3041 Assert(iGReg < X86_GREG_COUNT);
3042
3043 /*
3044 * If the CR3-load exiting control is set and the new CR3 value does not
3045 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3046 *
3047 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3048 */
3049 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3050 {
3051 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3052
3053 VMXVEXITINFO ExitInfo;
3054 RT_ZERO(ExitInfo);
3055 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3056 ExitInfo.cbInstr = cbInstr;
3057 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3058 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3059 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3060 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3061 }
3062
3063 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3064}
3065
3066
3067/**
3068 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3069 *
3070 * @returns VBox strict status code.
3071 * @param pVCpu The cross context virtual CPU structure.
3072 * @param iGReg The general register to which the CR8 value is being stored.
3073 * @param cbInstr The instruction length in bytes.
3074 */
3075IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3076{
3077 Assert(iGReg < X86_GREG_COUNT);
3078
3079 /*
3080 * If the CR8-store exiting control is set, we must cause a VM-exit.
3081 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3082 */
3083 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3084 {
3085 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3086
3087 VMXVEXITINFO ExitInfo;
3088 RT_ZERO(ExitInfo);
3089 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3090 ExitInfo.cbInstr = cbInstr;
3091 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3092 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3093 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3094 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3095 }
3096
3097 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3098}
3099
3100
3101/**
3102 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3103 *
3104 * @returns VBox strict status code.
3105 * @param pVCpu The cross context virtual CPU structure.
3106 * @param iGReg The general register from which the CR8 value is being
3107 * loaded.
3108 * @param cbInstr The instruction length in bytes.
3109 */
3110IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3111{
3112 Assert(iGReg < X86_GREG_COUNT);
3113
3114 /*
3115 * If the CR8-load exiting control is set, we must cause a VM-exit.
3116 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3117 */
3118 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3119 {
3120 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3121
3122 VMXVEXITINFO ExitInfo;
3123 RT_ZERO(ExitInfo);
3124 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3125 ExitInfo.cbInstr = cbInstr;
3126 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3127 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3128 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3129 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3130 }
3131
3132 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3133}
3134
3135
3136/**
3137 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3138 * GReg,DRx' (DRx read).
3139 *
3140 * @returns VBox strict status code.
3141 * @param pVCpu The cross context virtual CPU structure.
3142 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3143 * VMXINSTRID_MOV_FROM_DRX).
3144 * @param iDrReg The debug register being accessed.
3145 * @param iGReg The general register to/from which the DRx value is being
3146 * store/loaded.
3147 * @param cbInstr The instruction length in bytes.
3148 */
3149IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3150 uint8_t cbInstr)
3151{
3152 Assert(iDrReg <= 7);
3153 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3154 Assert(iGReg < X86_GREG_COUNT);
3155
3156 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3157 {
3158 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3159 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3160 VMXVEXITINFO ExitInfo;
3161 RT_ZERO(ExitInfo);
3162 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3163 ExitInfo.cbInstr = cbInstr;
3164 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3165 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3166 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3167 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3168 }
3169
3170 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3171}
3172
3173
3174/**
3175 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3176 *
3177 * @returns VBox strict status code.
3178 * @param pVCpu The cross context virtual CPU structure.
3179 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3180 * VMXINSTRID_IO_OUT).
3181 * @param u16Port The I/O port being accessed.
3182 * @param fImm Whether the I/O port was encoded using an immediate operand
3183 * or the implicit DX register.
3184 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3185 * @param cbInstr The instruction length in bytes.
3186 */
3187IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3188 uint8_t cbInstr)
3189{
3190 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3191 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3192
3193 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3194 if (fIntercept)
3195 {
3196 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3197 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3198 VMXVEXITINFO ExitInfo;
3199 RT_ZERO(ExitInfo);
3200 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3201 ExitInfo.cbInstr = cbInstr;
3202 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3203 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3204 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3205 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3206 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3207 }
3208
3209 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3210}
3211
3212
3213/**
3214 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3215 *
3216 * @returns VBox strict status code.
3217 * @param pVCpu The cross context virtual CPU structure.
3218 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3219 * VMXINSTRID_IO_OUTS).
3220 * @param u16Port The I/O port being accessed.
3221 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3222 * @param fRep Whether the instruction has a REP prefix or not.
3223 * @param ExitInstrInfo The VM-exit instruction info. field.
3224 * @param cbInstr The instruction length in bytes.
3225 */
3226IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3227 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3228{
3229 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3230 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3231 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3232 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3233 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3234
3235 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3236 if (fIntercept)
3237 {
3238 /*
3239 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3240 */
3241 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3242 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3243 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3244 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3245 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3246
3247 uint32_t uDirection;
3248 uint64_t uGuestLinearAddr;
3249 if (uInstrId == VMXINSTRID_IO_INS)
3250 {
3251 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3252 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3253 }
3254 else
3255 {
3256 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3257 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3258 }
3259
3260 /*
3261 * If the segment is unusable, the guest-linear address in undefined.
3262 * We shall clear it for consistency.
3263 *
3264 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3265 */
3266 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3267 uGuestLinearAddr = 0;
3268
3269 VMXVEXITINFO ExitInfo;
3270 RT_ZERO(ExitInfo);
3271 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3272 ExitInfo.cbInstr = cbInstr;
3273 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3274 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3275 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3276 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3277 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3278 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3279 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3280 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3281 ExitInfo.InstrInfo = ExitInstrInfo;
3282 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3283 }
3284
3285 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3286}
3287
3288
3289/**
3290 * VMX VM-exit handler for VM-exits due to MWAIT.
3291 *
3292 * @returns VBox strict status code.
3293 * @param pVCpu The cross context virtual CPU structure.
3294 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3295 * @param cbInstr The instruction length in bytes.
3296 */
3297IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3298{
3299 VMXVEXITINFO ExitInfo;
3300 RT_ZERO(ExitInfo);
3301 ExitInfo.uReason = VMX_EXIT_MWAIT;
3302 ExitInfo.cbInstr = cbInstr;
3303 ExitInfo.u64Qual = fMonitorHwArmed;
3304 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3305}
3306
3307
3308/**
3309 * VMX VM-exit handler for VM-exits due to PAUSE.
3310 *
3311 * @returns VBox strict status code.
3312 * @param pVCpu The cross context virtual CPU structure.
3313 * @param cbInstr The instruction length in bytes.
3314 */
3315IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3316{
3317 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3318
3319 /*
3320 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3321 * "PAUSE-loop exiting" control.
3322 *
3323 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3324 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3325 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3326 * a VM-exit.
3327 *
3328 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3329 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3330 */
3331 bool fIntercept = false;
3332 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3333 fIntercept = true;
3334 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3335 && pVCpu->iem.s.uCpl == 0)
3336 {
3337 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3338
3339 /*
3340 * A previous-PAUSE-tick value of 0 is used to identify the first time
3341 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3342 * consider this to be the first execution of PAUSE in a loop according
3343 * to the Intel.
3344 *
3345 * All subsequent records for the previous-PAUSE-tick we ensure that it
3346 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3347 */
3348 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3349 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3350 uint64_t const uTick = TMCpuTickGet(pVCpu);
3351 uint32_t const uPleGap = pVmcs->u32PleGap;
3352 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3353 if ( *puPrevPauseTick == 0
3354 || uTick - *puPrevPauseTick > uPleGap)
3355 *puFirstPauseLoopTick = uTick;
3356 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3357 fIntercept = true;
3358
3359 *puPrevPauseTick = uTick | 1;
3360 }
3361
3362 if (fIntercept)
3363 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3364
3365 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3366}
3367
3368
3369/**
3370 * VMX VM-exit handler for VM-exits due to task switches.
3371 *
3372 * @returns VBox strict status code.
3373 * @param pVCpu The cross context virtual CPU structure.
3374 * @param enmTaskSwitch The cause of the task switch.
3375 * @param SelNewTss The selector of the new TSS.
3376 * @param cbInstr The instruction length in bytes.
3377 */
3378IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3379{
3380 /*
3381 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3382 *
3383 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3384 * instruction or delivery of the exception generated by one of these instructions
3385 * lead to a task switch through a task gate in the IDT, we need to provide the
3386 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3387 * leaves the VM-exit instruction length field undefined.
3388 *
3389 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3390 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3391 */
3392 Assert(cbInstr <= 15);
3393
3394 uint8_t uType;
3395 switch (enmTaskSwitch)
3396 {
3397 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3398 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3399 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3400 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3401 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3402 }
3403
3404 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3405 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3406 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3407 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3408}
3409
3410
3411/**
3412 * VMX VM-exit handler for trap-like VM-exits.
3413 *
3414 * @returns VBox strict status code.
3415 * @param pVCpu The cross context virtual CPU structure.
3416 * @param pExitInfo Pointer to the VM-exit information.
3417 * @param pExitEventInfo Pointer to the VM-exit event information.
3418 */
3419IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3420{
3421 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3422 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3423 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3424}
3425
3426
3427/**
3428 * VMX VM-exit handler for VM-exits due to task switches.
3429 *
3430 * This is intended for task switches where the caller provides all the relevant
3431 * VM-exit information.
3432 *
3433 * @returns VBox strict status code.
3434 * @param pVCpu The cross context virtual CPU structure.
3435 * @param pExitInfo Pointer to the VM-exit information.
3436 * @param pExitEventInfo Pointer to the VM-exit event information.
3437 */
3438IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3439 PCVMXVEXITEVENTINFO pExitEventInfo)
3440{
3441 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3442 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3443 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3444 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3445 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3446}
3447
3448
3449/**
3450 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3451 *
3452 * @returns VBox strict status code.
3453 * @param pVCpu The cross context virtual CPU structure.
3454 */
3455IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3456{
3457 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3458 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3459
3460 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3461 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3462
3463 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3464 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3465 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3466
3467 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3468 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3469}
3470
3471
3472/**
3473 * VMX VM-exit handler for VM-exits due to external interrupts.
3474 *
3475 * @returns VBox strict status code.
3476 * @param pVCpu The cross context virtual CPU structure.
3477 * @param uVector The external interrupt vector (pass 0 if the interrupt
3478 * is still pending since we typically won't know the
3479 * vector).
3480 * @param fIntPending Whether the external interrupt is pending or
3481 * acknowledged in the interrupt controller.
3482 */
3483IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3484{
3485 Assert(!fIntPending || uVector == 0);
3486
3487 /* The VM-exit is subject to "External interrupt exiting" being set. */
3488 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3489 {
3490 if (fIntPending)
3491 {
3492 /*
3493 * If the interrupt is pending and we don't need to acknowledge the
3494 * interrupt on VM-exit, cause the VM-exit immediately.
3495 *
3496 * See Intel spec 25.2 "Other Causes Of VM Exits".
3497 */
3498 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3499 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3500
3501 /*
3502 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3503 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3504 * acknowledged that the interrupt has been consumed. Callers would have to call
3505 * us again after getting the vector (and ofc, with fIntPending with false).
3506 */
3507 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3508 }
3509
3510 /*
3511 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3512 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3513 * all set, we need to record the vector of the external interrupt in the
3514 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3515 *
3516 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3517 */
3518 uint32_t uExitIntInfo;
3519 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3520 {
3521 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3522 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3523 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3524 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3525 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3526 }
3527 else
3528 uExitIntInfo = 0;
3529 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3530
3531 /*
3532 * Cause the VM-exit whether or not the vector has been stored
3533 * in the VM-exit interruption-information field.
3534 */
3535 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3536 }
3537
3538 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3539}
3540
3541
3542/**
3543 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3544 * an event.
3545 *
3546 * @returns VBox strict status code.
3547 * @param pVCpu The cross context virtual CPU structure.
3548 */
3549IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3550{
3551 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3552 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3553 {
3554 /*
3555 * The NMI-unblocking due to IRET field need not be set for double faults.
3556 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3557 */
3558 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3559 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3560 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3561 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3562 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3563 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3564 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3565 }
3566
3567 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3568}
3569
3570
3571/**
3572 * VMX VM-exit handler for VM-exit due to delivery of an events.
3573 *
3574 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3575 * all the relevant VM-exit information.
3576 *
3577 * @returns VBox strict status code.
3578 * @param pVCpu The cross context virtual CPU structure.
3579 * @param pExitInfo Pointer to the VM-exit information.
3580 * @param pExitEventInfo Pointer to the VM-exit event information.
3581 */
3582IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3583{
3584 Assert(pExitInfo);
3585 Assert(pExitEventInfo);
3586 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3587 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3588
3589 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3590 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3591 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3592 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3593 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3594 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3595}
3596
3597
3598/**
3599 * VMX VM-exit handler for VM-exits due to delivery of an event.
3600 *
3601 * @returns VBox strict status code.
3602 * @param pVCpu The cross context virtual CPU structure.
3603 * @param uVector The interrupt / exception vector.
3604 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3605 * @param uErrCode The error code associated with the event.
3606 * @param uCr2 The CR2 value in case of a \#PF exception.
3607 * @param cbInstr The instruction length in bytes.
3608 */
3609IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3610 uint8_t cbInstr)
3611{
3612 /*
3613 * If the event is being injected as part of VM-entry, it is -not- subject to event
3614 * intercepts in the nested-guest. However, secondary exceptions that occur during
3615 * injection of any event -are- subject to event interception.
3616 *
3617 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3618 */
3619 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3620 {
3621 /*
3622 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3623 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3624 *
3625 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3626 */
3627 if ( uVector == X86_XCPT_NMI
3628 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3629 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3630 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3631 else
3632 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3633
3634 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3635 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3636 }
3637
3638 /*
3639 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3640 * If not, the caller will continue delivery of the external interrupt as it would
3641 * normally. The interrupt is no longer pending in the interrupt controller at this
3642 * point.
3643 */
3644 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3645 {
3646 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3647 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3648 }
3649
3650 /*
3651 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3652 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3653 * interrupts.
3654 */
3655 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3656 bool fIntercept;
3657 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3658 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3659 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3660 else
3661 {
3662 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3663 fIntercept = false;
3664 }
3665
3666 /*
3667 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3668 * relevant VM-exit information and cause the VM-exit.
3669 */
3670 if (fIntercept)
3671 {
3672 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3673
3674 /* Construct the rest of the event related information fields and cause the VM-exit. */
3675 uint64_t u64ExitQual;
3676 if (uVector == X86_XCPT_PF)
3677 {
3678 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3679 u64ExitQual = uCr2;
3680 }
3681 else if (uVector == X86_XCPT_DB)
3682 {
3683 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3684 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3685 }
3686 else
3687 u64ExitQual = 0;
3688
3689 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3690 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3691 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3692 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3693 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3694 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3695 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3696 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3697 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3698 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3699
3700 /*
3701 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3702 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3703 * length.
3704 */
3705 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3706 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3707 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3708 else
3709 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3710
3711 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3712 }
3713
3714 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3715}
3716
3717
3718/**
3719 * VMX VM-exit handler for APIC accesses.
3720 *
3721 * @param pVCpu The cross context virtual CPU structure.
3722 * @param offAccess The offset of the register being accessed.
3723 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3724 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3725 */
3726IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3727{
3728 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3729
3730 VMXAPICACCESS enmAccess;
3731 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3732 if (fInEventDelivery)
3733 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3734 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3735 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3736 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3737 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3738 else
3739 enmAccess = VMXAPICACCESS_LINEAR_READ;
3740
3741 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3742 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3743 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3744}
3745
3746
3747/**
3748 * VMX VM-exit handler for APIC accesses.
3749 *
3750 * This is intended for APIC accesses where the caller provides all the
3751 * relevant VM-exit information.
3752 *
3753 * @returns VBox strict status code.
3754 * @param pVCpu The cross context virtual CPU structure.
3755 * @param pExitInfo Pointer to the VM-exit information.
3756 * @param pExitEventInfo Pointer to the VM-exit event information.
3757 */
3758IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3759 PCVMXVEXITEVENTINFO pExitEventInfo)
3760{
3761 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3762 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3763 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3764 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3765 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3766 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3767 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3768 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3769 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3770}
3771
3772
3773/**
3774 * VMX VM-exit handler for APIC-write VM-exits.
3775 *
3776 * @param pVCpu The cross context virtual CPU structure.
3777 * @param offApic The write to the virtual-APIC page offset that caused this
3778 * VM-exit.
3779 */
3780IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3781{
3782 Assert(offApic < XAPIC_OFF_END + 4);
3783 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3784 offApic &= UINT16_C(0xfff);
3785 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3786}
3787
3788
3789/**
3790 * Sets virtual-APIC write emulation as pending.
3791 *
3792 * @param pVCpu The cross context virtual CPU structure.
3793 * @param offApic The offset in the virtual-APIC page that was written.
3794 */
3795DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3796{
3797 Assert(offApic < XAPIC_OFF_END + 4);
3798
3799 /*
3800 * Record the currently updated APIC offset, as we need this later for figuring
3801 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3802 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3803 */
3804 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3805
3806 /*
3807 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3808 * virtualization or APIC-write emulation).
3809 */
3810 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3811 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3812}
3813
3814
3815/**
3816 * Clears any pending virtual-APIC write emulation.
3817 *
3818 * @returns The virtual-APIC offset that was written before clearing it.
3819 * @param pVCpu The cross context virtual CPU structure.
3820 */
3821DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3822{
3823 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3824 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3825 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3826 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3827 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3828 return offVirtApicWrite;
3829}
3830
3831
3832/**
3833 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3834 *
3835 * @returns The register from the virtual-APIC page.
3836 * @param pVCpu The cross context virtual CPU structure.
3837 * @param offReg The offset of the register being read.
3838 */
3839IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3840{
3841 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3842
3843 uint32_t uReg = 0;
3844 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3845 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3846 AssertMsgStmt(RT_SUCCESS(rc),
3847 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3848 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3849 uReg = 0);
3850 return uReg;
3851}
3852
3853
3854/**
3855 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3856 *
3857 * @returns The register from the virtual-APIC page.
3858 * @param pVCpu The cross context virtual CPU structure.
3859 * @param offReg The offset of the register being read.
3860 */
3861IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3862{
3863 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3864
3865 uint64_t uReg = 0;
3866 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3867 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3868 AssertMsgStmt(RT_SUCCESS(rc),
3869 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3870 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3871 uReg = 0);
3872 return uReg;
3873}
3874
3875
3876/**
3877 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3878 *
3879 * @param pVCpu The cross context virtual CPU structure.
3880 * @param offReg The offset of the register being written.
3881 * @param uReg The register value to write.
3882 */
3883IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3884{
3885 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3886
3887 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3888 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3889 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3890 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3891}
3892
3893
3894/**
3895 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3896 *
3897 * @param pVCpu The cross context virtual CPU structure.
3898 * @param offReg The offset of the register being written.
3899 * @param uReg The register value to write.
3900 */
3901IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3902{
3903 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3904
3905 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3906 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3907 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3908 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3909}
3910
3911
3912/**
3913 * Sets the vector in a virtual-APIC 256-bit sparse register.
3914 *
3915 * @param pVCpu The cross context virtual CPU structure.
3916 * @param offReg The offset of the 256-bit spare register.
3917 * @param uVector The vector to set.
3918 *
3919 * @remarks This is based on our APIC device code.
3920 */
3921IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3922{
3923 /* Determine the vector offset within the chunk. */
3924 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3925
3926 /* Read the chunk at the offset. */
3927 uint32_t uReg;
3928 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3929 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3930 if (RT_SUCCESS(rc))
3931 {
3932 /* Modify the chunk. */
3933 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3934 uReg |= RT_BIT(idxVectorBit);
3935
3936 /* Write the chunk. */
3937 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3938 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3939 uVector, offReg, GCPhysVirtApic, rc));
3940 }
3941 else
3942 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3943 uVector, offReg, GCPhysVirtApic, rc));
3944}
3945
3946
3947/**
3948 * Clears the vector in a virtual-APIC 256-bit sparse register.
3949 *
3950 * @param pVCpu The cross context virtual CPU structure.
3951 * @param offReg The offset of the 256-bit spare register.
3952 * @param uVector The vector to clear.
3953 *
3954 * @remarks This is based on our APIC device code.
3955 */
3956IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3957{
3958 /* Determine the vector offset within the chunk. */
3959 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3960
3961 /* Read the chunk at the offset. */
3962 uint32_t uReg;
3963 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3964 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3965 if (RT_SUCCESS(rc))
3966 {
3967 /* Modify the chunk. */
3968 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3969 uReg &= ~RT_BIT(idxVectorBit);
3970
3971 /* Write the chunk. */
3972 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3973 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3974 uVector, offReg, GCPhysVirtApic, rc));
3975 }
3976 else
3977 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3978 uVector, offReg, GCPhysVirtApic, rc));
3979}
3980
3981
3982/**
3983 * Checks if a memory access to the APIC-access page must causes an APIC-access
3984 * VM-exit.
3985 *
3986 * @param pVCpu The cross context virtual CPU structure.
3987 * @param offAccess The offset of the register being accessed.
3988 * @param cbAccess The size of the access in bytes.
3989 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
3990 * IEM_ACCESS_TYPE_WRITE).
3991 *
3992 * @remarks This must not be used for MSR-based APIC-access page accesses!
3993 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
3994 */
3995IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
3996{
3997 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3998 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
3999
4000 /*
4001 * We must cause a VM-exit if any of the following are true:
4002 * - TPR shadowing isn't active.
4003 * - The access size exceeds 32-bits.
4004 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4005 *
4006 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4007 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4008 */
4009 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4010 || cbAccess > sizeof(uint32_t)
4011 || ((offAccess + cbAccess - 1) & 0xc)
4012 || offAccess >= XAPIC_OFF_END + 4)
4013 return true;
4014
4015 /*
4016 * If the access is part of an operation where we have already
4017 * virtualized a virtual-APIC write, we must cause a VM-exit.
4018 */
4019 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4020 return true;
4021
4022 /*
4023 * Check write accesses to the APIC-access page that cause VM-exits.
4024 */
4025 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4026 {
4027 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4028 {
4029 /*
4030 * With APIC-register virtualization, a write access to any of the
4031 * following registers are virtualized. Accessing any other register
4032 * causes a VM-exit.
4033 */
4034 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4035 switch (offAlignedAccess)
4036 {
4037 case XAPIC_OFF_ID:
4038 case XAPIC_OFF_TPR:
4039 case XAPIC_OFF_EOI:
4040 case XAPIC_OFF_LDR:
4041 case XAPIC_OFF_DFR:
4042 case XAPIC_OFF_SVR:
4043 case XAPIC_OFF_ESR:
4044 case XAPIC_OFF_ICR_LO:
4045 case XAPIC_OFF_ICR_HI:
4046 case XAPIC_OFF_LVT_TIMER:
4047 case XAPIC_OFF_LVT_THERMAL:
4048 case XAPIC_OFF_LVT_PERF:
4049 case XAPIC_OFF_LVT_LINT0:
4050 case XAPIC_OFF_LVT_LINT1:
4051 case XAPIC_OFF_LVT_ERROR:
4052 case XAPIC_OFF_TIMER_ICR:
4053 case XAPIC_OFF_TIMER_DCR:
4054 break;
4055 default:
4056 return true;
4057 }
4058 }
4059 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4060 {
4061 /*
4062 * With virtual-interrupt delivery, a write access to any of the
4063 * following registers are virtualized. Accessing any other register
4064 * causes a VM-exit.
4065 *
4066 * Note! The specification does not allow writing to offsets in-between
4067 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4068 */
4069 switch (offAccess)
4070 {
4071 case XAPIC_OFF_TPR:
4072 case XAPIC_OFF_EOI:
4073 case XAPIC_OFF_ICR_LO:
4074 break;
4075 default:
4076 return true;
4077 }
4078 }
4079 else
4080 {
4081 /*
4082 * Without APIC-register virtualization or virtual-interrupt delivery,
4083 * only TPR accesses are virtualized.
4084 */
4085 if (offAccess == XAPIC_OFF_TPR)
4086 { /* likely */ }
4087 else
4088 return true;
4089 }
4090 }
4091 else
4092 {
4093 /*
4094 * Check read accesses to the APIC-access page that cause VM-exits.
4095 */
4096 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4097 {
4098 /*
4099 * With APIC-register virtualization, a read access to any of the
4100 * following registers are virtualized. Accessing any other register
4101 * causes a VM-exit.
4102 */
4103 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4104 switch (offAlignedAccess)
4105 {
4106 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4107 case XAPIC_OFF_ID:
4108 case XAPIC_OFF_VERSION:
4109 case XAPIC_OFF_TPR:
4110 case XAPIC_OFF_EOI:
4111 case XAPIC_OFF_LDR:
4112 case XAPIC_OFF_DFR:
4113 case XAPIC_OFF_SVR:
4114 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4115 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4116 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4117 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4118 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4119 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4120 case XAPIC_OFF_ESR:
4121 case XAPIC_OFF_ICR_LO:
4122 case XAPIC_OFF_ICR_HI:
4123 case XAPIC_OFF_LVT_TIMER:
4124 case XAPIC_OFF_LVT_THERMAL:
4125 case XAPIC_OFF_LVT_PERF:
4126 case XAPIC_OFF_LVT_LINT0:
4127 case XAPIC_OFF_LVT_LINT1:
4128 case XAPIC_OFF_LVT_ERROR:
4129 case XAPIC_OFF_TIMER_ICR:
4130 case XAPIC_OFF_TIMER_DCR:
4131 break;
4132 default:
4133 return true;
4134 }
4135 }
4136 else
4137 {
4138 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4139 if (offAccess == XAPIC_OFF_TPR)
4140 { /* likely */ }
4141 else
4142 return true;
4143 }
4144 }
4145
4146 /* The APIC access is virtualized, does not cause a VM-exit. */
4147 return false;
4148}
4149
4150
4151/**
4152 * Virtualizes a memory-based APIC access where the address is not used to access
4153 * memory.
4154 *
4155 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4156 * page-faults but do not use the address to access memory.
4157 *
4158 * @param pVCpu The cross context virtual CPU structure.
4159 * @param pGCPhysAccess Pointer to the guest-physical address used.
4160 */
4161IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4162{
4163 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4164 Assert(pGCPhysAccess);
4165
4166 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4167 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4168 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4169
4170 if (GCPhysAccess == GCPhysApic)
4171 {
4172 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4173 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4174 uint16_t const cbAccess = 1;
4175 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4176 if (fIntercept)
4177 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4178
4179 *pGCPhysAccess = GCPhysApic | offAccess;
4180 return VINF_VMX_MODIFIES_BEHAVIOR;
4181 }
4182
4183 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4184}
4185
4186
4187/**
4188 * Virtualizes a memory-based APIC access.
4189 *
4190 * @returns VBox strict status code.
4191 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4192 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4193 *
4194 * @param pVCpu The cross context virtual CPU structure.
4195 * @param offAccess The offset of the register being accessed (within the
4196 * APIC-access page).
4197 * @param cbAccess The size of the access in bytes.
4198 * @param pvData Pointer to the data being written or where to store the data
4199 * being read.
4200 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4201 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4202 */
4203IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4204 uint32_t fAccess)
4205{
4206 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4207 Assert(pvData);
4208 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4209 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4210 || (fAccess & IEM_ACCESS_INSTRUCTION));
4211
4212 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4213 if (fIntercept)
4214 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4215
4216 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4217 {
4218 /*
4219 * A write access to the APIC-access page that is virtualized (rather than
4220 * causing a VM-exit) writes data to the virtual-APIC page.
4221 */
4222 uint32_t const u32Data = *(uint32_t *)pvData;
4223 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4224
4225 /*
4226 * Record the currently updated APIC offset, as we need this later for figuring
4227 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4228 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4229 *
4230 * After completion of the current operation, we need to perform TPR virtualization,
4231 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4232 *
4233 * The current operation may be a REP-prefixed string instruction, execution of any
4234 * other instruction, or delivery of an event through the IDT.
4235 *
4236 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4237 * performed now but later after completion of the current operation.
4238 *
4239 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4240 */
4241 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4242 }
4243 else
4244 {
4245 /*
4246 * A read access from the APIC-access page that is virtualized (rather than
4247 * causing a VM-exit) returns data from the virtual-APIC page.
4248 *
4249 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4250 */
4251 Assert(cbAccess <= 4);
4252 Assert(offAccess < XAPIC_OFF_END + 4);
4253 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4254
4255 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4256 u32Data &= s_auAccessSizeMasks[cbAccess];
4257 *(uint32_t *)pvData = u32Data;
4258 }
4259
4260 return VINF_VMX_MODIFIES_BEHAVIOR;
4261}
4262
4263
4264/**
4265 * Virtualizes an MSR-based APIC read access.
4266 *
4267 * @returns VBox strict status code.
4268 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4269 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4270 * handled by the x2APIC device.
4271 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4272 * not within the range of valid MSRs, caller must raise \#GP(0).
4273 * @param pVCpu The cross context virtual CPU structure.
4274 * @param idMsr The x2APIC MSR being read.
4275 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4276 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4277 */
4278IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4279{
4280 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4281 Assert(pu64Value);
4282
4283 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4284 {
4285 if ( idMsr >= MSR_IA32_X2APIC_START
4286 && idMsr <= MSR_IA32_X2APIC_END)
4287 {
4288 uint16_t const offReg = (idMsr & 0xff) << 4;
4289 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4290 *pu64Value = u64Value;
4291 return VINF_VMX_MODIFIES_BEHAVIOR;
4292 }
4293 return VERR_OUT_OF_RANGE;
4294 }
4295
4296 if (idMsr == MSR_IA32_X2APIC_TPR)
4297 {
4298 uint16_t const offReg = (idMsr & 0xff) << 4;
4299 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4300 *pu64Value = u64Value;
4301 return VINF_VMX_MODIFIES_BEHAVIOR;
4302 }
4303
4304 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4305}
4306
4307
4308/**
4309 * Virtualizes an MSR-based APIC write access.
4310 *
4311 * @returns VBox strict status code.
4312 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4313 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4314 * not within the range of valid MSRs, caller must raise \#GP(0).
4315 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4316 *
4317 * @param pVCpu The cross context virtual CPU structure.
4318 * @param idMsr The x2APIC MSR being written.
4319 * @param u64Value The value of the x2APIC MSR being written.
4320 */
4321IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4322{
4323 /*
4324 * Check if the access is to be virtualized.
4325 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4326 */
4327 if ( idMsr == MSR_IA32_X2APIC_TPR
4328 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4329 && ( idMsr == MSR_IA32_X2APIC_EOI
4330 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4331 {
4332 /* Validate the MSR write depending on the register. */
4333 switch (idMsr)
4334 {
4335 case MSR_IA32_X2APIC_TPR:
4336 case MSR_IA32_X2APIC_SELF_IPI:
4337 {
4338 if (u64Value & UINT64_C(0xffffffffffffff00))
4339 return VERR_OUT_OF_RANGE;
4340 break;
4341 }
4342 case MSR_IA32_X2APIC_EOI:
4343 {
4344 if (u64Value != 0)
4345 return VERR_OUT_OF_RANGE;
4346 break;
4347 }
4348 }
4349
4350 /* Write the MSR to the virtual-APIC page. */
4351 uint16_t const offReg = (idMsr & 0xff) << 4;
4352 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4353
4354 /*
4355 * Record the currently updated APIC offset, as we need this later for figuring
4356 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4357 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4358 */
4359 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4360
4361 return VINF_VMX_MODIFIES_BEHAVIOR;
4362 }
4363
4364 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4365}
4366
4367
4368/**
4369 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4370 *
4371 * @returns VBox status code.
4372 * @retval VINF_SUCCESS when the highest set bit is found.
4373 * @retval VERR_NOT_FOUND when no bit is set.
4374 *
4375 * @param pVCpu The cross context virtual CPU structure.
4376 * @param offReg The offset of the APIC 256-bit sparse register.
4377 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4378 * set in the register. Only valid when VINF_SUCCESS is
4379 * returned.
4380 *
4381 * @remarks The format of the 256-bit sparse register here mirrors that found in
4382 * real APIC hardware.
4383 */
4384static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4385{
4386 Assert(offReg < XAPIC_OFF_END + 4);
4387 Assert(pidxHighestBit);
4388
4389 /*
4390 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4391 * However, in each fragment only the first 4 bytes are used.
4392 */
4393 uint8_t const cFrags = 8;
4394 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4395 {
4396 uint16_t const offFrag = iFrag * 16;
4397 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4398 if (!u32Frag)
4399 continue;
4400
4401 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4402 Assert(idxHighestBit > 0);
4403 --idxHighestBit;
4404 Assert(idxHighestBit <= UINT8_MAX);
4405 *pidxHighestBit = idxHighestBit;
4406 return VINF_SUCCESS;
4407 }
4408 return VERR_NOT_FOUND;
4409}
4410
4411
4412/**
4413 * Evaluates pending virtual interrupts.
4414 *
4415 * @param pVCpu The cross context virtual CPU structure.
4416 */
4417IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4418{
4419 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4420
4421 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4422 {
4423 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4424 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4425
4426 if ((uRvi >> 4) > (uPpr >> 4))
4427 {
4428 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4429 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4430 }
4431 else
4432 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4433 }
4434}
4435
4436
4437/**
4438 * Performs PPR virtualization.
4439 *
4440 * @returns VBox strict status code.
4441 * @param pVCpu The cross context virtual CPU structure.
4442 */
4443IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4444{
4445 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4446 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4447
4448 /*
4449 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4450 * or EOI-virtualization.
4451 *
4452 * See Intel spec. 29.1.3 "PPR Virtualization".
4453 */
4454 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4455 uint32_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4456
4457 uint32_t uPpr;
4458 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4459 uPpr = uTpr & 0xff;
4460 else
4461 uPpr = uSvi & 0xf0;
4462
4463 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4464 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4465}
4466
4467
4468/**
4469 * Performs VMX TPR virtualization.
4470 *
4471 * @returns VBox strict status code.
4472 * @param pVCpu The cross context virtual CPU structure.
4473 */
4474IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4475{
4476 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4477
4478 /*
4479 * We should have already performed the virtual-APIC write to the TPR offset
4480 * in the virtual-APIC page. We now perform TPR virtualization.
4481 *
4482 * See Intel spec. 29.1.2 "TPR Virtualization".
4483 */
4484 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4485 {
4486 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4487 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4488
4489 /*
4490 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4491 * See Intel spec. 29.1.2 "TPR Virtualization".
4492 */
4493 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4494 {
4495 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4496 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4497 }
4498 }
4499 else
4500 {
4501 iemVmxPprVirtualization(pVCpu);
4502 iemVmxEvalPendingVirtIntrs(pVCpu);
4503 }
4504
4505 return VINF_SUCCESS;
4506}
4507
4508
4509/**
4510 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4511 * not.
4512 *
4513 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4514 * @param pVCpu The cross context virtual CPU structure.
4515 * @param uVector The interrupt that was acknowledged using an EOI.
4516 */
4517IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4518{
4519 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4520 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4521
4522 if (uVector < 64)
4523 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4524 if (uVector < 128)
4525 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4526 if (uVector < 192)
4527 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4528 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4529}
4530
4531
4532/**
4533 * Performs EOI virtualization.
4534 *
4535 * @returns VBox strict status code.
4536 * @param pVCpu The cross context virtual CPU structure.
4537 */
4538IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4539{
4540 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4541 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4542
4543 /*
4544 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4545 * and get the next guest-interrupt that's in-service (if any).
4546 *
4547 * See Intel spec. 29.1.4 "EOI Virtualization".
4548 */
4549 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4550 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4551 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4552
4553 uint8_t uVector = uSvi;
4554 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4555
4556 uVector = 0;
4557 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4558
4559 if (uVector)
4560 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4561 else
4562 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4563
4564 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4565 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4566
4567 iemVmxPprVirtualization(pVCpu);
4568 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4569 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4570 iemVmxEvalPendingVirtIntrs(pVCpu);
4571 return VINF_SUCCESS;
4572}
4573
4574
4575/**
4576 * Performs self-IPI virtualization.
4577 *
4578 * @returns VBox strict status code.
4579 * @param pVCpu The cross context virtual CPU structure.
4580 */
4581IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4582{
4583 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4584 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4585
4586 /*
4587 * We should have already performed the virtual-APIC write to the self-IPI offset
4588 * in the virtual-APIC page. We now perform self-IPI virtualization.
4589 *
4590 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4591 */
4592 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4593 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4594 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4595 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4596 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4597 if (uVector > uRvi)
4598 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4599 iemVmxEvalPendingVirtIntrs(pVCpu);
4600 return VINF_SUCCESS;
4601}
4602
4603
4604/**
4605 * Performs VMX APIC-write emulation.
4606 *
4607 * @returns VBox strict status code.
4608 * @param pVCpu The cross context virtual CPU structure.
4609 */
4610IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4611{
4612 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4613
4614 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4615 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4616
4617 /*
4618 * Perform APIC-write emulation based on the virtual-APIC register written.
4619 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4620 */
4621 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4622 VBOXSTRICTRC rcStrict;
4623 switch (offApicWrite)
4624 {
4625 case XAPIC_OFF_TPR:
4626 {
4627 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4628 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4629 uTpr &= UINT32_C(0x000000ff);
4630 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4631 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4632 rcStrict = iemVmxTprVirtualization(pVCpu);
4633 break;
4634 }
4635
4636 case XAPIC_OFF_EOI:
4637 {
4638 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4639 {
4640 /* Clear VEOI and perform EOI virtualization. */
4641 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4642 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4643 rcStrict = iemVmxEoiVirtualization(pVCpu);
4644 }
4645 else
4646 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4647 break;
4648 }
4649
4650 case XAPIC_OFF_ICR_LO:
4651 {
4652 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4653 {
4654 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4655 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4656 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4657 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4658 if ( !(uIcrLo & fIcrLoMb0)
4659 && (uIcrLo & fIcrLoMb1))
4660 {
4661 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4662 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4663 }
4664 else
4665 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4666 }
4667 else
4668 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4669 break;
4670 }
4671
4672 case XAPIC_OFF_ICR_HI:
4673 {
4674 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4675 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4676 uIcrHi &= UINT32_C(0xff000000);
4677 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4678 rcStrict = VINF_SUCCESS;
4679 break;
4680 }
4681
4682 default:
4683 {
4684 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4685 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4686 break;
4687 }
4688 }
4689
4690 return rcStrict;
4691}
4692
4693
4694/**
4695 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4696 *
4697 * @param pVCpu The cross context virtual CPU structure.
4698 * @param pszInstr The VMX instruction name (for logging purposes).
4699 */
4700DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4701{
4702 /*
4703 * Guest Control Registers, Debug Registers, and MSRs.
4704 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4705 */
4706 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4707 const char * const pszFailure = "VM-exit";
4708 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4709
4710 /* CR0 reserved bits. */
4711 {
4712 /* CR0 MB1 bits. */
4713 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4714 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4715 if (fUnrestrictedGuest)
4716 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4717 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4718 { /* likely */ }
4719 else
4720 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4721
4722 /* CR0 MBZ bits. */
4723 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4724 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4725 { /* likely */ }
4726 else
4727 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4728
4729 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4730 if ( !fUnrestrictedGuest
4731 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4732 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4733 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4734 }
4735
4736 /* CR4 reserved bits. */
4737 {
4738 /* CR4 MB1 bits. */
4739 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4740 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4741 { /* likely */ }
4742 else
4743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4744
4745 /* CR4 MBZ bits. */
4746 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4747 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4748 { /* likely */ }
4749 else
4750 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4751 }
4752
4753 /* DEBUGCTL MSR. */
4754 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4755 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4756 { /* likely */ }
4757 else
4758 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4759
4760 /* 64-bit CPU checks. */
4761 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4762 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4763 {
4764 if (fGstInLongMode)
4765 {
4766 /* PAE must be set. */
4767 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4768 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4769 { /* likely */ }
4770 else
4771 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4772 }
4773 else
4774 {
4775 /* PCIDE should not be set. */
4776 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4777 { /* likely */ }
4778 else
4779 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4780 }
4781
4782 /* CR3. */
4783 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4784 { /* likely */ }
4785 else
4786 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4787
4788 /* DR7. */
4789 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4790 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4791 { /* likely */ }
4792 else
4793 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4794
4795 /* SYSENTER ESP and SYSENTER EIP. */
4796 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4797 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4798 { /* likely */ }
4799 else
4800 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4801 }
4802
4803 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4804 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4805
4806 /* PAT MSR. */
4807 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4808 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4809 { /* likely */ }
4810 else
4811 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4812
4813 /* EFER MSR. */
4814 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4815 {
4816 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4817 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4818 { /* likely */ }
4819 else
4820 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4821
4822 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4823 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4824 if ( fGstLma == fGstInLongMode
4825 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4826 || fGstLma == fGstLme))
4827 { /* likely */ }
4828 else
4829 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4830 }
4831
4832 /* We don't support IA32_BNDCFGS MSR yet. */
4833 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4834
4835 NOREF(pszInstr);
4836 NOREF(pszFailure);
4837 return VINF_SUCCESS;
4838}
4839
4840
4841/**
4842 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4843 *
4844 * @param pVCpu The cross context virtual CPU structure.
4845 * @param pszInstr The VMX instruction name (for logging purposes).
4846 */
4847DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4848{
4849 /*
4850 * Segment registers.
4851 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4852 */
4853 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4854 const char * const pszFailure = "VM-exit";
4855 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4856 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4857 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4858
4859 /* Selectors. */
4860 if ( !fGstInV86Mode
4861 && !fUnrestrictedGuest
4862 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4863 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4864
4865 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4866 {
4867 CPUMSELREG SelReg;
4868 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4869 if (RT_LIKELY(rc == VINF_SUCCESS))
4870 { /* likely */ }
4871 else
4872 return rc;
4873
4874 /*
4875 * Virtual-8086 mode checks.
4876 */
4877 if (fGstInV86Mode)
4878 {
4879 /* Base address. */
4880 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4881 { /* likely */ }
4882 else
4883 {
4884 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4885 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4886 }
4887
4888 /* Limit. */
4889 if (SelReg.u32Limit == 0xffff)
4890 { /* likely */ }
4891 else
4892 {
4893 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4894 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4895 }
4896
4897 /* Attribute. */
4898 if (SelReg.Attr.u == 0xf3)
4899 { /* likely */ }
4900 else
4901 {
4902 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4903 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4904 }
4905
4906 /* We're done; move to checking the next segment. */
4907 continue;
4908 }
4909
4910 /* Checks done by 64-bit CPUs. */
4911 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4912 {
4913 /* Base address. */
4914 if ( iSegReg == X86_SREG_FS
4915 || iSegReg == X86_SREG_GS)
4916 {
4917 if (X86_IS_CANONICAL(SelReg.u64Base))
4918 { /* likely */ }
4919 else
4920 {
4921 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4922 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4923 }
4924 }
4925 else if (iSegReg == X86_SREG_CS)
4926 {
4927 if (!RT_HI_U32(SelReg.u64Base))
4928 { /* likely */ }
4929 else
4930 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
4931 }
4932 else
4933 {
4934 if ( SelReg.Attr.n.u1Unusable
4935 || !RT_HI_U32(SelReg.u64Base))
4936 { /* likely */ }
4937 else
4938 {
4939 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4940 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4941 }
4942 }
4943 }
4944
4945 /*
4946 * Checks outside Virtual-8086 mode.
4947 */
4948 uint8_t const uSegType = SelReg.Attr.n.u4Type;
4949 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
4950 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
4951 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
4952 uint8_t const fPresent = SelReg.Attr.n.u1Present;
4953 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
4954 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
4955 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
4956
4957 /* Code or usable segment. */
4958 if ( iSegReg == X86_SREG_CS
4959 || fUsable)
4960 {
4961 /* Reserved bits (bits 31:17 and bits 11:8). */
4962 if (!(SelReg.Attr.u & 0xfffe0f00))
4963 { /* likely */ }
4964 else
4965 {
4966 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
4967 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4968 }
4969
4970 /* Descriptor type. */
4971 if (fCodeDataSeg)
4972 { /* likely */ }
4973 else
4974 {
4975 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
4976 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4977 }
4978
4979 /* Present. */
4980 if (fPresent)
4981 { /* likely */ }
4982 else
4983 {
4984 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
4985 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4986 }
4987
4988 /* Granularity. */
4989 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
4990 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
4991 { /* likely */ }
4992 else
4993 {
4994 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
4995 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4996 }
4997 }
4998
4999 if (iSegReg == X86_SREG_CS)
5000 {
5001 /* Segment Type and DPL. */
5002 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5003 && fUnrestrictedGuest)
5004 {
5005 if (uDpl == 0)
5006 { /* likely */ }
5007 else
5008 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5009 }
5010 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5011 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5012 {
5013 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5014 if (uDpl == AttrSs.n.u2Dpl)
5015 { /* likely */ }
5016 else
5017 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5018 }
5019 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5020 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5021 {
5022 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5023 if (uDpl <= AttrSs.n.u2Dpl)
5024 { /* likely */ }
5025 else
5026 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5027 }
5028 else
5029 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5030
5031 /* Def/Big. */
5032 if ( fGstInLongMode
5033 && fSegLong)
5034 {
5035 if (uDefBig == 0)
5036 { /* likely */ }
5037 else
5038 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5039 }
5040 }
5041 else if (iSegReg == X86_SREG_SS)
5042 {
5043 /* Segment Type. */
5044 if ( !fUsable
5045 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5046 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5047 { /* likely */ }
5048 else
5049 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5050
5051 /* DPL. */
5052 if (!fUnrestrictedGuest)
5053 {
5054 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5055 { /* likely */ }
5056 else
5057 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5058 }
5059 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5060 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5061 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5062 {
5063 if (uDpl == 0)
5064 { /* likely */ }
5065 else
5066 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5067 }
5068 }
5069 else
5070 {
5071 /* DS, ES, FS, GS. */
5072 if (fUsable)
5073 {
5074 /* Segment type. */
5075 if (uSegType & X86_SEL_TYPE_ACCESSED)
5076 { /* likely */ }
5077 else
5078 {
5079 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5080 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5081 }
5082
5083 if ( !(uSegType & X86_SEL_TYPE_CODE)
5084 || (uSegType & X86_SEL_TYPE_READ))
5085 { /* likely */ }
5086 else
5087 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5088
5089 /* DPL. */
5090 if ( !fUnrestrictedGuest
5091 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5092 {
5093 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5094 { /* likely */ }
5095 else
5096 {
5097 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5098 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5099 }
5100 }
5101 }
5102 }
5103 }
5104
5105 /*
5106 * LDTR.
5107 */
5108 {
5109 CPUMSELREG Ldtr;
5110 Ldtr.Sel = pVmcs->GuestLdtr;
5111 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5112 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5113 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5114
5115 if (!Ldtr.Attr.n.u1Unusable)
5116 {
5117 /* Selector. */
5118 if (!(Ldtr.Sel & X86_SEL_LDT))
5119 { /* likely */ }
5120 else
5121 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5122
5123 /* Base. */
5124 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5125 {
5126 if (X86_IS_CANONICAL(Ldtr.u64Base))
5127 { /* likely */ }
5128 else
5129 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5130 }
5131
5132 /* Attributes. */
5133 /* Reserved bits (bits 31:17 and bits 11:8). */
5134 if (!(Ldtr.Attr.u & 0xfffe0f00))
5135 { /* likely */ }
5136 else
5137 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5138
5139 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5140 { /* likely */ }
5141 else
5142 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5143
5144 if (!Ldtr.Attr.n.u1DescType)
5145 { /* likely */ }
5146 else
5147 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5148
5149 if (Ldtr.Attr.n.u1Present)
5150 { /* likely */ }
5151 else
5152 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5153
5154 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5155 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5156 { /* likely */ }
5157 else
5158 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5159 }
5160 }
5161
5162 /*
5163 * TR.
5164 */
5165 {
5166 CPUMSELREG Tr;
5167 Tr.Sel = pVmcs->GuestTr;
5168 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5169 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5170 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5171
5172 /* Selector. */
5173 if (!(Tr.Sel & X86_SEL_LDT))
5174 { /* likely */ }
5175 else
5176 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5177
5178 /* Base. */
5179 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5180 {
5181 if (X86_IS_CANONICAL(Tr.u64Base))
5182 { /* likely */ }
5183 else
5184 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5185 }
5186
5187 /* Attributes. */
5188 /* Reserved bits (bits 31:17 and bits 11:8). */
5189 if (!(Tr.Attr.u & 0xfffe0f00))
5190 { /* likely */ }
5191 else
5192 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5193
5194 if (!Tr.Attr.n.u1Unusable)
5195 { /* likely */ }
5196 else
5197 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5198
5199 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5200 || ( !fGstInLongMode
5201 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5202 { /* likely */ }
5203 else
5204 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5205
5206 if (!Tr.Attr.n.u1DescType)
5207 { /* likely */ }
5208 else
5209 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5210
5211 if (Tr.Attr.n.u1Present)
5212 { /* likely */ }
5213 else
5214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5215
5216 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5217 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5218 { /* likely */ }
5219 else
5220 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5221 }
5222
5223 NOREF(pszInstr);
5224 NOREF(pszFailure);
5225 return VINF_SUCCESS;
5226}
5227
5228
5229/**
5230 * Checks guest GDTR and IDTR as part of VM-entry.
5231 *
5232 * @param pVCpu The cross context virtual CPU structure.
5233 * @param pszInstr The VMX instruction name (for logging purposes).
5234 */
5235DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5236{
5237 /*
5238 * GDTR and IDTR.
5239 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5240 */
5241 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5242 const char *const pszFailure = "VM-exit";
5243
5244 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5245 {
5246 /* Base. */
5247 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5248 { /* likely */ }
5249 else
5250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5251
5252 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5253 { /* likely */ }
5254 else
5255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5256 }
5257
5258 /* Limit. */
5259 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5260 { /* likely */ }
5261 else
5262 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5263
5264 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5265 { /* likely */ }
5266 else
5267 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5268
5269 NOREF(pszInstr);
5270 NOREF(pszFailure);
5271 return VINF_SUCCESS;
5272}
5273
5274
5275/**
5276 * Checks guest RIP and RFLAGS as part of VM-entry.
5277 *
5278 * @param pVCpu The cross context virtual CPU structure.
5279 * @param pszInstr The VMX instruction name (for logging purposes).
5280 */
5281DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5282{
5283 /*
5284 * RIP and RFLAGS.
5285 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5286 */
5287 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5288 const char *const pszFailure = "VM-exit";
5289 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5290
5291 /* RIP. */
5292 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5293 {
5294 X86DESCATTR AttrCs;
5295 AttrCs.u = pVmcs->u32GuestCsAttr;
5296 if ( !fGstInLongMode
5297 || !AttrCs.n.u1Long)
5298 {
5299 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5300 { /* likely */ }
5301 else
5302 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5303 }
5304
5305 if ( fGstInLongMode
5306 && AttrCs.n.u1Long)
5307 {
5308 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5309 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5310 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5311 { /* likely */ }
5312 else
5313 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5314 }
5315 }
5316
5317 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5318 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5319 : pVmcs->u64GuestRFlags.s.Lo;
5320 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5321 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5322 { /* likely */ }
5323 else
5324 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5325
5326 if ( fGstInLongMode
5327 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5328 {
5329 if (!(uGuestRFlags & X86_EFL_VM))
5330 { /* likely */ }
5331 else
5332 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5333 }
5334
5335 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5336 {
5337 if (uGuestRFlags & X86_EFL_IF)
5338 { /* likely */ }
5339 else
5340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5341 }
5342
5343 NOREF(pszInstr);
5344 NOREF(pszFailure);
5345 return VINF_SUCCESS;
5346}
5347
5348
5349/**
5350 * Checks guest non-register state as part of VM-entry.
5351 *
5352 * @param pVCpu The cross context virtual CPU structure.
5353 * @param pszInstr The VMX instruction name (for logging purposes).
5354 */
5355DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5356{
5357 /*
5358 * Guest non-register state.
5359 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5360 */
5361 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5362 const char *const pszFailure = "VM-exit";
5363
5364 /*
5365 * Activity state.
5366 */
5367 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5368 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5369 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5370 { /* likely */ }
5371 else
5372 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5373
5374 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5375 if ( !AttrSs.n.u2Dpl
5376 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5377 { /* likely */ }
5378 else
5379 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5380
5381 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5382 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5383 {
5384 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5385 { /* likely */ }
5386 else
5387 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5388 }
5389
5390 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5391 {
5392 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5393 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5394 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5395 switch (pVmcs->u32GuestActivityState)
5396 {
5397 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5398 {
5399 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5400 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5401 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5402 && ( uVector == X86_XCPT_DB
5403 || uVector == X86_XCPT_MC))
5404 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5405 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5406 { /* likely */ }
5407 else
5408 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5409 break;
5410 }
5411
5412 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5413 {
5414 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5415 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5416 && uVector == X86_XCPT_MC))
5417 { /* likely */ }
5418 else
5419 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5420 break;
5421 }
5422
5423 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5424 default:
5425 break;
5426 }
5427 }
5428
5429 /*
5430 * Interruptibility state.
5431 */
5432 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5433 { /* likely */ }
5434 else
5435 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5436
5437 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5438 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5439 { /* likely */ }
5440 else
5441 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5442
5443 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5444 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5445 { /* likely */ }
5446 else
5447 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5448
5449 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5450 {
5451 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5452 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5453 {
5454 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5455 { /* likely */ }
5456 else
5457 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5458 }
5459 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5460 {
5461 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5462 { /* likely */ }
5463 else
5464 {
5465 /*
5466 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5467 * We update the Exit qualification only when blocking-by-STI is set
5468 * without blocking-by-MovSS being set. Although in practise it does not
5469 * make much difference since the order of checks are implementation defined.
5470 */
5471 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5472 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5473 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5474 }
5475
5476 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5477 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5478 { /* likely */ }
5479 else
5480 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5481 }
5482 }
5483
5484 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5485 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5486 { /* likely */ }
5487 else
5488 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5489
5490 /* We don't support SGX yet. So enclave-interruption must not be set. */
5491 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5492 { /* likely */ }
5493 else
5494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5495
5496 /*
5497 * Pending debug exceptions.
5498 */
5499 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5500 ? pVmcs->u64GuestPendingDbgXcpts.u
5501 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5502 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5503 { /* likely */ }
5504 else
5505 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5506
5507 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5508 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5509 {
5510 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5511 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5512 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5513 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5514
5515 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5516 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5517 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5518 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5519 }
5520
5521 /* We don't support RTM (Real-time Transactional Memory) yet. */
5522 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5523 { /* likely */ }
5524 else
5525 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5526
5527 /*
5528 * VMCS link pointer.
5529 */
5530 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5531 {
5532 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5533 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5534 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5535 { /* likely */ }
5536 else
5537 {
5538 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5539 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5540 }
5541
5542 /* Validate the address. */
5543 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5544 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5545 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5546 { /* likely */ }
5547 else
5548 {
5549 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5550 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5551 }
5552 }
5553
5554 NOREF(pszInstr);
5555 NOREF(pszFailure);
5556 return VINF_SUCCESS;
5557}
5558
5559
5560/**
5561 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5562 * VM-entry.
5563 *
5564 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5565 * @param pVCpu The cross context virtual CPU structure.
5566 * @param pszInstr The VMX instruction name (for logging purposes).
5567 * @param pVmcs Pointer to the virtual VMCS.
5568 */
5569IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPUCC pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5570{
5571 /*
5572 * Check PDPTEs.
5573 * See Intel spec. 4.4.1 "PDPTE Registers".
5574 */
5575 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5576 const char *const pszFailure = "VM-exit";
5577
5578 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5579 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5580 if (RT_SUCCESS(rc))
5581 {
5582 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5583 {
5584 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5585 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5586 { /* likely */ }
5587 else
5588 {
5589 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5590 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5591 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5592 }
5593 }
5594 }
5595 else
5596 {
5597 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5598 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5599 }
5600
5601 NOREF(pszFailure);
5602 NOREF(pszInstr);
5603 return rc;
5604}
5605
5606
5607/**
5608 * Checks guest PDPTEs as part of VM-entry.
5609 *
5610 * @param pVCpu The cross context virtual CPU structure.
5611 * @param pszInstr The VMX instruction name (for logging purposes).
5612 */
5613DECLINLINE(int) iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr)
5614{
5615 /*
5616 * Guest PDPTEs.
5617 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5618 */
5619 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5620 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5621
5622 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5623 int rc;
5624 if ( !fGstInLongMode
5625 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5626 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5627 {
5628 /*
5629 * We don't support nested-paging for nested-guests yet.
5630 *
5631 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5632 * rather we need to check the PDPTEs referenced by the guest CR3.
5633 */
5634 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5635 }
5636 else
5637 rc = VINF_SUCCESS;
5638 return rc;
5639}
5640
5641
5642/**
5643 * Checks guest-state as part of VM-entry.
5644 *
5645 * @returns VBox status code.
5646 * @param pVCpu The cross context virtual CPU structure.
5647 * @param pszInstr The VMX instruction name (for logging purposes).
5648 */
5649IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr)
5650{
5651 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5652 if (RT_SUCCESS(rc))
5653 {
5654 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5655 if (RT_SUCCESS(rc))
5656 {
5657 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5658 if (RT_SUCCESS(rc))
5659 {
5660 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5661 if (RT_SUCCESS(rc))
5662 {
5663 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5664 if (RT_SUCCESS(rc))
5665 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5666 }
5667 }
5668 }
5669 }
5670 return rc;
5671}
5672
5673
5674/**
5675 * Checks host-state as part of VM-entry.
5676 *
5677 * @returns VBox status code.
5678 * @param pVCpu The cross context virtual CPU structure.
5679 * @param pszInstr The VMX instruction name (for logging purposes).
5680 */
5681IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5682{
5683 /*
5684 * Host Control Registers and MSRs.
5685 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5686 */
5687 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5688 const char * const pszFailure = "VMFail";
5689
5690 /* CR0 reserved bits. */
5691 {
5692 /* CR0 MB1 bits. */
5693 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5694 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5695 { /* likely */ }
5696 else
5697 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5698
5699 /* CR0 MBZ bits. */
5700 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5701 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5702 { /* likely */ }
5703 else
5704 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5705 }
5706
5707 /* CR4 reserved bits. */
5708 {
5709 /* CR4 MB1 bits. */
5710 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5711 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5712 { /* likely */ }
5713 else
5714 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5715
5716 /* CR4 MBZ bits. */
5717 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5718 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5719 { /* likely */ }
5720 else
5721 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5722 }
5723
5724 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5725 {
5726 /* CR3 reserved bits. */
5727 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5728 { /* likely */ }
5729 else
5730 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5731
5732 /* SYSENTER ESP and SYSENTER EIP. */
5733 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5734 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5735 { /* likely */ }
5736 else
5737 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5738 }
5739
5740 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5741 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5742
5743 /* PAT MSR. */
5744 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5745 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5746 { /* likely */ }
5747 else
5748 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5749
5750 /* EFER MSR. */
5751 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5752 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5753 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5754 { /* likely */ }
5755 else
5756 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5757
5758 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5759 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5760 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5761 if ( fHostInLongMode == fHostLma
5762 && fHostInLongMode == fHostLme)
5763 { /* likely */ }
5764 else
5765 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5766
5767 /*
5768 * Host Segment and Descriptor-Table Registers.
5769 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5770 */
5771 /* Selector RPL and TI. */
5772 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5773 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5774 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5775 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5776 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5777 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5778 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5779 { /* likely */ }
5780 else
5781 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5782
5783 /* CS and TR selectors cannot be 0. */
5784 if ( pVmcs->HostCs
5785 && pVmcs->HostTr)
5786 { /* likely */ }
5787 else
5788 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5789
5790 /* SS cannot be 0 if 32-bit host. */
5791 if ( fHostInLongMode
5792 || pVmcs->HostSs)
5793 { /* likely */ }
5794 else
5795 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5796
5797 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5798 {
5799 /* FS, GS, GDTR, IDTR, TR base address. */
5800 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5801 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5802 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5803 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5804 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5805 { /* likely */ }
5806 else
5807 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5808 }
5809
5810 /*
5811 * Host address-space size for 64-bit CPUs.
5812 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5813 */
5814 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5815 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5816 {
5817 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5818
5819 /* Logical processor in IA-32e mode. */
5820 if (fCpuInLongMode)
5821 {
5822 if (fHostInLongMode)
5823 {
5824 /* PAE must be set. */
5825 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5826 { /* likely */ }
5827 else
5828 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5829
5830 /* RIP must be canonical. */
5831 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5832 { /* likely */ }
5833 else
5834 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5835 }
5836 else
5837 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5838 }
5839 else
5840 {
5841 /* Logical processor is outside IA-32e mode. */
5842 if ( !fGstInLongMode
5843 && !fHostInLongMode)
5844 {
5845 /* PCIDE should not be set. */
5846 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5847 { /* likely */ }
5848 else
5849 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5850
5851 /* The high 32-bits of RIP MBZ. */
5852 if (!pVmcs->u64HostRip.s.Hi)
5853 { /* likely */ }
5854 else
5855 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5856 }
5857 else
5858 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5859 }
5860 }
5861 else
5862 {
5863 /* Host address-space size for 32-bit CPUs. */
5864 if ( !fGstInLongMode
5865 && !fHostInLongMode)
5866 { /* likely */ }
5867 else
5868 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5869 }
5870
5871 NOREF(pszInstr);
5872 NOREF(pszFailure);
5873 return VINF_SUCCESS;
5874}
5875
5876
5877/**
5878 * Checks VMCS controls fields as part of VM-entry.
5879 *
5880 * @returns VBox status code.
5881 * @param pVCpu The cross context virtual CPU structure.
5882 * @param pszInstr The VMX instruction name (for logging purposes).
5883 *
5884 * @remarks This may update secondary-processor based VM-execution control fields
5885 * in the current VMCS if necessary.
5886 */
5887IEM_STATIC int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr)
5888{
5889 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5890 const char * const pszFailure = "VMFail";
5891
5892 /*
5893 * VM-execution controls.
5894 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
5895 */
5896 {
5897 /* Pin-based VM-execution controls. */
5898 {
5899 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
5900 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
5901 { /* likely */ }
5902 else
5903 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
5904
5905 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
5906 { /* likely */ }
5907 else
5908 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
5909 }
5910
5911 /* Processor-based VM-execution controls. */
5912 {
5913 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
5914 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
5915 { /* likely */ }
5916 else
5917 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
5918
5919 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
5920 { /* likely */ }
5921 else
5922 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
5923 }
5924
5925 /* Secondary processor-based VM-execution controls. */
5926 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
5927 {
5928 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
5929 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
5930 { /* likely */ }
5931 else
5932 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
5933
5934 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
5935 { /* likely */ }
5936 else
5937 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
5938 }
5939 else
5940 Assert(!pVmcs->u32ProcCtls2);
5941
5942 /* CR3-target count. */
5943 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
5944 { /* likely */ }
5945 else
5946 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
5947
5948 /* I/O bitmaps physical addresses. */
5949 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
5950 {
5951 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
5952 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
5953 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5954 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
5955 { /* likely */ }
5956 else
5957 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
5958
5959 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
5960 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
5961 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5962 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
5963 { /* likely */ }
5964 else
5965 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
5966 }
5967
5968 /* MSR bitmap physical address. */
5969 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
5970 {
5971 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
5972 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
5973 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5974 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
5975 { /* likely */ }
5976 else
5977 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
5978 }
5979
5980 /* TPR shadow related controls. */
5981 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
5982 {
5983 /* Virtual-APIC page physical address. */
5984 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
5985 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
5986 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5987 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
5988 { /* likely */ }
5989 else
5990 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
5991
5992 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
5993 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
5994 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
5995 { /* likely */ }
5996 else
5997 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
5998
5999 /* The rest done XXX document */
6000 }
6001 else
6002 {
6003 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6004 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6005 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6006 { /* likely */ }
6007 else
6008 {
6009 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6010 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6011 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6012 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6013 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6014 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6015 }
6016 }
6017
6018 /* NMI exiting and virtual-NMIs. */
6019 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6020 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6021 { /* likely */ }
6022 else
6023 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6024
6025 /* Virtual-NMIs and NMI-window exiting. */
6026 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6027 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6028 { /* likely */ }
6029 else
6030 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6031
6032 /* Virtualize APIC accesses. */
6033 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6034 {
6035 /* APIC-access physical address. */
6036 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6037 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6038 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6039 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6040 { /* likely */ }
6041 else
6042 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6043
6044 /*
6045 * Disallow APIC-access page and virtual-APIC page from being the same address.
6046 * Note! This is not an Intel requirement, but one imposed by our implementation.
6047 */
6048 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6049 * redirecting accesses between the APIC-access page and the virtual-APIC
6050 * page. If any nested hypervisor requires this, we can implement it later. */
6051 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6052 {
6053 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6054 if (GCPhysVirtApic != GCPhysApicAccess)
6055 { /* likely */ }
6056 else
6057 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6058 }
6059 }
6060
6061 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6062 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6063 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6064 { /* likely */ }
6065 else
6066 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6067
6068 /* Virtual-interrupt delivery requires external interrupt exiting. */
6069 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6070 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6071 { /* likely */ }
6072 else
6073 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6074
6075 /* VPID. */
6076 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6077 || pVmcs->u16Vpid != 0)
6078 { /* likely */ }
6079 else
6080 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6081
6082 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6083 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6084 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6085 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6086 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6087 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6088 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6089 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6090
6091 /* VMCS shadowing. */
6092 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6093 {
6094 /* VMREAD-bitmap physical address. */
6095 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6096 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6097 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6098 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6099 { /* likely */ }
6100 else
6101 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6102
6103 /* VMWRITE-bitmap physical address. */
6104 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6105 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6106 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6107 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6108 { /* likely */ }
6109 else
6110 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6111 }
6112 }
6113
6114 /*
6115 * VM-exit controls.
6116 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6117 */
6118 {
6119 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6120 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6121 { /* likely */ }
6122 else
6123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6124
6125 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6126 { /* likely */ }
6127 else
6128 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6129
6130 /* Save preemption timer without activating it. */
6131 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6132 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6133 { /* likely */ }
6134 else
6135 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6136
6137 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6138 if (pVmcs->u32ExitMsrStoreCount)
6139 {
6140 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6141 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6142 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6143 { /* likely */ }
6144 else
6145 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6146 }
6147
6148 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6149 if (pVmcs->u32ExitMsrLoadCount)
6150 {
6151 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6152 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6153 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6154 { /* likely */ }
6155 else
6156 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6157 }
6158 }
6159
6160 /*
6161 * VM-entry controls.
6162 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6163 */
6164 {
6165 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6166 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6167 { /* likely */ }
6168 else
6169 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6170
6171 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6172 { /* likely */ }
6173 else
6174 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6175
6176 /* Event injection. */
6177 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6178 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6179 {
6180 /* Type and vector. */
6181 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6182 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6183 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6184 if ( !uRsvd
6185 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6186 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6187 { /* likely */ }
6188 else
6189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6190
6191 /* Exception error code. */
6192 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6193 {
6194 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6195 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6196 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6197 { /* likely */ }
6198 else
6199 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6200
6201 /* Exceptions that provide an error code. */
6202 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6203 && ( uVector == X86_XCPT_DF
6204 || uVector == X86_XCPT_TS
6205 || uVector == X86_XCPT_NP
6206 || uVector == X86_XCPT_SS
6207 || uVector == X86_XCPT_GP
6208 || uVector == X86_XCPT_PF
6209 || uVector == X86_XCPT_AC))
6210 { /* likely */ }
6211 else
6212 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6213
6214 /* Exception error-code reserved bits. */
6215 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6216 { /* likely */ }
6217 else
6218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6219
6220 /* Injecting a software interrupt, software exception or privileged software exception. */
6221 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6222 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6223 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6224 {
6225 /* Instruction length must be in the range 0-15. */
6226 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6227 { /* likely */ }
6228 else
6229 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6230
6231 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6232 if ( pVmcs->u32EntryInstrLen != 0
6233 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6234 { /* likely */ }
6235 else
6236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6237 }
6238 }
6239 }
6240
6241 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6242 if (pVmcs->u32EntryMsrLoadCount)
6243 {
6244 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6245 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6246 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6247 { /* likely */ }
6248 else
6249 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6250 }
6251
6252 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6253 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6254 }
6255
6256 NOREF(pszInstr);
6257 NOREF(pszFailure);
6258 return VINF_SUCCESS;
6259}
6260
6261
6262/**
6263 * Loads the guest control registers, debug register and some MSRs as part of
6264 * VM-entry.
6265 *
6266 * @param pVCpu The cross context virtual CPU structure.
6267 */
6268IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6269{
6270 /*
6271 * Load guest control registers, debug registers and MSRs.
6272 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6273 */
6274 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6275
6276 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6277 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6278 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6279 CPUMSetGuestCR0(pVCpu, uGstCr0);
6280 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6281 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6282
6283 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6284 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6285
6286 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6287 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6288 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6289
6290 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6291 {
6292 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6293
6294 /* EFER MSR. */
6295 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6296 {
6297 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6298 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6299 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6300 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6301 if (fGstInLongMode)
6302 {
6303 /* If the nested-guest is in long mode, LMA and LME are both set. */
6304 Assert(fGstPaging);
6305 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6306 }
6307 else
6308 {
6309 /*
6310 * If the nested-guest is outside long mode:
6311 * - With paging: LMA is cleared, LME is cleared.
6312 * - Without paging: LMA is cleared, LME is left unmodified.
6313 */
6314 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6315 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6316 }
6317 }
6318 /* else: see below. */
6319 }
6320
6321 /* PAT MSR. */
6322 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6323 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6324
6325 /* EFER MSR. */
6326 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6327 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6328
6329 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6330 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6331
6332 /* We don't support IA32_BNDCFGS MSR yet. */
6333 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6334
6335 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6336}
6337
6338
6339/**
6340 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6341 *
6342 * @param pVCpu The cross context virtual CPU structure.
6343 */
6344IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6345{
6346 /*
6347 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6348 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6349 */
6350 /* CS, SS, ES, DS, FS, GS. */
6351 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6352 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6353 {
6354 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6355 CPUMSELREG VmcsSelReg;
6356 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6357 AssertRC(rc); NOREF(rc);
6358 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6359 {
6360 pGstSelReg->Sel = VmcsSelReg.Sel;
6361 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6362 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6363 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6364 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6365 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6366 }
6367 else
6368 {
6369 pGstSelReg->Sel = VmcsSelReg.Sel;
6370 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6371 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6372 switch (iSegReg)
6373 {
6374 case X86_SREG_CS:
6375 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6376 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6377 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6378 break;
6379
6380 case X86_SREG_SS:
6381 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6382 pGstSelReg->u32Limit = 0;
6383 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6384 break;
6385
6386 case X86_SREG_ES:
6387 case X86_SREG_DS:
6388 pGstSelReg->u64Base = 0;
6389 pGstSelReg->u32Limit = 0;
6390 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6391 break;
6392
6393 case X86_SREG_FS:
6394 case X86_SREG_GS:
6395 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6396 pGstSelReg->u32Limit = 0;
6397 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6398 break;
6399 }
6400 Assert(pGstSelReg->Attr.n.u1Unusable);
6401 }
6402 }
6403
6404 /* LDTR. */
6405 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6406 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6407 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6408 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6409 {
6410 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6411 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6412 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6413 }
6414 else
6415 {
6416 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6417 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6418 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6419 }
6420
6421 /* TR. */
6422 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6423 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6424 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6425 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6426 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6427 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6428 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6429
6430 /* GDTR. */
6431 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6432 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6433
6434 /* IDTR. */
6435 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6436 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6437}
6438
6439
6440/**
6441 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6442 *
6443 * @returns VBox status code.
6444 * @param pVCpu The cross context virtual CPU structure.
6445 * @param pszInstr The VMX instruction name (for logging purposes).
6446 */
6447IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6448{
6449 /*
6450 * Load guest MSRs.
6451 * See Intel spec. 26.4 "Loading MSRs".
6452 */
6453 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6454 const char *const pszFailure = "VM-exit";
6455
6456 /*
6457 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6458 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6459 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6460 */
6461 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6462 if (!cMsrs)
6463 return VINF_SUCCESS;
6464
6465 /*
6466 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6467 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6468 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6469 */
6470 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6471 if (fIsMsrCountValid)
6472 { /* likely */ }
6473 else
6474 {
6475 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6476 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6477 }
6478
6479 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6480 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea),
6481 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6482 if (RT_SUCCESS(rc))
6483 {
6484 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea);
6485 Assert(pMsr);
6486 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6487 {
6488 if ( !pMsr->u32Reserved
6489 && pMsr->u32Msr != MSR_K8_FS_BASE
6490 && pMsr->u32Msr != MSR_K8_GS_BASE
6491 && pMsr->u32Msr != MSR_K6_EFER
6492 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6493 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6494 {
6495 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6496 if (rcStrict == VINF_SUCCESS)
6497 continue;
6498
6499 /*
6500 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6501 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6502 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6503 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6504 * MSR in ring-0 if possible, or come up with a better, generic solution.
6505 */
6506 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6507 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6508 ? kVmxVDiag_Vmentry_MsrLoadRing3
6509 : kVmxVDiag_Vmentry_MsrLoad;
6510 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6511 }
6512 else
6513 {
6514 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6515 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6516 }
6517 }
6518 }
6519 else
6520 {
6521 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6522 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6523 }
6524
6525 NOREF(pszInstr);
6526 NOREF(pszFailure);
6527 return VINF_SUCCESS;
6528}
6529
6530
6531/**
6532 * Loads the guest-state non-register state as part of VM-entry.
6533 *
6534 * @returns VBox status code.
6535 * @param pVCpu The cross context virtual CPU structure.
6536 *
6537 * @remarks This must be called only after loading the nested-guest register state
6538 * (especially nested-guest RIP).
6539 */
6540IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu)
6541{
6542 /*
6543 * Load guest non-register state.
6544 * See Intel spec. 26.6 "Special Features of VM Entry"
6545 */
6546 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6547
6548 /*
6549 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6550 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6551 *
6552 * See Intel spec. 26.6.1 "Interruptibility State".
6553 */
6554 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6555 if ( !fEntryVectoring
6556 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6557 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6558 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6559 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6560
6561 /* NMI blocking. */
6562 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6563 {
6564 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6565 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6566 else
6567 {
6568 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6569 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6570 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6571 }
6572 }
6573 else
6574 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6575
6576 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6577
6578 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6579 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6580
6581 /* VPID is irrelevant. We don't support VPID yet. */
6582
6583 /* Clear address-range monitoring. */
6584 EMMonitorWaitClear(pVCpu);
6585}
6586
6587
6588/**
6589 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
6590 *
6591 * @param pVCpu The cross context virtual CPU structure.
6592 * @param pszInstr The VMX instruction name (for logging purposes).
6593 *
6594 * @remarks This assumes various VMCS related data structure pointers have already
6595 * been verified prior to calling this function.
6596 */
6597IEM_STATIC int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr)
6598{
6599 const char *const pszFailure = "VM-exit";
6600 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6601
6602 /*
6603 * Virtualize APIC accesses.
6604 */
6605 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6606 {
6607 /* APIC-access physical address. */
6608 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6609
6610 /*
6611 * Register the handler for the APIC-access page.
6612 *
6613 * We don't deregister the APIC-access page handler during the VM-exit as a different
6614 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6615 *
6616 * We leave the page registered until the first access that happens outside VMX non-root
6617 * mode. Guest software is allowed to access structures such as the APIC-access page
6618 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6619 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6620 *
6621 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6622 */
6623 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6624 {
6625 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6626 PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
6627 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6628 pVCpu0->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6629 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6630 if (RT_SUCCESS(rc))
6631 { /* likely */ }
6632 else
6633 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6634 }
6635 }
6636
6637 /*
6638 * VMCS shadowing.
6639 */
6640 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6641 {
6642 /* Read the VMREAD-bitmap. */
6643 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6644 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6645 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6646 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6647 if (RT_SUCCESS(rc))
6648 { /* likely */ }
6649 else
6650 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6651
6652 /* Read the VMWRITE-bitmap. */
6653 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
6654 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6655 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6656 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6657 if (RT_SUCCESS(rc))
6658 { /* likely */ }
6659 else
6660 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6661 }
6662
6663 /*
6664 * I/O bitmaps.
6665 */
6666 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6667 {
6668 /* Read the IO bitmap A. */
6669 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6670 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap));
6671 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap),
6672 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
6673 if (RT_SUCCESS(rc))
6674 { /* likely */ }
6675 else
6676 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
6677
6678 /* Read the IO bitmap B. */
6679 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6680 uint8_t *pbIoBitmapB = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
6681 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pbIoBitmapB, GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
6682 if (RT_SUCCESS(rc))
6683 { /* likely */ }
6684 else
6685 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
6686 }
6687
6688 /*
6689 * TPR shadow and Virtual-APIC page.
6690 */
6691 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6692 {
6693 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6694 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6695 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6696 {
6697 /* Read the VTPR from the virtual-APIC page. */
6698 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6699 uint8_t u8VTpr;
6700 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6701 if (RT_SUCCESS(rc))
6702 { /* likely */ }
6703 else
6704 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6705
6706 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6707 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6708 { /* likely */ }
6709 else
6710 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6711 }
6712 }
6713
6714 /*
6715 * VMCS link pointer.
6716 */
6717 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6718 {
6719 /* Read the VMCS-link pointer from guest memory. */
6720 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6721 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
6722 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
6723 GCPhysShadowVmcs, VMX_V_SHADOW_VMCS_SIZE);
6724 if (RT_SUCCESS(rc))
6725 { /* likely */ }
6726 else
6727 {
6728 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6729 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6730 }
6731
6732 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6733 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6734 { /* likely */ }
6735 else
6736 {
6737 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6738 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6739 }
6740
6741 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6742 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6743 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
6744 { /* likely */ }
6745 else
6746 {
6747 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6748 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6749 }
6750
6751 /* Update our cache of the guest physical address of the shadow VMCS. */
6752 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6753 }
6754
6755 /*
6756 * MSR bitmap.
6757 */
6758 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6759 {
6760 /* Read the MSR bitmap. */
6761 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6762 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6763 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6764 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6765 if (RT_SUCCESS(rc))
6766 { /* likely */ }
6767 else
6768 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6769 }
6770
6771 NOREF(pszFailure);
6772 NOREF(pszInstr);
6773 return VINF_SUCCESS;
6774}
6775
6776
6777/**
6778 * Loads the guest-state as part of VM-entry.
6779 *
6780 * @returns VBox status code.
6781 * @param pVCpu The cross context virtual CPU structure.
6782 * @param pszInstr The VMX instruction name (for logging purposes).
6783 *
6784 * @remarks This must be done after all the necessary steps prior to loading of
6785 * guest-state (e.g. checking various VMCS state).
6786 */
6787IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6788{
6789 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
6790 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6791
6792 /* Load guest segment registers. */
6793 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6794
6795 /*
6796 * Load guest RIP, RSP and RFLAGS.
6797 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6798 */
6799 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6800 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6801 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6802 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6803
6804 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6805 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6806 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6807
6808 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
6809 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6810
6811 /* Load VMX related structures and state referenced by the VMCS. */
6812 int rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
6813 if (rc == VINF_SUCCESS)
6814 { /* likely */ }
6815 else
6816 return rc;
6817
6818 NOREF(pszInstr);
6819 return VINF_SUCCESS;
6820}
6821
6822
6823/**
6824 * Returns whether there are is a pending debug exception on VM-entry.
6825 *
6826 * @param pVCpu The cross context virtual CPU structure.
6827 * @param pszInstr The VMX instruction name (for logging purposes).
6828 */
6829IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6830{
6831 /*
6832 * Pending debug exceptions.
6833 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6834 */
6835 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6836 Assert(pVmcs);
6837
6838 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6839 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6840 if (fPendingDbgXcpt)
6841 {
6842 uint8_t uEntryIntInfoType;
6843 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6844 if (fEntryVectoring)
6845 {
6846 switch (uEntryIntInfoType)
6847 {
6848 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6849 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6850 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6851 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6852 fPendingDbgXcpt = false;
6853 break;
6854
6855 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6856 {
6857 /*
6858 * Whether the pending debug exception for software exceptions other than
6859 * #BP and #OF is delivered after injecting the exception or is discard
6860 * is CPU implementation specific. We will discard them (easier).
6861 */
6862 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6863 if ( uVector != X86_XCPT_BP
6864 && uVector != X86_XCPT_OF)
6865 fPendingDbgXcpt = false;
6866 RT_FALL_THRU();
6867 }
6868 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6869 {
6870 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6871 fPendingDbgXcpt = false;
6872 break;
6873 }
6874 }
6875 }
6876 else
6877 {
6878 /*
6879 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6880 * pending debug exception is held pending or is discarded is CPU implementation
6881 * specific. We will discard them (easier).
6882 */
6883 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6884 fPendingDbgXcpt = false;
6885
6886 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
6887 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
6888 fPendingDbgXcpt = false;
6889 }
6890 }
6891
6892 NOREF(pszInstr);
6893 return fPendingDbgXcpt;
6894}
6895
6896
6897/**
6898 * Set up the monitor-trap flag (MTF).
6899 *
6900 * @param pVCpu The cross context virtual CPU structure.
6901 * @param pszInstr The VMX instruction name (for logging purposes).
6902 */
6903IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
6904{
6905 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6906 Assert(pVmcs);
6907 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
6908 {
6909 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
6910 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
6911 }
6912 else
6913 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
6914 NOREF(pszInstr);
6915}
6916
6917
6918/**
6919 * Sets up NMI-window exiting.
6920 *
6921 * @param pVCpu The cross context virtual CPU structure.
6922 * @param pszInstr The VMX instruction name (for logging purposes).
6923 */
6924IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
6925{
6926 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6927 Assert(pVmcs);
6928 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
6929 {
6930 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
6931 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
6932 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
6933 }
6934 else
6935 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
6936 NOREF(pszInstr);
6937}
6938
6939
6940/**
6941 * Sets up interrupt-window exiting.
6942 *
6943 * @param pVCpu The cross context virtual CPU structure.
6944 * @param pszInstr The VMX instruction name (for logging purposes).
6945 */
6946IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
6947{
6948 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6949 Assert(pVmcs);
6950 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
6951 {
6952 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
6953 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
6954 }
6955 else
6956 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
6957 NOREF(pszInstr);
6958}
6959
6960
6961/**
6962 * Set up the VMX-preemption timer.
6963 *
6964 * @param pVCpu The cross context virtual CPU structure.
6965 * @param pszInstr The VMX instruction name (for logging purposes).
6966 */
6967IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
6968{
6969 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6970 Assert(pVmcs);
6971 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6972 {
6973 /*
6974 * If the timer is 0, we must cause a VM-exit before executing the first
6975 * nested-guest instruction. So we can flag as though the timer has already
6976 * expired and we will check and cause a VM-exit at the right priority elsewhere
6977 * in the code.
6978 */
6979 uint64_t uEntryTick;
6980 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
6981 if (uPreemptTimer)
6982 {
6983 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
6984 AssertRC(rc);
6985 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
6986 }
6987 else
6988 {
6989 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
6990 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
6991 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
6992 }
6993
6994 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
6995 }
6996 else
6997 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
6998
6999 NOREF(pszInstr);
7000}
7001
7002
7003/**
7004 * Injects an event using TRPM given a VM-entry interruption info. and related
7005 * fields.
7006 *
7007 * @param pVCpu The cross context virtual CPU structure.
7008 * @param pszInstr The VMX instruction name (for logging purposes).
7009 * @param uEntryIntInfo The VM-entry interruption info.
7010 * @param uErrCode The error code associated with the event if any.
7011 * @param cbInstr The VM-entry instruction length (for software
7012 * interrupts and software exceptions). Pass 0
7013 * otherwise.
7014 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7015 */
7016IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7017 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7018{
7019 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7020
7021 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7022 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7023 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7024
7025 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7026
7027 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7028 AssertRC(rc);
7029 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7030
7031 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7032 {
7033 TRPMSetErrorCode(pVCpu, uErrCode);
7034 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7035 }
7036
7037 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7038 {
7039 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7040 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7041 }
7042 else
7043 {
7044 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7045 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7046 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7047 {
7048 TRPMSetInstrLength(pVCpu, cbInstr);
7049 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7050 }
7051 }
7052
7053 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7054 {
7055 TRPMSetTrapDueToIcebp(pVCpu);
7056 Log(("%s: Injecting: icebp\n", pszInstr));
7057 }
7058
7059 NOREF(pszInstr);
7060}
7061
7062
7063/**
7064 * Performs event injection (if any) as part of VM-entry.
7065 *
7066 * @param pVCpu The cross context virtual CPU structure.
7067 * @param pszInstr The VMX instruction name (for logging purposes).
7068 */
7069IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7070{
7071 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7072
7073 /*
7074 * Inject events.
7075 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7076 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7077 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7078 * the actually delivery of this event.
7079 *
7080 * See Intel spec. 26.5 "Event Injection".
7081 */
7082 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7083 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7084
7085 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7086 if (fEntryIntInfoValid)
7087 {
7088 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7089 {
7090 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7091 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7092 }
7093 else
7094 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7095 pVCpu->cpum.GstCtx.cr2);
7096
7097 /*
7098 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7099 *
7100 * However, we do it here on VM-entry as well because while it isn't visible to guest
7101 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7102 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7103 *
7104 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7105 */
7106 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7107 }
7108 else
7109 {
7110 /*
7111 * Inject any pending guest debug exception.
7112 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7113 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7114 */
7115 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7116 if (fPendingDbgXcpt)
7117 {
7118 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7119 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7120 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7121 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7122 0 /* GCPtrFaultAddress */);
7123 }
7124 }
7125
7126 NOREF(pszInstr);
7127}
7128
7129
7130/**
7131 * Initializes all read-only VMCS fields as part of VM-entry.
7132 *
7133 * @param pVCpu The cross context virtual CPU structure.
7134 */
7135IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7136{
7137 /*
7138 * Any VMCS field which we do not establish on every VM-exit but may potentially
7139 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7140 * specified to be undefined, needs to be initialized here.
7141 *
7142 * Thus, it is especially important to clear the Exit qualification field
7143 * since it must be zero for VM-exits where it is not used. Similarly, the
7144 * VM-exit interruption information field's valid bit needs to be cleared for
7145 * the same reasons.
7146 */
7147 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7148 Assert(pVmcs);
7149
7150 /* 16-bit (none currently). */
7151 /* 32-bit. */
7152 pVmcs->u32RoVmInstrError = 0;
7153 pVmcs->u32RoExitReason = 0;
7154 pVmcs->u32RoExitIntInfo = 0;
7155 pVmcs->u32RoExitIntErrCode = 0;
7156 pVmcs->u32RoIdtVectoringInfo = 0;
7157 pVmcs->u32RoIdtVectoringErrCode = 0;
7158 pVmcs->u32RoExitInstrLen = 0;
7159 pVmcs->u32RoExitInstrInfo = 0;
7160
7161 /* 64-bit. */
7162 pVmcs->u64RoGuestPhysAddr.u = 0;
7163
7164 /* Natural-width. */
7165 pVmcs->u64RoExitQual.u = 0;
7166 pVmcs->u64RoIoRcx.u = 0;
7167 pVmcs->u64RoIoRsi.u = 0;
7168 pVmcs->u64RoIoRdi.u = 0;
7169 pVmcs->u64RoIoRip.u = 0;
7170 pVmcs->u64RoGuestLinearAddr.u = 0;
7171}
7172
7173
7174/**
7175 * VMLAUNCH/VMRESUME instruction execution worker.
7176 *
7177 * @returns Strict VBox status code.
7178 * @param pVCpu The cross context virtual CPU structure.
7179 * @param cbInstr The instruction length in bytes.
7180 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7181 * VMXINSTRID_VMRESUME).
7182 *
7183 * @remarks Common VMX instruction checks are already expected to by the caller,
7184 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7185 */
7186IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7187{
7188# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7189 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7190 return VINF_EM_RAW_EMULATE_INSTR;
7191# else
7192 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7193 || uInstrId == VMXINSTRID_VMRESUME);
7194 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7195
7196 /* Nested-guest intercept. */
7197 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7198 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7199
7200 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7201
7202 /*
7203 * Basic VM-entry checks.
7204 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7205 * The checks following that do not have to follow a specific order.
7206 *
7207 * See Intel spec. 26.1 "Basic VM-entry Checks".
7208 */
7209
7210 /* CPL. */
7211 if (pVCpu->iem.s.uCpl == 0)
7212 { /* likely */ }
7213 else
7214 {
7215 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7216 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7217 return iemRaiseGeneralProtectionFault0(pVCpu);
7218 }
7219
7220 /* Current VMCS valid. */
7221 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7222 { /* likely */ }
7223 else
7224 {
7225 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7226 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7227 iemVmxVmFailInvalid(pVCpu);
7228 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7229 return VINF_SUCCESS;
7230 }
7231
7232 /* Current VMCS is not a shadow VMCS. */
7233 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7234 { /* likely */ }
7235 else
7236 {
7237 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7238 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7239 iemVmxVmFailInvalid(pVCpu);
7240 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7241 return VINF_SUCCESS;
7242 }
7243
7244 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7245 * use block-by-STI here which is not quite correct. */
7246 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7247 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7248 { /* likely */ }
7249 else
7250 {
7251 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7252 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7253 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7254 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7255 return VINF_SUCCESS;
7256 }
7257
7258 if (uInstrId == VMXINSTRID_VMLAUNCH)
7259 {
7260 /* VMLAUNCH with non-clear VMCS. */
7261 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7262 { /* likely */ }
7263 else
7264 {
7265 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7266 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7267 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7268 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7269 return VINF_SUCCESS;
7270 }
7271 }
7272 else
7273 {
7274 /* VMRESUME with non-launched VMCS. */
7275 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7276 { /* likely */ }
7277 else
7278 {
7279 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7280 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7281 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7282 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7283 return VINF_SUCCESS;
7284 }
7285 }
7286
7287 /*
7288 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7289 * while entering VMX non-root mode. We do some of this while checking VM-execution
7290 * controls. The nested hypervisor should not make assumptions and cannot expect
7291 * predictable behavior if changes to these structures are made in guest memory while
7292 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7293 * modify them anyway as we cache them in host memory.
7294 *
7295 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7296 */
7297 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7298 Assert(pVmcs);
7299 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7300
7301 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7302 if (RT_SUCCESS(rc))
7303 {
7304 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7305 if (RT_SUCCESS(rc))
7306 {
7307 /*
7308 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7309 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7310 * ones that may occur during VM-entry below).
7311 */
7312 iemVmxVmentryInitReadOnlyFields(pVCpu);
7313
7314 /*
7315 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7316 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7317 * VM-exit when required.
7318 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7319 */
7320 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7321
7322 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7323 if (RT_SUCCESS(rc))
7324 {
7325 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7326 if (RT_SUCCESS(rc))
7327 {
7328 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7329 if (RT_SUCCESS(rc))
7330 {
7331 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7332
7333 /* VMLAUNCH instruction must update the VMCS launch state. */
7334 if (uInstrId == VMXINSTRID_VMLAUNCH)
7335 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7336
7337 /* Perform the VMX transition (PGM updates). */
7338 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7339 if (rcStrict == VINF_SUCCESS)
7340 { /* likely */ }
7341 else if (RT_SUCCESS(rcStrict))
7342 {
7343 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7344 VBOXSTRICTRC_VAL(rcStrict)));
7345 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7346 }
7347 else
7348 {
7349 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7350 return rcStrict;
7351 }
7352
7353 /* Paranoia. */
7354 Assert(rcStrict == VINF_SUCCESS);
7355
7356 /* We've now entered nested-guest execution. */
7357 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7358
7359 /*
7360 * The priority of potential VM-exits during VM-entry is important.
7361 * The priorities of VM-exits and events are listed from highest
7362 * to lowest as follows:
7363 *
7364 * 1. Event injection.
7365 * 2. Trap on task-switch (T flag set in TSS).
7366 * 3. TPR below threshold / APIC-write.
7367 * 4. SMI, INIT.
7368 * 5. MTF exit.
7369 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7370 * 7. VMX-preemption timer.
7371 * 9. NMI-window exit.
7372 * 10. NMI injection.
7373 * 11. Interrupt-window exit.
7374 * 12. Virtual-interrupt injection.
7375 * 13. Interrupt injection.
7376 * 14. Process next instruction (fetch, decode, execute).
7377 */
7378
7379 /* Setup VMX-preemption timer. */
7380 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7381
7382 /* Setup monitor-trap flag. */
7383 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7384
7385 /* Setup NMI-window exiting. */
7386 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7387
7388 /* Setup interrupt-window exiting. */
7389 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7390
7391 /*
7392 * Inject any event that the nested hypervisor wants to inject.
7393 * Note! We cannot immediately perform the event injection here as we may have
7394 * pending PGM operations to perform due to switching page tables and/or
7395 * mode.
7396 */
7397 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7398
7399# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7400 /* Reschedule to IEM-only execution of the nested-guest. */
7401 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7402 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7403 if (rcSched != VINF_SUCCESS)
7404 iemSetPassUpStatus(pVCpu, rcSched);
7405# endif
7406
7407 /* Finally, done. */
7408 Log3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",
7409 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7410 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7411 pVCpu->cpum.GstCtx.msrEFER));
7412 return VINF_SUCCESS;
7413 }
7414 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7415 pVmcs->u64RoExitQual.u);
7416 }
7417 }
7418 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7419 pVmcs->u64RoExitQual.u);
7420 }
7421
7422 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7423 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7424 return VINF_SUCCESS;
7425 }
7426
7427 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7428 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7429 return VINF_SUCCESS;
7430# endif
7431}
7432
7433
7434/**
7435 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7436 * (causes a VM-exit) or not.
7437 *
7438 * @returns @c true if the instruction is intercepted, @c false otherwise.
7439 * @param pVCpu The cross context virtual CPU structure.
7440 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7441 * VMX_EXIT_WRMSR).
7442 * @param idMsr The MSR.
7443 */
7444IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7445{
7446 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7447 Assert( uExitReason == VMX_EXIT_RDMSR
7448 || uExitReason == VMX_EXIT_WRMSR);
7449
7450 /* Consult the MSR bitmap if the feature is supported. */
7451 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7452 Assert(pVmcs);
7453 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7454 {
7455 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7456 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr);
7457 if (uExitReason == VMX_EXIT_RDMSR)
7458 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7459 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7460 }
7461
7462 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7463 return true;
7464}
7465
7466
7467/**
7468 * VMREAD instruction execution worker that does not perform any validation checks.
7469 *
7470 * Callers are expected to have performed the necessary checks and to ensure the
7471 * VMREAD will succeed.
7472 *
7473 * @param pVmcs Pointer to the virtual VMCS.
7474 * @param pu64Dst Where to write the VMCS value.
7475 * @param u64VmcsField The VMCS field.
7476 *
7477 * @remarks May be called with interrupts disabled.
7478 */
7479IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7480{
7481 VMXVMCSFIELD VmcsField;
7482 VmcsField.u = u64VmcsField;
7483 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7484 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7485 uint8_t const uWidthType = (uWidth << 2) | uType;
7486 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7487 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7488 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7489 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
7490 uWidth, uType, uIndex, uIndex));
7491 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7492
7493 /*
7494 * Read the VMCS component based on the field's effective width.
7495 *
7496 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7497 * indicates high bits (little endian).
7498 *
7499 * Note! The caller is responsible to trim the result and update registers
7500 * or memory locations are required. Here we just zero-extend to the largest
7501 * type (i.e. 64-bits).
7502 */
7503 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7504 uint8_t const *pbField = pbVmcs + offField;
7505 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7506 switch (uEffWidth)
7507 {
7508 case VMX_VMCSFIELD_WIDTH_64BIT:
7509 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7510 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7511 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7512 }
7513}
7514
7515
7516/**
7517 * VMREAD common (memory/register) instruction execution worker.
7518 *
7519 * @returns Strict VBox status code.
7520 * @param pVCpu The cross context virtual CPU structure.
7521 * @param cbInstr The instruction length in bytes.
7522 * @param pu64Dst Where to write the VMCS value (only updated when
7523 * VINF_SUCCESS is returned).
7524 * @param u64VmcsField The VMCS field.
7525 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7526 * NULL.
7527 */
7528IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7529 PCVMXVEXITINFO pExitInfo)
7530{
7531 /* Nested-guest intercept. */
7532 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7533 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7534 {
7535 if (pExitInfo)
7536 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7537 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7538 }
7539
7540 /* CPL. */
7541 if (pVCpu->iem.s.uCpl == 0)
7542 { /* likely */ }
7543 else
7544 {
7545 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7546 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7547 return iemRaiseGeneralProtectionFault0(pVCpu);
7548 }
7549
7550 /* VMCS pointer in root mode. */
7551 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7552 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7553 { /* likely */ }
7554 else
7555 {
7556 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7557 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7558 iemVmxVmFailInvalid(pVCpu);
7559 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7560 return VINF_SUCCESS;
7561 }
7562
7563 /* VMCS-link pointer in non-root mode. */
7564 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7565 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7566 { /* likely */ }
7567 else
7568 {
7569 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7570 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7571 iemVmxVmFailInvalid(pVCpu);
7572 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7573 return VINF_SUCCESS;
7574 }
7575
7576 /* Supported VMCS field. */
7577 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7578 { /* likely */ }
7579 else
7580 {
7581 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7582 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7583 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7584 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7585 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7586 return VINF_SUCCESS;
7587 }
7588
7589 /*
7590 * Reading from the current or shadow VMCS.
7591 */
7592 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7593 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7594 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7595 Assert(pVmcs);
7596 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7597 return VINF_SUCCESS;
7598}
7599
7600
7601/**
7602 * VMREAD (64-bit register) instruction execution worker.
7603 *
7604 * @returns Strict VBox status code.
7605 * @param pVCpu The cross context virtual CPU structure.
7606 * @param cbInstr The instruction length in bytes.
7607 * @param pu64Dst Where to store the VMCS field's value.
7608 * @param u64VmcsField The VMCS field.
7609 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7610 * NULL.
7611 */
7612IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7613 PCVMXVEXITINFO pExitInfo)
7614{
7615 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7616 if (rcStrict == VINF_SUCCESS)
7617 {
7618 iemVmxVmreadSuccess(pVCpu, cbInstr);
7619 return VINF_SUCCESS;
7620 }
7621
7622 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7623 return rcStrict;
7624}
7625
7626
7627/**
7628 * VMREAD (32-bit register) instruction execution worker.
7629 *
7630 * @returns Strict VBox status code.
7631 * @param pVCpu The cross context virtual CPU structure.
7632 * @param cbInstr The instruction length in bytes.
7633 * @param pu32Dst Where to store the VMCS field's value.
7634 * @param u32VmcsField The VMCS field.
7635 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7636 * NULL.
7637 */
7638IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7639 PCVMXVEXITINFO pExitInfo)
7640{
7641 uint64_t u64Dst;
7642 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7643 if (rcStrict == VINF_SUCCESS)
7644 {
7645 *pu32Dst = u64Dst;
7646 iemVmxVmreadSuccess(pVCpu, cbInstr);
7647 return VINF_SUCCESS;
7648 }
7649
7650 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7651 return rcStrict;
7652}
7653
7654
7655/**
7656 * VMREAD (memory) instruction execution worker.
7657 *
7658 * @returns Strict VBox status code.
7659 * @param pVCpu The cross context virtual CPU structure.
7660 * @param cbInstr The instruction length in bytes.
7661 * @param iEffSeg The effective segment register to use with @a u64Val.
7662 * Pass UINT8_MAX if it is a register access.
7663 * @param GCPtrDst The guest linear address to store the VMCS field's
7664 * value.
7665 * @param u64VmcsField The VMCS field.
7666 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7667 * NULL.
7668 */
7669IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7670 PCVMXVEXITINFO pExitInfo)
7671{
7672 uint64_t u64Dst;
7673 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7674 if (rcStrict == VINF_SUCCESS)
7675 {
7676 /*
7677 * Write the VMCS field's value to the location specified in guest-memory.
7678 */
7679 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7680 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7681 else
7682 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7683 if (rcStrict == VINF_SUCCESS)
7684 {
7685 iemVmxVmreadSuccess(pVCpu, cbInstr);
7686 return VINF_SUCCESS;
7687 }
7688
7689 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7690 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7691 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7692 return rcStrict;
7693 }
7694
7695 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7696 return rcStrict;
7697}
7698
7699
7700/**
7701 * VMWRITE instruction execution worker that does not perform any validation
7702 * checks.
7703 *
7704 * Callers are expected to have performed the necessary checks and to ensure the
7705 * VMWRITE will succeed.
7706 *
7707 * @param pVmcs Pointer to the virtual VMCS.
7708 * @param u64Val The value to write.
7709 * @param u64VmcsField The VMCS field.
7710 *
7711 * @remarks May be called with interrupts disabled.
7712 */
7713IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7714{
7715 VMXVMCSFIELD VmcsField;
7716 VmcsField.u = u64VmcsField;
7717 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7718 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7719 uint8_t const uWidthType = (uWidth << 2) | uType;
7720 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7721 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7722 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7723 Assert(offField < VMX_V_VMCS_SIZE);
7724 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7725
7726 /*
7727 * Write the VMCS component based on the field's effective width.
7728 *
7729 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7730 * indicates high bits (little endian).
7731 */
7732 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7733 uint8_t *pbField = pbVmcs + offField;
7734 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7735 switch (uEffWidth)
7736 {
7737 case VMX_VMCSFIELD_WIDTH_64BIT:
7738 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7739 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7740 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7741 }
7742}
7743
7744
7745/**
7746 * VMWRITE instruction execution worker.
7747 *
7748 * @returns Strict VBox status code.
7749 * @param pVCpu The cross context virtual CPU structure.
7750 * @param cbInstr The instruction length in bytes.
7751 * @param iEffSeg The effective segment register to use with @a u64Val.
7752 * Pass UINT8_MAX if it is a register access.
7753 * @param u64Val The value to write (or guest linear address to the
7754 * value), @a iEffSeg will indicate if it's a memory
7755 * operand.
7756 * @param u64VmcsField The VMCS field.
7757 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7758 * NULL.
7759 */
7760IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7761 PCVMXVEXITINFO pExitInfo)
7762{
7763 /* Nested-guest intercept. */
7764 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7765 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7766 {
7767 if (pExitInfo)
7768 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7769 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7770 }
7771
7772 /* CPL. */
7773 if (pVCpu->iem.s.uCpl == 0)
7774 { /* likely */ }
7775 else
7776 {
7777 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7778 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7779 return iemRaiseGeneralProtectionFault0(pVCpu);
7780 }
7781
7782 /* VMCS pointer in root mode. */
7783 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7784 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7785 { /* likely */ }
7786 else
7787 {
7788 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7789 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7790 iemVmxVmFailInvalid(pVCpu);
7791 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7792 return VINF_SUCCESS;
7793 }
7794
7795 /* VMCS-link pointer in non-root mode. */
7796 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7797 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7798 { /* likely */ }
7799 else
7800 {
7801 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7802 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7803 iemVmxVmFailInvalid(pVCpu);
7804 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7805 return VINF_SUCCESS;
7806 }
7807
7808 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7809 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7810 if (!fIsRegOperand)
7811 {
7812 /* Read the value from the specified guest memory location. */
7813 VBOXSTRICTRC rcStrict;
7814 RTGCPTR const GCPtrVal = u64Val;
7815 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7816 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7817 else
7818 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7819 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7820 {
7821 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7822 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7823 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7824 return rcStrict;
7825 }
7826 }
7827 else
7828 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7829
7830 /* Supported VMCS field. */
7831 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7832 { /* likely */ }
7833 else
7834 {
7835 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7836 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7837 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7838 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7839 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7840 return VINF_SUCCESS;
7841 }
7842
7843 /* Read-only VMCS field. */
7844 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7845 if ( !fIsFieldReadOnly
7846 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7847 { /* likely */ }
7848 else
7849 {
7850 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7851 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7852 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7853 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7854 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7855 return VINF_SUCCESS;
7856 }
7857
7858 /*
7859 * Write to the current or shadow VMCS.
7860 */
7861 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7862 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7863 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7864 : pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7865 Assert(pVmcs);
7866 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7867
7868 /* Notify HM that the VMCS content might have changed. */
7869 if (!fInVmxNonRootMode)
7870 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7871
7872 iemVmxVmSucceed(pVCpu);
7873 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7874 return VINF_SUCCESS;
7875}
7876
7877
7878/**
7879 * VMCLEAR instruction execution worker.
7880 *
7881 * @returns Strict VBox status code.
7882 * @param pVCpu The cross context virtual CPU structure.
7883 * @param cbInstr The instruction length in bytes.
7884 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7885 * @param GCPtrVmcs The linear address of the VMCS pointer.
7886 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7887 *
7888 * @remarks Common VMX instruction checks are already expected to by the caller,
7889 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7890 */
7891IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7892 PCVMXVEXITINFO pExitInfo)
7893{
7894 /* Nested-guest intercept. */
7895 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7896 {
7897 if (pExitInfo)
7898 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7899 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7900 }
7901
7902 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7903
7904 /* CPL. */
7905 if (pVCpu->iem.s.uCpl == 0)
7906 { /* likely */ }
7907 else
7908 {
7909 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7910 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7911 return iemRaiseGeneralProtectionFault0(pVCpu);
7912 }
7913
7914 /* Get the VMCS pointer from the location specified by the source memory operand. */
7915 RTGCPHYS GCPhysVmcs;
7916 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7917 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
7918 { /* likely */ }
7919 else
7920 {
7921 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7922 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
7923 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
7924 return rcStrict;
7925 }
7926
7927 /* VMCS pointer alignment. */
7928 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
7929 { /* likely */ }
7930 else
7931 {
7932 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
7933 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
7934 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7935 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7936 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7937 return VINF_SUCCESS;
7938 }
7939
7940 /* VMCS physical-address width limits. */
7941 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
7942 { /* likely */ }
7943 else
7944 {
7945 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7946 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
7947 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7948 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7949 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7950 return VINF_SUCCESS;
7951 }
7952
7953 /* VMCS is not the VMXON region. */
7954 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7955 { /* likely */ }
7956 else
7957 {
7958 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7959 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
7960 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7961 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
7962 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7963 return VINF_SUCCESS;
7964 }
7965
7966 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7967 restriction imposed by our implementation. */
7968 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7969 { /* likely */ }
7970 else
7971 {
7972 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
7973 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
7974 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7975 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7976 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7977 return VINF_SUCCESS;
7978 }
7979
7980 /*
7981 * VMCLEAR allows committing and clearing any valid VMCS pointer.
7982 *
7983 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
7984 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
7985 * to 'clear'.
7986 */
7987 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
7988 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
7989 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
7990 {
7991 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
7992 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
7993 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
7994 }
7995 else
7996 {
7997 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
7998 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
7999 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8000 if (RT_FAILURE(rcStrict))
8001 return rcStrict;
8002 }
8003
8004 iemVmxVmSucceed(pVCpu);
8005 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8006 return VINF_SUCCESS;
8007}
8008
8009
8010/**
8011 * VMPTRST instruction execution worker.
8012 *
8013 * @returns Strict VBox status code.
8014 * @param pVCpu The cross context virtual CPU structure.
8015 * @param cbInstr The instruction length in bytes.
8016 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8017 * @param GCPtrVmcs The linear address of where to store the current VMCS
8018 * pointer.
8019 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8020 *
8021 * @remarks Common VMX instruction checks are already expected to by the caller,
8022 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8023 */
8024IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8025 PCVMXVEXITINFO pExitInfo)
8026{
8027 /* Nested-guest intercept. */
8028 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8029 {
8030 if (pExitInfo)
8031 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8032 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8033 }
8034
8035 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8036
8037 /* CPL. */
8038 if (pVCpu->iem.s.uCpl == 0)
8039 { /* likely */ }
8040 else
8041 {
8042 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8043 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8044 return iemRaiseGeneralProtectionFault0(pVCpu);
8045 }
8046
8047 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8048 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8049 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8050 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8051 {
8052 iemVmxVmSucceed(pVCpu);
8053 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8054 return rcStrict;
8055 }
8056
8057 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8058 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8059 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8060 return rcStrict;
8061}
8062
8063
8064/**
8065 * VMPTRLD instruction execution worker.
8066 *
8067 * @returns Strict VBox status code.
8068 * @param pVCpu The cross context virtual CPU structure.
8069 * @param cbInstr The instruction length in bytes.
8070 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8071 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8072 *
8073 * @remarks Common VMX instruction checks are already expected to by the caller,
8074 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8075 */
8076IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8077 PCVMXVEXITINFO pExitInfo)
8078{
8079 /* Nested-guest intercept. */
8080 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8081 {
8082 if (pExitInfo)
8083 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8084 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8085 }
8086
8087 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8088
8089 /* CPL. */
8090 if (pVCpu->iem.s.uCpl == 0)
8091 { /* likely */ }
8092 else
8093 {
8094 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8095 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8096 return iemRaiseGeneralProtectionFault0(pVCpu);
8097 }
8098
8099 /* Get the VMCS pointer from the location specified by the source memory operand. */
8100 RTGCPHYS GCPhysVmcs;
8101 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8102 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8103 { /* likely */ }
8104 else
8105 {
8106 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8107 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8108 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8109 return rcStrict;
8110 }
8111
8112 /* VMCS pointer alignment. */
8113 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8114 { /* likely */ }
8115 else
8116 {
8117 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8118 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8119 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8120 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8121 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8122 return VINF_SUCCESS;
8123 }
8124
8125 /* VMCS physical-address width limits. */
8126 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8127 { /* likely */ }
8128 else
8129 {
8130 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8131 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8132 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8133 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8134 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8135 return VINF_SUCCESS;
8136 }
8137
8138 /* VMCS is not the VMXON region. */
8139 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8140 { /* likely */ }
8141 else
8142 {
8143 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8144 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8145 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8146 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8147 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8148 return VINF_SUCCESS;
8149 }
8150
8151 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8152 restriction imposed by our implementation. */
8153 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8154 { /* likely */ }
8155 else
8156 {
8157 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8158 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8159 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8160 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8161 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8162 return VINF_SUCCESS;
8163 }
8164
8165 /* Read just the VMCS revision from the VMCS. */
8166 VMXVMCSREVID VmcsRevId;
8167 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8168 if (RT_SUCCESS(rc))
8169 { /* likely */ }
8170 else
8171 {
8172 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8173 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8174 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8175 return rc;
8176 }
8177
8178 /*
8179 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8180 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8181 */
8182 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8183 && ( !VmcsRevId.n.fIsShadowVmcs
8184 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8185 { /* likely */ }
8186 else
8187 {
8188 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8189 {
8190 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8191 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8192 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8193 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8194 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8195 return VINF_SUCCESS;
8196 }
8197
8198 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8199 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8200 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8201 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8202 return VINF_SUCCESS;
8203 }
8204
8205 /*
8206 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8207 * the cache of an existing, current VMCS back to guest memory before loading a new,
8208 * different current VMCS.
8209 */
8210 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8211 {
8212 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8213 {
8214 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8215 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8216 }
8217
8218 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8219 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8220 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8221 if (RT_SUCCESS(rc))
8222 {
8223 /* Notify HM that a new, current VMCS is loaded. */
8224 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8225 }
8226 else
8227 {
8228 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8229 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8230 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8231 return rc;
8232 }
8233 }
8234
8235 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8236 iemVmxVmSucceed(pVCpu);
8237 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8238 return VINF_SUCCESS;
8239}
8240
8241
8242/**
8243 * INVVPID instruction execution worker.
8244 *
8245 * @returns Strict VBox status code.
8246 * @param pVCpu The cross context virtual CPU structure.
8247 * @param cbInstr The instruction length in bytes.
8248 * @param iEffSeg The segment of the invvpid descriptor.
8249 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8250 * @param u64InvvpidType The invalidation type.
8251 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8252 * NULL.
8253 *
8254 * @remarks Common VMX instruction checks are already expected to by the caller,
8255 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8256 */
8257IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8258 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8259{
8260 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8261 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8262 return iemRaiseUndefinedOpcode(pVCpu);
8263
8264 /* Nested-guest intercept. */
8265 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8266 {
8267 if (pExitInfo)
8268 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8269 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8270 }
8271
8272 /* CPL. */
8273 if (pVCpu->iem.s.uCpl != 0)
8274 {
8275 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8276 return iemRaiseGeneralProtectionFault0(pVCpu);
8277 }
8278
8279 /*
8280 * Validate INVVPID invalidation type.
8281 *
8282 * The instruction specifies exactly ONE of the supported invalidation types.
8283 *
8284 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8285 * supported. In theory, it's possible for a CPU to not support flushing individual
8286 * addresses but all the other types or any other combination. We do not take any
8287 * shortcuts here by assuming the types we currently expose to the guest.
8288 */
8289 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8290 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8291 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8292 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8293 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8294 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8295 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8296 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8297 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8298 { /* likely */ }
8299 else
8300 {
8301 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8302 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8303 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8304 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8305 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8306 return VINF_SUCCESS;
8307 }
8308
8309 /*
8310 * Fetch the invvpid descriptor from guest memory.
8311 */
8312 RTUINT128U uDesc;
8313 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8314 if (rcStrict == VINF_SUCCESS)
8315 {
8316 /*
8317 * Validate the descriptor.
8318 */
8319 if (uDesc.s.Lo > 0xfff)
8320 {
8321 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8322 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8323 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8324 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8325 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8326 return VINF_SUCCESS;
8327 }
8328
8329 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8330 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8331 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8332 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8333 switch (u64InvvpidType)
8334 {
8335 case VMXTLBFLUSHVPID_INDIV_ADDR:
8336 {
8337 if (uVpid != 0)
8338 {
8339 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8340 {
8341 /* Invalidate mappings for the linear address tagged with VPID. */
8342 /** @todo PGM support for VPID? Currently just flush everything. */
8343 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8344 iemVmxVmSucceed(pVCpu);
8345 }
8346 else
8347 {
8348 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8349 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8350 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8351 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8352 }
8353 }
8354 else
8355 {
8356 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8357 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8358 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8359 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8360 }
8361 break;
8362 }
8363
8364 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8365 {
8366 if (uVpid != 0)
8367 {
8368 /* Invalidate all mappings with VPID. */
8369 /** @todo PGM support for VPID? Currently just flush everything. */
8370 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8371 iemVmxVmSucceed(pVCpu);
8372 }
8373 else
8374 {
8375 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8376 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8377 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8378 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8379 }
8380 break;
8381 }
8382
8383 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8384 {
8385 /* Invalidate all mappings with non-zero VPIDs. */
8386 /** @todo PGM support for VPID? Currently just flush everything. */
8387 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8388 iemVmxVmSucceed(pVCpu);
8389 break;
8390 }
8391
8392 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8393 {
8394 if (uVpid != 0)
8395 {
8396 /* Invalidate all mappings with VPID except global translations. */
8397 /** @todo PGM support for VPID? Currently just flush everything. */
8398 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8399 iemVmxVmSucceed(pVCpu);
8400 }
8401 else
8402 {
8403 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8404 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8405 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8406 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8407 }
8408 break;
8409 }
8410 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8411 }
8412 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8413 }
8414 return rcStrict;
8415}
8416
8417
8418/**
8419 * VMXON instruction execution worker.
8420 *
8421 * @returns Strict VBox status code.
8422 * @param pVCpu The cross context virtual CPU structure.
8423 * @param cbInstr The instruction length in bytes.
8424 * @param iEffSeg The effective segment register to use with @a
8425 * GCPtrVmxon.
8426 * @param GCPtrVmxon The linear address of the VMXON pointer.
8427 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8428 *
8429 * @remarks Common VMX instruction checks are already expected to by the caller,
8430 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8431 */
8432IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8433 PCVMXVEXITINFO pExitInfo)
8434{
8435 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8436 {
8437 /* CPL. */
8438 if (pVCpu->iem.s.uCpl == 0)
8439 { /* likely */ }
8440 else
8441 {
8442 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8443 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8444 return iemRaiseGeneralProtectionFault0(pVCpu);
8445 }
8446
8447 /* A20M (A20 Masked) mode. */
8448 if (PGMPhysIsA20Enabled(pVCpu))
8449 { /* likely */ }
8450 else
8451 {
8452 Log(("vmxon: A20M mode -> #GP(0)\n"));
8453 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8454 return iemRaiseGeneralProtectionFault0(pVCpu);
8455 }
8456
8457 /* CR0. */
8458 {
8459 /* CR0 MB1 bits. */
8460 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8461 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8462 { /* likely */ }
8463 else
8464 {
8465 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8466 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8467 return iemRaiseGeneralProtectionFault0(pVCpu);
8468 }
8469
8470 /* CR0 MBZ bits. */
8471 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8472 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8473 { /* likely */ }
8474 else
8475 {
8476 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8477 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8478 return iemRaiseGeneralProtectionFault0(pVCpu);
8479 }
8480 }
8481
8482 /* CR4. */
8483 {
8484 /* CR4 MB1 bits. */
8485 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8486 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8487 { /* likely */ }
8488 else
8489 {
8490 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8491 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8492 return iemRaiseGeneralProtectionFault0(pVCpu);
8493 }
8494
8495 /* CR4 MBZ bits. */
8496 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8497 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8498 { /* likely */ }
8499 else
8500 {
8501 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8502 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8503 return iemRaiseGeneralProtectionFault0(pVCpu);
8504 }
8505 }
8506
8507 /* Feature control MSR's LOCK and VMXON bits. */
8508 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8509 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8510 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8511 { /* likely */ }
8512 else
8513 {
8514 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8515 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8516 return iemRaiseGeneralProtectionFault0(pVCpu);
8517 }
8518
8519 /* Get the VMXON pointer from the location specified by the source memory operand. */
8520 RTGCPHYS GCPhysVmxon;
8521 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8522 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8523 { /* likely */ }
8524 else
8525 {
8526 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8527 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8528 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8529 return rcStrict;
8530 }
8531
8532 /* VMXON region pointer alignment. */
8533 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8534 { /* likely */ }
8535 else
8536 {
8537 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8538 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8539 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8540 iemVmxVmFailInvalid(pVCpu);
8541 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8542 return VINF_SUCCESS;
8543 }
8544
8545 /* VMXON physical-address width limits. */
8546 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8547 { /* likely */ }
8548 else
8549 {
8550 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8551 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8552 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8553 iemVmxVmFailInvalid(pVCpu);
8554 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8555 return VINF_SUCCESS;
8556 }
8557
8558 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8559 restriction imposed by our implementation. */
8560 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8561 { /* likely */ }
8562 else
8563 {
8564 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8565 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8566 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8567 iemVmxVmFailInvalid(pVCpu);
8568 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8569 return VINF_SUCCESS;
8570 }
8571
8572 /* Read the VMCS revision ID from the VMXON region. */
8573 VMXVMCSREVID VmcsRevId;
8574 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8575 if (RT_SUCCESS(rc))
8576 { /* likely */ }
8577 else
8578 {
8579 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8580 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8581 return rc;
8582 }
8583
8584 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8585 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8586 { /* likely */ }
8587 else
8588 {
8589 /* Revision ID mismatch. */
8590 if (!VmcsRevId.n.fIsShadowVmcs)
8591 {
8592 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8593 VmcsRevId.n.u31RevisionId));
8594 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8595 iemVmxVmFailInvalid(pVCpu);
8596 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8597 return VINF_SUCCESS;
8598 }
8599
8600 /* Shadow VMCS disallowed. */
8601 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8602 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8603 iemVmxVmFailInvalid(pVCpu);
8604 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8605 return VINF_SUCCESS;
8606 }
8607
8608 /*
8609 * Record that we're in VMX operation, block INIT, block and disable A20M.
8610 */
8611 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8612 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8613 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8614
8615 /* Clear address-range monitoring. */
8616 EMMonitorWaitClear(pVCpu);
8617 /** @todo NSTVMX: Intel PT. */
8618
8619 iemVmxVmSucceed(pVCpu);
8620 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8621 return VINF_SUCCESS;
8622 }
8623 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8624 {
8625 /* Nested-guest intercept. */
8626 if (pExitInfo)
8627 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8628 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8629 }
8630
8631 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8632
8633 /* CPL. */
8634 if (pVCpu->iem.s.uCpl > 0)
8635 {
8636 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8637 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8638 return iemRaiseGeneralProtectionFault0(pVCpu);
8639 }
8640
8641 /* VMXON when already in VMX root mode. */
8642 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8643 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8644 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8645 return VINF_SUCCESS;
8646}
8647
8648
8649/**
8650 * Implements 'VMXOFF'.
8651 *
8652 * @remarks Common VMX instruction checks are already expected to by the caller,
8653 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8654 */
8655IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8656{
8657 /* Nested-guest intercept. */
8658 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8659 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8660
8661 /* CPL. */
8662 if (pVCpu->iem.s.uCpl == 0)
8663 { /* likely */ }
8664 else
8665 {
8666 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8667 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8668 return iemRaiseGeneralProtectionFault0(pVCpu);
8669 }
8670
8671 /* Dual monitor treatment of SMIs and SMM. */
8672 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8673 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8674 { /* likely */ }
8675 else
8676 {
8677 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8678 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8679 return VINF_SUCCESS;
8680 }
8681
8682 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8683 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8684 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8685
8686 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8687 { /** @todo NSTVMX: Unblock SMI. */ }
8688
8689 EMMonitorWaitClear(pVCpu);
8690 /** @todo NSTVMX: Unblock and enable A20M. */
8691
8692 iemVmxVmSucceed(pVCpu);
8693 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8694 return VINF_SUCCESS;
8695}
8696
8697
8698/**
8699 * Implements 'VMXON'.
8700 */
8701IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8702{
8703 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8704}
8705
8706
8707/**
8708 * Implements 'VMLAUNCH'.
8709 */
8710IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8711{
8712 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8713}
8714
8715
8716/**
8717 * Implements 'VMRESUME'.
8718 */
8719IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8720{
8721 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8722}
8723
8724
8725/**
8726 * Implements 'VMPTRLD'.
8727 */
8728IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8729{
8730 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8731}
8732
8733
8734/**
8735 * Implements 'VMPTRST'.
8736 */
8737IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8738{
8739 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8740}
8741
8742
8743/**
8744 * Implements 'VMCLEAR'.
8745 */
8746IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8747{
8748 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8749}
8750
8751
8752/**
8753 * Implements 'VMWRITE' register.
8754 */
8755IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8756{
8757 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8758}
8759
8760
8761/**
8762 * Implements 'VMWRITE' memory.
8763 */
8764IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8765{
8766 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8767}
8768
8769
8770/**
8771 * Implements 'VMREAD' register (64-bit).
8772 */
8773IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8774{
8775 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8776}
8777
8778
8779/**
8780 * Implements 'VMREAD' register (32-bit).
8781 */
8782IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8783{
8784 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8785}
8786
8787
8788/**
8789 * Implements 'VMREAD' memory, 64-bit register.
8790 */
8791IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8792{
8793 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8794}
8795
8796
8797/**
8798 * Implements 'VMREAD' memory, 32-bit register.
8799 */
8800IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8801{
8802 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8803}
8804
8805
8806/**
8807 * Implements 'INVVPID'.
8808 */
8809IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8810{
8811 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8812}
8813
8814
8815/**
8816 * Implements VMX's implementation of PAUSE.
8817 */
8818IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8819{
8820 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8821 {
8822 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8823 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8824 return rcStrict;
8825 }
8826
8827 /*
8828 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8829 * a VM-exit, the instruction operates normally.
8830 */
8831 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8832 return VINF_SUCCESS;
8833}
8834
8835#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8836
8837
8838/**
8839 * Implements 'VMCALL'.
8840 */
8841IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8842{
8843#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8844 /* Nested-guest intercept. */
8845 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8846 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8847#endif
8848
8849 /* Join forces with vmmcall. */
8850 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8851}
8852
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