VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 91323

Last change on this file since 91323 was 91323, checked in by vboxsync, 3 years ago

VMM: bugref:10106 Fixed IA32_FEATURE_CONTROL MSR reported to the guest.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 91323 2021-09-22 10:04:56Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_EPT_VIOLATION
177 * VMX_EXIT_EPT_MISCONFIG
178 * VMX_EXIT_INVEPT
179 * VMX_EXIT_RDRAND
180 * VMX_EXIT_VMFUNC
181 * VMX_EXIT_ENCLS
182 * VMX_EXIT_RDSEED
183 * VMX_EXIT_PML_FULL
184 * VMX_EXIT_XSAVES
185 * VMX_EXIT_XRSTORS
186 */
187/**
188 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
189 *
190 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
191 * second dimension is the Index, see VMXVMCSFIELD.
192 */
193uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
194{
195 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
196 {
197 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
198 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
199 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
200 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
201 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 27 */ UINT16_MAX,
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 26-27 */ UINT16_MAX, UINT16_MAX
227 },
228 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
233 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
234 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
235 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
236 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
237 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
239 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
240 },
241 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
242 {
243 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
244 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
245 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
246 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
247 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
248 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
249 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
250 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
251 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
252 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
253 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
254 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
255 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
256 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
257 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
258 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
259 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
260 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
261 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
262 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
263 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
264 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
265 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
266 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
267 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
268 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
269 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
270 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
271 },
272 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
273 {
274 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
275 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
276 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
277 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
278 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
279 },
280 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
281 {
282 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
283 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
284 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
285 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
286 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
287 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
288 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
289 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
290 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
291 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
292 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
293 /* 11 */ UINT16_MAX,
294 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
295 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
296 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
297 },
298 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
299 {
300 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
301 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
302 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
303 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
304 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
307 },
308 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
309 {
310 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
311 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
312 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
313 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
314 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
315 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
316 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
317 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
318 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
319 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
320 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
321 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
322 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
323 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
324 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
325 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
326 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
327 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
328 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
329 /* 26-27 */ UINT16_MAX, UINT16_MAX
330 },
331 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
332 {
333 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
334 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
335 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
336 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
337 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
338 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
339 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
340 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
341 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
342 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
343 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
344 },
345 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
346 {
347 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
348 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
349 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
350 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
351 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
352 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
353 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
354 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
355 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
356 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
357 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
358 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
359 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
360 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
361 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
362 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
363 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
364 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
365 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
366 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
367 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
368 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
369 /* 22 */ UINT16_MAX,
370 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
371 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
376 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
377 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
378 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
379 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
380 },
381 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
382 {
383 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
384 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
385 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
386 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
387 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
388 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
389 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
390 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
391 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
392 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
393 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
394 },
395 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
396 {
397 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
398 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
399 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
400 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
401 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
402 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
403 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
404 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
405 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
406 },
407 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
408 {
409 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
410 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
411 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
412 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
413 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
414 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
415 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
416 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
417 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
418 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
419 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
420 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
421 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
422 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
423 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
424 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
425 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
426 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
427 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
428 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
429 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
430 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
431 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
432 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
433 },
434 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
435 {
436 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
437 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
438 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
439 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
440 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
441 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
442 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
443 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
444 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
445 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
446 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
447 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
448 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
449 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
450 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
451 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
452 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
453 }
454};
455
456
457/**
458 * Gets a host selector from the VMCS.
459 *
460 * @param pVmcs Pointer to the virtual VMCS.
461 * @param iSelReg The index of the segment register (X86_SREG_XXX).
462 */
463DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
464{
465 Assert(iSegReg < X86_SREG_COUNT);
466 RTSEL HostSel;
467 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
468 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
469 uint8_t const uWidthType = (uWidth << 2) | uType;
470 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
471 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
472 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
473 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
474 uint8_t const *pbField = pbVmcs + offField;
475 HostSel = *(uint16_t *)pbField;
476 return HostSel;
477}
478
479
480/**
481 * Sets a guest segment register in the VMCS.
482 *
483 * @param pVmcs Pointer to the virtual VMCS.
484 * @param iSegReg The index of the segment register (X86_SREG_XXX).
485 * @param pSelReg Pointer to the segment register.
486 */
487IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
488{
489 Assert(pSelReg);
490 Assert(iSegReg < X86_SREG_COUNT);
491
492 /* Selector. */
493 {
494 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
495 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
496 uint8_t const uWidthType = (uWidth << 2) | uType;
497 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
498 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
499 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
500 uint8_t *pbVmcs = (uint8_t *)pVmcs;
501 uint8_t *pbField = pbVmcs + offField;
502 *(uint16_t *)pbField = pSelReg->Sel;
503 }
504
505 /* Limit. */
506 {
507 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
508 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
509 uint8_t const uWidthType = (uWidth << 2) | uType;
510 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
511 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
512 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
513 uint8_t *pbVmcs = (uint8_t *)pVmcs;
514 uint8_t *pbField = pbVmcs + offField;
515 *(uint32_t *)pbField = pSelReg->u32Limit;
516 }
517
518 /* Base. */
519 {
520 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
521 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
522 uint8_t const uWidthType = (uWidth << 2) | uType;
523 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
524 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
525 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
526 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
527 uint8_t const *pbField = pbVmcs + offField;
528 *(uint64_t *)pbField = pSelReg->u64Base;
529 }
530
531 /* Attributes. */
532 {
533 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
534 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
535 | X86DESCATTR_UNUSABLE;
536 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
537 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
538 uint8_t const uWidthType = (uWidth << 2) | uType;
539 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
540 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
541 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
542 uint8_t *pbVmcs = (uint8_t *)pVmcs;
543 uint8_t *pbField = pbVmcs + offField;
544 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
545 }
546}
547
548
549/**
550 * Gets a guest segment register from the VMCS.
551 *
552 * @returns VBox status code.
553 * @param pVmcs Pointer to the virtual VMCS.
554 * @param iSegReg The index of the segment register (X86_SREG_XXX).
555 * @param pSelReg Where to store the segment register (only updated when
556 * VINF_SUCCESS is returned).
557 *
558 * @remarks Warning! This does not validate the contents of the retrieved segment
559 * register.
560 */
561IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
562{
563 Assert(pSelReg);
564 Assert(iSegReg < X86_SREG_COUNT);
565
566 /* Selector. */
567 uint16_t u16Sel;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u16Sel = *(uint16_t *)pbField;
578 }
579
580 /* Limit. */
581 uint32_t u32Limit;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u32Limit = *(uint32_t *)pbField;
592 }
593
594 /* Base. */
595 uint64_t u64Base;
596 {
597 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
598 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
599 uint8_t const uWidthType = (uWidth << 2) | uType;
600 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
601 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
602 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
603 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
604 uint8_t const *pbField = pbVmcs + offField;
605 u64Base = *(uint64_t *)pbField;
606 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
607 }
608
609 /* Attributes. */
610 uint32_t u32Attr;
611 {
612 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
613 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
614 uint8_t const uWidthType = (uWidth << 2) | uType;
615 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
616 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
617 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
618 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
619 uint8_t const *pbField = pbVmcs + offField;
620 u32Attr = *(uint32_t *)pbField;
621 }
622
623 pSelReg->Sel = u16Sel;
624 pSelReg->ValidSel = u16Sel;
625 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
626 pSelReg->u32Limit = u32Limit;
627 pSelReg->u64Base = u64Base;
628 pSelReg->Attr.u = u32Attr;
629 return VINF_SUCCESS;
630}
631
632
633/**
634 * Converts an IEM exception event type to a VMX event type.
635 *
636 * @returns The VMX event type.
637 * @param uVector The interrupt / exception vector.
638 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
639 */
640DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
641{
642 /* Paranoia (callers may use these interchangeably). */
643 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
644 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
645 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
646 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
647 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
648 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
649 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
650 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
651 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
652 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
653 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
654 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
655
656 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
657 {
658 if (uVector == X86_XCPT_NMI)
659 return VMX_EXIT_INT_INFO_TYPE_NMI;
660 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
661 }
662
663 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
664 {
665 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
666 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
667 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
668 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
669 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
670 }
671
672 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
673 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
674}
675
676
677/**
678 * Sets the Exit qualification VMCS field.
679 *
680 * @param pVCpu The cross context virtual CPU structure.
681 * @param u64ExitQual The Exit qualification.
682 */
683DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
684{
685 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
686}
687
688
689/**
690 * Sets the VM-exit interruption information field.
691 *
692 * @param pVCpu The cross context virtual CPU structure.
693 * @param uExitIntInfo The VM-exit interruption information.
694 */
695DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
696{
697 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
698}
699
700
701/**
702 * Sets the VM-exit interruption error code.
703 *
704 * @param pVCpu The cross context virtual CPU structure.
705 * @param uErrCode The error code.
706 */
707DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
708{
709 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
710}
711
712
713/**
714 * Sets the IDT-vectoring information field.
715 *
716 * @param pVCpu The cross context virtual CPU structure.
717 * @param uIdtVectorInfo The IDT-vectoring information.
718 */
719DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
720{
721 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
722}
723
724
725/**
726 * Sets the IDT-vectoring error code field.
727 *
728 * @param pVCpu The cross context virtual CPU structure.
729 * @param uErrCode The error code.
730 */
731DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
732{
733 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
734}
735
736
737/**
738 * Sets the VM-exit guest-linear address VMCS field.
739 *
740 * @param pVCpu The cross context virtual CPU structure.
741 * @param uGuestLinearAddr The VM-exit guest-linear address.
742 */
743DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
744{
745 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
746}
747
748
749/**
750 * Sets the VM-exit guest-physical address VMCS field.
751 *
752 * @param pVCpu The cross context virtual CPU structure.
753 * @param uGuestPhysAddr The VM-exit guest-physical address.
754 */
755DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
756{
757 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
758}
759
760
761/**
762 * Sets the VM-exit instruction length VMCS field.
763 *
764 * @param pVCpu The cross context virtual CPU structure.
765 * @param cbInstr The VM-exit instruction length in bytes.
766 *
767 * @remarks Callers may clear this field to 0. Hence, this function does not check
768 * the validity of the instruction length.
769 */
770DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
771{
772 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
773}
774
775
776/**
777 * Sets the VM-exit instruction info. VMCS field.
778 *
779 * @param pVCpu The cross context virtual CPU structure.
780 * @param uExitInstrInfo The VM-exit instruction information.
781 */
782DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
783{
784 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
785}
786
787
788/**
789 * Sets the guest pending-debug exceptions field.
790 *
791 * @param pVCpu The cross context virtual CPU structure.
792 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
793 */
794DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
795{
796 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
797 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
798}
799
800
801/**
802 * Implements VMSucceed for VMX instruction success.
803 *
804 * @param pVCpu The cross context virtual CPU structure.
805 */
806DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
807{
808 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
809}
810
811
812/**
813 * Implements VMFailInvalid for VMX instruction failure.
814 *
815 * @param pVCpu The cross context virtual CPU structure.
816 */
817DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
818{
819 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
820}
821
822
823/**
824 * Implements VMFail for VMX instruction failure.
825 *
826 * @param pVCpu The cross context virtual CPU structure.
827 * @param enmInsErr The VM instruction error.
828 */
829DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
830{
831 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
832}
833
834
835/**
836 * Checks if the given auto-load/store MSR area count is valid for the
837 * implementation.
838 *
839 * @returns @c true if it's within the valid limit, @c false otherwise.
840 * @param pVCpu The cross context virtual CPU structure.
841 * @param uMsrCount The MSR area count to check.
842 */
843DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
844{
845 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
846 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
847 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
848 if (uMsrCount <= cMaxSupportedMsrs)
849 return true;
850 return false;
851}
852
853
854/**
855 * Flushes the current VMCS contents back to guest memory.
856 *
857 * @returns VBox status code.
858 * @param pVCpu The cross context virtual CPU structure.
859 */
860DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
861{
862 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
863 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
864 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
865 return rc;
866}
867
868
869/**
870 * Populates the current VMCS contents from guest memory.
871 *
872 * @returns VBox status code.
873 * @param pVCpu The cross context virtual CPU structure.
874 */
875DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
876{
877 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
879 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
880 return rc;
881}
882
883
884/**
885 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
886 *
887 * @param pVCpu The cross context virtual CPU structure.
888 */
889DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
890{
891 iemVmxVmSucceed(pVCpu);
892 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
893}
894
895
896/**
897 * Gets the instruction diagnostic for segment base checks during VM-entry of a
898 * nested-guest.
899 *
900 * @param iSegReg The segment index (X86_SREG_XXX).
901 */
902IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
903{
904 switch (iSegReg)
905 {
906 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
907 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
908 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
909 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
910 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
911 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
912 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
913 }
914}
915
916
917/**
918 * Gets the instruction diagnostic for segment base checks during VM-entry of a
919 * nested-guest that is in Virtual-8086 mode.
920 *
921 * @param iSegReg The segment index (X86_SREG_XXX).
922 */
923IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
924{
925 switch (iSegReg)
926 {
927 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
928 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
929 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
930 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
931 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
932 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
933 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
934 }
935}
936
937
938/**
939 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
940 * nested-guest that is in Virtual-8086 mode.
941 *
942 * @param iSegReg The segment index (X86_SREG_XXX).
943 */
944IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
945{
946 switch (iSegReg)
947 {
948 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
949 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
950 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
951 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
952 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
953 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
954 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
955 }
956}
957
958
959/**
960 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
961 * nested-guest that is in Virtual-8086 mode.
962 *
963 * @param iSegReg The segment index (X86_SREG_XXX).
964 */
965IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
966{
967 switch (iSegReg)
968 {
969 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
970 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
971 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
972 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
973 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
974 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
975 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
976 }
977}
978
979
980/**
981 * Gets the instruction diagnostic for segment attributes reserved bits failure
982 * during VM-entry of a nested-guest.
983 *
984 * @param iSegReg The segment index (X86_SREG_XXX).
985 */
986IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
987{
988 switch (iSegReg)
989 {
990 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
991 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
992 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
993 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
994 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
995 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
996 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
997 }
998}
999
1000
1001/**
1002 * Gets the instruction diagnostic for segment attributes descriptor-type
1003 * (code/segment or system) failure during VM-entry of a nested-guest.
1004 *
1005 * @param iSegReg The segment index (X86_SREG_XXX).
1006 */
1007IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1008{
1009 switch (iSegReg)
1010 {
1011 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1012 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1013 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1014 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1015 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1016 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1017 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1018 }
1019}
1020
1021
1022/**
1023 * Gets the instruction diagnostic for segment attributes descriptor-type
1024 * (code/segment or system) failure during VM-entry of a nested-guest.
1025 *
1026 * @param iSegReg The segment index (X86_SREG_XXX).
1027 */
1028IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1029{
1030 switch (iSegReg)
1031 {
1032 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1033 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1034 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1035 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1036 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1037 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1038 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1039 }
1040}
1041
1042
1043/**
1044 * Gets the instruction diagnostic for segment attribute granularity failure during
1045 * VM-entry of a nested-guest.
1046 *
1047 * @param iSegReg The segment index (X86_SREG_XXX).
1048 */
1049IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1050{
1051 switch (iSegReg)
1052 {
1053 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1054 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1055 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1056 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1057 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1058 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1059 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1060 }
1061}
1062
1063/**
1064 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1065 * VM-entry of a nested-guest.
1066 *
1067 * @param iSegReg The segment index (X86_SREG_XXX).
1068 */
1069IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1070{
1071 switch (iSegReg)
1072 {
1073 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1074 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1075 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1076 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1077 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1078 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1079 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1080 }
1081}
1082
1083
1084/**
1085 * Gets the instruction diagnostic for segment attribute type accessed failure
1086 * during VM-entry of a nested-guest.
1087 *
1088 * @param iSegReg The segment index (X86_SREG_XXX).
1089 */
1090IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1091{
1092 switch (iSegReg)
1093 {
1094 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1095 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1096 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1097 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1098 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1099 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1100 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1101 }
1102}
1103
1104
1105/**
1106 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1107 * failure during VM-entry of a nested-guest.
1108 *
1109 * @param iSegReg The PDPTE entry index.
1110 */
1111IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1112{
1113 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1114 switch (iPdpte)
1115 {
1116 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1117 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1118 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1119 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1120 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1121 }
1122}
1123
1124
1125/**
1126 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1127 * failure during VM-exit of a nested-guest.
1128 *
1129 * @param iSegReg The PDPTE entry index.
1130 */
1131IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1132{
1133 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1134 switch (iPdpte)
1135 {
1136 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1137 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1138 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1139 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1140 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1141 }
1142}
1143
1144
1145/**
1146 * Saves the guest control registers, debug registers and some MSRs are part of
1147 * VM-exit.
1148 *
1149 * @param pVCpu The cross context virtual CPU structure.
1150 */
1151IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1152{
1153 /*
1154 * Saves the guest control registers, debug registers and some MSRs.
1155 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1156 */
1157 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1158
1159 /* Save control registers. */
1160 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1161 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1162 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1163
1164 /* Save SYSENTER CS, ESP, EIP. */
1165 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1166 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1167 {
1168 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1169 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1170 }
1171 else
1172 {
1173 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1174 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1175 }
1176
1177 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1178 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1179 {
1180 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1181 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1182 }
1183
1184 /* Save PAT MSR. */
1185 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1186 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1187
1188 /* Save EFER MSR. */
1189 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1190 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1191
1192 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1193 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1194
1195 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1196}
1197
1198
1199/**
1200 * Saves the guest force-flags in preparation of entering the nested-guest.
1201 *
1202 * @param pVCpu The cross context virtual CPU structure.
1203 */
1204IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1205{
1206 /* We shouldn't be called multiple times during VM-entry. */
1207 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1208
1209 /* MTF should not be set outside VMX non-root mode. */
1210 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1211
1212 /*
1213 * Preserve the required force-flags.
1214 *
1215 * We cache and clear force-flags that would affect the execution of the
1216 * nested-guest. Cached flags are then restored while returning to the guest
1217 * if necessary.
1218 *
1219 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1220 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1221 * instruction. Interrupt inhibition for any nested-guest instruction
1222 * is supplied by the guest-interruptibility state VMCS field and will
1223 * be set up as part of loading the guest state.
1224 *
1225 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1226 * successful VM-entry (due to invalid guest-state) need to continue
1227 * blocking NMIs if it was in effect before VM-entry.
1228 *
1229 * - MTF need not be preserved as it's used only in VMX non-root mode and
1230 * is supplied through the VM-execution controls.
1231 *
1232 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1233 * we will be able to generate interrupts that may cause VM-exits for
1234 * the nested-guest.
1235 */
1236 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1237}
1238
1239
1240/**
1241 * Restores the guest force-flags in preparation of exiting the nested-guest.
1242 *
1243 * @param pVCpu The cross context virtual CPU structure.
1244 */
1245IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1246{
1247 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1248 {
1249 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1250 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1251 }
1252}
1253
1254
1255/**
1256 * Perform a VMX transition updated PGM, IEM and CPUM.
1257 *
1258 * @param pVCpu The cross context virtual CPU structure.
1259 */
1260IEM_STATIC int iemVmxWorldSwitch(PVMCPUCC pVCpu)
1261{
1262 /*
1263 * Inform PGM about paging mode changes.
1264 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1265 * see comment in iemMemPageTranslateAndCheckAccess().
1266 */
1267 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1268# ifdef IN_RING3
1269 Assert(rc != VINF_PGM_CHANGE_MODE);
1270# endif
1271 AssertRCReturn(rc, rc);
1272
1273 /* Inform CPUM (recompiler), can later be removed. */
1274 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1275
1276 /*
1277 * Flush the TLB with new CR3. This is required in case the PGM mode change
1278 * above doesn't actually change anything.
1279 */
1280 if (rc == VINF_SUCCESS)
1281 {
1282 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1283 AssertRCReturn(rc, rc);
1284 }
1285
1286 /* Re-initialize IEM cache/state after the drastic mode switch. */
1287 iemReInitExec(pVCpu);
1288 return rc;
1289}
1290
1291
1292/**
1293 * Calculates the current VMX-preemption timer value.
1294 *
1295 * @returns The current VMX-preemption timer value.
1296 * @param pVCpu The cross context virtual CPU structure.
1297 */
1298IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1299{
1300 /*
1301 * Assume the following:
1302 * PreemptTimerShift = 5
1303 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1304 * EntryTick = 50000 (TSC at time of VM-entry)
1305 *
1306 * CurTick Delta PreemptTimerVal
1307 * ----------------------------------
1308 * 60000 10000 2
1309 * 80000 30000 1
1310 * 90000 40000 0 -> VM-exit.
1311 *
1312 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1313 * The saved VMX-preemption timer value is calculated as follows:
1314 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1315 * E.g.:
1316 * Delta = 10000
1317 * Tmp = 10000 / (2 * 10000) = 0.5
1318 * NewPt = 2 - 0.5 = 2
1319 * Delta = 30000
1320 * Tmp = 30000 / (2 * 10000) = 1.5
1321 * NewPt = 2 - 1.5 = 1
1322 * Delta = 40000
1323 * Tmp = 40000 / 20000 = 2
1324 * NewPt = 2 - 2 = 0
1325 */
1326 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1327 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1328 if (uVmcsPreemptVal > 0)
1329 {
1330 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1331 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1332 uint64_t const uDelta = uCurTick - uEntryTick;
1333 uint32_t const uPreemptTimer = uVmcsPreemptVal
1334 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1335 return uPreemptTimer;
1336 }
1337 return 0;
1338}
1339
1340
1341/**
1342 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1343 *
1344 * @param pVCpu The cross context virtual CPU structure.
1345 */
1346IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1347{
1348 /*
1349 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1350 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1351 */
1352 /* CS, SS, ES, DS, FS, GS. */
1353 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1354 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1355 {
1356 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1357 if (!pSelReg->Attr.n.u1Unusable)
1358 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1359 else
1360 {
1361 /*
1362 * For unusable segments the attributes are undefined except for CS and SS.
1363 * For the rest we don't bother preserving anything but the unusable bit.
1364 */
1365 switch (iSegReg)
1366 {
1367 case X86_SREG_CS:
1368 pVmcs->GuestCs = pSelReg->Sel;
1369 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1370 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1371 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1372 | X86DESCATTR_UNUSABLE);
1373 break;
1374
1375 case X86_SREG_SS:
1376 pVmcs->GuestSs = pSelReg->Sel;
1377 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1378 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1379 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1380 break;
1381
1382 case X86_SREG_DS:
1383 pVmcs->GuestDs = pSelReg->Sel;
1384 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1385 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1386 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1387 break;
1388
1389 case X86_SREG_ES:
1390 pVmcs->GuestEs = pSelReg->Sel;
1391 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1392 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1393 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1394 break;
1395
1396 case X86_SREG_FS:
1397 pVmcs->GuestFs = pSelReg->Sel;
1398 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1399 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1400 break;
1401
1402 case X86_SREG_GS:
1403 pVmcs->GuestGs = pSelReg->Sel;
1404 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1405 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1406 break;
1407 }
1408 }
1409 }
1410
1411 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1412 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1413 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1414 | X86DESCATTR_UNUSABLE;
1415 /* LDTR. */
1416 {
1417 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1418 pVmcs->GuestLdtr = pSelReg->Sel;
1419 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1420 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1421 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1422 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1423 }
1424
1425 /* TR. */
1426 {
1427 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1428 pVmcs->GuestTr = pSelReg->Sel;
1429 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1430 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1431 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1432 }
1433
1434 /* GDTR. */
1435 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1436 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1437
1438 /* IDTR. */
1439 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1440 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1441}
1442
1443
1444/**
1445 * Saves guest non-register state as part of VM-exit.
1446 *
1447 * @param pVCpu The cross context virtual CPU structure.
1448 * @param uExitReason The VM-exit reason.
1449 */
1450IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1451{
1452 /*
1453 * Save guest non-register state.
1454 * See Intel spec. 27.3.4 "Saving Non-Register State".
1455 */
1456 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1457
1458 /*
1459 * Activity state.
1460 * Most VM-exits will occur in the active state. However, if the first instruction
1461 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1462 * the VM-exit will be from the HLT activity state.
1463 *
1464 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1465 */
1466 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1467 * not? */
1468 EMSTATE const enmActivityState = EMGetState(pVCpu);
1469 switch (enmActivityState)
1470 {
1471 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1472 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1473 }
1474
1475 /*
1476 * Interruptibility-state.
1477 */
1478 /* NMI. */
1479 pVmcs->u32GuestIntrState = 0;
1480 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1481 {
1482 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1483 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1484 }
1485 else
1486 {
1487 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1488 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1489 }
1490
1491 /* Blocking-by-STI. */
1492 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1493 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1494 {
1495 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1496 * currently. */
1497 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1498 }
1499 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1500
1501 /*
1502 * Pending debug exceptions.
1503 *
1504 * For VM-exits where it is not applicable, we can safely zero out the field.
1505 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1506 */
1507 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1508 && uExitReason != VMX_EXIT_SMI
1509 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1510 && !VMXIsVmexitTrapLike(uExitReason))
1511 {
1512 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1513 * block-by-MovSS is in effect. */
1514 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1515 }
1516
1517 /*
1518 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1519 *
1520 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1521 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1522 */
1523 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1524 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1525 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1526
1527 /* PDPTEs. */
1528 /* We don't support EPT yet. */
1529 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1530 pVmcs->u64GuestPdpte0.u = 0;
1531 pVmcs->u64GuestPdpte1.u = 0;
1532 pVmcs->u64GuestPdpte2.u = 0;
1533 pVmcs->u64GuestPdpte3.u = 0;
1534}
1535
1536
1537/**
1538 * Saves the guest-state as part of VM-exit.
1539 *
1540 * @returns VBox status code.
1541 * @param pVCpu The cross context virtual CPU structure.
1542 * @param uExitReason The VM-exit reason.
1543 */
1544IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1545{
1546 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1547 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1548
1549 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1550 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1551 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1552
1553 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1554}
1555
1556
1557/**
1558 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1559 *
1560 * @returns VBox status code.
1561 * @param pVCpu The cross context virtual CPU structure.
1562 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1563 */
1564IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1565{
1566 /*
1567 * Save guest MSRs.
1568 * See Intel spec. 27.4 "Saving MSRs".
1569 */
1570 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1571 const char * const pszFailure = "VMX-abort";
1572
1573 /*
1574 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1575 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1576 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1577 */
1578 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1579 if (!cMsrs)
1580 return VINF_SUCCESS;
1581
1582 /*
1583 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1584 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1585 * implementation causes a VMX-abort followed by a triple-fault.
1586 */
1587 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1588 if (fIsMsrCountValid)
1589 { /* likely */ }
1590 else
1591 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1592
1593 /*
1594 * Optimization if the nested hypervisor is using the same guest-physical page for both
1595 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1596 */
1597 PVMXAUTOMSR pMsrArea;
1598 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1599 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1600 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1601 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1602 else
1603 {
1604 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1605 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1606 if (RT_SUCCESS(rc))
1607 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1608 else
1609 {
1610 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1611 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1612 }
1613 }
1614
1615 /*
1616 * Update VM-exit MSR store area.
1617 */
1618 PVMXAUTOMSR pMsr = pMsrArea;
1619 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1620 {
1621 if ( !pMsr->u32Reserved
1622 && pMsr->u32Msr != MSR_IA32_SMBASE
1623 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1624 {
1625 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1626 if (rcStrict == VINF_SUCCESS)
1627 continue;
1628
1629 /*
1630 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1631 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1632 * recording the MSR index in the auxiliary info. field and indicated further by our
1633 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1634 * if possible, or come up with a better, generic solution.
1635 */
1636 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1637 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1638 ? kVmxVDiag_Vmexit_MsrStoreRing3
1639 : kVmxVDiag_Vmexit_MsrStore;
1640 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1641 }
1642 else
1643 {
1644 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1645 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1646 }
1647 }
1648
1649 /*
1650 * Commit the VM-exit MSR store are to guest memory.
1651 */
1652 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1653 if (RT_SUCCESS(rc))
1654 return VINF_SUCCESS;
1655
1656 NOREF(uExitReason);
1657 NOREF(pszFailure);
1658
1659 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1660 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1661}
1662
1663
1664/**
1665 * Performs a VMX abort (due to an fatal error during VM-exit).
1666 *
1667 * @returns Strict VBox status code.
1668 * @param pVCpu The cross context virtual CPU structure.
1669 * @param enmAbort The VMX abort reason.
1670 */
1671IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1672{
1673 /*
1674 * Perform the VMX abort.
1675 * See Intel spec. 27.7 "VMX Aborts".
1676 */
1677 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1678
1679 /* We don't support SMX yet. */
1680 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1681 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1682 {
1683 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1684 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1685 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1686 }
1687
1688 return VINF_EM_TRIPLE_FAULT;
1689}
1690
1691
1692/**
1693 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1694 *
1695 * @param pVCpu The cross context virtual CPU structure.
1696 */
1697IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1698{
1699 /*
1700 * Load host control registers, debug registers and MSRs.
1701 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1702 */
1703 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1704 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1705
1706 /* CR0. */
1707 {
1708 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1709 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1710 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1711 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1712 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1713 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1714 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1715
1716 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1717 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1718 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1719 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1720 }
1721
1722 /* CR4. */
1723 {
1724 /* CR4 fixed bits are not modified. */
1725 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1726 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1727 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1728 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1729 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1730 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1731 if (fHostInLongMode)
1732 uValidHostCr4 |= X86_CR4_PAE;
1733 else
1734 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1735
1736 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1737 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1738 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1739 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1740 }
1741
1742 /* CR3 (host value validated while checking host-state during VM-entry). */
1743 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1744
1745 /* DR7. */
1746 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1747
1748 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1749
1750 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1751 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1752 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1753 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1754
1755 /* FS, GS bases are loaded later while we load host segment registers. */
1756
1757 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1758 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1759 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1760 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1761 {
1762 if (fHostInLongMode)
1763 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1764 else
1765 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1766 }
1767
1768 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1769
1770 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1771 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1772 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1773
1774 /* We don't support IA32_BNDCFGS MSR yet. */
1775}
1776
1777
1778/**
1779 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1780 *
1781 * @param pVCpu The cross context virtual CPU structure.
1782 */
1783IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1784{
1785 /*
1786 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1787 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1788 *
1789 * Warning! Be careful to not touch fields that are reserved by VT-x,
1790 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1791 */
1792 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1793 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1794
1795 /* CS, SS, ES, DS, FS, GS. */
1796 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1797 {
1798 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1799 bool const fUnusable = RT_BOOL(HostSel == 0);
1800 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1801
1802 /* Selector. */
1803 pSelReg->Sel = HostSel;
1804 pSelReg->ValidSel = HostSel;
1805 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1806
1807 /* Limit. */
1808 pSelReg->u32Limit = 0xffffffff;
1809
1810 /* Base. */
1811 pSelReg->u64Base = 0;
1812
1813 /* Attributes. */
1814 if (iSegReg == X86_SREG_CS)
1815 {
1816 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1817 pSelReg->Attr.n.u1DescType = 1;
1818 pSelReg->Attr.n.u2Dpl = 0;
1819 pSelReg->Attr.n.u1Present = 1;
1820 pSelReg->Attr.n.u1Long = fHostInLongMode;
1821 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1822 pSelReg->Attr.n.u1Granularity = 1;
1823 Assert(!pSelReg->Attr.n.u1Unusable);
1824 Assert(!fUnusable);
1825 }
1826 else
1827 {
1828 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1829 pSelReg->Attr.n.u1DescType = 1;
1830 pSelReg->Attr.n.u2Dpl = 0;
1831 pSelReg->Attr.n.u1Present = 1;
1832 pSelReg->Attr.n.u1DefBig = 1;
1833 pSelReg->Attr.n.u1Granularity = 1;
1834 pSelReg->Attr.n.u1Unusable = fUnusable;
1835 }
1836 }
1837
1838 /* FS base. */
1839 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1840 || fHostInLongMode)
1841 {
1842 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1843 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1844 }
1845
1846 /* GS base. */
1847 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1848 || fHostInLongMode)
1849 {
1850 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1851 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1852 }
1853
1854 /* TR. */
1855 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1856 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1857 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1858 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1859 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1860 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1861 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1862 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1863 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1864 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1865 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1866 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1867 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1868
1869 /* LDTR (Warning! do not touch the base and limits here). */
1870 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1871 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1872 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1873 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1874
1875 /* GDTR. */
1876 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1877 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1878 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1879
1880 /* IDTR.*/
1881 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1882 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1883 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1884}
1885
1886
1887/**
1888 * Checks host PDPTes as part of VM-exit.
1889 *
1890 * @param pVCpu The cross context virtual CPU structure.
1891 * @param uExitReason The VM-exit reason (for logging purposes).
1892 */
1893IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPUCC pVCpu, uint32_t uExitReason)
1894{
1895 /*
1896 * Check host PDPTEs.
1897 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1898 */
1899 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1900 const char * const pszFailure = "VMX-abort";
1901 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1902
1903 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1904 && !fHostInLongMode)
1905 {
1906 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
1907 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
1908 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
1909 if (RT_SUCCESS(rc))
1910 {
1911 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
1912 {
1913 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
1914 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
1915 { /* likely */ }
1916 else
1917 {
1918 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
1919 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1920 }
1921 }
1922 }
1923 else
1924 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
1925 }
1926
1927 NOREF(pszFailure);
1928 NOREF(uExitReason);
1929 return VINF_SUCCESS;
1930}
1931
1932
1933/**
1934 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1935 *
1936 * @returns VBox status code.
1937 * @param pVCpu The cross context virtual CPU structure.
1938 * @param pszInstr The VMX instruction name (for logging purposes).
1939 */
1940IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1941{
1942 /*
1943 * Load host MSRs.
1944 * See Intel spec. 27.6 "Loading MSRs".
1945 */
1946 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1947 const char * const pszFailure = "VMX-abort";
1948
1949 /*
1950 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1951 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1952 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1953 */
1954 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1955 if (!cMsrs)
1956 return VINF_SUCCESS;
1957
1958 /*
1959 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1960 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1961 * implementation causes a VMX-abort followed by a triple-fault.
1962 */
1963 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1964 if (fIsMsrCountValid)
1965 { /* likely */ }
1966 else
1967 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1968
1969 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1970 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1971 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1972 if (RT_SUCCESS(rc))
1973 {
1974 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1975 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1976 {
1977 if ( !pMsr->u32Reserved
1978 && pMsr->u32Msr != MSR_K8_FS_BASE
1979 && pMsr->u32Msr != MSR_K8_GS_BASE
1980 && pMsr->u32Msr != MSR_K6_EFER
1981 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1982 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1983 {
1984 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1985 if (rcStrict == VINF_SUCCESS)
1986 continue;
1987
1988 /*
1989 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1990 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1991 * recording the MSR index in the auxiliary info. field and indicated further by our
1992 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1993 * if possible, or come up with a better, generic solution.
1994 */
1995 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1996 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1997 ? kVmxVDiag_Vmexit_MsrLoadRing3
1998 : kVmxVDiag_Vmexit_MsrLoad;
1999 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2000 }
2001 else
2002 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2003 }
2004 }
2005 else
2006 {
2007 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2008 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2009 }
2010
2011 NOREF(uExitReason);
2012 NOREF(pszFailure);
2013 return VINF_SUCCESS;
2014}
2015
2016
2017/**
2018 * Loads the host state as part of VM-exit.
2019 *
2020 * @returns Strict VBox status code.
2021 * @param pVCpu The cross context virtual CPU structure.
2022 * @param uExitReason The VM-exit reason (for logging purposes).
2023 */
2024IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
2025{
2026 /*
2027 * Load host state.
2028 * See Intel spec. 27.5 "Loading Host State".
2029 */
2030 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2031 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2032
2033 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2034 if ( CPUMIsGuestInLongMode(pVCpu)
2035 && !fHostInLongMode)
2036 {
2037 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2038 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2039 }
2040
2041 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2042 iemVmxVmexitLoadHostSegRegs(pVCpu);
2043
2044 /*
2045 * Load host RIP, RSP and RFLAGS.
2046 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2047 */
2048 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2049 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2050 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2051
2052 /* Clear address range monitoring. */
2053 EMMonitorWaitClear(pVCpu);
2054
2055 /* Perform the VMX transition (PGM updates). */
2056 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2057 if (rcStrict == VINF_SUCCESS)
2058 {
2059 /* Check host PDPTEs (only when we've fully switched page tables_. */
2060 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2061 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2062 if (RT_FAILURE(rc))
2063 {
2064 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2065 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2066 }
2067 }
2068 else if (RT_SUCCESS(rcStrict))
2069 {
2070 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2071 uExitReason));
2072 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2073 }
2074 else
2075 {
2076 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2077 return VBOXSTRICTRC_VAL(rcStrict);
2078 }
2079
2080 Assert(rcStrict == VINF_SUCCESS);
2081
2082 /* Load MSRs from the VM-exit auto-load MSR area. */
2083 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2084 if (RT_FAILURE(rc))
2085 {
2086 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2087 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2088 }
2089 return VINF_SUCCESS;
2090}
2091
2092
2093/**
2094 * Gets VM-exit instruction information along with any displacement for an
2095 * instruction VM-exit.
2096 *
2097 * @returns The VM-exit instruction information.
2098 * @param pVCpu The cross context virtual CPU structure.
2099 * @param uExitReason The VM-exit reason.
2100 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2101 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2102 * NULL.
2103 */
2104IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2105{
2106 RTGCPTR GCPtrDisp;
2107 VMXEXITINSTRINFO ExitInstrInfo;
2108 ExitInstrInfo.u = 0;
2109
2110 /*
2111 * Get and parse the ModR/M byte from our decoded opcodes.
2112 */
2113 uint8_t bRm;
2114 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2115 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2116 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2117 {
2118 /*
2119 * ModR/M indicates register addressing.
2120 *
2121 * The primary/secondary register operands are reported in the iReg1 or iReg2
2122 * fields depending on whether it is a read/write form.
2123 */
2124 uint8_t idxReg1;
2125 uint8_t idxReg2;
2126 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2127 {
2128 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2129 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2130 }
2131 else
2132 {
2133 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2134 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2135 }
2136 ExitInstrInfo.All.u2Scaling = 0;
2137 ExitInstrInfo.All.iReg1 = idxReg1;
2138 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2139 ExitInstrInfo.All.fIsRegOperand = 1;
2140 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2141 ExitInstrInfo.All.iSegReg = 0;
2142 ExitInstrInfo.All.iIdxReg = 0;
2143 ExitInstrInfo.All.fIdxRegInvalid = 1;
2144 ExitInstrInfo.All.iBaseReg = 0;
2145 ExitInstrInfo.All.fBaseRegInvalid = 1;
2146 ExitInstrInfo.All.iReg2 = idxReg2;
2147
2148 /* Displacement not applicable for register addressing. */
2149 GCPtrDisp = 0;
2150 }
2151 else
2152 {
2153 /*
2154 * ModR/M indicates memory addressing.
2155 */
2156 uint8_t uScale = 0;
2157 bool fBaseRegValid = false;
2158 bool fIdxRegValid = false;
2159 uint8_t iBaseReg = 0;
2160 uint8_t iIdxReg = 0;
2161 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2162 {
2163 /*
2164 * Parse the ModR/M, displacement for 16-bit addressing mode.
2165 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2166 */
2167 uint16_t u16Disp = 0;
2168 uint8_t const offDisp = offModRm + sizeof(bRm);
2169 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2170 {
2171 /* Displacement without any registers. */
2172 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2173 }
2174 else
2175 {
2176 /* Register (index and base). */
2177 switch (bRm & X86_MODRM_RM_MASK)
2178 {
2179 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2180 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2181 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2182 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2183 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2184 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2185 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2186 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2187 }
2188
2189 /* Register + displacement. */
2190 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2191 {
2192 case 0: break;
2193 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2194 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2195 default:
2196 {
2197 /* Register addressing, handled at the beginning. */
2198 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2199 break;
2200 }
2201 }
2202 }
2203
2204 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2205 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2206 }
2207 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2208 {
2209 /*
2210 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2211 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2212 */
2213 uint32_t u32Disp = 0;
2214 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2215 {
2216 /* Displacement without any registers. */
2217 uint8_t const offDisp = offModRm + sizeof(bRm);
2218 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2219 }
2220 else
2221 {
2222 /* Register (and perhaps scale, index and base). */
2223 uint8_t offDisp = offModRm + sizeof(bRm);
2224 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2225 if (iBaseReg == 4)
2226 {
2227 /* An SIB byte follows the ModR/M byte, parse it. */
2228 uint8_t bSib;
2229 uint8_t const offSib = offModRm + sizeof(bRm);
2230 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2231
2232 /* A displacement may follow SIB, update its offset. */
2233 offDisp += sizeof(bSib);
2234
2235 /* Get the scale. */
2236 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2237
2238 /* Get the index register. */
2239 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2240 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2241
2242 /* Get the base register. */
2243 iBaseReg = bSib & X86_SIB_BASE_MASK;
2244 fBaseRegValid = true;
2245 if (iBaseReg == 5)
2246 {
2247 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2248 {
2249 /* Mod is 0 implies a 32-bit displacement with no base. */
2250 fBaseRegValid = false;
2251 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2252 }
2253 else
2254 {
2255 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2256 iBaseReg = X86_GREG_xBP;
2257 }
2258 }
2259 }
2260
2261 /* Register + displacement. */
2262 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2263 {
2264 case 0: /* Handled above */ break;
2265 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2266 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2267 default:
2268 {
2269 /* Register addressing, handled at the beginning. */
2270 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2271 break;
2272 }
2273 }
2274 }
2275
2276 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2277 }
2278 else
2279 {
2280 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2281
2282 /*
2283 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2284 * See Intel instruction spec. 2.2 "IA-32e Mode".
2285 */
2286 uint64_t u64Disp = 0;
2287 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2288 if (fRipRelativeAddr)
2289 {
2290 /*
2291 * RIP-relative addressing mode.
2292 *
2293 * The displacement is 32-bit signed implying an offset range of +/-2G.
2294 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2295 */
2296 uint8_t const offDisp = offModRm + sizeof(bRm);
2297 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2298 }
2299 else
2300 {
2301 uint8_t offDisp = offModRm + sizeof(bRm);
2302
2303 /*
2304 * Register (and perhaps scale, index and base).
2305 *
2306 * REX.B extends the most-significant bit of the base register. However, REX.B
2307 * is ignored while determining whether an SIB follows the opcode. Hence, we
2308 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2309 *
2310 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2311 */
2312 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2313 if (iBaseReg == 4)
2314 {
2315 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2316 uint8_t bSib;
2317 uint8_t const offSib = offModRm + sizeof(bRm);
2318 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2319
2320 /* Displacement may follow SIB, update its offset. */
2321 offDisp += sizeof(bSib);
2322
2323 /* Get the scale. */
2324 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2325
2326 /* Get the index. */
2327 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2328 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2329
2330 /* Get the base. */
2331 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2332 fBaseRegValid = true;
2333 if (iBaseReg == 5)
2334 {
2335 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2336 {
2337 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2338 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2339 }
2340 else
2341 {
2342 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2343 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2344 }
2345 }
2346 }
2347 iBaseReg |= pVCpu->iem.s.uRexB;
2348
2349 /* Register + displacement. */
2350 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2351 {
2352 case 0: /* Handled above */ break;
2353 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2354 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2355 default:
2356 {
2357 /* Register addressing, handled at the beginning. */
2358 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2359 break;
2360 }
2361 }
2362 }
2363
2364 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2365 }
2366
2367 /*
2368 * The primary or secondary register operand is reported in iReg2 depending
2369 * on whether the primary operand is in read/write form.
2370 */
2371 uint8_t idxReg2;
2372 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2373 {
2374 idxReg2 = bRm & X86_MODRM_RM_MASK;
2375 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2376 idxReg2 |= pVCpu->iem.s.uRexB;
2377 }
2378 else
2379 {
2380 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2381 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2382 idxReg2 |= pVCpu->iem.s.uRexReg;
2383 }
2384 ExitInstrInfo.All.u2Scaling = uScale;
2385 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2386 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2387 ExitInstrInfo.All.fIsRegOperand = 0;
2388 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2389 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2390 ExitInstrInfo.All.iIdxReg = iIdxReg;
2391 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2392 ExitInstrInfo.All.iBaseReg = iBaseReg;
2393 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2394 ExitInstrInfo.All.iReg2 = idxReg2;
2395 }
2396
2397 /*
2398 * Handle exceptions to the norm for certain instructions.
2399 * (e.g. some instructions convey an instruction identity in place of iReg2).
2400 */
2401 switch (uExitReason)
2402 {
2403 case VMX_EXIT_GDTR_IDTR_ACCESS:
2404 {
2405 Assert(VMXINSTRID_IS_VALID(uInstrId));
2406 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2407 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2408 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2409 break;
2410 }
2411
2412 case VMX_EXIT_LDTR_TR_ACCESS:
2413 {
2414 Assert(VMXINSTRID_IS_VALID(uInstrId));
2415 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2416 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2417 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2418 break;
2419 }
2420
2421 case VMX_EXIT_RDRAND:
2422 case VMX_EXIT_RDSEED:
2423 {
2424 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2425 break;
2426 }
2427 }
2428
2429 /* Update displacement and return the constructed VM-exit instruction information field. */
2430 if (pGCPtrDisp)
2431 *pGCPtrDisp = GCPtrDisp;
2432
2433 return ExitInstrInfo.u;
2434}
2435
2436
2437/**
2438 * VMX VM-exit handler.
2439 *
2440 * @returns Strict VBox status code.
2441 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2442 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2443 * triple-fault.
2444 *
2445 * @param pVCpu The cross context virtual CPU structure.
2446 * @param uExitReason The VM-exit reason.
2447 * @param u64ExitQual The Exit qualification.
2448 */
2449IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2450{
2451# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2452 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2453 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2454 return VERR_IEM_IPE_7;
2455# else
2456 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2457
2458 /*
2459 * Import all the guest-CPU state.
2460 *
2461 * HM on returning to guest execution would have to reset up a whole lot of state
2462 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2463 * the state and flag reloading the entire state on re-entry. So import the entire
2464 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2465 */
2466 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2467
2468 /*
2469 * Ensure VM-entry interruption information valid bit is cleared.
2470 *
2471 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2472 * by invalid-guest state or machine-check exceptions) also clear this bit.
2473 *
2474 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2475 */
2476 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2477 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2478
2479 /*
2480 * Update the VM-exit reason and Exit qualification.
2481 * Other VMCS read-only data fields are expected to be updated by the caller already.
2482 */
2483 pVmcs->u32RoExitReason = uExitReason;
2484 pVmcs->u64RoExitQual.u = u64ExitQual;
2485
2486 Log3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2487 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2488 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2489
2490 /*
2491 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2492 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2493 */
2494 {
2495 uint8_t uVector;
2496 uint32_t fFlags;
2497 uint32_t uErrCode;
2498 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2499 if (fInEventDelivery)
2500 {
2501 /*
2502 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2503 * caused by a triple-fault or the original event results in a double-fault that
2504 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2505 * original event information into the IDT-vectoring information fields.
2506 *
2507 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2508 */
2509 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2510 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2511 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2512 {
2513 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2514 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2515 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2516 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2517 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2518 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2519 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2520 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2521 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2522 pVCpu->cpum.GstCtx.cr2));
2523 }
2524 }
2525 }
2526
2527 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2528 Assert(pVmcs->u64RoIoRcx.u == 0);
2529 Assert(pVmcs->u64RoIoRsi.u == 0);
2530 Assert(pVmcs->u64RoIoRdi.u == 0);
2531 Assert(pVmcs->u64RoIoRip.u == 0);
2532
2533 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2534 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2535 {
2536 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2537 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2538 }
2539
2540 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2541 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2542
2543 /*
2544 * Save the guest state back into the VMCS.
2545 * We only need to save the state when the VM-entry was successful.
2546 */
2547 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2548 if (!fVmentryFailed)
2549 {
2550 /*
2551 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2552 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2553 *
2554 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2555 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2556 * as guest-CPU state would not been modified. Hence for now, we do this only when
2557 * the VM-entry succeeded.
2558 */
2559 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2560 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2561 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2562 {
2563 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2564 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2565 else
2566 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2567 }
2568
2569 /*
2570 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2571 * occurs in enclave mode/SMM which we don't support yet.
2572 *
2573 * If we ever add support for it, we can pass just the lower bits to the functions
2574 * below, till then an assert should suffice.
2575 */
2576 Assert(!RT_HI_U16(uExitReason));
2577
2578 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2579 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2580 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2581 if (RT_SUCCESS(rc))
2582 { /* likely */ }
2583 else
2584 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2585
2586 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2587 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2588 }
2589 else
2590 {
2591 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2592 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2593 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2594 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2595 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2596 }
2597
2598 /*
2599 * Stop any running VMX-preemption timer if necessary.
2600 */
2601 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2602 CPUMStopGuestVmxPremptTimer(pVCpu);
2603
2604 /*
2605 * Clear any pending VMX nested-guest force-flags.
2606 * These force-flags have no effect on (outer) guest execution and will
2607 * be re-evaluated and setup on the next nested-guest VM-entry.
2608 */
2609 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2610
2611 /* Restore the host (outer guest) state. */
2612 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2613 if (RT_SUCCESS(rcStrict))
2614 {
2615 Assert(rcStrict == VINF_SUCCESS);
2616 rcStrict = VINF_VMX_VMEXIT;
2617 }
2618 else
2619 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2620
2621 /* We're no longer in nested-guest execution mode. */
2622 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2623
2624 /* Notify HM that the current VMCS fields have been modified. */
2625 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2626
2627 /* Notify HM that we've completed the VM-exit. */
2628 HMNotifyVmxNstGstVmexit(pVCpu);
2629
2630# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2631 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2632 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2633 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2634 if (rcSched != VINF_SUCCESS)
2635 iemSetPassUpStatus(pVCpu, rcSched);
2636# endif
2637 return rcStrict;
2638# endif
2639}
2640
2641
2642/**
2643 * VMX VM-exit handler for VM-exits due to instruction execution.
2644 *
2645 * This is intended for instructions where the caller provides all the relevant
2646 * VM-exit information.
2647 *
2648 * @returns Strict VBox status code.
2649 * @param pVCpu The cross context virtual CPU structure.
2650 * @param pExitInfo Pointer to the VM-exit information.
2651 */
2652IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2653{
2654 /*
2655 * For instructions where any of the following fields are not applicable:
2656 * - Exit qualification must be cleared.
2657 * - VM-exit instruction info. is undefined.
2658 * - Guest-linear address is undefined.
2659 * - Guest-physical address is undefined.
2660 *
2661 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2662 * instruction execution. For VM-exits that are not due to instruction execution this
2663 * field is undefined.
2664 *
2665 * In our implementation in IEM, all undefined fields are generally cleared. However,
2666 * if the caller supplies information (from say the physical CPU directly) it is
2667 * then possible that the undefined fields are not cleared.
2668 *
2669 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2670 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2671 */
2672 Assert(pExitInfo);
2673 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2674 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2675 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2676
2677 /* Update all the relevant fields from the VM-exit instruction information struct. */
2678 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2679 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2680 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2681 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2682
2683 /* Perform the VM-exit. */
2684 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2685}
2686
2687
2688/**
2689 * VMX VM-exit handler for VM-exits due to instruction execution.
2690 *
2691 * This is intended for instructions that only provide the VM-exit instruction
2692 * length.
2693 *
2694 * @param pVCpu The cross context virtual CPU structure.
2695 * @param uExitReason The VM-exit reason.
2696 * @param cbInstr The instruction length in bytes.
2697 */
2698IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2699{
2700 VMXVEXITINFO ExitInfo;
2701 RT_ZERO(ExitInfo);
2702 ExitInfo.uReason = uExitReason;
2703 ExitInfo.cbInstr = cbInstr;
2704
2705#ifdef VBOX_STRICT
2706 /*
2707 * To prevent us from shooting ourselves in the foot.
2708 * The follow instructions should convey more than just the instruction length.
2709 */
2710 switch (uExitReason)
2711 {
2712 case VMX_EXIT_INVEPT:
2713 case VMX_EXIT_INVPCID:
2714 case VMX_EXIT_INVVPID:
2715 case VMX_EXIT_LDTR_TR_ACCESS:
2716 case VMX_EXIT_GDTR_IDTR_ACCESS:
2717 case VMX_EXIT_VMCLEAR:
2718 case VMX_EXIT_VMPTRLD:
2719 case VMX_EXIT_VMPTRST:
2720 case VMX_EXIT_VMREAD:
2721 case VMX_EXIT_VMWRITE:
2722 case VMX_EXIT_VMXON:
2723 case VMX_EXIT_XRSTORS:
2724 case VMX_EXIT_XSAVES:
2725 case VMX_EXIT_RDRAND:
2726 case VMX_EXIT_RDSEED:
2727 case VMX_EXIT_IO_INSTR:
2728 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2729 break;
2730 }
2731#endif
2732
2733 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2734}
2735
2736
2737/**
2738 * VMX VM-exit handler for VM-exits due to instruction execution.
2739 *
2740 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2741 * instruction information and Exit qualification fields.
2742 *
2743 * @param pVCpu The cross context virtual CPU structure.
2744 * @param uExitReason The VM-exit reason.
2745 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2746 * @param cbInstr The instruction length in bytes.
2747 *
2748 * @remarks Do not use this for INS/OUTS instruction.
2749 */
2750IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2751{
2752 VMXVEXITINFO ExitInfo;
2753 RT_ZERO(ExitInfo);
2754 ExitInfo.uReason = uExitReason;
2755 ExitInfo.cbInstr = cbInstr;
2756
2757 /*
2758 * Update the Exit qualification field with displacement bytes.
2759 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2760 */
2761 switch (uExitReason)
2762 {
2763 case VMX_EXIT_INVEPT:
2764 case VMX_EXIT_INVPCID:
2765 case VMX_EXIT_INVVPID:
2766 case VMX_EXIT_LDTR_TR_ACCESS:
2767 case VMX_EXIT_GDTR_IDTR_ACCESS:
2768 case VMX_EXIT_VMCLEAR:
2769 case VMX_EXIT_VMPTRLD:
2770 case VMX_EXIT_VMPTRST:
2771 case VMX_EXIT_VMREAD:
2772 case VMX_EXIT_VMWRITE:
2773 case VMX_EXIT_VMXON:
2774 case VMX_EXIT_XRSTORS:
2775 case VMX_EXIT_XSAVES:
2776 case VMX_EXIT_RDRAND:
2777 case VMX_EXIT_RDSEED:
2778 {
2779 /* Construct the VM-exit instruction information. */
2780 RTGCPTR GCPtrDisp;
2781 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2782
2783 /* Update the VM-exit instruction information. */
2784 ExitInfo.InstrInfo.u = uInstrInfo;
2785
2786 /* Update the Exit qualification. */
2787 ExitInfo.u64Qual = GCPtrDisp;
2788 break;
2789 }
2790
2791 default:
2792 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2793 break;
2794 }
2795
2796 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2797}
2798
2799
2800/**
2801 * VMX VM-exit handler for VM-exits due to INVLPG.
2802 *
2803 * @returns Strict VBox status code.
2804 * @param pVCpu The cross context virtual CPU structure.
2805 * @param GCPtrPage The guest-linear address of the page being invalidated.
2806 * @param cbInstr The instruction length in bytes.
2807 */
2808IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2809{
2810 VMXVEXITINFO ExitInfo;
2811 RT_ZERO(ExitInfo);
2812 ExitInfo.uReason = VMX_EXIT_INVLPG;
2813 ExitInfo.cbInstr = cbInstr;
2814 ExitInfo.u64Qual = GCPtrPage;
2815 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2816
2817 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2818}
2819
2820
2821/**
2822 * VMX VM-exit handler for VM-exits due to LMSW.
2823 *
2824 * @returns Strict VBox status code.
2825 * @param pVCpu The cross context virtual CPU structure.
2826 * @param uGuestCr0 The current guest CR0.
2827 * @param pu16NewMsw The machine-status word specified in LMSW's source
2828 * operand. This will be updated depending on the VMX
2829 * guest/host CR0 mask if LMSW is not intercepted.
2830 * @param GCPtrEffDst The guest-linear address of the source operand in case
2831 * of a memory operand. For register operand, pass
2832 * NIL_RTGCPTR.
2833 * @param cbInstr The instruction length in bytes.
2834 */
2835IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2836 uint8_t cbInstr)
2837{
2838 Assert(pu16NewMsw);
2839
2840 uint16_t const uNewMsw = *pu16NewMsw;
2841 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2842 {
2843 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2844
2845 VMXVEXITINFO ExitInfo;
2846 RT_ZERO(ExitInfo);
2847 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2848 ExitInfo.cbInstr = cbInstr;
2849
2850 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2851 if (fMemOperand)
2852 {
2853 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2854 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2855 }
2856
2857 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2858 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2859 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2860 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2861
2862 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2863 }
2864
2865 /*
2866 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2867 * CR0 guest/host mask must be left unmodified.
2868 *
2869 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2870 */
2871 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2872 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2873 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2874
2875 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2876}
2877
2878
2879/**
2880 * VMX VM-exit handler for VM-exits due to CLTS.
2881 *
2882 * @returns Strict VBox status code.
2883 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2884 * VM-exit but must not modify the guest CR0.TS bit.
2885 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2886 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2887 * CR0 fixed bits in VMX operation).
2888 * @param pVCpu The cross context virtual CPU structure.
2889 * @param cbInstr The instruction length in bytes.
2890 */
2891IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2892{
2893 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2894 uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2895
2896 /*
2897 * If CR0.TS is owned by the host:
2898 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2899 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2900 * CLTS instruction completes without clearing CR0.TS.
2901 *
2902 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2903 */
2904 if (fGstHostMask & X86_CR0_TS)
2905 {
2906 if (fReadShadow & X86_CR0_TS)
2907 {
2908 Log2(("clts: Guest intercept -> VM-exit\n"));
2909
2910 VMXVEXITINFO ExitInfo;
2911 RT_ZERO(ExitInfo);
2912 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2913 ExitInfo.cbInstr = cbInstr;
2914 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2915 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2916 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2917 }
2918
2919 return VINF_VMX_MODIFIES_BEHAVIOR;
2920 }
2921
2922 /*
2923 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2924 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2925 */
2926 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2927}
2928
2929
2930/**
2931 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2932 * (CR0/CR4 write).
2933 *
2934 * @returns Strict VBox status code.
2935 * @param pVCpu The cross context virtual CPU structure.
2936 * @param iCrReg The control register (either CR0 or CR4).
2937 * @param uGuestCrX The current guest CR0/CR4.
2938 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2939 * VM-exit is caused.
2940 * @param iGReg The general register from which the CR0/CR4 value is being
2941 * loaded.
2942 * @param cbInstr The instruction length in bytes.
2943 */
2944IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2945 uint8_t cbInstr)
2946{
2947 Assert(puNewCrX);
2948 Assert(iCrReg == 0 || iCrReg == 4);
2949 Assert(iGReg < X86_GREG_COUNT);
2950
2951 uint64_t const uNewCrX = *puNewCrX;
2952 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2953 {
2954 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2955
2956 VMXVEXITINFO ExitInfo;
2957 RT_ZERO(ExitInfo);
2958 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2959 ExitInfo.cbInstr = cbInstr;
2960 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2961 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2962 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2963 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2964 }
2965
2966 /*
2967 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2968 * must not be modified the instruction.
2969 *
2970 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2971 */
2972 uint64_t uGuestCrX;
2973 uint64_t fGstHostMask;
2974 if (iCrReg == 0)
2975 {
2976 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2977 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2978 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2979 }
2980 else
2981 {
2982 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2983 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2984 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2985 }
2986
2987 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2988 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2989}
2990
2991
2992/**
2993 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2994 *
2995 * @returns VBox strict status code.
2996 * @param pVCpu The cross context virtual CPU structure.
2997 * @param iGReg The general register to which the CR3 value is being stored.
2998 * @param cbInstr The instruction length in bytes.
2999 */
3000IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3001{
3002 Assert(iGReg < X86_GREG_COUNT);
3003 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3004
3005 /*
3006 * If the CR3-store exiting control is set, we must cause a VM-exit.
3007 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3008 */
3009 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3010 {
3011 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3012
3013 VMXVEXITINFO ExitInfo;
3014 RT_ZERO(ExitInfo);
3015 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3016 ExitInfo.cbInstr = cbInstr;
3017 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3018 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3019 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3020 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3021 }
3022
3023 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3024}
3025
3026
3027/**
3028 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3029 *
3030 * @returns VBox strict status code.
3031 * @param pVCpu The cross context virtual CPU structure.
3032 * @param uNewCr3 The new CR3 value.
3033 * @param iGReg The general register from which the CR3 value is being
3034 * loaded.
3035 * @param cbInstr The instruction length in bytes.
3036 */
3037IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3038{
3039 Assert(iGReg < X86_GREG_COUNT);
3040
3041 /*
3042 * If the CR3-load exiting control is set and the new CR3 value does not
3043 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3044 *
3045 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3046 */
3047 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3048 {
3049 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3050
3051 VMXVEXITINFO ExitInfo;
3052 RT_ZERO(ExitInfo);
3053 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3054 ExitInfo.cbInstr = cbInstr;
3055 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3056 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3057 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3058 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3059 }
3060
3061 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3062}
3063
3064
3065/**
3066 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3067 *
3068 * @returns VBox strict status code.
3069 * @param pVCpu The cross context virtual CPU structure.
3070 * @param iGReg The general register to which the CR8 value is being stored.
3071 * @param cbInstr The instruction length in bytes.
3072 */
3073IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3074{
3075 Assert(iGReg < X86_GREG_COUNT);
3076
3077 /*
3078 * If the CR8-store exiting control is set, we must cause a VM-exit.
3079 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3080 */
3081 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3082 {
3083 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3084
3085 VMXVEXITINFO ExitInfo;
3086 RT_ZERO(ExitInfo);
3087 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3088 ExitInfo.cbInstr = cbInstr;
3089 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3090 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3091 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3092 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3093 }
3094
3095 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3096}
3097
3098
3099/**
3100 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3101 *
3102 * @returns VBox strict status code.
3103 * @param pVCpu The cross context virtual CPU structure.
3104 * @param iGReg The general register from which the CR8 value is being
3105 * loaded.
3106 * @param cbInstr The instruction length in bytes.
3107 */
3108IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3109{
3110 Assert(iGReg < X86_GREG_COUNT);
3111
3112 /*
3113 * If the CR8-load exiting control is set, we must cause a VM-exit.
3114 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3115 */
3116 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3117 {
3118 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3119
3120 VMXVEXITINFO ExitInfo;
3121 RT_ZERO(ExitInfo);
3122 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3123 ExitInfo.cbInstr = cbInstr;
3124 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3125 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3126 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3127 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3128 }
3129
3130 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3131}
3132
3133
3134/**
3135 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3136 * GReg,DRx' (DRx read).
3137 *
3138 * @returns VBox strict status code.
3139 * @param pVCpu The cross context virtual CPU structure.
3140 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3141 * VMXINSTRID_MOV_FROM_DRX).
3142 * @param iDrReg The debug register being accessed.
3143 * @param iGReg The general register to/from which the DRx value is being
3144 * store/loaded.
3145 * @param cbInstr The instruction length in bytes.
3146 */
3147IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3148 uint8_t cbInstr)
3149{
3150 Assert(iDrReg <= 7);
3151 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3152 Assert(iGReg < X86_GREG_COUNT);
3153
3154 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3155 {
3156 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3157 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3158 VMXVEXITINFO ExitInfo;
3159 RT_ZERO(ExitInfo);
3160 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3161 ExitInfo.cbInstr = cbInstr;
3162 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3163 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3164 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3165 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3166 }
3167
3168 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3169}
3170
3171
3172/**
3173 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3174 *
3175 * @returns VBox strict status code.
3176 * @param pVCpu The cross context virtual CPU structure.
3177 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3178 * VMXINSTRID_IO_OUT).
3179 * @param u16Port The I/O port being accessed.
3180 * @param fImm Whether the I/O port was encoded using an immediate operand
3181 * or the implicit DX register.
3182 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3183 * @param cbInstr The instruction length in bytes.
3184 */
3185IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3186 uint8_t cbInstr)
3187{
3188 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3189 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3190
3191 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3192 if (fIntercept)
3193 {
3194 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3195 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3196 VMXVEXITINFO ExitInfo;
3197 RT_ZERO(ExitInfo);
3198 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3199 ExitInfo.cbInstr = cbInstr;
3200 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3201 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3202 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3203 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3204 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3205 }
3206
3207 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3208}
3209
3210
3211/**
3212 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3213 *
3214 * @returns VBox strict status code.
3215 * @param pVCpu The cross context virtual CPU structure.
3216 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3217 * VMXINSTRID_IO_OUTS).
3218 * @param u16Port The I/O port being accessed.
3219 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3220 * @param fRep Whether the instruction has a REP prefix or not.
3221 * @param ExitInstrInfo The VM-exit instruction info. field.
3222 * @param cbInstr The instruction length in bytes.
3223 */
3224IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3225 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3226{
3227 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3228 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3229 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3230 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3231 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3232
3233 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3234 if (fIntercept)
3235 {
3236 /*
3237 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3238 */
3239 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3240 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3241 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3242 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3243 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3244
3245 uint32_t uDirection;
3246 uint64_t uGuestLinearAddr;
3247 if (uInstrId == VMXINSTRID_IO_INS)
3248 {
3249 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3250 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3251 }
3252 else
3253 {
3254 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3255 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3256 }
3257
3258 /*
3259 * If the segment is unusable, the guest-linear address in undefined.
3260 * We shall clear it for consistency.
3261 *
3262 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3263 */
3264 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3265 uGuestLinearAddr = 0;
3266
3267 VMXVEXITINFO ExitInfo;
3268 RT_ZERO(ExitInfo);
3269 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3270 ExitInfo.cbInstr = cbInstr;
3271 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3272 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3273 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3274 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3275 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3276 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3277 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3278 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3279 ExitInfo.InstrInfo = ExitInstrInfo;
3280 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3281 }
3282
3283 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3284}
3285
3286
3287/**
3288 * VMX VM-exit handler for VM-exits due to MWAIT.
3289 *
3290 * @returns VBox strict status code.
3291 * @param pVCpu The cross context virtual CPU structure.
3292 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3293 * @param cbInstr The instruction length in bytes.
3294 */
3295IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3296{
3297 VMXVEXITINFO ExitInfo;
3298 RT_ZERO(ExitInfo);
3299 ExitInfo.uReason = VMX_EXIT_MWAIT;
3300 ExitInfo.cbInstr = cbInstr;
3301 ExitInfo.u64Qual = fMonitorHwArmed;
3302 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3303}
3304
3305
3306/**
3307 * VMX VM-exit handler for VM-exits due to PAUSE.
3308 *
3309 * @returns VBox strict status code.
3310 * @param pVCpu The cross context virtual CPU structure.
3311 * @param cbInstr The instruction length in bytes.
3312 */
3313IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3314{
3315 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3316
3317 /*
3318 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3319 * "PAUSE-loop exiting" control.
3320 *
3321 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3322 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3323 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3324 * a VM-exit.
3325 *
3326 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3327 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3328 */
3329 bool fIntercept = false;
3330 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3331 fIntercept = true;
3332 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3333 && pVCpu->iem.s.uCpl == 0)
3334 {
3335 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3336
3337 /*
3338 * A previous-PAUSE-tick value of 0 is used to identify the first time
3339 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3340 * consider this to be the first execution of PAUSE in a loop according
3341 * to the Intel.
3342 *
3343 * All subsequent records for the previous-PAUSE-tick we ensure that it
3344 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3345 */
3346 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3347 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3348 uint64_t const uTick = TMCpuTickGet(pVCpu);
3349 uint32_t const uPleGap = pVmcs->u32PleGap;
3350 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3351 if ( *puPrevPauseTick == 0
3352 || uTick - *puPrevPauseTick > uPleGap)
3353 *puFirstPauseLoopTick = uTick;
3354 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3355 fIntercept = true;
3356
3357 *puPrevPauseTick = uTick | 1;
3358 }
3359
3360 if (fIntercept)
3361 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3362
3363 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3364}
3365
3366
3367/**
3368 * VMX VM-exit handler for VM-exits due to task switches.
3369 *
3370 * @returns VBox strict status code.
3371 * @param pVCpu The cross context virtual CPU structure.
3372 * @param enmTaskSwitch The cause of the task switch.
3373 * @param SelNewTss The selector of the new TSS.
3374 * @param cbInstr The instruction length in bytes.
3375 */
3376IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3377{
3378 /*
3379 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3380 *
3381 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3382 * instruction or delivery of the exception generated by one of these instructions
3383 * lead to a task switch through a task gate in the IDT, we need to provide the
3384 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3385 * leaves the VM-exit instruction length field undefined.
3386 *
3387 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3388 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3389 */
3390 Assert(cbInstr <= 15);
3391
3392 uint8_t uType;
3393 switch (enmTaskSwitch)
3394 {
3395 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3396 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3397 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3398 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3399 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3400 }
3401
3402 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3403 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3404 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3405 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3406}
3407
3408
3409/**
3410 * VMX VM-exit handler for trap-like VM-exits.
3411 *
3412 * @returns VBox strict status code.
3413 * @param pVCpu The cross context virtual CPU structure.
3414 * @param pExitInfo Pointer to the VM-exit information.
3415 * @param pExitEventInfo Pointer to the VM-exit event information.
3416 */
3417IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3418{
3419 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3420 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3421 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3422}
3423
3424
3425/**
3426 * VMX VM-exit handler for VM-exits due to task switches.
3427 *
3428 * This is intended for task switches where the caller provides all the relevant
3429 * VM-exit information.
3430 *
3431 * @returns VBox strict status code.
3432 * @param pVCpu The cross context virtual CPU structure.
3433 * @param pExitInfo Pointer to the VM-exit information.
3434 * @param pExitEventInfo Pointer to the VM-exit event information.
3435 */
3436IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3437 PCVMXVEXITEVENTINFO pExitEventInfo)
3438{
3439 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3440 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3441 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3442 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3443 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3444}
3445
3446
3447/**
3448 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3449 *
3450 * @returns VBox strict status code.
3451 * @param pVCpu The cross context virtual CPU structure.
3452 */
3453IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3454{
3455 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3456 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3457
3458 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3459 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3460
3461 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3462 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3463 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3464
3465 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3466 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3467}
3468
3469
3470/**
3471 * VMX VM-exit handler for VM-exits due to external interrupts.
3472 *
3473 * @returns VBox strict status code.
3474 * @param pVCpu The cross context virtual CPU structure.
3475 * @param uVector The external interrupt vector (pass 0 if the interrupt
3476 * is still pending since we typically won't know the
3477 * vector).
3478 * @param fIntPending Whether the external interrupt is pending or
3479 * acknowledged in the interrupt controller.
3480 */
3481IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3482{
3483 Assert(!fIntPending || uVector == 0);
3484
3485 /* The VM-exit is subject to "External interrupt exiting" being set. */
3486 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3487 {
3488 if (fIntPending)
3489 {
3490 /*
3491 * If the interrupt is pending and we don't need to acknowledge the
3492 * interrupt on VM-exit, cause the VM-exit immediately.
3493 *
3494 * See Intel spec 25.2 "Other Causes Of VM Exits".
3495 */
3496 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3497 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3498
3499 /*
3500 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3501 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3502 * acknowledged that the interrupt has been consumed. Callers would have to call
3503 * us again after getting the vector (and ofc, with fIntPending with false).
3504 */
3505 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3506 }
3507
3508 /*
3509 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3510 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3511 * all set, we need to record the vector of the external interrupt in the
3512 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3513 *
3514 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3515 */
3516 uint32_t uExitIntInfo;
3517 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3518 {
3519 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3520 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3521 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3522 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3523 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3524 }
3525 else
3526 uExitIntInfo = 0;
3527 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3528
3529 /*
3530 * Cause the VM-exit whether or not the vector has been stored
3531 * in the VM-exit interruption-information field.
3532 */
3533 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3534 }
3535
3536 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3537}
3538
3539
3540/**
3541 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3542 * an event.
3543 *
3544 * @returns VBox strict status code.
3545 * @param pVCpu The cross context virtual CPU structure.
3546 */
3547IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3548{
3549 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3550 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3551 {
3552 /*
3553 * The NMI-unblocking due to IRET field need not be set for double faults.
3554 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3555 */
3556 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3557 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3558 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3559 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3560 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3561 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3562 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3563 }
3564
3565 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3566}
3567
3568
3569/**
3570 * VMX VM-exit handler for VM-exit due to delivery of an events.
3571 *
3572 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3573 * all the relevant VM-exit information.
3574 *
3575 * @returns VBox strict status code.
3576 * @param pVCpu The cross context virtual CPU structure.
3577 * @param pExitInfo Pointer to the VM-exit information.
3578 * @param pExitEventInfo Pointer to the VM-exit event information.
3579 */
3580IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3581{
3582 Assert(pExitInfo);
3583 Assert(pExitEventInfo);
3584 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3585 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3586
3587 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3588 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3589 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3590 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3591 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3592 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3593}
3594
3595
3596/**
3597 * VMX VM-exit handler for VM-exits due to delivery of an event.
3598 *
3599 * @returns VBox strict status code.
3600 * @param pVCpu The cross context virtual CPU structure.
3601 * @param uVector The interrupt / exception vector.
3602 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3603 * @param uErrCode The error code associated with the event.
3604 * @param uCr2 The CR2 value in case of a \#PF exception.
3605 * @param cbInstr The instruction length in bytes.
3606 */
3607IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3608 uint8_t cbInstr)
3609{
3610 /*
3611 * If the event is being injected as part of VM-entry, it is -not- subject to event
3612 * intercepts in the nested-guest. However, secondary exceptions that occur during
3613 * injection of any event -are- subject to event interception.
3614 *
3615 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3616 */
3617 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3618 {
3619 /*
3620 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3621 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3622 *
3623 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3624 */
3625 if ( uVector == X86_XCPT_NMI
3626 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3627 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3628 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3629 else
3630 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3631
3632 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3633 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3634 }
3635
3636 /*
3637 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3638 * If not, the caller will continue delivery of the external interrupt as it would
3639 * normally. The interrupt is no longer pending in the interrupt controller at this
3640 * point.
3641 */
3642 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3643 {
3644 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3645 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3646 }
3647
3648 /*
3649 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3650 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3651 * interrupts.
3652 */
3653 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3654 bool fIntercept;
3655 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3656 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3657 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3658 else
3659 {
3660 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3661 fIntercept = false;
3662 }
3663
3664 /*
3665 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3666 * relevant VM-exit information and cause the VM-exit.
3667 */
3668 if (fIntercept)
3669 {
3670 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3671
3672 /* Construct the rest of the event related information fields and cause the VM-exit. */
3673 uint64_t u64ExitQual;
3674 if (uVector == X86_XCPT_PF)
3675 {
3676 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3677 u64ExitQual = uCr2;
3678 }
3679 else if (uVector == X86_XCPT_DB)
3680 {
3681 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3682 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3683 }
3684 else
3685 u64ExitQual = 0;
3686
3687 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3688 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3689 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3690 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3691 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3692 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3693 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3694 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3695 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3696 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3697
3698 /*
3699 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3700 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3701 * length.
3702 */
3703 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3704 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3705 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3706 else
3707 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3708
3709 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3710 }
3711
3712 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3713}
3714
3715
3716/**
3717 * VMX VM-exit handler for APIC accesses.
3718 *
3719 * @param pVCpu The cross context virtual CPU structure.
3720 * @param offAccess The offset of the register being accessed.
3721 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3722 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3723 */
3724IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3725{
3726 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3727
3728 VMXAPICACCESS enmAccess;
3729 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3730 if (fInEventDelivery)
3731 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3732 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3733 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3734 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3735 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3736 else
3737 enmAccess = VMXAPICACCESS_LINEAR_READ;
3738
3739 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3740 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3741 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3742}
3743
3744
3745/**
3746 * VMX VM-exit handler for APIC accesses.
3747 *
3748 * This is intended for APIC accesses where the caller provides all the
3749 * relevant VM-exit information.
3750 *
3751 * @returns VBox strict status code.
3752 * @param pVCpu The cross context virtual CPU structure.
3753 * @param pExitInfo Pointer to the VM-exit information.
3754 * @param pExitEventInfo Pointer to the VM-exit event information.
3755 */
3756IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3757 PCVMXVEXITEVENTINFO pExitEventInfo)
3758{
3759 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3760 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3761 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3762 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3763 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3764 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3765 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3766 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3767 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3768}
3769
3770
3771/**
3772 * VMX VM-exit handler for APIC-write VM-exits.
3773 *
3774 * @param pVCpu The cross context virtual CPU structure.
3775 * @param offApic The write to the virtual-APIC page offset that caused this
3776 * VM-exit.
3777 */
3778IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3779{
3780 Assert(offApic < XAPIC_OFF_END + 4);
3781 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3782 offApic &= UINT16_C(0xfff);
3783 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3784}
3785
3786
3787/**
3788 * Sets virtual-APIC write emulation as pending.
3789 *
3790 * @param pVCpu The cross context virtual CPU structure.
3791 * @param offApic The offset in the virtual-APIC page that was written.
3792 */
3793DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3794{
3795 Assert(offApic < XAPIC_OFF_END + 4);
3796
3797 /*
3798 * Record the currently updated APIC offset, as we need this later for figuring
3799 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3800 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3801 */
3802 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3803
3804 /*
3805 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3806 * virtualization or APIC-write emulation).
3807 */
3808 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3809 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3810}
3811
3812
3813/**
3814 * Clears any pending virtual-APIC write emulation.
3815 *
3816 * @returns The virtual-APIC offset that was written before clearing it.
3817 * @param pVCpu The cross context virtual CPU structure.
3818 */
3819DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3820{
3821 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3822 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3823 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3824 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3825 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3826 return offVirtApicWrite;
3827}
3828
3829
3830/**
3831 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3832 *
3833 * @returns The register from the virtual-APIC page.
3834 * @param pVCpu The cross context virtual CPU structure.
3835 * @param offReg The offset of the register being read.
3836 */
3837IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3838{
3839 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3840
3841 uint32_t uReg = 0;
3842 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3843 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3844 AssertMsgStmt(RT_SUCCESS(rc),
3845 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3846 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3847 uReg = 0);
3848 return uReg;
3849}
3850
3851
3852/**
3853 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3854 *
3855 * @returns The register from the virtual-APIC page.
3856 * @param pVCpu The cross context virtual CPU structure.
3857 * @param offReg The offset of the register being read.
3858 */
3859IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3860{
3861 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3862
3863 uint64_t uReg = 0;
3864 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3865 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3866 AssertMsgStmt(RT_SUCCESS(rc),
3867 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3868 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3869 uReg = 0);
3870 return uReg;
3871}
3872
3873
3874/**
3875 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3876 *
3877 * @param pVCpu The cross context virtual CPU structure.
3878 * @param offReg The offset of the register being written.
3879 * @param uReg The register value to write.
3880 */
3881IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3882{
3883 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3884
3885 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3886 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3887 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3888 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3889}
3890
3891
3892/**
3893 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3894 *
3895 * @param pVCpu The cross context virtual CPU structure.
3896 * @param offReg The offset of the register being written.
3897 * @param uReg The register value to write.
3898 */
3899IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3900{
3901 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3902
3903 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3904 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3905 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3906 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3907}
3908
3909
3910/**
3911 * Sets the vector in a virtual-APIC 256-bit sparse register.
3912 *
3913 * @param pVCpu The cross context virtual CPU structure.
3914 * @param offReg The offset of the 256-bit spare register.
3915 * @param uVector The vector to set.
3916 *
3917 * @remarks This is based on our APIC device code.
3918 */
3919IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3920{
3921 /* Determine the vector offset within the chunk. */
3922 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3923
3924 /* Read the chunk at the offset. */
3925 uint32_t uReg;
3926 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3927 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3928 if (RT_SUCCESS(rc))
3929 {
3930 /* Modify the chunk. */
3931 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3932 uReg |= RT_BIT(idxVectorBit);
3933
3934 /* Write the chunk. */
3935 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3936 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3937 uVector, offReg, GCPhysVirtApic, rc));
3938 }
3939 else
3940 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3941 uVector, offReg, GCPhysVirtApic, rc));
3942}
3943
3944
3945/**
3946 * Clears the vector in a virtual-APIC 256-bit sparse register.
3947 *
3948 * @param pVCpu The cross context virtual CPU structure.
3949 * @param offReg The offset of the 256-bit spare register.
3950 * @param uVector The vector to clear.
3951 *
3952 * @remarks This is based on our APIC device code.
3953 */
3954IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3955{
3956 /* Determine the vector offset within the chunk. */
3957 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3958
3959 /* Read the chunk at the offset. */
3960 uint32_t uReg;
3961 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3962 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3963 if (RT_SUCCESS(rc))
3964 {
3965 /* Modify the chunk. */
3966 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3967 uReg &= ~RT_BIT(idxVectorBit);
3968
3969 /* Write the chunk. */
3970 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3971 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3972 uVector, offReg, GCPhysVirtApic, rc));
3973 }
3974 else
3975 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3976 uVector, offReg, GCPhysVirtApic, rc));
3977}
3978
3979
3980/**
3981 * Checks if a memory access to the APIC-access page must causes an APIC-access
3982 * VM-exit.
3983 *
3984 * @param pVCpu The cross context virtual CPU structure.
3985 * @param offAccess The offset of the register being accessed.
3986 * @param cbAccess The size of the access in bytes.
3987 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
3988 * IEM_ACCESS_TYPE_WRITE).
3989 *
3990 * @remarks This must not be used for MSR-based APIC-access page accesses!
3991 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
3992 */
3993IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
3994{
3995 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3996 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
3997
3998 /*
3999 * We must cause a VM-exit if any of the following are true:
4000 * - TPR shadowing isn't active.
4001 * - The access size exceeds 32-bits.
4002 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4003 *
4004 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4005 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4006 */
4007 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4008 || cbAccess > sizeof(uint32_t)
4009 || ((offAccess + cbAccess - 1) & 0xc)
4010 || offAccess >= XAPIC_OFF_END + 4)
4011 return true;
4012
4013 /*
4014 * If the access is part of an operation where we have already
4015 * virtualized a virtual-APIC write, we must cause a VM-exit.
4016 */
4017 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4018 return true;
4019
4020 /*
4021 * Check write accesses to the APIC-access page that cause VM-exits.
4022 */
4023 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4024 {
4025 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4026 {
4027 /*
4028 * With APIC-register virtualization, a write access to any of the
4029 * following registers are virtualized. Accessing any other register
4030 * causes a VM-exit.
4031 */
4032 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4033 switch (offAlignedAccess)
4034 {
4035 case XAPIC_OFF_ID:
4036 case XAPIC_OFF_TPR:
4037 case XAPIC_OFF_EOI:
4038 case XAPIC_OFF_LDR:
4039 case XAPIC_OFF_DFR:
4040 case XAPIC_OFF_SVR:
4041 case XAPIC_OFF_ESR:
4042 case XAPIC_OFF_ICR_LO:
4043 case XAPIC_OFF_ICR_HI:
4044 case XAPIC_OFF_LVT_TIMER:
4045 case XAPIC_OFF_LVT_THERMAL:
4046 case XAPIC_OFF_LVT_PERF:
4047 case XAPIC_OFF_LVT_LINT0:
4048 case XAPIC_OFF_LVT_LINT1:
4049 case XAPIC_OFF_LVT_ERROR:
4050 case XAPIC_OFF_TIMER_ICR:
4051 case XAPIC_OFF_TIMER_DCR:
4052 break;
4053 default:
4054 return true;
4055 }
4056 }
4057 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4058 {
4059 /*
4060 * With virtual-interrupt delivery, a write access to any of the
4061 * following registers are virtualized. Accessing any other register
4062 * causes a VM-exit.
4063 *
4064 * Note! The specification does not allow writing to offsets in-between
4065 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4066 */
4067 switch (offAccess)
4068 {
4069 case XAPIC_OFF_TPR:
4070 case XAPIC_OFF_EOI:
4071 case XAPIC_OFF_ICR_LO:
4072 break;
4073 default:
4074 return true;
4075 }
4076 }
4077 else
4078 {
4079 /*
4080 * Without APIC-register virtualization or virtual-interrupt delivery,
4081 * only TPR accesses are virtualized.
4082 */
4083 if (offAccess == XAPIC_OFF_TPR)
4084 { /* likely */ }
4085 else
4086 return true;
4087 }
4088 }
4089 else
4090 {
4091 /*
4092 * Check read accesses to the APIC-access page that cause VM-exits.
4093 */
4094 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4095 {
4096 /*
4097 * With APIC-register virtualization, a read access to any of the
4098 * following registers are virtualized. Accessing any other register
4099 * causes a VM-exit.
4100 */
4101 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4102 switch (offAlignedAccess)
4103 {
4104 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4105 case XAPIC_OFF_ID:
4106 case XAPIC_OFF_VERSION:
4107 case XAPIC_OFF_TPR:
4108 case XAPIC_OFF_EOI:
4109 case XAPIC_OFF_LDR:
4110 case XAPIC_OFF_DFR:
4111 case XAPIC_OFF_SVR:
4112 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4113 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4114 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4115 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4116 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4117 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4118 case XAPIC_OFF_ESR:
4119 case XAPIC_OFF_ICR_LO:
4120 case XAPIC_OFF_ICR_HI:
4121 case XAPIC_OFF_LVT_TIMER:
4122 case XAPIC_OFF_LVT_THERMAL:
4123 case XAPIC_OFF_LVT_PERF:
4124 case XAPIC_OFF_LVT_LINT0:
4125 case XAPIC_OFF_LVT_LINT1:
4126 case XAPIC_OFF_LVT_ERROR:
4127 case XAPIC_OFF_TIMER_ICR:
4128 case XAPIC_OFF_TIMER_DCR:
4129 break;
4130 default:
4131 return true;
4132 }
4133 }
4134 else
4135 {
4136 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4137 if (offAccess == XAPIC_OFF_TPR)
4138 { /* likely */ }
4139 else
4140 return true;
4141 }
4142 }
4143
4144 /* The APIC access is virtualized, does not cause a VM-exit. */
4145 return false;
4146}
4147
4148
4149/**
4150 * Virtualizes a memory-based APIC access where the address is not used to access
4151 * memory.
4152 *
4153 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4154 * page-faults but do not use the address to access memory.
4155 *
4156 * @param pVCpu The cross context virtual CPU structure.
4157 * @param pGCPhysAccess Pointer to the guest-physical address used.
4158 */
4159IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4160{
4161 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4162 Assert(pGCPhysAccess);
4163
4164 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4165 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4166 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4167
4168 if (GCPhysAccess == GCPhysApic)
4169 {
4170 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4171 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4172 uint16_t const cbAccess = 1;
4173 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4174 if (fIntercept)
4175 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4176
4177 *pGCPhysAccess = GCPhysApic | offAccess;
4178 return VINF_VMX_MODIFIES_BEHAVIOR;
4179 }
4180
4181 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4182}
4183
4184
4185/**
4186 * Virtualizes a memory-based APIC access.
4187 *
4188 * @returns VBox strict status code.
4189 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4190 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4191 *
4192 * @param pVCpu The cross context virtual CPU structure.
4193 * @param offAccess The offset of the register being accessed (within the
4194 * APIC-access page).
4195 * @param cbAccess The size of the access in bytes.
4196 * @param pvData Pointer to the data being written or where to store the data
4197 * being read.
4198 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4199 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4200 */
4201IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4202 uint32_t fAccess)
4203{
4204 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4205 Assert(pvData);
4206 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4207 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4208 || (fAccess & IEM_ACCESS_INSTRUCTION));
4209
4210 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4211 if (fIntercept)
4212 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4213
4214 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4215 {
4216 /*
4217 * A write access to the APIC-access page that is virtualized (rather than
4218 * causing a VM-exit) writes data to the virtual-APIC page.
4219 */
4220 uint32_t const u32Data = *(uint32_t *)pvData;
4221 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4222
4223 /*
4224 * Record the currently updated APIC offset, as we need this later for figuring
4225 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4226 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4227 *
4228 * After completion of the current operation, we need to perform TPR virtualization,
4229 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4230 *
4231 * The current operation may be a REP-prefixed string instruction, execution of any
4232 * other instruction, or delivery of an event through the IDT.
4233 *
4234 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4235 * performed now but later after completion of the current operation.
4236 *
4237 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4238 */
4239 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4240 }
4241 else
4242 {
4243 /*
4244 * A read access from the APIC-access page that is virtualized (rather than
4245 * causing a VM-exit) returns data from the virtual-APIC page.
4246 *
4247 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4248 */
4249 Assert(cbAccess <= 4);
4250 Assert(offAccess < XAPIC_OFF_END + 4);
4251 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4252
4253 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4254 u32Data &= s_auAccessSizeMasks[cbAccess];
4255 *(uint32_t *)pvData = u32Data;
4256 }
4257
4258 return VINF_VMX_MODIFIES_BEHAVIOR;
4259}
4260
4261
4262/**
4263 * Virtualizes an MSR-based APIC read access.
4264 *
4265 * @returns VBox strict status code.
4266 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4267 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4268 * handled by the x2APIC device.
4269 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4270 * not within the range of valid MSRs, caller must raise \#GP(0).
4271 * @param pVCpu The cross context virtual CPU structure.
4272 * @param idMsr The x2APIC MSR being read.
4273 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4274 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4275 */
4276IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4277{
4278 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4279 Assert(pu64Value);
4280
4281 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4282 {
4283 if ( idMsr >= MSR_IA32_X2APIC_START
4284 && idMsr <= MSR_IA32_X2APIC_END)
4285 {
4286 uint16_t const offReg = (idMsr & 0xff) << 4;
4287 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4288 *pu64Value = u64Value;
4289 return VINF_VMX_MODIFIES_BEHAVIOR;
4290 }
4291 return VERR_OUT_OF_RANGE;
4292 }
4293
4294 if (idMsr == MSR_IA32_X2APIC_TPR)
4295 {
4296 uint16_t const offReg = (idMsr & 0xff) << 4;
4297 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4298 *pu64Value = u64Value;
4299 return VINF_VMX_MODIFIES_BEHAVIOR;
4300 }
4301
4302 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4303}
4304
4305
4306/**
4307 * Virtualizes an MSR-based APIC write access.
4308 *
4309 * @returns VBox strict status code.
4310 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4311 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4312 * not within the range of valid MSRs, caller must raise \#GP(0).
4313 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4314 *
4315 * @param pVCpu The cross context virtual CPU structure.
4316 * @param idMsr The x2APIC MSR being written.
4317 * @param u64Value The value of the x2APIC MSR being written.
4318 */
4319IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4320{
4321 /*
4322 * Check if the access is to be virtualized.
4323 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4324 */
4325 if ( idMsr == MSR_IA32_X2APIC_TPR
4326 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4327 && ( idMsr == MSR_IA32_X2APIC_EOI
4328 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4329 {
4330 /* Validate the MSR write depending on the register. */
4331 switch (idMsr)
4332 {
4333 case MSR_IA32_X2APIC_TPR:
4334 case MSR_IA32_X2APIC_SELF_IPI:
4335 {
4336 if (u64Value & UINT64_C(0xffffffffffffff00))
4337 return VERR_OUT_OF_RANGE;
4338 break;
4339 }
4340 case MSR_IA32_X2APIC_EOI:
4341 {
4342 if (u64Value != 0)
4343 return VERR_OUT_OF_RANGE;
4344 break;
4345 }
4346 }
4347
4348 /* Write the MSR to the virtual-APIC page. */
4349 uint16_t const offReg = (idMsr & 0xff) << 4;
4350 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4351
4352 /*
4353 * Record the currently updated APIC offset, as we need this later for figuring
4354 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4355 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4356 */
4357 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4358
4359 return VINF_VMX_MODIFIES_BEHAVIOR;
4360 }
4361
4362 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4363}
4364
4365
4366/**
4367 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4368 *
4369 * @returns VBox status code.
4370 * @retval VINF_SUCCESS when the highest set bit is found.
4371 * @retval VERR_NOT_FOUND when no bit is set.
4372 *
4373 * @param pVCpu The cross context virtual CPU structure.
4374 * @param offReg The offset of the APIC 256-bit sparse register.
4375 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4376 * set in the register. Only valid when VINF_SUCCESS is
4377 * returned.
4378 *
4379 * @remarks The format of the 256-bit sparse register here mirrors that found in
4380 * real APIC hardware.
4381 */
4382static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4383{
4384 Assert(offReg < XAPIC_OFF_END + 4);
4385 Assert(pidxHighestBit);
4386
4387 /*
4388 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4389 * However, in each fragment only the first 4 bytes are used.
4390 */
4391 uint8_t const cFrags = 8;
4392 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4393 {
4394 uint16_t const offFrag = iFrag * 16;
4395 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4396 if (!u32Frag)
4397 continue;
4398
4399 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4400 Assert(idxHighestBit > 0);
4401 --idxHighestBit;
4402 Assert(idxHighestBit <= UINT8_MAX);
4403 *pidxHighestBit = idxHighestBit;
4404 return VINF_SUCCESS;
4405 }
4406 return VERR_NOT_FOUND;
4407}
4408
4409
4410/**
4411 * Evaluates pending virtual interrupts.
4412 *
4413 * @param pVCpu The cross context virtual CPU structure.
4414 */
4415IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4416{
4417 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4418
4419 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4420 {
4421 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4422 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4423
4424 if ((uRvi >> 4) > (uPpr >> 4))
4425 {
4426 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4427 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4428 }
4429 else
4430 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4431 }
4432}
4433
4434
4435/**
4436 * Performs PPR virtualization.
4437 *
4438 * @returns VBox strict status code.
4439 * @param pVCpu The cross context virtual CPU structure.
4440 */
4441IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4442{
4443 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4444 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4445
4446 /*
4447 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4448 * or EOI-virtualization.
4449 *
4450 * See Intel spec. 29.1.3 "PPR Virtualization".
4451 */
4452 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4453 uint32_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4454
4455 uint32_t uPpr;
4456 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4457 uPpr = uTpr & 0xff;
4458 else
4459 uPpr = uSvi & 0xf0;
4460
4461 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4462 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4463}
4464
4465
4466/**
4467 * Performs VMX TPR virtualization.
4468 *
4469 * @returns VBox strict status code.
4470 * @param pVCpu The cross context virtual CPU structure.
4471 */
4472IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4473{
4474 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4475
4476 /*
4477 * We should have already performed the virtual-APIC write to the TPR offset
4478 * in the virtual-APIC page. We now perform TPR virtualization.
4479 *
4480 * See Intel spec. 29.1.2 "TPR Virtualization".
4481 */
4482 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4483 {
4484 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4485 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4486
4487 /*
4488 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4489 * See Intel spec. 29.1.2 "TPR Virtualization".
4490 */
4491 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4492 {
4493 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4494 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4495 }
4496 }
4497 else
4498 {
4499 iemVmxPprVirtualization(pVCpu);
4500 iemVmxEvalPendingVirtIntrs(pVCpu);
4501 }
4502
4503 return VINF_SUCCESS;
4504}
4505
4506
4507/**
4508 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4509 * not.
4510 *
4511 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4512 * @param pVCpu The cross context virtual CPU structure.
4513 * @param uVector The interrupt that was acknowledged using an EOI.
4514 */
4515IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4516{
4517 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4518 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4519
4520 if (uVector < 64)
4521 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4522 if (uVector < 128)
4523 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4524 if (uVector < 192)
4525 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4526 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4527}
4528
4529
4530/**
4531 * Performs EOI virtualization.
4532 *
4533 * @returns VBox strict status code.
4534 * @param pVCpu The cross context virtual CPU structure.
4535 */
4536IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4537{
4538 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4539 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4540
4541 /*
4542 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4543 * and get the next guest-interrupt that's in-service (if any).
4544 *
4545 * See Intel spec. 29.1.4 "EOI Virtualization".
4546 */
4547 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4548 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4549 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4550
4551 uint8_t uVector = uSvi;
4552 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4553
4554 uVector = 0;
4555 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4556
4557 if (uVector)
4558 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4559 else
4560 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4561
4562 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4563 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4564
4565 iemVmxPprVirtualization(pVCpu);
4566 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4567 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4568 iemVmxEvalPendingVirtIntrs(pVCpu);
4569 return VINF_SUCCESS;
4570}
4571
4572
4573/**
4574 * Performs self-IPI virtualization.
4575 *
4576 * @returns VBox strict status code.
4577 * @param pVCpu The cross context virtual CPU structure.
4578 */
4579IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4580{
4581 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4582 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4583
4584 /*
4585 * We should have already performed the virtual-APIC write to the self-IPI offset
4586 * in the virtual-APIC page. We now perform self-IPI virtualization.
4587 *
4588 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4589 */
4590 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4591 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4592 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4593 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4594 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4595 if (uVector > uRvi)
4596 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4597 iemVmxEvalPendingVirtIntrs(pVCpu);
4598 return VINF_SUCCESS;
4599}
4600
4601
4602/**
4603 * Performs VMX APIC-write emulation.
4604 *
4605 * @returns VBox strict status code.
4606 * @param pVCpu The cross context virtual CPU structure.
4607 */
4608IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4609{
4610 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4611
4612 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4613 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4614
4615 /*
4616 * Perform APIC-write emulation based on the virtual-APIC register written.
4617 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4618 */
4619 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4620 VBOXSTRICTRC rcStrict;
4621 switch (offApicWrite)
4622 {
4623 case XAPIC_OFF_TPR:
4624 {
4625 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4626 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4627 uTpr &= UINT32_C(0x000000ff);
4628 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4629 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4630 rcStrict = iemVmxTprVirtualization(pVCpu);
4631 break;
4632 }
4633
4634 case XAPIC_OFF_EOI:
4635 {
4636 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4637 {
4638 /* Clear VEOI and perform EOI virtualization. */
4639 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4640 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4641 rcStrict = iemVmxEoiVirtualization(pVCpu);
4642 }
4643 else
4644 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4645 break;
4646 }
4647
4648 case XAPIC_OFF_ICR_LO:
4649 {
4650 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4651 {
4652 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4653 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4654 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4655 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4656 if ( !(uIcrLo & fIcrLoMb0)
4657 && (uIcrLo & fIcrLoMb1))
4658 {
4659 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4660 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4661 }
4662 else
4663 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4664 }
4665 else
4666 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4667 break;
4668 }
4669
4670 case XAPIC_OFF_ICR_HI:
4671 {
4672 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4673 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4674 uIcrHi &= UINT32_C(0xff000000);
4675 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4676 rcStrict = VINF_SUCCESS;
4677 break;
4678 }
4679
4680 default:
4681 {
4682 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4683 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4684 break;
4685 }
4686 }
4687
4688 return rcStrict;
4689}
4690
4691
4692/**
4693 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4694 *
4695 * @param pVCpu The cross context virtual CPU structure.
4696 * @param pszInstr The VMX instruction name (for logging purposes).
4697 */
4698DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4699{
4700 /*
4701 * Guest Control Registers, Debug Registers, and MSRs.
4702 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4703 */
4704 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4705 const char * const pszFailure = "VM-exit";
4706 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4707
4708 /* CR0 reserved bits. */
4709 {
4710 /* CR0 MB1 bits. */
4711 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4712 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4713 if (fUnrestrictedGuest)
4714 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4715 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4716 { /* likely */ }
4717 else
4718 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4719
4720 /* CR0 MBZ bits. */
4721 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4722 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4723 { /* likely */ }
4724 else
4725 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4726
4727 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4728 if ( !fUnrestrictedGuest
4729 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4730 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4731 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4732 }
4733
4734 /* CR4 reserved bits. */
4735 {
4736 /* CR4 MB1 bits. */
4737 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4738 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4739 { /* likely */ }
4740 else
4741 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4742
4743 /* CR4 MBZ bits. */
4744 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4745 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4746 { /* likely */ }
4747 else
4748 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4749 }
4750
4751 /* DEBUGCTL MSR. */
4752 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4753 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4754 { /* likely */ }
4755 else
4756 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4757
4758 /* 64-bit CPU checks. */
4759 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4760 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4761 {
4762 if (fGstInLongMode)
4763 {
4764 /* PAE must be set. */
4765 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4766 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4767 { /* likely */ }
4768 else
4769 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4770 }
4771 else
4772 {
4773 /* PCIDE should not be set. */
4774 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4775 { /* likely */ }
4776 else
4777 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4778 }
4779
4780 /* CR3. */
4781 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4782 { /* likely */ }
4783 else
4784 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4785
4786 /* DR7. */
4787 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4788 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4789 { /* likely */ }
4790 else
4791 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4792
4793 /* SYSENTER ESP and SYSENTER EIP. */
4794 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4795 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4796 { /* likely */ }
4797 else
4798 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4799 }
4800
4801 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4802 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4803
4804 /* PAT MSR. */
4805 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4806 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4807 { /* likely */ }
4808 else
4809 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4810
4811 /* EFER MSR. */
4812 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4813 {
4814 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4815 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4816 { /* likely */ }
4817 else
4818 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4819
4820 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4821 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4822 if ( fGstLma == fGstInLongMode
4823 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4824 || fGstLma == fGstLme))
4825 { /* likely */ }
4826 else
4827 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4828 }
4829
4830 /* We don't support IA32_BNDCFGS MSR yet. */
4831 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4832
4833 NOREF(pszInstr);
4834 NOREF(pszFailure);
4835 return VINF_SUCCESS;
4836}
4837
4838
4839/**
4840 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4841 *
4842 * @param pVCpu The cross context virtual CPU structure.
4843 * @param pszInstr The VMX instruction name (for logging purposes).
4844 */
4845DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4846{
4847 /*
4848 * Segment registers.
4849 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4850 */
4851 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4852 const char * const pszFailure = "VM-exit";
4853 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4854 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4855 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4856
4857 /* Selectors. */
4858 if ( !fGstInV86Mode
4859 && !fUnrestrictedGuest
4860 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4861 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4862
4863 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4864 {
4865 CPUMSELREG SelReg;
4866 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4867 if (RT_LIKELY(rc == VINF_SUCCESS))
4868 { /* likely */ }
4869 else
4870 return rc;
4871
4872 /*
4873 * Virtual-8086 mode checks.
4874 */
4875 if (fGstInV86Mode)
4876 {
4877 /* Base address. */
4878 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4879 { /* likely */ }
4880 else
4881 {
4882 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4883 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4884 }
4885
4886 /* Limit. */
4887 if (SelReg.u32Limit == 0xffff)
4888 { /* likely */ }
4889 else
4890 {
4891 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4892 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4893 }
4894
4895 /* Attribute. */
4896 if (SelReg.Attr.u == 0xf3)
4897 { /* likely */ }
4898 else
4899 {
4900 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4901 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4902 }
4903
4904 /* We're done; move to checking the next segment. */
4905 continue;
4906 }
4907
4908 /* Checks done by 64-bit CPUs. */
4909 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4910 {
4911 /* Base address. */
4912 if ( iSegReg == X86_SREG_FS
4913 || iSegReg == X86_SREG_GS)
4914 {
4915 if (X86_IS_CANONICAL(SelReg.u64Base))
4916 { /* likely */ }
4917 else
4918 {
4919 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4920 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4921 }
4922 }
4923 else if (iSegReg == X86_SREG_CS)
4924 {
4925 if (!RT_HI_U32(SelReg.u64Base))
4926 { /* likely */ }
4927 else
4928 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
4929 }
4930 else
4931 {
4932 if ( SelReg.Attr.n.u1Unusable
4933 || !RT_HI_U32(SelReg.u64Base))
4934 { /* likely */ }
4935 else
4936 {
4937 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4938 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4939 }
4940 }
4941 }
4942
4943 /*
4944 * Checks outside Virtual-8086 mode.
4945 */
4946 uint8_t const uSegType = SelReg.Attr.n.u4Type;
4947 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
4948 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
4949 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
4950 uint8_t const fPresent = SelReg.Attr.n.u1Present;
4951 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
4952 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
4953 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
4954
4955 /* Code or usable segment. */
4956 if ( iSegReg == X86_SREG_CS
4957 || fUsable)
4958 {
4959 /* Reserved bits (bits 31:17 and bits 11:8). */
4960 if (!(SelReg.Attr.u & 0xfffe0f00))
4961 { /* likely */ }
4962 else
4963 {
4964 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
4965 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4966 }
4967
4968 /* Descriptor type. */
4969 if (fCodeDataSeg)
4970 { /* likely */ }
4971 else
4972 {
4973 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
4974 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4975 }
4976
4977 /* Present. */
4978 if (fPresent)
4979 { /* likely */ }
4980 else
4981 {
4982 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
4983 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4984 }
4985
4986 /* Granularity. */
4987 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
4988 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
4989 { /* likely */ }
4990 else
4991 {
4992 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
4993 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4994 }
4995 }
4996
4997 if (iSegReg == X86_SREG_CS)
4998 {
4999 /* Segment Type and DPL. */
5000 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5001 && fUnrestrictedGuest)
5002 {
5003 if (uDpl == 0)
5004 { /* likely */ }
5005 else
5006 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5007 }
5008 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5009 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5010 {
5011 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5012 if (uDpl == AttrSs.n.u2Dpl)
5013 { /* likely */ }
5014 else
5015 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5016 }
5017 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5018 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5019 {
5020 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5021 if (uDpl <= AttrSs.n.u2Dpl)
5022 { /* likely */ }
5023 else
5024 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5025 }
5026 else
5027 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5028
5029 /* Def/Big. */
5030 if ( fGstInLongMode
5031 && fSegLong)
5032 {
5033 if (uDefBig == 0)
5034 { /* likely */ }
5035 else
5036 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5037 }
5038 }
5039 else if (iSegReg == X86_SREG_SS)
5040 {
5041 /* Segment Type. */
5042 if ( !fUsable
5043 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5044 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5045 { /* likely */ }
5046 else
5047 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5048
5049 /* DPL. */
5050 if (!fUnrestrictedGuest)
5051 {
5052 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5053 { /* likely */ }
5054 else
5055 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5056 }
5057 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5058 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5059 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5060 {
5061 if (uDpl == 0)
5062 { /* likely */ }
5063 else
5064 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5065 }
5066 }
5067 else
5068 {
5069 /* DS, ES, FS, GS. */
5070 if (fUsable)
5071 {
5072 /* Segment type. */
5073 if (uSegType & X86_SEL_TYPE_ACCESSED)
5074 { /* likely */ }
5075 else
5076 {
5077 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5078 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5079 }
5080
5081 if ( !(uSegType & X86_SEL_TYPE_CODE)
5082 || (uSegType & X86_SEL_TYPE_READ))
5083 { /* likely */ }
5084 else
5085 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5086
5087 /* DPL. */
5088 if ( !fUnrestrictedGuest
5089 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5090 {
5091 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5092 { /* likely */ }
5093 else
5094 {
5095 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5096 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5097 }
5098 }
5099 }
5100 }
5101 }
5102
5103 /*
5104 * LDTR.
5105 */
5106 {
5107 CPUMSELREG Ldtr;
5108 Ldtr.Sel = pVmcs->GuestLdtr;
5109 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5110 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5111 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5112
5113 if (!Ldtr.Attr.n.u1Unusable)
5114 {
5115 /* Selector. */
5116 if (!(Ldtr.Sel & X86_SEL_LDT))
5117 { /* likely */ }
5118 else
5119 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5120
5121 /* Base. */
5122 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5123 {
5124 if (X86_IS_CANONICAL(Ldtr.u64Base))
5125 { /* likely */ }
5126 else
5127 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5128 }
5129
5130 /* Attributes. */
5131 /* Reserved bits (bits 31:17 and bits 11:8). */
5132 if (!(Ldtr.Attr.u & 0xfffe0f00))
5133 { /* likely */ }
5134 else
5135 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5136
5137 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5138 { /* likely */ }
5139 else
5140 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5141
5142 if (!Ldtr.Attr.n.u1DescType)
5143 { /* likely */ }
5144 else
5145 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5146
5147 if (Ldtr.Attr.n.u1Present)
5148 { /* likely */ }
5149 else
5150 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5151
5152 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5153 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5154 { /* likely */ }
5155 else
5156 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5157 }
5158 }
5159
5160 /*
5161 * TR.
5162 */
5163 {
5164 CPUMSELREG Tr;
5165 Tr.Sel = pVmcs->GuestTr;
5166 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5167 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5168 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5169
5170 /* Selector. */
5171 if (!(Tr.Sel & X86_SEL_LDT))
5172 { /* likely */ }
5173 else
5174 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5175
5176 /* Base. */
5177 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5178 {
5179 if (X86_IS_CANONICAL(Tr.u64Base))
5180 { /* likely */ }
5181 else
5182 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5183 }
5184
5185 /* Attributes. */
5186 /* Reserved bits (bits 31:17 and bits 11:8). */
5187 if (!(Tr.Attr.u & 0xfffe0f00))
5188 { /* likely */ }
5189 else
5190 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5191
5192 if (!Tr.Attr.n.u1Unusable)
5193 { /* likely */ }
5194 else
5195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5196
5197 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5198 || ( !fGstInLongMode
5199 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5200 { /* likely */ }
5201 else
5202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5203
5204 if (!Tr.Attr.n.u1DescType)
5205 { /* likely */ }
5206 else
5207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5208
5209 if (Tr.Attr.n.u1Present)
5210 { /* likely */ }
5211 else
5212 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5213
5214 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5215 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5216 { /* likely */ }
5217 else
5218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5219 }
5220
5221 NOREF(pszInstr);
5222 NOREF(pszFailure);
5223 return VINF_SUCCESS;
5224}
5225
5226
5227/**
5228 * Checks guest GDTR and IDTR as part of VM-entry.
5229 *
5230 * @param pVCpu The cross context virtual CPU structure.
5231 * @param pszInstr The VMX instruction name (for logging purposes).
5232 */
5233DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5234{
5235 /*
5236 * GDTR and IDTR.
5237 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5238 */
5239 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5240 const char *const pszFailure = "VM-exit";
5241
5242 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5243 {
5244 /* Base. */
5245 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5246 { /* likely */ }
5247 else
5248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5249
5250 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5251 { /* likely */ }
5252 else
5253 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5254 }
5255
5256 /* Limit. */
5257 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5258 { /* likely */ }
5259 else
5260 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5261
5262 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5263 { /* likely */ }
5264 else
5265 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5266
5267 NOREF(pszInstr);
5268 NOREF(pszFailure);
5269 return VINF_SUCCESS;
5270}
5271
5272
5273/**
5274 * Checks guest RIP and RFLAGS as part of VM-entry.
5275 *
5276 * @param pVCpu The cross context virtual CPU structure.
5277 * @param pszInstr The VMX instruction name (for logging purposes).
5278 */
5279DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5280{
5281 /*
5282 * RIP and RFLAGS.
5283 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5284 */
5285 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5286 const char *const pszFailure = "VM-exit";
5287 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5288
5289 /* RIP. */
5290 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5291 {
5292 X86DESCATTR AttrCs;
5293 AttrCs.u = pVmcs->u32GuestCsAttr;
5294 if ( !fGstInLongMode
5295 || !AttrCs.n.u1Long)
5296 {
5297 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5298 { /* likely */ }
5299 else
5300 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5301 }
5302
5303 if ( fGstInLongMode
5304 && AttrCs.n.u1Long)
5305 {
5306 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5307 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5308 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5309 { /* likely */ }
5310 else
5311 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5312 }
5313 }
5314
5315 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5316 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5317 : pVmcs->u64GuestRFlags.s.Lo;
5318 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5319 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5320 { /* likely */ }
5321 else
5322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5323
5324 if ( fGstInLongMode
5325 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5326 {
5327 if (!(uGuestRFlags & X86_EFL_VM))
5328 { /* likely */ }
5329 else
5330 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5331 }
5332
5333 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5334 {
5335 if (uGuestRFlags & X86_EFL_IF)
5336 { /* likely */ }
5337 else
5338 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5339 }
5340
5341 NOREF(pszInstr);
5342 NOREF(pszFailure);
5343 return VINF_SUCCESS;
5344}
5345
5346
5347/**
5348 * Checks guest non-register state as part of VM-entry.
5349 *
5350 * @param pVCpu The cross context virtual CPU structure.
5351 * @param pszInstr The VMX instruction name (for logging purposes).
5352 */
5353DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5354{
5355 /*
5356 * Guest non-register state.
5357 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5358 */
5359 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5360 const char *const pszFailure = "VM-exit";
5361
5362 /*
5363 * Activity state.
5364 */
5365 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5366 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5367 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5368 { /* likely */ }
5369 else
5370 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5371
5372 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5373 if ( !AttrSs.n.u2Dpl
5374 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5375 { /* likely */ }
5376 else
5377 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5378
5379 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5380 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5381 {
5382 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5383 { /* likely */ }
5384 else
5385 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5386 }
5387
5388 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5389 {
5390 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5391 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5392 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5393 switch (pVmcs->u32GuestActivityState)
5394 {
5395 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5396 {
5397 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5398 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5399 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5400 && ( uVector == X86_XCPT_DB
5401 || uVector == X86_XCPT_MC))
5402 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5403 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5404 { /* likely */ }
5405 else
5406 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5407 break;
5408 }
5409
5410 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5411 {
5412 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5413 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5414 && uVector == X86_XCPT_MC))
5415 { /* likely */ }
5416 else
5417 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5418 break;
5419 }
5420
5421 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5422 default:
5423 break;
5424 }
5425 }
5426
5427 /*
5428 * Interruptibility state.
5429 */
5430 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5431 { /* likely */ }
5432 else
5433 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5434
5435 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5436 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5437 { /* likely */ }
5438 else
5439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5440
5441 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5442 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5443 { /* likely */ }
5444 else
5445 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5446
5447 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5448 {
5449 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5450 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5451 {
5452 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5453 { /* likely */ }
5454 else
5455 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5456 }
5457 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5458 {
5459 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5460 { /* likely */ }
5461 else
5462 {
5463 /*
5464 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5465 * We update the Exit qualification only when blocking-by-STI is set
5466 * without blocking-by-MovSS being set. Although in practise it does not
5467 * make much difference since the order of checks are implementation defined.
5468 */
5469 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5470 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5471 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5472 }
5473
5474 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5475 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5476 { /* likely */ }
5477 else
5478 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5479 }
5480 }
5481
5482 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5483 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5484 { /* likely */ }
5485 else
5486 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5487
5488 /* We don't support SGX yet. So enclave-interruption must not be set. */
5489 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5490 { /* likely */ }
5491 else
5492 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5493
5494 /*
5495 * Pending debug exceptions.
5496 */
5497 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5498 ? pVmcs->u64GuestPendingDbgXcpts.u
5499 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5500 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5501 { /* likely */ }
5502 else
5503 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5504
5505 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5506 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5507 {
5508 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5509 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5510 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5511 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5512
5513 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5514 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5515 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5516 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5517 }
5518
5519 /* We don't support RTM (Real-time Transactional Memory) yet. */
5520 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5521 { /* likely */ }
5522 else
5523 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5524
5525 /*
5526 * VMCS link pointer.
5527 */
5528 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5529 {
5530 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5531 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5532 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5533 { /* likely */ }
5534 else
5535 {
5536 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5537 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5538 }
5539
5540 /* Validate the address. */
5541 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5542 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5543 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5544 { /* likely */ }
5545 else
5546 {
5547 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5548 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5549 }
5550 }
5551
5552 NOREF(pszInstr);
5553 NOREF(pszFailure);
5554 return VINF_SUCCESS;
5555}
5556
5557
5558/**
5559 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5560 * VM-entry.
5561 *
5562 * @returns @c true if all PDPTEs are valid, @c false otherwise.
5563 * @param pVCpu The cross context virtual CPU structure.
5564 * @param pszInstr The VMX instruction name (for logging purposes).
5565 * @param pVmcs Pointer to the virtual VMCS.
5566 */
5567IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPUCC pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
5568{
5569 /*
5570 * Check PDPTEs.
5571 * See Intel spec. 4.4.1 "PDPTE Registers".
5572 */
5573 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
5574 const char *const pszFailure = "VM-exit";
5575
5576 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
5577 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
5578 if (RT_SUCCESS(rc))
5579 {
5580 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
5581 {
5582 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
5583 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
5584 { /* likely */ }
5585 else
5586 {
5587 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5588 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
5589 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5590 }
5591 }
5592 }
5593 else
5594 {
5595 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5596 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
5597 }
5598
5599 NOREF(pszFailure);
5600 NOREF(pszInstr);
5601 return rc;
5602}
5603
5604
5605/**
5606 * Checks guest PDPTEs as part of VM-entry.
5607 *
5608 * @param pVCpu The cross context virtual CPU structure.
5609 * @param pszInstr The VMX instruction name (for logging purposes).
5610 */
5611DECLINLINE(int) iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr)
5612{
5613 /*
5614 * Guest PDPTEs.
5615 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5616 */
5617 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5618 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5619
5620 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
5621 int rc;
5622 if ( !fGstInLongMode
5623 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5624 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5625 {
5626 /*
5627 * We don't support nested-paging for nested-guests yet.
5628 *
5629 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
5630 * rather we need to check the PDPTEs referenced by the guest CR3.
5631 */
5632 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
5633 }
5634 else
5635 rc = VINF_SUCCESS;
5636 return rc;
5637}
5638
5639
5640/**
5641 * Checks guest-state as part of VM-entry.
5642 *
5643 * @returns VBox status code.
5644 * @param pVCpu The cross context virtual CPU structure.
5645 * @param pszInstr The VMX instruction name (for logging purposes).
5646 */
5647IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr)
5648{
5649 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5650 if (RT_SUCCESS(rc))
5651 {
5652 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5653 if (RT_SUCCESS(rc))
5654 {
5655 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5656 if (RT_SUCCESS(rc))
5657 {
5658 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5659 if (RT_SUCCESS(rc))
5660 {
5661 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5662 if (RT_SUCCESS(rc))
5663 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5664 }
5665 }
5666 }
5667 }
5668 return rc;
5669}
5670
5671
5672/**
5673 * Checks host-state as part of VM-entry.
5674 *
5675 * @returns VBox status code.
5676 * @param pVCpu The cross context virtual CPU structure.
5677 * @param pszInstr The VMX instruction name (for logging purposes).
5678 */
5679IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5680{
5681 /*
5682 * Host Control Registers and MSRs.
5683 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5684 */
5685 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5686 const char * const pszFailure = "VMFail";
5687
5688 /* CR0 reserved bits. */
5689 {
5690 /* CR0 MB1 bits. */
5691 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5692 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5693 { /* likely */ }
5694 else
5695 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5696
5697 /* CR0 MBZ bits. */
5698 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5699 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5700 { /* likely */ }
5701 else
5702 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5703 }
5704
5705 /* CR4 reserved bits. */
5706 {
5707 /* CR4 MB1 bits. */
5708 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5709 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5710 { /* likely */ }
5711 else
5712 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5713
5714 /* CR4 MBZ bits. */
5715 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5716 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5717 { /* likely */ }
5718 else
5719 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5720 }
5721
5722 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5723 {
5724 /* CR3 reserved bits. */
5725 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5726 { /* likely */ }
5727 else
5728 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5729
5730 /* SYSENTER ESP and SYSENTER EIP. */
5731 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5732 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5733 { /* likely */ }
5734 else
5735 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5736 }
5737
5738 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5739 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5740
5741 /* PAT MSR. */
5742 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5743 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5744 { /* likely */ }
5745 else
5746 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5747
5748 /* EFER MSR. */
5749 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5750 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5751 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5752 { /* likely */ }
5753 else
5754 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5755
5756 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5757 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5758 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5759 if ( fHostInLongMode == fHostLma
5760 && fHostInLongMode == fHostLme)
5761 { /* likely */ }
5762 else
5763 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5764
5765 /*
5766 * Host Segment and Descriptor-Table Registers.
5767 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5768 */
5769 /* Selector RPL and TI. */
5770 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5771 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5772 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5773 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5774 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5775 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5776 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5777 { /* likely */ }
5778 else
5779 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5780
5781 /* CS and TR selectors cannot be 0. */
5782 if ( pVmcs->HostCs
5783 && pVmcs->HostTr)
5784 { /* likely */ }
5785 else
5786 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5787
5788 /* SS cannot be 0 if 32-bit host. */
5789 if ( fHostInLongMode
5790 || pVmcs->HostSs)
5791 { /* likely */ }
5792 else
5793 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5794
5795 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5796 {
5797 /* FS, GS, GDTR, IDTR, TR base address. */
5798 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5799 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5800 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5801 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5802 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5803 { /* likely */ }
5804 else
5805 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5806 }
5807
5808 /*
5809 * Host address-space size for 64-bit CPUs.
5810 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5811 */
5812 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5813 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5814 {
5815 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5816
5817 /* Logical processor in IA-32e mode. */
5818 if (fCpuInLongMode)
5819 {
5820 if (fHostInLongMode)
5821 {
5822 /* PAE must be set. */
5823 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5824 { /* likely */ }
5825 else
5826 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5827
5828 /* RIP must be canonical. */
5829 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5830 { /* likely */ }
5831 else
5832 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5833 }
5834 else
5835 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5836 }
5837 else
5838 {
5839 /* Logical processor is outside IA-32e mode. */
5840 if ( !fGstInLongMode
5841 && !fHostInLongMode)
5842 {
5843 /* PCIDE should not be set. */
5844 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5845 { /* likely */ }
5846 else
5847 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5848
5849 /* The high 32-bits of RIP MBZ. */
5850 if (!pVmcs->u64HostRip.s.Hi)
5851 { /* likely */ }
5852 else
5853 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5854 }
5855 else
5856 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5857 }
5858 }
5859 else
5860 {
5861 /* Host address-space size for 32-bit CPUs. */
5862 if ( !fGstInLongMode
5863 && !fHostInLongMode)
5864 { /* likely */ }
5865 else
5866 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5867 }
5868
5869 NOREF(pszInstr);
5870 NOREF(pszFailure);
5871 return VINF_SUCCESS;
5872}
5873
5874
5875/**
5876 * Checks VMCS controls fields as part of VM-entry.
5877 *
5878 * @returns VBox status code.
5879 * @param pVCpu The cross context virtual CPU structure.
5880 * @param pszInstr The VMX instruction name (for logging purposes).
5881 *
5882 * @remarks This may update secondary-processor based VM-execution control fields
5883 * in the current VMCS if necessary.
5884 */
5885IEM_STATIC int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr)
5886{
5887 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5888 const char * const pszFailure = "VMFail";
5889
5890 /*
5891 * VM-execution controls.
5892 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
5893 */
5894 {
5895 /* Pin-based VM-execution controls. */
5896 {
5897 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
5898 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
5899 { /* likely */ }
5900 else
5901 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
5902
5903 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
5904 { /* likely */ }
5905 else
5906 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
5907 }
5908
5909 /* Processor-based VM-execution controls. */
5910 {
5911 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
5912 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
5913 { /* likely */ }
5914 else
5915 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
5916
5917 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
5918 { /* likely */ }
5919 else
5920 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
5921 }
5922
5923 /* Secondary processor-based VM-execution controls. */
5924 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
5925 {
5926 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
5927 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
5928 { /* likely */ }
5929 else
5930 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
5931
5932 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
5933 { /* likely */ }
5934 else
5935 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
5936 }
5937 else
5938 Assert(!pVmcs->u32ProcCtls2);
5939
5940 /* CR3-target count. */
5941 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
5942 { /* likely */ }
5943 else
5944 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
5945
5946 /* I/O bitmaps physical addresses. */
5947 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
5948 {
5949 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
5950 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
5951 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5952 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
5953 { /* likely */ }
5954 else
5955 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
5956
5957 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
5958 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
5959 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5960 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
5961 { /* likely */ }
5962 else
5963 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
5964 }
5965
5966 /* MSR bitmap physical address. */
5967 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
5968 {
5969 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
5970 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
5971 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5972 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
5973 { /* likely */ }
5974 else
5975 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
5976 }
5977
5978 /* TPR shadow related controls. */
5979 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
5980 {
5981 /* Virtual-APIC page physical address. */
5982 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
5983 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
5984 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5985 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
5986 { /* likely */ }
5987 else
5988 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
5989
5990 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
5991 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
5992 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
5993 { /* likely */ }
5994 else
5995 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
5996
5997 /* The rest done XXX document */
5998 }
5999 else
6000 {
6001 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6002 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6003 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6004 { /* likely */ }
6005 else
6006 {
6007 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6008 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6009 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6010 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6011 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6012 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6013 }
6014 }
6015
6016 /* NMI exiting and virtual-NMIs. */
6017 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6018 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6019 { /* likely */ }
6020 else
6021 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6022
6023 /* Virtual-NMIs and NMI-window exiting. */
6024 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6025 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6026 { /* likely */ }
6027 else
6028 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6029
6030 /* Virtualize APIC accesses. */
6031 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6032 {
6033 /* APIC-access physical address. */
6034 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6035 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6036 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6037 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6038 { /* likely */ }
6039 else
6040 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6041
6042 /*
6043 * Disallow APIC-access page and virtual-APIC page from being the same address.
6044 * Note! This is not an Intel requirement, but one imposed by our implementation.
6045 */
6046 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6047 * redirecting accesses between the APIC-access page and the virtual-APIC
6048 * page. If any nested hypervisor requires this, we can implement it later. */
6049 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6050 {
6051 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6052 if (GCPhysVirtApic != GCPhysApicAccess)
6053 { /* likely */ }
6054 else
6055 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6056 }
6057 }
6058
6059 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6060 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6061 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6062 { /* likely */ }
6063 else
6064 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6065
6066 /* Virtual-interrupt delivery requires external interrupt exiting. */
6067 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6068 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6069 { /* likely */ }
6070 else
6071 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6072
6073 /* VPID. */
6074 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6075 || pVmcs->u16Vpid != 0)
6076 { /* likely */ }
6077 else
6078 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6079
6080 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6081 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6082 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6083 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6084 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6085 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6086 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6087 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6088
6089 /* VMCS shadowing. */
6090 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6091 {
6092 /* VMREAD-bitmap physical address. */
6093 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6094 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6095 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6096 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6097 { /* likely */ }
6098 else
6099 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6100
6101 /* VMWRITE-bitmap physical address. */
6102 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6103 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6104 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6105 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6106 { /* likely */ }
6107 else
6108 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6109 }
6110 }
6111
6112 /*
6113 * VM-exit controls.
6114 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6115 */
6116 {
6117 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6118 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6119 { /* likely */ }
6120 else
6121 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6122
6123 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6124 { /* likely */ }
6125 else
6126 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6127
6128 /* Save preemption timer without activating it. */
6129 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6130 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6131 { /* likely */ }
6132 else
6133 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6134
6135 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6136 if (pVmcs->u32ExitMsrStoreCount)
6137 {
6138 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6139 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6140 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6141 { /* likely */ }
6142 else
6143 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6144 }
6145
6146 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6147 if (pVmcs->u32ExitMsrLoadCount)
6148 {
6149 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6150 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6151 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6152 { /* likely */ }
6153 else
6154 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6155 }
6156 }
6157
6158 /*
6159 * VM-entry controls.
6160 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6161 */
6162 {
6163 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6164 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6165 { /* likely */ }
6166 else
6167 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6168
6169 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6170 { /* likely */ }
6171 else
6172 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6173
6174 /* Event injection. */
6175 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6176 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6177 {
6178 /* Type and vector. */
6179 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6180 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6181 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6182 if ( !uRsvd
6183 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6184 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6185 { /* likely */ }
6186 else
6187 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6188
6189 /* Exception error code. */
6190 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6191 {
6192 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6193 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6194 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6195 { /* likely */ }
6196 else
6197 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6198
6199 /* Exceptions that provide an error code. */
6200 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6201 && ( uVector == X86_XCPT_DF
6202 || uVector == X86_XCPT_TS
6203 || uVector == X86_XCPT_NP
6204 || uVector == X86_XCPT_SS
6205 || uVector == X86_XCPT_GP
6206 || uVector == X86_XCPT_PF
6207 || uVector == X86_XCPT_AC))
6208 { /* likely */ }
6209 else
6210 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6211
6212 /* Exception error-code reserved bits. */
6213 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6214 { /* likely */ }
6215 else
6216 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6217
6218 /* Injecting a software interrupt, software exception or privileged software exception. */
6219 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6220 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6221 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6222 {
6223 /* Instruction length must be in the range 0-15. */
6224 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6225 { /* likely */ }
6226 else
6227 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6228
6229 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6230 if ( pVmcs->u32EntryInstrLen != 0
6231 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6232 { /* likely */ }
6233 else
6234 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6235 }
6236 }
6237 }
6238
6239 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6240 if (pVmcs->u32EntryMsrLoadCount)
6241 {
6242 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6243 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6244 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6245 { /* likely */ }
6246 else
6247 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6248 }
6249
6250 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6251 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6252 }
6253
6254 NOREF(pszInstr);
6255 NOREF(pszFailure);
6256 return VINF_SUCCESS;
6257}
6258
6259
6260/**
6261 * Loads the guest control registers, debug register and some MSRs as part of
6262 * VM-entry.
6263 *
6264 * @param pVCpu The cross context virtual CPU structure.
6265 */
6266IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6267{
6268 /*
6269 * Load guest control registers, debug registers and MSRs.
6270 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6271 */
6272 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6273
6274 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6275 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6276 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6277 CPUMSetGuestCR0(pVCpu, uGstCr0);
6278 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6279 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6280
6281 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6282 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6283
6284 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6285 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6286 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6287
6288 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6289 {
6290 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6291
6292 /* EFER MSR. */
6293 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6294 {
6295 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6296 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6297 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6298 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6299 if (fGstInLongMode)
6300 {
6301 /* If the nested-guest is in long mode, LMA and LME are both set. */
6302 Assert(fGstPaging);
6303 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6304 }
6305 else
6306 {
6307 /*
6308 * If the nested-guest is outside long mode:
6309 * - With paging: LMA is cleared, LME is cleared.
6310 * - Without paging: LMA is cleared, LME is left unmodified.
6311 */
6312 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6313 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6314 }
6315 }
6316 /* else: see below. */
6317 }
6318
6319 /* PAT MSR. */
6320 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6321 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6322
6323 /* EFER MSR. */
6324 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6325 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6326
6327 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6328 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6329
6330 /* We don't support IA32_BNDCFGS MSR yet. */
6331 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6332
6333 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6334}
6335
6336
6337/**
6338 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6339 *
6340 * @param pVCpu The cross context virtual CPU structure.
6341 */
6342IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6343{
6344 /*
6345 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6346 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6347 */
6348 /* CS, SS, ES, DS, FS, GS. */
6349 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6350 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6351 {
6352 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6353 CPUMSELREG VmcsSelReg;
6354 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6355 AssertRC(rc); NOREF(rc);
6356 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6357 {
6358 pGstSelReg->Sel = VmcsSelReg.Sel;
6359 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6360 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6361 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6362 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6363 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6364 }
6365 else
6366 {
6367 pGstSelReg->Sel = VmcsSelReg.Sel;
6368 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6369 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6370 switch (iSegReg)
6371 {
6372 case X86_SREG_CS:
6373 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6374 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6375 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6376 break;
6377
6378 case X86_SREG_SS:
6379 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6380 pGstSelReg->u32Limit = 0;
6381 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6382 break;
6383
6384 case X86_SREG_ES:
6385 case X86_SREG_DS:
6386 pGstSelReg->u64Base = 0;
6387 pGstSelReg->u32Limit = 0;
6388 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6389 break;
6390
6391 case X86_SREG_FS:
6392 case X86_SREG_GS:
6393 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6394 pGstSelReg->u32Limit = 0;
6395 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6396 break;
6397 }
6398 Assert(pGstSelReg->Attr.n.u1Unusable);
6399 }
6400 }
6401
6402 /* LDTR. */
6403 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6404 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6405 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6406 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6407 {
6408 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6409 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6410 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6411 }
6412 else
6413 {
6414 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6415 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6416 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6417 }
6418
6419 /* TR. */
6420 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6421 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6422 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6423 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6424 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6425 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6426 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6427
6428 /* GDTR. */
6429 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6430 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6431
6432 /* IDTR. */
6433 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6434 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6435}
6436
6437
6438/**
6439 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6440 *
6441 * @returns VBox status code.
6442 * @param pVCpu The cross context virtual CPU structure.
6443 * @param pszInstr The VMX instruction name (for logging purposes).
6444 */
6445IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6446{
6447 /*
6448 * Load guest MSRs.
6449 * See Intel spec. 26.4 "Loading MSRs".
6450 */
6451 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6452 const char *const pszFailure = "VM-exit";
6453
6454 /*
6455 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6456 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6457 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6458 */
6459 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6460 if (!cMsrs)
6461 return VINF_SUCCESS;
6462
6463 /*
6464 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6465 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6466 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6467 */
6468 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6469 if (fIsMsrCountValid)
6470 { /* likely */ }
6471 else
6472 {
6473 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6474 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6475 }
6476
6477 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6478 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6479 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6480 if (RT_SUCCESS(rc))
6481 {
6482 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6483 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6484 {
6485 if ( !pMsr->u32Reserved
6486 && pMsr->u32Msr != MSR_K8_FS_BASE
6487 && pMsr->u32Msr != MSR_K8_GS_BASE
6488 && pMsr->u32Msr != MSR_K6_EFER
6489 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6490 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6491 {
6492 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6493 if (rcStrict == VINF_SUCCESS)
6494 continue;
6495
6496 /*
6497 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6498 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6499 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6500 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6501 * MSR in ring-0 if possible, or come up with a better, generic solution.
6502 */
6503 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6504 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6505 ? kVmxVDiag_Vmentry_MsrLoadRing3
6506 : kVmxVDiag_Vmentry_MsrLoad;
6507 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6508 }
6509 else
6510 {
6511 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6512 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6513 }
6514 }
6515 }
6516 else
6517 {
6518 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6519 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6520 }
6521
6522 NOREF(pszInstr);
6523 NOREF(pszFailure);
6524 return VINF_SUCCESS;
6525}
6526
6527
6528/**
6529 * Loads the guest-state non-register state as part of VM-entry.
6530 *
6531 * @returns VBox status code.
6532 * @param pVCpu The cross context virtual CPU structure.
6533 *
6534 * @remarks This must be called only after loading the nested-guest register state
6535 * (especially nested-guest RIP).
6536 */
6537IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu)
6538{
6539 /*
6540 * Load guest non-register state.
6541 * See Intel spec. 26.6 "Special Features of VM Entry"
6542 */
6543 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6544
6545 /*
6546 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6547 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6548 *
6549 * See Intel spec. 26.6.1 "Interruptibility State".
6550 */
6551 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6552 if ( !fEntryVectoring
6553 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6554 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6555 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6556 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6557
6558 /* NMI blocking. */
6559 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6560 {
6561 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6562 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6563 else
6564 {
6565 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6566 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6567 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6568 }
6569 }
6570 else
6571 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6572
6573 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6574
6575 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6576 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6577
6578 /* VPID is irrelevant. We don't support VPID yet. */
6579
6580 /* Clear address-range monitoring. */
6581 EMMonitorWaitClear(pVCpu);
6582}
6583
6584
6585/**
6586 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
6587 *
6588 * @param pVCpu The cross context virtual CPU structure.
6589 * @param pszInstr The VMX instruction name (for logging purposes).
6590 *
6591 * @remarks This assumes various VMCS related data structure pointers have already
6592 * been verified prior to calling this function.
6593 */
6594IEM_STATIC int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr)
6595{
6596 const char *const pszFailure = "VM-exit";
6597 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6598
6599 /*
6600 * Virtualize APIC accesses.
6601 */
6602 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6603 {
6604 /* APIC-access physical address. */
6605 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6606
6607 /*
6608 * Register the handler for the APIC-access page.
6609 *
6610 * We don't deregister the APIC-access page handler during the VM-exit as a different
6611 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6612 *
6613 * We leave the page registered until the first access that happens outside VMX non-root
6614 * mode. Guest software is allowed to access structures such as the APIC-access page
6615 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6616 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6617 *
6618 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6619 */
6620 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6621 {
6622 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6623 PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
6624 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6625 pVCpu0->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6626 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6627 if (RT_SUCCESS(rc))
6628 { /* likely */ }
6629 else
6630 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6631 }
6632 }
6633
6634 /*
6635 * VMCS shadowing.
6636 */
6637 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6638 {
6639 /* Read the VMREAD-bitmap. */
6640 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6641 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
6642 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
6643 if (RT_SUCCESS(rc))
6644 { /* likely */ }
6645 else
6646 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6647
6648 /* Read the VMWRITE-bitmap. */
6649 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
6650 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
6651 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
6652 if (RT_SUCCESS(rc))
6653 { /* likely */ }
6654 else
6655 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6656 }
6657
6658 /*
6659 * I/O bitmaps.
6660 */
6661 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6662 {
6663 /* Read the IO bitmap A. */
6664 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6665 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
6666 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
6667 if (RT_SUCCESS(rc))
6668 { /* likely */ }
6669 else
6670 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
6671
6672 /* Read the IO bitmap B. */
6673 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6674 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
6675 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
6676 if (RT_SUCCESS(rc))
6677 { /* likely */ }
6678 else
6679 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
6680 }
6681
6682 /*
6683 * TPR shadow and Virtual-APIC page.
6684 */
6685 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6686 {
6687 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6688 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6689 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6690 {
6691 /* Read the VTPR from the virtual-APIC page. */
6692 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6693 uint8_t u8VTpr;
6694 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6695 if (RT_SUCCESS(rc))
6696 { /* likely */ }
6697 else
6698 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6699
6700 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6701 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6702 { /* likely */ }
6703 else
6704 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6705 }
6706 }
6707
6708 /*
6709 * VMCS link pointer.
6710 */
6711 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6712 {
6713 /* Read the VMCS-link pointer from guest memory. */
6714 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6715 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
6716 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
6717 if (RT_SUCCESS(rc))
6718 { /* likely */ }
6719 else
6720 {
6721 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6722 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6723 }
6724
6725 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6726 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6727 { /* likely */ }
6728 else
6729 {
6730 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6731 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6732 }
6733
6734 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6735 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6736 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
6737 { /* likely */ }
6738 else
6739 {
6740 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6741 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6742 }
6743
6744 /* Update our cache of the guest physical address of the shadow VMCS. */
6745 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6746 }
6747
6748 /*
6749 * MSR bitmap.
6750 */
6751 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6752 {
6753 /* Read the MSR bitmap. */
6754 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6755 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
6756 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
6757 if (RT_SUCCESS(rc))
6758 { /* likely */ }
6759 else
6760 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6761 }
6762
6763 NOREF(pszFailure);
6764 NOREF(pszInstr);
6765 return VINF_SUCCESS;
6766}
6767
6768
6769/**
6770 * Loads the guest-state as part of VM-entry.
6771 *
6772 * @returns VBox status code.
6773 * @param pVCpu The cross context virtual CPU structure.
6774 * @param pszInstr The VMX instruction name (for logging purposes).
6775 *
6776 * @remarks This must be done after all the necessary steps prior to loading of
6777 * guest-state (e.g. checking various VMCS state).
6778 */
6779IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6780{
6781 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
6782 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6783
6784 /* Load guest segment registers. */
6785 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6786
6787 /*
6788 * Load guest RIP, RSP and RFLAGS.
6789 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6790 */
6791 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6792 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6793 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6794 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6795
6796 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6797 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6798 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6799
6800 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
6801 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6802
6803 /* Load VMX related structures and state referenced by the VMCS. */
6804 int rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
6805 if (rc == VINF_SUCCESS)
6806 { /* likely */ }
6807 else
6808 return rc;
6809
6810 NOREF(pszInstr);
6811 return VINF_SUCCESS;
6812}
6813
6814
6815/**
6816 * Returns whether there are is a pending debug exception on VM-entry.
6817 *
6818 * @param pVCpu The cross context virtual CPU structure.
6819 * @param pszInstr The VMX instruction name (for logging purposes).
6820 */
6821IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6822{
6823 /*
6824 * Pending debug exceptions.
6825 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6826 */
6827 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6828 Assert(pVmcs);
6829
6830 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6831 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6832 if (fPendingDbgXcpt)
6833 {
6834 uint8_t uEntryIntInfoType;
6835 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6836 if (fEntryVectoring)
6837 {
6838 switch (uEntryIntInfoType)
6839 {
6840 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6841 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6842 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6843 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6844 fPendingDbgXcpt = false;
6845 break;
6846
6847 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6848 {
6849 /*
6850 * Whether the pending debug exception for software exceptions other than
6851 * #BP and #OF is delivered after injecting the exception or is discard
6852 * is CPU implementation specific. We will discard them (easier).
6853 */
6854 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6855 if ( uVector != X86_XCPT_BP
6856 && uVector != X86_XCPT_OF)
6857 fPendingDbgXcpt = false;
6858 RT_FALL_THRU();
6859 }
6860 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6861 {
6862 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6863 fPendingDbgXcpt = false;
6864 break;
6865 }
6866 }
6867 }
6868 else
6869 {
6870 /*
6871 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6872 * pending debug exception is held pending or is discarded is CPU implementation
6873 * specific. We will discard them (easier).
6874 */
6875 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6876 fPendingDbgXcpt = false;
6877
6878 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
6879 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
6880 fPendingDbgXcpt = false;
6881 }
6882 }
6883
6884 NOREF(pszInstr);
6885 return fPendingDbgXcpt;
6886}
6887
6888
6889/**
6890 * Set up the monitor-trap flag (MTF).
6891 *
6892 * @param pVCpu The cross context virtual CPU structure.
6893 * @param pszInstr The VMX instruction name (for logging purposes).
6894 */
6895IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
6896{
6897 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6898 Assert(pVmcs);
6899 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
6900 {
6901 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
6902 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
6903 }
6904 else
6905 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
6906 NOREF(pszInstr);
6907}
6908
6909
6910/**
6911 * Sets up NMI-window exiting.
6912 *
6913 * @param pVCpu The cross context virtual CPU structure.
6914 * @param pszInstr The VMX instruction name (for logging purposes).
6915 */
6916IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
6917{
6918 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6919 Assert(pVmcs);
6920 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
6921 {
6922 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
6923 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
6924 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
6925 }
6926 else
6927 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
6928 NOREF(pszInstr);
6929}
6930
6931
6932/**
6933 * Sets up interrupt-window exiting.
6934 *
6935 * @param pVCpu The cross context virtual CPU structure.
6936 * @param pszInstr The VMX instruction name (for logging purposes).
6937 */
6938IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
6939{
6940 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6941 Assert(pVmcs);
6942 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
6943 {
6944 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
6945 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
6946 }
6947 else
6948 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
6949 NOREF(pszInstr);
6950}
6951
6952
6953/**
6954 * Set up the VMX-preemption timer.
6955 *
6956 * @param pVCpu The cross context virtual CPU structure.
6957 * @param pszInstr The VMX instruction name (for logging purposes).
6958 */
6959IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
6960{
6961 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6962 Assert(pVmcs);
6963 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6964 {
6965 /*
6966 * If the timer is 0, we must cause a VM-exit before executing the first
6967 * nested-guest instruction. So we can flag as though the timer has already
6968 * expired and we will check and cause a VM-exit at the right priority elsewhere
6969 * in the code.
6970 */
6971 uint64_t uEntryTick;
6972 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
6973 if (uPreemptTimer)
6974 {
6975 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
6976 AssertRC(rc);
6977 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
6978 }
6979 else
6980 {
6981 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
6982 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
6983 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
6984 }
6985
6986 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
6987 }
6988 else
6989 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
6990
6991 NOREF(pszInstr);
6992}
6993
6994
6995/**
6996 * Injects an event using TRPM given a VM-entry interruption info. and related
6997 * fields.
6998 *
6999 * @param pVCpu The cross context virtual CPU structure.
7000 * @param pszInstr The VMX instruction name (for logging purposes).
7001 * @param uEntryIntInfo The VM-entry interruption info.
7002 * @param uErrCode The error code associated with the event if any.
7003 * @param cbInstr The VM-entry instruction length (for software
7004 * interrupts and software exceptions). Pass 0
7005 * otherwise.
7006 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7007 */
7008IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7009 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7010{
7011 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7012
7013 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7014 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7015 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7016
7017 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7018
7019 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7020 AssertRC(rc);
7021 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7022
7023 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7024 {
7025 TRPMSetErrorCode(pVCpu, uErrCode);
7026 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7027 }
7028
7029 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7030 {
7031 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7032 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7033 }
7034 else
7035 {
7036 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7037 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7038 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7039 {
7040 TRPMSetInstrLength(pVCpu, cbInstr);
7041 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7042 }
7043 }
7044
7045 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7046 {
7047 TRPMSetTrapDueToIcebp(pVCpu);
7048 Log(("%s: Injecting: icebp\n", pszInstr));
7049 }
7050
7051 NOREF(pszInstr);
7052}
7053
7054
7055/**
7056 * Performs event injection (if any) as part of VM-entry.
7057 *
7058 * @param pVCpu The cross context virtual CPU structure.
7059 * @param pszInstr The VMX instruction name (for logging purposes).
7060 */
7061IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7062{
7063 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7064
7065 /*
7066 * Inject events.
7067 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7068 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7069 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7070 * the actually delivery of this event.
7071 *
7072 * See Intel spec. 26.5 "Event Injection".
7073 */
7074 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7075 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7076
7077 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7078 if (fEntryIntInfoValid)
7079 {
7080 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7081 {
7082 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7083 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7084 }
7085 else
7086 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7087 pVCpu->cpum.GstCtx.cr2);
7088
7089 /*
7090 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7091 *
7092 * However, we do it here on VM-entry as well because while it isn't visible to guest
7093 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7094 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7095 *
7096 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7097 */
7098 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7099 }
7100 else
7101 {
7102 /*
7103 * Inject any pending guest debug exception.
7104 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7105 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7106 */
7107 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7108 if (fPendingDbgXcpt)
7109 {
7110 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7111 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7112 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7113 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7114 0 /* GCPtrFaultAddress */);
7115 }
7116 }
7117
7118 NOREF(pszInstr);
7119}
7120
7121
7122/**
7123 * Initializes all read-only VMCS fields as part of VM-entry.
7124 *
7125 * @param pVCpu The cross context virtual CPU structure.
7126 */
7127IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7128{
7129 /*
7130 * Any VMCS field which we do not establish on every VM-exit but may potentially
7131 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7132 * specified to be undefined, needs to be initialized here.
7133 *
7134 * Thus, it is especially important to clear the Exit qualification field
7135 * since it must be zero for VM-exits where it is not used. Similarly, the
7136 * VM-exit interruption information field's valid bit needs to be cleared for
7137 * the same reasons.
7138 */
7139 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7140 Assert(pVmcs);
7141
7142 /* 16-bit (none currently). */
7143 /* 32-bit. */
7144 pVmcs->u32RoVmInstrError = 0;
7145 pVmcs->u32RoExitReason = 0;
7146 pVmcs->u32RoExitIntInfo = 0;
7147 pVmcs->u32RoExitIntErrCode = 0;
7148 pVmcs->u32RoIdtVectoringInfo = 0;
7149 pVmcs->u32RoIdtVectoringErrCode = 0;
7150 pVmcs->u32RoExitInstrLen = 0;
7151 pVmcs->u32RoExitInstrInfo = 0;
7152
7153 /* 64-bit. */
7154 pVmcs->u64RoGuestPhysAddr.u = 0;
7155
7156 /* Natural-width. */
7157 pVmcs->u64RoExitQual.u = 0;
7158 pVmcs->u64RoIoRcx.u = 0;
7159 pVmcs->u64RoIoRsi.u = 0;
7160 pVmcs->u64RoIoRdi.u = 0;
7161 pVmcs->u64RoIoRip.u = 0;
7162 pVmcs->u64RoGuestLinearAddr.u = 0;
7163}
7164
7165
7166/**
7167 * VMLAUNCH/VMRESUME instruction execution worker.
7168 *
7169 * @returns Strict VBox status code.
7170 * @param pVCpu The cross context virtual CPU structure.
7171 * @param cbInstr The instruction length in bytes.
7172 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7173 * VMXINSTRID_VMRESUME).
7174 *
7175 * @remarks Common VMX instruction checks are already expected to by the caller,
7176 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7177 */
7178IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7179{
7180# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7181 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7182 return VINF_EM_RAW_EMULATE_INSTR;
7183# else
7184 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7185 || uInstrId == VMXINSTRID_VMRESUME);
7186 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7187
7188 /* Nested-guest intercept. */
7189 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7190 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7191
7192 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7193
7194 /*
7195 * Basic VM-entry checks.
7196 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7197 * The checks following that do not have to follow a specific order.
7198 *
7199 * See Intel spec. 26.1 "Basic VM-entry Checks".
7200 */
7201
7202 /* CPL. */
7203 if (pVCpu->iem.s.uCpl == 0)
7204 { /* likely */ }
7205 else
7206 {
7207 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7208 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7209 return iemRaiseGeneralProtectionFault0(pVCpu);
7210 }
7211
7212 /* Current VMCS valid. */
7213 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7214 { /* likely */ }
7215 else
7216 {
7217 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7218 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7219 iemVmxVmFailInvalid(pVCpu);
7220 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7221 return VINF_SUCCESS;
7222 }
7223
7224 /* Current VMCS is not a shadow VMCS. */
7225 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7226 { /* likely */ }
7227 else
7228 {
7229 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7230 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7231 iemVmxVmFailInvalid(pVCpu);
7232 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7233 return VINF_SUCCESS;
7234 }
7235
7236 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7237 * use block-by-STI here which is not quite correct. */
7238 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7239 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7240 { /* likely */ }
7241 else
7242 {
7243 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7244 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7245 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7246 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7247 return VINF_SUCCESS;
7248 }
7249
7250 if (uInstrId == VMXINSTRID_VMLAUNCH)
7251 {
7252 /* VMLAUNCH with non-clear VMCS. */
7253 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7254 { /* likely */ }
7255 else
7256 {
7257 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7258 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7259 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7260 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7261 return VINF_SUCCESS;
7262 }
7263 }
7264 else
7265 {
7266 /* VMRESUME with non-launched VMCS. */
7267 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7268 { /* likely */ }
7269 else
7270 {
7271 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7272 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7273 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7274 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7275 return VINF_SUCCESS;
7276 }
7277 }
7278
7279 /*
7280 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7281 * while entering VMX non-root mode. We do some of this while checking VM-execution
7282 * controls. The nested hypervisor should not make assumptions and cannot expect
7283 * predictable behavior if changes to these structures are made in guest memory while
7284 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7285 * modify them anyway as we cache them in host memory.
7286 *
7287 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7288 */
7289 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7290 Assert(pVmcs);
7291 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7292
7293 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7294 if (RT_SUCCESS(rc))
7295 {
7296 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7297 if (RT_SUCCESS(rc))
7298 {
7299 /*
7300 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7301 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7302 * ones that may occur during VM-entry below).
7303 */
7304 iemVmxVmentryInitReadOnlyFields(pVCpu);
7305
7306 /*
7307 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7308 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7309 * VM-exit when required.
7310 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7311 */
7312 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7313
7314 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7315 if (RT_SUCCESS(rc))
7316 {
7317 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7318 if (RT_SUCCESS(rc))
7319 {
7320 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7321 if (RT_SUCCESS(rc))
7322 {
7323 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7324
7325 /* VMLAUNCH instruction must update the VMCS launch state. */
7326 if (uInstrId == VMXINSTRID_VMLAUNCH)
7327 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7328
7329 /* Perform the VMX transition (PGM updates). */
7330 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7331 if (rcStrict == VINF_SUCCESS)
7332 { /* likely */ }
7333 else if (RT_SUCCESS(rcStrict))
7334 {
7335 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7336 VBOXSTRICTRC_VAL(rcStrict)));
7337 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7338 }
7339 else
7340 {
7341 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7342 return rcStrict;
7343 }
7344
7345 /* Paranoia. */
7346 Assert(rcStrict == VINF_SUCCESS);
7347
7348 /* We've now entered nested-guest execution. */
7349 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7350
7351 /*
7352 * The priority of potential VM-exits during VM-entry is important.
7353 * The priorities of VM-exits and events are listed from highest
7354 * to lowest as follows:
7355 *
7356 * 1. Event injection.
7357 * 2. Trap on task-switch (T flag set in TSS).
7358 * 3. TPR below threshold / APIC-write.
7359 * 4. SMI, INIT.
7360 * 5. MTF exit.
7361 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7362 * 7. VMX-preemption timer.
7363 * 9. NMI-window exit.
7364 * 10. NMI injection.
7365 * 11. Interrupt-window exit.
7366 * 12. Virtual-interrupt injection.
7367 * 13. Interrupt injection.
7368 * 14. Process next instruction (fetch, decode, execute).
7369 */
7370
7371 /* Setup VMX-preemption timer. */
7372 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7373
7374 /* Setup monitor-trap flag. */
7375 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7376
7377 /* Setup NMI-window exiting. */
7378 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7379
7380 /* Setup interrupt-window exiting. */
7381 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7382
7383 /*
7384 * Inject any event that the nested hypervisor wants to inject.
7385 * Note! We cannot immediately perform the event injection here as we may have
7386 * pending PGM operations to perform due to switching page tables and/or
7387 * mode.
7388 */
7389 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7390
7391# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7392 /* Reschedule to IEM-only execution of the nested-guest. */
7393 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7394 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7395 if (rcSched != VINF_SUCCESS)
7396 iemSetPassUpStatus(pVCpu, rcSched);
7397# endif
7398
7399 /* Finally, done. */
7400 Log3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",
7401 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7402 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7403 pVCpu->cpum.GstCtx.msrEFER));
7404 return VINF_SUCCESS;
7405 }
7406 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7407 pVmcs->u64RoExitQual.u);
7408 }
7409 }
7410 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7411 pVmcs->u64RoExitQual.u);
7412 }
7413
7414 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7415 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7416 return VINF_SUCCESS;
7417 }
7418
7419 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7420 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7421 return VINF_SUCCESS;
7422# endif
7423}
7424
7425
7426/**
7427 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7428 * (causes a VM-exit) or not.
7429 *
7430 * @returns @c true if the instruction is intercepted, @c false otherwise.
7431 * @param pVCpu The cross context virtual CPU structure.
7432 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7433 * VMX_EXIT_WRMSR).
7434 * @param idMsr The MSR.
7435 */
7436IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7437{
7438 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7439 Assert( uExitReason == VMX_EXIT_RDMSR
7440 || uExitReason == VMX_EXIT_WRMSR);
7441
7442 /* Consult the MSR bitmap if the feature is supported. */
7443 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7444 Assert(pVmcs);
7445 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7446 {
7447 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7448 if (uExitReason == VMX_EXIT_RDMSR)
7449 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7450 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7451 }
7452
7453 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7454 return true;
7455}
7456
7457
7458/**
7459 * VMREAD instruction execution worker that does not perform any validation checks.
7460 *
7461 * Callers are expected to have performed the necessary checks and to ensure the
7462 * VMREAD will succeed.
7463 *
7464 * @param pVmcs Pointer to the virtual VMCS.
7465 * @param pu64Dst Where to write the VMCS value.
7466 * @param u64VmcsField The VMCS field.
7467 *
7468 * @remarks May be called with interrupts disabled.
7469 */
7470IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7471{
7472 VMXVMCSFIELD VmcsField;
7473 VmcsField.u = u64VmcsField;
7474 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7475 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7476 uint8_t const uWidthType = (uWidth << 2) | uType;
7477 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7478 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7479 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7480 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
7481 uWidth, uType, uIndex, uIndex));
7482 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7483
7484 /*
7485 * Read the VMCS component based on the field's effective width.
7486 *
7487 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7488 * indicates high bits (little endian).
7489 *
7490 * Note! The caller is responsible to trim the result and update registers
7491 * or memory locations are required. Here we just zero-extend to the largest
7492 * type (i.e. 64-bits).
7493 */
7494 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7495 uint8_t const *pbField = pbVmcs + offField;
7496 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7497 switch (uEffWidth)
7498 {
7499 case VMX_VMCSFIELD_WIDTH_64BIT:
7500 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7501 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7502 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7503 }
7504}
7505
7506
7507/**
7508 * VMREAD common (memory/register) instruction execution worker.
7509 *
7510 * @returns Strict VBox status code.
7511 * @param pVCpu The cross context virtual CPU structure.
7512 * @param cbInstr The instruction length in bytes.
7513 * @param pu64Dst Where to write the VMCS value (only updated when
7514 * VINF_SUCCESS is returned).
7515 * @param u64VmcsField The VMCS field.
7516 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7517 * NULL.
7518 */
7519IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7520 PCVMXVEXITINFO pExitInfo)
7521{
7522 /* Nested-guest intercept. */
7523 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7524 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7525 {
7526 if (pExitInfo)
7527 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7528 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7529 }
7530
7531 /* CPL. */
7532 if (pVCpu->iem.s.uCpl == 0)
7533 { /* likely */ }
7534 else
7535 {
7536 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7537 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7538 return iemRaiseGeneralProtectionFault0(pVCpu);
7539 }
7540
7541 /* VMCS pointer in root mode. */
7542 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7543 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7544 { /* likely */ }
7545 else
7546 {
7547 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7548 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7549 iemVmxVmFailInvalid(pVCpu);
7550 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7551 return VINF_SUCCESS;
7552 }
7553
7554 /* VMCS-link pointer in non-root mode. */
7555 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7556 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7557 { /* likely */ }
7558 else
7559 {
7560 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7561 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7562 iemVmxVmFailInvalid(pVCpu);
7563 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7564 return VINF_SUCCESS;
7565 }
7566
7567 /* Supported VMCS field. */
7568 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7569 { /* likely */ }
7570 else
7571 {
7572 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7573 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7574 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7575 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7576 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7577 return VINF_SUCCESS;
7578 }
7579
7580 /*
7581 * Reading from the current or shadow VMCS.
7582 */
7583 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7584 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7585 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7586 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7587 return VINF_SUCCESS;
7588}
7589
7590
7591/**
7592 * VMREAD (64-bit register) instruction execution worker.
7593 *
7594 * @returns Strict VBox status code.
7595 * @param pVCpu The cross context virtual CPU structure.
7596 * @param cbInstr The instruction length in bytes.
7597 * @param pu64Dst Where to store the VMCS field's value.
7598 * @param u64VmcsField The VMCS field.
7599 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7600 * NULL.
7601 */
7602IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7603 PCVMXVEXITINFO pExitInfo)
7604{
7605 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7606 if (rcStrict == VINF_SUCCESS)
7607 {
7608 iemVmxVmreadSuccess(pVCpu, cbInstr);
7609 return VINF_SUCCESS;
7610 }
7611
7612 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7613 return rcStrict;
7614}
7615
7616
7617/**
7618 * VMREAD (32-bit register) instruction execution worker.
7619 *
7620 * @returns Strict VBox status code.
7621 * @param pVCpu The cross context virtual CPU structure.
7622 * @param cbInstr The instruction length in bytes.
7623 * @param pu32Dst Where to store the VMCS field's value.
7624 * @param u32VmcsField The VMCS field.
7625 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7626 * NULL.
7627 */
7628IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7629 PCVMXVEXITINFO pExitInfo)
7630{
7631 uint64_t u64Dst;
7632 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7633 if (rcStrict == VINF_SUCCESS)
7634 {
7635 *pu32Dst = u64Dst;
7636 iemVmxVmreadSuccess(pVCpu, cbInstr);
7637 return VINF_SUCCESS;
7638 }
7639
7640 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7641 return rcStrict;
7642}
7643
7644
7645/**
7646 * VMREAD (memory) instruction execution worker.
7647 *
7648 * @returns Strict VBox status code.
7649 * @param pVCpu The cross context virtual CPU structure.
7650 * @param cbInstr The instruction length in bytes.
7651 * @param iEffSeg The effective segment register to use with @a u64Val.
7652 * Pass UINT8_MAX if it is a register access.
7653 * @param GCPtrDst The guest linear address to store the VMCS field's
7654 * value.
7655 * @param u64VmcsField The VMCS field.
7656 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7657 * NULL.
7658 */
7659IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7660 PCVMXVEXITINFO pExitInfo)
7661{
7662 uint64_t u64Dst;
7663 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7664 if (rcStrict == VINF_SUCCESS)
7665 {
7666 /*
7667 * Write the VMCS field's value to the location specified in guest-memory.
7668 */
7669 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7670 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7671 else
7672 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7673 if (rcStrict == VINF_SUCCESS)
7674 {
7675 iemVmxVmreadSuccess(pVCpu, cbInstr);
7676 return VINF_SUCCESS;
7677 }
7678
7679 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7680 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7681 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7682 return rcStrict;
7683 }
7684
7685 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7686 return rcStrict;
7687}
7688
7689
7690/**
7691 * VMWRITE instruction execution worker that does not perform any validation
7692 * checks.
7693 *
7694 * Callers are expected to have performed the necessary checks and to ensure the
7695 * VMWRITE will succeed.
7696 *
7697 * @param pVmcs Pointer to the virtual VMCS.
7698 * @param u64Val The value to write.
7699 * @param u64VmcsField The VMCS field.
7700 *
7701 * @remarks May be called with interrupts disabled.
7702 */
7703IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7704{
7705 VMXVMCSFIELD VmcsField;
7706 VmcsField.u = u64VmcsField;
7707 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7708 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7709 uint8_t const uWidthType = (uWidth << 2) | uType;
7710 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7711 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7712 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7713 Assert(offField < VMX_V_VMCS_SIZE);
7714 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7715
7716 /*
7717 * Write the VMCS component based on the field's effective width.
7718 *
7719 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7720 * indicates high bits (little endian).
7721 */
7722 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7723 uint8_t *pbField = pbVmcs + offField;
7724 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7725 switch (uEffWidth)
7726 {
7727 case VMX_VMCSFIELD_WIDTH_64BIT:
7728 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7729 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7730 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7731 }
7732}
7733
7734
7735/**
7736 * VMWRITE instruction execution worker.
7737 *
7738 * @returns Strict VBox status code.
7739 * @param pVCpu The cross context virtual CPU structure.
7740 * @param cbInstr The instruction length in bytes.
7741 * @param iEffSeg The effective segment register to use with @a u64Val.
7742 * Pass UINT8_MAX if it is a register access.
7743 * @param u64Val The value to write (or guest linear address to the
7744 * value), @a iEffSeg will indicate if it's a memory
7745 * operand.
7746 * @param u64VmcsField The VMCS field.
7747 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7748 * NULL.
7749 */
7750IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7751 PCVMXVEXITINFO pExitInfo)
7752{
7753 /* Nested-guest intercept. */
7754 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7755 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7756 {
7757 if (pExitInfo)
7758 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7759 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7760 }
7761
7762 /* CPL. */
7763 if (pVCpu->iem.s.uCpl == 0)
7764 { /* likely */ }
7765 else
7766 {
7767 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7768 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7769 return iemRaiseGeneralProtectionFault0(pVCpu);
7770 }
7771
7772 /* VMCS pointer in root mode. */
7773 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7774 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7775 { /* likely */ }
7776 else
7777 {
7778 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7779 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7780 iemVmxVmFailInvalid(pVCpu);
7781 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7782 return VINF_SUCCESS;
7783 }
7784
7785 /* VMCS-link pointer in non-root mode. */
7786 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7787 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7788 { /* likely */ }
7789 else
7790 {
7791 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7792 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7793 iemVmxVmFailInvalid(pVCpu);
7794 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7795 return VINF_SUCCESS;
7796 }
7797
7798 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7799 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7800 if (!fIsRegOperand)
7801 {
7802 /* Read the value from the specified guest memory location. */
7803 VBOXSTRICTRC rcStrict;
7804 RTGCPTR const GCPtrVal = u64Val;
7805 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7806 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7807 else
7808 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7809 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7810 {
7811 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7812 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7813 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7814 return rcStrict;
7815 }
7816 }
7817 else
7818 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7819
7820 /* Supported VMCS field. */
7821 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7822 { /* likely */ }
7823 else
7824 {
7825 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7826 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7827 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7828 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7829 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7830 return VINF_SUCCESS;
7831 }
7832
7833 /* Read-only VMCS field. */
7834 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7835 if ( !fIsFieldReadOnly
7836 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7837 { /* likely */ }
7838 else
7839 {
7840 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7841 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7842 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7843 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7844 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7845 return VINF_SUCCESS;
7846 }
7847
7848 /*
7849 * Write to the current or shadow VMCS.
7850 */
7851 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7852 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7853 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7854 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7855 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7856
7857 /* Notify HM that the VMCS content might have changed. */
7858 if (!fInVmxNonRootMode)
7859 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7860
7861 iemVmxVmSucceed(pVCpu);
7862 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7863 return VINF_SUCCESS;
7864}
7865
7866
7867/**
7868 * VMCLEAR instruction execution worker.
7869 *
7870 * @returns Strict VBox status code.
7871 * @param pVCpu The cross context virtual CPU structure.
7872 * @param cbInstr The instruction length in bytes.
7873 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7874 * @param GCPtrVmcs The linear address of the VMCS pointer.
7875 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7876 *
7877 * @remarks Common VMX instruction checks are already expected to by the caller,
7878 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7879 */
7880IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7881 PCVMXVEXITINFO pExitInfo)
7882{
7883 /* Nested-guest intercept. */
7884 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7885 {
7886 if (pExitInfo)
7887 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7888 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7889 }
7890
7891 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7892
7893 /* CPL. */
7894 if (pVCpu->iem.s.uCpl == 0)
7895 { /* likely */ }
7896 else
7897 {
7898 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7899 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7900 return iemRaiseGeneralProtectionFault0(pVCpu);
7901 }
7902
7903 /* Get the VMCS pointer from the location specified by the source memory operand. */
7904 RTGCPHYS GCPhysVmcs;
7905 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7906 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
7907 { /* likely */ }
7908 else
7909 {
7910 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
7911 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
7912 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
7913 return rcStrict;
7914 }
7915
7916 /* VMCS pointer alignment. */
7917 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
7918 { /* likely */ }
7919 else
7920 {
7921 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
7922 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
7923 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7924 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7925 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7926 return VINF_SUCCESS;
7927 }
7928
7929 /* VMCS physical-address width limits. */
7930 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
7931 { /* likely */ }
7932 else
7933 {
7934 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
7935 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
7936 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7937 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7938 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7939 return VINF_SUCCESS;
7940 }
7941
7942 /* VMCS is not the VMXON region. */
7943 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
7944 { /* likely */ }
7945 else
7946 {
7947 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
7948 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
7949 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7950 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
7951 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7952 return VINF_SUCCESS;
7953 }
7954
7955 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
7956 restriction imposed by our implementation. */
7957 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
7958 { /* likely */ }
7959 else
7960 {
7961 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
7962 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
7963 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
7964 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
7965 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7966 return VINF_SUCCESS;
7967 }
7968
7969 /*
7970 * VMCLEAR allows committing and clearing any valid VMCS pointer.
7971 *
7972 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
7973 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
7974 * to 'clear'.
7975 */
7976 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
7977 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
7978 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
7979 {
7980 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
7981 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
7982 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
7983 }
7984 else
7985 {
7986 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
7987 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
7988 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
7989 if (RT_FAILURE(rcStrict))
7990 return rcStrict;
7991 }
7992
7993 iemVmxVmSucceed(pVCpu);
7994 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7995 return VINF_SUCCESS;
7996}
7997
7998
7999/**
8000 * VMPTRST instruction execution worker.
8001 *
8002 * @returns Strict VBox status code.
8003 * @param pVCpu The cross context virtual CPU structure.
8004 * @param cbInstr The instruction length in bytes.
8005 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8006 * @param GCPtrVmcs The linear address of where to store the current VMCS
8007 * pointer.
8008 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8009 *
8010 * @remarks Common VMX instruction checks are already expected to by the caller,
8011 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8012 */
8013IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8014 PCVMXVEXITINFO pExitInfo)
8015{
8016 /* Nested-guest intercept. */
8017 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8018 {
8019 if (pExitInfo)
8020 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8021 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8022 }
8023
8024 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8025
8026 /* CPL. */
8027 if (pVCpu->iem.s.uCpl == 0)
8028 { /* likely */ }
8029 else
8030 {
8031 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8032 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8033 return iemRaiseGeneralProtectionFault0(pVCpu);
8034 }
8035
8036 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8037 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8038 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8039 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8040 {
8041 iemVmxVmSucceed(pVCpu);
8042 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8043 return rcStrict;
8044 }
8045
8046 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8047 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8048 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8049 return rcStrict;
8050}
8051
8052
8053/**
8054 * VMPTRLD instruction execution worker.
8055 *
8056 * @returns Strict VBox status code.
8057 * @param pVCpu The cross context virtual CPU structure.
8058 * @param cbInstr The instruction length in bytes.
8059 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8060 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8061 *
8062 * @remarks Common VMX instruction checks are already expected to by the caller,
8063 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8064 */
8065IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8066 PCVMXVEXITINFO pExitInfo)
8067{
8068 /* Nested-guest intercept. */
8069 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8070 {
8071 if (pExitInfo)
8072 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8073 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8074 }
8075
8076 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8077
8078 /* CPL. */
8079 if (pVCpu->iem.s.uCpl == 0)
8080 { /* likely */ }
8081 else
8082 {
8083 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8084 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8085 return iemRaiseGeneralProtectionFault0(pVCpu);
8086 }
8087
8088 /* Get the VMCS pointer from the location specified by the source memory operand. */
8089 RTGCPHYS GCPhysVmcs;
8090 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8091 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8092 { /* likely */ }
8093 else
8094 {
8095 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8096 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8097 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8098 return rcStrict;
8099 }
8100
8101 /* VMCS pointer alignment. */
8102 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8103 { /* likely */ }
8104 else
8105 {
8106 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8107 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8108 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8109 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8110 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8111 return VINF_SUCCESS;
8112 }
8113
8114 /* VMCS physical-address width limits. */
8115 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8116 { /* likely */ }
8117 else
8118 {
8119 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8120 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8121 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8122 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8123 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8124 return VINF_SUCCESS;
8125 }
8126
8127 /* VMCS is not the VMXON region. */
8128 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8129 { /* likely */ }
8130 else
8131 {
8132 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8133 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8134 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8135 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8136 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8137 return VINF_SUCCESS;
8138 }
8139
8140 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8141 restriction imposed by our implementation. */
8142 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8143 { /* likely */ }
8144 else
8145 {
8146 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8147 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8148 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8149 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8150 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8151 return VINF_SUCCESS;
8152 }
8153
8154 /* Read just the VMCS revision from the VMCS. */
8155 VMXVMCSREVID VmcsRevId;
8156 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8157 if (RT_SUCCESS(rc))
8158 { /* likely */ }
8159 else
8160 {
8161 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8162 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8163 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8164 return rc;
8165 }
8166
8167 /*
8168 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8169 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8170 */
8171 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8172 && ( !VmcsRevId.n.fIsShadowVmcs
8173 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8174 { /* likely */ }
8175 else
8176 {
8177 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8178 {
8179 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8180 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8181 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8182 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8183 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8184 return VINF_SUCCESS;
8185 }
8186
8187 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8188 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8189 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8190 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8191 return VINF_SUCCESS;
8192 }
8193
8194 /*
8195 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8196 * the cache of an existing, current VMCS back to guest memory before loading a new,
8197 * different current VMCS.
8198 */
8199 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8200 {
8201 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8202 {
8203 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8204 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8205 }
8206
8207 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8208 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8209 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8210 if (RT_SUCCESS(rc))
8211 {
8212 /* Notify HM that a new, current VMCS is loaded. */
8213 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8214 }
8215 else
8216 {
8217 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8218 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8219 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8220 return rc;
8221 }
8222 }
8223
8224 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8225 iemVmxVmSucceed(pVCpu);
8226 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8227 return VINF_SUCCESS;
8228}
8229
8230
8231/**
8232 * INVVPID instruction execution worker.
8233 *
8234 * @returns Strict VBox status code.
8235 * @param pVCpu The cross context virtual CPU structure.
8236 * @param cbInstr The instruction length in bytes.
8237 * @param iEffSeg The segment of the invvpid descriptor.
8238 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8239 * @param u64InvvpidType The invalidation type.
8240 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8241 * NULL.
8242 *
8243 * @remarks Common VMX instruction checks are already expected to by the caller,
8244 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8245 */
8246IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8247 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8248{
8249 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8250 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8251 return iemRaiseUndefinedOpcode(pVCpu);
8252
8253 /* Nested-guest intercept. */
8254 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8255 {
8256 if (pExitInfo)
8257 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8258 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8259 }
8260
8261 /* CPL. */
8262 if (pVCpu->iem.s.uCpl != 0)
8263 {
8264 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8265 return iemRaiseGeneralProtectionFault0(pVCpu);
8266 }
8267
8268 /*
8269 * Validate INVVPID invalidation type.
8270 *
8271 * The instruction specifies exactly ONE of the supported invalidation types.
8272 *
8273 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8274 * supported. In theory, it's possible for a CPU to not support flushing individual
8275 * addresses but all the other types or any other combination. We do not take any
8276 * shortcuts here by assuming the types we currently expose to the guest.
8277 */
8278 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8279 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8280 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8281 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8282 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8283 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8284 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8285 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8286 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8287 { /* likely */ }
8288 else
8289 {
8290 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8291 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8292 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8293 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8294 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8295 return VINF_SUCCESS;
8296 }
8297
8298 /*
8299 * Fetch the invvpid descriptor from guest memory.
8300 */
8301 RTUINT128U uDesc;
8302 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8303 if (rcStrict == VINF_SUCCESS)
8304 {
8305 /*
8306 * Validate the descriptor.
8307 */
8308 if (uDesc.s.Lo > 0xfff)
8309 {
8310 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8311 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8312 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8313 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8314 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8315 return VINF_SUCCESS;
8316 }
8317
8318 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8319 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8320 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8321 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8322 switch (u64InvvpidType)
8323 {
8324 case VMXTLBFLUSHVPID_INDIV_ADDR:
8325 {
8326 if (uVpid != 0)
8327 {
8328 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8329 {
8330 /* Invalidate mappings for the linear address tagged with VPID. */
8331 /** @todo PGM support for VPID? Currently just flush everything. */
8332 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8333 iemVmxVmSucceed(pVCpu);
8334 }
8335 else
8336 {
8337 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8338 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8339 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8340 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8341 }
8342 }
8343 else
8344 {
8345 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8346 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8347 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8348 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8349 }
8350 break;
8351 }
8352
8353 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8354 {
8355 if (uVpid != 0)
8356 {
8357 /* Invalidate all mappings with VPID. */
8358 /** @todo PGM support for VPID? Currently just flush everything. */
8359 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8360 iemVmxVmSucceed(pVCpu);
8361 }
8362 else
8363 {
8364 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8365 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8366 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8367 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8368 }
8369 break;
8370 }
8371
8372 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8373 {
8374 /* Invalidate all mappings with non-zero VPIDs. */
8375 /** @todo PGM support for VPID? Currently just flush everything. */
8376 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8377 iemVmxVmSucceed(pVCpu);
8378 break;
8379 }
8380
8381 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8382 {
8383 if (uVpid != 0)
8384 {
8385 /* Invalidate all mappings with VPID except global translations. */
8386 /** @todo PGM support for VPID? Currently just flush everything. */
8387 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8388 iemVmxVmSucceed(pVCpu);
8389 }
8390 else
8391 {
8392 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8393 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8394 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8395 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8396 }
8397 break;
8398 }
8399 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8400 }
8401 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8402 }
8403 return rcStrict;
8404}
8405
8406
8407/**
8408 * VMXON instruction execution worker.
8409 *
8410 * @returns Strict VBox status code.
8411 * @param pVCpu The cross context virtual CPU structure.
8412 * @param cbInstr The instruction length in bytes.
8413 * @param iEffSeg The effective segment register to use with @a
8414 * GCPtrVmxon.
8415 * @param GCPtrVmxon The linear address of the VMXON pointer.
8416 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8417 *
8418 * @remarks Common VMX instruction checks are already expected to by the caller,
8419 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8420 */
8421IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8422 PCVMXVEXITINFO pExitInfo)
8423{
8424 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8425 {
8426 /* CPL. */
8427 if (pVCpu->iem.s.uCpl == 0)
8428 { /* likely */ }
8429 else
8430 {
8431 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8432 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8433 return iemRaiseGeneralProtectionFault0(pVCpu);
8434 }
8435
8436 /* A20M (A20 Masked) mode. */
8437 if (PGMPhysIsA20Enabled(pVCpu))
8438 { /* likely */ }
8439 else
8440 {
8441 Log(("vmxon: A20M mode -> #GP(0)\n"));
8442 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8443 return iemRaiseGeneralProtectionFault0(pVCpu);
8444 }
8445
8446 /* CR0. */
8447 {
8448 /* CR0 MB1 bits. */
8449 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8450 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8451 { /* likely */ }
8452 else
8453 {
8454 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8455 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8456 return iemRaiseGeneralProtectionFault0(pVCpu);
8457 }
8458
8459 /* CR0 MBZ bits. */
8460 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8461 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8462 { /* likely */ }
8463 else
8464 {
8465 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8466 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8467 return iemRaiseGeneralProtectionFault0(pVCpu);
8468 }
8469 }
8470
8471 /* CR4. */
8472 {
8473 /* CR4 MB1 bits. */
8474 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8475 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8476 { /* likely */ }
8477 else
8478 {
8479 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8480 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8481 return iemRaiseGeneralProtectionFault0(pVCpu);
8482 }
8483
8484 /* CR4 MBZ bits. */
8485 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8486 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8487 { /* likely */ }
8488 else
8489 {
8490 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8491 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8492 return iemRaiseGeneralProtectionFault0(pVCpu);
8493 }
8494 }
8495
8496 /* Feature control MSR's LOCK and VMXON bits. */
8497 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
8498 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8499 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8500 { /* likely */ }
8501 else
8502 {
8503 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8504 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8505 return iemRaiseGeneralProtectionFault0(pVCpu);
8506 }
8507
8508 /* Get the VMXON pointer from the location specified by the source memory operand. */
8509 RTGCPHYS GCPhysVmxon;
8510 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8511 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8512 { /* likely */ }
8513 else
8514 {
8515 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8516 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8517 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8518 return rcStrict;
8519 }
8520
8521 /* VMXON region pointer alignment. */
8522 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8523 { /* likely */ }
8524 else
8525 {
8526 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8527 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8528 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8529 iemVmxVmFailInvalid(pVCpu);
8530 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8531 return VINF_SUCCESS;
8532 }
8533
8534 /* VMXON physical-address width limits. */
8535 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8536 { /* likely */ }
8537 else
8538 {
8539 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8540 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8541 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8542 iemVmxVmFailInvalid(pVCpu);
8543 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8544 return VINF_SUCCESS;
8545 }
8546
8547 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8548 restriction imposed by our implementation. */
8549 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8550 { /* likely */ }
8551 else
8552 {
8553 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8554 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8555 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8556 iemVmxVmFailInvalid(pVCpu);
8557 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8558 return VINF_SUCCESS;
8559 }
8560
8561 /* Read the VMCS revision ID from the VMXON region. */
8562 VMXVMCSREVID VmcsRevId;
8563 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8564 if (RT_SUCCESS(rc))
8565 { /* likely */ }
8566 else
8567 {
8568 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8569 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8570 return rc;
8571 }
8572
8573 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8574 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8575 { /* likely */ }
8576 else
8577 {
8578 /* Revision ID mismatch. */
8579 if (!VmcsRevId.n.fIsShadowVmcs)
8580 {
8581 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8582 VmcsRevId.n.u31RevisionId));
8583 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8584 iemVmxVmFailInvalid(pVCpu);
8585 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8586 return VINF_SUCCESS;
8587 }
8588
8589 /* Shadow VMCS disallowed. */
8590 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8591 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8592 iemVmxVmFailInvalid(pVCpu);
8593 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8594 return VINF_SUCCESS;
8595 }
8596
8597 /*
8598 * Record that we're in VMX operation, block INIT, block and disable A20M.
8599 */
8600 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8601 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8602 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8603
8604 /* Clear address-range monitoring. */
8605 EMMonitorWaitClear(pVCpu);
8606 /** @todo NSTVMX: Intel PT. */
8607
8608 iemVmxVmSucceed(pVCpu);
8609 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8610 return VINF_SUCCESS;
8611 }
8612 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8613 {
8614 /* Nested-guest intercept. */
8615 if (pExitInfo)
8616 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8617 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8618 }
8619
8620 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8621
8622 /* CPL. */
8623 if (pVCpu->iem.s.uCpl > 0)
8624 {
8625 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8626 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8627 return iemRaiseGeneralProtectionFault0(pVCpu);
8628 }
8629
8630 /* VMXON when already in VMX root mode. */
8631 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8632 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8633 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8634 return VINF_SUCCESS;
8635}
8636
8637
8638/**
8639 * Implements 'VMXOFF'.
8640 *
8641 * @remarks Common VMX instruction checks are already expected to by the caller,
8642 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8643 */
8644IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8645{
8646 /* Nested-guest intercept. */
8647 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8648 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8649
8650 /* CPL. */
8651 if (pVCpu->iem.s.uCpl == 0)
8652 { /* likely */ }
8653 else
8654 {
8655 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8656 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8657 return iemRaiseGeneralProtectionFault0(pVCpu);
8658 }
8659
8660 /* Dual monitor treatment of SMIs and SMM. */
8661 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8662 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8663 { /* likely */ }
8664 else
8665 {
8666 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8667 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8668 return VINF_SUCCESS;
8669 }
8670
8671 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8672 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8673 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8674
8675 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8676 { /** @todo NSTVMX: Unblock SMI. */ }
8677
8678 EMMonitorWaitClear(pVCpu);
8679 /** @todo NSTVMX: Unblock and enable A20M. */
8680
8681 iemVmxVmSucceed(pVCpu);
8682 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8683 return VINF_SUCCESS;
8684}
8685
8686
8687/**
8688 * Implements 'VMXON'.
8689 */
8690IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8691{
8692 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8693}
8694
8695
8696/**
8697 * Implements 'VMLAUNCH'.
8698 */
8699IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8700{
8701 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8702}
8703
8704
8705/**
8706 * Implements 'VMRESUME'.
8707 */
8708IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8709{
8710 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8711}
8712
8713
8714/**
8715 * Implements 'VMPTRLD'.
8716 */
8717IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8718{
8719 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8720}
8721
8722
8723/**
8724 * Implements 'VMPTRST'.
8725 */
8726IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8727{
8728 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8729}
8730
8731
8732/**
8733 * Implements 'VMCLEAR'.
8734 */
8735IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8736{
8737 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8738}
8739
8740
8741/**
8742 * Implements 'VMWRITE' register.
8743 */
8744IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8745{
8746 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8747}
8748
8749
8750/**
8751 * Implements 'VMWRITE' memory.
8752 */
8753IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8754{
8755 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8756}
8757
8758
8759/**
8760 * Implements 'VMREAD' register (64-bit).
8761 */
8762IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8763{
8764 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8765}
8766
8767
8768/**
8769 * Implements 'VMREAD' register (32-bit).
8770 */
8771IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8772{
8773 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8774}
8775
8776
8777/**
8778 * Implements 'VMREAD' memory, 64-bit register.
8779 */
8780IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8781{
8782 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8783}
8784
8785
8786/**
8787 * Implements 'VMREAD' memory, 32-bit register.
8788 */
8789IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8790{
8791 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8792}
8793
8794
8795/**
8796 * Implements 'INVVPID'.
8797 */
8798IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8799{
8800 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8801}
8802
8803
8804/**
8805 * Implements VMX's implementation of PAUSE.
8806 */
8807IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8808{
8809 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8810 {
8811 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8812 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8813 return rcStrict;
8814 }
8815
8816 /*
8817 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8818 * a VM-exit, the instruction operates normally.
8819 */
8820 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8821 return VINF_SUCCESS;
8822}
8823
8824#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8825
8826
8827/**
8828 * Implements 'VMCALL'.
8829 */
8830IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8831{
8832#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8833 /* Nested-guest intercept. */
8834 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8835 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8836#endif
8837
8838 /* Join forces with vmmcall. */
8839 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8840}
8841
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