VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 91974

Last change on this file since 91974 was 91974, checked in by vboxsync, 3 years ago

VMM/IEM: Nested VMX: bugref:10092 Peel out EPTP checking as a separate function, can be re-used when implementing EPTP switching/VMFUNC in the future.
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File size: 357.0 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 91974 2021-10-21 16:26:49Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_EPT_VIOLATION
177 * VMX_EXIT_EPT_MISCONFIG
178 * VMX_EXIT_INVEPT
179 * VMX_EXIT_RDRAND
180 * VMX_EXIT_VMFUNC
181 * VMX_EXIT_ENCLS
182 * VMX_EXIT_RDSEED
183 * VMX_EXIT_PML_FULL
184 * VMX_EXIT_XSAVES
185 * VMX_EXIT_XRSTORS
186 */
187/**
188 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
189 *
190 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
191 * second dimension is the Index, see VMXVMCSFIELD.
192 */
193uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
194{
195 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
196 {
197 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
198 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
199 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
200 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
201 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 27 */ UINT16_MAX,
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 26-27 */ UINT16_MAX, UINT16_MAX
227 },
228 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
233 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
234 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
235 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
236 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
237 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
239 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
240 },
241 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
242 {
243 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
244 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
245 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
246 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
247 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
248 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
249 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
250 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
251 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
252 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
253 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
254 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
255 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
256 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
257 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
258 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
259 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
260 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
261 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
262 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
263 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
264 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
265 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
266 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
267 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
268 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
269 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
270 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
271 },
272 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
273 {
274 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
275 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
276 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
277 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
278 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
279 },
280 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
281 {
282 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
283 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
284 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
285 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
286 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
287 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
288 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
289 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
290 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
291 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
292 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
293 /* 11 */ UINT16_MAX,
294 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
295 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
296 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
297 },
298 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
299 {
300 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
301 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
302 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
303 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
304 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
307 },
308 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
309 {
310 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
311 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
312 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
313 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
314 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
315 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
316 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
317 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
318 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
319 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
320 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
321 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
322 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
323 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
324 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
325 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
326 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
327 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
328 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
329 /* 26-27 */ UINT16_MAX, UINT16_MAX
330 },
331 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
332 {
333 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
334 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
335 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
336 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
337 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
338 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
339 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
340 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
341 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
342 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
343 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
344 },
345 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
346 {
347 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
348 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
349 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
350 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
351 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
352 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
353 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
354 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
355 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
356 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
357 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
358 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
359 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
360 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
361 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
362 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
363 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
364 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
365 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
366 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
367 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
368 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
369 /* 22 */ UINT16_MAX,
370 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
371 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
376 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
377 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
378 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
379 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
380 },
381 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
382 {
383 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
384 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
385 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
386 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
387 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
388 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
389 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
390 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
391 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
392 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
393 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
394 },
395 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
396 {
397 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
398 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
399 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
400 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
401 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
402 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
403 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
404 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
405 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
406 },
407 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
408 {
409 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
410 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
411 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
412 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
413 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
414 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
415 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
416 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
417 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
418 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
419 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
420 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
421 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
422 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
423 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
424 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
425 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
426 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
427 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
428 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
429 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
430 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
431 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
432 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
433 },
434 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
435 {
436 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
437 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
438 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
439 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
440 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
441 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
442 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
443 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
444 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
445 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
446 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
447 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
448 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
449 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
450 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
451 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
452 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
453 }
454};
455
456
457/**
458 * Gets a host selector from the VMCS.
459 *
460 * @param pVmcs Pointer to the virtual VMCS.
461 * @param iSelReg The index of the segment register (X86_SREG_XXX).
462 */
463DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
464{
465 Assert(iSegReg < X86_SREG_COUNT);
466 RTSEL HostSel;
467 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
468 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
469 uint8_t const uWidthType = (uWidth << 2) | uType;
470 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
471 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
472 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
473 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
474 uint8_t const *pbField = pbVmcs + offField;
475 HostSel = *(uint16_t *)pbField;
476 return HostSel;
477}
478
479
480/**
481 * Sets a guest segment register in the VMCS.
482 *
483 * @param pVmcs Pointer to the virtual VMCS.
484 * @param iSegReg The index of the segment register (X86_SREG_XXX).
485 * @param pSelReg Pointer to the segment register.
486 */
487IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
488{
489 Assert(pSelReg);
490 Assert(iSegReg < X86_SREG_COUNT);
491
492 /* Selector. */
493 {
494 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
495 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
496 uint8_t const uWidthType = (uWidth << 2) | uType;
497 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
498 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
499 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
500 uint8_t *pbVmcs = (uint8_t *)pVmcs;
501 uint8_t *pbField = pbVmcs + offField;
502 *(uint16_t *)pbField = pSelReg->Sel;
503 }
504
505 /* Limit. */
506 {
507 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
508 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
509 uint8_t const uWidthType = (uWidth << 2) | uType;
510 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
511 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
512 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
513 uint8_t *pbVmcs = (uint8_t *)pVmcs;
514 uint8_t *pbField = pbVmcs + offField;
515 *(uint32_t *)pbField = pSelReg->u32Limit;
516 }
517
518 /* Base. */
519 {
520 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
521 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
522 uint8_t const uWidthType = (uWidth << 2) | uType;
523 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
524 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
525 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
526 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
527 uint8_t const *pbField = pbVmcs + offField;
528 *(uint64_t *)pbField = pSelReg->u64Base;
529 }
530
531 /* Attributes. */
532 {
533 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
534 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
535 | X86DESCATTR_UNUSABLE;
536 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
537 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
538 uint8_t const uWidthType = (uWidth << 2) | uType;
539 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
540 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
541 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
542 uint8_t *pbVmcs = (uint8_t *)pVmcs;
543 uint8_t *pbField = pbVmcs + offField;
544 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
545 }
546}
547
548
549/**
550 * Gets a guest segment register from the VMCS.
551 *
552 * @returns VBox status code.
553 * @param pVmcs Pointer to the virtual VMCS.
554 * @param iSegReg The index of the segment register (X86_SREG_XXX).
555 * @param pSelReg Where to store the segment register (only updated when
556 * VINF_SUCCESS is returned).
557 *
558 * @remarks Warning! This does not validate the contents of the retrieved segment
559 * register.
560 */
561IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
562{
563 Assert(pSelReg);
564 Assert(iSegReg < X86_SREG_COUNT);
565
566 /* Selector. */
567 uint16_t u16Sel;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u16Sel = *(uint16_t *)pbField;
578 }
579
580 /* Limit. */
581 uint32_t u32Limit;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u32Limit = *(uint32_t *)pbField;
592 }
593
594 /* Base. */
595 uint64_t u64Base;
596 {
597 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
598 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
599 uint8_t const uWidthType = (uWidth << 2) | uType;
600 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
601 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
602 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
603 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
604 uint8_t const *pbField = pbVmcs + offField;
605 u64Base = *(uint64_t *)pbField;
606 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
607 }
608
609 /* Attributes. */
610 uint32_t u32Attr;
611 {
612 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
613 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
614 uint8_t const uWidthType = (uWidth << 2) | uType;
615 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
616 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
617 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
618 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
619 uint8_t const *pbField = pbVmcs + offField;
620 u32Attr = *(uint32_t *)pbField;
621 }
622
623 pSelReg->Sel = u16Sel;
624 pSelReg->ValidSel = u16Sel;
625 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
626 pSelReg->u32Limit = u32Limit;
627 pSelReg->u64Base = u64Base;
628 pSelReg->Attr.u = u32Attr;
629 return VINF_SUCCESS;
630}
631
632
633/**
634 * Converts an IEM exception event type to a VMX event type.
635 *
636 * @returns The VMX event type.
637 * @param uVector The interrupt / exception vector.
638 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
639 */
640DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
641{
642 /* Paranoia (callers may use these interchangeably). */
643 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
644 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
645 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
646 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
647 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
648 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
649 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
650 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
651 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
652 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
653 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
654 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
655
656 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
657 {
658 if (uVector == X86_XCPT_NMI)
659 return VMX_EXIT_INT_INFO_TYPE_NMI;
660 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
661 }
662
663 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
664 {
665 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
666 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
667 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
668 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
669 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
670 }
671
672 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
673 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
674}
675
676
677/**
678 * Sets the Exit qualification VMCS field.
679 *
680 * @param pVCpu The cross context virtual CPU structure.
681 * @param u64ExitQual The Exit qualification.
682 */
683DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
684{
685 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
686}
687
688
689/**
690 * Sets the VM-exit interruption information field.
691 *
692 * @param pVCpu The cross context virtual CPU structure.
693 * @param uExitIntInfo The VM-exit interruption information.
694 */
695DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
696{
697 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
698}
699
700
701/**
702 * Sets the VM-exit interruption error code.
703 *
704 * @param pVCpu The cross context virtual CPU structure.
705 * @param uErrCode The error code.
706 */
707DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
708{
709 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
710}
711
712
713/**
714 * Sets the IDT-vectoring information field.
715 *
716 * @param pVCpu The cross context virtual CPU structure.
717 * @param uIdtVectorInfo The IDT-vectoring information.
718 */
719DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
720{
721 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
722}
723
724
725/**
726 * Sets the IDT-vectoring error code field.
727 *
728 * @param pVCpu The cross context virtual CPU structure.
729 * @param uErrCode The error code.
730 */
731DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
732{
733 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
734}
735
736
737/**
738 * Sets the VM-exit guest-linear address VMCS field.
739 *
740 * @param pVCpu The cross context virtual CPU structure.
741 * @param uGuestLinearAddr The VM-exit guest-linear address.
742 */
743DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
744{
745 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
746}
747
748
749/**
750 * Sets the VM-exit guest-physical address VMCS field.
751 *
752 * @param pVCpu The cross context virtual CPU structure.
753 * @param uGuestPhysAddr The VM-exit guest-physical address.
754 */
755DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
756{
757 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
758}
759
760
761/**
762 * Sets the VM-exit instruction length VMCS field.
763 *
764 * @param pVCpu The cross context virtual CPU structure.
765 * @param cbInstr The VM-exit instruction length in bytes.
766 *
767 * @remarks Callers may clear this field to 0. Hence, this function does not check
768 * the validity of the instruction length.
769 */
770DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
771{
772 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
773}
774
775
776/**
777 * Sets the VM-exit instruction info. VMCS field.
778 *
779 * @param pVCpu The cross context virtual CPU structure.
780 * @param uExitInstrInfo The VM-exit instruction information.
781 */
782DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
783{
784 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
785}
786
787
788/**
789 * Sets the guest pending-debug exceptions field.
790 *
791 * @param pVCpu The cross context virtual CPU structure.
792 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
793 */
794DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
795{
796 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
797 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
798}
799
800
801/**
802 * Implements VMSucceed for VMX instruction success.
803 *
804 * @param pVCpu The cross context virtual CPU structure.
805 */
806DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
807{
808 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
809}
810
811
812/**
813 * Implements VMFailInvalid for VMX instruction failure.
814 *
815 * @param pVCpu The cross context virtual CPU structure.
816 */
817DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
818{
819 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
820}
821
822
823/**
824 * Implements VMFail for VMX instruction failure.
825 *
826 * @param pVCpu The cross context virtual CPU structure.
827 * @param enmInsErr The VM instruction error.
828 */
829DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
830{
831 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
832}
833
834
835/**
836 * Checks if the given auto-load/store MSR area count is valid for the
837 * implementation.
838 *
839 * @returns @c true if it's within the valid limit, @c false otherwise.
840 * @param pVCpu The cross context virtual CPU structure.
841 * @param uMsrCount The MSR area count to check.
842 */
843DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
844{
845 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
846 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
847 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
848 if (uMsrCount <= cMaxSupportedMsrs)
849 return true;
850 return false;
851}
852
853
854/**
855 * Flushes the current VMCS contents back to guest memory.
856 *
857 * @returns VBox status code.
858 * @param pVCpu The cross context virtual CPU structure.
859 */
860DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
861{
862 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
863 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
864 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
865 return rc;
866}
867
868
869/**
870 * Populates the current VMCS contents from guest memory.
871 *
872 * @returns VBox status code.
873 * @param pVCpu The cross context virtual CPU structure.
874 */
875DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
876{
877 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
879 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
880 return rc;
881}
882
883
884/**
885 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
886 *
887 * @param pVCpu The cross context virtual CPU structure.
888 */
889DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
890{
891 iemVmxVmSucceed(pVCpu);
892 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
893}
894
895
896/**
897 * Gets the instruction diagnostic for segment base checks during VM-entry of a
898 * nested-guest.
899 *
900 * @param iSegReg The segment index (X86_SREG_XXX).
901 */
902IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
903{
904 switch (iSegReg)
905 {
906 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
907 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
908 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
909 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
910 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
911 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
912 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
913 }
914}
915
916
917/**
918 * Gets the instruction diagnostic for segment base checks during VM-entry of a
919 * nested-guest that is in Virtual-8086 mode.
920 *
921 * @param iSegReg The segment index (X86_SREG_XXX).
922 */
923IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
924{
925 switch (iSegReg)
926 {
927 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
928 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
929 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
930 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
931 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
932 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
933 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
934 }
935}
936
937
938/**
939 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
940 * nested-guest that is in Virtual-8086 mode.
941 *
942 * @param iSegReg The segment index (X86_SREG_XXX).
943 */
944IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
945{
946 switch (iSegReg)
947 {
948 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
949 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
950 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
951 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
952 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
953 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
954 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
955 }
956}
957
958
959/**
960 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
961 * nested-guest that is in Virtual-8086 mode.
962 *
963 * @param iSegReg The segment index (X86_SREG_XXX).
964 */
965IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
966{
967 switch (iSegReg)
968 {
969 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
970 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
971 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
972 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
973 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
974 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
975 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
976 }
977}
978
979
980/**
981 * Gets the instruction diagnostic for segment attributes reserved bits failure
982 * during VM-entry of a nested-guest.
983 *
984 * @param iSegReg The segment index (X86_SREG_XXX).
985 */
986IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
987{
988 switch (iSegReg)
989 {
990 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
991 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
992 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
993 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
994 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
995 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
996 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
997 }
998}
999
1000
1001/**
1002 * Gets the instruction diagnostic for segment attributes descriptor-type
1003 * (code/segment or system) failure during VM-entry of a nested-guest.
1004 *
1005 * @param iSegReg The segment index (X86_SREG_XXX).
1006 */
1007IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1008{
1009 switch (iSegReg)
1010 {
1011 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1012 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1013 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1014 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1015 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1016 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1017 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1018 }
1019}
1020
1021
1022/**
1023 * Gets the instruction diagnostic for segment attributes descriptor-type
1024 * (code/segment or system) failure during VM-entry of a nested-guest.
1025 *
1026 * @param iSegReg The segment index (X86_SREG_XXX).
1027 */
1028IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1029{
1030 switch (iSegReg)
1031 {
1032 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1033 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1034 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1035 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1036 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1037 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1038 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1039 }
1040}
1041
1042
1043/**
1044 * Gets the instruction diagnostic for segment attribute granularity failure during
1045 * VM-entry of a nested-guest.
1046 *
1047 * @param iSegReg The segment index (X86_SREG_XXX).
1048 */
1049IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1050{
1051 switch (iSegReg)
1052 {
1053 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1054 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1055 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1056 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1057 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1058 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1059 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1060 }
1061}
1062
1063/**
1064 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1065 * VM-entry of a nested-guest.
1066 *
1067 * @param iSegReg The segment index (X86_SREG_XXX).
1068 */
1069IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1070{
1071 switch (iSegReg)
1072 {
1073 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1074 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1075 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1076 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1077 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1078 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1079 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1080 }
1081}
1082
1083
1084/**
1085 * Gets the instruction diagnostic for segment attribute type accessed failure
1086 * during VM-entry of a nested-guest.
1087 *
1088 * @param iSegReg The segment index (X86_SREG_XXX).
1089 */
1090IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1091{
1092 switch (iSegReg)
1093 {
1094 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1095 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1096 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1097 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1098 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1099 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1100 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1101 }
1102}
1103
1104
1105/**
1106 * Saves the guest control registers, debug registers and some MSRs are part of
1107 * VM-exit.
1108 *
1109 * @param pVCpu The cross context virtual CPU structure.
1110 */
1111IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1112{
1113 /*
1114 * Saves the guest control registers, debug registers and some MSRs.
1115 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1116 */
1117 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1118
1119 /* Save control registers. */
1120 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1121 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1122 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1123
1124 /* Save SYSENTER CS, ESP, EIP. */
1125 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1126 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1127 {
1128 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1129 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1130 }
1131 else
1132 {
1133 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1134 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1135 }
1136
1137 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1138 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1139 {
1140 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1141 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1142 }
1143
1144 /* Save PAT MSR. */
1145 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1146 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1147
1148 /* Save EFER MSR. */
1149 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1150 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1151
1152 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1153 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1154
1155 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1156}
1157
1158
1159/**
1160 * Saves the guest force-flags in preparation of entering the nested-guest.
1161 *
1162 * @param pVCpu The cross context virtual CPU structure.
1163 */
1164IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1165{
1166 /* We shouldn't be called multiple times during VM-entry. */
1167 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1168
1169 /* MTF should not be set outside VMX non-root mode. */
1170 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1171
1172 /*
1173 * Preserve the required force-flags.
1174 *
1175 * We cache and clear force-flags that would affect the execution of the
1176 * nested-guest. Cached flags are then restored while returning to the guest
1177 * if necessary.
1178 *
1179 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1180 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1181 * instruction. Interrupt inhibition for any nested-guest instruction
1182 * is supplied by the guest-interruptibility state VMCS field and will
1183 * be set up as part of loading the guest state.
1184 *
1185 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1186 * successful VM-entry (due to invalid guest-state) need to continue
1187 * blocking NMIs if it was in effect before VM-entry.
1188 *
1189 * - MTF need not be preserved as it's used only in VMX non-root mode and
1190 * is supplied through the VM-execution controls.
1191 *
1192 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1193 * we will be able to generate interrupts that may cause VM-exits for
1194 * the nested-guest.
1195 */
1196 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1197}
1198
1199
1200/**
1201 * Restores the guest force-flags in preparation of exiting the nested-guest.
1202 *
1203 * @param pVCpu The cross context virtual CPU structure.
1204 */
1205IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1206{
1207 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1208 {
1209 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1210 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1211 }
1212}
1213
1214
1215/**
1216 * Performs the VMX transition to/from VMX non-root mode.
1217 *
1218 * @param pVCpu The cross context virtual CPU structure.
1219 * @param fPdpesMapped Whether the PAE PDPTEs (and PDPT) have been mapped.
1220*/
1221IEM_STATIC int iemVmxTransition(PVMCPUCC pVCpu, bool fPdpesMapped)
1222{
1223 /*
1224 * Inform PGM about paging mode changes.
1225 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1226 * see comment in iemMemPageTranslateAndCheckAccess().
1227 */
1228 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1229# ifdef IN_RING3
1230 Assert(rc != VINF_PGM_CHANGE_MODE);
1231# endif
1232 AssertRCReturn(rc, rc);
1233
1234 /* Inform CPUM (recompiler), can later be removed. */
1235 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1236
1237 /*
1238 * Flush the TLB with new CR3. This is required in case the PGM mode change
1239 * above doesn't actually change anything.
1240 */
1241 if (rc == VINF_SUCCESS)
1242 {
1243 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* fGlobal */, fPdpesMapped);
1244 AssertRCReturn(rc, rc);
1245 }
1246
1247 /* Re-initialize IEM cache/state after the drastic mode switch. */
1248 iemReInitExec(pVCpu);
1249 return rc;
1250}
1251
1252
1253/**
1254 * Calculates the current VMX-preemption timer value.
1255 *
1256 * @returns The current VMX-preemption timer value.
1257 * @param pVCpu The cross context virtual CPU structure.
1258 */
1259IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1260{
1261 /*
1262 * Assume the following:
1263 * PreemptTimerShift = 5
1264 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1265 * EntryTick = 50000 (TSC at time of VM-entry)
1266 *
1267 * CurTick Delta PreemptTimerVal
1268 * ----------------------------------
1269 * 60000 10000 2
1270 * 80000 30000 1
1271 * 90000 40000 0 -> VM-exit.
1272 *
1273 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1274 * The saved VMX-preemption timer value is calculated as follows:
1275 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1276 * E.g.:
1277 * Delta = 10000
1278 * Tmp = 10000 / (2 * 10000) = 0.5
1279 * NewPt = 2 - 0.5 = 2
1280 * Delta = 30000
1281 * Tmp = 30000 / (2 * 10000) = 1.5
1282 * NewPt = 2 - 1.5 = 1
1283 * Delta = 40000
1284 * Tmp = 40000 / 20000 = 2
1285 * NewPt = 2 - 2 = 0
1286 */
1287 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1288 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1289 if (uVmcsPreemptVal > 0)
1290 {
1291 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1292 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1293 uint64_t const uDelta = uCurTick - uEntryTick;
1294 uint32_t const uPreemptTimer = uVmcsPreemptVal
1295 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1296 return uPreemptTimer;
1297 }
1298 return 0;
1299}
1300
1301
1302/**
1303 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1304 *
1305 * @param pVCpu The cross context virtual CPU structure.
1306 */
1307IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1308{
1309 /*
1310 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1311 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1312 */
1313 /* CS, SS, ES, DS, FS, GS. */
1314 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1315 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1316 {
1317 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1318 if (!pSelReg->Attr.n.u1Unusable)
1319 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1320 else
1321 {
1322 /*
1323 * For unusable segments the attributes are undefined except for CS and SS.
1324 * For the rest we don't bother preserving anything but the unusable bit.
1325 */
1326 switch (iSegReg)
1327 {
1328 case X86_SREG_CS:
1329 pVmcs->GuestCs = pSelReg->Sel;
1330 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1331 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1332 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1333 | X86DESCATTR_UNUSABLE);
1334 break;
1335
1336 case X86_SREG_SS:
1337 pVmcs->GuestSs = pSelReg->Sel;
1338 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1339 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1340 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1341 break;
1342
1343 case X86_SREG_DS:
1344 pVmcs->GuestDs = pSelReg->Sel;
1345 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1346 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1347 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1348 break;
1349
1350 case X86_SREG_ES:
1351 pVmcs->GuestEs = pSelReg->Sel;
1352 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1353 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1354 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1355 break;
1356
1357 case X86_SREG_FS:
1358 pVmcs->GuestFs = pSelReg->Sel;
1359 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1360 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1361 break;
1362
1363 case X86_SREG_GS:
1364 pVmcs->GuestGs = pSelReg->Sel;
1365 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1366 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1367 break;
1368 }
1369 }
1370 }
1371
1372 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1373 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1374 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1375 | X86DESCATTR_UNUSABLE;
1376 /* LDTR. */
1377 {
1378 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1379 pVmcs->GuestLdtr = pSelReg->Sel;
1380 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1381 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1382 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1383 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1384 }
1385
1386 /* TR. */
1387 {
1388 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1389 pVmcs->GuestTr = pSelReg->Sel;
1390 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1391 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1392 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1393 }
1394
1395 /* GDTR. */
1396 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1397 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1398
1399 /* IDTR. */
1400 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1401 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1402}
1403
1404
1405/**
1406 * Saves guest non-register state as part of VM-exit.
1407 *
1408 * @param pVCpu The cross context virtual CPU structure.
1409 * @param uExitReason The VM-exit reason.
1410 */
1411IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1412{
1413 /*
1414 * Save guest non-register state.
1415 * See Intel spec. 27.3.4 "Saving Non-Register State".
1416 */
1417 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1418
1419 /*
1420 * Activity state.
1421 * Most VM-exits will occur in the active state. However, if the first instruction
1422 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1423 * the VM-exit will be from the HLT activity state.
1424 *
1425 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1426 */
1427 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1428 * not? */
1429 EMSTATE const enmActivityState = EMGetState(pVCpu);
1430 switch (enmActivityState)
1431 {
1432 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1433 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1434 }
1435
1436 /*
1437 * Interruptibility-state.
1438 */
1439 /* NMI. */
1440 pVmcs->u32GuestIntrState = 0;
1441 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1442 {
1443 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1444 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1445 }
1446 else
1447 {
1448 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1449 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1450 }
1451
1452 /* Blocking-by-STI. */
1453 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1454 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1455 {
1456 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1457 * currently. */
1458 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1459 }
1460 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1461
1462 /*
1463 * Pending debug exceptions.
1464 *
1465 * For VM-exits where it is not applicable, we can safely zero out the field.
1466 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1467 */
1468 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1469 && uExitReason != VMX_EXIT_SMI
1470 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1471 && !VMXIsVmexitTrapLike(uExitReason))
1472 {
1473 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1474 * block-by-MovSS is in effect. */
1475 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1476 }
1477
1478 /*
1479 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1480 *
1481 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1482 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1483 */
1484 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1485 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1486 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1487
1488 /*
1489 * PAE PDPTEs.
1490 *
1491 * If EPT is enabled and PAE paging was used at the time of the VM-exit,
1492 * the PDPTEs are saved from the VMCS. Otherwise they're undefined but
1493 * we zero them for consistency.
1494 */
1495 if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1496 && !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
1497 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1498 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
1499 {
1500 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1501 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1502 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1503 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1504 }
1505 else
1506 {
1507 pVmcs->u64GuestPdpte0.u = 0;
1508 pVmcs->u64GuestPdpte1.u = 0;
1509 pVmcs->u64GuestPdpte2.u = 0;
1510 pVmcs->u64GuestPdpte3.u = 0;
1511 }
1512}
1513
1514
1515/**
1516 * Saves the guest-state as part of VM-exit.
1517 *
1518 * @returns VBox status code.
1519 * @param pVCpu The cross context virtual CPU structure.
1520 * @param uExitReason The VM-exit reason.
1521 */
1522IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1523{
1524 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1525 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1526
1527 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1528 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1529 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1530
1531 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1532}
1533
1534
1535/**
1536 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1537 *
1538 * @returns VBox status code.
1539 * @param pVCpu The cross context virtual CPU structure.
1540 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1541 */
1542IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1543{
1544 /*
1545 * Save guest MSRs.
1546 * See Intel spec. 27.4 "Saving MSRs".
1547 */
1548 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1549 const char * const pszFailure = "VMX-abort";
1550
1551 /*
1552 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1553 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1554 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1555 */
1556 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1557 if (!cMsrs)
1558 return VINF_SUCCESS;
1559
1560 /*
1561 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1562 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1563 * implementation causes a VMX-abort followed by a triple-fault.
1564 */
1565 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1566 if (fIsMsrCountValid)
1567 { /* likely */ }
1568 else
1569 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1570
1571 /*
1572 * Optimization if the nested hypervisor is using the same guest-physical page for both
1573 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1574 */
1575 PVMXAUTOMSR pMsrArea;
1576 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1577 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1578 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1579 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1580 else
1581 {
1582 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1583 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1584 if (RT_SUCCESS(rc))
1585 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1586 else
1587 {
1588 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1589 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1590 }
1591 }
1592
1593 /*
1594 * Update VM-exit MSR store area.
1595 */
1596 PVMXAUTOMSR pMsr = pMsrArea;
1597 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1598 {
1599 if ( !pMsr->u32Reserved
1600 && pMsr->u32Msr != MSR_IA32_SMBASE
1601 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1602 {
1603 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1604 if (rcStrict == VINF_SUCCESS)
1605 continue;
1606
1607 /*
1608 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1609 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1610 * recording the MSR index in the auxiliary info. field and indicated further by our
1611 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1612 * if possible, or come up with a better, generic solution.
1613 */
1614 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1615 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1616 ? kVmxVDiag_Vmexit_MsrStoreRing3
1617 : kVmxVDiag_Vmexit_MsrStore;
1618 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1619 }
1620 else
1621 {
1622 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1623 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1624 }
1625 }
1626
1627 /*
1628 * Commit the VM-exit MSR store are to guest memory.
1629 */
1630 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1631 if (RT_SUCCESS(rc))
1632 return VINF_SUCCESS;
1633
1634 NOREF(uExitReason);
1635 NOREF(pszFailure);
1636
1637 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1638 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1639}
1640
1641
1642/**
1643 * Performs a VMX abort (due to an fatal error during VM-exit).
1644 *
1645 * @returns Strict VBox status code.
1646 * @param pVCpu The cross context virtual CPU structure.
1647 * @param enmAbort The VMX abort reason.
1648 */
1649IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1650{
1651 /*
1652 * Perform the VMX abort.
1653 * See Intel spec. 27.7 "VMX Aborts".
1654 */
1655 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1656
1657 /* We don't support SMX yet. */
1658 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1659 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1660 {
1661 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1662 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1663 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1664 }
1665
1666 return VINF_EM_TRIPLE_FAULT;
1667}
1668
1669
1670/**
1671 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1672 *
1673 * @param pVCpu The cross context virtual CPU structure.
1674 */
1675IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1676{
1677 /*
1678 * Load host control registers, debug registers and MSRs.
1679 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1680 */
1681 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1682 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1683
1684 /* CR0. */
1685 {
1686 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1687 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1688 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1689 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1690 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1691 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1692 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1693
1694 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1695 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1696 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1697 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1698 }
1699
1700 /* CR4. */
1701 {
1702 /* CR4 fixed bits are not modified. */
1703 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1704 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1705 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1706 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1707 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1708 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1709 if (fHostInLongMode)
1710 uValidHostCr4 |= X86_CR4_PAE;
1711 else
1712 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1713
1714 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1715 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1716 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1717 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1718 }
1719
1720 /* CR3 (host value validated while checking host-state during VM-entry). */
1721 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1722
1723 /* DR7. */
1724 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1725
1726 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1727
1728 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1729 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1730 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1731 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1732
1733 /* FS, GS bases are loaded later while we load host segment registers. */
1734
1735 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1736 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1737 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1738 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1739 {
1740 if (fHostInLongMode)
1741 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1742 else
1743 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1744 }
1745
1746 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1747
1748 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1749 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1750 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1751
1752 /* We don't support IA32_BNDCFGS MSR yet. */
1753}
1754
1755
1756/**
1757 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1758 *
1759 * @param pVCpu The cross context virtual CPU structure.
1760 */
1761IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1762{
1763 /*
1764 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1765 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1766 *
1767 * Warning! Be careful to not touch fields that are reserved by VT-x,
1768 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1769 */
1770 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1771 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1772
1773 /* CS, SS, ES, DS, FS, GS. */
1774 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1775 {
1776 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1777 bool const fUnusable = RT_BOOL(HostSel == 0);
1778 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1779
1780 /* Selector. */
1781 pSelReg->Sel = HostSel;
1782 pSelReg->ValidSel = HostSel;
1783 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1784
1785 /* Limit. */
1786 pSelReg->u32Limit = 0xffffffff;
1787
1788 /* Base. */
1789 pSelReg->u64Base = 0;
1790
1791 /* Attributes. */
1792 if (iSegReg == X86_SREG_CS)
1793 {
1794 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1795 pSelReg->Attr.n.u1DescType = 1;
1796 pSelReg->Attr.n.u2Dpl = 0;
1797 pSelReg->Attr.n.u1Present = 1;
1798 pSelReg->Attr.n.u1Long = fHostInLongMode;
1799 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1800 pSelReg->Attr.n.u1Granularity = 1;
1801 Assert(!pSelReg->Attr.n.u1Unusable);
1802 Assert(!fUnusable);
1803 }
1804 else
1805 {
1806 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1807 pSelReg->Attr.n.u1DescType = 1;
1808 pSelReg->Attr.n.u2Dpl = 0;
1809 pSelReg->Attr.n.u1Present = 1;
1810 pSelReg->Attr.n.u1DefBig = 1;
1811 pSelReg->Attr.n.u1Granularity = 1;
1812 pSelReg->Attr.n.u1Unusable = fUnusable;
1813 }
1814 }
1815
1816 /* FS base. */
1817 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1818 || fHostInLongMode)
1819 {
1820 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1821 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1822 }
1823
1824 /* GS base. */
1825 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1826 || fHostInLongMode)
1827 {
1828 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1829 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1830 }
1831
1832 /* TR. */
1833 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1834 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1835 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1836 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1837 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1838 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1839 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1840 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1841 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1842 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1843 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1844 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1845 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1846
1847 /* LDTR (Warning! do not touch the base and limits here). */
1848 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1849 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1850 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1851 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1852
1853 /* GDTR. */
1854 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1855 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1856 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1857
1858 /* IDTR.*/
1859 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1860 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1861 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1862}
1863
1864
1865/**
1866 * Checks the host PAE PDPTEs assuming we are switching to a PAE mode host.
1867 *
1868 * @param pVCpu The cross context virtual CPU structure.
1869 * @param uExitReason The VMX instruction name (for logging purposes).
1870 *
1871 * @remarks Caller must ensure the preconditions are met before calling this
1872 * function as failure here will trigger VMX aborts!
1873 */
1874IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPUCC pVCpu, uint32_t uExitReason)
1875{
1876 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1877 const char * const pszFailure = "VMX-abort";
1878 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
1879 if (RT_SUCCESS(rc))
1880 return rc;
1881 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpte);
1882}
1883
1884
1885/**
1886 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1887 *
1888 * @returns VBox status code.
1889 * @param pVCpu The cross context virtual CPU structure.
1890 * @param uExitReason The VMX instruction name (for logging purposes).
1891 */
1892IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1893{
1894 /*
1895 * Load host MSRs.
1896 * See Intel spec. 27.6 "Loading MSRs".
1897 */
1898 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1899 const char * const pszFailure = "VMX-abort";
1900
1901 /*
1902 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1903 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1904 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1905 */
1906 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1907 if (!cMsrs)
1908 return VINF_SUCCESS;
1909
1910 /*
1911 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1912 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1913 * implementation causes a VMX-abort followed by a triple-fault.
1914 */
1915 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1916 if (fIsMsrCountValid)
1917 { /* likely */ }
1918 else
1919 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1920
1921 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1922 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1923 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1924 if (RT_SUCCESS(rc))
1925 {
1926 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1927 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1928 {
1929 if ( !pMsr->u32Reserved
1930 && pMsr->u32Msr != MSR_K8_FS_BASE
1931 && pMsr->u32Msr != MSR_K8_GS_BASE
1932 && pMsr->u32Msr != MSR_K6_EFER
1933 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1934 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1935 {
1936 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1937 if (rcStrict == VINF_SUCCESS)
1938 continue;
1939
1940 /*
1941 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1942 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1943 * recording the MSR index in the auxiliary info. field and indicated further by our
1944 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1945 * if possible, or come up with a better, generic solution.
1946 */
1947 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1948 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1949 ? kVmxVDiag_Vmexit_MsrLoadRing3
1950 : kVmxVDiag_Vmexit_MsrLoad;
1951 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1952 }
1953 else
1954 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1955 }
1956 }
1957 else
1958 {
1959 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1960 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1961 }
1962
1963 NOREF(uExitReason);
1964 NOREF(pszFailure);
1965 return VINF_SUCCESS;
1966}
1967
1968
1969/**
1970 * Loads the host state as part of VM-exit.
1971 *
1972 * @returns Strict VBox status code.
1973 * @param pVCpu The cross context virtual CPU structure.
1974 * @param uExitReason The VM-exit reason (for logging purposes).
1975 */
1976IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
1977{
1978 /*
1979 * Load host state.
1980 * See Intel spec. 27.5 "Loading Host State".
1981 */
1982 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1983 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1984
1985 /* We cannot return from a long-mode guest to a host that is not in long mode. */
1986 if ( CPUMIsGuestInLongMode(pVCpu)
1987 && !fHostInLongMode)
1988 {
1989 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
1990 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
1991 }
1992
1993 /*
1994 * Check host PAE PDPTEs prior to loading the host state.
1995 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1996 */
1997 bool fPdpesMapped;
1998 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
1999 && !fHostInLongMode
2000 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2001 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2002 {
2003 int const rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2004 if (RT_FAILURE(rc))
2005 {
2006 Log(("VM-exit attempting to load invalid PDPTEs -> VMX-Abort\n"));
2007 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2008 }
2009 fPdpesMapped = true;
2010 }
2011 else
2012 fPdpesMapped = false;
2013
2014 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2015 iemVmxVmexitLoadHostSegRegs(pVCpu);
2016
2017 /*
2018 * Load host RIP, RSP and RFLAGS.
2019 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2020 */
2021 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2022 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2023 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2024
2025 /* Clear address range monitoring. */
2026 EMMonitorWaitClear(pVCpu);
2027
2028 /* Perform the VMX transition (PGM updates). */
2029 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu, fPdpesMapped);
2030 if (rcStrict == VINF_SUCCESS)
2031 { /* likely */ }
2032 else if (RT_SUCCESS(rcStrict))
2033 {
2034 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2035 uExitReason));
2036 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2037 }
2038 else
2039 {
2040 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2041 return VBOXSTRICTRC_VAL(rcStrict);
2042 }
2043
2044 Assert(rcStrict == VINF_SUCCESS);
2045
2046 /* Load MSRs from the VM-exit auto-load MSR area. */
2047 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2048 if (RT_FAILURE(rc))
2049 {
2050 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2051 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2052 }
2053 return VINF_SUCCESS;
2054}
2055
2056
2057/**
2058 * Gets VM-exit instruction information along with any displacement for an
2059 * instruction VM-exit.
2060 *
2061 * @returns The VM-exit instruction information.
2062 * @param pVCpu The cross context virtual CPU structure.
2063 * @param uExitReason The VM-exit reason.
2064 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2065 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2066 * NULL.
2067 */
2068IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2069{
2070 RTGCPTR GCPtrDisp;
2071 VMXEXITINSTRINFO ExitInstrInfo;
2072 ExitInstrInfo.u = 0;
2073
2074 /*
2075 * Get and parse the ModR/M byte from our decoded opcodes.
2076 */
2077 uint8_t bRm;
2078 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2079 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2080 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2081 {
2082 /*
2083 * ModR/M indicates register addressing.
2084 *
2085 * The primary/secondary register operands are reported in the iReg1 or iReg2
2086 * fields depending on whether it is a read/write form.
2087 */
2088 uint8_t idxReg1;
2089 uint8_t idxReg2;
2090 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2091 {
2092 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2093 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2094 }
2095 else
2096 {
2097 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2098 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2099 }
2100 ExitInstrInfo.All.u2Scaling = 0;
2101 ExitInstrInfo.All.iReg1 = idxReg1;
2102 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2103 ExitInstrInfo.All.fIsRegOperand = 1;
2104 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2105 ExitInstrInfo.All.iSegReg = 0;
2106 ExitInstrInfo.All.iIdxReg = 0;
2107 ExitInstrInfo.All.fIdxRegInvalid = 1;
2108 ExitInstrInfo.All.iBaseReg = 0;
2109 ExitInstrInfo.All.fBaseRegInvalid = 1;
2110 ExitInstrInfo.All.iReg2 = idxReg2;
2111
2112 /* Displacement not applicable for register addressing. */
2113 GCPtrDisp = 0;
2114 }
2115 else
2116 {
2117 /*
2118 * ModR/M indicates memory addressing.
2119 */
2120 uint8_t uScale = 0;
2121 bool fBaseRegValid = false;
2122 bool fIdxRegValid = false;
2123 uint8_t iBaseReg = 0;
2124 uint8_t iIdxReg = 0;
2125 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2126 {
2127 /*
2128 * Parse the ModR/M, displacement for 16-bit addressing mode.
2129 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2130 */
2131 uint16_t u16Disp = 0;
2132 uint8_t const offDisp = offModRm + sizeof(bRm);
2133 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2134 {
2135 /* Displacement without any registers. */
2136 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2137 }
2138 else
2139 {
2140 /* Register (index and base). */
2141 switch (bRm & X86_MODRM_RM_MASK)
2142 {
2143 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2144 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2145 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2146 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2147 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2148 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2149 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2150 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2151 }
2152
2153 /* Register + displacement. */
2154 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2155 {
2156 case 0: break;
2157 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2158 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2159 default:
2160 {
2161 /* Register addressing, handled at the beginning. */
2162 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2163 break;
2164 }
2165 }
2166 }
2167
2168 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2169 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2170 }
2171 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2172 {
2173 /*
2174 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2175 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2176 */
2177 uint32_t u32Disp = 0;
2178 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2179 {
2180 /* Displacement without any registers. */
2181 uint8_t const offDisp = offModRm + sizeof(bRm);
2182 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2183 }
2184 else
2185 {
2186 /* Register (and perhaps scale, index and base). */
2187 uint8_t offDisp = offModRm + sizeof(bRm);
2188 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2189 if (iBaseReg == 4)
2190 {
2191 /* An SIB byte follows the ModR/M byte, parse it. */
2192 uint8_t bSib;
2193 uint8_t const offSib = offModRm + sizeof(bRm);
2194 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2195
2196 /* A displacement may follow SIB, update its offset. */
2197 offDisp += sizeof(bSib);
2198
2199 /* Get the scale. */
2200 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2201
2202 /* Get the index register. */
2203 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2204 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2205
2206 /* Get the base register. */
2207 iBaseReg = bSib & X86_SIB_BASE_MASK;
2208 fBaseRegValid = true;
2209 if (iBaseReg == 5)
2210 {
2211 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2212 {
2213 /* Mod is 0 implies a 32-bit displacement with no base. */
2214 fBaseRegValid = false;
2215 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2216 }
2217 else
2218 {
2219 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2220 iBaseReg = X86_GREG_xBP;
2221 }
2222 }
2223 }
2224
2225 /* Register + displacement. */
2226 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2227 {
2228 case 0: /* Handled above */ break;
2229 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2230 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2231 default:
2232 {
2233 /* Register addressing, handled at the beginning. */
2234 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2235 break;
2236 }
2237 }
2238 }
2239
2240 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2241 }
2242 else
2243 {
2244 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2245
2246 /*
2247 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2248 * See Intel instruction spec. 2.2 "IA-32e Mode".
2249 */
2250 uint64_t u64Disp = 0;
2251 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2252 if (fRipRelativeAddr)
2253 {
2254 /*
2255 * RIP-relative addressing mode.
2256 *
2257 * The displacement is 32-bit signed implying an offset range of +/-2G.
2258 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2259 */
2260 uint8_t const offDisp = offModRm + sizeof(bRm);
2261 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2262 }
2263 else
2264 {
2265 uint8_t offDisp = offModRm + sizeof(bRm);
2266
2267 /*
2268 * Register (and perhaps scale, index and base).
2269 *
2270 * REX.B extends the most-significant bit of the base register. However, REX.B
2271 * is ignored while determining whether an SIB follows the opcode. Hence, we
2272 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2273 *
2274 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2275 */
2276 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2277 if (iBaseReg == 4)
2278 {
2279 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2280 uint8_t bSib;
2281 uint8_t const offSib = offModRm + sizeof(bRm);
2282 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2283
2284 /* Displacement may follow SIB, update its offset. */
2285 offDisp += sizeof(bSib);
2286
2287 /* Get the scale. */
2288 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2289
2290 /* Get the index. */
2291 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2292 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2293
2294 /* Get the base. */
2295 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2296 fBaseRegValid = true;
2297 if (iBaseReg == 5)
2298 {
2299 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2300 {
2301 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2302 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2303 }
2304 else
2305 {
2306 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2307 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2308 }
2309 }
2310 }
2311 iBaseReg |= pVCpu->iem.s.uRexB;
2312
2313 /* Register + displacement. */
2314 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2315 {
2316 case 0: /* Handled above */ break;
2317 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2318 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2319 default:
2320 {
2321 /* Register addressing, handled at the beginning. */
2322 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2323 break;
2324 }
2325 }
2326 }
2327
2328 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2329 }
2330
2331 /*
2332 * The primary or secondary register operand is reported in iReg2 depending
2333 * on whether the primary operand is in read/write form.
2334 */
2335 uint8_t idxReg2;
2336 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2337 {
2338 idxReg2 = bRm & X86_MODRM_RM_MASK;
2339 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2340 idxReg2 |= pVCpu->iem.s.uRexB;
2341 }
2342 else
2343 {
2344 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2345 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2346 idxReg2 |= pVCpu->iem.s.uRexReg;
2347 }
2348 ExitInstrInfo.All.u2Scaling = uScale;
2349 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2350 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2351 ExitInstrInfo.All.fIsRegOperand = 0;
2352 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2353 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2354 ExitInstrInfo.All.iIdxReg = iIdxReg;
2355 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2356 ExitInstrInfo.All.iBaseReg = iBaseReg;
2357 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2358 ExitInstrInfo.All.iReg2 = idxReg2;
2359 }
2360
2361 /*
2362 * Handle exceptions to the norm for certain instructions.
2363 * (e.g. some instructions convey an instruction identity in place of iReg2).
2364 */
2365 switch (uExitReason)
2366 {
2367 case VMX_EXIT_GDTR_IDTR_ACCESS:
2368 {
2369 Assert(VMXINSTRID_IS_VALID(uInstrId));
2370 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2371 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2372 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2373 break;
2374 }
2375
2376 case VMX_EXIT_LDTR_TR_ACCESS:
2377 {
2378 Assert(VMXINSTRID_IS_VALID(uInstrId));
2379 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2380 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2381 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2382 break;
2383 }
2384
2385 case VMX_EXIT_RDRAND:
2386 case VMX_EXIT_RDSEED:
2387 {
2388 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2389 break;
2390 }
2391 }
2392
2393 /* Update displacement and return the constructed VM-exit instruction information field. */
2394 if (pGCPtrDisp)
2395 *pGCPtrDisp = GCPtrDisp;
2396
2397 return ExitInstrInfo.u;
2398}
2399
2400
2401/**
2402 * VMX VM-exit handler.
2403 *
2404 * @returns Strict VBox status code.
2405 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2406 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2407 * triple-fault.
2408 *
2409 * @param pVCpu The cross context virtual CPU structure.
2410 * @param uExitReason The VM-exit reason.
2411 * @param u64ExitQual The Exit qualification.
2412 */
2413IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2414{
2415# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2416 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2417 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2418 return VERR_IEM_IPE_7;
2419# else
2420 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2421
2422 /*
2423 * Import all the guest-CPU state.
2424 *
2425 * HM on returning to guest execution would have to reset up a whole lot of state
2426 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2427 * the state and flag reloading the entire state on re-entry. So import the entire
2428 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2429 */
2430 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2431
2432 /*
2433 * Ensure VM-entry interruption information valid bit is cleared.
2434 *
2435 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2436 * by invalid-guest state or machine-check exceptions) also clear this bit.
2437 *
2438 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2439 */
2440 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2441 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2442
2443 /*
2444 * Update the VM-exit reason and Exit qualification.
2445 * Other VMCS read-only data fields are expected to be updated by the caller already.
2446 */
2447 pVmcs->u32RoExitReason = uExitReason;
2448 pVmcs->u64RoExitQual.u = u64ExitQual;
2449
2450 Log3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2451 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2452 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2453
2454 /*
2455 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2456 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2457 */
2458 {
2459 uint8_t uVector;
2460 uint32_t fFlags;
2461 uint32_t uErrCode;
2462 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2463 if (fInEventDelivery)
2464 {
2465 /*
2466 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2467 * caused by a triple-fault or the original event results in a double-fault that
2468 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2469 * original event information into the IDT-vectoring information fields.
2470 *
2471 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2472 */
2473 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2474 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2475 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2476 {
2477 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2478 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2479 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2480 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2481 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2482 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2483 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2484 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2485 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2486 pVCpu->cpum.GstCtx.cr2));
2487 }
2488 }
2489 }
2490
2491 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2492 Assert(pVmcs->u64RoIoRcx.u == 0);
2493 Assert(pVmcs->u64RoIoRsi.u == 0);
2494 Assert(pVmcs->u64RoIoRdi.u == 0);
2495 Assert(pVmcs->u64RoIoRip.u == 0);
2496
2497 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2498 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2499 {
2500 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2501 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2502 }
2503
2504 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2505 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2506
2507 /*
2508 * Save the guest state back into the VMCS.
2509 * We only need to save the state when the VM-entry was successful.
2510 */
2511 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2512 if (!fVmentryFailed)
2513 {
2514 /*
2515 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2516 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2517 *
2518 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2519 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2520 * as guest-CPU state would not been modified. Hence for now, we do this only when
2521 * the VM-entry succeeded.
2522 */
2523 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2524 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2525 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2526 {
2527 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2528 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2529 else
2530 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2531 }
2532
2533 /*
2534 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2535 * occurs in enclave mode/SMM which we don't support yet.
2536 *
2537 * If we ever add support for it, we can pass just the lower bits to the functions
2538 * below, till then an assert should suffice.
2539 */
2540 Assert(!RT_HI_U16(uExitReason));
2541
2542 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2543 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2544 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2545 if (RT_SUCCESS(rc))
2546 { /* likely */ }
2547 else
2548 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2549
2550 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2551 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2552 }
2553 else
2554 {
2555 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2556 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2557 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2558 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2559 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2560 }
2561
2562 /*
2563 * Stop any running VMX-preemption timer if necessary.
2564 */
2565 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2566 CPUMStopGuestVmxPremptTimer(pVCpu);
2567
2568 /*
2569 * Clear any pending VMX nested-guest force-flags.
2570 * These force-flags have no effect on (outer) guest execution and will
2571 * be re-evaluated and setup on the next nested-guest VM-entry.
2572 */
2573 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2574
2575 /* Restore the host (outer guest) state. */
2576 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2577 if (RT_SUCCESS(rcStrict))
2578 {
2579 Assert(rcStrict == VINF_SUCCESS);
2580 rcStrict = VINF_VMX_VMEXIT;
2581 }
2582 else
2583 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2584
2585 /* We're no longer in nested-guest execution mode. */
2586 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2587
2588 /* Notify HM that the current VMCS fields have been modified. */
2589 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2590
2591 /* Notify HM that we've completed the VM-exit. */
2592 HMNotifyVmxNstGstVmexit(pVCpu);
2593
2594# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2595 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2596 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2597 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2598 if (rcSched != VINF_SUCCESS)
2599 iemSetPassUpStatus(pVCpu, rcSched);
2600# endif
2601 return rcStrict;
2602# endif
2603}
2604
2605
2606/**
2607 * VMX VM-exit handler for VM-exits due to instruction execution.
2608 *
2609 * This is intended for instructions where the caller provides all the relevant
2610 * VM-exit information.
2611 *
2612 * @returns Strict VBox status code.
2613 * @param pVCpu The cross context virtual CPU structure.
2614 * @param pExitInfo Pointer to the VM-exit information.
2615 */
2616IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2617{
2618 /*
2619 * For instructions where any of the following fields are not applicable:
2620 * - Exit qualification must be cleared.
2621 * - VM-exit instruction info. is undefined.
2622 * - Guest-linear address is undefined.
2623 * - Guest-physical address is undefined.
2624 *
2625 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2626 * instruction execution. For VM-exits that are not due to instruction execution this
2627 * field is undefined.
2628 *
2629 * In our implementation in IEM, all undefined fields are generally cleared. However,
2630 * if the caller supplies information (from say the physical CPU directly) it is
2631 * then possible that the undefined fields are not cleared.
2632 *
2633 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2634 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2635 */
2636 Assert(pExitInfo);
2637 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2638 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2639 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2640
2641 /* Update all the relevant fields from the VM-exit instruction information struct. */
2642 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2643 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2644 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2645 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2646
2647 /* Perform the VM-exit. */
2648 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2649}
2650
2651
2652/**
2653 * VMX VM-exit handler for VM-exits due to instruction execution.
2654 *
2655 * This is intended for instructions that only provide the VM-exit instruction
2656 * length.
2657 *
2658 * @param pVCpu The cross context virtual CPU structure.
2659 * @param uExitReason The VM-exit reason.
2660 * @param cbInstr The instruction length in bytes.
2661 */
2662IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2663{
2664 VMXVEXITINFO ExitInfo;
2665 RT_ZERO(ExitInfo);
2666 ExitInfo.uReason = uExitReason;
2667 ExitInfo.cbInstr = cbInstr;
2668
2669#ifdef VBOX_STRICT
2670 /*
2671 * To prevent us from shooting ourselves in the foot.
2672 * The follow instructions should convey more than just the instruction length.
2673 */
2674 switch (uExitReason)
2675 {
2676 case VMX_EXIT_INVEPT:
2677 case VMX_EXIT_INVPCID:
2678 case VMX_EXIT_INVVPID:
2679 case VMX_EXIT_LDTR_TR_ACCESS:
2680 case VMX_EXIT_GDTR_IDTR_ACCESS:
2681 case VMX_EXIT_VMCLEAR:
2682 case VMX_EXIT_VMPTRLD:
2683 case VMX_EXIT_VMPTRST:
2684 case VMX_EXIT_VMREAD:
2685 case VMX_EXIT_VMWRITE:
2686 case VMX_EXIT_VMXON:
2687 case VMX_EXIT_XRSTORS:
2688 case VMX_EXIT_XSAVES:
2689 case VMX_EXIT_RDRAND:
2690 case VMX_EXIT_RDSEED:
2691 case VMX_EXIT_IO_INSTR:
2692 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2693 break;
2694 }
2695#endif
2696
2697 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2698}
2699
2700
2701/**
2702 * VMX VM-exit handler for VM-exits due to instruction execution.
2703 *
2704 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2705 * instruction information and Exit qualification fields.
2706 *
2707 * @param pVCpu The cross context virtual CPU structure.
2708 * @param uExitReason The VM-exit reason.
2709 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2710 * @param cbInstr The instruction length in bytes.
2711 *
2712 * @remarks Do not use this for INS/OUTS instruction.
2713 */
2714IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2715{
2716 VMXVEXITINFO ExitInfo;
2717 RT_ZERO(ExitInfo);
2718 ExitInfo.uReason = uExitReason;
2719 ExitInfo.cbInstr = cbInstr;
2720
2721 /*
2722 * Update the Exit qualification field with displacement bytes.
2723 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2724 */
2725 switch (uExitReason)
2726 {
2727 case VMX_EXIT_INVEPT:
2728 case VMX_EXIT_INVPCID:
2729 case VMX_EXIT_INVVPID:
2730 case VMX_EXIT_LDTR_TR_ACCESS:
2731 case VMX_EXIT_GDTR_IDTR_ACCESS:
2732 case VMX_EXIT_VMCLEAR:
2733 case VMX_EXIT_VMPTRLD:
2734 case VMX_EXIT_VMPTRST:
2735 case VMX_EXIT_VMREAD:
2736 case VMX_EXIT_VMWRITE:
2737 case VMX_EXIT_VMXON:
2738 case VMX_EXIT_XRSTORS:
2739 case VMX_EXIT_XSAVES:
2740 case VMX_EXIT_RDRAND:
2741 case VMX_EXIT_RDSEED:
2742 {
2743 /* Construct the VM-exit instruction information. */
2744 RTGCPTR GCPtrDisp;
2745 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2746
2747 /* Update the VM-exit instruction information. */
2748 ExitInfo.InstrInfo.u = uInstrInfo;
2749
2750 /* Update the Exit qualification. */
2751 ExitInfo.u64Qual = GCPtrDisp;
2752 break;
2753 }
2754
2755 default:
2756 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2757 break;
2758 }
2759
2760 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2761}
2762
2763
2764/**
2765 * VMX VM-exit handler for VM-exits due to INVLPG.
2766 *
2767 * @returns Strict VBox status code.
2768 * @param pVCpu The cross context virtual CPU structure.
2769 * @param GCPtrPage The guest-linear address of the page being invalidated.
2770 * @param cbInstr The instruction length in bytes.
2771 */
2772IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2773{
2774 VMXVEXITINFO ExitInfo;
2775 RT_ZERO(ExitInfo);
2776 ExitInfo.uReason = VMX_EXIT_INVLPG;
2777 ExitInfo.cbInstr = cbInstr;
2778 ExitInfo.u64Qual = GCPtrPage;
2779 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2780
2781 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2782}
2783
2784
2785/**
2786 * VMX VM-exit handler for VM-exits due to LMSW.
2787 *
2788 * @returns Strict VBox status code.
2789 * @param pVCpu The cross context virtual CPU structure.
2790 * @param uGuestCr0 The current guest CR0.
2791 * @param pu16NewMsw The machine-status word specified in LMSW's source
2792 * operand. This will be updated depending on the VMX
2793 * guest/host CR0 mask if LMSW is not intercepted.
2794 * @param GCPtrEffDst The guest-linear address of the source operand in case
2795 * of a memory operand. For register operand, pass
2796 * NIL_RTGCPTR.
2797 * @param cbInstr The instruction length in bytes.
2798 */
2799IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2800 uint8_t cbInstr)
2801{
2802 Assert(pu16NewMsw);
2803
2804 uint16_t const uNewMsw = *pu16NewMsw;
2805 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2806 {
2807 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2808
2809 VMXVEXITINFO ExitInfo;
2810 RT_ZERO(ExitInfo);
2811 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2812 ExitInfo.cbInstr = cbInstr;
2813
2814 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2815 if (fMemOperand)
2816 {
2817 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2818 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2819 }
2820
2821 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2822 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2823 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2824 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2825
2826 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2827 }
2828
2829 /*
2830 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2831 * CR0 guest/host mask must be left unmodified.
2832 *
2833 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2834 */
2835 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2836 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2837 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2838
2839 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2840}
2841
2842
2843/**
2844 * VMX VM-exit handler for VM-exits due to CLTS.
2845 *
2846 * @returns Strict VBox status code.
2847 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2848 * VM-exit but must not modify the guest CR0.TS bit.
2849 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2850 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2851 * CR0 fixed bits in VMX operation).
2852 * @param pVCpu The cross context virtual CPU structure.
2853 * @param cbInstr The instruction length in bytes.
2854 */
2855IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2856{
2857 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2858 uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2859
2860 /*
2861 * If CR0.TS is owned by the host:
2862 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2863 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2864 * CLTS instruction completes without clearing CR0.TS.
2865 *
2866 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2867 */
2868 if (fGstHostMask & X86_CR0_TS)
2869 {
2870 if (fReadShadow & X86_CR0_TS)
2871 {
2872 Log2(("clts: Guest intercept -> VM-exit\n"));
2873
2874 VMXVEXITINFO ExitInfo;
2875 RT_ZERO(ExitInfo);
2876 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2877 ExitInfo.cbInstr = cbInstr;
2878 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2879 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2880 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2881 }
2882
2883 return VINF_VMX_MODIFIES_BEHAVIOR;
2884 }
2885
2886 /*
2887 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2888 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2889 */
2890 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2891}
2892
2893
2894/**
2895 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2896 * (CR0/CR4 write).
2897 *
2898 * @returns Strict VBox status code.
2899 * @param pVCpu The cross context virtual CPU structure.
2900 * @param iCrReg The control register (either CR0 or CR4).
2901 * @param uGuestCrX The current guest CR0/CR4.
2902 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2903 * VM-exit is caused.
2904 * @param iGReg The general register from which the CR0/CR4 value is being
2905 * loaded.
2906 * @param cbInstr The instruction length in bytes.
2907 */
2908IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2909 uint8_t cbInstr)
2910{
2911 Assert(puNewCrX);
2912 Assert(iCrReg == 0 || iCrReg == 4);
2913 Assert(iGReg < X86_GREG_COUNT);
2914
2915 uint64_t const uNewCrX = *puNewCrX;
2916 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2917 {
2918 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2919
2920 VMXVEXITINFO ExitInfo;
2921 RT_ZERO(ExitInfo);
2922 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2923 ExitInfo.cbInstr = cbInstr;
2924 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2925 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2926 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2927 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2928 }
2929
2930 /*
2931 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2932 * must not be modified the instruction.
2933 *
2934 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2935 */
2936 uint64_t uGuestCrX;
2937 uint64_t fGstHostMask;
2938 if (iCrReg == 0)
2939 {
2940 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2941 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2942 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2943 }
2944 else
2945 {
2946 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2947 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2948 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2949 }
2950
2951 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2952 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2953}
2954
2955
2956/**
2957 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2958 *
2959 * @returns VBox strict status code.
2960 * @param pVCpu The cross context virtual CPU structure.
2961 * @param iGReg The general register to which the CR3 value is being stored.
2962 * @param cbInstr The instruction length in bytes.
2963 */
2964IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
2965{
2966 Assert(iGReg < X86_GREG_COUNT);
2967 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
2968
2969 /*
2970 * If the CR3-store exiting control is set, we must cause a VM-exit.
2971 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2972 */
2973 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
2974 {
2975 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
2976
2977 VMXVEXITINFO ExitInfo;
2978 RT_ZERO(ExitInfo);
2979 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2980 ExitInfo.cbInstr = cbInstr;
2981 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
2982 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
2983 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2984 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2985 }
2986
2987 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2988}
2989
2990
2991/**
2992 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
2993 *
2994 * @returns VBox strict status code.
2995 * @param pVCpu The cross context virtual CPU structure.
2996 * @param uNewCr3 The new CR3 value.
2997 * @param iGReg The general register from which the CR3 value is being
2998 * loaded.
2999 * @param cbInstr The instruction length in bytes.
3000 */
3001IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3002{
3003 Assert(iGReg < X86_GREG_COUNT);
3004
3005 /*
3006 * If the CR3-load exiting control is set and the new CR3 value does not
3007 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3008 *
3009 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3010 */
3011 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3012 {
3013 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3014
3015 VMXVEXITINFO ExitInfo;
3016 RT_ZERO(ExitInfo);
3017 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3018 ExitInfo.cbInstr = cbInstr;
3019 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3020 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3021 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3022 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3023 }
3024
3025 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3026}
3027
3028
3029/**
3030 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3031 *
3032 * @returns VBox strict status code.
3033 * @param pVCpu The cross context virtual CPU structure.
3034 * @param iGReg The general register to which the CR8 value is being stored.
3035 * @param cbInstr The instruction length in bytes.
3036 */
3037IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3038{
3039 Assert(iGReg < X86_GREG_COUNT);
3040
3041 /*
3042 * If the CR8-store exiting control is set, we must cause a VM-exit.
3043 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3044 */
3045 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3046 {
3047 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3048
3049 VMXVEXITINFO ExitInfo;
3050 RT_ZERO(ExitInfo);
3051 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3052 ExitInfo.cbInstr = cbInstr;
3053 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3054 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3055 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3056 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3057 }
3058
3059 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3060}
3061
3062
3063/**
3064 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3065 *
3066 * @returns VBox strict status code.
3067 * @param pVCpu The cross context virtual CPU structure.
3068 * @param iGReg The general register from which the CR8 value is being
3069 * loaded.
3070 * @param cbInstr The instruction length in bytes.
3071 */
3072IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3073{
3074 Assert(iGReg < X86_GREG_COUNT);
3075
3076 /*
3077 * If the CR8-load exiting control is set, we must cause a VM-exit.
3078 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3079 */
3080 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3081 {
3082 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3083
3084 VMXVEXITINFO ExitInfo;
3085 RT_ZERO(ExitInfo);
3086 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3087 ExitInfo.cbInstr = cbInstr;
3088 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3089 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3090 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3091 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3092 }
3093
3094 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3095}
3096
3097
3098/**
3099 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3100 * GReg,DRx' (DRx read).
3101 *
3102 * @returns VBox strict status code.
3103 * @param pVCpu The cross context virtual CPU structure.
3104 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3105 * VMXINSTRID_MOV_FROM_DRX).
3106 * @param iDrReg The debug register being accessed.
3107 * @param iGReg The general register to/from which the DRx value is being
3108 * store/loaded.
3109 * @param cbInstr The instruction length in bytes.
3110 */
3111IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3112 uint8_t cbInstr)
3113{
3114 Assert(iDrReg <= 7);
3115 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3116 Assert(iGReg < X86_GREG_COUNT);
3117
3118 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3119 {
3120 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3121 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3122 VMXVEXITINFO ExitInfo;
3123 RT_ZERO(ExitInfo);
3124 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3125 ExitInfo.cbInstr = cbInstr;
3126 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3127 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3128 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3129 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3130 }
3131
3132 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3133}
3134
3135
3136/**
3137 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3138 *
3139 * @returns VBox strict status code.
3140 * @param pVCpu The cross context virtual CPU structure.
3141 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3142 * VMXINSTRID_IO_OUT).
3143 * @param u16Port The I/O port being accessed.
3144 * @param fImm Whether the I/O port was encoded using an immediate operand
3145 * or the implicit DX register.
3146 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3147 * @param cbInstr The instruction length in bytes.
3148 */
3149IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3150 uint8_t cbInstr)
3151{
3152 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3153 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3154
3155 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3156 if (fIntercept)
3157 {
3158 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3159 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3160 VMXVEXITINFO ExitInfo;
3161 RT_ZERO(ExitInfo);
3162 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3163 ExitInfo.cbInstr = cbInstr;
3164 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3165 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3166 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3167 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3168 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3169 }
3170
3171 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3172}
3173
3174
3175/**
3176 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3177 *
3178 * @returns VBox strict status code.
3179 * @param pVCpu The cross context virtual CPU structure.
3180 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3181 * VMXINSTRID_IO_OUTS).
3182 * @param u16Port The I/O port being accessed.
3183 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3184 * @param fRep Whether the instruction has a REP prefix or not.
3185 * @param ExitInstrInfo The VM-exit instruction info. field.
3186 * @param cbInstr The instruction length in bytes.
3187 */
3188IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3189 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3190{
3191 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3192 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3193 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3194 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3195 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3196
3197 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3198 if (fIntercept)
3199 {
3200 /*
3201 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3202 */
3203 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3204 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3205 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3206 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3207 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3208
3209 uint32_t uDirection;
3210 uint64_t uGuestLinearAddr;
3211 if (uInstrId == VMXINSTRID_IO_INS)
3212 {
3213 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3214 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3215 }
3216 else
3217 {
3218 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3219 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3220 }
3221
3222 /*
3223 * If the segment is unusable, the guest-linear address in undefined.
3224 * We shall clear it for consistency.
3225 *
3226 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3227 */
3228 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3229 uGuestLinearAddr = 0;
3230
3231 VMXVEXITINFO ExitInfo;
3232 RT_ZERO(ExitInfo);
3233 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3234 ExitInfo.cbInstr = cbInstr;
3235 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3236 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3237 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3238 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3239 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3240 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3241 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3242 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3243 ExitInfo.InstrInfo = ExitInstrInfo;
3244 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3245 }
3246
3247 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3248}
3249
3250
3251/**
3252 * VMX VM-exit handler for VM-exits due to MWAIT.
3253 *
3254 * @returns VBox strict status code.
3255 * @param pVCpu The cross context virtual CPU structure.
3256 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3257 * @param cbInstr The instruction length in bytes.
3258 */
3259IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3260{
3261 VMXVEXITINFO ExitInfo;
3262 RT_ZERO(ExitInfo);
3263 ExitInfo.uReason = VMX_EXIT_MWAIT;
3264 ExitInfo.cbInstr = cbInstr;
3265 ExitInfo.u64Qual = fMonitorHwArmed;
3266 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3267}
3268
3269
3270/**
3271 * VMX VM-exit handler for VM-exits due to PAUSE.
3272 *
3273 * @returns VBox strict status code.
3274 * @param pVCpu The cross context virtual CPU structure.
3275 * @param cbInstr The instruction length in bytes.
3276 */
3277IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3278{
3279 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3280
3281 /*
3282 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3283 * "PAUSE-loop exiting" control.
3284 *
3285 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3286 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3287 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3288 * a VM-exit.
3289 *
3290 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3291 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3292 */
3293 bool fIntercept = false;
3294 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3295 fIntercept = true;
3296 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3297 && pVCpu->iem.s.uCpl == 0)
3298 {
3299 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3300
3301 /*
3302 * A previous-PAUSE-tick value of 0 is used to identify the first time
3303 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3304 * consider this to be the first execution of PAUSE in a loop according
3305 * to the Intel.
3306 *
3307 * All subsequent records for the previous-PAUSE-tick we ensure that it
3308 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3309 */
3310 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3311 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3312 uint64_t const uTick = TMCpuTickGet(pVCpu);
3313 uint32_t const uPleGap = pVmcs->u32PleGap;
3314 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3315 if ( *puPrevPauseTick == 0
3316 || uTick - *puPrevPauseTick > uPleGap)
3317 *puFirstPauseLoopTick = uTick;
3318 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3319 fIntercept = true;
3320
3321 *puPrevPauseTick = uTick | 1;
3322 }
3323
3324 if (fIntercept)
3325 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3326
3327 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3328}
3329
3330
3331/**
3332 * VMX VM-exit handler for VM-exits due to task switches.
3333 *
3334 * @returns VBox strict status code.
3335 * @param pVCpu The cross context virtual CPU structure.
3336 * @param enmTaskSwitch The cause of the task switch.
3337 * @param SelNewTss The selector of the new TSS.
3338 * @param cbInstr The instruction length in bytes.
3339 */
3340IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3341{
3342 /*
3343 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3344 *
3345 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3346 * instruction or delivery of the exception generated by one of these instructions
3347 * lead to a task switch through a task gate in the IDT, we need to provide the
3348 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3349 * leaves the VM-exit instruction length field undefined.
3350 *
3351 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3352 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3353 */
3354 Assert(cbInstr <= 15);
3355
3356 uint8_t uType;
3357 switch (enmTaskSwitch)
3358 {
3359 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3360 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3361 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3362 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3363 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3364 }
3365
3366 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3367 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3368 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3369 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3370}
3371
3372
3373/**
3374 * VMX VM-exit handler for trap-like VM-exits.
3375 *
3376 * @returns VBox strict status code.
3377 * @param pVCpu The cross context virtual CPU structure.
3378 * @param pExitInfo Pointer to the VM-exit information.
3379 * @param pExitEventInfo Pointer to the VM-exit event information.
3380 */
3381IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3382{
3383 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3384 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3385 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3386}
3387
3388
3389/**
3390 * VMX VM-exit handler for VM-exits due to task switches.
3391 *
3392 * This is intended for task switches where the caller provides all the relevant
3393 * VM-exit information.
3394 *
3395 * @returns VBox strict status code.
3396 * @param pVCpu The cross context virtual CPU structure.
3397 * @param pExitInfo Pointer to the VM-exit information.
3398 * @param pExitEventInfo Pointer to the VM-exit event information.
3399 */
3400IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3401 PCVMXVEXITEVENTINFO pExitEventInfo)
3402{
3403 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3404 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3405 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3406 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3407 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3408}
3409
3410
3411/**
3412 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3413 *
3414 * @returns VBox strict status code.
3415 * @param pVCpu The cross context virtual CPU structure.
3416 */
3417IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3418{
3419 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3420 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3421
3422 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3423 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3424
3425 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3426 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3427 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3428
3429 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3430 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3431}
3432
3433
3434/**
3435 * VMX VM-exit handler for VM-exits due to external interrupts.
3436 *
3437 * @returns VBox strict status code.
3438 * @param pVCpu The cross context virtual CPU structure.
3439 * @param uVector The external interrupt vector (pass 0 if the interrupt
3440 * is still pending since we typically won't know the
3441 * vector).
3442 * @param fIntPending Whether the external interrupt is pending or
3443 * acknowledged in the interrupt controller.
3444 */
3445IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3446{
3447 Assert(!fIntPending || uVector == 0);
3448
3449 /* The VM-exit is subject to "External interrupt exiting" being set. */
3450 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3451 {
3452 if (fIntPending)
3453 {
3454 /*
3455 * If the interrupt is pending and we don't need to acknowledge the
3456 * interrupt on VM-exit, cause the VM-exit immediately.
3457 *
3458 * See Intel spec 25.2 "Other Causes Of VM Exits".
3459 */
3460 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3461 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3462
3463 /*
3464 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3465 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3466 * acknowledged that the interrupt has been consumed. Callers would have to call
3467 * us again after getting the vector (and ofc, with fIntPending with false).
3468 */
3469 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3470 }
3471
3472 /*
3473 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3474 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3475 * all set, we need to record the vector of the external interrupt in the
3476 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3477 *
3478 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3479 */
3480 uint32_t uExitIntInfo;
3481 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3482 {
3483 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3484 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3485 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3486 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3487 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3488 }
3489 else
3490 uExitIntInfo = 0;
3491 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3492
3493 /*
3494 * Cause the VM-exit whether or not the vector has been stored
3495 * in the VM-exit interruption-information field.
3496 */
3497 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3498 }
3499
3500 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3501}
3502
3503
3504/**
3505 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3506 * an event.
3507 *
3508 * @returns VBox strict status code.
3509 * @param pVCpu The cross context virtual CPU structure.
3510 */
3511IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3512{
3513 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3514 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3515 {
3516 /*
3517 * The NMI-unblocking due to IRET field need not be set for double faults.
3518 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3519 */
3520 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3521 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3522 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3523 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3524 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3525 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3526 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3527 }
3528
3529 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3530}
3531
3532
3533/**
3534 * VMX VM-exit handler for VM-exit due to delivery of an events.
3535 *
3536 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3537 * all the relevant VM-exit information.
3538 *
3539 * @returns VBox strict status code.
3540 * @param pVCpu The cross context virtual CPU structure.
3541 * @param pExitInfo Pointer to the VM-exit information.
3542 * @param pExitEventInfo Pointer to the VM-exit event information.
3543 */
3544IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3545{
3546 Assert(pExitInfo);
3547 Assert(pExitEventInfo);
3548 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3549 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3550
3551 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3552 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3553 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3554 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3555 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3556 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3557}
3558
3559
3560/**
3561 * VMX VM-exit handler for VM-exits due to delivery of an event.
3562 *
3563 * @returns VBox strict status code.
3564 * @param pVCpu The cross context virtual CPU structure.
3565 * @param uVector The interrupt / exception vector.
3566 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3567 * @param uErrCode The error code associated with the event.
3568 * @param uCr2 The CR2 value in case of a \#PF exception.
3569 * @param cbInstr The instruction length in bytes.
3570 */
3571IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3572 uint8_t cbInstr)
3573{
3574 /*
3575 * If the event is being injected as part of VM-entry, it is -not- subject to event
3576 * intercepts in the nested-guest. However, secondary exceptions that occur during
3577 * injection of any event -are- subject to event interception.
3578 *
3579 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3580 */
3581 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3582 {
3583 /*
3584 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3585 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3586 *
3587 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3588 */
3589 if ( uVector == X86_XCPT_NMI
3590 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3591 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3592 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3593 else
3594 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3595
3596 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3597 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3598 }
3599
3600 /*
3601 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3602 * If not, the caller will continue delivery of the external interrupt as it would
3603 * normally. The interrupt is no longer pending in the interrupt controller at this
3604 * point.
3605 */
3606 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3607 {
3608 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3609 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3610 }
3611
3612 /*
3613 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3614 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3615 * interrupts.
3616 */
3617 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3618 bool fIntercept;
3619 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3620 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3621 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3622 else
3623 {
3624 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3625 fIntercept = false;
3626 }
3627
3628 /*
3629 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3630 * relevant VM-exit information and cause the VM-exit.
3631 */
3632 if (fIntercept)
3633 {
3634 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3635
3636 /* Construct the rest of the event related information fields and cause the VM-exit. */
3637 uint64_t u64ExitQual;
3638 if (uVector == X86_XCPT_PF)
3639 {
3640 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3641 u64ExitQual = uCr2;
3642 }
3643 else if (uVector == X86_XCPT_DB)
3644 {
3645 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3646 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3647 }
3648 else
3649 u64ExitQual = 0;
3650
3651 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3652 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3653 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3654 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3655 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3656 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3657 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3658 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3659 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3660 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3661
3662 /*
3663 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3664 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3665 * length.
3666 */
3667 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3668 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3669 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3670 else
3671 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3672
3673 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3674 }
3675
3676 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3677}
3678
3679
3680#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3681/**
3682 * VMX VM-exit handler for EPT violation.
3683 *
3684 * @param pVCpu The cross context virtual CPU structure.
3685 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3686 * @param fEptAccess The EPT paging structure bits.
3687 * @param GCPhysAddr The physical address causing the EPT violation.
3688 * @param GCPtrAddr The linear address causing the EPT violation.
3689 * @param cbInstr The VM-exit instruction length.
3690 */
3691IEM_STATIC VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint64_t fEptAccess, RTGCPHYS GCPhysAddr,
3692 uint64_t GCPtrAddr, bool fLinearAddrValid, uint8_t cbInstr)
3693{
3694 /*
3695 * If the linear address isn't valid (can happen when loading PDPTEs
3696 * as part of MOV CR execution) the linear address field is undefined.
3697 * While we can leave it this way, it's preferrable to zero it for consistency.
3698 */
3699 Assert(fLinearAddrValid || GCPtrAddr == 0);
3700
3701 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3702 uint8_t const fSupportsAccessDirty = fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY;
3703
3704 uint8_t const fDataRead = ((fAccess & IEM_ACCESS_DATA_R) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3705 uint8_t const fDataWrite = ((fAccess & IEM_ACCESS_DATA_RW) == IEM_ACCESS_DATA_RW) | fSupportsAccessDirty;
3706 uint8_t const fInstrFetch = (fAccess & IEM_ACCESS_INSTRUCTION) == IEM_ACCESS_INSTRUCTION;
3707 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3708 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3709 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3710 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3711
3712 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
3713 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
3714 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
3715 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
3716 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
3717 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
3718 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fLinearAddrValid)
3719 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
3720
3721 /** @todo bit 8 of Exit Qualification!
3722 * If the access causing the EPT violation is to a guest-physical address that is
3723 * the translation of a linear address.
3724 * - OR -
3725 * if the access causing the EPT violation is to a paging-structure entry as part
3726 * of a page walk or the update of an accessed or dirty bit.
3727 *
3728 * Caller needs to be able to distinguish this... */
3729
3730#ifdef VBOX_STRICT
3731 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
3732 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
3733 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
3734 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
3735 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3736 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3737 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
3738#endif
3739
3740 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3741 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
3742 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3743
3744 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
3745}
3746#endif
3747
3748
3749/**
3750 * VMX VM-exit handler for APIC accesses.
3751 *
3752 * @param pVCpu The cross context virtual CPU structure.
3753 * @param offAccess The offset of the register being accessed.
3754 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3755 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3756 */
3757IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3758{
3759 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3760
3761 VMXAPICACCESS enmAccess;
3762 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3763 if (fInEventDelivery)
3764 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3765 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3766 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3767 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3768 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3769 else
3770 enmAccess = VMXAPICACCESS_LINEAR_READ;
3771
3772 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3773 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3774 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3775}
3776
3777
3778/**
3779 * VMX VM-exit handler for APIC accesses.
3780 *
3781 * This is intended for APIC accesses where the caller provides all the
3782 * relevant VM-exit information.
3783 *
3784 * @returns VBox strict status code.
3785 * @param pVCpu The cross context virtual CPU structure.
3786 * @param pExitInfo Pointer to the VM-exit information.
3787 * @param pExitEventInfo Pointer to the VM-exit event information.
3788 */
3789IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3790 PCVMXVEXITEVENTINFO pExitEventInfo)
3791{
3792 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3793 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3794 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3795 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3796 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3797 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3798 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3799 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3800 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3801}
3802
3803
3804/**
3805 * VMX VM-exit handler for APIC-write VM-exits.
3806 *
3807 * @param pVCpu The cross context virtual CPU structure.
3808 * @param offApic The write to the virtual-APIC page offset that caused this
3809 * VM-exit.
3810 */
3811IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3812{
3813 Assert(offApic < XAPIC_OFF_END + 4);
3814 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3815 offApic &= UINT16_C(0xfff);
3816 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3817}
3818
3819
3820/**
3821 * Sets virtual-APIC write emulation as pending.
3822 *
3823 * @param pVCpu The cross context virtual CPU structure.
3824 * @param offApic The offset in the virtual-APIC page that was written.
3825 */
3826DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3827{
3828 Assert(offApic < XAPIC_OFF_END + 4);
3829
3830 /*
3831 * Record the currently updated APIC offset, as we need this later for figuring
3832 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3833 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3834 */
3835 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3836
3837 /*
3838 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3839 * virtualization or APIC-write emulation).
3840 */
3841 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3842 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3843}
3844
3845
3846/**
3847 * Clears any pending virtual-APIC write emulation.
3848 *
3849 * @returns The virtual-APIC offset that was written before clearing it.
3850 * @param pVCpu The cross context virtual CPU structure.
3851 */
3852DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3853{
3854 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3855 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3856 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3857 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3858 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3859 return offVirtApicWrite;
3860}
3861
3862
3863/**
3864 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3865 *
3866 * @returns The register from the virtual-APIC page.
3867 * @param pVCpu The cross context virtual CPU structure.
3868 * @param offReg The offset of the register being read.
3869 */
3870IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3871{
3872 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3873
3874 uint32_t uReg = 0;
3875 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3876 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3877 AssertMsgStmt(RT_SUCCESS(rc),
3878 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3879 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3880 uReg = 0);
3881 return uReg;
3882}
3883
3884
3885/**
3886 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3887 *
3888 * @returns The register from the virtual-APIC page.
3889 * @param pVCpu The cross context virtual CPU structure.
3890 * @param offReg The offset of the register being read.
3891 */
3892IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3893{
3894 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3895
3896 uint64_t uReg = 0;
3897 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3898 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3899 AssertMsgStmt(RT_SUCCESS(rc),
3900 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3901 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3902 uReg = 0);
3903 return uReg;
3904}
3905
3906
3907/**
3908 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3909 *
3910 * @param pVCpu The cross context virtual CPU structure.
3911 * @param offReg The offset of the register being written.
3912 * @param uReg The register value to write.
3913 */
3914IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3915{
3916 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3917
3918 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3919 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3920 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3921 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3922}
3923
3924
3925/**
3926 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3927 *
3928 * @param pVCpu The cross context virtual CPU structure.
3929 * @param offReg The offset of the register being written.
3930 * @param uReg The register value to write.
3931 */
3932IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3933{
3934 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3935
3936 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3937 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3938 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3939 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3940}
3941
3942
3943/**
3944 * Sets the vector in a virtual-APIC 256-bit sparse register.
3945 *
3946 * @param pVCpu The cross context virtual CPU structure.
3947 * @param offReg The offset of the 256-bit spare register.
3948 * @param uVector The vector to set.
3949 *
3950 * @remarks This is based on our APIC device code.
3951 */
3952IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3953{
3954 /* Determine the vector offset within the chunk. */
3955 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3956
3957 /* Read the chunk at the offset. */
3958 uint32_t uReg;
3959 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3960 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3961 if (RT_SUCCESS(rc))
3962 {
3963 /* Modify the chunk. */
3964 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3965 uReg |= RT_BIT(idxVectorBit);
3966
3967 /* Write the chunk. */
3968 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3969 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3970 uVector, offReg, GCPhysVirtApic, rc));
3971 }
3972 else
3973 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3974 uVector, offReg, GCPhysVirtApic, rc));
3975}
3976
3977
3978/**
3979 * Clears the vector in a virtual-APIC 256-bit sparse register.
3980 *
3981 * @param pVCpu The cross context virtual CPU structure.
3982 * @param offReg The offset of the 256-bit spare register.
3983 * @param uVector The vector to clear.
3984 *
3985 * @remarks This is based on our APIC device code.
3986 */
3987IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3988{
3989 /* Determine the vector offset within the chunk. */
3990 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3991
3992 /* Read the chunk at the offset. */
3993 uint32_t uReg;
3994 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3995 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3996 if (RT_SUCCESS(rc))
3997 {
3998 /* Modify the chunk. */
3999 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4000 uReg &= ~RT_BIT(idxVectorBit);
4001
4002 /* Write the chunk. */
4003 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4004 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4005 uVector, offReg, GCPhysVirtApic, rc));
4006 }
4007 else
4008 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4009 uVector, offReg, GCPhysVirtApic, rc));
4010}
4011
4012
4013/**
4014 * Checks if a memory access to the APIC-access page must causes an APIC-access
4015 * VM-exit.
4016 *
4017 * @param pVCpu The cross context virtual CPU structure.
4018 * @param offAccess The offset of the register being accessed.
4019 * @param cbAccess The size of the access in bytes.
4020 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4021 * IEM_ACCESS_TYPE_WRITE).
4022 *
4023 * @remarks This must not be used for MSR-based APIC-access page accesses!
4024 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4025 */
4026IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4027{
4028 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4029 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4030
4031 /*
4032 * We must cause a VM-exit if any of the following are true:
4033 * - TPR shadowing isn't active.
4034 * - The access size exceeds 32-bits.
4035 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4036 *
4037 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4038 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4039 */
4040 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4041 || cbAccess > sizeof(uint32_t)
4042 || ((offAccess + cbAccess - 1) & 0xc)
4043 || offAccess >= XAPIC_OFF_END + 4)
4044 return true;
4045
4046 /*
4047 * If the access is part of an operation where we have already
4048 * virtualized a virtual-APIC write, we must cause a VM-exit.
4049 */
4050 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4051 return true;
4052
4053 /*
4054 * Check write accesses to the APIC-access page that cause VM-exits.
4055 */
4056 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4057 {
4058 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4059 {
4060 /*
4061 * With APIC-register virtualization, a write access to any of the
4062 * following registers are virtualized. Accessing any other register
4063 * causes a VM-exit.
4064 */
4065 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4066 switch (offAlignedAccess)
4067 {
4068 case XAPIC_OFF_ID:
4069 case XAPIC_OFF_TPR:
4070 case XAPIC_OFF_EOI:
4071 case XAPIC_OFF_LDR:
4072 case XAPIC_OFF_DFR:
4073 case XAPIC_OFF_SVR:
4074 case XAPIC_OFF_ESR:
4075 case XAPIC_OFF_ICR_LO:
4076 case XAPIC_OFF_ICR_HI:
4077 case XAPIC_OFF_LVT_TIMER:
4078 case XAPIC_OFF_LVT_THERMAL:
4079 case XAPIC_OFF_LVT_PERF:
4080 case XAPIC_OFF_LVT_LINT0:
4081 case XAPIC_OFF_LVT_LINT1:
4082 case XAPIC_OFF_LVT_ERROR:
4083 case XAPIC_OFF_TIMER_ICR:
4084 case XAPIC_OFF_TIMER_DCR:
4085 break;
4086 default:
4087 return true;
4088 }
4089 }
4090 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4091 {
4092 /*
4093 * With virtual-interrupt delivery, a write access to any of the
4094 * following registers are virtualized. Accessing any other register
4095 * causes a VM-exit.
4096 *
4097 * Note! The specification does not allow writing to offsets in-between
4098 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4099 */
4100 switch (offAccess)
4101 {
4102 case XAPIC_OFF_TPR:
4103 case XAPIC_OFF_EOI:
4104 case XAPIC_OFF_ICR_LO:
4105 break;
4106 default:
4107 return true;
4108 }
4109 }
4110 else
4111 {
4112 /*
4113 * Without APIC-register virtualization or virtual-interrupt delivery,
4114 * only TPR accesses are virtualized.
4115 */
4116 if (offAccess == XAPIC_OFF_TPR)
4117 { /* likely */ }
4118 else
4119 return true;
4120 }
4121 }
4122 else
4123 {
4124 /*
4125 * Check read accesses to the APIC-access page that cause VM-exits.
4126 */
4127 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4128 {
4129 /*
4130 * With APIC-register virtualization, a read access to any of the
4131 * following registers are virtualized. Accessing any other register
4132 * causes a VM-exit.
4133 */
4134 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4135 switch (offAlignedAccess)
4136 {
4137 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4138 case XAPIC_OFF_ID:
4139 case XAPIC_OFF_VERSION:
4140 case XAPIC_OFF_TPR:
4141 case XAPIC_OFF_EOI:
4142 case XAPIC_OFF_LDR:
4143 case XAPIC_OFF_DFR:
4144 case XAPIC_OFF_SVR:
4145 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4146 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4147 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4148 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4149 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4150 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4151 case XAPIC_OFF_ESR:
4152 case XAPIC_OFF_ICR_LO:
4153 case XAPIC_OFF_ICR_HI:
4154 case XAPIC_OFF_LVT_TIMER:
4155 case XAPIC_OFF_LVT_THERMAL:
4156 case XAPIC_OFF_LVT_PERF:
4157 case XAPIC_OFF_LVT_LINT0:
4158 case XAPIC_OFF_LVT_LINT1:
4159 case XAPIC_OFF_LVT_ERROR:
4160 case XAPIC_OFF_TIMER_ICR:
4161 case XAPIC_OFF_TIMER_DCR:
4162 break;
4163 default:
4164 return true;
4165 }
4166 }
4167 else
4168 {
4169 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4170 if (offAccess == XAPIC_OFF_TPR)
4171 { /* likely */ }
4172 else
4173 return true;
4174 }
4175 }
4176
4177 /* The APIC access is virtualized, does not cause a VM-exit. */
4178 return false;
4179}
4180
4181
4182/**
4183 * Virtualizes a memory-based APIC access where the address is not used to access
4184 * memory.
4185 *
4186 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4187 * page-faults but do not use the address to access memory.
4188 *
4189 * @param pVCpu The cross context virtual CPU structure.
4190 * @param pGCPhysAccess Pointer to the guest-physical address used.
4191 */
4192IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4193{
4194 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4195 Assert(pGCPhysAccess);
4196
4197 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4198 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4199 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4200
4201 if (GCPhysAccess == GCPhysApic)
4202 {
4203 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4204 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4205 uint16_t const cbAccess = 1;
4206 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4207 if (fIntercept)
4208 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4209
4210 *pGCPhysAccess = GCPhysApic | offAccess;
4211 return VINF_VMX_MODIFIES_BEHAVIOR;
4212 }
4213
4214 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4215}
4216
4217
4218/**
4219 * Virtualizes a memory-based APIC access.
4220 *
4221 * @returns VBox strict status code.
4222 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4223 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4224 *
4225 * @param pVCpu The cross context virtual CPU structure.
4226 * @param offAccess The offset of the register being accessed (within the
4227 * APIC-access page).
4228 * @param cbAccess The size of the access in bytes.
4229 * @param pvData Pointer to the data being written or where to store the data
4230 * being read.
4231 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4232 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4233 */
4234IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4235 uint32_t fAccess)
4236{
4237 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4238 Assert(pvData);
4239 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4240 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4241 || (fAccess & IEM_ACCESS_INSTRUCTION));
4242
4243 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4244 if (fIntercept)
4245 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4246
4247 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4248 {
4249 /*
4250 * A write access to the APIC-access page that is virtualized (rather than
4251 * causing a VM-exit) writes data to the virtual-APIC page.
4252 */
4253 uint32_t const u32Data = *(uint32_t *)pvData;
4254 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4255
4256 /*
4257 * Record the currently updated APIC offset, as we need this later for figuring
4258 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4259 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4260 *
4261 * After completion of the current operation, we need to perform TPR virtualization,
4262 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4263 *
4264 * The current operation may be a REP-prefixed string instruction, execution of any
4265 * other instruction, or delivery of an event through the IDT.
4266 *
4267 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4268 * performed now but later after completion of the current operation.
4269 *
4270 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4271 */
4272 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4273 }
4274 else
4275 {
4276 /*
4277 * A read access from the APIC-access page that is virtualized (rather than
4278 * causing a VM-exit) returns data from the virtual-APIC page.
4279 *
4280 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4281 */
4282 Assert(cbAccess <= 4);
4283 Assert(offAccess < XAPIC_OFF_END + 4);
4284 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4285
4286 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4287 u32Data &= s_auAccessSizeMasks[cbAccess];
4288 *(uint32_t *)pvData = u32Data;
4289 }
4290
4291 return VINF_VMX_MODIFIES_BEHAVIOR;
4292}
4293
4294
4295/**
4296 * Virtualizes an MSR-based APIC read access.
4297 *
4298 * @returns VBox strict status code.
4299 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4300 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4301 * handled by the x2APIC device.
4302 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4303 * not within the range of valid MSRs, caller must raise \#GP(0).
4304 * @param pVCpu The cross context virtual CPU structure.
4305 * @param idMsr The x2APIC MSR being read.
4306 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4307 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4308 */
4309IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4310{
4311 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4312 Assert(pu64Value);
4313
4314 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4315 {
4316 if ( idMsr >= MSR_IA32_X2APIC_START
4317 && idMsr <= MSR_IA32_X2APIC_END)
4318 {
4319 uint16_t const offReg = (idMsr & 0xff) << 4;
4320 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4321 *pu64Value = u64Value;
4322 return VINF_VMX_MODIFIES_BEHAVIOR;
4323 }
4324 return VERR_OUT_OF_RANGE;
4325 }
4326
4327 if (idMsr == MSR_IA32_X2APIC_TPR)
4328 {
4329 uint16_t const offReg = (idMsr & 0xff) << 4;
4330 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4331 *pu64Value = u64Value;
4332 return VINF_VMX_MODIFIES_BEHAVIOR;
4333 }
4334
4335 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4336}
4337
4338
4339/**
4340 * Virtualizes an MSR-based APIC write access.
4341 *
4342 * @returns VBox strict status code.
4343 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4344 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4345 * not within the range of valid MSRs, caller must raise \#GP(0).
4346 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4347 *
4348 * @param pVCpu The cross context virtual CPU structure.
4349 * @param idMsr The x2APIC MSR being written.
4350 * @param u64Value The value of the x2APIC MSR being written.
4351 */
4352IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4353{
4354 /*
4355 * Check if the access is to be virtualized.
4356 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4357 */
4358 if ( idMsr == MSR_IA32_X2APIC_TPR
4359 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4360 && ( idMsr == MSR_IA32_X2APIC_EOI
4361 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4362 {
4363 /* Validate the MSR write depending on the register. */
4364 switch (idMsr)
4365 {
4366 case MSR_IA32_X2APIC_TPR:
4367 case MSR_IA32_X2APIC_SELF_IPI:
4368 {
4369 if (u64Value & UINT64_C(0xffffffffffffff00))
4370 return VERR_OUT_OF_RANGE;
4371 break;
4372 }
4373 case MSR_IA32_X2APIC_EOI:
4374 {
4375 if (u64Value != 0)
4376 return VERR_OUT_OF_RANGE;
4377 break;
4378 }
4379 }
4380
4381 /* Write the MSR to the virtual-APIC page. */
4382 uint16_t const offReg = (idMsr & 0xff) << 4;
4383 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4384
4385 /*
4386 * Record the currently updated APIC offset, as we need this later for figuring
4387 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4388 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4389 */
4390 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4391
4392 return VINF_VMX_MODIFIES_BEHAVIOR;
4393 }
4394
4395 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4396}
4397
4398
4399/**
4400 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4401 *
4402 * @returns VBox status code.
4403 * @retval VINF_SUCCESS when the highest set bit is found.
4404 * @retval VERR_NOT_FOUND when no bit is set.
4405 *
4406 * @param pVCpu The cross context virtual CPU structure.
4407 * @param offReg The offset of the APIC 256-bit sparse register.
4408 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4409 * set in the register. Only valid when VINF_SUCCESS is
4410 * returned.
4411 *
4412 * @remarks The format of the 256-bit sparse register here mirrors that found in
4413 * real APIC hardware.
4414 */
4415static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4416{
4417 Assert(offReg < XAPIC_OFF_END + 4);
4418 Assert(pidxHighestBit);
4419
4420 /*
4421 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4422 * However, in each fragment only the first 4 bytes are used.
4423 */
4424 uint8_t const cFrags = 8;
4425 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4426 {
4427 uint16_t const offFrag = iFrag * 16;
4428 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4429 if (!u32Frag)
4430 continue;
4431
4432 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4433 Assert(idxHighestBit > 0);
4434 --idxHighestBit;
4435 Assert(idxHighestBit <= UINT8_MAX);
4436 *pidxHighestBit = idxHighestBit;
4437 return VINF_SUCCESS;
4438 }
4439 return VERR_NOT_FOUND;
4440}
4441
4442
4443/**
4444 * Evaluates pending virtual interrupts.
4445 *
4446 * @param pVCpu The cross context virtual CPU structure.
4447 */
4448IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4449{
4450 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4451
4452 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4453 {
4454 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4455 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4456
4457 if ((uRvi >> 4) > (uPpr >> 4))
4458 {
4459 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4460 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4461 }
4462 else
4463 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4464 }
4465}
4466
4467
4468/**
4469 * Performs PPR virtualization.
4470 *
4471 * @returns VBox strict status code.
4472 * @param pVCpu The cross context virtual CPU structure.
4473 */
4474IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4475{
4476 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4477 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4478
4479 /*
4480 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4481 * or EOI-virtualization.
4482 *
4483 * See Intel spec. 29.1.3 "PPR Virtualization".
4484 */
4485 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4486 uint32_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4487
4488 uint32_t uPpr;
4489 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4490 uPpr = uTpr & 0xff;
4491 else
4492 uPpr = uSvi & 0xf0;
4493
4494 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4495 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4496}
4497
4498
4499/**
4500 * Performs VMX TPR virtualization.
4501 *
4502 * @returns VBox strict status code.
4503 * @param pVCpu The cross context virtual CPU structure.
4504 */
4505IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4506{
4507 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4508
4509 /*
4510 * We should have already performed the virtual-APIC write to the TPR offset
4511 * in the virtual-APIC page. We now perform TPR virtualization.
4512 *
4513 * See Intel spec. 29.1.2 "TPR Virtualization".
4514 */
4515 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4516 {
4517 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4518 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4519
4520 /*
4521 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4522 * See Intel spec. 29.1.2 "TPR Virtualization".
4523 */
4524 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4525 {
4526 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4527 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4528 }
4529 }
4530 else
4531 {
4532 iemVmxPprVirtualization(pVCpu);
4533 iemVmxEvalPendingVirtIntrs(pVCpu);
4534 }
4535
4536 return VINF_SUCCESS;
4537}
4538
4539
4540/**
4541 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4542 * not.
4543 *
4544 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4545 * @param pVCpu The cross context virtual CPU structure.
4546 * @param uVector The interrupt that was acknowledged using an EOI.
4547 */
4548IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4549{
4550 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4551 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4552
4553 if (uVector < 64)
4554 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4555 if (uVector < 128)
4556 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4557 if (uVector < 192)
4558 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4559 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4560}
4561
4562
4563/**
4564 * Performs EOI virtualization.
4565 *
4566 * @returns VBox strict status code.
4567 * @param pVCpu The cross context virtual CPU structure.
4568 */
4569IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4570{
4571 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4572 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4573
4574 /*
4575 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4576 * and get the next guest-interrupt that's in-service (if any).
4577 *
4578 * See Intel spec. 29.1.4 "EOI Virtualization".
4579 */
4580 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4581 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4582 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4583
4584 uint8_t uVector = uSvi;
4585 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4586
4587 uVector = 0;
4588 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4589
4590 if (uVector)
4591 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4592 else
4593 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4594
4595 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4596 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4597
4598 iemVmxPprVirtualization(pVCpu);
4599 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4600 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4601 iemVmxEvalPendingVirtIntrs(pVCpu);
4602 return VINF_SUCCESS;
4603}
4604
4605
4606/**
4607 * Performs self-IPI virtualization.
4608 *
4609 * @returns VBox strict status code.
4610 * @param pVCpu The cross context virtual CPU structure.
4611 */
4612IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4613{
4614 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4615 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4616
4617 /*
4618 * We should have already performed the virtual-APIC write to the self-IPI offset
4619 * in the virtual-APIC page. We now perform self-IPI virtualization.
4620 *
4621 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4622 */
4623 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4624 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4625 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4626 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4627 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4628 if (uVector > uRvi)
4629 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4630 iemVmxEvalPendingVirtIntrs(pVCpu);
4631 return VINF_SUCCESS;
4632}
4633
4634
4635/**
4636 * Performs VMX APIC-write emulation.
4637 *
4638 * @returns VBox strict status code.
4639 * @param pVCpu The cross context virtual CPU structure.
4640 */
4641IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4642{
4643 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4644
4645 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4646 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4647
4648 /*
4649 * Perform APIC-write emulation based on the virtual-APIC register written.
4650 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4651 */
4652 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4653 VBOXSTRICTRC rcStrict;
4654 switch (offApicWrite)
4655 {
4656 case XAPIC_OFF_TPR:
4657 {
4658 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4659 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4660 uTpr &= UINT32_C(0x000000ff);
4661 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4662 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4663 rcStrict = iemVmxTprVirtualization(pVCpu);
4664 break;
4665 }
4666
4667 case XAPIC_OFF_EOI:
4668 {
4669 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4670 {
4671 /* Clear VEOI and perform EOI virtualization. */
4672 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4673 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4674 rcStrict = iemVmxEoiVirtualization(pVCpu);
4675 }
4676 else
4677 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4678 break;
4679 }
4680
4681 case XAPIC_OFF_ICR_LO:
4682 {
4683 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4684 {
4685 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4686 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4687 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4688 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4689 if ( !(uIcrLo & fIcrLoMb0)
4690 && (uIcrLo & fIcrLoMb1))
4691 {
4692 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4693 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4694 }
4695 else
4696 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4697 }
4698 else
4699 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4700 break;
4701 }
4702
4703 case XAPIC_OFF_ICR_HI:
4704 {
4705 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4706 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4707 uIcrHi &= UINT32_C(0xff000000);
4708 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4709 rcStrict = VINF_SUCCESS;
4710 break;
4711 }
4712
4713 default:
4714 {
4715 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4716 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4717 break;
4718 }
4719 }
4720
4721 return rcStrict;
4722}
4723
4724
4725/**
4726 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4727 *
4728 * @param pVCpu The cross context virtual CPU structure.
4729 * @param pszInstr The VMX instruction name (for logging purposes).
4730 */
4731DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4732{
4733 /*
4734 * Guest Control Registers, Debug Registers, and MSRs.
4735 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4736 */
4737 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4738 const char * const pszFailure = "VM-exit";
4739 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4740
4741 /* CR0 reserved bits. */
4742 {
4743 /* CR0 MB1 bits. */
4744 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4745 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4746 if (fUnrestrictedGuest)
4747 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4748 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4749 { /* likely */ }
4750 else
4751 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4752
4753 /* CR0 MBZ bits. */
4754 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4755 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4756 { /* likely */ }
4757 else
4758 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4759
4760 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4761 if ( !fUnrestrictedGuest
4762 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4763 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4764 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4765 }
4766
4767 /* CR4 reserved bits. */
4768 {
4769 /* CR4 MB1 bits. */
4770 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4771 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4772 { /* likely */ }
4773 else
4774 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4775
4776 /* CR4 MBZ bits. */
4777 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4778 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4779 { /* likely */ }
4780 else
4781 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4782 }
4783
4784 /* DEBUGCTL MSR. */
4785 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4786 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4787 { /* likely */ }
4788 else
4789 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4790
4791 /* 64-bit CPU checks. */
4792 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4793 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4794 {
4795 if (fGstInLongMode)
4796 {
4797 /* PAE must be set. */
4798 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4799 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4800 { /* likely */ }
4801 else
4802 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4803 }
4804 else
4805 {
4806 /* PCIDE should not be set. */
4807 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4808 { /* likely */ }
4809 else
4810 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4811 }
4812
4813 /* CR3. */
4814 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4815 { /* likely */ }
4816 else
4817 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4818
4819 /* DR7. */
4820 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4821 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4822 { /* likely */ }
4823 else
4824 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4825
4826 /* SYSENTER ESP and SYSENTER EIP. */
4827 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4828 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4829 { /* likely */ }
4830 else
4831 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4832 }
4833
4834 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4835 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4836
4837 /* PAT MSR. */
4838 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4839 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4840 { /* likely */ }
4841 else
4842 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4843
4844 /* EFER MSR. */
4845 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4846 {
4847 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4848 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4849 { /* likely */ }
4850 else
4851 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4852
4853 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4854 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4855 if ( fGstLma == fGstInLongMode
4856 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4857 || fGstLma == fGstLme))
4858 { /* likely */ }
4859 else
4860 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4861 }
4862
4863 /* We don't support IA32_BNDCFGS MSR yet. */
4864 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4865
4866 NOREF(pszInstr);
4867 NOREF(pszFailure);
4868 return VINF_SUCCESS;
4869}
4870
4871
4872/**
4873 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4874 *
4875 * @param pVCpu The cross context virtual CPU structure.
4876 * @param pszInstr The VMX instruction name (for logging purposes).
4877 */
4878DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4879{
4880 /*
4881 * Segment registers.
4882 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4883 */
4884 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4885 const char * const pszFailure = "VM-exit";
4886 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4887 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4888 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4889
4890 /* Selectors. */
4891 if ( !fGstInV86Mode
4892 && !fUnrestrictedGuest
4893 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4894 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4895
4896 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4897 {
4898 CPUMSELREG SelReg;
4899 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4900 if (RT_LIKELY(rc == VINF_SUCCESS))
4901 { /* likely */ }
4902 else
4903 return rc;
4904
4905 /*
4906 * Virtual-8086 mode checks.
4907 */
4908 if (fGstInV86Mode)
4909 {
4910 /* Base address. */
4911 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4912 { /* likely */ }
4913 else
4914 {
4915 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4916 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4917 }
4918
4919 /* Limit. */
4920 if (SelReg.u32Limit == 0xffff)
4921 { /* likely */ }
4922 else
4923 {
4924 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4925 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4926 }
4927
4928 /* Attribute. */
4929 if (SelReg.Attr.u == 0xf3)
4930 { /* likely */ }
4931 else
4932 {
4933 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4934 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4935 }
4936
4937 /* We're done; move to checking the next segment. */
4938 continue;
4939 }
4940
4941 /* Checks done by 64-bit CPUs. */
4942 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4943 {
4944 /* Base address. */
4945 if ( iSegReg == X86_SREG_FS
4946 || iSegReg == X86_SREG_GS)
4947 {
4948 if (X86_IS_CANONICAL(SelReg.u64Base))
4949 { /* likely */ }
4950 else
4951 {
4952 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4953 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4954 }
4955 }
4956 else if (iSegReg == X86_SREG_CS)
4957 {
4958 if (!RT_HI_U32(SelReg.u64Base))
4959 { /* likely */ }
4960 else
4961 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
4962 }
4963 else
4964 {
4965 if ( SelReg.Attr.n.u1Unusable
4966 || !RT_HI_U32(SelReg.u64Base))
4967 { /* likely */ }
4968 else
4969 {
4970 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4971 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4972 }
4973 }
4974 }
4975
4976 /*
4977 * Checks outside Virtual-8086 mode.
4978 */
4979 uint8_t const uSegType = SelReg.Attr.n.u4Type;
4980 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
4981 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
4982 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
4983 uint8_t const fPresent = SelReg.Attr.n.u1Present;
4984 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
4985 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
4986 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
4987
4988 /* Code or usable segment. */
4989 if ( iSegReg == X86_SREG_CS
4990 || fUsable)
4991 {
4992 /* Reserved bits (bits 31:17 and bits 11:8). */
4993 if (!(SelReg.Attr.u & 0xfffe0f00))
4994 { /* likely */ }
4995 else
4996 {
4997 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
4998 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4999 }
5000
5001 /* Descriptor type. */
5002 if (fCodeDataSeg)
5003 { /* likely */ }
5004 else
5005 {
5006 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5007 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5008 }
5009
5010 /* Present. */
5011 if (fPresent)
5012 { /* likely */ }
5013 else
5014 {
5015 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5016 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5017 }
5018
5019 /* Granularity. */
5020 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5021 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5022 { /* likely */ }
5023 else
5024 {
5025 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5026 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5027 }
5028 }
5029
5030 if (iSegReg == X86_SREG_CS)
5031 {
5032 /* Segment Type and DPL. */
5033 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5034 && fUnrestrictedGuest)
5035 {
5036 if (uDpl == 0)
5037 { /* likely */ }
5038 else
5039 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5040 }
5041 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5042 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5043 {
5044 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5045 if (uDpl == AttrSs.n.u2Dpl)
5046 { /* likely */ }
5047 else
5048 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5049 }
5050 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5051 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5052 {
5053 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5054 if (uDpl <= AttrSs.n.u2Dpl)
5055 { /* likely */ }
5056 else
5057 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5058 }
5059 else
5060 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5061
5062 /* Def/Big. */
5063 if ( fGstInLongMode
5064 && fSegLong)
5065 {
5066 if (uDefBig == 0)
5067 { /* likely */ }
5068 else
5069 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5070 }
5071 }
5072 else if (iSegReg == X86_SREG_SS)
5073 {
5074 /* Segment Type. */
5075 if ( !fUsable
5076 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5077 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5078 { /* likely */ }
5079 else
5080 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5081
5082 /* DPL. */
5083 if (!fUnrestrictedGuest)
5084 {
5085 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5086 { /* likely */ }
5087 else
5088 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5089 }
5090 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5091 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5092 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5093 {
5094 if (uDpl == 0)
5095 { /* likely */ }
5096 else
5097 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5098 }
5099 }
5100 else
5101 {
5102 /* DS, ES, FS, GS. */
5103 if (fUsable)
5104 {
5105 /* Segment type. */
5106 if (uSegType & X86_SEL_TYPE_ACCESSED)
5107 { /* likely */ }
5108 else
5109 {
5110 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5111 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5112 }
5113
5114 if ( !(uSegType & X86_SEL_TYPE_CODE)
5115 || (uSegType & X86_SEL_TYPE_READ))
5116 { /* likely */ }
5117 else
5118 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5119
5120 /* DPL. */
5121 if ( !fUnrestrictedGuest
5122 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5123 {
5124 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5125 { /* likely */ }
5126 else
5127 {
5128 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5129 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5130 }
5131 }
5132 }
5133 }
5134 }
5135
5136 /*
5137 * LDTR.
5138 */
5139 {
5140 CPUMSELREG Ldtr;
5141 Ldtr.Sel = pVmcs->GuestLdtr;
5142 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5143 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5144 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5145
5146 if (!Ldtr.Attr.n.u1Unusable)
5147 {
5148 /* Selector. */
5149 if (!(Ldtr.Sel & X86_SEL_LDT))
5150 { /* likely */ }
5151 else
5152 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5153
5154 /* Base. */
5155 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5156 {
5157 if (X86_IS_CANONICAL(Ldtr.u64Base))
5158 { /* likely */ }
5159 else
5160 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5161 }
5162
5163 /* Attributes. */
5164 /* Reserved bits (bits 31:17 and bits 11:8). */
5165 if (!(Ldtr.Attr.u & 0xfffe0f00))
5166 { /* likely */ }
5167 else
5168 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5169
5170 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5171 { /* likely */ }
5172 else
5173 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5174
5175 if (!Ldtr.Attr.n.u1DescType)
5176 { /* likely */ }
5177 else
5178 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5179
5180 if (Ldtr.Attr.n.u1Present)
5181 { /* likely */ }
5182 else
5183 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5184
5185 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5186 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5187 { /* likely */ }
5188 else
5189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5190 }
5191 }
5192
5193 /*
5194 * TR.
5195 */
5196 {
5197 CPUMSELREG Tr;
5198 Tr.Sel = pVmcs->GuestTr;
5199 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5200 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5201 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5202
5203 /* Selector. */
5204 if (!(Tr.Sel & X86_SEL_LDT))
5205 { /* likely */ }
5206 else
5207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5208
5209 /* Base. */
5210 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5211 {
5212 if (X86_IS_CANONICAL(Tr.u64Base))
5213 { /* likely */ }
5214 else
5215 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5216 }
5217
5218 /* Attributes. */
5219 /* Reserved bits (bits 31:17 and bits 11:8). */
5220 if (!(Tr.Attr.u & 0xfffe0f00))
5221 { /* likely */ }
5222 else
5223 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5224
5225 if (!Tr.Attr.n.u1Unusable)
5226 { /* likely */ }
5227 else
5228 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5229
5230 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5231 || ( !fGstInLongMode
5232 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5233 { /* likely */ }
5234 else
5235 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5236
5237 if (!Tr.Attr.n.u1DescType)
5238 { /* likely */ }
5239 else
5240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5241
5242 if (Tr.Attr.n.u1Present)
5243 { /* likely */ }
5244 else
5245 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5246
5247 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5248 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5249 { /* likely */ }
5250 else
5251 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5252 }
5253
5254 NOREF(pszInstr);
5255 NOREF(pszFailure);
5256 return VINF_SUCCESS;
5257}
5258
5259
5260/**
5261 * Checks guest GDTR and IDTR as part of VM-entry.
5262 *
5263 * @param pVCpu The cross context virtual CPU structure.
5264 * @param pszInstr The VMX instruction name (for logging purposes).
5265 */
5266DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5267{
5268 /*
5269 * GDTR and IDTR.
5270 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5271 */
5272 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5273 const char *const pszFailure = "VM-exit";
5274
5275 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5276 {
5277 /* Base. */
5278 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5279 { /* likely */ }
5280 else
5281 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5282
5283 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5284 { /* likely */ }
5285 else
5286 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5287 }
5288
5289 /* Limit. */
5290 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5291 { /* likely */ }
5292 else
5293 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5294
5295 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5296 { /* likely */ }
5297 else
5298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5299
5300 NOREF(pszInstr);
5301 NOREF(pszFailure);
5302 return VINF_SUCCESS;
5303}
5304
5305
5306/**
5307 * Checks guest RIP and RFLAGS as part of VM-entry.
5308 *
5309 * @param pVCpu The cross context virtual CPU structure.
5310 * @param pszInstr The VMX instruction name (for logging purposes).
5311 */
5312DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5313{
5314 /*
5315 * RIP and RFLAGS.
5316 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5317 */
5318 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5319 const char *const pszFailure = "VM-exit";
5320 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5321
5322 /* RIP. */
5323 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5324 {
5325 X86DESCATTR AttrCs;
5326 AttrCs.u = pVmcs->u32GuestCsAttr;
5327 if ( !fGstInLongMode
5328 || !AttrCs.n.u1Long)
5329 {
5330 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5331 { /* likely */ }
5332 else
5333 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5334 }
5335
5336 if ( fGstInLongMode
5337 && AttrCs.n.u1Long)
5338 {
5339 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5340 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5341 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5342 { /* likely */ }
5343 else
5344 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5345 }
5346 }
5347
5348 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5349 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5350 : pVmcs->u64GuestRFlags.s.Lo;
5351 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5352 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5353 { /* likely */ }
5354 else
5355 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5356
5357 if ( fGstInLongMode
5358 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5359 {
5360 if (!(uGuestRFlags & X86_EFL_VM))
5361 { /* likely */ }
5362 else
5363 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5364 }
5365
5366 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5367 {
5368 if (uGuestRFlags & X86_EFL_IF)
5369 { /* likely */ }
5370 else
5371 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5372 }
5373
5374 NOREF(pszInstr);
5375 NOREF(pszFailure);
5376 return VINF_SUCCESS;
5377}
5378
5379
5380/**
5381 * Checks guest non-register state as part of VM-entry.
5382 *
5383 * @param pVCpu The cross context virtual CPU structure.
5384 * @param pszInstr The VMX instruction name (for logging purposes).
5385 */
5386DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5387{
5388 /*
5389 * Guest non-register state.
5390 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5391 */
5392 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5393 const char *const pszFailure = "VM-exit";
5394
5395 /*
5396 * Activity state.
5397 */
5398 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5399 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5400 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5401 { /* likely */ }
5402 else
5403 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5404
5405 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5406 if ( !AttrSs.n.u2Dpl
5407 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5408 { /* likely */ }
5409 else
5410 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5411
5412 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5413 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5414 {
5415 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5416 { /* likely */ }
5417 else
5418 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5419 }
5420
5421 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5422 {
5423 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5424 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5425 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5426 switch (pVmcs->u32GuestActivityState)
5427 {
5428 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5429 {
5430 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5431 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5432 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5433 && ( uVector == X86_XCPT_DB
5434 || uVector == X86_XCPT_MC))
5435 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5436 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5437 { /* likely */ }
5438 else
5439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5440 break;
5441 }
5442
5443 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5444 {
5445 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5446 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5447 && uVector == X86_XCPT_MC))
5448 { /* likely */ }
5449 else
5450 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5451 break;
5452 }
5453
5454 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5455 default:
5456 break;
5457 }
5458 }
5459
5460 /*
5461 * Interruptibility state.
5462 */
5463 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5464 { /* likely */ }
5465 else
5466 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5467
5468 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5469 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5470 { /* likely */ }
5471 else
5472 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5473
5474 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5475 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5476 { /* likely */ }
5477 else
5478 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5479
5480 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5481 {
5482 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5483 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5484 {
5485 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5486 { /* likely */ }
5487 else
5488 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5489 }
5490 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5491 {
5492 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5493 { /* likely */ }
5494 else
5495 {
5496 /*
5497 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5498 * We update the Exit qualification only when blocking-by-STI is set
5499 * without blocking-by-MovSS being set. Although in practise it does not
5500 * make much difference since the order of checks are implementation defined.
5501 */
5502 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5503 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5504 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5505 }
5506
5507 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5508 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5509 { /* likely */ }
5510 else
5511 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5512 }
5513 }
5514
5515 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5516 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5517 { /* likely */ }
5518 else
5519 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5520
5521 /* We don't support SGX yet. So enclave-interruption must not be set. */
5522 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5523 { /* likely */ }
5524 else
5525 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5526
5527 /*
5528 * Pending debug exceptions.
5529 */
5530 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5531 ? pVmcs->u64GuestPendingDbgXcpts.u
5532 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5533 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5534 { /* likely */ }
5535 else
5536 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5537
5538 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5539 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5540 {
5541 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5542 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5543 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5544 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5545
5546 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5547 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5548 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5549 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5550 }
5551
5552 /* We don't support RTM (Real-time Transactional Memory) yet. */
5553 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5554 { /* likely */ }
5555 else
5556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5557
5558 /*
5559 * VMCS link pointer.
5560 */
5561 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5562 {
5563 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5564 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5565 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5566 { /* likely */ }
5567 else
5568 {
5569 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5570 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5571 }
5572
5573 /* Validate the address. */
5574 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5575 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5576 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5577 { /* likely */ }
5578 else
5579 {
5580 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5581 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5582 }
5583 }
5584
5585 NOREF(pszInstr);
5586 NOREF(pszFailure);
5587 return VINF_SUCCESS;
5588}
5589
5590
5591/**
5592 * Checks guest PDPTEs as part of VM-entry.
5593 *
5594 * @param pVCpu The cross context virtual CPU structure.
5595 * @param pfPdpesMapped Where to store whether PAE PDPTEs (and PDPT) have been
5596 * mapped as part of checking guest state.
5597 * @param pszInstr The VMX instruction name (for logging purposes).
5598 */
5599IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, bool *pfPdpesMapped, const char *pszInstr)
5600{
5601 /*
5602 * Guest PDPTEs.
5603 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5604 */
5605 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5606 const char * const pszFailure = "VM-exit";
5607 *pfPdpesMapped = false;
5608
5609 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
5610 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5611 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5612 {
5613#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5614 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
5615 {
5616 /* Get PDPTEs from the VMCS. */
5617 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
5618 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
5619 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
5620 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
5621 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
5622
5623 /* Check validity of the PDPTEs. */
5624 bool const fValid = PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]);
5625 if (fValid)
5626 { /* likely */ }
5627 else
5628 {
5629 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5630 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5631 }
5632 }
5633 else
5634#endif
5635 {
5636 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
5637 if (rc == VINF_SUCCESS)
5638 *pfPdpesMapped = true;
5639 else
5640 {
5641 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5642 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5643 }
5644 }
5645 }
5646
5647 NOREF(pszInstr);
5648 NOREF(pszFailure);
5649 return VINF_SUCCESS;
5650}
5651
5652
5653/**
5654 * Checks guest-state as part of VM-entry.
5655 *
5656 * @returns VBox status code.
5657 * @param pVCpu The cross context virtual CPU structure.
5658 * @param pfPdpesMapped Where to store whether PAE PDPTEs (and PDPT) have been
5659 * mapped as part of checking guest state.
5660 * @param pszInstr The VMX instruction name (for logging purposes).
5661 */
5662IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, bool *pfPdpesMapped, const char *pszInstr)
5663{
5664 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5665 if (RT_SUCCESS(rc))
5666 {
5667 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5668 if (RT_SUCCESS(rc))
5669 {
5670 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5671 if (RT_SUCCESS(rc))
5672 {
5673 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5674 if (RT_SUCCESS(rc))
5675 {
5676 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5677 if (RT_SUCCESS(rc))
5678 return iemVmxVmentryCheckGuestPdptes(pVCpu, pfPdpesMapped, pszInstr);
5679 }
5680 }
5681 }
5682 }
5683 return rc;
5684}
5685
5686
5687/**
5688 * Checks host-state as part of VM-entry.
5689 *
5690 * @returns VBox status code.
5691 * @param pVCpu The cross context virtual CPU structure.
5692 * @param pszInstr The VMX instruction name (for logging purposes).
5693 */
5694IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5695{
5696 /*
5697 * Host Control Registers and MSRs.
5698 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5699 */
5700 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5701 const char * const pszFailure = "VMFail";
5702
5703 /* CR0 reserved bits. */
5704 {
5705 /* CR0 MB1 bits. */
5706 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5707 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5708 { /* likely */ }
5709 else
5710 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5711
5712 /* CR0 MBZ bits. */
5713 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5714 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5715 { /* likely */ }
5716 else
5717 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5718 }
5719
5720 /* CR4 reserved bits. */
5721 {
5722 /* CR4 MB1 bits. */
5723 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5724 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5725 { /* likely */ }
5726 else
5727 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5728
5729 /* CR4 MBZ bits. */
5730 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5731 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5732 { /* likely */ }
5733 else
5734 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5735 }
5736
5737 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5738 {
5739 /* CR3 reserved bits. */
5740 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5741 { /* likely */ }
5742 else
5743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5744
5745 /* SYSENTER ESP and SYSENTER EIP. */
5746 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5747 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5748 { /* likely */ }
5749 else
5750 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5751 }
5752
5753 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5754 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5755
5756 /* PAT MSR. */
5757 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5758 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5759 { /* likely */ }
5760 else
5761 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5762
5763 /* EFER MSR. */
5764 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5765 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5766 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5767 { /* likely */ }
5768 else
5769 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5770
5771 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5772 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5773 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5774 if ( fHostInLongMode == fHostLma
5775 && fHostInLongMode == fHostLme)
5776 { /* likely */ }
5777 else
5778 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5779
5780 /*
5781 * Host Segment and Descriptor-Table Registers.
5782 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5783 */
5784 /* Selector RPL and TI. */
5785 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5786 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5787 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5788 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5789 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5790 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5791 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5792 { /* likely */ }
5793 else
5794 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5795
5796 /* CS and TR selectors cannot be 0. */
5797 if ( pVmcs->HostCs
5798 && pVmcs->HostTr)
5799 { /* likely */ }
5800 else
5801 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5802
5803 /* SS cannot be 0 if 32-bit host. */
5804 if ( fHostInLongMode
5805 || pVmcs->HostSs)
5806 { /* likely */ }
5807 else
5808 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5809
5810 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5811 {
5812 /* FS, GS, GDTR, IDTR, TR base address. */
5813 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5814 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5815 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5816 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5817 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5818 { /* likely */ }
5819 else
5820 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5821 }
5822
5823 /*
5824 * Host address-space size for 64-bit CPUs.
5825 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5826 */
5827 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5828 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5829 {
5830 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5831
5832 /* Logical processor in IA-32e mode. */
5833 if (fCpuInLongMode)
5834 {
5835 if (fHostInLongMode)
5836 {
5837 /* PAE must be set. */
5838 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5839 { /* likely */ }
5840 else
5841 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5842
5843 /* RIP must be canonical. */
5844 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5845 { /* likely */ }
5846 else
5847 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5848 }
5849 else
5850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5851 }
5852 else
5853 {
5854 /* Logical processor is outside IA-32e mode. */
5855 if ( !fGstInLongMode
5856 && !fHostInLongMode)
5857 {
5858 /* PCIDE should not be set. */
5859 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5860 { /* likely */ }
5861 else
5862 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5863
5864 /* The high 32-bits of RIP MBZ. */
5865 if (!pVmcs->u64HostRip.s.Hi)
5866 { /* likely */ }
5867 else
5868 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5869 }
5870 else
5871 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5872 }
5873 }
5874 else
5875 {
5876 /* Host address-space size for 32-bit CPUs. */
5877 if ( !fGstInLongMode
5878 && !fHostInLongMode)
5879 { /* likely */ }
5880 else
5881 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5882 }
5883
5884 NOREF(pszInstr);
5885 NOREF(pszFailure);
5886 return VINF_SUCCESS;
5887}
5888
5889
5890#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5891/**
5892 * Checks the EPT pointer VMCS field as part of VM-entry.
5893 *
5894 * @returns VBox status code.
5895 * @param pVCpu The cross context virtual CPU structure.
5896 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
5897 * updated on success). Optional, can be NULL.
5898 */
5899IEM_STATIC int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, VMXVDIAG *penmVmxDiag)
5900{
5901 VMXVDIAG enmVmxDiag;
5902 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5903
5904 /* Reserved bits. */
5905 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
5906 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
5907 if (pVmcs->u64EptPtr.u & fValidMask)
5908 {
5909 /* Memory Type. */
5910 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
5911 uint8_t const fMemType = RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_MEMTYPE);
5912 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
5913 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
5914 || ( fMemType == VMX_EPTP_MEMTYPE_UC
5915 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
5916 {
5917 /*
5918 * Page walk length (PML4).
5919 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
5920 * of 5 but that seems to be removed from the latest specs. leaving only PML4
5921 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
5922 */
5923 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
5924 if (RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
5925 {
5926 /* Access and dirty bits support in EPT structures. */
5927 if ( !RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_ACCESS_DIRTY)
5928 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
5929 return VINF_SUCCESS;
5930
5931 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
5932 }
5933 else
5934 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
5935 }
5936 else
5937 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
5938 }
5939 else
5940 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
5941
5942 if (penmVmxDiag)
5943 *penmVmxDiag = enmVmxDiag;
5944 return VERR_VMX_VMENTRY_FAILED;
5945}
5946#endif
5947
5948
5949/**
5950 * Checks VMCS controls fields as part of VM-entry.
5951 *
5952 * @returns VBox status code.
5953 * @param pVCpu The cross context virtual CPU structure.
5954 * @param pszInstr The VMX instruction name (for logging purposes).
5955 *
5956 * @remarks This may update secondary-processor based VM-execution control fields
5957 * in the current VMCS if necessary.
5958 */
5959IEM_STATIC int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr)
5960{
5961 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5962 const char * const pszFailure = "VMFail";
5963
5964 /*
5965 * VM-execution controls.
5966 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
5967 */
5968 {
5969 /* Pin-based VM-execution controls. */
5970 {
5971 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
5972 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
5973 { /* likely */ }
5974 else
5975 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
5976
5977 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
5978 { /* likely */ }
5979 else
5980 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
5981 }
5982
5983 /* Processor-based VM-execution controls. */
5984 {
5985 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
5986 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
5987 { /* likely */ }
5988 else
5989 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
5990
5991 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
5992 { /* likely */ }
5993 else
5994 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
5995 }
5996
5997 /* Secondary processor-based VM-execution controls. */
5998 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
5999 {
6000 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6001 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6002 { /* likely */ }
6003 else
6004 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6005
6006 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6007 { /* likely */ }
6008 else
6009 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6010 }
6011 else
6012 Assert(!pVmcs->u32ProcCtls2);
6013
6014 /* CR3-target count. */
6015 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6016 { /* likely */ }
6017 else
6018 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6019
6020 /* I/O bitmaps physical addresses. */
6021 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6022 {
6023 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6024 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6025 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6026 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6027 { /* likely */ }
6028 else
6029 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6030
6031 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6032 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6033 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6034 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6035 { /* likely */ }
6036 else
6037 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6038 }
6039
6040 /* MSR bitmap physical address. */
6041 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6042 {
6043 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6044 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6045 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6046 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6047 { /* likely */ }
6048 else
6049 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6050 }
6051
6052 /* TPR shadow related controls. */
6053 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6054 {
6055 /* Virtual-APIC page physical address. */
6056 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6057 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6058 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6059 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6060 { /* likely */ }
6061 else
6062 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6063
6064 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6065 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6066 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6067 { /* likely */ }
6068 else
6069 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6070
6071 /* The rest done XXX document */
6072 }
6073 else
6074 {
6075 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6076 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6077 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6078 { /* likely */ }
6079 else
6080 {
6081 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6082 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6083 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6084 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6085 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6086 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6087 }
6088 }
6089
6090 /* NMI exiting and virtual-NMIs. */
6091 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6092 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6093 { /* likely */ }
6094 else
6095 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6096
6097 /* Virtual-NMIs and NMI-window exiting. */
6098 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6099 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6100 { /* likely */ }
6101 else
6102 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6103
6104 /* Virtualize APIC accesses. */
6105 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6106 {
6107 /* APIC-access physical address. */
6108 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6109 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6110 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6111 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6112 { /* likely */ }
6113 else
6114 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6115
6116 /*
6117 * Disallow APIC-access page and virtual-APIC page from being the same address.
6118 * Note! This is not an Intel requirement, but one imposed by our implementation.
6119 */
6120 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6121 * redirecting accesses between the APIC-access page and the virtual-APIC
6122 * page. If any nested hypervisor requires this, we can implement it later. */
6123 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6124 {
6125 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6126 if (GCPhysVirtApic != GCPhysApicAccess)
6127 { /* likely */ }
6128 else
6129 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6130 }
6131 }
6132
6133 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6134 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6135 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6136 { /* likely */ }
6137 else
6138 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6139
6140 /* Virtual-interrupt delivery requires external interrupt exiting. */
6141 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6142 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6143 { /* likely */ }
6144 else
6145 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6146
6147 /* VPID. */
6148 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6149 || pVmcs->u16Vpid != 0)
6150 { /* likely */ }
6151 else
6152 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6153
6154#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6155 /* Extended Page Tables Pointer (EPTP). */
6156 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6157 {
6158 VMXVDIAG enmVmxDiag;
6159 rc = iemVmxVmentryCheckEptPtr(pVCpu, &enmVmxDiag);
6160 if (RT_SUCCESS(rc))
6161 { /* likely */ }
6162 else
6163 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6164 }
6165#else
6166 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6167#endif
6168
6169 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6170 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6171 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6172 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6173 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6174 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6175 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6176
6177 /* VMCS shadowing. */
6178 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6179 {
6180 /* VMREAD-bitmap physical address. */
6181 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6182 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6183 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6184 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6185 { /* likely */ }
6186 else
6187 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6188
6189 /* VMWRITE-bitmap physical address. */
6190 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6191 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6192 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6193 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6194 { /* likely */ }
6195 else
6196 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6197 }
6198 }
6199
6200 /*
6201 * VM-exit controls.
6202 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6203 */
6204 {
6205 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6206 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6207 { /* likely */ }
6208 else
6209 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6210
6211 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6212 { /* likely */ }
6213 else
6214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6215
6216 /* Save preemption timer without activating it. */
6217 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6218 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6219 { /* likely */ }
6220 else
6221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6222
6223 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6224 if (pVmcs->u32ExitMsrStoreCount)
6225 {
6226 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6227 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6228 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6229 { /* likely */ }
6230 else
6231 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6232 }
6233
6234 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6235 if (pVmcs->u32ExitMsrLoadCount)
6236 {
6237 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6238 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6239 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6240 { /* likely */ }
6241 else
6242 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6243 }
6244 }
6245
6246 /*
6247 * VM-entry controls.
6248 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6249 */
6250 {
6251 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6252 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6253 { /* likely */ }
6254 else
6255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6256
6257 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6258 { /* likely */ }
6259 else
6260 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6261
6262 /* Event injection. */
6263 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6264 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6265 {
6266 /* Type and vector. */
6267 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6268 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6269 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6270 if ( !uRsvd
6271 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6272 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6273 { /* likely */ }
6274 else
6275 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6276
6277 /* Exception error code. */
6278 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6279 {
6280 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6281 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6282 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6283 { /* likely */ }
6284 else
6285 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6286
6287 /* Exceptions that provide an error code. */
6288 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6289 && ( uVector == X86_XCPT_DF
6290 || uVector == X86_XCPT_TS
6291 || uVector == X86_XCPT_NP
6292 || uVector == X86_XCPT_SS
6293 || uVector == X86_XCPT_GP
6294 || uVector == X86_XCPT_PF
6295 || uVector == X86_XCPT_AC))
6296 { /* likely */ }
6297 else
6298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6299
6300 /* Exception error-code reserved bits. */
6301 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6302 { /* likely */ }
6303 else
6304 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6305
6306 /* Injecting a software interrupt, software exception or privileged software exception. */
6307 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6308 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6309 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6310 {
6311 /* Instruction length must be in the range 0-15. */
6312 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6313 { /* likely */ }
6314 else
6315 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6316
6317 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6318 if ( pVmcs->u32EntryInstrLen != 0
6319 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6320 { /* likely */ }
6321 else
6322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6323 }
6324 }
6325 }
6326
6327 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6328 if (pVmcs->u32EntryMsrLoadCount)
6329 {
6330 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6331 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6332 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6333 { /* likely */ }
6334 else
6335 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6336 }
6337
6338 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6339 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6340 }
6341
6342 NOREF(pszInstr);
6343 NOREF(pszFailure);
6344 return VINF_SUCCESS;
6345}
6346
6347
6348/**
6349 * Loads the guest control registers, debug register and some MSRs as part of
6350 * VM-entry.
6351 *
6352 * @param pVCpu The cross context virtual CPU structure.
6353 */
6354IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6355{
6356 /*
6357 * Load guest control registers, debug registers and MSRs.
6358 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6359 */
6360 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6361
6362 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6363 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6364 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6365 CPUMSetGuestCR0(pVCpu, uGstCr0);
6366 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6367 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6368
6369 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6370 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6371
6372 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6373 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6374 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6375
6376 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6377 {
6378 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6379
6380 /* EFER MSR. */
6381 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6382 {
6383 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6384 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6385 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6386 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6387 if (fGstInLongMode)
6388 {
6389 /* If the nested-guest is in long mode, LMA and LME are both set. */
6390 Assert(fGstPaging);
6391 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6392 }
6393 else
6394 {
6395 /*
6396 * If the nested-guest is outside long mode:
6397 * - With paging: LMA is cleared, LME is cleared.
6398 * - Without paging: LMA is cleared, LME is left unmodified.
6399 */
6400 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6401 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6402 }
6403 }
6404 /* else: see below. */
6405 }
6406
6407 /* PAT MSR. */
6408 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6409 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6410
6411 /* EFER MSR. */
6412 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6413 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6414
6415 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6416 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6417
6418 /* We don't support IA32_BNDCFGS MSR yet. */
6419 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6420
6421 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6422}
6423
6424
6425/**
6426 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6427 *
6428 * @param pVCpu The cross context virtual CPU structure.
6429 */
6430IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6431{
6432 /*
6433 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6434 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6435 */
6436 /* CS, SS, ES, DS, FS, GS. */
6437 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6438 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6439 {
6440 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6441 CPUMSELREG VmcsSelReg;
6442 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6443 AssertRC(rc); NOREF(rc);
6444 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6445 {
6446 pGstSelReg->Sel = VmcsSelReg.Sel;
6447 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6448 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6449 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6450 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6451 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6452 }
6453 else
6454 {
6455 pGstSelReg->Sel = VmcsSelReg.Sel;
6456 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6457 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6458 switch (iSegReg)
6459 {
6460 case X86_SREG_CS:
6461 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6462 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6463 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6464 break;
6465
6466 case X86_SREG_SS:
6467 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6468 pGstSelReg->u32Limit = 0;
6469 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6470 break;
6471
6472 case X86_SREG_ES:
6473 case X86_SREG_DS:
6474 pGstSelReg->u64Base = 0;
6475 pGstSelReg->u32Limit = 0;
6476 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6477 break;
6478
6479 case X86_SREG_FS:
6480 case X86_SREG_GS:
6481 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6482 pGstSelReg->u32Limit = 0;
6483 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6484 break;
6485 }
6486 Assert(pGstSelReg->Attr.n.u1Unusable);
6487 }
6488 }
6489
6490 /* LDTR. */
6491 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6492 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6493 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6494 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6495 {
6496 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6497 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6498 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6499 }
6500 else
6501 {
6502 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6503 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6504 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6505 }
6506
6507 /* TR. */
6508 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6509 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6510 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6511 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6512 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6513 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6514 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6515
6516 /* GDTR. */
6517 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6518 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6519
6520 /* IDTR. */
6521 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6522 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6523}
6524
6525
6526/**
6527 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6528 *
6529 * @returns VBox status code.
6530 * @param pVCpu The cross context virtual CPU structure.
6531 * @param pszInstr The VMX instruction name (for logging purposes).
6532 */
6533IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6534{
6535 /*
6536 * Load guest MSRs.
6537 * See Intel spec. 26.4 "Loading MSRs".
6538 */
6539 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6540 const char *const pszFailure = "VM-exit";
6541
6542 /*
6543 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6544 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6545 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6546 */
6547 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6548 if (!cMsrs)
6549 return VINF_SUCCESS;
6550
6551 /*
6552 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6553 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6554 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6555 */
6556 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6557 if (fIsMsrCountValid)
6558 { /* likely */ }
6559 else
6560 {
6561 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6562 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6563 }
6564
6565 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6566 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6567 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6568 if (RT_SUCCESS(rc))
6569 {
6570 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6571 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6572 {
6573 if ( !pMsr->u32Reserved
6574 && pMsr->u32Msr != MSR_K8_FS_BASE
6575 && pMsr->u32Msr != MSR_K8_GS_BASE
6576 && pMsr->u32Msr != MSR_K6_EFER
6577 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6578 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6579 {
6580 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6581 if (rcStrict == VINF_SUCCESS)
6582 continue;
6583
6584 /*
6585 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6586 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6587 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6588 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6589 * MSR in ring-0 if possible, or come up with a better, generic solution.
6590 */
6591 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6592 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6593 ? kVmxVDiag_Vmentry_MsrLoadRing3
6594 : kVmxVDiag_Vmentry_MsrLoad;
6595 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6596 }
6597 else
6598 {
6599 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6600 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6601 }
6602 }
6603 }
6604 else
6605 {
6606 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6607 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6608 }
6609
6610 NOREF(pszInstr);
6611 NOREF(pszFailure);
6612 return VINF_SUCCESS;
6613}
6614
6615
6616/**
6617 * Loads the guest-state non-register state as part of VM-entry.
6618 *
6619 * @returns VBox status code.
6620 * @param pVCpu The cross context virtual CPU structure.
6621 *
6622 * @remarks This must be called only after loading the nested-guest register state
6623 * (especially nested-guest RIP).
6624 */
6625IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu)
6626{
6627 /*
6628 * Load guest non-register state.
6629 * See Intel spec. 26.6 "Special Features of VM Entry"
6630 */
6631 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6632
6633 /*
6634 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6635 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6636 *
6637 * See Intel spec. 26.6.1 "Interruptibility State".
6638 */
6639 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6640 if ( !fEntryVectoring
6641 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6642 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6643 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6644 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6645
6646 /* NMI blocking. */
6647 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6648 {
6649 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6650 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6651 else
6652 {
6653 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6654 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6655 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6656 }
6657 }
6658 else
6659 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6660
6661 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6662
6663 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
6664 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6665
6666 /* VPID is irrelevant. We don't support VPID yet. */
6667
6668 /* Clear address-range monitoring. */
6669 EMMonitorWaitClear(pVCpu);
6670}
6671
6672
6673/**
6674 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
6675 *
6676 * @param pVCpu The cross context virtual CPU structure.
6677 * @param pszInstr The VMX instruction name (for logging purposes).
6678 *
6679 * @remarks This assumes various VMCS related data structure pointers have already
6680 * been verified prior to calling this function.
6681 */
6682IEM_STATIC int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr)
6683{
6684 const char *const pszFailure = "VM-exit";
6685 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6686
6687 /*
6688 * Virtualize APIC accesses.
6689 */
6690 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6691 {
6692 /* APIC-access physical address. */
6693 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6694
6695 /*
6696 * Register the handler for the APIC-access page.
6697 *
6698 * We don't deregister the APIC-access page handler during the VM-exit as a different
6699 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6700 *
6701 * We leave the page registered until the first access that happens outside VMX non-root
6702 * mode. Guest software is allowed to access structures such as the APIC-access page
6703 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6704 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6705 *
6706 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6707 */
6708 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6709 {
6710 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6711 PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
6712 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6713 pVCpu0->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6714 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6715 if (RT_SUCCESS(rc))
6716 { /* likely */ }
6717 else
6718 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6719 }
6720 }
6721
6722 /*
6723 * VMCS shadowing.
6724 */
6725 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6726 {
6727 /* Read the VMREAD-bitmap. */
6728 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6729 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
6730 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
6731 if (RT_SUCCESS(rc))
6732 { /* likely */ }
6733 else
6734 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6735
6736 /* Read the VMWRITE-bitmap. */
6737 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
6738 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
6739 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
6740 if (RT_SUCCESS(rc))
6741 { /* likely */ }
6742 else
6743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6744 }
6745
6746 /*
6747 * I/O bitmaps.
6748 */
6749 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6750 {
6751 /* Read the IO bitmap A. */
6752 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6753 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
6754 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
6755 if (RT_SUCCESS(rc))
6756 { /* likely */ }
6757 else
6758 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
6759
6760 /* Read the IO bitmap B. */
6761 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6762 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
6763 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
6764 if (RT_SUCCESS(rc))
6765 { /* likely */ }
6766 else
6767 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
6768 }
6769
6770 /*
6771 * TPR shadow and Virtual-APIC page.
6772 */
6773 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6774 {
6775 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6776 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6777 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6778 {
6779 /* Read the VTPR from the virtual-APIC page. */
6780 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6781 uint8_t u8VTpr;
6782 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6783 if (RT_SUCCESS(rc))
6784 { /* likely */ }
6785 else
6786 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6787
6788 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6789 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6790 { /* likely */ }
6791 else
6792 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6793 }
6794 }
6795
6796 /*
6797 * VMCS link pointer.
6798 */
6799 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6800 {
6801 /* Read the VMCS-link pointer from guest memory. */
6802 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6803 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
6804 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
6805 if (RT_SUCCESS(rc))
6806 { /* likely */ }
6807 else
6808 {
6809 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6810 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6811 }
6812
6813 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6814 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6815 { /* likely */ }
6816 else
6817 {
6818 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6819 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6820 }
6821
6822 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6823 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6824 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
6825 { /* likely */ }
6826 else
6827 {
6828 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6829 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6830 }
6831
6832 /* Update our cache of the guest physical address of the shadow VMCS. */
6833 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6834 }
6835
6836 /*
6837 * MSR bitmap.
6838 */
6839 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6840 {
6841 /* Read the MSR bitmap. */
6842 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6843 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
6844 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
6845 if (RT_SUCCESS(rc))
6846 { /* likely */ }
6847 else
6848 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6849 }
6850
6851 NOREF(pszFailure);
6852 NOREF(pszInstr);
6853 return VINF_SUCCESS;
6854}
6855
6856
6857/**
6858 * Loads the guest-state as part of VM-entry.
6859 *
6860 * @returns VBox status code.
6861 * @param pVCpu The cross context virtual CPU structure.
6862 * @param pszInstr The VMX instruction name (for logging purposes).
6863 *
6864 * @remarks This must be done after all the necessary steps prior to loading of
6865 * guest-state (e.g. checking various VMCS state).
6866 */
6867IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6868{
6869 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
6870 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6871
6872 /* Load guest segment registers. */
6873 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6874
6875 /*
6876 * Load guest RIP, RSP and RFLAGS.
6877 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6878 */
6879 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6880 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6881 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6882 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6883
6884 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6885 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6886 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6887
6888 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
6889 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6890
6891 /* Load VMX related structures and state referenced by the VMCS. */
6892 int rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
6893 if (rc == VINF_SUCCESS)
6894 { /* likely */ }
6895 else
6896 return rc;
6897
6898 NOREF(pszInstr);
6899 return VINF_SUCCESS;
6900}
6901
6902
6903/**
6904 * Returns whether there are is a pending debug exception on VM-entry.
6905 *
6906 * @param pVCpu The cross context virtual CPU structure.
6907 * @param pszInstr The VMX instruction name (for logging purposes).
6908 */
6909IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6910{
6911 /*
6912 * Pending debug exceptions.
6913 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6914 */
6915 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6916 Assert(pVmcs);
6917
6918 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6919 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6920 if (fPendingDbgXcpt)
6921 {
6922 uint8_t uEntryIntInfoType;
6923 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6924 if (fEntryVectoring)
6925 {
6926 switch (uEntryIntInfoType)
6927 {
6928 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6929 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6930 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6931 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6932 fPendingDbgXcpt = false;
6933 break;
6934
6935 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6936 {
6937 /*
6938 * Whether the pending debug exception for software exceptions other than
6939 * #BP and #OF is delivered after injecting the exception or is discard
6940 * is CPU implementation specific. We will discard them (easier).
6941 */
6942 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6943 if ( uVector != X86_XCPT_BP
6944 && uVector != X86_XCPT_OF)
6945 fPendingDbgXcpt = false;
6946 RT_FALL_THRU();
6947 }
6948 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6949 {
6950 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6951 fPendingDbgXcpt = false;
6952 break;
6953 }
6954 }
6955 }
6956 else
6957 {
6958 /*
6959 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6960 * pending debug exception is held pending or is discarded is CPU implementation
6961 * specific. We will discard them (easier).
6962 */
6963 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6964 fPendingDbgXcpt = false;
6965
6966 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
6967 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
6968 fPendingDbgXcpt = false;
6969 }
6970 }
6971
6972 NOREF(pszInstr);
6973 return fPendingDbgXcpt;
6974}
6975
6976
6977/**
6978 * Set up the monitor-trap flag (MTF).
6979 *
6980 * @param pVCpu The cross context virtual CPU structure.
6981 * @param pszInstr The VMX instruction name (for logging purposes).
6982 */
6983IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
6984{
6985 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6986 Assert(pVmcs);
6987 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
6988 {
6989 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
6990 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
6991 }
6992 else
6993 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
6994 NOREF(pszInstr);
6995}
6996
6997
6998/**
6999 * Sets up NMI-window exiting.
7000 *
7001 * @param pVCpu The cross context virtual CPU structure.
7002 * @param pszInstr The VMX instruction name (for logging purposes).
7003 */
7004IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
7005{
7006 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7007 Assert(pVmcs);
7008 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7009 {
7010 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7011 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7012 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7013 }
7014 else
7015 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7016 NOREF(pszInstr);
7017}
7018
7019
7020/**
7021 * Sets up interrupt-window exiting.
7022 *
7023 * @param pVCpu The cross context virtual CPU structure.
7024 * @param pszInstr The VMX instruction name (for logging purposes).
7025 */
7026IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
7027{
7028 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7029 Assert(pVmcs);
7030 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7031 {
7032 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7033 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7034 }
7035 else
7036 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7037 NOREF(pszInstr);
7038}
7039
7040
7041/**
7042 * Set up the VMX-preemption timer.
7043 *
7044 * @param pVCpu The cross context virtual CPU structure.
7045 * @param pszInstr The VMX instruction name (for logging purposes).
7046 */
7047IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
7048{
7049 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7050 Assert(pVmcs);
7051 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7052 {
7053 /*
7054 * If the timer is 0, we must cause a VM-exit before executing the first
7055 * nested-guest instruction. So we can flag as though the timer has already
7056 * expired and we will check and cause a VM-exit at the right priority elsewhere
7057 * in the code.
7058 */
7059 uint64_t uEntryTick;
7060 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7061 if (uPreemptTimer)
7062 {
7063 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7064 AssertRC(rc);
7065 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7066 }
7067 else
7068 {
7069 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7070 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7071 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7072 }
7073
7074 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7075 }
7076 else
7077 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7078
7079 NOREF(pszInstr);
7080}
7081
7082
7083/**
7084 * Injects an event using TRPM given a VM-entry interruption info. and related
7085 * fields.
7086 *
7087 * @param pVCpu The cross context virtual CPU structure.
7088 * @param pszInstr The VMX instruction name (for logging purposes).
7089 * @param uEntryIntInfo The VM-entry interruption info.
7090 * @param uErrCode The error code associated with the event if any.
7091 * @param cbInstr The VM-entry instruction length (for software
7092 * interrupts and software exceptions). Pass 0
7093 * otherwise.
7094 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7095 */
7096IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7097 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7098{
7099 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7100
7101 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7102 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7103 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7104
7105 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7106
7107 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7108 AssertRC(rc);
7109 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7110
7111 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7112 {
7113 TRPMSetErrorCode(pVCpu, uErrCode);
7114 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7115 }
7116
7117 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7118 {
7119 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7120 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7121 }
7122 else
7123 {
7124 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7125 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7126 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7127 {
7128 TRPMSetInstrLength(pVCpu, cbInstr);
7129 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7130 }
7131 }
7132
7133 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7134 {
7135 TRPMSetTrapDueToIcebp(pVCpu);
7136 Log(("%s: Injecting: icebp\n", pszInstr));
7137 }
7138
7139 NOREF(pszInstr);
7140}
7141
7142
7143/**
7144 * Performs event injection (if any) as part of VM-entry.
7145 *
7146 * @param pVCpu The cross context virtual CPU structure.
7147 * @param pszInstr The VMX instruction name (for logging purposes).
7148 */
7149IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7150{
7151 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7152
7153 /*
7154 * Inject events.
7155 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7156 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7157 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7158 * the actually delivery of this event.
7159 *
7160 * See Intel spec. 26.5 "Event Injection".
7161 */
7162 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7163 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7164
7165 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7166 if (fEntryIntInfoValid)
7167 {
7168 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7169 {
7170 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7171 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7172 }
7173 else
7174 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7175 pVCpu->cpum.GstCtx.cr2);
7176
7177 /*
7178 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7179 *
7180 * However, we do it here on VM-entry as well because while it isn't visible to guest
7181 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7182 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7183 *
7184 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7185 */
7186 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7187 }
7188 else
7189 {
7190 /*
7191 * Inject any pending guest debug exception.
7192 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7193 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7194 */
7195 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7196 if (fPendingDbgXcpt)
7197 {
7198 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7199 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7200 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7201 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7202 0 /* GCPtrFaultAddress */);
7203 }
7204 }
7205
7206 NOREF(pszInstr);
7207}
7208
7209
7210/**
7211 * Initializes all read-only VMCS fields as part of VM-entry.
7212 *
7213 * @param pVCpu The cross context virtual CPU structure.
7214 */
7215IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7216{
7217 /*
7218 * Any VMCS field which we do not establish on every VM-exit but may potentially
7219 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7220 * specified to be undefined, needs to be initialized here.
7221 *
7222 * Thus, it is especially important to clear the Exit qualification field
7223 * since it must be zero for VM-exits where it is not used. Similarly, the
7224 * VM-exit interruption information field's valid bit needs to be cleared for
7225 * the same reasons.
7226 */
7227 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7228 Assert(pVmcs);
7229
7230 /* 16-bit (none currently). */
7231 /* 32-bit. */
7232 pVmcs->u32RoVmInstrError = 0;
7233 pVmcs->u32RoExitReason = 0;
7234 pVmcs->u32RoExitIntInfo = 0;
7235 pVmcs->u32RoExitIntErrCode = 0;
7236 pVmcs->u32RoIdtVectoringInfo = 0;
7237 pVmcs->u32RoIdtVectoringErrCode = 0;
7238 pVmcs->u32RoExitInstrLen = 0;
7239 pVmcs->u32RoExitInstrInfo = 0;
7240
7241 /* 64-bit. */
7242 pVmcs->u64RoGuestPhysAddr.u = 0;
7243
7244 /* Natural-width. */
7245 pVmcs->u64RoExitQual.u = 0;
7246 pVmcs->u64RoIoRcx.u = 0;
7247 pVmcs->u64RoIoRsi.u = 0;
7248 pVmcs->u64RoIoRdi.u = 0;
7249 pVmcs->u64RoIoRip.u = 0;
7250 pVmcs->u64RoGuestLinearAddr.u = 0;
7251}
7252
7253
7254/**
7255 * VMLAUNCH/VMRESUME instruction execution worker.
7256 *
7257 * @returns Strict VBox status code.
7258 * @param pVCpu The cross context virtual CPU structure.
7259 * @param cbInstr The instruction length in bytes.
7260 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7261 * VMXINSTRID_VMRESUME).
7262 *
7263 * @remarks Common VMX instruction checks are already expected to by the caller,
7264 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7265 */
7266IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7267{
7268# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7269 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7270 return VINF_EM_RAW_EMULATE_INSTR;
7271# else
7272 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7273 || uInstrId == VMXINSTRID_VMRESUME);
7274 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7275
7276 /* Nested-guest intercept. */
7277 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7278 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7279
7280 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7281
7282 /*
7283 * Basic VM-entry checks.
7284 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7285 * The checks following that do not have to follow a specific order.
7286 *
7287 * See Intel spec. 26.1 "Basic VM-entry Checks".
7288 */
7289
7290 /* CPL. */
7291 if (pVCpu->iem.s.uCpl == 0)
7292 { /* likely */ }
7293 else
7294 {
7295 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7296 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7297 return iemRaiseGeneralProtectionFault0(pVCpu);
7298 }
7299
7300 /* Current VMCS valid. */
7301 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7302 { /* likely */ }
7303 else
7304 {
7305 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7306 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7307 iemVmxVmFailInvalid(pVCpu);
7308 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7309 return VINF_SUCCESS;
7310 }
7311
7312 /* Current VMCS is not a shadow VMCS. */
7313 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7314 { /* likely */ }
7315 else
7316 {
7317 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7318 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7319 iemVmxVmFailInvalid(pVCpu);
7320 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7321 return VINF_SUCCESS;
7322 }
7323
7324 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7325 * use block-by-STI here which is not quite correct. */
7326 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7327 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7328 { /* likely */ }
7329 else
7330 {
7331 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7332 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7333 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7334 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7335 return VINF_SUCCESS;
7336 }
7337
7338 if (uInstrId == VMXINSTRID_VMLAUNCH)
7339 {
7340 /* VMLAUNCH with non-clear VMCS. */
7341 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7342 { /* likely */ }
7343 else
7344 {
7345 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7346 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7347 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7348 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7349 return VINF_SUCCESS;
7350 }
7351 }
7352 else
7353 {
7354 /* VMRESUME with non-launched VMCS. */
7355 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7356 { /* likely */ }
7357 else
7358 {
7359 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7360 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7361 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7362 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7363 return VINF_SUCCESS;
7364 }
7365 }
7366
7367 /*
7368 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7369 * while entering VMX non-root mode. We do some of this while checking VM-execution
7370 * controls. The nested hypervisor should not make assumptions and cannot expect
7371 * predictable behavior if changes to these structures are made in guest memory while
7372 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7373 * modify them anyway as we cache them in host memory.
7374 *
7375 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7376 */
7377 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7378 Assert(pVmcs);
7379 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7380
7381 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7382 if (RT_SUCCESS(rc))
7383 {
7384 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7385 if (RT_SUCCESS(rc))
7386 {
7387 /*
7388 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7389 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7390 * ones that may occur during VM-entry below).
7391 */
7392 iemVmxVmentryInitReadOnlyFields(pVCpu);
7393
7394 /*
7395 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7396 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7397 * VM-exit when required.
7398 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7399 */
7400 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7401
7402 bool fPdpesMapped;
7403 rc = iemVmxVmentryCheckGuestState(pVCpu, &fPdpesMapped, pszInstr);
7404 if (RT_SUCCESS(rc))
7405 {
7406 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7407 if (RT_SUCCESS(rc))
7408 {
7409 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7410 if (RT_SUCCESS(rc))
7411 {
7412 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7413
7414 /* VMLAUNCH instruction must update the VMCS launch state. */
7415 if (uInstrId == VMXINSTRID_VMLAUNCH)
7416 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7417
7418 /* Perform the VMX transition (PGM updates). */
7419 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu, fPdpesMapped);
7420 if (rcStrict == VINF_SUCCESS)
7421 { /* likely */ }
7422 else if (RT_SUCCESS(rcStrict))
7423 {
7424 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7425 VBOXSTRICTRC_VAL(rcStrict)));
7426 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7427 }
7428 else
7429 {
7430 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7431 return rcStrict;
7432 }
7433
7434 /* Paranoia. */
7435 Assert(rcStrict == VINF_SUCCESS);
7436
7437 /* We've now entered nested-guest execution. */
7438 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7439
7440 /*
7441 * The priority of potential VM-exits during VM-entry is important.
7442 * The priorities of VM-exits and events are listed from highest
7443 * to lowest as follows:
7444 *
7445 * 1. Event injection.
7446 * 2. Trap on task-switch (T flag set in TSS).
7447 * 3. TPR below threshold / APIC-write.
7448 * 4. SMI, INIT.
7449 * 5. MTF exit.
7450 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7451 * 7. VMX-preemption timer.
7452 * 9. NMI-window exit.
7453 * 10. NMI injection.
7454 * 11. Interrupt-window exit.
7455 * 12. Virtual-interrupt injection.
7456 * 13. Interrupt injection.
7457 * 14. Process next instruction (fetch, decode, execute).
7458 */
7459
7460 /* Setup VMX-preemption timer. */
7461 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7462
7463 /* Setup monitor-trap flag. */
7464 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7465
7466 /* Setup NMI-window exiting. */
7467 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7468
7469 /* Setup interrupt-window exiting. */
7470 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7471
7472 /*
7473 * Inject any event that the nested hypervisor wants to inject.
7474 * Note! We cannot immediately perform the event injection here as we may have
7475 * pending PGM operations to perform due to switching page tables and/or
7476 * mode.
7477 */
7478 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7479
7480# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7481 /* Reschedule to IEM-only execution of the nested-guest. */
7482 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7483 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7484 if (rcSched != VINF_SUCCESS)
7485 iemSetPassUpStatus(pVCpu, rcSched);
7486# endif
7487
7488 /* Finally, done. */
7489 Log3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",
7490 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7491 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7492 pVCpu->cpum.GstCtx.msrEFER));
7493 return VINF_SUCCESS;
7494 }
7495 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7496 pVmcs->u64RoExitQual.u);
7497 }
7498 }
7499 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7500 pVmcs->u64RoExitQual.u);
7501 }
7502
7503 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7504 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7505 return VINF_SUCCESS;
7506 }
7507
7508 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7509 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7510 return VINF_SUCCESS;
7511# endif
7512}
7513
7514
7515/**
7516 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7517 * (causes a VM-exit) or not.
7518 *
7519 * @returns @c true if the instruction is intercepted, @c false otherwise.
7520 * @param pVCpu The cross context virtual CPU structure.
7521 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7522 * VMX_EXIT_WRMSR).
7523 * @param idMsr The MSR.
7524 */
7525IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7526{
7527 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7528 Assert( uExitReason == VMX_EXIT_RDMSR
7529 || uExitReason == VMX_EXIT_WRMSR);
7530
7531 /* Consult the MSR bitmap if the feature is supported. */
7532 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7533 Assert(pVmcs);
7534 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7535 {
7536 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7537 if (uExitReason == VMX_EXIT_RDMSR)
7538 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7539 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7540 }
7541
7542 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7543 return true;
7544}
7545
7546
7547/**
7548 * VMREAD instruction execution worker that does not perform any validation checks.
7549 *
7550 * Callers are expected to have performed the necessary checks and to ensure the
7551 * VMREAD will succeed.
7552 *
7553 * @param pVmcs Pointer to the virtual VMCS.
7554 * @param pu64Dst Where to write the VMCS value.
7555 * @param u64VmcsField The VMCS field.
7556 *
7557 * @remarks May be called with interrupts disabled.
7558 */
7559IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7560{
7561 VMXVMCSFIELD VmcsField;
7562 VmcsField.u = u64VmcsField;
7563 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7564 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7565 uint8_t const uWidthType = (uWidth << 2) | uType;
7566 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7567 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7568 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7569 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
7570 uWidth, uType, uIndex, uIndex));
7571 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7572
7573 /*
7574 * Read the VMCS component based on the field's effective width.
7575 *
7576 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7577 * indicates high bits (little endian).
7578 *
7579 * Note! The caller is responsible to trim the result and update registers
7580 * or memory locations are required. Here we just zero-extend to the largest
7581 * type (i.e. 64-bits).
7582 */
7583 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7584 uint8_t const *pbField = pbVmcs + offField;
7585 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7586 switch (uEffWidth)
7587 {
7588 case VMX_VMCSFIELD_WIDTH_64BIT:
7589 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7590 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7591 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7592 }
7593}
7594
7595
7596/**
7597 * VMREAD common (memory/register) instruction execution worker.
7598 *
7599 * @returns Strict VBox status code.
7600 * @param pVCpu The cross context virtual CPU structure.
7601 * @param cbInstr The instruction length in bytes.
7602 * @param pu64Dst Where to write the VMCS value (only updated when
7603 * VINF_SUCCESS is returned).
7604 * @param u64VmcsField The VMCS field.
7605 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7606 * NULL.
7607 */
7608IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7609 PCVMXVEXITINFO pExitInfo)
7610{
7611 /* Nested-guest intercept. */
7612 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7613 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7614 {
7615 if (pExitInfo)
7616 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7617 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7618 }
7619
7620 /* CPL. */
7621 if (pVCpu->iem.s.uCpl == 0)
7622 { /* likely */ }
7623 else
7624 {
7625 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7626 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7627 return iemRaiseGeneralProtectionFault0(pVCpu);
7628 }
7629
7630 /* VMCS pointer in root mode. */
7631 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7632 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7633 { /* likely */ }
7634 else
7635 {
7636 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7637 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7638 iemVmxVmFailInvalid(pVCpu);
7639 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7640 return VINF_SUCCESS;
7641 }
7642
7643 /* VMCS-link pointer in non-root mode. */
7644 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7645 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7646 { /* likely */ }
7647 else
7648 {
7649 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7650 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7651 iemVmxVmFailInvalid(pVCpu);
7652 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7653 return VINF_SUCCESS;
7654 }
7655
7656 /* Supported VMCS field. */
7657 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7658 { /* likely */ }
7659 else
7660 {
7661 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7662 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7663 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7664 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7665 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7666 return VINF_SUCCESS;
7667 }
7668
7669 /*
7670 * Reading from the current or shadow VMCS.
7671 */
7672 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7673 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7674 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7675 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7676 return VINF_SUCCESS;
7677}
7678
7679
7680/**
7681 * VMREAD (64-bit register) instruction execution worker.
7682 *
7683 * @returns Strict VBox status code.
7684 * @param pVCpu The cross context virtual CPU structure.
7685 * @param cbInstr The instruction length in bytes.
7686 * @param pu64Dst Where to store the VMCS field's value.
7687 * @param u64VmcsField The VMCS field.
7688 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7689 * NULL.
7690 */
7691IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7692 PCVMXVEXITINFO pExitInfo)
7693{
7694 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7695 if (rcStrict == VINF_SUCCESS)
7696 {
7697 iemVmxVmreadSuccess(pVCpu, cbInstr);
7698 return VINF_SUCCESS;
7699 }
7700
7701 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7702 return rcStrict;
7703}
7704
7705
7706/**
7707 * VMREAD (32-bit register) instruction execution worker.
7708 *
7709 * @returns Strict VBox status code.
7710 * @param pVCpu The cross context virtual CPU structure.
7711 * @param cbInstr The instruction length in bytes.
7712 * @param pu32Dst Where to store the VMCS field's value.
7713 * @param u32VmcsField The VMCS field.
7714 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7715 * NULL.
7716 */
7717IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7718 PCVMXVEXITINFO pExitInfo)
7719{
7720 uint64_t u64Dst;
7721 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7722 if (rcStrict == VINF_SUCCESS)
7723 {
7724 *pu32Dst = u64Dst;
7725 iemVmxVmreadSuccess(pVCpu, cbInstr);
7726 return VINF_SUCCESS;
7727 }
7728
7729 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7730 return rcStrict;
7731}
7732
7733
7734/**
7735 * VMREAD (memory) instruction execution worker.
7736 *
7737 * @returns Strict VBox status code.
7738 * @param pVCpu The cross context virtual CPU structure.
7739 * @param cbInstr The instruction length in bytes.
7740 * @param iEffSeg The effective segment register to use with @a u64Val.
7741 * Pass UINT8_MAX if it is a register access.
7742 * @param GCPtrDst The guest linear address to store the VMCS field's
7743 * value.
7744 * @param u64VmcsField The VMCS field.
7745 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7746 * NULL.
7747 */
7748IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7749 PCVMXVEXITINFO pExitInfo)
7750{
7751 uint64_t u64Dst;
7752 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7753 if (rcStrict == VINF_SUCCESS)
7754 {
7755 /*
7756 * Write the VMCS field's value to the location specified in guest-memory.
7757 */
7758 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7759 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7760 else
7761 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7762 if (rcStrict == VINF_SUCCESS)
7763 {
7764 iemVmxVmreadSuccess(pVCpu, cbInstr);
7765 return VINF_SUCCESS;
7766 }
7767
7768 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7769 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7770 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7771 return rcStrict;
7772 }
7773
7774 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7775 return rcStrict;
7776}
7777
7778
7779/**
7780 * VMWRITE instruction execution worker that does not perform any validation
7781 * checks.
7782 *
7783 * Callers are expected to have performed the necessary checks and to ensure the
7784 * VMWRITE will succeed.
7785 *
7786 * @param pVmcs Pointer to the virtual VMCS.
7787 * @param u64Val The value to write.
7788 * @param u64VmcsField The VMCS field.
7789 *
7790 * @remarks May be called with interrupts disabled.
7791 */
7792IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7793{
7794 VMXVMCSFIELD VmcsField;
7795 VmcsField.u = u64VmcsField;
7796 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7797 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7798 uint8_t const uWidthType = (uWidth << 2) | uType;
7799 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7800 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7801 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7802 Assert(offField < VMX_V_VMCS_SIZE);
7803 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7804
7805 /*
7806 * Write the VMCS component based on the field's effective width.
7807 *
7808 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7809 * indicates high bits (little endian).
7810 */
7811 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7812 uint8_t *pbField = pbVmcs + offField;
7813 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7814 switch (uEffWidth)
7815 {
7816 case VMX_VMCSFIELD_WIDTH_64BIT:
7817 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7818 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7819 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7820 }
7821}
7822
7823
7824/**
7825 * VMWRITE instruction execution worker.
7826 *
7827 * @returns Strict VBox status code.
7828 * @param pVCpu The cross context virtual CPU structure.
7829 * @param cbInstr The instruction length in bytes.
7830 * @param iEffSeg The effective segment register to use with @a u64Val.
7831 * Pass UINT8_MAX if it is a register access.
7832 * @param u64Val The value to write (or guest linear address to the
7833 * value), @a iEffSeg will indicate if it's a memory
7834 * operand.
7835 * @param u64VmcsField The VMCS field.
7836 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7837 * NULL.
7838 */
7839IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7840 PCVMXVEXITINFO pExitInfo)
7841{
7842 /* Nested-guest intercept. */
7843 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7844 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7845 {
7846 if (pExitInfo)
7847 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7848 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7849 }
7850
7851 /* CPL. */
7852 if (pVCpu->iem.s.uCpl == 0)
7853 { /* likely */ }
7854 else
7855 {
7856 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7857 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7858 return iemRaiseGeneralProtectionFault0(pVCpu);
7859 }
7860
7861 /* VMCS pointer in root mode. */
7862 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7863 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7864 { /* likely */ }
7865 else
7866 {
7867 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7868 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7869 iemVmxVmFailInvalid(pVCpu);
7870 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7871 return VINF_SUCCESS;
7872 }
7873
7874 /* VMCS-link pointer in non-root mode. */
7875 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7876 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7877 { /* likely */ }
7878 else
7879 {
7880 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7881 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7882 iemVmxVmFailInvalid(pVCpu);
7883 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7884 return VINF_SUCCESS;
7885 }
7886
7887 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7888 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7889 if (!fIsRegOperand)
7890 {
7891 /* Read the value from the specified guest memory location. */
7892 VBOXSTRICTRC rcStrict;
7893 RTGCPTR const GCPtrVal = u64Val;
7894 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7895 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7896 else
7897 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7898 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7899 {
7900 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7901 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7902 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7903 return rcStrict;
7904 }
7905 }
7906 else
7907 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7908
7909 /* Supported VMCS field. */
7910 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7911 { /* likely */ }
7912 else
7913 {
7914 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7915 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7916 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7917 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7918 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7919 return VINF_SUCCESS;
7920 }
7921
7922 /* Read-only VMCS field. */
7923 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7924 if ( !fIsFieldReadOnly
7925 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7926 { /* likely */ }
7927 else
7928 {
7929 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7930 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7931 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7932 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7933 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7934 return VINF_SUCCESS;
7935 }
7936
7937 /*
7938 * Write to the current or shadow VMCS.
7939 */
7940 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7941 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7942 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7943 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7944 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7945
7946 /* Notify HM that the VMCS content might have changed. */
7947 if (!fInVmxNonRootMode)
7948 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7949
7950 iemVmxVmSucceed(pVCpu);
7951 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7952 return VINF_SUCCESS;
7953}
7954
7955
7956/**
7957 * VMCLEAR instruction execution worker.
7958 *
7959 * @returns Strict VBox status code.
7960 * @param pVCpu The cross context virtual CPU structure.
7961 * @param cbInstr The instruction length in bytes.
7962 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7963 * @param GCPtrVmcs The linear address of the VMCS pointer.
7964 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7965 *
7966 * @remarks Common VMX instruction checks are already expected to by the caller,
7967 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7968 */
7969IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
7970 PCVMXVEXITINFO pExitInfo)
7971{
7972 /* Nested-guest intercept. */
7973 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7974 {
7975 if (pExitInfo)
7976 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7977 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
7978 }
7979
7980 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7981
7982 /* CPL. */
7983 if (pVCpu->iem.s.uCpl == 0)
7984 { /* likely */ }
7985 else
7986 {
7987 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7988 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
7989 return iemRaiseGeneralProtectionFault0(pVCpu);
7990 }
7991
7992 /* Get the VMCS pointer from the location specified by the source memory operand. */
7993 RTGCPHYS GCPhysVmcs;
7994 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
7995 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
7996 { /* likely */ }
7997 else
7998 {
7999 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8000 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8001 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8002 return rcStrict;
8003 }
8004
8005 /* VMCS pointer alignment. */
8006 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8007 { /* likely */ }
8008 else
8009 {
8010 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8011 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8012 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8013 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8014 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8015 return VINF_SUCCESS;
8016 }
8017
8018 /* VMCS physical-address width limits. */
8019 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8020 { /* likely */ }
8021 else
8022 {
8023 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8024 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8025 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8026 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8027 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8028 return VINF_SUCCESS;
8029 }
8030
8031 /* VMCS is not the VMXON region. */
8032 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8033 { /* likely */ }
8034 else
8035 {
8036 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8037 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8038 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8039 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8040 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8041 return VINF_SUCCESS;
8042 }
8043
8044 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8045 restriction imposed by our implementation. */
8046 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8047 { /* likely */ }
8048 else
8049 {
8050 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8051 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8052 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8053 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8054 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8055 return VINF_SUCCESS;
8056 }
8057
8058 /*
8059 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8060 *
8061 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8062 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8063 * to 'clear'.
8064 */
8065 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8066 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8067 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8068 {
8069 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8070 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8071 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8072 }
8073 else
8074 {
8075 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8076 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8077 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8078 if (RT_FAILURE(rcStrict))
8079 return rcStrict;
8080 }
8081
8082 iemVmxVmSucceed(pVCpu);
8083 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8084 return VINF_SUCCESS;
8085}
8086
8087
8088/**
8089 * VMPTRST instruction execution worker.
8090 *
8091 * @returns Strict VBox status code.
8092 * @param pVCpu The cross context virtual CPU structure.
8093 * @param cbInstr The instruction length in bytes.
8094 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8095 * @param GCPtrVmcs The linear address of where to store the current VMCS
8096 * pointer.
8097 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8098 *
8099 * @remarks Common VMX instruction checks are already expected to by the caller,
8100 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8101 */
8102IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8103 PCVMXVEXITINFO pExitInfo)
8104{
8105 /* Nested-guest intercept. */
8106 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8107 {
8108 if (pExitInfo)
8109 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8110 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8111 }
8112
8113 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8114
8115 /* CPL. */
8116 if (pVCpu->iem.s.uCpl == 0)
8117 { /* likely */ }
8118 else
8119 {
8120 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8121 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8122 return iemRaiseGeneralProtectionFault0(pVCpu);
8123 }
8124
8125 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8126 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8127 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8128 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8129 {
8130 iemVmxVmSucceed(pVCpu);
8131 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8132 return rcStrict;
8133 }
8134
8135 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8136 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8137 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8138 return rcStrict;
8139}
8140
8141
8142/**
8143 * VMPTRLD instruction execution worker.
8144 *
8145 * @returns Strict VBox status code.
8146 * @param pVCpu The cross context virtual CPU structure.
8147 * @param cbInstr The instruction length in bytes.
8148 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8149 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8150 *
8151 * @remarks Common VMX instruction checks are already expected to by the caller,
8152 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8153 */
8154IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8155 PCVMXVEXITINFO pExitInfo)
8156{
8157 /* Nested-guest intercept. */
8158 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8159 {
8160 if (pExitInfo)
8161 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8162 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8163 }
8164
8165 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8166
8167 /* CPL. */
8168 if (pVCpu->iem.s.uCpl == 0)
8169 { /* likely */ }
8170 else
8171 {
8172 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8173 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8174 return iemRaiseGeneralProtectionFault0(pVCpu);
8175 }
8176
8177 /* Get the VMCS pointer from the location specified by the source memory operand. */
8178 RTGCPHYS GCPhysVmcs;
8179 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8180 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8181 { /* likely */ }
8182 else
8183 {
8184 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8185 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8186 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8187 return rcStrict;
8188 }
8189
8190 /* VMCS pointer alignment. */
8191 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8192 { /* likely */ }
8193 else
8194 {
8195 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8196 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8197 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8198 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8199 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8200 return VINF_SUCCESS;
8201 }
8202
8203 /* VMCS physical-address width limits. */
8204 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8205 { /* likely */ }
8206 else
8207 {
8208 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8209 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8210 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8211 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8212 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8213 return VINF_SUCCESS;
8214 }
8215
8216 /* VMCS is not the VMXON region. */
8217 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8218 { /* likely */ }
8219 else
8220 {
8221 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8222 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8223 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8224 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8225 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8226 return VINF_SUCCESS;
8227 }
8228
8229 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8230 restriction imposed by our implementation. */
8231 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8232 { /* likely */ }
8233 else
8234 {
8235 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8236 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8237 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8238 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8239 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8240 return VINF_SUCCESS;
8241 }
8242
8243 /* Read just the VMCS revision from the VMCS. */
8244 VMXVMCSREVID VmcsRevId;
8245 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8246 if (RT_SUCCESS(rc))
8247 { /* likely */ }
8248 else
8249 {
8250 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8251 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8252 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8253 return rc;
8254 }
8255
8256 /*
8257 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8258 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8259 */
8260 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8261 && ( !VmcsRevId.n.fIsShadowVmcs
8262 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8263 { /* likely */ }
8264 else
8265 {
8266 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8267 {
8268 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8269 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8270 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8271 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8272 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8273 return VINF_SUCCESS;
8274 }
8275
8276 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8277 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8278 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8279 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8280 return VINF_SUCCESS;
8281 }
8282
8283 /*
8284 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8285 * the cache of an existing, current VMCS back to guest memory before loading a new,
8286 * different current VMCS.
8287 */
8288 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8289 {
8290 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8291 {
8292 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8293 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8294 }
8295
8296 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8297 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8298 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8299 if (RT_SUCCESS(rc))
8300 {
8301 /* Notify HM that a new, current VMCS is loaded. */
8302 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8303 }
8304 else
8305 {
8306 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8307 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8308 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8309 return rc;
8310 }
8311 }
8312
8313 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8314 iemVmxVmSucceed(pVCpu);
8315 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8316 return VINF_SUCCESS;
8317}
8318
8319
8320/**
8321 * INVVPID instruction execution worker.
8322 *
8323 * @returns Strict VBox status code.
8324 * @param pVCpu The cross context virtual CPU structure.
8325 * @param cbInstr The instruction length in bytes.
8326 * @param iEffSeg The segment of the invvpid descriptor.
8327 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8328 * @param u64InvvpidType The invalidation type.
8329 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8330 * NULL.
8331 *
8332 * @remarks Common VMX instruction checks are already expected to by the caller,
8333 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8334 */
8335IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8336 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8337{
8338 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8339 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8340 return iemRaiseUndefinedOpcode(pVCpu);
8341
8342 /* Nested-guest intercept. */
8343 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8344 {
8345 if (pExitInfo)
8346 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8347 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8348 }
8349
8350 /* CPL. */
8351 if (pVCpu->iem.s.uCpl != 0)
8352 {
8353 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8354 return iemRaiseGeneralProtectionFault0(pVCpu);
8355 }
8356
8357 /*
8358 * Validate INVVPID invalidation type.
8359 *
8360 * The instruction specifies exactly ONE of the supported invalidation types.
8361 *
8362 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8363 * supported. In theory, it's possible for a CPU to not support flushing individual
8364 * addresses but all the other types or any other combination. We do not take any
8365 * shortcuts here by assuming the types we currently expose to the guest.
8366 */
8367 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8368 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8369 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8370 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8371 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8372 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8373 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8374 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8375 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8376 { /* likely */ }
8377 else
8378 {
8379 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8380 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8381 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8382 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8383 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8384 return VINF_SUCCESS;
8385 }
8386
8387 /*
8388 * Fetch the invvpid descriptor from guest memory.
8389 */
8390 RTUINT128U uDesc;
8391 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8392 if (rcStrict == VINF_SUCCESS)
8393 {
8394 /*
8395 * Validate the descriptor.
8396 */
8397 if (uDesc.s.Lo > 0xfff)
8398 {
8399 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8400 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8401 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8402 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8403 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8404 return VINF_SUCCESS;
8405 }
8406
8407 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8408 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8409 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8410 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8411 switch (u64InvvpidType)
8412 {
8413 case VMXTLBFLUSHVPID_INDIV_ADDR:
8414 {
8415 if (uVpid != 0)
8416 {
8417 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8418 {
8419 /* Invalidate mappings for the linear address tagged with VPID. */
8420 /** @todo PGM support for VPID? Currently just flush everything. */
8421 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8422 iemVmxVmSucceed(pVCpu);
8423 }
8424 else
8425 {
8426 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8427 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8428 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8429 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8430 }
8431 }
8432 else
8433 {
8434 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8435 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8436 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8437 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8438 }
8439 break;
8440 }
8441
8442 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8443 {
8444 if (uVpid != 0)
8445 {
8446 /* Invalidate all mappings with VPID. */
8447 /** @todo PGM support for VPID? Currently just flush everything. */
8448 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8449 iemVmxVmSucceed(pVCpu);
8450 }
8451 else
8452 {
8453 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8454 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8455 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8456 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8457 }
8458 break;
8459 }
8460
8461 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8462 {
8463 /* Invalidate all mappings with non-zero VPIDs. */
8464 /** @todo PGM support for VPID? Currently just flush everything. */
8465 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8466 iemVmxVmSucceed(pVCpu);
8467 break;
8468 }
8469
8470 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8471 {
8472 if (uVpid != 0)
8473 {
8474 /* Invalidate all mappings with VPID except global translations. */
8475 /** @todo PGM support for VPID? Currently just flush everything. */
8476 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8477 iemVmxVmSucceed(pVCpu);
8478 }
8479 else
8480 {
8481 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8482 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8483 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8484 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8485 }
8486 break;
8487 }
8488 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8489 }
8490 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8491 }
8492 return rcStrict;
8493}
8494
8495
8496/**
8497 * VMXON instruction execution worker.
8498 *
8499 * @returns Strict VBox status code.
8500 * @param pVCpu The cross context virtual CPU structure.
8501 * @param cbInstr The instruction length in bytes.
8502 * @param iEffSeg The effective segment register to use with @a
8503 * GCPtrVmxon.
8504 * @param GCPtrVmxon The linear address of the VMXON pointer.
8505 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8506 *
8507 * @remarks Common VMX instruction checks are already expected to by the caller,
8508 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8509 */
8510IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8511 PCVMXVEXITINFO pExitInfo)
8512{
8513 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8514 {
8515 /* CPL. */
8516 if (pVCpu->iem.s.uCpl == 0)
8517 { /* likely */ }
8518 else
8519 {
8520 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8521 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8522 return iemRaiseGeneralProtectionFault0(pVCpu);
8523 }
8524
8525 /* A20M (A20 Masked) mode. */
8526 if (PGMPhysIsA20Enabled(pVCpu))
8527 { /* likely */ }
8528 else
8529 {
8530 Log(("vmxon: A20M mode -> #GP(0)\n"));
8531 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8532 return iemRaiseGeneralProtectionFault0(pVCpu);
8533 }
8534
8535 /* CR0. */
8536 {
8537 /* CR0 MB1 bits. */
8538 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8539 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8540 { /* likely */ }
8541 else
8542 {
8543 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8544 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8545 return iemRaiseGeneralProtectionFault0(pVCpu);
8546 }
8547
8548 /* CR0 MBZ bits. */
8549 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8550 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8551 { /* likely */ }
8552 else
8553 {
8554 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8555 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8556 return iemRaiseGeneralProtectionFault0(pVCpu);
8557 }
8558 }
8559
8560 /* CR4. */
8561 {
8562 /* CR4 MB1 bits. */
8563 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8564 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8565 { /* likely */ }
8566 else
8567 {
8568 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8569 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8570 return iemRaiseGeneralProtectionFault0(pVCpu);
8571 }
8572
8573 /* CR4 MBZ bits. */
8574 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8575 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8576 { /* likely */ }
8577 else
8578 {
8579 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8580 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8581 return iemRaiseGeneralProtectionFault0(pVCpu);
8582 }
8583 }
8584
8585 /* Feature control MSR's LOCK and VMXON bits. */
8586 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
8587 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8588 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8589 { /* likely */ }
8590 else
8591 {
8592 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8593 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8594 return iemRaiseGeneralProtectionFault0(pVCpu);
8595 }
8596
8597 /* Get the VMXON pointer from the location specified by the source memory operand. */
8598 RTGCPHYS GCPhysVmxon;
8599 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8600 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8601 { /* likely */ }
8602 else
8603 {
8604 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8605 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8606 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8607 return rcStrict;
8608 }
8609
8610 /* VMXON region pointer alignment. */
8611 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8612 { /* likely */ }
8613 else
8614 {
8615 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8616 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8617 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8618 iemVmxVmFailInvalid(pVCpu);
8619 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8620 return VINF_SUCCESS;
8621 }
8622
8623 /* VMXON physical-address width limits. */
8624 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8625 { /* likely */ }
8626 else
8627 {
8628 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8629 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8630 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8631 iemVmxVmFailInvalid(pVCpu);
8632 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8633 return VINF_SUCCESS;
8634 }
8635
8636 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8637 restriction imposed by our implementation. */
8638 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8639 { /* likely */ }
8640 else
8641 {
8642 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8643 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8644 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8645 iemVmxVmFailInvalid(pVCpu);
8646 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8647 return VINF_SUCCESS;
8648 }
8649
8650 /* Read the VMCS revision ID from the VMXON region. */
8651 VMXVMCSREVID VmcsRevId;
8652 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8653 if (RT_SUCCESS(rc))
8654 { /* likely */ }
8655 else
8656 {
8657 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8658 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8659 return rc;
8660 }
8661
8662 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8663 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8664 { /* likely */ }
8665 else
8666 {
8667 /* Revision ID mismatch. */
8668 if (!VmcsRevId.n.fIsShadowVmcs)
8669 {
8670 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8671 VmcsRevId.n.u31RevisionId));
8672 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8673 iemVmxVmFailInvalid(pVCpu);
8674 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8675 return VINF_SUCCESS;
8676 }
8677
8678 /* Shadow VMCS disallowed. */
8679 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8680 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8681 iemVmxVmFailInvalid(pVCpu);
8682 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8683 return VINF_SUCCESS;
8684 }
8685
8686 /*
8687 * Record that we're in VMX operation, block INIT, block and disable A20M.
8688 */
8689 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8690 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8691 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8692
8693 /* Clear address-range monitoring. */
8694 EMMonitorWaitClear(pVCpu);
8695 /** @todo NSTVMX: Intel PT. */
8696
8697 iemVmxVmSucceed(pVCpu);
8698 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8699 return VINF_SUCCESS;
8700 }
8701 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8702 {
8703 /* Nested-guest intercept. */
8704 if (pExitInfo)
8705 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8706 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8707 }
8708
8709 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8710
8711 /* CPL. */
8712 if (pVCpu->iem.s.uCpl > 0)
8713 {
8714 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8715 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8716 return iemRaiseGeneralProtectionFault0(pVCpu);
8717 }
8718
8719 /* VMXON when already in VMX root mode. */
8720 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8721 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8722 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8723 return VINF_SUCCESS;
8724}
8725
8726
8727/**
8728 * Implements 'VMXOFF'.
8729 *
8730 * @remarks Common VMX instruction checks are already expected to by the caller,
8731 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8732 */
8733IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8734{
8735 /* Nested-guest intercept. */
8736 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8737 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8738
8739 /* CPL. */
8740 if (pVCpu->iem.s.uCpl == 0)
8741 { /* likely */ }
8742 else
8743 {
8744 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8745 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8746 return iemRaiseGeneralProtectionFault0(pVCpu);
8747 }
8748
8749 /* Dual monitor treatment of SMIs and SMM. */
8750 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8751 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8752 { /* likely */ }
8753 else
8754 {
8755 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8756 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8757 return VINF_SUCCESS;
8758 }
8759
8760 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8761 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8762 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8763
8764 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8765 { /** @todo NSTVMX: Unblock SMI. */ }
8766
8767 EMMonitorWaitClear(pVCpu);
8768 /** @todo NSTVMX: Unblock and enable A20M. */
8769
8770 iemVmxVmSucceed(pVCpu);
8771 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8772 return VINF_SUCCESS;
8773}
8774
8775
8776/**
8777 * Implements 'VMXON'.
8778 */
8779IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8780{
8781 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8782}
8783
8784
8785/**
8786 * Implements 'VMLAUNCH'.
8787 */
8788IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8789{
8790 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8791}
8792
8793
8794/**
8795 * Implements 'VMRESUME'.
8796 */
8797IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8798{
8799 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8800}
8801
8802
8803/**
8804 * Implements 'VMPTRLD'.
8805 */
8806IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8807{
8808 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8809}
8810
8811
8812/**
8813 * Implements 'VMPTRST'.
8814 */
8815IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8816{
8817 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8818}
8819
8820
8821/**
8822 * Implements 'VMCLEAR'.
8823 */
8824IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8825{
8826 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8827}
8828
8829
8830/**
8831 * Implements 'VMWRITE' register.
8832 */
8833IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8834{
8835 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8836}
8837
8838
8839/**
8840 * Implements 'VMWRITE' memory.
8841 */
8842IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8843{
8844 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8845}
8846
8847
8848/**
8849 * Implements 'VMREAD' register (64-bit).
8850 */
8851IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8852{
8853 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8854}
8855
8856
8857/**
8858 * Implements 'VMREAD' register (32-bit).
8859 */
8860IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8861{
8862 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8863}
8864
8865
8866/**
8867 * Implements 'VMREAD' memory, 64-bit register.
8868 */
8869IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8870{
8871 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8872}
8873
8874
8875/**
8876 * Implements 'VMREAD' memory, 32-bit register.
8877 */
8878IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8879{
8880 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8881}
8882
8883
8884/**
8885 * Implements 'INVVPID'.
8886 */
8887IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8888{
8889 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8890}
8891
8892
8893/**
8894 * Implements VMX's implementation of PAUSE.
8895 */
8896IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8897{
8898 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8899 {
8900 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8901 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8902 return rcStrict;
8903 }
8904
8905 /*
8906 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8907 * a VM-exit, the instruction operates normally.
8908 */
8909 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8910 return VINF_SUCCESS;
8911}
8912
8913#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8914
8915
8916/**
8917 * Implements 'VMCALL'.
8918 */
8919IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8920{
8921#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8922 /* Nested-guest intercept. */
8923 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8924 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8925#endif
8926
8927 /* Join forces with vmmcall. */
8928 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8929}
8930
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