VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 92296

Last change on this file since 92296 was 91987, checked in by vboxsync, 3 years ago

VMM/IEM: Nested VMX: bugref:10092 Update VMLAUNCH/VMRESUME and VM-exit to update EPT pointer with PGM.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 91987 2021-10-22 03:22:15Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_EPT_VIOLATION
177 * VMX_EXIT_EPT_MISCONFIG
178 * VMX_EXIT_INVEPT
179 * VMX_EXIT_RDRAND
180 * VMX_EXIT_VMFUNC
181 * VMX_EXIT_ENCLS
182 * VMX_EXIT_RDSEED
183 * VMX_EXIT_PML_FULL
184 * VMX_EXIT_XSAVES
185 * VMX_EXIT_XRSTORS
186 */
187/**
188 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
189 *
190 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
191 * second dimension is the Index, see VMXVMCSFIELD.
192 */
193uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
194{
195 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
196 {
197 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
198 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
199 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
200 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
201 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 27 */ UINT16_MAX,
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 26-27 */ UINT16_MAX, UINT16_MAX
227 },
228 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
233 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
234 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
235 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
236 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
237 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
239 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
240 },
241 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
242 {
243 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
244 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
245 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
246 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
247 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
248 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
249 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
250 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
251 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
252 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
253 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
254 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
255 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
256 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
257 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
258 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
259 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
260 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
261 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
262 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
263 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
264 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
265 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
266 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
267 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
268 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
269 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
270 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
271 },
272 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
273 {
274 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
275 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
276 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
277 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
278 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
279 },
280 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
281 {
282 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
283 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
284 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
285 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
286 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
287 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
288 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
289 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
290 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
291 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
292 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
293 /* 11 */ UINT16_MAX,
294 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
295 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
296 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
297 },
298 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
299 {
300 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
301 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
302 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
303 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
304 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
307 },
308 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
309 {
310 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
311 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
312 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
313 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
314 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
315 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
316 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
317 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
318 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
319 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
320 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
321 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
322 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
323 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
324 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
325 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
326 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
327 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
328 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
329 /* 26-27 */ UINT16_MAX, UINT16_MAX
330 },
331 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
332 {
333 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
334 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
335 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
336 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
337 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
338 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
339 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
340 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
341 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
342 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
343 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
344 },
345 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
346 {
347 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
348 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
349 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
350 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
351 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
352 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
353 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
354 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
355 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
356 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
357 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
358 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
359 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
360 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
361 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
362 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
363 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
364 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
365 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
366 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
367 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
368 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
369 /* 22 */ UINT16_MAX,
370 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
371 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
376 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
377 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
378 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
379 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
380 },
381 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
382 {
383 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
384 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
385 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
386 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
387 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
388 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
389 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
390 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
391 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
392 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
393 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
394 },
395 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
396 {
397 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
398 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
399 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
400 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
401 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
402 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
403 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
404 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
405 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
406 },
407 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
408 {
409 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
410 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
411 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
412 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
413 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
414 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
415 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
416 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
417 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
418 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
419 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
420 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
421 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
422 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
423 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
424 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
425 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
426 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
427 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
428 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
429 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
430 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
431 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
432 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
433 },
434 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
435 {
436 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
437 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
438 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
439 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
440 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
441 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
442 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
443 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
444 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
445 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
446 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
447 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
448 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
449 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
450 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
451 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
452 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
453 }
454};
455
456
457/**
458 * Gets a host selector from the VMCS.
459 *
460 * @param pVmcs Pointer to the virtual VMCS.
461 * @param iSelReg The index of the segment register (X86_SREG_XXX).
462 */
463DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
464{
465 Assert(iSegReg < X86_SREG_COUNT);
466 RTSEL HostSel;
467 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
468 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
469 uint8_t const uWidthType = (uWidth << 2) | uType;
470 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
471 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
472 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
473 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
474 uint8_t const *pbField = pbVmcs + offField;
475 HostSel = *(uint16_t *)pbField;
476 return HostSel;
477}
478
479
480/**
481 * Sets a guest segment register in the VMCS.
482 *
483 * @param pVmcs Pointer to the virtual VMCS.
484 * @param iSegReg The index of the segment register (X86_SREG_XXX).
485 * @param pSelReg Pointer to the segment register.
486 */
487IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
488{
489 Assert(pSelReg);
490 Assert(iSegReg < X86_SREG_COUNT);
491
492 /* Selector. */
493 {
494 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
495 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
496 uint8_t const uWidthType = (uWidth << 2) | uType;
497 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
498 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
499 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
500 uint8_t *pbVmcs = (uint8_t *)pVmcs;
501 uint8_t *pbField = pbVmcs + offField;
502 *(uint16_t *)pbField = pSelReg->Sel;
503 }
504
505 /* Limit. */
506 {
507 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
508 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
509 uint8_t const uWidthType = (uWidth << 2) | uType;
510 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
511 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
512 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
513 uint8_t *pbVmcs = (uint8_t *)pVmcs;
514 uint8_t *pbField = pbVmcs + offField;
515 *(uint32_t *)pbField = pSelReg->u32Limit;
516 }
517
518 /* Base. */
519 {
520 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
521 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
522 uint8_t const uWidthType = (uWidth << 2) | uType;
523 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
524 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
525 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
526 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
527 uint8_t const *pbField = pbVmcs + offField;
528 *(uint64_t *)pbField = pSelReg->u64Base;
529 }
530
531 /* Attributes. */
532 {
533 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
534 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
535 | X86DESCATTR_UNUSABLE;
536 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
537 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
538 uint8_t const uWidthType = (uWidth << 2) | uType;
539 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
540 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
541 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
542 uint8_t *pbVmcs = (uint8_t *)pVmcs;
543 uint8_t *pbField = pbVmcs + offField;
544 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
545 }
546}
547
548
549/**
550 * Gets a guest segment register from the VMCS.
551 *
552 * @returns VBox status code.
553 * @param pVmcs Pointer to the virtual VMCS.
554 * @param iSegReg The index of the segment register (X86_SREG_XXX).
555 * @param pSelReg Where to store the segment register (only updated when
556 * VINF_SUCCESS is returned).
557 *
558 * @remarks Warning! This does not validate the contents of the retrieved segment
559 * register.
560 */
561IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
562{
563 Assert(pSelReg);
564 Assert(iSegReg < X86_SREG_COUNT);
565
566 /* Selector. */
567 uint16_t u16Sel;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u16Sel = *(uint16_t *)pbField;
578 }
579
580 /* Limit. */
581 uint32_t u32Limit;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u32Limit = *(uint32_t *)pbField;
592 }
593
594 /* Base. */
595 uint64_t u64Base;
596 {
597 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
598 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
599 uint8_t const uWidthType = (uWidth << 2) | uType;
600 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
601 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
602 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
603 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
604 uint8_t const *pbField = pbVmcs + offField;
605 u64Base = *(uint64_t *)pbField;
606 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
607 }
608
609 /* Attributes. */
610 uint32_t u32Attr;
611 {
612 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
613 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
614 uint8_t const uWidthType = (uWidth << 2) | uType;
615 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
616 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
617 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
618 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
619 uint8_t const *pbField = pbVmcs + offField;
620 u32Attr = *(uint32_t *)pbField;
621 }
622
623 pSelReg->Sel = u16Sel;
624 pSelReg->ValidSel = u16Sel;
625 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
626 pSelReg->u32Limit = u32Limit;
627 pSelReg->u64Base = u64Base;
628 pSelReg->Attr.u = u32Attr;
629 return VINF_SUCCESS;
630}
631
632
633/**
634 * Converts an IEM exception event type to a VMX event type.
635 *
636 * @returns The VMX event type.
637 * @param uVector The interrupt / exception vector.
638 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
639 */
640DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
641{
642 /* Paranoia (callers may use these interchangeably). */
643 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
644 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
645 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
646 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
647 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
648 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
649 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
650 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
651 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
652 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
653 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
654 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
655
656 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
657 {
658 if (uVector == X86_XCPT_NMI)
659 return VMX_EXIT_INT_INFO_TYPE_NMI;
660 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
661 }
662
663 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
664 {
665 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
666 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
667 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
668 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
669 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
670 }
671
672 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
673 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
674}
675
676
677/**
678 * Sets the Exit qualification VMCS field.
679 *
680 * @param pVCpu The cross context virtual CPU structure.
681 * @param u64ExitQual The Exit qualification.
682 */
683DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
684{
685 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
686}
687
688
689/**
690 * Sets the VM-exit interruption information field.
691 *
692 * @param pVCpu The cross context virtual CPU structure.
693 * @param uExitIntInfo The VM-exit interruption information.
694 */
695DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
696{
697 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
698}
699
700
701/**
702 * Sets the VM-exit interruption error code.
703 *
704 * @param pVCpu The cross context virtual CPU structure.
705 * @param uErrCode The error code.
706 */
707DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
708{
709 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
710}
711
712
713/**
714 * Sets the IDT-vectoring information field.
715 *
716 * @param pVCpu The cross context virtual CPU structure.
717 * @param uIdtVectorInfo The IDT-vectoring information.
718 */
719DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
720{
721 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
722}
723
724
725/**
726 * Sets the IDT-vectoring error code field.
727 *
728 * @param pVCpu The cross context virtual CPU structure.
729 * @param uErrCode The error code.
730 */
731DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
732{
733 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
734}
735
736
737/**
738 * Sets the VM-exit guest-linear address VMCS field.
739 *
740 * @param pVCpu The cross context virtual CPU structure.
741 * @param uGuestLinearAddr The VM-exit guest-linear address.
742 */
743DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
744{
745 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
746}
747
748
749/**
750 * Sets the VM-exit guest-physical address VMCS field.
751 *
752 * @param pVCpu The cross context virtual CPU structure.
753 * @param uGuestPhysAddr The VM-exit guest-physical address.
754 */
755DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
756{
757 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
758}
759
760
761/**
762 * Sets the VM-exit instruction length VMCS field.
763 *
764 * @param pVCpu The cross context virtual CPU structure.
765 * @param cbInstr The VM-exit instruction length in bytes.
766 *
767 * @remarks Callers may clear this field to 0. Hence, this function does not check
768 * the validity of the instruction length.
769 */
770DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
771{
772 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
773}
774
775
776/**
777 * Sets the VM-exit instruction info. VMCS field.
778 *
779 * @param pVCpu The cross context virtual CPU structure.
780 * @param uExitInstrInfo The VM-exit instruction information.
781 */
782DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
783{
784 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
785}
786
787
788/**
789 * Sets the guest pending-debug exceptions field.
790 *
791 * @param pVCpu The cross context virtual CPU structure.
792 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
793 */
794DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
795{
796 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
797 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
798}
799
800
801/**
802 * Implements VMSucceed for VMX instruction success.
803 *
804 * @param pVCpu The cross context virtual CPU structure.
805 */
806DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
807{
808 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
809}
810
811
812/**
813 * Implements VMFailInvalid for VMX instruction failure.
814 *
815 * @param pVCpu The cross context virtual CPU structure.
816 */
817DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
818{
819 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
820}
821
822
823/**
824 * Implements VMFail for VMX instruction failure.
825 *
826 * @param pVCpu The cross context virtual CPU structure.
827 * @param enmInsErr The VM instruction error.
828 */
829DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
830{
831 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
832}
833
834
835/**
836 * Checks if the given auto-load/store MSR area count is valid for the
837 * implementation.
838 *
839 * @returns @c true if it's within the valid limit, @c false otherwise.
840 * @param pVCpu The cross context virtual CPU structure.
841 * @param uMsrCount The MSR area count to check.
842 */
843DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
844{
845 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
846 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
847 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
848 if (uMsrCount <= cMaxSupportedMsrs)
849 return true;
850 return false;
851}
852
853
854/**
855 * Flushes the current VMCS contents back to guest memory.
856 *
857 * @returns VBox status code.
858 * @param pVCpu The cross context virtual CPU structure.
859 */
860DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
861{
862 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
863 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
864 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
865 return rc;
866}
867
868
869/**
870 * Populates the current VMCS contents from guest memory.
871 *
872 * @returns VBox status code.
873 * @param pVCpu The cross context virtual CPU structure.
874 */
875DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
876{
877 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
879 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
880 return rc;
881}
882
883
884/**
885 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
886 *
887 * @param pVCpu The cross context virtual CPU structure.
888 */
889DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
890{
891 iemVmxVmSucceed(pVCpu);
892 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
893}
894
895
896/**
897 * Gets the instruction diagnostic for segment base checks during VM-entry of a
898 * nested-guest.
899 *
900 * @param iSegReg The segment index (X86_SREG_XXX).
901 */
902IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
903{
904 switch (iSegReg)
905 {
906 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
907 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
908 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
909 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
910 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
911 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
912 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
913 }
914}
915
916
917/**
918 * Gets the instruction diagnostic for segment base checks during VM-entry of a
919 * nested-guest that is in Virtual-8086 mode.
920 *
921 * @param iSegReg The segment index (X86_SREG_XXX).
922 */
923IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
924{
925 switch (iSegReg)
926 {
927 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
928 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
929 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
930 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
931 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
932 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
933 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
934 }
935}
936
937
938/**
939 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
940 * nested-guest that is in Virtual-8086 mode.
941 *
942 * @param iSegReg The segment index (X86_SREG_XXX).
943 */
944IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
945{
946 switch (iSegReg)
947 {
948 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
949 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
950 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
951 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
952 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
953 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
954 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
955 }
956}
957
958
959/**
960 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
961 * nested-guest that is in Virtual-8086 mode.
962 *
963 * @param iSegReg The segment index (X86_SREG_XXX).
964 */
965IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
966{
967 switch (iSegReg)
968 {
969 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
970 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
971 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
972 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
973 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
974 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
975 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
976 }
977}
978
979
980/**
981 * Gets the instruction diagnostic for segment attributes reserved bits failure
982 * during VM-entry of a nested-guest.
983 *
984 * @param iSegReg The segment index (X86_SREG_XXX).
985 */
986IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
987{
988 switch (iSegReg)
989 {
990 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
991 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
992 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
993 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
994 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
995 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
996 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
997 }
998}
999
1000
1001/**
1002 * Gets the instruction diagnostic for segment attributes descriptor-type
1003 * (code/segment or system) failure during VM-entry of a nested-guest.
1004 *
1005 * @param iSegReg The segment index (X86_SREG_XXX).
1006 */
1007IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1008{
1009 switch (iSegReg)
1010 {
1011 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1012 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1013 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1014 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1015 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1016 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1017 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1018 }
1019}
1020
1021
1022/**
1023 * Gets the instruction diagnostic for segment attributes descriptor-type
1024 * (code/segment or system) failure during VM-entry of a nested-guest.
1025 *
1026 * @param iSegReg The segment index (X86_SREG_XXX).
1027 */
1028IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1029{
1030 switch (iSegReg)
1031 {
1032 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1033 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1034 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1035 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1036 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1037 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1038 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1039 }
1040}
1041
1042
1043/**
1044 * Gets the instruction diagnostic for segment attribute granularity failure during
1045 * VM-entry of a nested-guest.
1046 *
1047 * @param iSegReg The segment index (X86_SREG_XXX).
1048 */
1049IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1050{
1051 switch (iSegReg)
1052 {
1053 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1054 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1055 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1056 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1057 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1058 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1059 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1060 }
1061}
1062
1063/**
1064 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1065 * VM-entry of a nested-guest.
1066 *
1067 * @param iSegReg The segment index (X86_SREG_XXX).
1068 */
1069IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1070{
1071 switch (iSegReg)
1072 {
1073 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1074 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1075 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1076 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1077 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1078 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1079 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1080 }
1081}
1082
1083
1084/**
1085 * Gets the instruction diagnostic for segment attribute type accessed failure
1086 * during VM-entry of a nested-guest.
1087 *
1088 * @param iSegReg The segment index (X86_SREG_XXX).
1089 */
1090IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1091{
1092 switch (iSegReg)
1093 {
1094 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1095 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1096 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1097 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1098 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1099 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1100 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1101 }
1102}
1103
1104
1105/**
1106 * Saves the guest control registers, debug registers and some MSRs are part of
1107 * VM-exit.
1108 *
1109 * @param pVCpu The cross context virtual CPU structure.
1110 */
1111IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1112{
1113 /*
1114 * Saves the guest control registers, debug registers and some MSRs.
1115 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1116 */
1117 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1118
1119 /* Save control registers. */
1120 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1121 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1122 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1123
1124 /* Save SYSENTER CS, ESP, EIP. */
1125 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1126 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1127 {
1128 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1129 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1130 }
1131 else
1132 {
1133 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1134 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1135 }
1136
1137 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1138 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1139 {
1140 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1141 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1142 }
1143
1144 /* Save PAT MSR. */
1145 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1146 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1147
1148 /* Save EFER MSR. */
1149 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1150 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1151
1152 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1153 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1154
1155 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1156}
1157
1158
1159/**
1160 * Saves the guest force-flags in preparation of entering the nested-guest.
1161 *
1162 * @param pVCpu The cross context virtual CPU structure.
1163 */
1164IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1165{
1166 /* We shouldn't be called multiple times during VM-entry. */
1167 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1168
1169 /* MTF should not be set outside VMX non-root mode. */
1170 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1171
1172 /*
1173 * Preserve the required force-flags.
1174 *
1175 * We cache and clear force-flags that would affect the execution of the
1176 * nested-guest. Cached flags are then restored while returning to the guest
1177 * if necessary.
1178 *
1179 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1180 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1181 * instruction. Interrupt inhibition for any nested-guest instruction
1182 * is supplied by the guest-interruptibility state VMCS field and will
1183 * be set up as part of loading the guest state.
1184 *
1185 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1186 * successful VM-entry (due to invalid guest-state) need to continue
1187 * blocking NMIs if it was in effect before VM-entry.
1188 *
1189 * - MTF need not be preserved as it's used only in VMX non-root mode and
1190 * is supplied through the VM-execution controls.
1191 *
1192 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1193 * we will be able to generate interrupts that may cause VM-exits for
1194 * the nested-guest.
1195 */
1196 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1197}
1198
1199
1200/**
1201 * Restores the guest force-flags in preparation of exiting the nested-guest.
1202 *
1203 * @param pVCpu The cross context virtual CPU structure.
1204 */
1205IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1206{
1207 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1208 {
1209 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1210 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1211 }
1212}
1213
1214
1215/**
1216 * Performs the VMX transition to/from VMX non-root mode.
1217 *
1218 * @param pVCpu The cross context virtual CPU structure.
1219 * @param fPdpesMapped Whether the PAE PDPTEs (and PDPT) have been mapped.
1220*/
1221IEM_STATIC int iemVmxTransition(PVMCPUCC pVCpu, bool fPdpesMapped)
1222{
1223 /*
1224 * Inform PGM about paging mode changes.
1225 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1226 * see comment in iemMemPageTranslateAndCheckAccess().
1227 */
1228 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1229# ifdef IN_RING3
1230 Assert(rc != VINF_PGM_CHANGE_MODE);
1231# endif
1232 AssertRCReturn(rc, rc);
1233
1234 /* Inform CPUM (recompiler), can later be removed. */
1235 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1236
1237 /*
1238 * Flush the TLB with new CR3. This is required in case the PGM mode change
1239 * above doesn't actually change anything.
1240 */
1241 if (rc == VINF_SUCCESS)
1242 {
1243 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* fGlobal */, fPdpesMapped);
1244 AssertRCReturn(rc, rc);
1245 }
1246
1247 /* Re-initialize IEM cache/state after the drastic mode switch. */
1248 iemReInitExec(pVCpu);
1249 return rc;
1250}
1251
1252
1253/**
1254 * Calculates the current VMX-preemption timer value.
1255 *
1256 * @returns The current VMX-preemption timer value.
1257 * @param pVCpu The cross context virtual CPU structure.
1258 */
1259IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1260{
1261 /*
1262 * Assume the following:
1263 * PreemptTimerShift = 5
1264 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1265 * EntryTick = 50000 (TSC at time of VM-entry)
1266 *
1267 * CurTick Delta PreemptTimerVal
1268 * ----------------------------------
1269 * 60000 10000 2
1270 * 80000 30000 1
1271 * 90000 40000 0 -> VM-exit.
1272 *
1273 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1274 * The saved VMX-preemption timer value is calculated as follows:
1275 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1276 * E.g.:
1277 * Delta = 10000
1278 * Tmp = 10000 / (2 * 10000) = 0.5
1279 * NewPt = 2 - 0.5 = 2
1280 * Delta = 30000
1281 * Tmp = 30000 / (2 * 10000) = 1.5
1282 * NewPt = 2 - 1.5 = 1
1283 * Delta = 40000
1284 * Tmp = 40000 / 20000 = 2
1285 * NewPt = 2 - 2 = 0
1286 */
1287 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1288 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1289 if (uVmcsPreemptVal > 0)
1290 {
1291 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1292 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1293 uint64_t const uDelta = uCurTick - uEntryTick;
1294 uint32_t const uPreemptTimer = uVmcsPreemptVal
1295 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1296 return uPreemptTimer;
1297 }
1298 return 0;
1299}
1300
1301
1302/**
1303 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1304 *
1305 * @param pVCpu The cross context virtual CPU structure.
1306 */
1307IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1308{
1309 /*
1310 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1311 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1312 */
1313 /* CS, SS, ES, DS, FS, GS. */
1314 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1315 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1316 {
1317 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1318 if (!pSelReg->Attr.n.u1Unusable)
1319 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1320 else
1321 {
1322 /*
1323 * For unusable segments the attributes are undefined except for CS and SS.
1324 * For the rest we don't bother preserving anything but the unusable bit.
1325 */
1326 switch (iSegReg)
1327 {
1328 case X86_SREG_CS:
1329 pVmcs->GuestCs = pSelReg->Sel;
1330 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1331 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1332 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1333 | X86DESCATTR_UNUSABLE);
1334 break;
1335
1336 case X86_SREG_SS:
1337 pVmcs->GuestSs = pSelReg->Sel;
1338 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1339 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1340 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1341 break;
1342
1343 case X86_SREG_DS:
1344 pVmcs->GuestDs = pSelReg->Sel;
1345 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1346 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1347 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1348 break;
1349
1350 case X86_SREG_ES:
1351 pVmcs->GuestEs = pSelReg->Sel;
1352 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1353 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1354 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1355 break;
1356
1357 case X86_SREG_FS:
1358 pVmcs->GuestFs = pSelReg->Sel;
1359 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1360 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1361 break;
1362
1363 case X86_SREG_GS:
1364 pVmcs->GuestGs = pSelReg->Sel;
1365 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1366 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1367 break;
1368 }
1369 }
1370 }
1371
1372 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1373 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1374 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1375 | X86DESCATTR_UNUSABLE;
1376 /* LDTR. */
1377 {
1378 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1379 pVmcs->GuestLdtr = pSelReg->Sel;
1380 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1381 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1382 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1383 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1384 }
1385
1386 /* TR. */
1387 {
1388 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1389 pVmcs->GuestTr = pSelReg->Sel;
1390 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1391 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1392 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1393 }
1394
1395 /* GDTR. */
1396 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1397 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1398
1399 /* IDTR. */
1400 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1401 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1402}
1403
1404
1405/**
1406 * Saves guest non-register state as part of VM-exit.
1407 *
1408 * @param pVCpu The cross context virtual CPU structure.
1409 * @param uExitReason The VM-exit reason.
1410 */
1411IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1412{
1413 /*
1414 * Save guest non-register state.
1415 * See Intel spec. 27.3.4 "Saving Non-Register State".
1416 */
1417 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1418
1419 /*
1420 * Activity state.
1421 * Most VM-exits will occur in the active state. However, if the first instruction
1422 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1423 * the VM-exit will be from the HLT activity state.
1424 *
1425 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1426 */
1427 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1428 * not? */
1429 EMSTATE const enmActivityState = EMGetState(pVCpu);
1430 switch (enmActivityState)
1431 {
1432 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1433 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1434 }
1435
1436 /*
1437 * Interruptibility-state.
1438 */
1439 /* NMI. */
1440 pVmcs->u32GuestIntrState = 0;
1441 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1442 {
1443 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1444 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1445 }
1446 else
1447 {
1448 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1449 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1450 }
1451
1452 /* Blocking-by-STI. */
1453 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1454 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1455 {
1456 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1457 * currently. */
1458 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1459 }
1460 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1461
1462 /*
1463 * Pending debug exceptions.
1464 *
1465 * For VM-exits where it is not applicable, we can safely zero out the field.
1466 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1467 */
1468 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1469 && uExitReason != VMX_EXIT_SMI
1470 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1471 && !VMXIsVmexitTrapLike(uExitReason))
1472 {
1473 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1474 * block-by-MovSS is in effect. */
1475 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1476 }
1477
1478 /*
1479 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1480 *
1481 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1482 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1483 */
1484 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1485 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1486 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1487
1488 /*
1489 * PAE PDPTEs.
1490 *
1491 * If EPT is enabled and PAE paging was used at the time of the VM-exit,
1492 * the PDPTEs are saved from the VMCS. Otherwise they're undefined but
1493 * we zero them for consistency.
1494 */
1495 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1496 {
1497 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
1498 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1499 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
1500 {
1501 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1502 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1503 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1504 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1505 }
1506 else
1507 {
1508 pVmcs->u64GuestPdpte0.u = 0;
1509 pVmcs->u64GuestPdpte1.u = 0;
1510 pVmcs->u64GuestPdpte2.u = 0;
1511 pVmcs->u64GuestPdpte3.u = 0;
1512 }
1513
1514 /* Clear PGM's copy of the EPT pointer for added safety. */
1515 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1516 }
1517 else
1518 {
1519 pVmcs->u64GuestPdpte0.u = 0;
1520 pVmcs->u64GuestPdpte1.u = 0;
1521 pVmcs->u64GuestPdpte2.u = 0;
1522 pVmcs->u64GuestPdpte3.u = 0;
1523 }
1524}
1525
1526
1527/**
1528 * Saves the guest-state as part of VM-exit.
1529 *
1530 * @returns VBox status code.
1531 * @param pVCpu The cross context virtual CPU structure.
1532 * @param uExitReason The VM-exit reason.
1533 */
1534IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1535{
1536 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1537 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1538
1539 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1540 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1541 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1542
1543 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1544}
1545
1546
1547/**
1548 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1549 *
1550 * @returns VBox status code.
1551 * @param pVCpu The cross context virtual CPU structure.
1552 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1553 */
1554IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1555{
1556 /*
1557 * Save guest MSRs.
1558 * See Intel spec. 27.4 "Saving MSRs".
1559 */
1560 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1561 const char * const pszFailure = "VMX-abort";
1562
1563 /*
1564 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1565 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1566 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1567 */
1568 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1569 if (!cMsrs)
1570 return VINF_SUCCESS;
1571
1572 /*
1573 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1574 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1575 * implementation causes a VMX-abort followed by a triple-fault.
1576 */
1577 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1578 if (fIsMsrCountValid)
1579 { /* likely */ }
1580 else
1581 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1582
1583 /*
1584 * Optimization if the nested hypervisor is using the same guest-physical page for both
1585 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1586 */
1587 PVMXAUTOMSR pMsrArea;
1588 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1589 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1590 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1591 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1592 else
1593 {
1594 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1595 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1596 if (RT_SUCCESS(rc))
1597 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1598 else
1599 {
1600 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1601 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1602 }
1603 }
1604
1605 /*
1606 * Update VM-exit MSR store area.
1607 */
1608 PVMXAUTOMSR pMsr = pMsrArea;
1609 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1610 {
1611 if ( !pMsr->u32Reserved
1612 && pMsr->u32Msr != MSR_IA32_SMBASE
1613 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1614 {
1615 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1616 if (rcStrict == VINF_SUCCESS)
1617 continue;
1618
1619 /*
1620 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1621 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1622 * recording the MSR index in the auxiliary info. field and indicated further by our
1623 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1624 * if possible, or come up with a better, generic solution.
1625 */
1626 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1627 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1628 ? kVmxVDiag_Vmexit_MsrStoreRing3
1629 : kVmxVDiag_Vmexit_MsrStore;
1630 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1631 }
1632 else
1633 {
1634 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1635 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1636 }
1637 }
1638
1639 /*
1640 * Commit the VM-exit MSR store are to guest memory.
1641 */
1642 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1643 if (RT_SUCCESS(rc))
1644 return VINF_SUCCESS;
1645
1646 NOREF(uExitReason);
1647 NOREF(pszFailure);
1648
1649 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1650 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1651}
1652
1653
1654/**
1655 * Performs a VMX abort (due to an fatal error during VM-exit).
1656 *
1657 * @returns Strict VBox status code.
1658 * @param pVCpu The cross context virtual CPU structure.
1659 * @param enmAbort The VMX abort reason.
1660 */
1661IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1662{
1663 /*
1664 * Perform the VMX abort.
1665 * See Intel spec. 27.7 "VMX Aborts".
1666 */
1667 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1668
1669 /* We don't support SMX yet. */
1670 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1671 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1672 {
1673 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1674 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1675 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1676 }
1677
1678 return VINF_EM_TRIPLE_FAULT;
1679}
1680
1681
1682/**
1683 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1684 *
1685 * @param pVCpu The cross context virtual CPU structure.
1686 */
1687IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1688{
1689 /*
1690 * Load host control registers, debug registers and MSRs.
1691 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1692 */
1693 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1694 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1695
1696 /* CR0. */
1697 {
1698 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1699 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1700 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1701 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1702 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1703 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1704 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1705
1706 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1707 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1708 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1709 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1710 }
1711
1712 /* CR4. */
1713 {
1714 /* CR4 fixed bits are not modified. */
1715 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1716 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1717 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1718 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1719 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1720 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1721 if (fHostInLongMode)
1722 uValidHostCr4 |= X86_CR4_PAE;
1723 else
1724 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1725
1726 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1727 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1728 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1729 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1730 }
1731
1732 /* CR3 (host value validated while checking host-state during VM-entry). */
1733 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1734
1735 /* DR7. */
1736 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1737
1738 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1739
1740 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1741 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1742 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1743 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1744
1745 /* FS, GS bases are loaded later while we load host segment registers. */
1746
1747 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1748 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1749 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1750 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1751 {
1752 if (fHostInLongMode)
1753 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1754 else
1755 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1756 }
1757
1758 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1759
1760 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1761 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1762 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1763
1764 /* We don't support IA32_BNDCFGS MSR yet. */
1765}
1766
1767
1768/**
1769 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1770 *
1771 * @param pVCpu The cross context virtual CPU structure.
1772 */
1773IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1774{
1775 /*
1776 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1777 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1778 *
1779 * Warning! Be careful to not touch fields that are reserved by VT-x,
1780 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1781 */
1782 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1783 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1784
1785 /* CS, SS, ES, DS, FS, GS. */
1786 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1787 {
1788 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1789 bool const fUnusable = RT_BOOL(HostSel == 0);
1790 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1791
1792 /* Selector. */
1793 pSelReg->Sel = HostSel;
1794 pSelReg->ValidSel = HostSel;
1795 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1796
1797 /* Limit. */
1798 pSelReg->u32Limit = 0xffffffff;
1799
1800 /* Base. */
1801 pSelReg->u64Base = 0;
1802
1803 /* Attributes. */
1804 if (iSegReg == X86_SREG_CS)
1805 {
1806 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1807 pSelReg->Attr.n.u1DescType = 1;
1808 pSelReg->Attr.n.u2Dpl = 0;
1809 pSelReg->Attr.n.u1Present = 1;
1810 pSelReg->Attr.n.u1Long = fHostInLongMode;
1811 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1812 pSelReg->Attr.n.u1Granularity = 1;
1813 Assert(!pSelReg->Attr.n.u1Unusable);
1814 Assert(!fUnusable);
1815 }
1816 else
1817 {
1818 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1819 pSelReg->Attr.n.u1DescType = 1;
1820 pSelReg->Attr.n.u2Dpl = 0;
1821 pSelReg->Attr.n.u1Present = 1;
1822 pSelReg->Attr.n.u1DefBig = 1;
1823 pSelReg->Attr.n.u1Granularity = 1;
1824 pSelReg->Attr.n.u1Unusable = fUnusable;
1825 }
1826 }
1827
1828 /* FS base. */
1829 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1830 || fHostInLongMode)
1831 {
1832 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1833 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1834 }
1835
1836 /* GS base. */
1837 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1838 || fHostInLongMode)
1839 {
1840 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1841 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1842 }
1843
1844 /* TR. */
1845 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1846 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1847 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1848 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1849 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1850 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1851 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1852 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1853 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1854 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1855 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1856 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1857 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1858
1859 /* LDTR (Warning! do not touch the base and limits here). */
1860 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1861 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1862 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1863 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1864
1865 /* GDTR. */
1866 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1867 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1868 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1869
1870 /* IDTR.*/
1871 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1872 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1873 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1874}
1875
1876
1877/**
1878 * Checks the host PAE PDPTEs assuming we are switching to a PAE mode host.
1879 *
1880 * @param pVCpu The cross context virtual CPU structure.
1881 * @param uExitReason The VMX instruction name (for logging purposes).
1882 *
1883 * @remarks Caller must ensure the preconditions are met before calling this
1884 * function as failure here will trigger VMX aborts!
1885 */
1886IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPUCC pVCpu, uint32_t uExitReason)
1887{
1888 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1889 const char * const pszFailure = "VMX-abort";
1890 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
1891 if (RT_SUCCESS(rc))
1892 return rc;
1893 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpte);
1894}
1895
1896
1897/**
1898 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1899 *
1900 * @returns VBox status code.
1901 * @param pVCpu The cross context virtual CPU structure.
1902 * @param uExitReason The VMX instruction name (for logging purposes).
1903 */
1904IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1905{
1906 /*
1907 * Load host MSRs.
1908 * See Intel spec. 27.6 "Loading MSRs".
1909 */
1910 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1911 const char * const pszFailure = "VMX-abort";
1912
1913 /*
1914 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1915 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1916 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1917 */
1918 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1919 if (!cMsrs)
1920 return VINF_SUCCESS;
1921
1922 /*
1923 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1924 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1925 * implementation causes a VMX-abort followed by a triple-fault.
1926 */
1927 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1928 if (fIsMsrCountValid)
1929 { /* likely */ }
1930 else
1931 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1932
1933 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1934 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1935 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1936 if (RT_SUCCESS(rc))
1937 {
1938 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1939 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1940 {
1941 if ( !pMsr->u32Reserved
1942 && pMsr->u32Msr != MSR_K8_FS_BASE
1943 && pMsr->u32Msr != MSR_K8_GS_BASE
1944 && pMsr->u32Msr != MSR_K6_EFER
1945 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1946 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1947 {
1948 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1949 if (rcStrict == VINF_SUCCESS)
1950 continue;
1951
1952 /*
1953 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1954 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1955 * recording the MSR index in the auxiliary info. field and indicated further by our
1956 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1957 * if possible, or come up with a better, generic solution.
1958 */
1959 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1960 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1961 ? kVmxVDiag_Vmexit_MsrLoadRing3
1962 : kVmxVDiag_Vmexit_MsrLoad;
1963 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1964 }
1965 else
1966 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1967 }
1968 }
1969 else
1970 {
1971 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1972 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1973 }
1974
1975 NOREF(uExitReason);
1976 NOREF(pszFailure);
1977 return VINF_SUCCESS;
1978}
1979
1980
1981/**
1982 * Loads the host state as part of VM-exit.
1983 *
1984 * @returns Strict VBox status code.
1985 * @param pVCpu The cross context virtual CPU structure.
1986 * @param uExitReason The VM-exit reason (for logging purposes).
1987 */
1988IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
1989{
1990 /*
1991 * Load host state.
1992 * See Intel spec. 27.5 "Loading Host State".
1993 */
1994 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1995 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1996
1997 /* We cannot return from a long-mode guest to a host that is not in long mode. */
1998 if ( CPUMIsGuestInLongMode(pVCpu)
1999 && !fHostInLongMode)
2000 {
2001 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2002 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2003 }
2004
2005 /*
2006 * Check host PAE PDPTEs prior to loading the host state.
2007 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2008 */
2009 bool fPdpesMapped;
2010 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2011 && !fHostInLongMode
2012 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2013 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2014 {
2015 int const rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2016 if (RT_FAILURE(rc))
2017 {
2018 Log(("VM-exit attempting to load invalid PDPTEs -> VMX-Abort\n"));
2019 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2020 }
2021 fPdpesMapped = true;
2022 }
2023 else
2024 fPdpesMapped = false;
2025
2026 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2027 iemVmxVmexitLoadHostSegRegs(pVCpu);
2028
2029 /*
2030 * Load host RIP, RSP and RFLAGS.
2031 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2032 */
2033 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2034 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2035 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2036
2037 /* Clear address range monitoring. */
2038 EMMonitorWaitClear(pVCpu);
2039
2040 /* Perform the VMX transition (PGM updates). */
2041 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu, fPdpesMapped);
2042 if (rcStrict == VINF_SUCCESS)
2043 { /* likely */ }
2044 else if (RT_SUCCESS(rcStrict))
2045 {
2046 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2047 uExitReason));
2048 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2049 }
2050 else
2051 {
2052 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2053 return VBOXSTRICTRC_VAL(rcStrict);
2054 }
2055
2056 Assert(rcStrict == VINF_SUCCESS);
2057
2058 /* Load MSRs from the VM-exit auto-load MSR area. */
2059 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2060 if (RT_FAILURE(rc))
2061 {
2062 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2063 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2064 }
2065 return VINF_SUCCESS;
2066}
2067
2068
2069/**
2070 * Gets VM-exit instruction information along with any displacement for an
2071 * instruction VM-exit.
2072 *
2073 * @returns The VM-exit instruction information.
2074 * @param pVCpu The cross context virtual CPU structure.
2075 * @param uExitReason The VM-exit reason.
2076 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2077 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2078 * NULL.
2079 */
2080IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2081{
2082 RTGCPTR GCPtrDisp;
2083 VMXEXITINSTRINFO ExitInstrInfo;
2084 ExitInstrInfo.u = 0;
2085
2086 /*
2087 * Get and parse the ModR/M byte from our decoded opcodes.
2088 */
2089 uint8_t bRm;
2090 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2091 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2092 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2093 {
2094 /*
2095 * ModR/M indicates register addressing.
2096 *
2097 * The primary/secondary register operands are reported in the iReg1 or iReg2
2098 * fields depending on whether it is a read/write form.
2099 */
2100 uint8_t idxReg1;
2101 uint8_t idxReg2;
2102 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2103 {
2104 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2105 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2106 }
2107 else
2108 {
2109 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2110 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2111 }
2112 ExitInstrInfo.All.u2Scaling = 0;
2113 ExitInstrInfo.All.iReg1 = idxReg1;
2114 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2115 ExitInstrInfo.All.fIsRegOperand = 1;
2116 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2117 ExitInstrInfo.All.iSegReg = 0;
2118 ExitInstrInfo.All.iIdxReg = 0;
2119 ExitInstrInfo.All.fIdxRegInvalid = 1;
2120 ExitInstrInfo.All.iBaseReg = 0;
2121 ExitInstrInfo.All.fBaseRegInvalid = 1;
2122 ExitInstrInfo.All.iReg2 = idxReg2;
2123
2124 /* Displacement not applicable for register addressing. */
2125 GCPtrDisp = 0;
2126 }
2127 else
2128 {
2129 /*
2130 * ModR/M indicates memory addressing.
2131 */
2132 uint8_t uScale = 0;
2133 bool fBaseRegValid = false;
2134 bool fIdxRegValid = false;
2135 uint8_t iBaseReg = 0;
2136 uint8_t iIdxReg = 0;
2137 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2138 {
2139 /*
2140 * Parse the ModR/M, displacement for 16-bit addressing mode.
2141 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2142 */
2143 uint16_t u16Disp = 0;
2144 uint8_t const offDisp = offModRm + sizeof(bRm);
2145 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2146 {
2147 /* Displacement without any registers. */
2148 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2149 }
2150 else
2151 {
2152 /* Register (index and base). */
2153 switch (bRm & X86_MODRM_RM_MASK)
2154 {
2155 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2156 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2157 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2158 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2159 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2160 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2161 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2162 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2163 }
2164
2165 /* Register + displacement. */
2166 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2167 {
2168 case 0: break;
2169 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2170 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2171 default:
2172 {
2173 /* Register addressing, handled at the beginning. */
2174 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2175 break;
2176 }
2177 }
2178 }
2179
2180 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2181 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2182 }
2183 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2184 {
2185 /*
2186 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2187 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2188 */
2189 uint32_t u32Disp = 0;
2190 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2191 {
2192 /* Displacement without any registers. */
2193 uint8_t const offDisp = offModRm + sizeof(bRm);
2194 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2195 }
2196 else
2197 {
2198 /* Register (and perhaps scale, index and base). */
2199 uint8_t offDisp = offModRm + sizeof(bRm);
2200 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2201 if (iBaseReg == 4)
2202 {
2203 /* An SIB byte follows the ModR/M byte, parse it. */
2204 uint8_t bSib;
2205 uint8_t const offSib = offModRm + sizeof(bRm);
2206 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2207
2208 /* A displacement may follow SIB, update its offset. */
2209 offDisp += sizeof(bSib);
2210
2211 /* Get the scale. */
2212 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2213
2214 /* Get the index register. */
2215 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2216 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2217
2218 /* Get the base register. */
2219 iBaseReg = bSib & X86_SIB_BASE_MASK;
2220 fBaseRegValid = true;
2221 if (iBaseReg == 5)
2222 {
2223 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2224 {
2225 /* Mod is 0 implies a 32-bit displacement with no base. */
2226 fBaseRegValid = false;
2227 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2228 }
2229 else
2230 {
2231 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2232 iBaseReg = X86_GREG_xBP;
2233 }
2234 }
2235 }
2236
2237 /* Register + displacement. */
2238 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2239 {
2240 case 0: /* Handled above */ break;
2241 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2242 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2243 default:
2244 {
2245 /* Register addressing, handled at the beginning. */
2246 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2247 break;
2248 }
2249 }
2250 }
2251
2252 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2253 }
2254 else
2255 {
2256 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2257
2258 /*
2259 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2260 * See Intel instruction spec. 2.2 "IA-32e Mode".
2261 */
2262 uint64_t u64Disp = 0;
2263 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2264 if (fRipRelativeAddr)
2265 {
2266 /*
2267 * RIP-relative addressing mode.
2268 *
2269 * The displacement is 32-bit signed implying an offset range of +/-2G.
2270 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2271 */
2272 uint8_t const offDisp = offModRm + sizeof(bRm);
2273 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2274 }
2275 else
2276 {
2277 uint8_t offDisp = offModRm + sizeof(bRm);
2278
2279 /*
2280 * Register (and perhaps scale, index and base).
2281 *
2282 * REX.B extends the most-significant bit of the base register. However, REX.B
2283 * is ignored while determining whether an SIB follows the opcode. Hence, we
2284 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2285 *
2286 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2287 */
2288 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2289 if (iBaseReg == 4)
2290 {
2291 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2292 uint8_t bSib;
2293 uint8_t const offSib = offModRm + sizeof(bRm);
2294 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2295
2296 /* Displacement may follow SIB, update its offset. */
2297 offDisp += sizeof(bSib);
2298
2299 /* Get the scale. */
2300 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2301
2302 /* Get the index. */
2303 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2304 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2305
2306 /* Get the base. */
2307 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2308 fBaseRegValid = true;
2309 if (iBaseReg == 5)
2310 {
2311 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2312 {
2313 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2314 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2315 }
2316 else
2317 {
2318 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2319 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2320 }
2321 }
2322 }
2323 iBaseReg |= pVCpu->iem.s.uRexB;
2324
2325 /* Register + displacement. */
2326 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2327 {
2328 case 0: /* Handled above */ break;
2329 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2330 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2331 default:
2332 {
2333 /* Register addressing, handled at the beginning. */
2334 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2335 break;
2336 }
2337 }
2338 }
2339
2340 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2341 }
2342
2343 /*
2344 * The primary or secondary register operand is reported in iReg2 depending
2345 * on whether the primary operand is in read/write form.
2346 */
2347 uint8_t idxReg2;
2348 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2349 {
2350 idxReg2 = bRm & X86_MODRM_RM_MASK;
2351 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2352 idxReg2 |= pVCpu->iem.s.uRexB;
2353 }
2354 else
2355 {
2356 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2357 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2358 idxReg2 |= pVCpu->iem.s.uRexReg;
2359 }
2360 ExitInstrInfo.All.u2Scaling = uScale;
2361 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2362 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2363 ExitInstrInfo.All.fIsRegOperand = 0;
2364 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2365 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2366 ExitInstrInfo.All.iIdxReg = iIdxReg;
2367 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2368 ExitInstrInfo.All.iBaseReg = iBaseReg;
2369 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2370 ExitInstrInfo.All.iReg2 = idxReg2;
2371 }
2372
2373 /*
2374 * Handle exceptions to the norm for certain instructions.
2375 * (e.g. some instructions convey an instruction identity in place of iReg2).
2376 */
2377 switch (uExitReason)
2378 {
2379 case VMX_EXIT_GDTR_IDTR_ACCESS:
2380 {
2381 Assert(VMXINSTRID_IS_VALID(uInstrId));
2382 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2383 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2384 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2385 break;
2386 }
2387
2388 case VMX_EXIT_LDTR_TR_ACCESS:
2389 {
2390 Assert(VMXINSTRID_IS_VALID(uInstrId));
2391 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2392 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2393 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2394 break;
2395 }
2396
2397 case VMX_EXIT_RDRAND:
2398 case VMX_EXIT_RDSEED:
2399 {
2400 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2401 break;
2402 }
2403 }
2404
2405 /* Update displacement and return the constructed VM-exit instruction information field. */
2406 if (pGCPtrDisp)
2407 *pGCPtrDisp = GCPtrDisp;
2408
2409 return ExitInstrInfo.u;
2410}
2411
2412
2413/**
2414 * VMX VM-exit handler.
2415 *
2416 * @returns Strict VBox status code.
2417 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2418 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2419 * triple-fault.
2420 *
2421 * @param pVCpu The cross context virtual CPU structure.
2422 * @param uExitReason The VM-exit reason.
2423 * @param u64ExitQual The Exit qualification.
2424 */
2425IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2426{
2427# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2428 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2429 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2430 return VERR_IEM_IPE_7;
2431# else
2432 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2433
2434 /*
2435 * Import all the guest-CPU state.
2436 *
2437 * HM on returning to guest execution would have to reset up a whole lot of state
2438 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2439 * the state and flag reloading the entire state on re-entry. So import the entire
2440 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2441 */
2442 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2443
2444 /*
2445 * Ensure VM-entry interruption information valid bit is cleared.
2446 *
2447 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2448 * by invalid-guest state or machine-check exceptions) also clear this bit.
2449 *
2450 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2451 */
2452 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2453 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2454
2455 /*
2456 * Update the VM-exit reason and Exit qualification.
2457 * Other VMCS read-only data fields are expected to be updated by the caller already.
2458 */
2459 pVmcs->u32RoExitReason = uExitReason;
2460 pVmcs->u64RoExitQual.u = u64ExitQual;
2461
2462 Log3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2463 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2464 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2465
2466 /*
2467 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2468 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2469 */
2470 {
2471 uint8_t uVector;
2472 uint32_t fFlags;
2473 uint32_t uErrCode;
2474 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2475 if (fInEventDelivery)
2476 {
2477 /*
2478 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2479 * caused by a triple-fault or the original event results in a double-fault that
2480 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2481 * original event information into the IDT-vectoring information fields.
2482 *
2483 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2484 */
2485 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2486 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2487 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2488 {
2489 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2490 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2491 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2492 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2493 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2494 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2495 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2496 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2497 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2498 pVCpu->cpum.GstCtx.cr2));
2499 }
2500 }
2501 }
2502
2503 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2504 Assert(pVmcs->u64RoIoRcx.u == 0);
2505 Assert(pVmcs->u64RoIoRsi.u == 0);
2506 Assert(pVmcs->u64RoIoRdi.u == 0);
2507 Assert(pVmcs->u64RoIoRip.u == 0);
2508
2509 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2510 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2511 {
2512 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2513 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2514 }
2515
2516 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2517 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2518
2519 /*
2520 * Save the guest state back into the VMCS.
2521 * We only need to save the state when the VM-entry was successful.
2522 */
2523 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2524 if (!fVmentryFailed)
2525 {
2526 /*
2527 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2528 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2529 *
2530 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2531 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2532 * as guest-CPU state would not been modified. Hence for now, we do this only when
2533 * the VM-entry succeeded.
2534 */
2535 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2536 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2537 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2538 {
2539 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2540 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2541 else
2542 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2543 }
2544
2545 /*
2546 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2547 * occurs in enclave mode/SMM which we don't support yet.
2548 *
2549 * If we ever add support for it, we can pass just the lower bits to the functions
2550 * below, till then an assert should suffice.
2551 */
2552 Assert(!RT_HI_U16(uExitReason));
2553
2554 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2555 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2556 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2557 if (RT_SUCCESS(rc))
2558 { /* likely */ }
2559 else
2560 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2561
2562 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2563 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2564 }
2565 else
2566 {
2567 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2568 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2569 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2570 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2571 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2572 }
2573
2574 /*
2575 * Stop any running VMX-preemption timer if necessary.
2576 */
2577 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2578 CPUMStopGuestVmxPremptTimer(pVCpu);
2579
2580 /*
2581 * Clear any pending VMX nested-guest force-flags.
2582 * These force-flags have no effect on (outer) guest execution and will
2583 * be re-evaluated and setup on the next nested-guest VM-entry.
2584 */
2585 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2586
2587 /* Restore the host (outer guest) state. */
2588 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2589 if (RT_SUCCESS(rcStrict))
2590 {
2591 Assert(rcStrict == VINF_SUCCESS);
2592 rcStrict = VINF_VMX_VMEXIT;
2593 }
2594 else
2595 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2596
2597 /* We're no longer in nested-guest execution mode. */
2598 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2599
2600 /* Notify HM that the current VMCS fields have been modified. */
2601 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2602
2603 /* Notify HM that we've completed the VM-exit. */
2604 HMNotifyVmxNstGstVmexit(pVCpu);
2605
2606# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2607 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2608 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2609 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2610 if (rcSched != VINF_SUCCESS)
2611 iemSetPassUpStatus(pVCpu, rcSched);
2612# endif
2613 return rcStrict;
2614# endif
2615}
2616
2617
2618/**
2619 * VMX VM-exit handler for VM-exits due to instruction execution.
2620 *
2621 * This is intended for instructions where the caller provides all the relevant
2622 * VM-exit information.
2623 *
2624 * @returns Strict VBox status code.
2625 * @param pVCpu The cross context virtual CPU structure.
2626 * @param pExitInfo Pointer to the VM-exit information.
2627 */
2628IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2629{
2630 /*
2631 * For instructions where any of the following fields are not applicable:
2632 * - Exit qualification must be cleared.
2633 * - VM-exit instruction info. is undefined.
2634 * - Guest-linear address is undefined.
2635 * - Guest-physical address is undefined.
2636 *
2637 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2638 * instruction execution. For VM-exits that are not due to instruction execution this
2639 * field is undefined.
2640 *
2641 * In our implementation in IEM, all undefined fields are generally cleared. However,
2642 * if the caller supplies information (from say the physical CPU directly) it is
2643 * then possible that the undefined fields are not cleared.
2644 *
2645 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2646 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2647 */
2648 Assert(pExitInfo);
2649 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2650 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2651 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2652
2653 /* Update all the relevant fields from the VM-exit instruction information struct. */
2654 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2655 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2656 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2657 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2658
2659 /* Perform the VM-exit. */
2660 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2661}
2662
2663
2664/**
2665 * VMX VM-exit handler for VM-exits due to instruction execution.
2666 *
2667 * This is intended for instructions that only provide the VM-exit instruction
2668 * length.
2669 *
2670 * @param pVCpu The cross context virtual CPU structure.
2671 * @param uExitReason The VM-exit reason.
2672 * @param cbInstr The instruction length in bytes.
2673 */
2674IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2675{
2676 VMXVEXITINFO ExitInfo;
2677 RT_ZERO(ExitInfo);
2678 ExitInfo.uReason = uExitReason;
2679 ExitInfo.cbInstr = cbInstr;
2680
2681#ifdef VBOX_STRICT
2682 /*
2683 * To prevent us from shooting ourselves in the foot.
2684 * The follow instructions should convey more than just the instruction length.
2685 */
2686 switch (uExitReason)
2687 {
2688 case VMX_EXIT_INVEPT:
2689 case VMX_EXIT_INVPCID:
2690 case VMX_EXIT_INVVPID:
2691 case VMX_EXIT_LDTR_TR_ACCESS:
2692 case VMX_EXIT_GDTR_IDTR_ACCESS:
2693 case VMX_EXIT_VMCLEAR:
2694 case VMX_EXIT_VMPTRLD:
2695 case VMX_EXIT_VMPTRST:
2696 case VMX_EXIT_VMREAD:
2697 case VMX_EXIT_VMWRITE:
2698 case VMX_EXIT_VMXON:
2699 case VMX_EXIT_XRSTORS:
2700 case VMX_EXIT_XSAVES:
2701 case VMX_EXIT_RDRAND:
2702 case VMX_EXIT_RDSEED:
2703 case VMX_EXIT_IO_INSTR:
2704 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2705 break;
2706 }
2707#endif
2708
2709 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2710}
2711
2712
2713/**
2714 * VMX VM-exit handler for VM-exits due to instruction execution.
2715 *
2716 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2717 * instruction information and Exit qualification fields.
2718 *
2719 * @param pVCpu The cross context virtual CPU structure.
2720 * @param uExitReason The VM-exit reason.
2721 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2722 * @param cbInstr The instruction length in bytes.
2723 *
2724 * @remarks Do not use this for INS/OUTS instruction.
2725 */
2726IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2727{
2728 VMXVEXITINFO ExitInfo;
2729 RT_ZERO(ExitInfo);
2730 ExitInfo.uReason = uExitReason;
2731 ExitInfo.cbInstr = cbInstr;
2732
2733 /*
2734 * Update the Exit qualification field with displacement bytes.
2735 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2736 */
2737 switch (uExitReason)
2738 {
2739 case VMX_EXIT_INVEPT:
2740 case VMX_EXIT_INVPCID:
2741 case VMX_EXIT_INVVPID:
2742 case VMX_EXIT_LDTR_TR_ACCESS:
2743 case VMX_EXIT_GDTR_IDTR_ACCESS:
2744 case VMX_EXIT_VMCLEAR:
2745 case VMX_EXIT_VMPTRLD:
2746 case VMX_EXIT_VMPTRST:
2747 case VMX_EXIT_VMREAD:
2748 case VMX_EXIT_VMWRITE:
2749 case VMX_EXIT_VMXON:
2750 case VMX_EXIT_XRSTORS:
2751 case VMX_EXIT_XSAVES:
2752 case VMX_EXIT_RDRAND:
2753 case VMX_EXIT_RDSEED:
2754 {
2755 /* Construct the VM-exit instruction information. */
2756 RTGCPTR GCPtrDisp;
2757 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2758
2759 /* Update the VM-exit instruction information. */
2760 ExitInfo.InstrInfo.u = uInstrInfo;
2761
2762 /* Update the Exit qualification. */
2763 ExitInfo.u64Qual = GCPtrDisp;
2764 break;
2765 }
2766
2767 default:
2768 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2769 break;
2770 }
2771
2772 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2773}
2774
2775
2776/**
2777 * VMX VM-exit handler for VM-exits due to INVLPG.
2778 *
2779 * @returns Strict VBox status code.
2780 * @param pVCpu The cross context virtual CPU structure.
2781 * @param GCPtrPage The guest-linear address of the page being invalidated.
2782 * @param cbInstr The instruction length in bytes.
2783 */
2784IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2785{
2786 VMXVEXITINFO ExitInfo;
2787 RT_ZERO(ExitInfo);
2788 ExitInfo.uReason = VMX_EXIT_INVLPG;
2789 ExitInfo.cbInstr = cbInstr;
2790 ExitInfo.u64Qual = GCPtrPage;
2791 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2792
2793 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2794}
2795
2796
2797/**
2798 * VMX VM-exit handler for VM-exits due to LMSW.
2799 *
2800 * @returns Strict VBox status code.
2801 * @param pVCpu The cross context virtual CPU structure.
2802 * @param uGuestCr0 The current guest CR0.
2803 * @param pu16NewMsw The machine-status word specified in LMSW's source
2804 * operand. This will be updated depending on the VMX
2805 * guest/host CR0 mask if LMSW is not intercepted.
2806 * @param GCPtrEffDst The guest-linear address of the source operand in case
2807 * of a memory operand. For register operand, pass
2808 * NIL_RTGCPTR.
2809 * @param cbInstr The instruction length in bytes.
2810 */
2811IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2812 uint8_t cbInstr)
2813{
2814 Assert(pu16NewMsw);
2815
2816 uint16_t const uNewMsw = *pu16NewMsw;
2817 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2818 {
2819 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2820
2821 VMXVEXITINFO ExitInfo;
2822 RT_ZERO(ExitInfo);
2823 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2824 ExitInfo.cbInstr = cbInstr;
2825
2826 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2827 if (fMemOperand)
2828 {
2829 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2830 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2831 }
2832
2833 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2834 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2835 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2836 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2837
2838 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2839 }
2840
2841 /*
2842 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2843 * CR0 guest/host mask must be left unmodified.
2844 *
2845 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2846 */
2847 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2848 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2849 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2850
2851 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2852}
2853
2854
2855/**
2856 * VMX VM-exit handler for VM-exits due to CLTS.
2857 *
2858 * @returns Strict VBox status code.
2859 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2860 * VM-exit but must not modify the guest CR0.TS bit.
2861 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2862 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2863 * CR0 fixed bits in VMX operation).
2864 * @param pVCpu The cross context virtual CPU structure.
2865 * @param cbInstr The instruction length in bytes.
2866 */
2867IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2868{
2869 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2870 uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2871
2872 /*
2873 * If CR0.TS is owned by the host:
2874 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2875 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2876 * CLTS instruction completes without clearing CR0.TS.
2877 *
2878 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2879 */
2880 if (fGstHostMask & X86_CR0_TS)
2881 {
2882 if (fReadShadow & X86_CR0_TS)
2883 {
2884 Log2(("clts: Guest intercept -> VM-exit\n"));
2885
2886 VMXVEXITINFO ExitInfo;
2887 RT_ZERO(ExitInfo);
2888 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2889 ExitInfo.cbInstr = cbInstr;
2890 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2891 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2892 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2893 }
2894
2895 return VINF_VMX_MODIFIES_BEHAVIOR;
2896 }
2897
2898 /*
2899 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2900 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2901 */
2902 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2903}
2904
2905
2906/**
2907 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2908 * (CR0/CR4 write).
2909 *
2910 * @returns Strict VBox status code.
2911 * @param pVCpu The cross context virtual CPU structure.
2912 * @param iCrReg The control register (either CR0 or CR4).
2913 * @param uGuestCrX The current guest CR0/CR4.
2914 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2915 * VM-exit is caused.
2916 * @param iGReg The general register from which the CR0/CR4 value is being
2917 * loaded.
2918 * @param cbInstr The instruction length in bytes.
2919 */
2920IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2921 uint8_t cbInstr)
2922{
2923 Assert(puNewCrX);
2924 Assert(iCrReg == 0 || iCrReg == 4);
2925 Assert(iGReg < X86_GREG_COUNT);
2926
2927 uint64_t const uNewCrX = *puNewCrX;
2928 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2929 {
2930 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2931
2932 VMXVEXITINFO ExitInfo;
2933 RT_ZERO(ExitInfo);
2934 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2935 ExitInfo.cbInstr = cbInstr;
2936 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2937 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2938 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2939 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2940 }
2941
2942 /*
2943 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2944 * must not be modified the instruction.
2945 *
2946 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2947 */
2948 uint64_t uGuestCrX;
2949 uint64_t fGstHostMask;
2950 if (iCrReg == 0)
2951 {
2952 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2953 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2954 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2955 }
2956 else
2957 {
2958 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2959 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2960 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2961 }
2962
2963 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2964 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2965}
2966
2967
2968/**
2969 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2970 *
2971 * @returns VBox strict status code.
2972 * @param pVCpu The cross context virtual CPU structure.
2973 * @param iGReg The general register to which the CR3 value is being stored.
2974 * @param cbInstr The instruction length in bytes.
2975 */
2976IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
2977{
2978 Assert(iGReg < X86_GREG_COUNT);
2979 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
2980
2981 /*
2982 * If the CR3-store exiting control is set, we must cause a VM-exit.
2983 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2984 */
2985 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
2986 {
2987 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
2988
2989 VMXVEXITINFO ExitInfo;
2990 RT_ZERO(ExitInfo);
2991 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2992 ExitInfo.cbInstr = cbInstr;
2993 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
2994 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
2995 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2996 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2997 }
2998
2999 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3000}
3001
3002
3003/**
3004 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3005 *
3006 * @returns VBox strict status code.
3007 * @param pVCpu The cross context virtual CPU structure.
3008 * @param uNewCr3 The new CR3 value.
3009 * @param iGReg The general register from which the CR3 value is being
3010 * loaded.
3011 * @param cbInstr The instruction length in bytes.
3012 */
3013IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3014{
3015 Assert(iGReg < X86_GREG_COUNT);
3016
3017 /*
3018 * If the CR3-load exiting control is set and the new CR3 value does not
3019 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3020 *
3021 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3022 */
3023 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3024 {
3025 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3026
3027 VMXVEXITINFO ExitInfo;
3028 RT_ZERO(ExitInfo);
3029 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3030 ExitInfo.cbInstr = cbInstr;
3031 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3032 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3033 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3034 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3035 }
3036
3037 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3038}
3039
3040
3041/**
3042 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3043 *
3044 * @returns VBox strict status code.
3045 * @param pVCpu The cross context virtual CPU structure.
3046 * @param iGReg The general register to which the CR8 value is being stored.
3047 * @param cbInstr The instruction length in bytes.
3048 */
3049IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3050{
3051 Assert(iGReg < X86_GREG_COUNT);
3052
3053 /*
3054 * If the CR8-store exiting control is set, we must cause a VM-exit.
3055 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3056 */
3057 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3058 {
3059 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3060
3061 VMXVEXITINFO ExitInfo;
3062 RT_ZERO(ExitInfo);
3063 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3064 ExitInfo.cbInstr = cbInstr;
3065 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3066 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3067 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3068 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3069 }
3070
3071 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3072}
3073
3074
3075/**
3076 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3077 *
3078 * @returns VBox strict status code.
3079 * @param pVCpu The cross context virtual CPU structure.
3080 * @param iGReg The general register from which the CR8 value is being
3081 * loaded.
3082 * @param cbInstr The instruction length in bytes.
3083 */
3084IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3085{
3086 Assert(iGReg < X86_GREG_COUNT);
3087
3088 /*
3089 * If the CR8-load exiting control is set, we must cause a VM-exit.
3090 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3091 */
3092 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3093 {
3094 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3095
3096 VMXVEXITINFO ExitInfo;
3097 RT_ZERO(ExitInfo);
3098 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3099 ExitInfo.cbInstr = cbInstr;
3100 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3101 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3102 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3103 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3104 }
3105
3106 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3107}
3108
3109
3110/**
3111 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3112 * GReg,DRx' (DRx read).
3113 *
3114 * @returns VBox strict status code.
3115 * @param pVCpu The cross context virtual CPU structure.
3116 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3117 * VMXINSTRID_MOV_FROM_DRX).
3118 * @param iDrReg The debug register being accessed.
3119 * @param iGReg The general register to/from which the DRx value is being
3120 * store/loaded.
3121 * @param cbInstr The instruction length in bytes.
3122 */
3123IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3124 uint8_t cbInstr)
3125{
3126 Assert(iDrReg <= 7);
3127 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3128 Assert(iGReg < X86_GREG_COUNT);
3129
3130 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3131 {
3132 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3133 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3134 VMXVEXITINFO ExitInfo;
3135 RT_ZERO(ExitInfo);
3136 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3137 ExitInfo.cbInstr = cbInstr;
3138 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3139 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3140 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3141 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3142 }
3143
3144 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3145}
3146
3147
3148/**
3149 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3150 *
3151 * @returns VBox strict status code.
3152 * @param pVCpu The cross context virtual CPU structure.
3153 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3154 * VMXINSTRID_IO_OUT).
3155 * @param u16Port The I/O port being accessed.
3156 * @param fImm Whether the I/O port was encoded using an immediate operand
3157 * or the implicit DX register.
3158 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3159 * @param cbInstr The instruction length in bytes.
3160 */
3161IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3162 uint8_t cbInstr)
3163{
3164 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3165 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3166
3167 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3168 if (fIntercept)
3169 {
3170 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3171 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3172 VMXVEXITINFO ExitInfo;
3173 RT_ZERO(ExitInfo);
3174 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3175 ExitInfo.cbInstr = cbInstr;
3176 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3177 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3178 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3179 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3180 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3181 }
3182
3183 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3184}
3185
3186
3187/**
3188 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3189 *
3190 * @returns VBox strict status code.
3191 * @param pVCpu The cross context virtual CPU structure.
3192 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3193 * VMXINSTRID_IO_OUTS).
3194 * @param u16Port The I/O port being accessed.
3195 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3196 * @param fRep Whether the instruction has a REP prefix or not.
3197 * @param ExitInstrInfo The VM-exit instruction info. field.
3198 * @param cbInstr The instruction length in bytes.
3199 */
3200IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3201 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3202{
3203 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3204 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3205 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3206 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3207 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3208
3209 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3210 if (fIntercept)
3211 {
3212 /*
3213 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3214 */
3215 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3216 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3217 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3218 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3219 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3220
3221 uint32_t uDirection;
3222 uint64_t uGuestLinearAddr;
3223 if (uInstrId == VMXINSTRID_IO_INS)
3224 {
3225 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3226 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3227 }
3228 else
3229 {
3230 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3231 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3232 }
3233
3234 /*
3235 * If the segment is unusable, the guest-linear address in undefined.
3236 * We shall clear it for consistency.
3237 *
3238 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3239 */
3240 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3241 uGuestLinearAddr = 0;
3242
3243 VMXVEXITINFO ExitInfo;
3244 RT_ZERO(ExitInfo);
3245 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3246 ExitInfo.cbInstr = cbInstr;
3247 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3248 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3249 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3250 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3251 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3252 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3253 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3254 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3255 ExitInfo.InstrInfo = ExitInstrInfo;
3256 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3257 }
3258
3259 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3260}
3261
3262
3263/**
3264 * VMX VM-exit handler for VM-exits due to MWAIT.
3265 *
3266 * @returns VBox strict status code.
3267 * @param pVCpu The cross context virtual CPU structure.
3268 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3269 * @param cbInstr The instruction length in bytes.
3270 */
3271IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3272{
3273 VMXVEXITINFO ExitInfo;
3274 RT_ZERO(ExitInfo);
3275 ExitInfo.uReason = VMX_EXIT_MWAIT;
3276 ExitInfo.cbInstr = cbInstr;
3277 ExitInfo.u64Qual = fMonitorHwArmed;
3278 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3279}
3280
3281
3282/**
3283 * VMX VM-exit handler for VM-exits due to PAUSE.
3284 *
3285 * @returns VBox strict status code.
3286 * @param pVCpu The cross context virtual CPU structure.
3287 * @param cbInstr The instruction length in bytes.
3288 */
3289IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3290{
3291 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3292
3293 /*
3294 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3295 * "PAUSE-loop exiting" control.
3296 *
3297 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3298 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3299 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3300 * a VM-exit.
3301 *
3302 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3303 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3304 */
3305 bool fIntercept = false;
3306 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3307 fIntercept = true;
3308 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3309 && pVCpu->iem.s.uCpl == 0)
3310 {
3311 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3312
3313 /*
3314 * A previous-PAUSE-tick value of 0 is used to identify the first time
3315 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3316 * consider this to be the first execution of PAUSE in a loop according
3317 * to the Intel.
3318 *
3319 * All subsequent records for the previous-PAUSE-tick we ensure that it
3320 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3321 */
3322 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3323 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3324 uint64_t const uTick = TMCpuTickGet(pVCpu);
3325 uint32_t const uPleGap = pVmcs->u32PleGap;
3326 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3327 if ( *puPrevPauseTick == 0
3328 || uTick - *puPrevPauseTick > uPleGap)
3329 *puFirstPauseLoopTick = uTick;
3330 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3331 fIntercept = true;
3332
3333 *puPrevPauseTick = uTick | 1;
3334 }
3335
3336 if (fIntercept)
3337 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3338
3339 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3340}
3341
3342
3343/**
3344 * VMX VM-exit handler for VM-exits due to task switches.
3345 *
3346 * @returns VBox strict status code.
3347 * @param pVCpu The cross context virtual CPU structure.
3348 * @param enmTaskSwitch The cause of the task switch.
3349 * @param SelNewTss The selector of the new TSS.
3350 * @param cbInstr The instruction length in bytes.
3351 */
3352IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3353{
3354 /*
3355 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3356 *
3357 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3358 * instruction or delivery of the exception generated by one of these instructions
3359 * lead to a task switch through a task gate in the IDT, we need to provide the
3360 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3361 * leaves the VM-exit instruction length field undefined.
3362 *
3363 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3364 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3365 */
3366 Assert(cbInstr <= 15);
3367
3368 uint8_t uType;
3369 switch (enmTaskSwitch)
3370 {
3371 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3372 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3373 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3374 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3375 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3376 }
3377
3378 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3379 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3380 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3381 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3382}
3383
3384
3385/**
3386 * VMX VM-exit handler for trap-like VM-exits.
3387 *
3388 * @returns VBox strict status code.
3389 * @param pVCpu The cross context virtual CPU structure.
3390 * @param pExitInfo Pointer to the VM-exit information.
3391 * @param pExitEventInfo Pointer to the VM-exit event information.
3392 */
3393IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3394{
3395 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3396 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3397 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3398}
3399
3400
3401/**
3402 * VMX VM-exit handler for VM-exits due to task switches.
3403 *
3404 * This is intended for task switches where the caller provides all the relevant
3405 * VM-exit information.
3406 *
3407 * @returns VBox strict status code.
3408 * @param pVCpu The cross context virtual CPU structure.
3409 * @param pExitInfo Pointer to the VM-exit information.
3410 * @param pExitEventInfo Pointer to the VM-exit event information.
3411 */
3412IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3413 PCVMXVEXITEVENTINFO pExitEventInfo)
3414{
3415 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3416 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3417 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3418 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3419 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3420}
3421
3422
3423/**
3424 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3425 *
3426 * @returns VBox strict status code.
3427 * @param pVCpu The cross context virtual CPU structure.
3428 */
3429IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3430{
3431 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3432 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3433
3434 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3435 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3436
3437 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3438 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3439 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3440
3441 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3442 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3443}
3444
3445
3446/**
3447 * VMX VM-exit handler for VM-exits due to external interrupts.
3448 *
3449 * @returns VBox strict status code.
3450 * @param pVCpu The cross context virtual CPU structure.
3451 * @param uVector The external interrupt vector (pass 0 if the interrupt
3452 * is still pending since we typically won't know the
3453 * vector).
3454 * @param fIntPending Whether the external interrupt is pending or
3455 * acknowledged in the interrupt controller.
3456 */
3457IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3458{
3459 Assert(!fIntPending || uVector == 0);
3460
3461 /* The VM-exit is subject to "External interrupt exiting" being set. */
3462 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3463 {
3464 if (fIntPending)
3465 {
3466 /*
3467 * If the interrupt is pending and we don't need to acknowledge the
3468 * interrupt on VM-exit, cause the VM-exit immediately.
3469 *
3470 * See Intel spec 25.2 "Other Causes Of VM Exits".
3471 */
3472 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3473 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3474
3475 /*
3476 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3477 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3478 * acknowledged that the interrupt has been consumed. Callers would have to call
3479 * us again after getting the vector (and ofc, with fIntPending with false).
3480 */
3481 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3482 }
3483
3484 /*
3485 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3486 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3487 * all set, we need to record the vector of the external interrupt in the
3488 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3489 *
3490 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3491 */
3492 uint32_t uExitIntInfo;
3493 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3494 {
3495 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3496 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3497 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3498 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3499 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3500 }
3501 else
3502 uExitIntInfo = 0;
3503 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3504
3505 /*
3506 * Cause the VM-exit whether or not the vector has been stored
3507 * in the VM-exit interruption-information field.
3508 */
3509 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3510 }
3511
3512 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3513}
3514
3515
3516/**
3517 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3518 * an event.
3519 *
3520 * @returns VBox strict status code.
3521 * @param pVCpu The cross context virtual CPU structure.
3522 */
3523IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3524{
3525 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3526 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3527 {
3528 /*
3529 * The NMI-unblocking due to IRET field need not be set for double faults.
3530 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3531 */
3532 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3533 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3534 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3535 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3536 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3537 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3538 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3539 }
3540
3541 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3542}
3543
3544
3545/**
3546 * VMX VM-exit handler for VM-exit due to delivery of an events.
3547 *
3548 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3549 * all the relevant VM-exit information.
3550 *
3551 * @returns VBox strict status code.
3552 * @param pVCpu The cross context virtual CPU structure.
3553 * @param pExitInfo Pointer to the VM-exit information.
3554 * @param pExitEventInfo Pointer to the VM-exit event information.
3555 */
3556IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3557{
3558 Assert(pExitInfo);
3559 Assert(pExitEventInfo);
3560 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3561 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3562
3563 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3564 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3565 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3566 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3567 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3568 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3569}
3570
3571
3572/**
3573 * VMX VM-exit handler for VM-exits due to delivery of an event.
3574 *
3575 * @returns VBox strict status code.
3576 * @param pVCpu The cross context virtual CPU structure.
3577 * @param uVector The interrupt / exception vector.
3578 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3579 * @param uErrCode The error code associated with the event.
3580 * @param uCr2 The CR2 value in case of a \#PF exception.
3581 * @param cbInstr The instruction length in bytes.
3582 */
3583IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3584 uint8_t cbInstr)
3585{
3586 /*
3587 * If the event is being injected as part of VM-entry, it is -not- subject to event
3588 * intercepts in the nested-guest. However, secondary exceptions that occur during
3589 * injection of any event -are- subject to event interception.
3590 *
3591 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3592 */
3593 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3594 {
3595 /*
3596 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3597 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3598 *
3599 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3600 */
3601 if ( uVector == X86_XCPT_NMI
3602 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3603 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3604 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3605 else
3606 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3607
3608 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3609 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3610 }
3611
3612 /*
3613 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3614 * If not, the caller will continue delivery of the external interrupt as it would
3615 * normally. The interrupt is no longer pending in the interrupt controller at this
3616 * point.
3617 */
3618 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3619 {
3620 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3621 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3622 }
3623
3624 /*
3625 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3626 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3627 * interrupts.
3628 */
3629 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3630 bool fIntercept;
3631 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3632 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3633 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3634 else
3635 {
3636 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3637 fIntercept = false;
3638 }
3639
3640 /*
3641 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3642 * relevant VM-exit information and cause the VM-exit.
3643 */
3644 if (fIntercept)
3645 {
3646 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3647
3648 /* Construct the rest of the event related information fields and cause the VM-exit. */
3649 uint64_t u64ExitQual;
3650 if (uVector == X86_XCPT_PF)
3651 {
3652 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3653 u64ExitQual = uCr2;
3654 }
3655 else if (uVector == X86_XCPT_DB)
3656 {
3657 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3658 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3659 }
3660 else
3661 u64ExitQual = 0;
3662
3663 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3664 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3665 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3666 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3667 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3668 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3669 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3670 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3671 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3672 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3673
3674 /*
3675 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3676 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3677 * length.
3678 */
3679 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3680 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3681 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3682 else
3683 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3684
3685 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3686 }
3687
3688 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3689}
3690
3691
3692#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3693/**
3694 * VMX VM-exit handler for EPT violation.
3695 *
3696 * @param pVCpu The cross context virtual CPU structure.
3697 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3698 * @param fEptAccess The EPT paging structure bits.
3699 * @param GCPhysAddr The physical address causing the EPT violation.
3700 * @param GCPtrAddr The linear address causing the EPT violation.
3701 * @param cbInstr The VM-exit instruction length.
3702 */
3703IEM_STATIC VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint64_t fEptAccess, RTGCPHYS GCPhysAddr,
3704 uint64_t GCPtrAddr, bool fLinearAddrValid, uint8_t cbInstr)
3705{
3706 /*
3707 * If the linear address isn't valid (can happen when loading PDPTEs
3708 * as part of MOV CR execution) the linear address field is undefined.
3709 * While we can leave it this way, it's preferrable to zero it for consistency.
3710 */
3711 Assert(fLinearAddrValid || GCPtrAddr == 0);
3712
3713 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3714 uint8_t const fSupportsAccessDirty = fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY;
3715
3716 uint8_t const fDataRead = ((fAccess & IEM_ACCESS_DATA_R) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3717 uint8_t const fDataWrite = ((fAccess & IEM_ACCESS_DATA_RW) == IEM_ACCESS_DATA_RW) | fSupportsAccessDirty;
3718 uint8_t const fInstrFetch = (fAccess & IEM_ACCESS_INSTRUCTION) == IEM_ACCESS_INSTRUCTION;
3719 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3720 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3721 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3722 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3723
3724 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
3725 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
3726 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
3727 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
3728 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
3729 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
3730 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fLinearAddrValid)
3731 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
3732
3733 /** @todo bit 8 of Exit Qualification!
3734 * If the access causing the EPT violation is to a guest-physical address that is
3735 * the translation of a linear address.
3736 * - OR -
3737 * if the access causing the EPT violation is to a paging-structure entry as part
3738 * of a page walk or the update of an accessed or dirty bit.
3739 *
3740 * Caller needs to be able to distinguish this... */
3741
3742#ifdef VBOX_STRICT
3743 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
3744 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
3745 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
3746 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
3747 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3748 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3749 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
3750#endif
3751
3752 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3753 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
3754 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3755
3756 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
3757}
3758#endif
3759
3760
3761/**
3762 * VMX VM-exit handler for APIC accesses.
3763 *
3764 * @param pVCpu The cross context virtual CPU structure.
3765 * @param offAccess The offset of the register being accessed.
3766 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3767 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3768 */
3769IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3770{
3771 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3772
3773 VMXAPICACCESS enmAccess;
3774 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3775 if (fInEventDelivery)
3776 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3777 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3778 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3779 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3780 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3781 else
3782 enmAccess = VMXAPICACCESS_LINEAR_READ;
3783
3784 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3785 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3786 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3787}
3788
3789
3790/**
3791 * VMX VM-exit handler for APIC accesses.
3792 *
3793 * This is intended for APIC accesses where the caller provides all the
3794 * relevant VM-exit information.
3795 *
3796 * @returns VBox strict status code.
3797 * @param pVCpu The cross context virtual CPU structure.
3798 * @param pExitInfo Pointer to the VM-exit information.
3799 * @param pExitEventInfo Pointer to the VM-exit event information.
3800 */
3801IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3802 PCVMXVEXITEVENTINFO pExitEventInfo)
3803{
3804 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3805 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3806 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3807 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3808 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3809 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3810 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3811 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3812 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3813}
3814
3815
3816/**
3817 * VMX VM-exit handler for APIC-write VM-exits.
3818 *
3819 * @param pVCpu The cross context virtual CPU structure.
3820 * @param offApic The write to the virtual-APIC page offset that caused this
3821 * VM-exit.
3822 */
3823IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3824{
3825 Assert(offApic < XAPIC_OFF_END + 4);
3826 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3827 offApic &= UINT16_C(0xfff);
3828 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3829}
3830
3831
3832/**
3833 * Sets virtual-APIC write emulation as pending.
3834 *
3835 * @param pVCpu The cross context virtual CPU structure.
3836 * @param offApic The offset in the virtual-APIC page that was written.
3837 */
3838DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3839{
3840 Assert(offApic < XAPIC_OFF_END + 4);
3841
3842 /*
3843 * Record the currently updated APIC offset, as we need this later for figuring
3844 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3845 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3846 */
3847 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3848
3849 /*
3850 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3851 * virtualization or APIC-write emulation).
3852 */
3853 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3854 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3855}
3856
3857
3858/**
3859 * Clears any pending virtual-APIC write emulation.
3860 *
3861 * @returns The virtual-APIC offset that was written before clearing it.
3862 * @param pVCpu The cross context virtual CPU structure.
3863 */
3864DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3865{
3866 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3867 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3868 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3869 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3870 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3871 return offVirtApicWrite;
3872}
3873
3874
3875/**
3876 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3877 *
3878 * @returns The register from the virtual-APIC page.
3879 * @param pVCpu The cross context virtual CPU structure.
3880 * @param offReg The offset of the register being read.
3881 */
3882IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3883{
3884 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3885
3886 uint32_t uReg = 0;
3887 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3888 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3889 AssertMsgStmt(RT_SUCCESS(rc),
3890 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3891 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3892 uReg = 0);
3893 return uReg;
3894}
3895
3896
3897/**
3898 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3899 *
3900 * @returns The register from the virtual-APIC page.
3901 * @param pVCpu The cross context virtual CPU structure.
3902 * @param offReg The offset of the register being read.
3903 */
3904IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3905{
3906 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3907
3908 uint64_t uReg = 0;
3909 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3910 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3911 AssertMsgStmt(RT_SUCCESS(rc),
3912 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3913 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3914 uReg = 0);
3915 return uReg;
3916}
3917
3918
3919/**
3920 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3921 *
3922 * @param pVCpu The cross context virtual CPU structure.
3923 * @param offReg The offset of the register being written.
3924 * @param uReg The register value to write.
3925 */
3926IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3927{
3928 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3929
3930 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3931 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3932 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3933 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3934}
3935
3936
3937/**
3938 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3939 *
3940 * @param pVCpu The cross context virtual CPU structure.
3941 * @param offReg The offset of the register being written.
3942 * @param uReg The register value to write.
3943 */
3944IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3945{
3946 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3947
3948 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3949 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3950 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3951 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3952}
3953
3954
3955/**
3956 * Sets the vector in a virtual-APIC 256-bit sparse register.
3957 *
3958 * @param pVCpu The cross context virtual CPU structure.
3959 * @param offReg The offset of the 256-bit spare register.
3960 * @param uVector The vector to set.
3961 *
3962 * @remarks This is based on our APIC device code.
3963 */
3964IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3965{
3966 /* Determine the vector offset within the chunk. */
3967 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3968
3969 /* Read the chunk at the offset. */
3970 uint32_t uReg;
3971 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3972 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3973 if (RT_SUCCESS(rc))
3974 {
3975 /* Modify the chunk. */
3976 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3977 uReg |= RT_BIT(idxVectorBit);
3978
3979 /* Write the chunk. */
3980 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3981 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3982 uVector, offReg, GCPhysVirtApic, rc));
3983 }
3984 else
3985 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3986 uVector, offReg, GCPhysVirtApic, rc));
3987}
3988
3989
3990/**
3991 * Clears the vector in a virtual-APIC 256-bit sparse register.
3992 *
3993 * @param pVCpu The cross context virtual CPU structure.
3994 * @param offReg The offset of the 256-bit spare register.
3995 * @param uVector The vector to clear.
3996 *
3997 * @remarks This is based on our APIC device code.
3998 */
3999IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
4000{
4001 /* Determine the vector offset within the chunk. */
4002 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4003
4004 /* Read the chunk at the offset. */
4005 uint32_t uReg;
4006 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4007 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4008 if (RT_SUCCESS(rc))
4009 {
4010 /* Modify the chunk. */
4011 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4012 uReg &= ~RT_BIT(idxVectorBit);
4013
4014 /* Write the chunk. */
4015 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4016 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4017 uVector, offReg, GCPhysVirtApic, rc));
4018 }
4019 else
4020 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4021 uVector, offReg, GCPhysVirtApic, rc));
4022}
4023
4024
4025/**
4026 * Checks if a memory access to the APIC-access page must causes an APIC-access
4027 * VM-exit.
4028 *
4029 * @param pVCpu The cross context virtual CPU structure.
4030 * @param offAccess The offset of the register being accessed.
4031 * @param cbAccess The size of the access in bytes.
4032 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4033 * IEM_ACCESS_TYPE_WRITE).
4034 *
4035 * @remarks This must not be used for MSR-based APIC-access page accesses!
4036 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4037 */
4038IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4039{
4040 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4041 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4042
4043 /*
4044 * We must cause a VM-exit if any of the following are true:
4045 * - TPR shadowing isn't active.
4046 * - The access size exceeds 32-bits.
4047 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4048 *
4049 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4050 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4051 */
4052 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4053 || cbAccess > sizeof(uint32_t)
4054 || ((offAccess + cbAccess - 1) & 0xc)
4055 || offAccess >= XAPIC_OFF_END + 4)
4056 return true;
4057
4058 /*
4059 * If the access is part of an operation where we have already
4060 * virtualized a virtual-APIC write, we must cause a VM-exit.
4061 */
4062 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4063 return true;
4064
4065 /*
4066 * Check write accesses to the APIC-access page that cause VM-exits.
4067 */
4068 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4069 {
4070 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4071 {
4072 /*
4073 * With APIC-register virtualization, a write access to any of the
4074 * following registers are virtualized. Accessing any other register
4075 * causes a VM-exit.
4076 */
4077 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4078 switch (offAlignedAccess)
4079 {
4080 case XAPIC_OFF_ID:
4081 case XAPIC_OFF_TPR:
4082 case XAPIC_OFF_EOI:
4083 case XAPIC_OFF_LDR:
4084 case XAPIC_OFF_DFR:
4085 case XAPIC_OFF_SVR:
4086 case XAPIC_OFF_ESR:
4087 case XAPIC_OFF_ICR_LO:
4088 case XAPIC_OFF_ICR_HI:
4089 case XAPIC_OFF_LVT_TIMER:
4090 case XAPIC_OFF_LVT_THERMAL:
4091 case XAPIC_OFF_LVT_PERF:
4092 case XAPIC_OFF_LVT_LINT0:
4093 case XAPIC_OFF_LVT_LINT1:
4094 case XAPIC_OFF_LVT_ERROR:
4095 case XAPIC_OFF_TIMER_ICR:
4096 case XAPIC_OFF_TIMER_DCR:
4097 break;
4098 default:
4099 return true;
4100 }
4101 }
4102 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4103 {
4104 /*
4105 * With virtual-interrupt delivery, a write access to any of the
4106 * following registers are virtualized. Accessing any other register
4107 * causes a VM-exit.
4108 *
4109 * Note! The specification does not allow writing to offsets in-between
4110 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4111 */
4112 switch (offAccess)
4113 {
4114 case XAPIC_OFF_TPR:
4115 case XAPIC_OFF_EOI:
4116 case XAPIC_OFF_ICR_LO:
4117 break;
4118 default:
4119 return true;
4120 }
4121 }
4122 else
4123 {
4124 /*
4125 * Without APIC-register virtualization or virtual-interrupt delivery,
4126 * only TPR accesses are virtualized.
4127 */
4128 if (offAccess == XAPIC_OFF_TPR)
4129 { /* likely */ }
4130 else
4131 return true;
4132 }
4133 }
4134 else
4135 {
4136 /*
4137 * Check read accesses to the APIC-access page that cause VM-exits.
4138 */
4139 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4140 {
4141 /*
4142 * With APIC-register virtualization, a read access to any of the
4143 * following registers are virtualized. Accessing any other register
4144 * causes a VM-exit.
4145 */
4146 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4147 switch (offAlignedAccess)
4148 {
4149 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4150 case XAPIC_OFF_ID:
4151 case XAPIC_OFF_VERSION:
4152 case XAPIC_OFF_TPR:
4153 case XAPIC_OFF_EOI:
4154 case XAPIC_OFF_LDR:
4155 case XAPIC_OFF_DFR:
4156 case XAPIC_OFF_SVR:
4157 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4158 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4159 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4160 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4161 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4162 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4163 case XAPIC_OFF_ESR:
4164 case XAPIC_OFF_ICR_LO:
4165 case XAPIC_OFF_ICR_HI:
4166 case XAPIC_OFF_LVT_TIMER:
4167 case XAPIC_OFF_LVT_THERMAL:
4168 case XAPIC_OFF_LVT_PERF:
4169 case XAPIC_OFF_LVT_LINT0:
4170 case XAPIC_OFF_LVT_LINT1:
4171 case XAPIC_OFF_LVT_ERROR:
4172 case XAPIC_OFF_TIMER_ICR:
4173 case XAPIC_OFF_TIMER_DCR:
4174 break;
4175 default:
4176 return true;
4177 }
4178 }
4179 else
4180 {
4181 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4182 if (offAccess == XAPIC_OFF_TPR)
4183 { /* likely */ }
4184 else
4185 return true;
4186 }
4187 }
4188
4189 /* The APIC access is virtualized, does not cause a VM-exit. */
4190 return false;
4191}
4192
4193
4194/**
4195 * Virtualizes a memory-based APIC access where the address is not used to access
4196 * memory.
4197 *
4198 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4199 * page-faults but do not use the address to access memory.
4200 *
4201 * @param pVCpu The cross context virtual CPU structure.
4202 * @param pGCPhysAccess Pointer to the guest-physical address used.
4203 */
4204IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4205{
4206 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4207 Assert(pGCPhysAccess);
4208
4209 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4210 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4211 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4212
4213 if (GCPhysAccess == GCPhysApic)
4214 {
4215 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4216 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4217 uint16_t const cbAccess = 1;
4218 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4219 if (fIntercept)
4220 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4221
4222 *pGCPhysAccess = GCPhysApic | offAccess;
4223 return VINF_VMX_MODIFIES_BEHAVIOR;
4224 }
4225
4226 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4227}
4228
4229
4230/**
4231 * Virtualizes a memory-based APIC access.
4232 *
4233 * @returns VBox strict status code.
4234 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4235 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4236 *
4237 * @param pVCpu The cross context virtual CPU structure.
4238 * @param offAccess The offset of the register being accessed (within the
4239 * APIC-access page).
4240 * @param cbAccess The size of the access in bytes.
4241 * @param pvData Pointer to the data being written or where to store the data
4242 * being read.
4243 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4244 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4245 */
4246IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4247 uint32_t fAccess)
4248{
4249 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4250 Assert(pvData);
4251 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4252 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4253 || (fAccess & IEM_ACCESS_INSTRUCTION));
4254
4255 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4256 if (fIntercept)
4257 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4258
4259 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4260 {
4261 /*
4262 * A write access to the APIC-access page that is virtualized (rather than
4263 * causing a VM-exit) writes data to the virtual-APIC page.
4264 */
4265 uint32_t const u32Data = *(uint32_t *)pvData;
4266 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4267
4268 /*
4269 * Record the currently updated APIC offset, as we need this later for figuring
4270 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4271 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4272 *
4273 * After completion of the current operation, we need to perform TPR virtualization,
4274 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4275 *
4276 * The current operation may be a REP-prefixed string instruction, execution of any
4277 * other instruction, or delivery of an event through the IDT.
4278 *
4279 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4280 * performed now but later after completion of the current operation.
4281 *
4282 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4283 */
4284 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4285 }
4286 else
4287 {
4288 /*
4289 * A read access from the APIC-access page that is virtualized (rather than
4290 * causing a VM-exit) returns data from the virtual-APIC page.
4291 *
4292 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4293 */
4294 Assert(cbAccess <= 4);
4295 Assert(offAccess < XAPIC_OFF_END + 4);
4296 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4297
4298 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4299 u32Data &= s_auAccessSizeMasks[cbAccess];
4300 *(uint32_t *)pvData = u32Data;
4301 }
4302
4303 return VINF_VMX_MODIFIES_BEHAVIOR;
4304}
4305
4306
4307/**
4308 * Virtualizes an MSR-based APIC read access.
4309 *
4310 * @returns VBox strict status code.
4311 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4312 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4313 * handled by the x2APIC device.
4314 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4315 * not within the range of valid MSRs, caller must raise \#GP(0).
4316 * @param pVCpu The cross context virtual CPU structure.
4317 * @param idMsr The x2APIC MSR being read.
4318 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4319 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4320 */
4321IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4322{
4323 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4324 Assert(pu64Value);
4325
4326 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4327 {
4328 if ( idMsr >= MSR_IA32_X2APIC_START
4329 && idMsr <= MSR_IA32_X2APIC_END)
4330 {
4331 uint16_t const offReg = (idMsr & 0xff) << 4;
4332 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4333 *pu64Value = u64Value;
4334 return VINF_VMX_MODIFIES_BEHAVIOR;
4335 }
4336 return VERR_OUT_OF_RANGE;
4337 }
4338
4339 if (idMsr == MSR_IA32_X2APIC_TPR)
4340 {
4341 uint16_t const offReg = (idMsr & 0xff) << 4;
4342 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4343 *pu64Value = u64Value;
4344 return VINF_VMX_MODIFIES_BEHAVIOR;
4345 }
4346
4347 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4348}
4349
4350
4351/**
4352 * Virtualizes an MSR-based APIC write access.
4353 *
4354 * @returns VBox strict status code.
4355 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4356 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4357 * not within the range of valid MSRs, caller must raise \#GP(0).
4358 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4359 *
4360 * @param pVCpu The cross context virtual CPU structure.
4361 * @param idMsr The x2APIC MSR being written.
4362 * @param u64Value The value of the x2APIC MSR being written.
4363 */
4364IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4365{
4366 /*
4367 * Check if the access is to be virtualized.
4368 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4369 */
4370 if ( idMsr == MSR_IA32_X2APIC_TPR
4371 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4372 && ( idMsr == MSR_IA32_X2APIC_EOI
4373 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4374 {
4375 /* Validate the MSR write depending on the register. */
4376 switch (idMsr)
4377 {
4378 case MSR_IA32_X2APIC_TPR:
4379 case MSR_IA32_X2APIC_SELF_IPI:
4380 {
4381 if (u64Value & UINT64_C(0xffffffffffffff00))
4382 return VERR_OUT_OF_RANGE;
4383 break;
4384 }
4385 case MSR_IA32_X2APIC_EOI:
4386 {
4387 if (u64Value != 0)
4388 return VERR_OUT_OF_RANGE;
4389 break;
4390 }
4391 }
4392
4393 /* Write the MSR to the virtual-APIC page. */
4394 uint16_t const offReg = (idMsr & 0xff) << 4;
4395 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4396
4397 /*
4398 * Record the currently updated APIC offset, as we need this later for figuring
4399 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4400 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4401 */
4402 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4403
4404 return VINF_VMX_MODIFIES_BEHAVIOR;
4405 }
4406
4407 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4408}
4409
4410
4411/**
4412 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4413 *
4414 * @returns VBox status code.
4415 * @retval VINF_SUCCESS when the highest set bit is found.
4416 * @retval VERR_NOT_FOUND when no bit is set.
4417 *
4418 * @param pVCpu The cross context virtual CPU structure.
4419 * @param offReg The offset of the APIC 256-bit sparse register.
4420 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4421 * set in the register. Only valid when VINF_SUCCESS is
4422 * returned.
4423 *
4424 * @remarks The format of the 256-bit sparse register here mirrors that found in
4425 * real APIC hardware.
4426 */
4427static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4428{
4429 Assert(offReg < XAPIC_OFF_END + 4);
4430 Assert(pidxHighestBit);
4431
4432 /*
4433 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4434 * However, in each fragment only the first 4 bytes are used.
4435 */
4436 uint8_t const cFrags = 8;
4437 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4438 {
4439 uint16_t const offFrag = iFrag * 16;
4440 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4441 if (!u32Frag)
4442 continue;
4443
4444 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4445 Assert(idxHighestBit > 0);
4446 --idxHighestBit;
4447 Assert(idxHighestBit <= UINT8_MAX);
4448 *pidxHighestBit = idxHighestBit;
4449 return VINF_SUCCESS;
4450 }
4451 return VERR_NOT_FOUND;
4452}
4453
4454
4455/**
4456 * Evaluates pending virtual interrupts.
4457 *
4458 * @param pVCpu The cross context virtual CPU structure.
4459 */
4460IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4461{
4462 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4463
4464 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4465 {
4466 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4467 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4468
4469 if ((uRvi >> 4) > (uPpr >> 4))
4470 {
4471 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4472 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4473 }
4474 else
4475 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4476 }
4477}
4478
4479
4480/**
4481 * Performs PPR virtualization.
4482 *
4483 * @returns VBox strict status code.
4484 * @param pVCpu The cross context virtual CPU structure.
4485 */
4486IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4487{
4488 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4489 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4490
4491 /*
4492 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4493 * or EOI-virtualization.
4494 *
4495 * See Intel spec. 29.1.3 "PPR Virtualization".
4496 */
4497 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4498 uint32_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4499
4500 uint32_t uPpr;
4501 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4502 uPpr = uTpr & 0xff;
4503 else
4504 uPpr = uSvi & 0xf0;
4505
4506 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4507 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4508}
4509
4510
4511/**
4512 * Performs VMX TPR virtualization.
4513 *
4514 * @returns VBox strict status code.
4515 * @param pVCpu The cross context virtual CPU structure.
4516 */
4517IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4518{
4519 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4520
4521 /*
4522 * We should have already performed the virtual-APIC write to the TPR offset
4523 * in the virtual-APIC page. We now perform TPR virtualization.
4524 *
4525 * See Intel spec. 29.1.2 "TPR Virtualization".
4526 */
4527 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4528 {
4529 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4530 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4531
4532 /*
4533 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4534 * See Intel spec. 29.1.2 "TPR Virtualization".
4535 */
4536 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4537 {
4538 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4539 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4540 }
4541 }
4542 else
4543 {
4544 iemVmxPprVirtualization(pVCpu);
4545 iemVmxEvalPendingVirtIntrs(pVCpu);
4546 }
4547
4548 return VINF_SUCCESS;
4549}
4550
4551
4552/**
4553 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4554 * not.
4555 *
4556 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4557 * @param pVCpu The cross context virtual CPU structure.
4558 * @param uVector The interrupt that was acknowledged using an EOI.
4559 */
4560IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4561{
4562 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4563 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4564
4565 if (uVector < 64)
4566 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4567 if (uVector < 128)
4568 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4569 if (uVector < 192)
4570 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4571 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4572}
4573
4574
4575/**
4576 * Performs EOI virtualization.
4577 *
4578 * @returns VBox strict status code.
4579 * @param pVCpu The cross context virtual CPU structure.
4580 */
4581IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4582{
4583 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4584 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4585
4586 /*
4587 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4588 * and get the next guest-interrupt that's in-service (if any).
4589 *
4590 * See Intel spec. 29.1.4 "EOI Virtualization".
4591 */
4592 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4593 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4594 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4595
4596 uint8_t uVector = uSvi;
4597 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4598
4599 uVector = 0;
4600 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4601
4602 if (uVector)
4603 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4604 else
4605 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4606
4607 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4608 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4609
4610 iemVmxPprVirtualization(pVCpu);
4611 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4612 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4613 iemVmxEvalPendingVirtIntrs(pVCpu);
4614 return VINF_SUCCESS;
4615}
4616
4617
4618/**
4619 * Performs self-IPI virtualization.
4620 *
4621 * @returns VBox strict status code.
4622 * @param pVCpu The cross context virtual CPU structure.
4623 */
4624IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4625{
4626 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4627 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4628
4629 /*
4630 * We should have already performed the virtual-APIC write to the self-IPI offset
4631 * in the virtual-APIC page. We now perform self-IPI virtualization.
4632 *
4633 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4634 */
4635 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4636 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4637 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4638 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4639 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4640 if (uVector > uRvi)
4641 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4642 iemVmxEvalPendingVirtIntrs(pVCpu);
4643 return VINF_SUCCESS;
4644}
4645
4646
4647/**
4648 * Performs VMX APIC-write emulation.
4649 *
4650 * @returns VBox strict status code.
4651 * @param pVCpu The cross context virtual CPU structure.
4652 */
4653IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4654{
4655 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4656
4657 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4658 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4659
4660 /*
4661 * Perform APIC-write emulation based on the virtual-APIC register written.
4662 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4663 */
4664 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4665 VBOXSTRICTRC rcStrict;
4666 switch (offApicWrite)
4667 {
4668 case XAPIC_OFF_TPR:
4669 {
4670 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4671 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4672 uTpr &= UINT32_C(0x000000ff);
4673 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4674 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4675 rcStrict = iemVmxTprVirtualization(pVCpu);
4676 break;
4677 }
4678
4679 case XAPIC_OFF_EOI:
4680 {
4681 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4682 {
4683 /* Clear VEOI and perform EOI virtualization. */
4684 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4685 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4686 rcStrict = iemVmxEoiVirtualization(pVCpu);
4687 }
4688 else
4689 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4690 break;
4691 }
4692
4693 case XAPIC_OFF_ICR_LO:
4694 {
4695 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4696 {
4697 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4698 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4699 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4700 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4701 if ( !(uIcrLo & fIcrLoMb0)
4702 && (uIcrLo & fIcrLoMb1))
4703 {
4704 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4705 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4706 }
4707 else
4708 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4709 }
4710 else
4711 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4712 break;
4713 }
4714
4715 case XAPIC_OFF_ICR_HI:
4716 {
4717 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4718 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4719 uIcrHi &= UINT32_C(0xff000000);
4720 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4721 rcStrict = VINF_SUCCESS;
4722 break;
4723 }
4724
4725 default:
4726 {
4727 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4728 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4729 break;
4730 }
4731 }
4732
4733 return rcStrict;
4734}
4735
4736
4737/**
4738 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4739 *
4740 * @param pVCpu The cross context virtual CPU structure.
4741 * @param pszInstr The VMX instruction name (for logging purposes).
4742 */
4743DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4744{
4745 /*
4746 * Guest Control Registers, Debug Registers, and MSRs.
4747 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4748 */
4749 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4750 const char * const pszFailure = "VM-exit";
4751 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4752
4753 /* CR0 reserved bits. */
4754 {
4755 /* CR0 MB1 bits. */
4756 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4757 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4758 if (fUnrestrictedGuest)
4759 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4760 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4761 { /* likely */ }
4762 else
4763 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4764
4765 /* CR0 MBZ bits. */
4766 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4767 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4768 { /* likely */ }
4769 else
4770 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4771
4772 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4773 if ( !fUnrestrictedGuest
4774 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4775 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4776 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4777 }
4778
4779 /* CR4 reserved bits. */
4780 {
4781 /* CR4 MB1 bits. */
4782 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4783 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4784 { /* likely */ }
4785 else
4786 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4787
4788 /* CR4 MBZ bits. */
4789 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4790 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4791 { /* likely */ }
4792 else
4793 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4794 }
4795
4796 /* DEBUGCTL MSR. */
4797 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4798 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4799 { /* likely */ }
4800 else
4801 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4802
4803 /* 64-bit CPU checks. */
4804 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4805 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4806 {
4807 if (fGstInLongMode)
4808 {
4809 /* PAE must be set. */
4810 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4811 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4812 { /* likely */ }
4813 else
4814 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4815 }
4816 else
4817 {
4818 /* PCIDE should not be set. */
4819 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4820 { /* likely */ }
4821 else
4822 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4823 }
4824
4825 /* CR3. */
4826 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4827 { /* likely */ }
4828 else
4829 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4830
4831 /* DR7. */
4832 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4833 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4834 { /* likely */ }
4835 else
4836 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4837
4838 /* SYSENTER ESP and SYSENTER EIP. */
4839 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4840 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4841 { /* likely */ }
4842 else
4843 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4844 }
4845
4846 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4847 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4848
4849 /* PAT MSR. */
4850 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4851 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4852 { /* likely */ }
4853 else
4854 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4855
4856 /* EFER MSR. */
4857 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4858 {
4859 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4860 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4861 { /* likely */ }
4862 else
4863 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4864
4865 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4866 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4867 if ( fGstLma == fGstInLongMode
4868 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4869 || fGstLma == fGstLme))
4870 { /* likely */ }
4871 else
4872 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4873 }
4874
4875 /* We don't support IA32_BNDCFGS MSR yet. */
4876 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4877
4878 NOREF(pszInstr);
4879 NOREF(pszFailure);
4880 return VINF_SUCCESS;
4881}
4882
4883
4884/**
4885 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4886 *
4887 * @param pVCpu The cross context virtual CPU structure.
4888 * @param pszInstr The VMX instruction name (for logging purposes).
4889 */
4890DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4891{
4892 /*
4893 * Segment registers.
4894 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4895 */
4896 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4897 const char * const pszFailure = "VM-exit";
4898 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4899 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4900 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4901
4902 /* Selectors. */
4903 if ( !fGstInV86Mode
4904 && !fUnrestrictedGuest
4905 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4906 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4907
4908 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4909 {
4910 CPUMSELREG SelReg;
4911 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4912 if (RT_LIKELY(rc == VINF_SUCCESS))
4913 { /* likely */ }
4914 else
4915 return rc;
4916
4917 /*
4918 * Virtual-8086 mode checks.
4919 */
4920 if (fGstInV86Mode)
4921 {
4922 /* Base address. */
4923 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4924 { /* likely */ }
4925 else
4926 {
4927 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4928 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4929 }
4930
4931 /* Limit. */
4932 if (SelReg.u32Limit == 0xffff)
4933 { /* likely */ }
4934 else
4935 {
4936 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4937 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4938 }
4939
4940 /* Attribute. */
4941 if (SelReg.Attr.u == 0xf3)
4942 { /* likely */ }
4943 else
4944 {
4945 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4946 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4947 }
4948
4949 /* We're done; move to checking the next segment. */
4950 continue;
4951 }
4952
4953 /* Checks done by 64-bit CPUs. */
4954 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4955 {
4956 /* Base address. */
4957 if ( iSegReg == X86_SREG_FS
4958 || iSegReg == X86_SREG_GS)
4959 {
4960 if (X86_IS_CANONICAL(SelReg.u64Base))
4961 { /* likely */ }
4962 else
4963 {
4964 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4965 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4966 }
4967 }
4968 else if (iSegReg == X86_SREG_CS)
4969 {
4970 if (!RT_HI_U32(SelReg.u64Base))
4971 { /* likely */ }
4972 else
4973 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
4974 }
4975 else
4976 {
4977 if ( SelReg.Attr.n.u1Unusable
4978 || !RT_HI_U32(SelReg.u64Base))
4979 { /* likely */ }
4980 else
4981 {
4982 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4983 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4984 }
4985 }
4986 }
4987
4988 /*
4989 * Checks outside Virtual-8086 mode.
4990 */
4991 uint8_t const uSegType = SelReg.Attr.n.u4Type;
4992 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
4993 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
4994 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
4995 uint8_t const fPresent = SelReg.Attr.n.u1Present;
4996 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
4997 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
4998 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
4999
5000 /* Code or usable segment. */
5001 if ( iSegReg == X86_SREG_CS
5002 || fUsable)
5003 {
5004 /* Reserved bits (bits 31:17 and bits 11:8). */
5005 if (!(SelReg.Attr.u & 0xfffe0f00))
5006 { /* likely */ }
5007 else
5008 {
5009 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5010 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5011 }
5012
5013 /* Descriptor type. */
5014 if (fCodeDataSeg)
5015 { /* likely */ }
5016 else
5017 {
5018 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5019 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5020 }
5021
5022 /* Present. */
5023 if (fPresent)
5024 { /* likely */ }
5025 else
5026 {
5027 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5028 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5029 }
5030
5031 /* Granularity. */
5032 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5033 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5034 { /* likely */ }
5035 else
5036 {
5037 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5038 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5039 }
5040 }
5041
5042 if (iSegReg == X86_SREG_CS)
5043 {
5044 /* Segment Type and DPL. */
5045 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5046 && fUnrestrictedGuest)
5047 {
5048 if (uDpl == 0)
5049 { /* likely */ }
5050 else
5051 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5052 }
5053 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5054 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5055 {
5056 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5057 if (uDpl == AttrSs.n.u2Dpl)
5058 { /* likely */ }
5059 else
5060 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5061 }
5062 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5063 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5064 {
5065 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5066 if (uDpl <= AttrSs.n.u2Dpl)
5067 { /* likely */ }
5068 else
5069 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5070 }
5071 else
5072 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5073
5074 /* Def/Big. */
5075 if ( fGstInLongMode
5076 && fSegLong)
5077 {
5078 if (uDefBig == 0)
5079 { /* likely */ }
5080 else
5081 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5082 }
5083 }
5084 else if (iSegReg == X86_SREG_SS)
5085 {
5086 /* Segment Type. */
5087 if ( !fUsable
5088 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5089 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5090 { /* likely */ }
5091 else
5092 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5093
5094 /* DPL. */
5095 if (!fUnrestrictedGuest)
5096 {
5097 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5098 { /* likely */ }
5099 else
5100 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5101 }
5102 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5103 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5104 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5105 {
5106 if (uDpl == 0)
5107 { /* likely */ }
5108 else
5109 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5110 }
5111 }
5112 else
5113 {
5114 /* DS, ES, FS, GS. */
5115 if (fUsable)
5116 {
5117 /* Segment type. */
5118 if (uSegType & X86_SEL_TYPE_ACCESSED)
5119 { /* likely */ }
5120 else
5121 {
5122 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5124 }
5125
5126 if ( !(uSegType & X86_SEL_TYPE_CODE)
5127 || (uSegType & X86_SEL_TYPE_READ))
5128 { /* likely */ }
5129 else
5130 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5131
5132 /* DPL. */
5133 if ( !fUnrestrictedGuest
5134 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5135 {
5136 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5137 { /* likely */ }
5138 else
5139 {
5140 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5142 }
5143 }
5144 }
5145 }
5146 }
5147
5148 /*
5149 * LDTR.
5150 */
5151 {
5152 CPUMSELREG Ldtr;
5153 Ldtr.Sel = pVmcs->GuestLdtr;
5154 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5155 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5156 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5157
5158 if (!Ldtr.Attr.n.u1Unusable)
5159 {
5160 /* Selector. */
5161 if (!(Ldtr.Sel & X86_SEL_LDT))
5162 { /* likely */ }
5163 else
5164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5165
5166 /* Base. */
5167 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5168 {
5169 if (X86_IS_CANONICAL(Ldtr.u64Base))
5170 { /* likely */ }
5171 else
5172 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5173 }
5174
5175 /* Attributes. */
5176 /* Reserved bits (bits 31:17 and bits 11:8). */
5177 if (!(Ldtr.Attr.u & 0xfffe0f00))
5178 { /* likely */ }
5179 else
5180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5181
5182 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5183 { /* likely */ }
5184 else
5185 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5186
5187 if (!Ldtr.Attr.n.u1DescType)
5188 { /* likely */ }
5189 else
5190 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5191
5192 if (Ldtr.Attr.n.u1Present)
5193 { /* likely */ }
5194 else
5195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5196
5197 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5198 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5199 { /* likely */ }
5200 else
5201 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5202 }
5203 }
5204
5205 /*
5206 * TR.
5207 */
5208 {
5209 CPUMSELREG Tr;
5210 Tr.Sel = pVmcs->GuestTr;
5211 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5212 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5213 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5214
5215 /* Selector. */
5216 if (!(Tr.Sel & X86_SEL_LDT))
5217 { /* likely */ }
5218 else
5219 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5220
5221 /* Base. */
5222 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5223 {
5224 if (X86_IS_CANONICAL(Tr.u64Base))
5225 { /* likely */ }
5226 else
5227 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5228 }
5229
5230 /* Attributes. */
5231 /* Reserved bits (bits 31:17 and bits 11:8). */
5232 if (!(Tr.Attr.u & 0xfffe0f00))
5233 { /* likely */ }
5234 else
5235 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5236
5237 if (!Tr.Attr.n.u1Unusable)
5238 { /* likely */ }
5239 else
5240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5241
5242 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5243 || ( !fGstInLongMode
5244 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5245 { /* likely */ }
5246 else
5247 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5248
5249 if (!Tr.Attr.n.u1DescType)
5250 { /* likely */ }
5251 else
5252 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5253
5254 if (Tr.Attr.n.u1Present)
5255 { /* likely */ }
5256 else
5257 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5258
5259 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5260 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5261 { /* likely */ }
5262 else
5263 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5264 }
5265
5266 NOREF(pszInstr);
5267 NOREF(pszFailure);
5268 return VINF_SUCCESS;
5269}
5270
5271
5272/**
5273 * Checks guest GDTR and IDTR as part of VM-entry.
5274 *
5275 * @param pVCpu The cross context virtual CPU structure.
5276 * @param pszInstr The VMX instruction name (for logging purposes).
5277 */
5278DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5279{
5280 /*
5281 * GDTR and IDTR.
5282 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5283 */
5284 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5285 const char *const pszFailure = "VM-exit";
5286
5287 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5288 {
5289 /* Base. */
5290 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5291 { /* likely */ }
5292 else
5293 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5294
5295 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5296 { /* likely */ }
5297 else
5298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5299 }
5300
5301 /* Limit. */
5302 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5303 { /* likely */ }
5304 else
5305 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5306
5307 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5308 { /* likely */ }
5309 else
5310 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5311
5312 NOREF(pszInstr);
5313 NOREF(pszFailure);
5314 return VINF_SUCCESS;
5315}
5316
5317
5318/**
5319 * Checks guest RIP and RFLAGS as part of VM-entry.
5320 *
5321 * @param pVCpu The cross context virtual CPU structure.
5322 * @param pszInstr The VMX instruction name (for logging purposes).
5323 */
5324DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5325{
5326 /*
5327 * RIP and RFLAGS.
5328 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5329 */
5330 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5331 const char *const pszFailure = "VM-exit";
5332 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5333
5334 /* RIP. */
5335 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5336 {
5337 X86DESCATTR AttrCs;
5338 AttrCs.u = pVmcs->u32GuestCsAttr;
5339 if ( !fGstInLongMode
5340 || !AttrCs.n.u1Long)
5341 {
5342 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5343 { /* likely */ }
5344 else
5345 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5346 }
5347
5348 if ( fGstInLongMode
5349 && AttrCs.n.u1Long)
5350 {
5351 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5352 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5353 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5354 { /* likely */ }
5355 else
5356 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5357 }
5358 }
5359
5360 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5361 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5362 : pVmcs->u64GuestRFlags.s.Lo;
5363 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5364 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5365 { /* likely */ }
5366 else
5367 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5368
5369 if ( fGstInLongMode
5370 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5371 {
5372 if (!(uGuestRFlags & X86_EFL_VM))
5373 { /* likely */ }
5374 else
5375 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5376 }
5377
5378 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5379 {
5380 if (uGuestRFlags & X86_EFL_IF)
5381 { /* likely */ }
5382 else
5383 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5384 }
5385
5386 NOREF(pszInstr);
5387 NOREF(pszFailure);
5388 return VINF_SUCCESS;
5389}
5390
5391
5392/**
5393 * Checks guest non-register state as part of VM-entry.
5394 *
5395 * @param pVCpu The cross context virtual CPU structure.
5396 * @param pszInstr The VMX instruction name (for logging purposes).
5397 */
5398DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5399{
5400 /*
5401 * Guest non-register state.
5402 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5403 */
5404 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5405 const char *const pszFailure = "VM-exit";
5406
5407 /*
5408 * Activity state.
5409 */
5410 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5411 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5412 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5413 { /* likely */ }
5414 else
5415 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5416
5417 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5418 if ( !AttrSs.n.u2Dpl
5419 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5420 { /* likely */ }
5421 else
5422 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5423
5424 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5425 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5426 {
5427 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5428 { /* likely */ }
5429 else
5430 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5431 }
5432
5433 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5434 {
5435 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5436 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5437 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5438 switch (pVmcs->u32GuestActivityState)
5439 {
5440 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5441 {
5442 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5443 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5444 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5445 && ( uVector == X86_XCPT_DB
5446 || uVector == X86_XCPT_MC))
5447 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5448 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5449 { /* likely */ }
5450 else
5451 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5452 break;
5453 }
5454
5455 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5456 {
5457 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5458 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5459 && uVector == X86_XCPT_MC))
5460 { /* likely */ }
5461 else
5462 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5463 break;
5464 }
5465
5466 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5467 default:
5468 break;
5469 }
5470 }
5471
5472 /*
5473 * Interruptibility state.
5474 */
5475 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5476 { /* likely */ }
5477 else
5478 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5479
5480 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5481 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5482 { /* likely */ }
5483 else
5484 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5485
5486 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5487 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5488 { /* likely */ }
5489 else
5490 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5491
5492 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5493 {
5494 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5495 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5496 {
5497 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5498 { /* likely */ }
5499 else
5500 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5501 }
5502 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5503 {
5504 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5505 { /* likely */ }
5506 else
5507 {
5508 /*
5509 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5510 * We update the Exit qualification only when blocking-by-STI is set
5511 * without blocking-by-MovSS being set. Although in practise it does not
5512 * make much difference since the order of checks are implementation defined.
5513 */
5514 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5515 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5516 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5517 }
5518
5519 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5520 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5521 { /* likely */ }
5522 else
5523 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5524 }
5525 }
5526
5527 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5528 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5529 { /* likely */ }
5530 else
5531 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5532
5533 /* We don't support SGX yet. So enclave-interruption must not be set. */
5534 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5535 { /* likely */ }
5536 else
5537 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5538
5539 /*
5540 * Pending debug exceptions.
5541 */
5542 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5543 ? pVmcs->u64GuestPendingDbgXcpts.u
5544 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5545 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5546 { /* likely */ }
5547 else
5548 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5549
5550 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5551 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5552 {
5553 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5554 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5555 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5557
5558 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5559 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5560 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5561 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5562 }
5563
5564 /* We don't support RTM (Real-time Transactional Memory) yet. */
5565 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5566 { /* likely */ }
5567 else
5568 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5569
5570 /*
5571 * VMCS link pointer.
5572 */
5573 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5574 {
5575 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5576 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5577 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5578 { /* likely */ }
5579 else
5580 {
5581 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5582 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5583 }
5584
5585 /* Validate the address. */
5586 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5587 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5588 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5589 { /* likely */ }
5590 else
5591 {
5592 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5593 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5594 }
5595 }
5596
5597 NOREF(pszInstr);
5598 NOREF(pszFailure);
5599 return VINF_SUCCESS;
5600}
5601
5602
5603/**
5604 * Checks guest PDPTEs as part of VM-entry.
5605 *
5606 * @param pVCpu The cross context virtual CPU structure.
5607 * @param pfPdpesMapped Where to store whether PAE PDPTEs (and PDPT) have been
5608 * mapped as part of checking guest state.
5609 * @param pszInstr The VMX instruction name (for logging purposes).
5610 */
5611IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, bool *pfPdpesMapped, const char *pszInstr)
5612{
5613 /*
5614 * Guest PDPTEs.
5615 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5616 */
5617 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5618 const char * const pszFailure = "VM-exit";
5619 *pfPdpesMapped = false;
5620
5621 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
5622 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5623 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5624 {
5625#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5626 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
5627 {
5628 /* Get PDPTEs from the VMCS. */
5629 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
5630 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
5631 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
5632 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
5633 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
5634
5635 /* Check validity of the PDPTEs. */
5636 bool const fValid = PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]);
5637 if (fValid)
5638 { /* likely */ }
5639 else
5640 {
5641 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5642 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5643 }
5644 }
5645 else
5646#endif
5647 {
5648 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
5649 if (rc == VINF_SUCCESS)
5650 *pfPdpesMapped = true;
5651 else
5652 {
5653 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5654 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5655 }
5656 }
5657 }
5658
5659 NOREF(pszInstr);
5660 NOREF(pszFailure);
5661 return VINF_SUCCESS;
5662}
5663
5664
5665/**
5666 * Checks guest-state as part of VM-entry.
5667 *
5668 * @returns VBox status code.
5669 * @param pVCpu The cross context virtual CPU structure.
5670 * @param pfPdpesMapped Where to store whether PAE PDPTEs (and PDPT) have been
5671 * mapped as part of checking guest state.
5672 * @param pszInstr The VMX instruction name (for logging purposes).
5673 */
5674IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, bool *pfPdpesMapped, const char *pszInstr)
5675{
5676 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5677 if (RT_SUCCESS(rc))
5678 {
5679 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5680 if (RT_SUCCESS(rc))
5681 {
5682 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5683 if (RT_SUCCESS(rc))
5684 {
5685 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5686 if (RT_SUCCESS(rc))
5687 {
5688 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5689 if (RT_SUCCESS(rc))
5690 return iemVmxVmentryCheckGuestPdptes(pVCpu, pfPdpesMapped, pszInstr);
5691 }
5692 }
5693 }
5694 }
5695 return rc;
5696}
5697
5698
5699/**
5700 * Checks host-state as part of VM-entry.
5701 *
5702 * @returns VBox status code.
5703 * @param pVCpu The cross context virtual CPU structure.
5704 * @param pszInstr The VMX instruction name (for logging purposes).
5705 */
5706IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5707{
5708 /*
5709 * Host Control Registers and MSRs.
5710 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5711 */
5712 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5713 const char * const pszFailure = "VMFail";
5714
5715 /* CR0 reserved bits. */
5716 {
5717 /* CR0 MB1 bits. */
5718 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5719 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5720 { /* likely */ }
5721 else
5722 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5723
5724 /* CR0 MBZ bits. */
5725 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5726 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5727 { /* likely */ }
5728 else
5729 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5730 }
5731
5732 /* CR4 reserved bits. */
5733 {
5734 /* CR4 MB1 bits. */
5735 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5736 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5737 { /* likely */ }
5738 else
5739 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5740
5741 /* CR4 MBZ bits. */
5742 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5743 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5744 { /* likely */ }
5745 else
5746 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5747 }
5748
5749 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5750 {
5751 /* CR3 reserved bits. */
5752 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5753 { /* likely */ }
5754 else
5755 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5756
5757 /* SYSENTER ESP and SYSENTER EIP. */
5758 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5759 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5760 { /* likely */ }
5761 else
5762 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5763 }
5764
5765 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5766 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5767
5768 /* PAT MSR. */
5769 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5770 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5771 { /* likely */ }
5772 else
5773 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5774
5775 /* EFER MSR. */
5776 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5777 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5778 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5779 { /* likely */ }
5780 else
5781 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5782
5783 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5784 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5785 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5786 if ( fHostInLongMode == fHostLma
5787 && fHostInLongMode == fHostLme)
5788 { /* likely */ }
5789 else
5790 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5791
5792 /*
5793 * Host Segment and Descriptor-Table Registers.
5794 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5795 */
5796 /* Selector RPL and TI. */
5797 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5798 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5799 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5800 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5801 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5802 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5803 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5804 { /* likely */ }
5805 else
5806 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5807
5808 /* CS and TR selectors cannot be 0. */
5809 if ( pVmcs->HostCs
5810 && pVmcs->HostTr)
5811 { /* likely */ }
5812 else
5813 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5814
5815 /* SS cannot be 0 if 32-bit host. */
5816 if ( fHostInLongMode
5817 || pVmcs->HostSs)
5818 { /* likely */ }
5819 else
5820 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5821
5822 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5823 {
5824 /* FS, GS, GDTR, IDTR, TR base address. */
5825 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5826 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5827 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5828 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5829 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5830 { /* likely */ }
5831 else
5832 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5833 }
5834
5835 /*
5836 * Host address-space size for 64-bit CPUs.
5837 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5838 */
5839 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5840 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5841 {
5842 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5843
5844 /* Logical processor in IA-32e mode. */
5845 if (fCpuInLongMode)
5846 {
5847 if (fHostInLongMode)
5848 {
5849 /* PAE must be set. */
5850 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5851 { /* likely */ }
5852 else
5853 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5854
5855 /* RIP must be canonical. */
5856 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5857 { /* likely */ }
5858 else
5859 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5860 }
5861 else
5862 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5863 }
5864 else
5865 {
5866 /* Logical processor is outside IA-32e mode. */
5867 if ( !fGstInLongMode
5868 && !fHostInLongMode)
5869 {
5870 /* PCIDE should not be set. */
5871 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5872 { /* likely */ }
5873 else
5874 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5875
5876 /* The high 32-bits of RIP MBZ. */
5877 if (!pVmcs->u64HostRip.s.Hi)
5878 { /* likely */ }
5879 else
5880 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5881 }
5882 else
5883 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5884 }
5885 }
5886 else
5887 {
5888 /* Host address-space size for 32-bit CPUs. */
5889 if ( !fGstInLongMode
5890 && !fHostInLongMode)
5891 { /* likely */ }
5892 else
5893 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5894 }
5895
5896 NOREF(pszInstr);
5897 NOREF(pszFailure);
5898 return VINF_SUCCESS;
5899}
5900
5901
5902#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5903/**
5904 * Checks the EPT pointer VMCS field as part of VM-entry.
5905 *
5906 * @returns VBox status code.
5907 * @param pVCpu The cross context virtual CPU structure.
5908 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
5909 * updated on success). Optional, can be NULL.
5910 */
5911IEM_STATIC int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, VMXVDIAG *penmVmxDiag)
5912{
5913 VMXVDIAG enmVmxDiag;
5914 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5915
5916 /* Reserved bits. */
5917 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
5918 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
5919 if (pVmcs->u64EptPtr.u & fValidMask)
5920 {
5921 /* Memory Type. */
5922 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
5923 uint8_t const fMemType = RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_MEMTYPE);
5924 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
5925 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
5926 || ( fMemType == VMX_EPTP_MEMTYPE_UC
5927 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
5928 {
5929 /*
5930 * Page walk length (PML4).
5931 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
5932 * of 5 but that seems to be removed from the latest specs. leaving only PML4
5933 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
5934 */
5935 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
5936 if (RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
5937 {
5938 /* Access and dirty bits support in EPT structures. */
5939 if ( !RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_ACCESS_DIRTY)
5940 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
5941 return VINF_SUCCESS;
5942
5943 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
5944 }
5945 else
5946 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
5947 }
5948 else
5949 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
5950 }
5951 else
5952 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
5953
5954 if (penmVmxDiag)
5955 *penmVmxDiag = enmVmxDiag;
5956 return VERR_VMX_VMENTRY_FAILED;
5957}
5958#endif
5959
5960
5961/**
5962 * Checks VMCS controls fields as part of VM-entry.
5963 *
5964 * @returns VBox status code.
5965 * @param pVCpu The cross context virtual CPU structure.
5966 * @param pszInstr The VMX instruction name (for logging purposes).
5967 *
5968 * @remarks This may update secondary-processor based VM-execution control fields
5969 * in the current VMCS if necessary.
5970 */
5971IEM_STATIC int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr)
5972{
5973 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5974 const char * const pszFailure = "VMFail";
5975
5976 /*
5977 * VM-execution controls.
5978 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
5979 */
5980 {
5981 /* Pin-based VM-execution controls. */
5982 {
5983 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
5984 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
5985 { /* likely */ }
5986 else
5987 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
5988
5989 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
5990 { /* likely */ }
5991 else
5992 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
5993 }
5994
5995 /* Processor-based VM-execution controls. */
5996 {
5997 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
5998 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
5999 { /* likely */ }
6000 else
6001 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6002
6003 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6004 { /* likely */ }
6005 else
6006 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6007 }
6008
6009 /* Secondary processor-based VM-execution controls. */
6010 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6011 {
6012 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6013 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6014 { /* likely */ }
6015 else
6016 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6017
6018 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6019 { /* likely */ }
6020 else
6021 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6022 }
6023 else
6024 Assert(!pVmcs->u32ProcCtls2);
6025
6026 /* CR3-target count. */
6027 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6028 { /* likely */ }
6029 else
6030 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6031
6032 /* I/O bitmaps physical addresses. */
6033 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6034 {
6035 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6036 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6037 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6038 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6039 { /* likely */ }
6040 else
6041 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6042
6043 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6044 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6045 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6046 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6047 { /* likely */ }
6048 else
6049 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6050 }
6051
6052 /* MSR bitmap physical address. */
6053 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6054 {
6055 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6056 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6057 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6058 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6059 { /* likely */ }
6060 else
6061 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6062 }
6063
6064 /* TPR shadow related controls. */
6065 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6066 {
6067 /* Virtual-APIC page physical address. */
6068 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6069 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6070 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6071 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6072 { /* likely */ }
6073 else
6074 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6075
6076 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6077 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6078 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6079 { /* likely */ }
6080 else
6081 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6082
6083 /* The rest done XXX document */
6084 }
6085 else
6086 {
6087 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6088 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6089 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6090 { /* likely */ }
6091 else
6092 {
6093 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6094 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6095 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6096 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6097 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6098 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6099 }
6100 }
6101
6102 /* NMI exiting and virtual-NMIs. */
6103 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6104 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6105 { /* likely */ }
6106 else
6107 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6108
6109 /* Virtual-NMIs and NMI-window exiting. */
6110 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6111 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6112 { /* likely */ }
6113 else
6114 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6115
6116 /* Virtualize APIC accesses. */
6117 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6118 {
6119 /* APIC-access physical address. */
6120 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6121 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6122 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6123 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6124 { /* likely */ }
6125 else
6126 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6127
6128 /*
6129 * Disallow APIC-access page and virtual-APIC page from being the same address.
6130 * Note! This is not an Intel requirement, but one imposed by our implementation.
6131 */
6132 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6133 * redirecting accesses between the APIC-access page and the virtual-APIC
6134 * page. If any nested hypervisor requires this, we can implement it later. */
6135 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6136 {
6137 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6138 if (GCPhysVirtApic != GCPhysApicAccess)
6139 { /* likely */ }
6140 else
6141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6142 }
6143 }
6144
6145 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6146 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6147 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6148 { /* likely */ }
6149 else
6150 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6151
6152 /* Virtual-interrupt delivery requires external interrupt exiting. */
6153 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6154 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6155 { /* likely */ }
6156 else
6157 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6158
6159 /* VPID. */
6160 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6161 || pVmcs->u16Vpid != 0)
6162 { /* likely */ }
6163 else
6164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6165
6166#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6167 /* Extended-Page-Table Pointer (EPTP). */
6168 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6169 {
6170 VMXVDIAG enmVmxDiag;
6171 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, &enmVmxDiag);
6172 if (RT_SUCCESS(rc))
6173 { /* likely */ }
6174 else
6175 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6176 }
6177#else
6178 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6179#endif
6180
6181 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6182 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6183 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6184 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6185 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6186 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6187 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6188
6189 /* VMCS shadowing. */
6190 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6191 {
6192 /* VMREAD-bitmap physical address. */
6193 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6194 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6195 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6196 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6197 { /* likely */ }
6198 else
6199 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6200
6201 /* VMWRITE-bitmap physical address. */
6202 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6203 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6204 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6205 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6206 { /* likely */ }
6207 else
6208 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6209 }
6210 }
6211
6212 /*
6213 * VM-exit controls.
6214 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6215 */
6216 {
6217 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6218 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6219 { /* likely */ }
6220 else
6221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6222
6223 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6224 { /* likely */ }
6225 else
6226 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6227
6228 /* Save preemption timer without activating it. */
6229 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6230 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6231 { /* likely */ }
6232 else
6233 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6234
6235 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6236 if (pVmcs->u32ExitMsrStoreCount)
6237 {
6238 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6239 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6240 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6241 { /* likely */ }
6242 else
6243 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6244 }
6245
6246 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6247 if (pVmcs->u32ExitMsrLoadCount)
6248 {
6249 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6250 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6251 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6252 { /* likely */ }
6253 else
6254 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6255 }
6256 }
6257
6258 /*
6259 * VM-entry controls.
6260 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6261 */
6262 {
6263 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6264 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6265 { /* likely */ }
6266 else
6267 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6268
6269 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6270 { /* likely */ }
6271 else
6272 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6273
6274 /* Event injection. */
6275 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6276 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6277 {
6278 /* Type and vector. */
6279 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6280 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6281 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6282 if ( !uRsvd
6283 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6284 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6285 { /* likely */ }
6286 else
6287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6288
6289 /* Exception error code. */
6290 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6291 {
6292 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6293 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6294 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6295 { /* likely */ }
6296 else
6297 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6298
6299 /* Exceptions that provide an error code. */
6300 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6301 && ( uVector == X86_XCPT_DF
6302 || uVector == X86_XCPT_TS
6303 || uVector == X86_XCPT_NP
6304 || uVector == X86_XCPT_SS
6305 || uVector == X86_XCPT_GP
6306 || uVector == X86_XCPT_PF
6307 || uVector == X86_XCPT_AC))
6308 { /* likely */ }
6309 else
6310 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6311
6312 /* Exception error-code reserved bits. */
6313 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6314 { /* likely */ }
6315 else
6316 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6317
6318 /* Injecting a software interrupt, software exception or privileged software exception. */
6319 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6320 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6321 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6322 {
6323 /* Instruction length must be in the range 0-15. */
6324 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6325 { /* likely */ }
6326 else
6327 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6328
6329 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6330 if ( pVmcs->u32EntryInstrLen != 0
6331 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6332 { /* likely */ }
6333 else
6334 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6335 }
6336 }
6337 }
6338
6339 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6340 if (pVmcs->u32EntryMsrLoadCount)
6341 {
6342 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6343 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6344 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6345 { /* likely */ }
6346 else
6347 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6348 }
6349
6350 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6351 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6352 }
6353
6354 NOREF(pszInstr);
6355 NOREF(pszFailure);
6356 return VINF_SUCCESS;
6357}
6358
6359
6360/**
6361 * Loads the guest control registers, debug register and some MSRs as part of
6362 * VM-entry.
6363 *
6364 * @param pVCpu The cross context virtual CPU structure.
6365 */
6366IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6367{
6368 /*
6369 * Load guest control registers, debug registers and MSRs.
6370 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6371 */
6372 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6373
6374 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6375 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6376 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6377 CPUMSetGuestCR0(pVCpu, uGstCr0);
6378 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6379 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6380
6381 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6382 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6383
6384 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6385 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6386 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6387
6388 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6389 {
6390 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6391
6392 /* EFER MSR. */
6393 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6394 {
6395 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6396 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6397 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6398 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6399 if (fGstInLongMode)
6400 {
6401 /* If the nested-guest is in long mode, LMA and LME are both set. */
6402 Assert(fGstPaging);
6403 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6404 }
6405 else
6406 {
6407 /*
6408 * If the nested-guest is outside long mode:
6409 * - With paging: LMA is cleared, LME is cleared.
6410 * - Without paging: LMA is cleared, LME is left unmodified.
6411 */
6412 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6413 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6414 }
6415 }
6416 /* else: see below. */
6417 }
6418
6419 /* PAT MSR. */
6420 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6421 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6422
6423 /* EFER MSR. */
6424 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6425 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6426
6427 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6428 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6429
6430 /* We don't support IA32_BNDCFGS MSR yet. */
6431 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6432
6433 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6434}
6435
6436
6437/**
6438 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6439 *
6440 * @param pVCpu The cross context virtual CPU structure.
6441 */
6442IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6443{
6444 /*
6445 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6446 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6447 */
6448 /* CS, SS, ES, DS, FS, GS. */
6449 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6450 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6451 {
6452 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6453 CPUMSELREG VmcsSelReg;
6454 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6455 AssertRC(rc); NOREF(rc);
6456 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6457 {
6458 pGstSelReg->Sel = VmcsSelReg.Sel;
6459 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6460 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6461 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6462 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6463 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6464 }
6465 else
6466 {
6467 pGstSelReg->Sel = VmcsSelReg.Sel;
6468 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6469 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6470 switch (iSegReg)
6471 {
6472 case X86_SREG_CS:
6473 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6474 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6475 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6476 break;
6477
6478 case X86_SREG_SS:
6479 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6480 pGstSelReg->u32Limit = 0;
6481 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6482 break;
6483
6484 case X86_SREG_ES:
6485 case X86_SREG_DS:
6486 pGstSelReg->u64Base = 0;
6487 pGstSelReg->u32Limit = 0;
6488 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6489 break;
6490
6491 case X86_SREG_FS:
6492 case X86_SREG_GS:
6493 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6494 pGstSelReg->u32Limit = 0;
6495 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6496 break;
6497 }
6498 Assert(pGstSelReg->Attr.n.u1Unusable);
6499 }
6500 }
6501
6502 /* LDTR. */
6503 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6504 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6505 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6506 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6507 {
6508 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6509 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6510 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6511 }
6512 else
6513 {
6514 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6515 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6516 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6517 }
6518
6519 /* TR. */
6520 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6521 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6522 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6523 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6524 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6525 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6526 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6527
6528 /* GDTR. */
6529 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6530 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6531
6532 /* IDTR. */
6533 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6534 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6535}
6536
6537
6538/**
6539 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6540 *
6541 * @returns VBox status code.
6542 * @param pVCpu The cross context virtual CPU structure.
6543 * @param pszInstr The VMX instruction name (for logging purposes).
6544 */
6545IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6546{
6547 /*
6548 * Load guest MSRs.
6549 * See Intel spec. 26.4 "Loading MSRs".
6550 */
6551 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6552 const char *const pszFailure = "VM-exit";
6553
6554 /*
6555 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6556 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6557 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6558 */
6559 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6560 if (!cMsrs)
6561 return VINF_SUCCESS;
6562
6563 /*
6564 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6565 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6566 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6567 */
6568 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6569 if (fIsMsrCountValid)
6570 { /* likely */ }
6571 else
6572 {
6573 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6574 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6575 }
6576
6577 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6578 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6579 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6580 if (RT_SUCCESS(rc))
6581 {
6582 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6583 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6584 {
6585 if ( !pMsr->u32Reserved
6586 && pMsr->u32Msr != MSR_K8_FS_BASE
6587 && pMsr->u32Msr != MSR_K8_GS_BASE
6588 && pMsr->u32Msr != MSR_K6_EFER
6589 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6590 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6591 {
6592 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6593 if (rcStrict == VINF_SUCCESS)
6594 continue;
6595
6596 /*
6597 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6598 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6599 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6600 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6601 * MSR in ring-0 if possible, or come up with a better, generic solution.
6602 */
6603 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6604 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6605 ? kVmxVDiag_Vmentry_MsrLoadRing3
6606 : kVmxVDiag_Vmentry_MsrLoad;
6607 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6608 }
6609 else
6610 {
6611 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6612 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6613 }
6614 }
6615 }
6616 else
6617 {
6618 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6619 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6620 }
6621
6622 NOREF(pszInstr);
6623 NOREF(pszFailure);
6624 return VINF_SUCCESS;
6625}
6626
6627
6628/**
6629 * Loads the guest-state non-register state as part of VM-entry.
6630 *
6631 * @returns VBox status code.
6632 * @param pVCpu The cross context virtual CPU structure.
6633 *
6634 * @remarks This must be called only after loading the nested-guest register state
6635 * (especially nested-guest RIP).
6636 */
6637IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu)
6638{
6639 /*
6640 * Load guest non-register state.
6641 * See Intel spec. 26.6 "Special Features of VM Entry"
6642 */
6643 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6644
6645 /*
6646 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6647 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6648 *
6649 * See Intel spec. 26.6.1 "Interruptibility State".
6650 */
6651 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6652 if ( !fEntryVectoring
6653 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6654 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6655 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6656 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6657
6658 /* NMI blocking. */
6659 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6660 {
6661 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6662 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6663 else
6664 {
6665 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6666 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6667 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6668 }
6669 }
6670 else
6671 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6672
6673 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6674
6675 /*
6676 * Load the PAE PDPTEs from the VMCS when using EPT with PAE paging.
6677 */
6678 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6679 {
6680 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
6681 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
6682 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
6683 {
6684 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6685 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6686 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6687 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6688 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6689 AssertCompile(RT_ELEMENTS(aPaePdptes) == RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes));
6690 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes); i++)
6691 pVCpu->cpum.GstCtx.aPaePdpes[i].u = aPaePdptes[i].u;
6692 }
6693
6694 /*
6695 * Set PGM's copy of the EPT pointer.
6696 * The EPTP has already been validated while checking guest state.
6697 */
6698 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
6699 }
6700
6701 /* VPID is irrelevant. We don't support VPID yet. */
6702
6703 /* Clear address-range monitoring. */
6704 EMMonitorWaitClear(pVCpu);
6705}
6706
6707
6708/**
6709 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
6710 *
6711 * @param pVCpu The cross context virtual CPU structure.
6712 * @param pszInstr The VMX instruction name (for logging purposes).
6713 *
6714 * @remarks This assumes various VMCS related data structure pointers have already
6715 * been verified prior to calling this function.
6716 */
6717IEM_STATIC int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr)
6718{
6719 const char *const pszFailure = "VM-exit";
6720 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6721
6722 /*
6723 * Virtualize APIC accesses.
6724 */
6725 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6726 {
6727 /* APIC-access physical address. */
6728 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6729
6730 /*
6731 * Register the handler for the APIC-access page.
6732 *
6733 * We don't deregister the APIC-access page handler during the VM-exit as a different
6734 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6735 *
6736 * We leave the page registered until the first access that happens outside VMX non-root
6737 * mode. Guest software is allowed to access structures such as the APIC-access page
6738 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6739 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6740 *
6741 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6742 */
6743 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6744 {
6745 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6746 PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
6747 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6748 pVCpu0->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6749 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6750 if (RT_SUCCESS(rc))
6751 { /* likely */ }
6752 else
6753 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6754 }
6755 }
6756
6757 /*
6758 * VMCS shadowing.
6759 */
6760 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6761 {
6762 /* Read the VMREAD-bitmap. */
6763 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6764 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
6765 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
6766 if (RT_SUCCESS(rc))
6767 { /* likely */ }
6768 else
6769 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6770
6771 /* Read the VMWRITE-bitmap. */
6772 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
6773 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
6774 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
6775 if (RT_SUCCESS(rc))
6776 { /* likely */ }
6777 else
6778 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6779 }
6780
6781 /*
6782 * I/O bitmaps.
6783 */
6784 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6785 {
6786 /* Read the IO bitmap A. */
6787 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6788 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
6789 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
6790 if (RT_SUCCESS(rc))
6791 { /* likely */ }
6792 else
6793 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
6794
6795 /* Read the IO bitmap B. */
6796 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6797 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
6798 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
6799 if (RT_SUCCESS(rc))
6800 { /* likely */ }
6801 else
6802 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
6803 }
6804
6805 /*
6806 * TPR shadow and Virtual-APIC page.
6807 */
6808 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6809 {
6810 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6811 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6812 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6813 {
6814 /* Read the VTPR from the virtual-APIC page. */
6815 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6816 uint8_t u8VTpr;
6817 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6818 if (RT_SUCCESS(rc))
6819 { /* likely */ }
6820 else
6821 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6822
6823 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6824 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6825 { /* likely */ }
6826 else
6827 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6828 }
6829 }
6830
6831 /*
6832 * VMCS link pointer.
6833 */
6834 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6835 {
6836 /* Read the VMCS-link pointer from guest memory. */
6837 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6838 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
6839 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
6840 if (RT_SUCCESS(rc))
6841 { /* likely */ }
6842 else
6843 {
6844 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6845 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6846 }
6847
6848 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6849 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6850 { /* likely */ }
6851 else
6852 {
6853 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6854 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6855 }
6856
6857 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6858 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6859 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
6860 { /* likely */ }
6861 else
6862 {
6863 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6864 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6865 }
6866
6867 /* Update our cache of the guest physical address of the shadow VMCS. */
6868 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6869 }
6870
6871 /*
6872 * MSR bitmap.
6873 */
6874 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6875 {
6876 /* Read the MSR bitmap. */
6877 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
6879 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
6880 if (RT_SUCCESS(rc))
6881 { /* likely */ }
6882 else
6883 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6884 }
6885
6886 NOREF(pszFailure);
6887 NOREF(pszInstr);
6888 return VINF_SUCCESS;
6889}
6890
6891
6892/**
6893 * Loads the guest-state as part of VM-entry.
6894 *
6895 * @returns VBox status code.
6896 * @param pVCpu The cross context virtual CPU structure.
6897 * @param pszInstr The VMX instruction name (for logging purposes).
6898 *
6899 * @remarks This must be done after all the necessary steps prior to loading of
6900 * guest-state (e.g. checking various VMCS state).
6901 */
6902IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6903{
6904 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
6905 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6906
6907 /* Load guest segment registers. */
6908 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6909
6910 /*
6911 * Load guest RIP, RSP and RFLAGS.
6912 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6913 */
6914 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6915 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6916 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6917 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6918
6919 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6920 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6921 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6922
6923 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
6924 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6925
6926 /* Load VMX related structures and state referenced by the VMCS. */
6927 int rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
6928 if (rc == VINF_SUCCESS)
6929 { /* likely */ }
6930 else
6931 return rc;
6932
6933 NOREF(pszInstr);
6934 return VINF_SUCCESS;
6935}
6936
6937
6938/**
6939 * Returns whether there are is a pending debug exception on VM-entry.
6940 *
6941 * @param pVCpu The cross context virtual CPU structure.
6942 * @param pszInstr The VMX instruction name (for logging purposes).
6943 */
6944IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6945{
6946 /*
6947 * Pending debug exceptions.
6948 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6949 */
6950 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6951 Assert(pVmcs);
6952
6953 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6954 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6955 if (fPendingDbgXcpt)
6956 {
6957 uint8_t uEntryIntInfoType;
6958 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6959 if (fEntryVectoring)
6960 {
6961 switch (uEntryIntInfoType)
6962 {
6963 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6964 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6965 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6966 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6967 fPendingDbgXcpt = false;
6968 break;
6969
6970 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6971 {
6972 /*
6973 * Whether the pending debug exception for software exceptions other than
6974 * #BP and #OF is delivered after injecting the exception or is discard
6975 * is CPU implementation specific. We will discard them (easier).
6976 */
6977 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6978 if ( uVector != X86_XCPT_BP
6979 && uVector != X86_XCPT_OF)
6980 fPendingDbgXcpt = false;
6981 RT_FALL_THRU();
6982 }
6983 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6984 {
6985 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6986 fPendingDbgXcpt = false;
6987 break;
6988 }
6989 }
6990 }
6991 else
6992 {
6993 /*
6994 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6995 * pending debug exception is held pending or is discarded is CPU implementation
6996 * specific. We will discard them (easier).
6997 */
6998 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6999 fPendingDbgXcpt = false;
7000
7001 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7002 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7003 fPendingDbgXcpt = false;
7004 }
7005 }
7006
7007 NOREF(pszInstr);
7008 return fPendingDbgXcpt;
7009}
7010
7011
7012/**
7013 * Set up the monitor-trap flag (MTF).
7014 *
7015 * @param pVCpu The cross context virtual CPU structure.
7016 * @param pszInstr The VMX instruction name (for logging purposes).
7017 */
7018IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
7019{
7020 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7021 Assert(pVmcs);
7022 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7023 {
7024 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7025 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7026 }
7027 else
7028 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7029 NOREF(pszInstr);
7030}
7031
7032
7033/**
7034 * Sets up NMI-window exiting.
7035 *
7036 * @param pVCpu The cross context virtual CPU structure.
7037 * @param pszInstr The VMX instruction name (for logging purposes).
7038 */
7039IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
7040{
7041 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7042 Assert(pVmcs);
7043 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7044 {
7045 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7046 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7047 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7048 }
7049 else
7050 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7051 NOREF(pszInstr);
7052}
7053
7054
7055/**
7056 * Sets up interrupt-window exiting.
7057 *
7058 * @param pVCpu The cross context virtual CPU structure.
7059 * @param pszInstr The VMX instruction name (for logging purposes).
7060 */
7061IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
7062{
7063 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7064 Assert(pVmcs);
7065 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7066 {
7067 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7068 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7069 }
7070 else
7071 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7072 NOREF(pszInstr);
7073}
7074
7075
7076/**
7077 * Set up the VMX-preemption timer.
7078 *
7079 * @param pVCpu The cross context virtual CPU structure.
7080 * @param pszInstr The VMX instruction name (for logging purposes).
7081 */
7082IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
7083{
7084 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7085 Assert(pVmcs);
7086 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7087 {
7088 /*
7089 * If the timer is 0, we must cause a VM-exit before executing the first
7090 * nested-guest instruction. So we can flag as though the timer has already
7091 * expired and we will check and cause a VM-exit at the right priority elsewhere
7092 * in the code.
7093 */
7094 uint64_t uEntryTick;
7095 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7096 if (uPreemptTimer)
7097 {
7098 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7099 AssertRC(rc);
7100 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7101 }
7102 else
7103 {
7104 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7105 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7106 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7107 }
7108
7109 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7110 }
7111 else
7112 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7113
7114 NOREF(pszInstr);
7115}
7116
7117
7118/**
7119 * Injects an event using TRPM given a VM-entry interruption info. and related
7120 * fields.
7121 *
7122 * @param pVCpu The cross context virtual CPU structure.
7123 * @param pszInstr The VMX instruction name (for logging purposes).
7124 * @param uEntryIntInfo The VM-entry interruption info.
7125 * @param uErrCode The error code associated with the event if any.
7126 * @param cbInstr The VM-entry instruction length (for software
7127 * interrupts and software exceptions). Pass 0
7128 * otherwise.
7129 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7130 */
7131IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7132 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7133{
7134 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7135
7136 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7137 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7138 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7139
7140 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7141
7142 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7143 AssertRC(rc);
7144 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7145
7146 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7147 {
7148 TRPMSetErrorCode(pVCpu, uErrCode);
7149 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7150 }
7151
7152 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7153 {
7154 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7155 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7156 }
7157 else
7158 {
7159 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7160 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7161 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7162 {
7163 TRPMSetInstrLength(pVCpu, cbInstr);
7164 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7165 }
7166 }
7167
7168 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7169 {
7170 TRPMSetTrapDueToIcebp(pVCpu);
7171 Log(("%s: Injecting: icebp\n", pszInstr));
7172 }
7173
7174 NOREF(pszInstr);
7175}
7176
7177
7178/**
7179 * Performs event injection (if any) as part of VM-entry.
7180 *
7181 * @param pVCpu The cross context virtual CPU structure.
7182 * @param pszInstr The VMX instruction name (for logging purposes).
7183 */
7184IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7185{
7186 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7187
7188 /*
7189 * Inject events.
7190 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7191 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7192 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7193 * the actually delivery of this event.
7194 *
7195 * See Intel spec. 26.5 "Event Injection".
7196 */
7197 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7198 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7199
7200 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7201 if (fEntryIntInfoValid)
7202 {
7203 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7204 {
7205 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7206 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7207 }
7208 else
7209 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7210 pVCpu->cpum.GstCtx.cr2);
7211
7212 /*
7213 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7214 *
7215 * However, we do it here on VM-entry as well because while it isn't visible to guest
7216 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7217 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7218 *
7219 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7220 */
7221 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7222 }
7223 else
7224 {
7225 /*
7226 * Inject any pending guest debug exception.
7227 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7228 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7229 */
7230 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7231 if (fPendingDbgXcpt)
7232 {
7233 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7234 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7235 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7236 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7237 0 /* GCPtrFaultAddress */);
7238 }
7239 }
7240
7241 NOREF(pszInstr);
7242}
7243
7244
7245/**
7246 * Initializes all read-only VMCS fields as part of VM-entry.
7247 *
7248 * @param pVCpu The cross context virtual CPU structure.
7249 */
7250IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7251{
7252 /*
7253 * Any VMCS field which we do not establish on every VM-exit but may potentially
7254 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7255 * specified to be undefined, needs to be initialized here.
7256 *
7257 * Thus, it is especially important to clear the Exit qualification field
7258 * since it must be zero for VM-exits where it is not used. Similarly, the
7259 * VM-exit interruption information field's valid bit needs to be cleared for
7260 * the same reasons.
7261 */
7262 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7263 Assert(pVmcs);
7264
7265 /* 16-bit (none currently). */
7266 /* 32-bit. */
7267 pVmcs->u32RoVmInstrError = 0;
7268 pVmcs->u32RoExitReason = 0;
7269 pVmcs->u32RoExitIntInfo = 0;
7270 pVmcs->u32RoExitIntErrCode = 0;
7271 pVmcs->u32RoIdtVectoringInfo = 0;
7272 pVmcs->u32RoIdtVectoringErrCode = 0;
7273 pVmcs->u32RoExitInstrLen = 0;
7274 pVmcs->u32RoExitInstrInfo = 0;
7275
7276 /* 64-bit. */
7277 pVmcs->u64RoGuestPhysAddr.u = 0;
7278
7279 /* Natural-width. */
7280 pVmcs->u64RoExitQual.u = 0;
7281 pVmcs->u64RoIoRcx.u = 0;
7282 pVmcs->u64RoIoRsi.u = 0;
7283 pVmcs->u64RoIoRdi.u = 0;
7284 pVmcs->u64RoIoRip.u = 0;
7285 pVmcs->u64RoGuestLinearAddr.u = 0;
7286}
7287
7288
7289/**
7290 * VMLAUNCH/VMRESUME instruction execution worker.
7291 *
7292 * @returns Strict VBox status code.
7293 * @param pVCpu The cross context virtual CPU structure.
7294 * @param cbInstr The instruction length in bytes.
7295 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7296 * VMXINSTRID_VMRESUME).
7297 *
7298 * @remarks Common VMX instruction checks are already expected to by the caller,
7299 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7300 */
7301IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7302{
7303# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7304 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7305 return VINF_EM_RAW_EMULATE_INSTR;
7306# else
7307 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7308 || uInstrId == VMXINSTRID_VMRESUME);
7309 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7310
7311 /* Nested-guest intercept. */
7312 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7313 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7314
7315 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7316
7317 /*
7318 * Basic VM-entry checks.
7319 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7320 * The checks following that do not have to follow a specific order.
7321 *
7322 * See Intel spec. 26.1 "Basic VM-entry Checks".
7323 */
7324
7325 /* CPL. */
7326 if (pVCpu->iem.s.uCpl == 0)
7327 { /* likely */ }
7328 else
7329 {
7330 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7331 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7332 return iemRaiseGeneralProtectionFault0(pVCpu);
7333 }
7334
7335 /* Current VMCS valid. */
7336 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7337 { /* likely */ }
7338 else
7339 {
7340 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7341 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7342 iemVmxVmFailInvalid(pVCpu);
7343 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7344 return VINF_SUCCESS;
7345 }
7346
7347 /* Current VMCS is not a shadow VMCS. */
7348 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7349 { /* likely */ }
7350 else
7351 {
7352 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7353 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7354 iemVmxVmFailInvalid(pVCpu);
7355 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7356 return VINF_SUCCESS;
7357 }
7358
7359 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7360 * use block-by-STI here which is not quite correct. */
7361 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7362 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7363 { /* likely */ }
7364 else
7365 {
7366 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7367 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7368 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7369 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7370 return VINF_SUCCESS;
7371 }
7372
7373 if (uInstrId == VMXINSTRID_VMLAUNCH)
7374 {
7375 /* VMLAUNCH with non-clear VMCS. */
7376 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7377 { /* likely */ }
7378 else
7379 {
7380 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7381 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7382 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7383 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7384 return VINF_SUCCESS;
7385 }
7386 }
7387 else
7388 {
7389 /* VMRESUME with non-launched VMCS. */
7390 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7391 { /* likely */ }
7392 else
7393 {
7394 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7395 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7396 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7397 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7398 return VINF_SUCCESS;
7399 }
7400 }
7401
7402 /*
7403 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7404 * while entering VMX non-root mode. We do some of this while checking VM-execution
7405 * controls. The nested hypervisor should not make assumptions and cannot expect
7406 * predictable behavior if changes to these structures are made in guest memory while
7407 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7408 * modify them anyway as we cache them in host memory.
7409 *
7410 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7411 */
7412 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7413 Assert(pVmcs);
7414 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7415
7416 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7417 if (RT_SUCCESS(rc))
7418 {
7419 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7420 if (RT_SUCCESS(rc))
7421 {
7422 /*
7423 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7424 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7425 * ones that may occur during VM-entry below).
7426 */
7427 iemVmxVmentryInitReadOnlyFields(pVCpu);
7428
7429 /*
7430 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7431 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7432 * VM-exit when required.
7433 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7434 */
7435 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7436
7437 bool fPdpesMapped;
7438 rc = iemVmxVmentryCheckGuestState(pVCpu, &fPdpesMapped, pszInstr);
7439 if (RT_SUCCESS(rc))
7440 {
7441 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7442 if (RT_SUCCESS(rc))
7443 {
7444 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7445 if (RT_SUCCESS(rc))
7446 {
7447 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7448
7449 /* VMLAUNCH instruction must update the VMCS launch state. */
7450 if (uInstrId == VMXINSTRID_VMLAUNCH)
7451 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7452
7453 /* Perform the VMX transition (PGM updates). */
7454 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu, fPdpesMapped);
7455 if (rcStrict == VINF_SUCCESS)
7456 { /* likely */ }
7457 else if (RT_SUCCESS(rcStrict))
7458 {
7459 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7460 VBOXSTRICTRC_VAL(rcStrict)));
7461 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7462 }
7463 else
7464 {
7465 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7466 return rcStrict;
7467 }
7468
7469 /* Paranoia. */
7470 Assert(rcStrict == VINF_SUCCESS);
7471
7472 /* We've now entered nested-guest execution. */
7473 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7474
7475 /*
7476 * The priority of potential VM-exits during VM-entry is important.
7477 * The priorities of VM-exits and events are listed from highest
7478 * to lowest as follows:
7479 *
7480 * 1. Event injection.
7481 * 2. Trap on task-switch (T flag set in TSS).
7482 * 3. TPR below threshold / APIC-write.
7483 * 4. SMI, INIT.
7484 * 5. MTF exit.
7485 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7486 * 7. VMX-preemption timer.
7487 * 9. NMI-window exit.
7488 * 10. NMI injection.
7489 * 11. Interrupt-window exit.
7490 * 12. Virtual-interrupt injection.
7491 * 13. Interrupt injection.
7492 * 14. Process next instruction (fetch, decode, execute).
7493 */
7494
7495 /* Setup VMX-preemption timer. */
7496 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7497
7498 /* Setup monitor-trap flag. */
7499 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7500
7501 /* Setup NMI-window exiting. */
7502 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7503
7504 /* Setup interrupt-window exiting. */
7505 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7506
7507 /*
7508 * Inject any event that the nested hypervisor wants to inject.
7509 * Note! We cannot immediately perform the event injection here as we may have
7510 * pending PGM operations to perform due to switching page tables and/or
7511 * mode.
7512 */
7513 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7514
7515# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7516 /* Reschedule to IEM-only execution of the nested-guest. */
7517 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7518 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7519 if (rcSched != VINF_SUCCESS)
7520 iemSetPassUpStatus(pVCpu, rcSched);
7521# endif
7522
7523 /* Finally, done. */
7524 Log3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",
7525 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7526 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7527 pVCpu->cpum.GstCtx.msrEFER));
7528 return VINF_SUCCESS;
7529 }
7530 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7531 pVmcs->u64RoExitQual.u);
7532 }
7533 }
7534 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7535 pVmcs->u64RoExitQual.u);
7536 }
7537
7538 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7539 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7540 return VINF_SUCCESS;
7541 }
7542
7543 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7544 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7545 return VINF_SUCCESS;
7546# endif
7547}
7548
7549
7550/**
7551 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7552 * (causes a VM-exit) or not.
7553 *
7554 * @returns @c true if the instruction is intercepted, @c false otherwise.
7555 * @param pVCpu The cross context virtual CPU structure.
7556 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7557 * VMX_EXIT_WRMSR).
7558 * @param idMsr The MSR.
7559 */
7560IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7561{
7562 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7563 Assert( uExitReason == VMX_EXIT_RDMSR
7564 || uExitReason == VMX_EXIT_WRMSR);
7565
7566 /* Consult the MSR bitmap if the feature is supported. */
7567 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7568 Assert(pVmcs);
7569 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7570 {
7571 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7572 if (uExitReason == VMX_EXIT_RDMSR)
7573 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7574 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7575 }
7576
7577 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7578 return true;
7579}
7580
7581
7582/**
7583 * VMREAD instruction execution worker that does not perform any validation checks.
7584 *
7585 * Callers are expected to have performed the necessary checks and to ensure the
7586 * VMREAD will succeed.
7587 *
7588 * @param pVmcs Pointer to the virtual VMCS.
7589 * @param pu64Dst Where to write the VMCS value.
7590 * @param u64VmcsField The VMCS field.
7591 *
7592 * @remarks May be called with interrupts disabled.
7593 */
7594IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7595{
7596 VMXVMCSFIELD VmcsField;
7597 VmcsField.u = u64VmcsField;
7598 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7599 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7600 uint8_t const uWidthType = (uWidth << 2) | uType;
7601 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7602 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7603 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7604 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
7605 uWidth, uType, uIndex, uIndex));
7606 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7607
7608 /*
7609 * Read the VMCS component based on the field's effective width.
7610 *
7611 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7612 * indicates high bits (little endian).
7613 *
7614 * Note! The caller is responsible to trim the result and update registers
7615 * or memory locations are required. Here we just zero-extend to the largest
7616 * type (i.e. 64-bits).
7617 */
7618 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7619 uint8_t const *pbField = pbVmcs + offField;
7620 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7621 switch (uEffWidth)
7622 {
7623 case VMX_VMCSFIELD_WIDTH_64BIT:
7624 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7625 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7626 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7627 }
7628}
7629
7630
7631/**
7632 * VMREAD common (memory/register) instruction execution worker.
7633 *
7634 * @returns Strict VBox status code.
7635 * @param pVCpu The cross context virtual CPU structure.
7636 * @param cbInstr The instruction length in bytes.
7637 * @param pu64Dst Where to write the VMCS value (only updated when
7638 * VINF_SUCCESS is returned).
7639 * @param u64VmcsField The VMCS field.
7640 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7641 * NULL.
7642 */
7643IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7644 PCVMXVEXITINFO pExitInfo)
7645{
7646 /* Nested-guest intercept. */
7647 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7648 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7649 {
7650 if (pExitInfo)
7651 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7652 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7653 }
7654
7655 /* CPL. */
7656 if (pVCpu->iem.s.uCpl == 0)
7657 { /* likely */ }
7658 else
7659 {
7660 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7661 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7662 return iemRaiseGeneralProtectionFault0(pVCpu);
7663 }
7664
7665 /* VMCS pointer in root mode. */
7666 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7667 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7668 { /* likely */ }
7669 else
7670 {
7671 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7672 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7673 iemVmxVmFailInvalid(pVCpu);
7674 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7675 return VINF_SUCCESS;
7676 }
7677
7678 /* VMCS-link pointer in non-root mode. */
7679 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7680 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7681 { /* likely */ }
7682 else
7683 {
7684 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7685 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7686 iemVmxVmFailInvalid(pVCpu);
7687 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7688 return VINF_SUCCESS;
7689 }
7690
7691 /* Supported VMCS field. */
7692 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7693 { /* likely */ }
7694 else
7695 {
7696 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7697 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7698 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7699 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7700 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7701 return VINF_SUCCESS;
7702 }
7703
7704 /*
7705 * Reading from the current or shadow VMCS.
7706 */
7707 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7708 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7709 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7710 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7711 return VINF_SUCCESS;
7712}
7713
7714
7715/**
7716 * VMREAD (64-bit register) instruction execution worker.
7717 *
7718 * @returns Strict VBox status code.
7719 * @param pVCpu The cross context virtual CPU structure.
7720 * @param cbInstr The instruction length in bytes.
7721 * @param pu64Dst Where to store the VMCS field's value.
7722 * @param u64VmcsField The VMCS field.
7723 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7724 * NULL.
7725 */
7726IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7727 PCVMXVEXITINFO pExitInfo)
7728{
7729 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7730 if (rcStrict == VINF_SUCCESS)
7731 {
7732 iemVmxVmreadSuccess(pVCpu, cbInstr);
7733 return VINF_SUCCESS;
7734 }
7735
7736 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7737 return rcStrict;
7738}
7739
7740
7741/**
7742 * VMREAD (32-bit register) instruction execution worker.
7743 *
7744 * @returns Strict VBox status code.
7745 * @param pVCpu The cross context virtual CPU structure.
7746 * @param cbInstr The instruction length in bytes.
7747 * @param pu32Dst Where to store the VMCS field's value.
7748 * @param u32VmcsField The VMCS field.
7749 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7750 * NULL.
7751 */
7752IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7753 PCVMXVEXITINFO pExitInfo)
7754{
7755 uint64_t u64Dst;
7756 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7757 if (rcStrict == VINF_SUCCESS)
7758 {
7759 *pu32Dst = u64Dst;
7760 iemVmxVmreadSuccess(pVCpu, cbInstr);
7761 return VINF_SUCCESS;
7762 }
7763
7764 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7765 return rcStrict;
7766}
7767
7768
7769/**
7770 * VMREAD (memory) instruction execution worker.
7771 *
7772 * @returns Strict VBox status code.
7773 * @param pVCpu The cross context virtual CPU structure.
7774 * @param cbInstr The instruction length in bytes.
7775 * @param iEffSeg The effective segment register to use with @a u64Val.
7776 * Pass UINT8_MAX if it is a register access.
7777 * @param GCPtrDst The guest linear address to store the VMCS field's
7778 * value.
7779 * @param u64VmcsField The VMCS field.
7780 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7781 * NULL.
7782 */
7783IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7784 PCVMXVEXITINFO pExitInfo)
7785{
7786 uint64_t u64Dst;
7787 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7788 if (rcStrict == VINF_SUCCESS)
7789 {
7790 /*
7791 * Write the VMCS field's value to the location specified in guest-memory.
7792 */
7793 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7794 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7795 else
7796 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7797 if (rcStrict == VINF_SUCCESS)
7798 {
7799 iemVmxVmreadSuccess(pVCpu, cbInstr);
7800 return VINF_SUCCESS;
7801 }
7802
7803 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7804 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7805 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7806 return rcStrict;
7807 }
7808
7809 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7810 return rcStrict;
7811}
7812
7813
7814/**
7815 * VMWRITE instruction execution worker that does not perform any validation
7816 * checks.
7817 *
7818 * Callers are expected to have performed the necessary checks and to ensure the
7819 * VMWRITE will succeed.
7820 *
7821 * @param pVmcs Pointer to the virtual VMCS.
7822 * @param u64Val The value to write.
7823 * @param u64VmcsField The VMCS field.
7824 *
7825 * @remarks May be called with interrupts disabled.
7826 */
7827IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7828{
7829 VMXVMCSFIELD VmcsField;
7830 VmcsField.u = u64VmcsField;
7831 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7832 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7833 uint8_t const uWidthType = (uWidth << 2) | uType;
7834 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7835 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7836 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7837 Assert(offField < VMX_V_VMCS_SIZE);
7838 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7839
7840 /*
7841 * Write the VMCS component based on the field's effective width.
7842 *
7843 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7844 * indicates high bits (little endian).
7845 */
7846 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7847 uint8_t *pbField = pbVmcs + offField;
7848 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7849 switch (uEffWidth)
7850 {
7851 case VMX_VMCSFIELD_WIDTH_64BIT:
7852 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7853 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7854 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7855 }
7856}
7857
7858
7859/**
7860 * VMWRITE instruction execution worker.
7861 *
7862 * @returns Strict VBox status code.
7863 * @param pVCpu The cross context virtual CPU structure.
7864 * @param cbInstr The instruction length in bytes.
7865 * @param iEffSeg The effective segment register to use with @a u64Val.
7866 * Pass UINT8_MAX if it is a register access.
7867 * @param u64Val The value to write (or guest linear address to the
7868 * value), @a iEffSeg will indicate if it's a memory
7869 * operand.
7870 * @param u64VmcsField The VMCS field.
7871 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7872 * NULL.
7873 */
7874IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7875 PCVMXVEXITINFO pExitInfo)
7876{
7877 /* Nested-guest intercept. */
7878 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7879 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7880 {
7881 if (pExitInfo)
7882 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7883 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7884 }
7885
7886 /* CPL. */
7887 if (pVCpu->iem.s.uCpl == 0)
7888 { /* likely */ }
7889 else
7890 {
7891 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7892 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7893 return iemRaiseGeneralProtectionFault0(pVCpu);
7894 }
7895
7896 /* VMCS pointer in root mode. */
7897 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7898 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7899 { /* likely */ }
7900 else
7901 {
7902 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7903 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7904 iemVmxVmFailInvalid(pVCpu);
7905 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7906 return VINF_SUCCESS;
7907 }
7908
7909 /* VMCS-link pointer in non-root mode. */
7910 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7911 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7912 { /* likely */ }
7913 else
7914 {
7915 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7916 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7917 iemVmxVmFailInvalid(pVCpu);
7918 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7919 return VINF_SUCCESS;
7920 }
7921
7922 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7923 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7924 if (!fIsRegOperand)
7925 {
7926 /* Read the value from the specified guest memory location. */
7927 VBOXSTRICTRC rcStrict;
7928 RTGCPTR const GCPtrVal = u64Val;
7929 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7930 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7931 else
7932 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7933 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7934 {
7935 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7936 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7937 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7938 return rcStrict;
7939 }
7940 }
7941 else
7942 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7943
7944 /* Supported VMCS field. */
7945 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7946 { /* likely */ }
7947 else
7948 {
7949 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7950 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7951 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7952 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7953 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7954 return VINF_SUCCESS;
7955 }
7956
7957 /* Read-only VMCS field. */
7958 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7959 if ( !fIsFieldReadOnly
7960 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7961 { /* likely */ }
7962 else
7963 {
7964 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7965 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7966 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7967 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7968 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7969 return VINF_SUCCESS;
7970 }
7971
7972 /*
7973 * Write to the current or shadow VMCS.
7974 */
7975 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7976 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7977 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7978 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7979 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7980
7981 /* Notify HM that the VMCS content might have changed. */
7982 if (!fInVmxNonRootMode)
7983 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7984
7985 iemVmxVmSucceed(pVCpu);
7986 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7987 return VINF_SUCCESS;
7988}
7989
7990
7991/**
7992 * VMCLEAR instruction execution worker.
7993 *
7994 * @returns Strict VBox status code.
7995 * @param pVCpu The cross context virtual CPU structure.
7996 * @param cbInstr The instruction length in bytes.
7997 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7998 * @param GCPtrVmcs The linear address of the VMCS pointer.
7999 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8000 *
8001 * @remarks Common VMX instruction checks are already expected to by the caller,
8002 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8003 */
8004IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8005 PCVMXVEXITINFO pExitInfo)
8006{
8007 /* Nested-guest intercept. */
8008 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8009 {
8010 if (pExitInfo)
8011 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8012 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8013 }
8014
8015 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8016
8017 /* CPL. */
8018 if (pVCpu->iem.s.uCpl == 0)
8019 { /* likely */ }
8020 else
8021 {
8022 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8023 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8024 return iemRaiseGeneralProtectionFault0(pVCpu);
8025 }
8026
8027 /* Get the VMCS pointer from the location specified by the source memory operand. */
8028 RTGCPHYS GCPhysVmcs;
8029 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8030 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8031 { /* likely */ }
8032 else
8033 {
8034 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8035 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8036 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8037 return rcStrict;
8038 }
8039
8040 /* VMCS pointer alignment. */
8041 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8042 { /* likely */ }
8043 else
8044 {
8045 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8046 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8047 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8048 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8049 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8050 return VINF_SUCCESS;
8051 }
8052
8053 /* VMCS physical-address width limits. */
8054 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8055 { /* likely */ }
8056 else
8057 {
8058 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8059 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8060 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8061 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8062 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8063 return VINF_SUCCESS;
8064 }
8065
8066 /* VMCS is not the VMXON region. */
8067 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8068 { /* likely */ }
8069 else
8070 {
8071 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8072 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8073 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8074 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8075 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8076 return VINF_SUCCESS;
8077 }
8078
8079 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8080 restriction imposed by our implementation. */
8081 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8082 { /* likely */ }
8083 else
8084 {
8085 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8086 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8087 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8088 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8089 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8090 return VINF_SUCCESS;
8091 }
8092
8093 /*
8094 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8095 *
8096 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8097 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8098 * to 'clear'.
8099 */
8100 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8101 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8102 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8103 {
8104 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8105 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8106 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8107 }
8108 else
8109 {
8110 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8111 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8112 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8113 if (RT_FAILURE(rcStrict))
8114 return rcStrict;
8115 }
8116
8117 iemVmxVmSucceed(pVCpu);
8118 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8119 return VINF_SUCCESS;
8120}
8121
8122
8123/**
8124 * VMPTRST instruction execution worker.
8125 *
8126 * @returns Strict VBox status code.
8127 * @param pVCpu The cross context virtual CPU structure.
8128 * @param cbInstr The instruction length in bytes.
8129 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8130 * @param GCPtrVmcs The linear address of where to store the current VMCS
8131 * pointer.
8132 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8133 *
8134 * @remarks Common VMX instruction checks are already expected to by the caller,
8135 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8136 */
8137IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8138 PCVMXVEXITINFO pExitInfo)
8139{
8140 /* Nested-guest intercept. */
8141 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8142 {
8143 if (pExitInfo)
8144 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8145 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8146 }
8147
8148 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8149
8150 /* CPL. */
8151 if (pVCpu->iem.s.uCpl == 0)
8152 { /* likely */ }
8153 else
8154 {
8155 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8156 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8157 return iemRaiseGeneralProtectionFault0(pVCpu);
8158 }
8159
8160 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8161 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8162 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8163 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8164 {
8165 iemVmxVmSucceed(pVCpu);
8166 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8167 return rcStrict;
8168 }
8169
8170 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8171 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8172 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8173 return rcStrict;
8174}
8175
8176
8177/**
8178 * VMPTRLD instruction execution worker.
8179 *
8180 * @returns Strict VBox status code.
8181 * @param pVCpu The cross context virtual CPU structure.
8182 * @param cbInstr The instruction length in bytes.
8183 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8184 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8185 *
8186 * @remarks Common VMX instruction checks are already expected to by the caller,
8187 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8188 */
8189IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8190 PCVMXVEXITINFO pExitInfo)
8191{
8192 /* Nested-guest intercept. */
8193 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8194 {
8195 if (pExitInfo)
8196 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8197 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8198 }
8199
8200 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8201
8202 /* CPL. */
8203 if (pVCpu->iem.s.uCpl == 0)
8204 { /* likely */ }
8205 else
8206 {
8207 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8208 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8209 return iemRaiseGeneralProtectionFault0(pVCpu);
8210 }
8211
8212 /* Get the VMCS pointer from the location specified by the source memory operand. */
8213 RTGCPHYS GCPhysVmcs;
8214 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8215 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8216 { /* likely */ }
8217 else
8218 {
8219 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8220 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8221 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8222 return rcStrict;
8223 }
8224
8225 /* VMCS pointer alignment. */
8226 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8227 { /* likely */ }
8228 else
8229 {
8230 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8231 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8232 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8233 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8234 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8235 return VINF_SUCCESS;
8236 }
8237
8238 /* VMCS physical-address width limits. */
8239 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8240 { /* likely */ }
8241 else
8242 {
8243 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8244 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8245 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8246 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8247 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8248 return VINF_SUCCESS;
8249 }
8250
8251 /* VMCS is not the VMXON region. */
8252 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8253 { /* likely */ }
8254 else
8255 {
8256 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8257 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8258 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8259 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8260 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8261 return VINF_SUCCESS;
8262 }
8263
8264 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8265 restriction imposed by our implementation. */
8266 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8267 { /* likely */ }
8268 else
8269 {
8270 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8271 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8272 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8273 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8274 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8275 return VINF_SUCCESS;
8276 }
8277
8278 /* Read just the VMCS revision from the VMCS. */
8279 VMXVMCSREVID VmcsRevId;
8280 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8281 if (RT_SUCCESS(rc))
8282 { /* likely */ }
8283 else
8284 {
8285 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8286 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8287 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8288 return rc;
8289 }
8290
8291 /*
8292 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8293 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8294 */
8295 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8296 && ( !VmcsRevId.n.fIsShadowVmcs
8297 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8298 { /* likely */ }
8299 else
8300 {
8301 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8302 {
8303 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8304 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8305 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8306 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8307 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8308 return VINF_SUCCESS;
8309 }
8310
8311 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8312 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8313 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8314 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8315 return VINF_SUCCESS;
8316 }
8317
8318 /*
8319 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8320 * the cache of an existing, current VMCS back to guest memory before loading a new,
8321 * different current VMCS.
8322 */
8323 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8324 {
8325 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8326 {
8327 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8328 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8329 }
8330
8331 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8332 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8333 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8334 if (RT_SUCCESS(rc))
8335 {
8336 /* Notify HM that a new, current VMCS is loaded. */
8337 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8338 }
8339 else
8340 {
8341 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8342 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8343 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8344 return rc;
8345 }
8346 }
8347
8348 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8349 iemVmxVmSucceed(pVCpu);
8350 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8351 return VINF_SUCCESS;
8352}
8353
8354
8355/**
8356 * INVVPID instruction execution worker.
8357 *
8358 * @returns Strict VBox status code.
8359 * @param pVCpu The cross context virtual CPU structure.
8360 * @param cbInstr The instruction length in bytes.
8361 * @param iEffSeg The segment of the invvpid descriptor.
8362 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8363 * @param u64InvvpidType The invalidation type.
8364 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8365 * NULL.
8366 *
8367 * @remarks Common VMX instruction checks are already expected to by the caller,
8368 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8369 */
8370IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8371 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8372{
8373 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8374 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8375 return iemRaiseUndefinedOpcode(pVCpu);
8376
8377 /* Nested-guest intercept. */
8378 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8379 {
8380 if (pExitInfo)
8381 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8382 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8383 }
8384
8385 /* CPL. */
8386 if (pVCpu->iem.s.uCpl != 0)
8387 {
8388 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8389 return iemRaiseGeneralProtectionFault0(pVCpu);
8390 }
8391
8392 /*
8393 * Validate INVVPID invalidation type.
8394 *
8395 * The instruction specifies exactly ONE of the supported invalidation types.
8396 *
8397 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8398 * supported. In theory, it's possible for a CPU to not support flushing individual
8399 * addresses but all the other types or any other combination. We do not take any
8400 * shortcuts here by assuming the types we currently expose to the guest.
8401 */
8402 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8403 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8404 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8405 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8406 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8407 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8408 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8409 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8410 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8411 { /* likely */ }
8412 else
8413 {
8414 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8415 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8416 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8417 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8418 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8419 return VINF_SUCCESS;
8420 }
8421
8422 /*
8423 * Fetch the invvpid descriptor from guest memory.
8424 */
8425 RTUINT128U uDesc;
8426 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8427 if (rcStrict == VINF_SUCCESS)
8428 {
8429 /*
8430 * Validate the descriptor.
8431 */
8432 if (uDesc.s.Lo > 0xfff)
8433 {
8434 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8435 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8436 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8437 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8438 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8439 return VINF_SUCCESS;
8440 }
8441
8442 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8443 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8444 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8445 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8446 switch (u64InvvpidType)
8447 {
8448 case VMXTLBFLUSHVPID_INDIV_ADDR:
8449 {
8450 if (uVpid != 0)
8451 {
8452 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8453 {
8454 /* Invalidate mappings for the linear address tagged with VPID. */
8455 /** @todo PGM support for VPID? Currently just flush everything. */
8456 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8457 iemVmxVmSucceed(pVCpu);
8458 }
8459 else
8460 {
8461 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8462 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8463 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8464 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8465 }
8466 }
8467 else
8468 {
8469 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8470 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8471 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8472 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8473 }
8474 break;
8475 }
8476
8477 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8478 {
8479 if (uVpid != 0)
8480 {
8481 /* Invalidate all mappings with VPID. */
8482 /** @todo PGM support for VPID? Currently just flush everything. */
8483 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8484 iemVmxVmSucceed(pVCpu);
8485 }
8486 else
8487 {
8488 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8489 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8490 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8491 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8492 }
8493 break;
8494 }
8495
8496 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8497 {
8498 /* Invalidate all mappings with non-zero VPIDs. */
8499 /** @todo PGM support for VPID? Currently just flush everything. */
8500 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8501 iemVmxVmSucceed(pVCpu);
8502 break;
8503 }
8504
8505 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8506 {
8507 if (uVpid != 0)
8508 {
8509 /* Invalidate all mappings with VPID except global translations. */
8510 /** @todo PGM support for VPID? Currently just flush everything. */
8511 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8512 iemVmxVmSucceed(pVCpu);
8513 }
8514 else
8515 {
8516 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8517 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8518 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8519 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8520 }
8521 break;
8522 }
8523 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8524 }
8525 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8526 }
8527 return rcStrict;
8528}
8529
8530
8531/**
8532 * VMXON instruction execution worker.
8533 *
8534 * @returns Strict VBox status code.
8535 * @param pVCpu The cross context virtual CPU structure.
8536 * @param cbInstr The instruction length in bytes.
8537 * @param iEffSeg The effective segment register to use with @a
8538 * GCPtrVmxon.
8539 * @param GCPtrVmxon The linear address of the VMXON pointer.
8540 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8541 *
8542 * @remarks Common VMX instruction checks are already expected to by the caller,
8543 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8544 */
8545IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8546 PCVMXVEXITINFO pExitInfo)
8547{
8548 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8549 {
8550 /* CPL. */
8551 if (pVCpu->iem.s.uCpl == 0)
8552 { /* likely */ }
8553 else
8554 {
8555 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8556 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8557 return iemRaiseGeneralProtectionFault0(pVCpu);
8558 }
8559
8560 /* A20M (A20 Masked) mode. */
8561 if (PGMPhysIsA20Enabled(pVCpu))
8562 { /* likely */ }
8563 else
8564 {
8565 Log(("vmxon: A20M mode -> #GP(0)\n"));
8566 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8567 return iemRaiseGeneralProtectionFault0(pVCpu);
8568 }
8569
8570 /* CR0. */
8571 {
8572 /* CR0 MB1 bits. */
8573 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8574 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8575 { /* likely */ }
8576 else
8577 {
8578 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8579 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8580 return iemRaiseGeneralProtectionFault0(pVCpu);
8581 }
8582
8583 /* CR0 MBZ bits. */
8584 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8585 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8586 { /* likely */ }
8587 else
8588 {
8589 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8590 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8591 return iemRaiseGeneralProtectionFault0(pVCpu);
8592 }
8593 }
8594
8595 /* CR4. */
8596 {
8597 /* CR4 MB1 bits. */
8598 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8599 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8600 { /* likely */ }
8601 else
8602 {
8603 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8604 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8605 return iemRaiseGeneralProtectionFault0(pVCpu);
8606 }
8607
8608 /* CR4 MBZ bits. */
8609 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8610 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8611 { /* likely */ }
8612 else
8613 {
8614 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8615 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8616 return iemRaiseGeneralProtectionFault0(pVCpu);
8617 }
8618 }
8619
8620 /* Feature control MSR's LOCK and VMXON bits. */
8621 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
8622 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8623 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8624 { /* likely */ }
8625 else
8626 {
8627 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8628 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8629 return iemRaiseGeneralProtectionFault0(pVCpu);
8630 }
8631
8632 /* Get the VMXON pointer from the location specified by the source memory operand. */
8633 RTGCPHYS GCPhysVmxon;
8634 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8635 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8636 { /* likely */ }
8637 else
8638 {
8639 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8640 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8641 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8642 return rcStrict;
8643 }
8644
8645 /* VMXON region pointer alignment. */
8646 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8647 { /* likely */ }
8648 else
8649 {
8650 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8651 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8652 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8653 iemVmxVmFailInvalid(pVCpu);
8654 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8655 return VINF_SUCCESS;
8656 }
8657
8658 /* VMXON physical-address width limits. */
8659 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8660 { /* likely */ }
8661 else
8662 {
8663 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8664 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8665 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8666 iemVmxVmFailInvalid(pVCpu);
8667 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8668 return VINF_SUCCESS;
8669 }
8670
8671 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8672 restriction imposed by our implementation. */
8673 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8674 { /* likely */ }
8675 else
8676 {
8677 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8678 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8679 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8680 iemVmxVmFailInvalid(pVCpu);
8681 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8682 return VINF_SUCCESS;
8683 }
8684
8685 /* Read the VMCS revision ID from the VMXON region. */
8686 VMXVMCSREVID VmcsRevId;
8687 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8688 if (RT_SUCCESS(rc))
8689 { /* likely */ }
8690 else
8691 {
8692 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8693 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8694 return rc;
8695 }
8696
8697 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8698 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8699 { /* likely */ }
8700 else
8701 {
8702 /* Revision ID mismatch. */
8703 if (!VmcsRevId.n.fIsShadowVmcs)
8704 {
8705 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8706 VmcsRevId.n.u31RevisionId));
8707 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8708 iemVmxVmFailInvalid(pVCpu);
8709 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8710 return VINF_SUCCESS;
8711 }
8712
8713 /* Shadow VMCS disallowed. */
8714 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8715 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8716 iemVmxVmFailInvalid(pVCpu);
8717 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8718 return VINF_SUCCESS;
8719 }
8720
8721 /*
8722 * Record that we're in VMX operation, block INIT, block and disable A20M.
8723 */
8724 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8725 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8726 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8727
8728 /* Clear address-range monitoring. */
8729 EMMonitorWaitClear(pVCpu);
8730 /** @todo NSTVMX: Intel PT. */
8731
8732 iemVmxVmSucceed(pVCpu);
8733 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8734 return VINF_SUCCESS;
8735 }
8736 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8737 {
8738 /* Nested-guest intercept. */
8739 if (pExitInfo)
8740 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8741 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8742 }
8743
8744 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8745
8746 /* CPL. */
8747 if (pVCpu->iem.s.uCpl > 0)
8748 {
8749 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8750 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8751 return iemRaiseGeneralProtectionFault0(pVCpu);
8752 }
8753
8754 /* VMXON when already in VMX root mode. */
8755 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8756 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8757 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8758 return VINF_SUCCESS;
8759}
8760
8761
8762/**
8763 * Implements 'VMXOFF'.
8764 *
8765 * @remarks Common VMX instruction checks are already expected to by the caller,
8766 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8767 */
8768IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8769{
8770 /* Nested-guest intercept. */
8771 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8772 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8773
8774 /* CPL. */
8775 if (pVCpu->iem.s.uCpl == 0)
8776 { /* likely */ }
8777 else
8778 {
8779 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8780 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8781 return iemRaiseGeneralProtectionFault0(pVCpu);
8782 }
8783
8784 /* Dual monitor treatment of SMIs and SMM. */
8785 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8786 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8787 { /* likely */ }
8788 else
8789 {
8790 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8791 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8792 return VINF_SUCCESS;
8793 }
8794
8795 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8796 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8797 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8798
8799 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8800 { /** @todo NSTVMX: Unblock SMI. */ }
8801
8802 EMMonitorWaitClear(pVCpu);
8803 /** @todo NSTVMX: Unblock and enable A20M. */
8804
8805 iemVmxVmSucceed(pVCpu);
8806 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8807 return VINF_SUCCESS;
8808}
8809
8810
8811/**
8812 * Implements 'VMXON'.
8813 */
8814IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8815{
8816 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8817}
8818
8819
8820/**
8821 * Implements 'VMLAUNCH'.
8822 */
8823IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8824{
8825 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8826}
8827
8828
8829/**
8830 * Implements 'VMRESUME'.
8831 */
8832IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8833{
8834 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8835}
8836
8837
8838/**
8839 * Implements 'VMPTRLD'.
8840 */
8841IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8842{
8843 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8844}
8845
8846
8847/**
8848 * Implements 'VMPTRST'.
8849 */
8850IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8851{
8852 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8853}
8854
8855
8856/**
8857 * Implements 'VMCLEAR'.
8858 */
8859IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8860{
8861 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8862}
8863
8864
8865/**
8866 * Implements 'VMWRITE' register.
8867 */
8868IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8869{
8870 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8871}
8872
8873
8874/**
8875 * Implements 'VMWRITE' memory.
8876 */
8877IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8878{
8879 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8880}
8881
8882
8883/**
8884 * Implements 'VMREAD' register (64-bit).
8885 */
8886IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8887{
8888 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8889}
8890
8891
8892/**
8893 * Implements 'VMREAD' register (32-bit).
8894 */
8895IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8896{
8897 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8898}
8899
8900
8901/**
8902 * Implements 'VMREAD' memory, 64-bit register.
8903 */
8904IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8905{
8906 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8907}
8908
8909
8910/**
8911 * Implements 'VMREAD' memory, 32-bit register.
8912 */
8913IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8914{
8915 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8916}
8917
8918
8919/**
8920 * Implements 'INVVPID'.
8921 */
8922IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8923{
8924 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8925}
8926
8927
8928/**
8929 * Implements VMX's implementation of PAUSE.
8930 */
8931IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8932{
8933 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8934 {
8935 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8936 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8937 return rcStrict;
8938 }
8939
8940 /*
8941 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8942 * a VM-exit, the instruction operates normally.
8943 */
8944 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8945 return VINF_SUCCESS;
8946}
8947
8948#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8949
8950
8951/**
8952 * Implements 'VMCALL'.
8953 */
8954IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8955{
8956#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8957 /* Nested-guest intercept. */
8958 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8959 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8960#endif
8961
8962 /* Join forces with vmmcall. */
8963 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8964}
8965
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