VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 92500

Last change on this file since 92500 was 92493, checked in by vboxsync, 3 years ago

VMM: Nested VMX: bugref:10092 Purge VINF_PGM_CHANGE_MODE, no longer used.
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File size: 358.2 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 92493 2021-11-18 14:01:56Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_EPT_VIOLATION
177 * VMX_EXIT_EPT_MISCONFIG
178 * VMX_EXIT_INVEPT
179 * VMX_EXIT_RDRAND
180 * VMX_EXIT_VMFUNC
181 * VMX_EXIT_ENCLS
182 * VMX_EXIT_RDSEED
183 * VMX_EXIT_PML_FULL
184 * VMX_EXIT_XSAVES
185 * VMX_EXIT_XRSTORS
186 */
187/**
188 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
189 *
190 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
191 * second dimension is the Index, see VMXVMCSFIELD.
192 */
193uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
194{
195 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
196 {
197 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
198 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
199 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
200 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
201 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 27 */ UINT16_MAX,
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 26-27 */ UINT16_MAX, UINT16_MAX
227 },
228 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
233 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
234 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
235 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
236 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
237 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
239 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
240 },
241 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
242 {
243 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
244 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
245 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
246 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
247 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
248 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
249 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
250 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
251 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
252 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
253 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
254 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
255 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
256 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
257 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
258 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
259 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
260 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
261 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
262 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
263 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
264 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
265 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
266 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
267 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
268 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
269 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
270 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
271 },
272 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
273 {
274 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
275 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
276 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
277 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
278 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
279 },
280 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
281 {
282 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
283 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
284 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
285 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
286 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
287 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
288 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
289 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
290 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
291 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
292 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
293 /* 11 */ UINT16_MAX,
294 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
295 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
296 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
297 },
298 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
299 {
300 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
301 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
302 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
303 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
304 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
307 },
308 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
309 {
310 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
311 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
312 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
313 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
314 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
315 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
316 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
317 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
318 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
319 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
320 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
321 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
322 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
323 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
324 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
325 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
326 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
327 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
328 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
329 /* 26-27 */ UINT16_MAX, UINT16_MAX
330 },
331 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
332 {
333 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
334 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
335 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
336 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
337 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
338 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
339 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
340 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
341 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
342 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
343 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
344 },
345 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
346 {
347 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
348 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
349 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
350 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
351 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
352 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
353 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
354 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
355 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
356 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
357 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
358 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
359 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
360 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
361 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
362 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
363 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
364 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
365 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
366 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
367 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
368 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
369 /* 22 */ UINT16_MAX,
370 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
371 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
376 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
377 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
378 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
379 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
380 },
381 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
382 {
383 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
384 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
385 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
386 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
387 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
388 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
389 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
390 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
391 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
392 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
393 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
394 },
395 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
396 {
397 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
398 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
399 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
400 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
401 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
402 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
403 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
404 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
405 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
406 },
407 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
408 {
409 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
410 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
411 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
412 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
413 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
414 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
415 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
416 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
417 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
418 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
419 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
420 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
421 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
422 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
423 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
424 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
425 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
426 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
427 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
428 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
429 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
430 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
431 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
432 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
433 },
434 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
435 {
436 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
437 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
438 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
439 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
440 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
441 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
442 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
443 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
444 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
445 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
446 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
447 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
448 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
449 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
450 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
451 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
452 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
453 }
454};
455
456
457/**
458 * Gets a host selector from the VMCS.
459 *
460 * @param pVmcs Pointer to the virtual VMCS.
461 * @param iSelReg The index of the segment register (X86_SREG_XXX).
462 */
463DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
464{
465 Assert(iSegReg < X86_SREG_COUNT);
466 RTSEL HostSel;
467 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
468 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
469 uint8_t const uWidthType = (uWidth << 2) | uType;
470 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
471 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
472 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
473 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
474 uint8_t const *pbField = pbVmcs + offField;
475 HostSel = *(uint16_t *)pbField;
476 return HostSel;
477}
478
479
480/**
481 * Sets a guest segment register in the VMCS.
482 *
483 * @param pVmcs Pointer to the virtual VMCS.
484 * @param iSegReg The index of the segment register (X86_SREG_XXX).
485 * @param pSelReg Pointer to the segment register.
486 */
487IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
488{
489 Assert(pSelReg);
490 Assert(iSegReg < X86_SREG_COUNT);
491
492 /* Selector. */
493 {
494 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
495 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
496 uint8_t const uWidthType = (uWidth << 2) | uType;
497 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
498 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
499 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
500 uint8_t *pbVmcs = (uint8_t *)pVmcs;
501 uint8_t *pbField = pbVmcs + offField;
502 *(uint16_t *)pbField = pSelReg->Sel;
503 }
504
505 /* Limit. */
506 {
507 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
508 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
509 uint8_t const uWidthType = (uWidth << 2) | uType;
510 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
511 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
512 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
513 uint8_t *pbVmcs = (uint8_t *)pVmcs;
514 uint8_t *pbField = pbVmcs + offField;
515 *(uint32_t *)pbField = pSelReg->u32Limit;
516 }
517
518 /* Base. */
519 {
520 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
521 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
522 uint8_t const uWidthType = (uWidth << 2) | uType;
523 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
524 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
525 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
526 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
527 uint8_t const *pbField = pbVmcs + offField;
528 *(uint64_t *)pbField = pSelReg->u64Base;
529 }
530
531 /* Attributes. */
532 {
533 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
534 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
535 | X86DESCATTR_UNUSABLE;
536 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
537 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
538 uint8_t const uWidthType = (uWidth << 2) | uType;
539 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
540 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
541 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
542 uint8_t *pbVmcs = (uint8_t *)pVmcs;
543 uint8_t *pbField = pbVmcs + offField;
544 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
545 }
546}
547
548
549/**
550 * Gets a guest segment register from the VMCS.
551 *
552 * @returns VBox status code.
553 * @param pVmcs Pointer to the virtual VMCS.
554 * @param iSegReg The index of the segment register (X86_SREG_XXX).
555 * @param pSelReg Where to store the segment register (only updated when
556 * VINF_SUCCESS is returned).
557 *
558 * @remarks Warning! This does not validate the contents of the retrieved segment
559 * register.
560 */
561IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
562{
563 Assert(pSelReg);
564 Assert(iSegReg < X86_SREG_COUNT);
565
566 /* Selector. */
567 uint16_t u16Sel;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u16Sel = *(uint16_t *)pbField;
578 }
579
580 /* Limit. */
581 uint32_t u32Limit;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u32Limit = *(uint32_t *)pbField;
592 }
593
594 /* Base. */
595 uint64_t u64Base;
596 {
597 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
598 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
599 uint8_t const uWidthType = (uWidth << 2) | uType;
600 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
601 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
602 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
603 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
604 uint8_t const *pbField = pbVmcs + offField;
605 u64Base = *(uint64_t *)pbField;
606 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
607 }
608
609 /* Attributes. */
610 uint32_t u32Attr;
611 {
612 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
613 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
614 uint8_t const uWidthType = (uWidth << 2) | uType;
615 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
616 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
617 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
618 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
619 uint8_t const *pbField = pbVmcs + offField;
620 u32Attr = *(uint32_t *)pbField;
621 }
622
623 pSelReg->Sel = u16Sel;
624 pSelReg->ValidSel = u16Sel;
625 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
626 pSelReg->u32Limit = u32Limit;
627 pSelReg->u64Base = u64Base;
628 pSelReg->Attr.u = u32Attr;
629 return VINF_SUCCESS;
630}
631
632
633/**
634 * Converts an IEM exception event type to a VMX event type.
635 *
636 * @returns The VMX event type.
637 * @param uVector The interrupt / exception vector.
638 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
639 */
640DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
641{
642 /* Paranoia (callers may use these interchangeably). */
643 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
644 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
645 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
646 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
647 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
648 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
649 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
650 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
651 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
652 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
653 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
654 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
655
656 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
657 {
658 if (uVector == X86_XCPT_NMI)
659 return VMX_EXIT_INT_INFO_TYPE_NMI;
660 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
661 }
662
663 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
664 {
665 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
666 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
667 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
668 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
669 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
670 }
671
672 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
673 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
674}
675
676
677/**
678 * Sets the Exit qualification VMCS field.
679 *
680 * @param pVCpu The cross context virtual CPU structure.
681 * @param u64ExitQual The Exit qualification.
682 */
683DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
684{
685 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
686}
687
688
689/**
690 * Sets the VM-exit interruption information field.
691 *
692 * @param pVCpu The cross context virtual CPU structure.
693 * @param uExitIntInfo The VM-exit interruption information.
694 */
695DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
696{
697 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
698}
699
700
701/**
702 * Sets the VM-exit interruption error code.
703 *
704 * @param pVCpu The cross context virtual CPU structure.
705 * @param uErrCode The error code.
706 */
707DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
708{
709 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
710}
711
712
713/**
714 * Sets the IDT-vectoring information field.
715 *
716 * @param pVCpu The cross context virtual CPU structure.
717 * @param uIdtVectorInfo The IDT-vectoring information.
718 */
719DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
720{
721 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
722}
723
724
725/**
726 * Sets the IDT-vectoring error code field.
727 *
728 * @param pVCpu The cross context virtual CPU structure.
729 * @param uErrCode The error code.
730 */
731DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
732{
733 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
734}
735
736
737/**
738 * Sets the VM-exit guest-linear address VMCS field.
739 *
740 * @param pVCpu The cross context virtual CPU structure.
741 * @param uGuestLinearAddr The VM-exit guest-linear address.
742 */
743DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
744{
745 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
746}
747
748
749/**
750 * Sets the VM-exit guest-physical address VMCS field.
751 *
752 * @param pVCpu The cross context virtual CPU structure.
753 * @param uGuestPhysAddr The VM-exit guest-physical address.
754 */
755DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
756{
757 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
758}
759
760
761/**
762 * Sets the VM-exit instruction length VMCS field.
763 *
764 * @param pVCpu The cross context virtual CPU structure.
765 * @param cbInstr The VM-exit instruction length in bytes.
766 *
767 * @remarks Callers may clear this field to 0. Hence, this function does not check
768 * the validity of the instruction length.
769 */
770DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
771{
772 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
773}
774
775
776/**
777 * Sets the VM-exit instruction info. VMCS field.
778 *
779 * @param pVCpu The cross context virtual CPU structure.
780 * @param uExitInstrInfo The VM-exit instruction information.
781 */
782DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
783{
784 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
785}
786
787
788/**
789 * Sets the guest pending-debug exceptions field.
790 *
791 * @param pVCpu The cross context virtual CPU structure.
792 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
793 */
794DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
795{
796 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
797 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
798}
799
800
801/**
802 * Implements VMSucceed for VMX instruction success.
803 *
804 * @param pVCpu The cross context virtual CPU structure.
805 */
806DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
807{
808 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
809}
810
811
812/**
813 * Implements VMFailInvalid for VMX instruction failure.
814 *
815 * @param pVCpu The cross context virtual CPU structure.
816 */
817DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
818{
819 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
820}
821
822
823/**
824 * Implements VMFail for VMX instruction failure.
825 *
826 * @param pVCpu The cross context virtual CPU structure.
827 * @param enmInsErr The VM instruction error.
828 */
829DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
830{
831 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
832}
833
834
835/**
836 * Checks if the given auto-load/store MSR area count is valid for the
837 * implementation.
838 *
839 * @returns @c true if it's within the valid limit, @c false otherwise.
840 * @param pVCpu The cross context virtual CPU structure.
841 * @param uMsrCount The MSR area count to check.
842 */
843DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
844{
845 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
846 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
847 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
848 if (uMsrCount <= cMaxSupportedMsrs)
849 return true;
850 return false;
851}
852
853
854/**
855 * Flushes the current VMCS contents back to guest memory.
856 *
857 * @returns VBox status code.
858 * @param pVCpu The cross context virtual CPU structure.
859 */
860DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
861{
862 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
863 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
864 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
865 return rc;
866}
867
868
869/**
870 * Populates the current VMCS contents from guest memory.
871 *
872 * @returns VBox status code.
873 * @param pVCpu The cross context virtual CPU structure.
874 */
875DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
876{
877 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
879 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
880 return rc;
881}
882
883
884/**
885 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
886 *
887 * @param pVCpu The cross context virtual CPU structure.
888 */
889DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
890{
891 iemVmxVmSucceed(pVCpu);
892 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
893}
894
895
896/**
897 * Gets the instruction diagnostic for segment base checks during VM-entry of a
898 * nested-guest.
899 *
900 * @param iSegReg The segment index (X86_SREG_XXX).
901 */
902IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
903{
904 switch (iSegReg)
905 {
906 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
907 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
908 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
909 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
910 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
911 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
912 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
913 }
914}
915
916
917/**
918 * Gets the instruction diagnostic for segment base checks during VM-entry of a
919 * nested-guest that is in Virtual-8086 mode.
920 *
921 * @param iSegReg The segment index (X86_SREG_XXX).
922 */
923IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
924{
925 switch (iSegReg)
926 {
927 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
928 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
929 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
930 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
931 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
932 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
933 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
934 }
935}
936
937
938/**
939 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
940 * nested-guest that is in Virtual-8086 mode.
941 *
942 * @param iSegReg The segment index (X86_SREG_XXX).
943 */
944IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
945{
946 switch (iSegReg)
947 {
948 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
949 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
950 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
951 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
952 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
953 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
954 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
955 }
956}
957
958
959/**
960 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
961 * nested-guest that is in Virtual-8086 mode.
962 *
963 * @param iSegReg The segment index (X86_SREG_XXX).
964 */
965IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
966{
967 switch (iSegReg)
968 {
969 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
970 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
971 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
972 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
973 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
974 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
975 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
976 }
977}
978
979
980/**
981 * Gets the instruction diagnostic for segment attributes reserved bits failure
982 * during VM-entry of a nested-guest.
983 *
984 * @param iSegReg The segment index (X86_SREG_XXX).
985 */
986IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
987{
988 switch (iSegReg)
989 {
990 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
991 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
992 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
993 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
994 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
995 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
996 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
997 }
998}
999
1000
1001/**
1002 * Gets the instruction diagnostic for segment attributes descriptor-type
1003 * (code/segment or system) failure during VM-entry of a nested-guest.
1004 *
1005 * @param iSegReg The segment index (X86_SREG_XXX).
1006 */
1007IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1008{
1009 switch (iSegReg)
1010 {
1011 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1012 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1013 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1014 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1015 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1016 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1017 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1018 }
1019}
1020
1021
1022/**
1023 * Gets the instruction diagnostic for segment attributes descriptor-type
1024 * (code/segment or system) failure during VM-entry of a nested-guest.
1025 *
1026 * @param iSegReg The segment index (X86_SREG_XXX).
1027 */
1028IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1029{
1030 switch (iSegReg)
1031 {
1032 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1033 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1034 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1035 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1036 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1037 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1038 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1039 }
1040}
1041
1042
1043/**
1044 * Gets the instruction diagnostic for segment attribute granularity failure during
1045 * VM-entry of a nested-guest.
1046 *
1047 * @param iSegReg The segment index (X86_SREG_XXX).
1048 */
1049IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1050{
1051 switch (iSegReg)
1052 {
1053 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1054 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1055 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1056 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1057 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1058 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1059 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1060 }
1061}
1062
1063/**
1064 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1065 * VM-entry of a nested-guest.
1066 *
1067 * @param iSegReg The segment index (X86_SREG_XXX).
1068 */
1069IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1070{
1071 switch (iSegReg)
1072 {
1073 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1074 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1075 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1076 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1077 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1078 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1079 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1080 }
1081}
1082
1083
1084/**
1085 * Gets the instruction diagnostic for segment attribute type accessed failure
1086 * during VM-entry of a nested-guest.
1087 *
1088 * @param iSegReg The segment index (X86_SREG_XXX).
1089 */
1090IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1091{
1092 switch (iSegReg)
1093 {
1094 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1095 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1096 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1097 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1098 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1099 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1100 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1101 }
1102}
1103
1104
1105/**
1106 * Saves the guest control registers, debug registers and some MSRs are part of
1107 * VM-exit.
1108 *
1109 * @param pVCpu The cross context virtual CPU structure.
1110 */
1111IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1112{
1113 /*
1114 * Saves the guest control registers, debug registers and some MSRs.
1115 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1116 */
1117 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1118
1119 /* Save control registers. */
1120 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1121 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1122 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1123
1124 /* Save SYSENTER CS, ESP, EIP. */
1125 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1126 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1127 {
1128 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1129 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1130 }
1131 else
1132 {
1133 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1134 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1135 }
1136
1137 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1138 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1139 {
1140 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1141 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1142 }
1143
1144 /* Save PAT MSR. */
1145 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1146 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1147
1148 /* Save EFER MSR. */
1149 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1150 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1151
1152 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1153 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1154
1155 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1156}
1157
1158
1159/**
1160 * Saves the guest force-flags in preparation of entering the nested-guest.
1161 *
1162 * @param pVCpu The cross context virtual CPU structure.
1163 */
1164IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1165{
1166 /* We shouldn't be called multiple times during VM-entry. */
1167 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1168
1169 /* MTF should not be set outside VMX non-root mode. */
1170 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1171
1172 /*
1173 * Preserve the required force-flags.
1174 *
1175 * We cache and clear force-flags that would affect the execution of the
1176 * nested-guest. Cached flags are then restored while returning to the guest
1177 * if necessary.
1178 *
1179 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1180 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1181 * instruction. Interrupt inhibition for any nested-guest instruction
1182 * is supplied by the guest-interruptibility state VMCS field and will
1183 * be set up as part of loading the guest state.
1184 *
1185 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1186 * successful VM-entry (due to invalid guest-state) need to continue
1187 * blocking NMIs if it was in effect before VM-entry.
1188 *
1189 * - MTF need not be preserved as it's used only in VMX non-root mode and
1190 * is supplied through the VM-execution controls.
1191 *
1192 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1193 * we will be able to generate interrupts that may cause VM-exits for
1194 * the nested-guest.
1195 */
1196 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1197}
1198
1199
1200/**
1201 * Restores the guest force-flags in preparation of exiting the nested-guest.
1202 *
1203 * @param pVCpu The cross context virtual CPU structure.
1204 */
1205IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1206{
1207 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1208 {
1209 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1210 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1211 }
1212}
1213
1214
1215/**
1216 * Performs the VMX transition to/from VMX non-root mode.
1217 *
1218 * @param pVCpu The cross context virtual CPU structure.
1219 * @param fPdpesMapped Whether the PAE PDPTEs (and PDPT) have been mapped.
1220*/
1221IEM_STATIC int iemVmxTransition(PVMCPUCC pVCpu, bool fPdpesMapped)
1222{
1223 /*
1224 * Inform PGM about paging mode changes.
1225 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1226 * see comment in iemMemPageTranslateAndCheckAccess().
1227 */
1228 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1229 AssertRCReturn(rc, rc);
1230
1231 /* Inform CPUM (recompiler), can later be removed. */
1232 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1233
1234 /*
1235 * Flush the TLB with new CR3. This is required in case the PGM mode change
1236 * above doesn't actually change anything.
1237 */
1238 if (rc == VINF_SUCCESS)
1239 {
1240 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* fGlobal */, fPdpesMapped);
1241 AssertRCReturn(rc, rc);
1242 }
1243
1244 /* Re-initialize IEM cache/state after the drastic mode switch. */
1245 iemReInitExec(pVCpu);
1246 return rc;
1247}
1248
1249
1250/**
1251 * Calculates the current VMX-preemption timer value.
1252 *
1253 * @returns The current VMX-preemption timer value.
1254 * @param pVCpu The cross context virtual CPU structure.
1255 */
1256IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1257{
1258 /*
1259 * Assume the following:
1260 * PreemptTimerShift = 5
1261 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1262 * EntryTick = 50000 (TSC at time of VM-entry)
1263 *
1264 * CurTick Delta PreemptTimerVal
1265 * ----------------------------------
1266 * 60000 10000 2
1267 * 80000 30000 1
1268 * 90000 40000 0 -> VM-exit.
1269 *
1270 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1271 * The saved VMX-preemption timer value is calculated as follows:
1272 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1273 * E.g.:
1274 * Delta = 10000
1275 * Tmp = 10000 / (2 * 10000) = 0.5
1276 * NewPt = 2 - 0.5 = 2
1277 * Delta = 30000
1278 * Tmp = 30000 / (2 * 10000) = 1.5
1279 * NewPt = 2 - 1.5 = 1
1280 * Delta = 40000
1281 * Tmp = 40000 / 20000 = 2
1282 * NewPt = 2 - 2 = 0
1283 */
1284 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1285 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1286 if (uVmcsPreemptVal > 0)
1287 {
1288 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1289 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1290 uint64_t const uDelta = uCurTick - uEntryTick;
1291 uint32_t const uPreemptTimer = uVmcsPreemptVal
1292 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1293 return uPreemptTimer;
1294 }
1295 return 0;
1296}
1297
1298
1299/**
1300 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1301 *
1302 * @param pVCpu The cross context virtual CPU structure.
1303 */
1304IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1305{
1306 /*
1307 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1308 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1309 */
1310 /* CS, SS, ES, DS, FS, GS. */
1311 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1312 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1313 {
1314 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1315 if (!pSelReg->Attr.n.u1Unusable)
1316 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1317 else
1318 {
1319 /*
1320 * For unusable segments the attributes are undefined except for CS and SS.
1321 * For the rest we don't bother preserving anything but the unusable bit.
1322 */
1323 switch (iSegReg)
1324 {
1325 case X86_SREG_CS:
1326 pVmcs->GuestCs = pSelReg->Sel;
1327 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1328 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1329 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1330 | X86DESCATTR_UNUSABLE);
1331 break;
1332
1333 case X86_SREG_SS:
1334 pVmcs->GuestSs = pSelReg->Sel;
1335 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1336 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1337 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1338 break;
1339
1340 case X86_SREG_DS:
1341 pVmcs->GuestDs = pSelReg->Sel;
1342 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1343 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1344 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1345 break;
1346
1347 case X86_SREG_ES:
1348 pVmcs->GuestEs = pSelReg->Sel;
1349 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1350 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1351 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1352 break;
1353
1354 case X86_SREG_FS:
1355 pVmcs->GuestFs = pSelReg->Sel;
1356 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1357 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1358 break;
1359
1360 case X86_SREG_GS:
1361 pVmcs->GuestGs = pSelReg->Sel;
1362 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1363 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1364 break;
1365 }
1366 }
1367 }
1368
1369 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1370 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1371 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1372 | X86DESCATTR_UNUSABLE;
1373 /* LDTR. */
1374 {
1375 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1376 pVmcs->GuestLdtr = pSelReg->Sel;
1377 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1378 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1379 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1380 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1381 }
1382
1383 /* TR. */
1384 {
1385 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1386 pVmcs->GuestTr = pSelReg->Sel;
1387 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1388 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1389 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1390 }
1391
1392 /* GDTR. */
1393 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1394 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1395
1396 /* IDTR. */
1397 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1398 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1399}
1400
1401
1402/**
1403 * Saves guest non-register state as part of VM-exit.
1404 *
1405 * @param pVCpu The cross context virtual CPU structure.
1406 * @param uExitReason The VM-exit reason.
1407 */
1408IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1409{
1410 /*
1411 * Save guest non-register state.
1412 * See Intel spec. 27.3.4 "Saving Non-Register State".
1413 */
1414 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1415
1416 /*
1417 * Activity state.
1418 * Most VM-exits will occur in the active state. However, if the first instruction
1419 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1420 * the VM-exit will be from the HLT activity state.
1421 *
1422 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1423 */
1424 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1425 * not? */
1426 EMSTATE const enmActivityState = EMGetState(pVCpu);
1427 switch (enmActivityState)
1428 {
1429 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1430 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1431 }
1432
1433 /*
1434 * Interruptibility-state.
1435 */
1436 /* NMI. */
1437 pVmcs->u32GuestIntrState = 0;
1438 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1439 {
1440 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1441 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1442 }
1443 else
1444 {
1445 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1446 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1447 }
1448
1449 /* Blocking-by-STI. */
1450 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1451 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1452 {
1453 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1454 * currently. */
1455 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1456 }
1457 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1458
1459 /*
1460 * Pending debug exceptions.
1461 *
1462 * For VM-exits where it is not applicable, we can safely zero out the field.
1463 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1464 */
1465 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1466 && uExitReason != VMX_EXIT_SMI
1467 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1468 && !VMXIsVmexitTrapLike(uExitReason))
1469 {
1470 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1471 * block-by-MovSS is in effect. */
1472 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1473 }
1474
1475 /*
1476 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1477 *
1478 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1479 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1480 */
1481 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1482 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1483 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1484
1485 /*
1486 * PAE PDPTEs.
1487 *
1488 * If EPT is enabled and PAE paging was used at the time of the VM-exit,
1489 * the PDPTEs are saved from the VMCS. Otherwise they're undefined but
1490 * we zero them for consistency.
1491 */
1492 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1493 {
1494 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
1495 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1496 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
1497 {
1498 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1499 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1500 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1501 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1502 }
1503 else
1504 {
1505 pVmcs->u64GuestPdpte0.u = 0;
1506 pVmcs->u64GuestPdpte1.u = 0;
1507 pVmcs->u64GuestPdpte2.u = 0;
1508 pVmcs->u64GuestPdpte3.u = 0;
1509 }
1510
1511 /* Clear PGM's copy of the EPT pointer for added safety. */
1512 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1513 }
1514 else
1515 {
1516 pVmcs->u64GuestPdpte0.u = 0;
1517 pVmcs->u64GuestPdpte1.u = 0;
1518 pVmcs->u64GuestPdpte2.u = 0;
1519 pVmcs->u64GuestPdpte3.u = 0;
1520 }
1521}
1522
1523
1524/**
1525 * Saves the guest-state as part of VM-exit.
1526 *
1527 * @returns VBox status code.
1528 * @param pVCpu The cross context virtual CPU structure.
1529 * @param uExitReason The VM-exit reason.
1530 */
1531IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1532{
1533 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1534 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1535
1536 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1537 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1538 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1539
1540 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1541}
1542
1543
1544/**
1545 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1546 *
1547 * @returns VBox status code.
1548 * @param pVCpu The cross context virtual CPU structure.
1549 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1550 */
1551IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1552{
1553 /*
1554 * Save guest MSRs.
1555 * See Intel spec. 27.4 "Saving MSRs".
1556 */
1557 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1558 const char * const pszFailure = "VMX-abort";
1559
1560 /*
1561 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1562 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1563 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1564 */
1565 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1566 if (!cMsrs)
1567 return VINF_SUCCESS;
1568
1569 /*
1570 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1571 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1572 * implementation causes a VMX-abort followed by a triple-fault.
1573 */
1574 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1575 if (fIsMsrCountValid)
1576 { /* likely */ }
1577 else
1578 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1579
1580 /*
1581 * Optimization if the nested hypervisor is using the same guest-physical page for both
1582 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1583 */
1584 PVMXAUTOMSR pMsrArea;
1585 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1586 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1587 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1588 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1589 else
1590 {
1591 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1592 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1593 if (RT_SUCCESS(rc))
1594 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1595 else
1596 {
1597 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1598 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1599 }
1600 }
1601
1602 /*
1603 * Update VM-exit MSR store area.
1604 */
1605 PVMXAUTOMSR pMsr = pMsrArea;
1606 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1607 {
1608 if ( !pMsr->u32Reserved
1609 && pMsr->u32Msr != MSR_IA32_SMBASE
1610 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1611 {
1612 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1613 if (rcStrict == VINF_SUCCESS)
1614 continue;
1615
1616 /*
1617 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1618 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1619 * recording the MSR index in the auxiliary info. field and indicated further by our
1620 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1621 * if possible, or come up with a better, generic solution.
1622 */
1623 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1624 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1625 ? kVmxVDiag_Vmexit_MsrStoreRing3
1626 : kVmxVDiag_Vmexit_MsrStore;
1627 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1628 }
1629 else
1630 {
1631 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1632 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1633 }
1634 }
1635
1636 /*
1637 * Commit the VM-exit MSR store are to guest memory.
1638 */
1639 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1640 if (RT_SUCCESS(rc))
1641 return VINF_SUCCESS;
1642
1643 NOREF(uExitReason);
1644 NOREF(pszFailure);
1645
1646 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1647 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1648}
1649
1650
1651/**
1652 * Performs a VMX abort (due to an fatal error during VM-exit).
1653 *
1654 * @returns Strict VBox status code.
1655 * @param pVCpu The cross context virtual CPU structure.
1656 * @param enmAbort The VMX abort reason.
1657 */
1658IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1659{
1660 /*
1661 * Perform the VMX abort.
1662 * See Intel spec. 27.7 "VMX Aborts".
1663 */
1664 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1665
1666 /* We don't support SMX yet. */
1667 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1668 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1669 {
1670 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1671 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1672 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1673 }
1674
1675 return VINF_EM_TRIPLE_FAULT;
1676}
1677
1678
1679/**
1680 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1681 *
1682 * @param pVCpu The cross context virtual CPU structure.
1683 */
1684IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1685{
1686 /*
1687 * Load host control registers, debug registers and MSRs.
1688 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1689 */
1690 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1691 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1692
1693 /* CR0. */
1694 {
1695 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1696 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1697 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1698 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1699 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1700 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1701 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1702
1703 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1704 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1705 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1706 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1707 }
1708
1709 /* CR4. */
1710 {
1711 /* CR4 fixed bits are not modified. */
1712 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1713 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1714 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1715 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1716 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1717 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1718 if (fHostInLongMode)
1719 uValidHostCr4 |= X86_CR4_PAE;
1720 else
1721 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1722
1723 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1724 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1725 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1726 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1727 }
1728
1729 /* CR3 (host value validated while checking host-state during VM-entry). */
1730 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1731
1732 /* DR7. */
1733 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1734
1735 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1736
1737 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1738 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1739 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1740 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1741
1742 /* FS, GS bases are loaded later while we load host segment registers. */
1743
1744 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1745 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1746 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1747 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1748 {
1749 if (fHostInLongMode)
1750 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1751 else
1752 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1753 }
1754
1755 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1756
1757 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1758 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1759 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1760
1761 /* We don't support IA32_BNDCFGS MSR yet. */
1762}
1763
1764
1765/**
1766 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1767 *
1768 * @param pVCpu The cross context virtual CPU structure.
1769 */
1770IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1771{
1772 /*
1773 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1774 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1775 *
1776 * Warning! Be careful to not touch fields that are reserved by VT-x,
1777 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1778 */
1779 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1780 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1781
1782 /* CS, SS, ES, DS, FS, GS. */
1783 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1784 {
1785 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1786 bool const fUnusable = RT_BOOL(HostSel == 0);
1787 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1788
1789 /* Selector. */
1790 pSelReg->Sel = HostSel;
1791 pSelReg->ValidSel = HostSel;
1792 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1793
1794 /* Limit. */
1795 pSelReg->u32Limit = 0xffffffff;
1796
1797 /* Base. */
1798 pSelReg->u64Base = 0;
1799
1800 /* Attributes. */
1801 if (iSegReg == X86_SREG_CS)
1802 {
1803 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1804 pSelReg->Attr.n.u1DescType = 1;
1805 pSelReg->Attr.n.u2Dpl = 0;
1806 pSelReg->Attr.n.u1Present = 1;
1807 pSelReg->Attr.n.u1Long = fHostInLongMode;
1808 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1809 pSelReg->Attr.n.u1Granularity = 1;
1810 Assert(!pSelReg->Attr.n.u1Unusable);
1811 Assert(!fUnusable);
1812 }
1813 else
1814 {
1815 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1816 pSelReg->Attr.n.u1DescType = 1;
1817 pSelReg->Attr.n.u2Dpl = 0;
1818 pSelReg->Attr.n.u1Present = 1;
1819 pSelReg->Attr.n.u1DefBig = 1;
1820 pSelReg->Attr.n.u1Granularity = 1;
1821 pSelReg->Attr.n.u1Unusable = fUnusable;
1822 }
1823 }
1824
1825 /* FS base. */
1826 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1827 || fHostInLongMode)
1828 {
1829 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1830 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1831 }
1832
1833 /* GS base. */
1834 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1835 || fHostInLongMode)
1836 {
1837 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1838 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1839 }
1840
1841 /* TR. */
1842 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1843 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1844 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1845 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1846 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1847 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1848 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1849 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1850 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1851 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1852 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1853 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1854 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1855
1856 /* LDTR (Warning! do not touch the base and limits here). */
1857 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1858 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1859 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1860 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1861
1862 /* GDTR. */
1863 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1864 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1865 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1866
1867 /* IDTR.*/
1868 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1869 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1870 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1871}
1872
1873
1874/**
1875 * Checks the host PAE PDPTEs assuming we are switching to a PAE mode host.
1876 *
1877 * @param pVCpu The cross context virtual CPU structure.
1878 * @param uExitReason The VMX instruction name (for logging purposes).
1879 *
1880 * @remarks Caller must ensure the preconditions are met before calling this
1881 * function as failure here will trigger VMX aborts!
1882 */
1883IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPUCC pVCpu, uint32_t uExitReason)
1884{
1885 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1886 const char * const pszFailure = "VMX-abort";
1887 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
1888 if (RT_SUCCESS(rc))
1889 return rc;
1890 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpte);
1891}
1892
1893
1894/**
1895 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1896 *
1897 * @returns VBox status code.
1898 * @param pVCpu The cross context virtual CPU structure.
1899 * @param uExitReason The VMX instruction name (for logging purposes).
1900 */
1901IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1902{
1903 /*
1904 * Load host MSRs.
1905 * See Intel spec. 27.6 "Loading MSRs".
1906 */
1907 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1908 const char * const pszFailure = "VMX-abort";
1909
1910 /*
1911 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1912 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1913 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1914 */
1915 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1916 if (!cMsrs)
1917 return VINF_SUCCESS;
1918
1919 /*
1920 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1921 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1922 * implementation causes a VMX-abort followed by a triple-fault.
1923 */
1924 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1925 if (fIsMsrCountValid)
1926 { /* likely */ }
1927 else
1928 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1929
1930 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1931 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1932 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1933 if (RT_SUCCESS(rc))
1934 {
1935 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1936 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1937 {
1938 if ( !pMsr->u32Reserved
1939 && pMsr->u32Msr != MSR_K8_FS_BASE
1940 && pMsr->u32Msr != MSR_K8_GS_BASE
1941 && pMsr->u32Msr != MSR_K6_EFER
1942 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1943 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1944 {
1945 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1946 if (rcStrict == VINF_SUCCESS)
1947 continue;
1948
1949 /*
1950 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1951 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1952 * recording the MSR index in the auxiliary info. field and indicated further by our
1953 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1954 * if possible, or come up with a better, generic solution.
1955 */
1956 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1957 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1958 ? kVmxVDiag_Vmexit_MsrLoadRing3
1959 : kVmxVDiag_Vmexit_MsrLoad;
1960 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1961 }
1962 else
1963 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1964 }
1965 }
1966 else
1967 {
1968 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1969 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1970 }
1971
1972 NOREF(uExitReason);
1973 NOREF(pszFailure);
1974 return VINF_SUCCESS;
1975}
1976
1977
1978/**
1979 * Loads the host state as part of VM-exit.
1980 *
1981 * @returns Strict VBox status code.
1982 * @param pVCpu The cross context virtual CPU structure.
1983 * @param uExitReason The VM-exit reason (for logging purposes).
1984 */
1985IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
1986{
1987 /*
1988 * Load host state.
1989 * See Intel spec. 27.5 "Loading Host State".
1990 */
1991 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1992 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1993
1994 /* We cannot return from a long-mode guest to a host that is not in long mode. */
1995 if ( CPUMIsGuestInLongMode(pVCpu)
1996 && !fHostInLongMode)
1997 {
1998 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
1999 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2000 }
2001
2002 /*
2003 * Check host PAE PDPTEs prior to loading the host state.
2004 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2005 */
2006 bool fPdpesMapped;
2007 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2008 && !fHostInLongMode
2009 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2010 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2011 {
2012 int const rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2013 if (RT_FAILURE(rc))
2014 {
2015 Log(("VM-exit attempting to load invalid PDPTEs -> VMX-Abort\n"));
2016 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2017 }
2018 fPdpesMapped = true;
2019 }
2020 else
2021 fPdpesMapped = false;
2022
2023 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2024 iemVmxVmexitLoadHostSegRegs(pVCpu);
2025
2026 /*
2027 * Load host RIP, RSP and RFLAGS.
2028 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2029 */
2030 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2031 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2032 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2033
2034 /* Clear address range monitoring. */
2035 EMMonitorWaitClear(pVCpu);
2036
2037 /* Perform the VMX transition (PGM updates). */
2038 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu, fPdpesMapped);
2039 if (rcStrict == VINF_SUCCESS)
2040 { /* likely */ }
2041 else if (RT_SUCCESS(rcStrict))
2042 {
2043 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2044 uExitReason));
2045 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2046 }
2047 else
2048 {
2049 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2050 return VBOXSTRICTRC_VAL(rcStrict);
2051 }
2052
2053 Assert(rcStrict == VINF_SUCCESS);
2054
2055 /* Load MSRs from the VM-exit auto-load MSR area. */
2056 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2057 if (RT_FAILURE(rc))
2058 {
2059 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2060 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2061 }
2062 return VINF_SUCCESS;
2063}
2064
2065
2066/**
2067 * Gets VM-exit instruction information along with any displacement for an
2068 * instruction VM-exit.
2069 *
2070 * @returns The VM-exit instruction information.
2071 * @param pVCpu The cross context virtual CPU structure.
2072 * @param uExitReason The VM-exit reason.
2073 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2074 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2075 * NULL.
2076 */
2077IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2078{
2079 RTGCPTR GCPtrDisp;
2080 VMXEXITINSTRINFO ExitInstrInfo;
2081 ExitInstrInfo.u = 0;
2082
2083 /*
2084 * Get and parse the ModR/M byte from our decoded opcodes.
2085 */
2086 uint8_t bRm;
2087 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2088 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2089 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2090 {
2091 /*
2092 * ModR/M indicates register addressing.
2093 *
2094 * The primary/secondary register operands are reported in the iReg1 or iReg2
2095 * fields depending on whether it is a read/write form.
2096 */
2097 uint8_t idxReg1;
2098 uint8_t idxReg2;
2099 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2100 {
2101 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2102 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2103 }
2104 else
2105 {
2106 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2107 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2108 }
2109 ExitInstrInfo.All.u2Scaling = 0;
2110 ExitInstrInfo.All.iReg1 = idxReg1;
2111 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2112 ExitInstrInfo.All.fIsRegOperand = 1;
2113 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2114 ExitInstrInfo.All.iSegReg = 0;
2115 ExitInstrInfo.All.iIdxReg = 0;
2116 ExitInstrInfo.All.fIdxRegInvalid = 1;
2117 ExitInstrInfo.All.iBaseReg = 0;
2118 ExitInstrInfo.All.fBaseRegInvalid = 1;
2119 ExitInstrInfo.All.iReg2 = idxReg2;
2120
2121 /* Displacement not applicable for register addressing. */
2122 GCPtrDisp = 0;
2123 }
2124 else
2125 {
2126 /*
2127 * ModR/M indicates memory addressing.
2128 */
2129 uint8_t uScale = 0;
2130 bool fBaseRegValid = false;
2131 bool fIdxRegValid = false;
2132 uint8_t iBaseReg = 0;
2133 uint8_t iIdxReg = 0;
2134 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2135 {
2136 /*
2137 * Parse the ModR/M, displacement for 16-bit addressing mode.
2138 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2139 */
2140 uint16_t u16Disp = 0;
2141 uint8_t const offDisp = offModRm + sizeof(bRm);
2142 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2143 {
2144 /* Displacement without any registers. */
2145 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2146 }
2147 else
2148 {
2149 /* Register (index and base). */
2150 switch (bRm & X86_MODRM_RM_MASK)
2151 {
2152 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2153 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2154 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2155 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2156 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2157 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2158 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2159 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2160 }
2161
2162 /* Register + displacement. */
2163 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2164 {
2165 case 0: break;
2166 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2167 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2168 default:
2169 {
2170 /* Register addressing, handled at the beginning. */
2171 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2172 break;
2173 }
2174 }
2175 }
2176
2177 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2178 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2179 }
2180 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2181 {
2182 /*
2183 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2184 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2185 */
2186 uint32_t u32Disp = 0;
2187 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2188 {
2189 /* Displacement without any registers. */
2190 uint8_t const offDisp = offModRm + sizeof(bRm);
2191 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2192 }
2193 else
2194 {
2195 /* Register (and perhaps scale, index and base). */
2196 uint8_t offDisp = offModRm + sizeof(bRm);
2197 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2198 if (iBaseReg == 4)
2199 {
2200 /* An SIB byte follows the ModR/M byte, parse it. */
2201 uint8_t bSib;
2202 uint8_t const offSib = offModRm + sizeof(bRm);
2203 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2204
2205 /* A displacement may follow SIB, update its offset. */
2206 offDisp += sizeof(bSib);
2207
2208 /* Get the scale. */
2209 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2210
2211 /* Get the index register. */
2212 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2213 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2214
2215 /* Get the base register. */
2216 iBaseReg = bSib & X86_SIB_BASE_MASK;
2217 fBaseRegValid = true;
2218 if (iBaseReg == 5)
2219 {
2220 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2221 {
2222 /* Mod is 0 implies a 32-bit displacement with no base. */
2223 fBaseRegValid = false;
2224 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2225 }
2226 else
2227 {
2228 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2229 iBaseReg = X86_GREG_xBP;
2230 }
2231 }
2232 }
2233
2234 /* Register + displacement. */
2235 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2236 {
2237 case 0: /* Handled above */ break;
2238 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2239 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2240 default:
2241 {
2242 /* Register addressing, handled at the beginning. */
2243 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2244 break;
2245 }
2246 }
2247 }
2248
2249 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2250 }
2251 else
2252 {
2253 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2254
2255 /*
2256 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2257 * See Intel instruction spec. 2.2 "IA-32e Mode".
2258 */
2259 uint64_t u64Disp = 0;
2260 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2261 if (fRipRelativeAddr)
2262 {
2263 /*
2264 * RIP-relative addressing mode.
2265 *
2266 * The displacement is 32-bit signed implying an offset range of +/-2G.
2267 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2268 */
2269 uint8_t const offDisp = offModRm + sizeof(bRm);
2270 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2271 }
2272 else
2273 {
2274 uint8_t offDisp = offModRm + sizeof(bRm);
2275
2276 /*
2277 * Register (and perhaps scale, index and base).
2278 *
2279 * REX.B extends the most-significant bit of the base register. However, REX.B
2280 * is ignored while determining whether an SIB follows the opcode. Hence, we
2281 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2282 *
2283 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2284 */
2285 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2286 if (iBaseReg == 4)
2287 {
2288 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2289 uint8_t bSib;
2290 uint8_t const offSib = offModRm + sizeof(bRm);
2291 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2292
2293 /* Displacement may follow SIB, update its offset. */
2294 offDisp += sizeof(bSib);
2295
2296 /* Get the scale. */
2297 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2298
2299 /* Get the index. */
2300 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2301 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2302
2303 /* Get the base. */
2304 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2305 fBaseRegValid = true;
2306 if (iBaseReg == 5)
2307 {
2308 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2309 {
2310 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2311 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2312 }
2313 else
2314 {
2315 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2316 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2317 }
2318 }
2319 }
2320 iBaseReg |= pVCpu->iem.s.uRexB;
2321
2322 /* Register + displacement. */
2323 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2324 {
2325 case 0: /* Handled above */ break;
2326 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2327 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2328 default:
2329 {
2330 /* Register addressing, handled at the beginning. */
2331 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2332 break;
2333 }
2334 }
2335 }
2336
2337 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2338 }
2339
2340 /*
2341 * The primary or secondary register operand is reported in iReg2 depending
2342 * on whether the primary operand is in read/write form.
2343 */
2344 uint8_t idxReg2;
2345 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2346 {
2347 idxReg2 = bRm & X86_MODRM_RM_MASK;
2348 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2349 idxReg2 |= pVCpu->iem.s.uRexB;
2350 }
2351 else
2352 {
2353 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2354 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2355 idxReg2 |= pVCpu->iem.s.uRexReg;
2356 }
2357 ExitInstrInfo.All.u2Scaling = uScale;
2358 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2359 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2360 ExitInstrInfo.All.fIsRegOperand = 0;
2361 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2362 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2363 ExitInstrInfo.All.iIdxReg = iIdxReg;
2364 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2365 ExitInstrInfo.All.iBaseReg = iBaseReg;
2366 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2367 ExitInstrInfo.All.iReg2 = idxReg2;
2368 }
2369
2370 /*
2371 * Handle exceptions to the norm for certain instructions.
2372 * (e.g. some instructions convey an instruction identity in place of iReg2).
2373 */
2374 switch (uExitReason)
2375 {
2376 case VMX_EXIT_GDTR_IDTR_ACCESS:
2377 {
2378 Assert(VMXINSTRID_IS_VALID(uInstrId));
2379 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2380 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2381 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2382 break;
2383 }
2384
2385 case VMX_EXIT_LDTR_TR_ACCESS:
2386 {
2387 Assert(VMXINSTRID_IS_VALID(uInstrId));
2388 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2389 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2390 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2391 break;
2392 }
2393
2394 case VMX_EXIT_RDRAND:
2395 case VMX_EXIT_RDSEED:
2396 {
2397 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2398 break;
2399 }
2400 }
2401
2402 /* Update displacement and return the constructed VM-exit instruction information field. */
2403 if (pGCPtrDisp)
2404 *pGCPtrDisp = GCPtrDisp;
2405
2406 return ExitInstrInfo.u;
2407}
2408
2409
2410/**
2411 * VMX VM-exit handler.
2412 *
2413 * @returns Strict VBox status code.
2414 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2415 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2416 * triple-fault.
2417 *
2418 * @param pVCpu The cross context virtual CPU structure.
2419 * @param uExitReason The VM-exit reason.
2420 * @param u64ExitQual The Exit qualification.
2421 */
2422IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2423{
2424# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2425 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2426 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2427 return VERR_IEM_IPE_7;
2428# else
2429 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2430
2431 /*
2432 * Import all the guest-CPU state.
2433 *
2434 * HM on returning to guest execution would have to reset up a whole lot of state
2435 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2436 * the state and flag reloading the entire state on re-entry. So import the entire
2437 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2438 */
2439 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2440
2441 /*
2442 * Ensure VM-entry interruption information valid bit is cleared.
2443 *
2444 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2445 * by invalid-guest state or machine-check exceptions) also clear this bit.
2446 *
2447 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2448 */
2449 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2450 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2451
2452 /*
2453 * Update the VM-exit reason and Exit qualification.
2454 * Other VMCS read-only data fields are expected to be updated by the caller already.
2455 */
2456 pVmcs->u32RoExitReason = uExitReason;
2457 pVmcs->u64RoExitQual.u = u64ExitQual;
2458
2459 Log3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2460 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2461 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2462
2463 /*
2464 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2465 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2466 */
2467 {
2468 uint8_t uVector;
2469 uint32_t fFlags;
2470 uint32_t uErrCode;
2471 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2472 if (fInEventDelivery)
2473 {
2474 /*
2475 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2476 * caused by a triple-fault or the original event results in a double-fault that
2477 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2478 * original event information into the IDT-vectoring information fields.
2479 *
2480 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2481 */
2482 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2483 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2484 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2485 {
2486 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2487 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2488 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2489 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2490 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2491 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2492 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2493 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2494 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2495 pVCpu->cpum.GstCtx.cr2));
2496 }
2497 }
2498 }
2499
2500 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2501 Assert(pVmcs->u64RoIoRcx.u == 0);
2502 Assert(pVmcs->u64RoIoRsi.u == 0);
2503 Assert(pVmcs->u64RoIoRdi.u == 0);
2504 Assert(pVmcs->u64RoIoRip.u == 0);
2505
2506 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2507 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2508 {
2509 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2510 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2511 }
2512
2513 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2514 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2515
2516 /*
2517 * Save the guest state back into the VMCS.
2518 * We only need to save the state when the VM-entry was successful.
2519 */
2520 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2521 if (!fVmentryFailed)
2522 {
2523 /*
2524 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2525 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2526 *
2527 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2528 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2529 * as guest-CPU state would not been modified. Hence for now, we do this only when
2530 * the VM-entry succeeded.
2531 */
2532 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2533 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2534 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2535 {
2536 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2537 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2538 else
2539 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2540 }
2541
2542 /*
2543 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2544 * occurs in enclave mode/SMM which we don't support yet.
2545 *
2546 * If we ever add support for it, we can pass just the lower bits to the functions
2547 * below, till then an assert should suffice.
2548 */
2549 Assert(!RT_HI_U16(uExitReason));
2550
2551 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2552 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2553 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2554 if (RT_SUCCESS(rc))
2555 { /* likely */ }
2556 else
2557 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2558
2559 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2560 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2561 }
2562 else
2563 {
2564 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2565 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2566 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2567 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2568 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2569 }
2570
2571 /*
2572 * Stop any running VMX-preemption timer if necessary.
2573 */
2574 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2575 CPUMStopGuestVmxPremptTimer(pVCpu);
2576
2577 /*
2578 * Clear any pending VMX nested-guest force-flags.
2579 * These force-flags have no effect on (outer) guest execution and will
2580 * be re-evaluated and setup on the next nested-guest VM-entry.
2581 */
2582 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2583
2584 /* Restore the host (outer guest) state. */
2585 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2586 if (RT_SUCCESS(rcStrict))
2587 {
2588 Assert(rcStrict == VINF_SUCCESS);
2589 rcStrict = VINF_VMX_VMEXIT;
2590 }
2591 else
2592 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2593
2594 /* We're no longer in nested-guest execution mode. */
2595 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2596
2597 /* Notify HM that the current VMCS fields have been modified. */
2598 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2599
2600 /* Notify HM that we've completed the VM-exit. */
2601 HMNotifyVmxNstGstVmexit(pVCpu);
2602
2603# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2604 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2605 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2606 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2607 if (rcSched != VINF_SUCCESS)
2608 iemSetPassUpStatus(pVCpu, rcSched);
2609# endif
2610 return rcStrict;
2611# endif
2612}
2613
2614
2615/**
2616 * VMX VM-exit handler for VM-exits due to instruction execution.
2617 *
2618 * This is intended for instructions where the caller provides all the relevant
2619 * VM-exit information.
2620 *
2621 * @returns Strict VBox status code.
2622 * @param pVCpu The cross context virtual CPU structure.
2623 * @param pExitInfo Pointer to the VM-exit information.
2624 */
2625IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2626{
2627 /*
2628 * For instructions where any of the following fields are not applicable:
2629 * - Exit qualification must be cleared.
2630 * - VM-exit instruction info. is undefined.
2631 * - Guest-linear address is undefined.
2632 * - Guest-physical address is undefined.
2633 *
2634 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2635 * instruction execution. For VM-exits that are not due to instruction execution this
2636 * field is undefined.
2637 *
2638 * In our implementation in IEM, all undefined fields are generally cleared. However,
2639 * if the caller supplies information (from say the physical CPU directly) it is
2640 * then possible that the undefined fields are not cleared.
2641 *
2642 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2643 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2644 */
2645 Assert(pExitInfo);
2646 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2647 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2648 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2649
2650 /* Update all the relevant fields from the VM-exit instruction information struct. */
2651 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2652 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2653 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2654 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2655
2656 /* Perform the VM-exit. */
2657 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2658}
2659
2660
2661/**
2662 * VMX VM-exit handler for VM-exits due to instruction execution.
2663 *
2664 * This is intended for instructions that only provide the VM-exit instruction
2665 * length.
2666 *
2667 * @param pVCpu The cross context virtual CPU structure.
2668 * @param uExitReason The VM-exit reason.
2669 * @param cbInstr The instruction length in bytes.
2670 */
2671IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2672{
2673 VMXVEXITINFO ExitInfo;
2674 RT_ZERO(ExitInfo);
2675 ExitInfo.uReason = uExitReason;
2676 ExitInfo.cbInstr = cbInstr;
2677
2678#ifdef VBOX_STRICT
2679 /*
2680 * To prevent us from shooting ourselves in the foot.
2681 * The follow instructions should convey more than just the instruction length.
2682 */
2683 switch (uExitReason)
2684 {
2685 case VMX_EXIT_INVEPT:
2686 case VMX_EXIT_INVPCID:
2687 case VMX_EXIT_INVVPID:
2688 case VMX_EXIT_LDTR_TR_ACCESS:
2689 case VMX_EXIT_GDTR_IDTR_ACCESS:
2690 case VMX_EXIT_VMCLEAR:
2691 case VMX_EXIT_VMPTRLD:
2692 case VMX_EXIT_VMPTRST:
2693 case VMX_EXIT_VMREAD:
2694 case VMX_EXIT_VMWRITE:
2695 case VMX_EXIT_VMXON:
2696 case VMX_EXIT_XRSTORS:
2697 case VMX_EXIT_XSAVES:
2698 case VMX_EXIT_RDRAND:
2699 case VMX_EXIT_RDSEED:
2700 case VMX_EXIT_IO_INSTR:
2701 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2702 break;
2703 }
2704#endif
2705
2706 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2707}
2708
2709
2710/**
2711 * VMX VM-exit handler for VM-exits due to instruction execution.
2712 *
2713 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2714 * instruction information and Exit qualification fields.
2715 *
2716 * @param pVCpu The cross context virtual CPU structure.
2717 * @param uExitReason The VM-exit reason.
2718 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2719 * @param cbInstr The instruction length in bytes.
2720 *
2721 * @remarks Do not use this for INS/OUTS instruction.
2722 */
2723IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2724{
2725 VMXVEXITINFO ExitInfo;
2726 RT_ZERO(ExitInfo);
2727 ExitInfo.uReason = uExitReason;
2728 ExitInfo.cbInstr = cbInstr;
2729
2730 /*
2731 * Update the Exit qualification field with displacement bytes.
2732 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2733 */
2734 switch (uExitReason)
2735 {
2736 case VMX_EXIT_INVEPT:
2737 case VMX_EXIT_INVPCID:
2738 case VMX_EXIT_INVVPID:
2739 case VMX_EXIT_LDTR_TR_ACCESS:
2740 case VMX_EXIT_GDTR_IDTR_ACCESS:
2741 case VMX_EXIT_VMCLEAR:
2742 case VMX_EXIT_VMPTRLD:
2743 case VMX_EXIT_VMPTRST:
2744 case VMX_EXIT_VMREAD:
2745 case VMX_EXIT_VMWRITE:
2746 case VMX_EXIT_VMXON:
2747 case VMX_EXIT_XRSTORS:
2748 case VMX_EXIT_XSAVES:
2749 case VMX_EXIT_RDRAND:
2750 case VMX_EXIT_RDSEED:
2751 {
2752 /* Construct the VM-exit instruction information. */
2753 RTGCPTR GCPtrDisp;
2754 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2755
2756 /* Update the VM-exit instruction information. */
2757 ExitInfo.InstrInfo.u = uInstrInfo;
2758
2759 /* Update the Exit qualification. */
2760 ExitInfo.u64Qual = GCPtrDisp;
2761 break;
2762 }
2763
2764 default:
2765 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2766 break;
2767 }
2768
2769 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2770}
2771
2772
2773/**
2774 * VMX VM-exit handler for VM-exits due to INVLPG.
2775 *
2776 * @returns Strict VBox status code.
2777 * @param pVCpu The cross context virtual CPU structure.
2778 * @param GCPtrPage The guest-linear address of the page being invalidated.
2779 * @param cbInstr The instruction length in bytes.
2780 */
2781IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2782{
2783 VMXVEXITINFO ExitInfo;
2784 RT_ZERO(ExitInfo);
2785 ExitInfo.uReason = VMX_EXIT_INVLPG;
2786 ExitInfo.cbInstr = cbInstr;
2787 ExitInfo.u64Qual = GCPtrPage;
2788 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2789
2790 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2791}
2792
2793
2794/**
2795 * VMX VM-exit handler for VM-exits due to LMSW.
2796 *
2797 * @returns Strict VBox status code.
2798 * @param pVCpu The cross context virtual CPU structure.
2799 * @param uGuestCr0 The current guest CR0.
2800 * @param pu16NewMsw The machine-status word specified in LMSW's source
2801 * operand. This will be updated depending on the VMX
2802 * guest/host CR0 mask if LMSW is not intercepted.
2803 * @param GCPtrEffDst The guest-linear address of the source operand in case
2804 * of a memory operand. For register operand, pass
2805 * NIL_RTGCPTR.
2806 * @param cbInstr The instruction length in bytes.
2807 */
2808IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2809 uint8_t cbInstr)
2810{
2811 Assert(pu16NewMsw);
2812
2813 uint16_t const uNewMsw = *pu16NewMsw;
2814 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2815 {
2816 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2817
2818 VMXVEXITINFO ExitInfo;
2819 RT_ZERO(ExitInfo);
2820 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2821 ExitInfo.cbInstr = cbInstr;
2822
2823 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2824 if (fMemOperand)
2825 {
2826 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2827 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2828 }
2829
2830 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2831 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2832 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2833 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2834
2835 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2836 }
2837
2838 /*
2839 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2840 * CR0 guest/host mask must be left unmodified.
2841 *
2842 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2843 */
2844 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2845 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2846 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2847
2848 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2849}
2850
2851
2852/**
2853 * VMX VM-exit handler for VM-exits due to CLTS.
2854 *
2855 * @returns Strict VBox status code.
2856 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2857 * VM-exit but must not modify the guest CR0.TS bit.
2858 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2859 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2860 * CR0 fixed bits in VMX operation).
2861 * @param pVCpu The cross context virtual CPU structure.
2862 * @param cbInstr The instruction length in bytes.
2863 */
2864IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2865{
2866 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2867 uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2868
2869 /*
2870 * If CR0.TS is owned by the host:
2871 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2872 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2873 * CLTS instruction completes without clearing CR0.TS.
2874 *
2875 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2876 */
2877 if (fGstHostMask & X86_CR0_TS)
2878 {
2879 if (fReadShadow & X86_CR0_TS)
2880 {
2881 Log2(("clts: Guest intercept -> VM-exit\n"));
2882
2883 VMXVEXITINFO ExitInfo;
2884 RT_ZERO(ExitInfo);
2885 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2886 ExitInfo.cbInstr = cbInstr;
2887 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2888 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2889 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2890 }
2891
2892 return VINF_VMX_MODIFIES_BEHAVIOR;
2893 }
2894
2895 /*
2896 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2897 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2898 */
2899 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2900}
2901
2902
2903/**
2904 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2905 * (CR0/CR4 write).
2906 *
2907 * @returns Strict VBox status code.
2908 * @param pVCpu The cross context virtual CPU structure.
2909 * @param iCrReg The control register (either CR0 or CR4).
2910 * @param uGuestCrX The current guest CR0/CR4.
2911 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2912 * VM-exit is caused.
2913 * @param iGReg The general register from which the CR0/CR4 value is being
2914 * loaded.
2915 * @param cbInstr The instruction length in bytes.
2916 */
2917IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2918 uint8_t cbInstr)
2919{
2920 Assert(puNewCrX);
2921 Assert(iCrReg == 0 || iCrReg == 4);
2922 Assert(iGReg < X86_GREG_COUNT);
2923
2924 uint64_t const uNewCrX = *puNewCrX;
2925 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2926 {
2927 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2928
2929 VMXVEXITINFO ExitInfo;
2930 RT_ZERO(ExitInfo);
2931 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2932 ExitInfo.cbInstr = cbInstr;
2933 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2934 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2935 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2936 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2937 }
2938
2939 /*
2940 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2941 * must not be modified the instruction.
2942 *
2943 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2944 */
2945 uint64_t uGuestCrX;
2946 uint64_t fGstHostMask;
2947 if (iCrReg == 0)
2948 {
2949 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2950 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2951 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2952 }
2953 else
2954 {
2955 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2956 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2957 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2958 }
2959
2960 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2961 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2962}
2963
2964
2965/**
2966 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2967 *
2968 * @returns VBox strict status code.
2969 * @param pVCpu The cross context virtual CPU structure.
2970 * @param iGReg The general register to which the CR3 value is being stored.
2971 * @param cbInstr The instruction length in bytes.
2972 */
2973IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
2974{
2975 Assert(iGReg < X86_GREG_COUNT);
2976 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
2977
2978 /*
2979 * If the CR3-store exiting control is set, we must cause a VM-exit.
2980 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2981 */
2982 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
2983 {
2984 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
2985
2986 VMXVEXITINFO ExitInfo;
2987 RT_ZERO(ExitInfo);
2988 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2989 ExitInfo.cbInstr = cbInstr;
2990 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
2991 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
2992 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2993 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2994 }
2995
2996 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2997}
2998
2999
3000/**
3001 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3002 *
3003 * @returns VBox strict status code.
3004 * @param pVCpu The cross context virtual CPU structure.
3005 * @param uNewCr3 The new CR3 value.
3006 * @param iGReg The general register from which the CR3 value is being
3007 * loaded.
3008 * @param cbInstr The instruction length in bytes.
3009 */
3010IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3011{
3012 Assert(iGReg < X86_GREG_COUNT);
3013
3014 /*
3015 * If the CR3-load exiting control is set and the new CR3 value does not
3016 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3017 *
3018 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3019 */
3020 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3021 {
3022 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3023
3024 VMXVEXITINFO ExitInfo;
3025 RT_ZERO(ExitInfo);
3026 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3027 ExitInfo.cbInstr = cbInstr;
3028 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3029 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3030 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3031 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3032 }
3033
3034 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3035}
3036
3037
3038/**
3039 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3040 *
3041 * @returns VBox strict status code.
3042 * @param pVCpu The cross context virtual CPU structure.
3043 * @param iGReg The general register to which the CR8 value is being stored.
3044 * @param cbInstr The instruction length in bytes.
3045 */
3046IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3047{
3048 Assert(iGReg < X86_GREG_COUNT);
3049
3050 /*
3051 * If the CR8-store exiting control is set, we must cause a VM-exit.
3052 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3053 */
3054 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3055 {
3056 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3057
3058 VMXVEXITINFO ExitInfo;
3059 RT_ZERO(ExitInfo);
3060 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3061 ExitInfo.cbInstr = cbInstr;
3062 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3063 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3064 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3065 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3066 }
3067
3068 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3069}
3070
3071
3072/**
3073 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3074 *
3075 * @returns VBox strict status code.
3076 * @param pVCpu The cross context virtual CPU structure.
3077 * @param iGReg The general register from which the CR8 value is being
3078 * loaded.
3079 * @param cbInstr The instruction length in bytes.
3080 */
3081IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3082{
3083 Assert(iGReg < X86_GREG_COUNT);
3084
3085 /*
3086 * If the CR8-load exiting control is set, we must cause a VM-exit.
3087 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3088 */
3089 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3090 {
3091 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3092
3093 VMXVEXITINFO ExitInfo;
3094 RT_ZERO(ExitInfo);
3095 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3096 ExitInfo.cbInstr = cbInstr;
3097 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3098 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3099 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3100 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3101 }
3102
3103 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3104}
3105
3106
3107/**
3108 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3109 * GReg,DRx' (DRx read).
3110 *
3111 * @returns VBox strict status code.
3112 * @param pVCpu The cross context virtual CPU structure.
3113 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3114 * VMXINSTRID_MOV_FROM_DRX).
3115 * @param iDrReg The debug register being accessed.
3116 * @param iGReg The general register to/from which the DRx value is being
3117 * store/loaded.
3118 * @param cbInstr The instruction length in bytes.
3119 */
3120IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3121 uint8_t cbInstr)
3122{
3123 Assert(iDrReg <= 7);
3124 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3125 Assert(iGReg < X86_GREG_COUNT);
3126
3127 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3128 {
3129 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3130 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3131 VMXVEXITINFO ExitInfo;
3132 RT_ZERO(ExitInfo);
3133 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3134 ExitInfo.cbInstr = cbInstr;
3135 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3136 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3137 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3138 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3139 }
3140
3141 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3142}
3143
3144
3145/**
3146 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3147 *
3148 * @returns VBox strict status code.
3149 * @param pVCpu The cross context virtual CPU structure.
3150 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3151 * VMXINSTRID_IO_OUT).
3152 * @param u16Port The I/O port being accessed.
3153 * @param fImm Whether the I/O port was encoded using an immediate operand
3154 * or the implicit DX register.
3155 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3156 * @param cbInstr The instruction length in bytes.
3157 */
3158IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3159 uint8_t cbInstr)
3160{
3161 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3162 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3163
3164 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3165 if (fIntercept)
3166 {
3167 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3168 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3169 VMXVEXITINFO ExitInfo;
3170 RT_ZERO(ExitInfo);
3171 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3172 ExitInfo.cbInstr = cbInstr;
3173 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3174 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3175 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3176 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3177 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3178 }
3179
3180 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3181}
3182
3183
3184/**
3185 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3186 *
3187 * @returns VBox strict status code.
3188 * @param pVCpu The cross context virtual CPU structure.
3189 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3190 * VMXINSTRID_IO_OUTS).
3191 * @param u16Port The I/O port being accessed.
3192 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3193 * @param fRep Whether the instruction has a REP prefix or not.
3194 * @param ExitInstrInfo The VM-exit instruction info. field.
3195 * @param cbInstr The instruction length in bytes.
3196 */
3197IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3198 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3199{
3200 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3201 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3202 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3203 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3204 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3205
3206 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3207 if (fIntercept)
3208 {
3209 /*
3210 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3211 */
3212 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3213 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3214 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3215 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3216 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3217
3218 uint32_t uDirection;
3219 uint64_t uGuestLinearAddr;
3220 if (uInstrId == VMXINSTRID_IO_INS)
3221 {
3222 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3223 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3224 }
3225 else
3226 {
3227 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3228 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3229 }
3230
3231 /*
3232 * If the segment is unusable, the guest-linear address in undefined.
3233 * We shall clear it for consistency.
3234 *
3235 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3236 */
3237 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3238 uGuestLinearAddr = 0;
3239
3240 VMXVEXITINFO ExitInfo;
3241 RT_ZERO(ExitInfo);
3242 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3243 ExitInfo.cbInstr = cbInstr;
3244 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3245 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3246 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3247 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3248 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3249 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3250 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3251 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3252 ExitInfo.InstrInfo = ExitInstrInfo;
3253 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3254 }
3255
3256 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3257}
3258
3259
3260/**
3261 * VMX VM-exit handler for VM-exits due to MWAIT.
3262 *
3263 * @returns VBox strict status code.
3264 * @param pVCpu The cross context virtual CPU structure.
3265 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3266 * @param cbInstr The instruction length in bytes.
3267 */
3268IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3269{
3270 VMXVEXITINFO ExitInfo;
3271 RT_ZERO(ExitInfo);
3272 ExitInfo.uReason = VMX_EXIT_MWAIT;
3273 ExitInfo.cbInstr = cbInstr;
3274 ExitInfo.u64Qual = fMonitorHwArmed;
3275 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3276}
3277
3278
3279/**
3280 * VMX VM-exit handler for VM-exits due to PAUSE.
3281 *
3282 * @returns VBox strict status code.
3283 * @param pVCpu The cross context virtual CPU structure.
3284 * @param cbInstr The instruction length in bytes.
3285 */
3286IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3287{
3288 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3289
3290 /*
3291 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3292 * "PAUSE-loop exiting" control.
3293 *
3294 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3295 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3296 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3297 * a VM-exit.
3298 *
3299 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3300 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3301 */
3302 bool fIntercept = false;
3303 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3304 fIntercept = true;
3305 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3306 && pVCpu->iem.s.uCpl == 0)
3307 {
3308 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3309
3310 /*
3311 * A previous-PAUSE-tick value of 0 is used to identify the first time
3312 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3313 * consider this to be the first execution of PAUSE in a loop according
3314 * to the Intel.
3315 *
3316 * All subsequent records for the previous-PAUSE-tick we ensure that it
3317 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3318 */
3319 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3320 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3321 uint64_t const uTick = TMCpuTickGet(pVCpu);
3322 uint32_t const uPleGap = pVmcs->u32PleGap;
3323 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3324 if ( *puPrevPauseTick == 0
3325 || uTick - *puPrevPauseTick > uPleGap)
3326 *puFirstPauseLoopTick = uTick;
3327 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3328 fIntercept = true;
3329
3330 *puPrevPauseTick = uTick | 1;
3331 }
3332
3333 if (fIntercept)
3334 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3335
3336 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3337}
3338
3339
3340/**
3341 * VMX VM-exit handler for VM-exits due to task switches.
3342 *
3343 * @returns VBox strict status code.
3344 * @param pVCpu The cross context virtual CPU structure.
3345 * @param enmTaskSwitch The cause of the task switch.
3346 * @param SelNewTss The selector of the new TSS.
3347 * @param cbInstr The instruction length in bytes.
3348 */
3349IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3350{
3351 /*
3352 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3353 *
3354 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3355 * instruction or delivery of the exception generated by one of these instructions
3356 * lead to a task switch through a task gate in the IDT, we need to provide the
3357 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3358 * leaves the VM-exit instruction length field undefined.
3359 *
3360 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3361 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3362 */
3363 Assert(cbInstr <= 15);
3364
3365 uint8_t uType;
3366 switch (enmTaskSwitch)
3367 {
3368 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3369 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3370 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3371 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3372 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3373 }
3374
3375 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3376 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3377 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3378 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3379}
3380
3381
3382/**
3383 * VMX VM-exit handler for trap-like VM-exits.
3384 *
3385 * @returns VBox strict status code.
3386 * @param pVCpu The cross context virtual CPU structure.
3387 * @param pExitInfo Pointer to the VM-exit information.
3388 * @param pExitEventInfo Pointer to the VM-exit event information.
3389 */
3390IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3391{
3392 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3393 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3394 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3395}
3396
3397
3398/**
3399 * VMX VM-exit handler for VM-exits due to task switches.
3400 *
3401 * This is intended for task switches where the caller provides all the relevant
3402 * VM-exit information.
3403 *
3404 * @returns VBox strict status code.
3405 * @param pVCpu The cross context virtual CPU structure.
3406 * @param pExitInfo Pointer to the VM-exit information.
3407 * @param pExitEventInfo Pointer to the VM-exit event information.
3408 */
3409IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3410 PCVMXVEXITEVENTINFO pExitEventInfo)
3411{
3412 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3413 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3414 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3415 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3416 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3417}
3418
3419
3420/**
3421 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3422 *
3423 * @returns VBox strict status code.
3424 * @param pVCpu The cross context virtual CPU structure.
3425 */
3426IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3427{
3428 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3429 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3430
3431 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3432 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3433
3434 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3435 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3436 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3437
3438 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3439 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3440}
3441
3442
3443/**
3444 * VMX VM-exit handler for VM-exits due to external interrupts.
3445 *
3446 * @returns VBox strict status code.
3447 * @param pVCpu The cross context virtual CPU structure.
3448 * @param uVector The external interrupt vector (pass 0 if the interrupt
3449 * is still pending since we typically won't know the
3450 * vector).
3451 * @param fIntPending Whether the external interrupt is pending or
3452 * acknowledged in the interrupt controller.
3453 */
3454IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3455{
3456 Assert(!fIntPending || uVector == 0);
3457
3458 /* The VM-exit is subject to "External interrupt exiting" being set. */
3459 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3460 {
3461 if (fIntPending)
3462 {
3463 /*
3464 * If the interrupt is pending and we don't need to acknowledge the
3465 * interrupt on VM-exit, cause the VM-exit immediately.
3466 *
3467 * See Intel spec 25.2 "Other Causes Of VM Exits".
3468 */
3469 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3470 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3471
3472 /*
3473 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3474 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3475 * acknowledged that the interrupt has been consumed. Callers would have to call
3476 * us again after getting the vector (and ofc, with fIntPending with false).
3477 */
3478 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3479 }
3480
3481 /*
3482 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3483 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3484 * all set, we need to record the vector of the external interrupt in the
3485 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3486 *
3487 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3488 */
3489 uint32_t uExitIntInfo;
3490 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3491 {
3492 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3493 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3494 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3495 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3496 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3497 }
3498 else
3499 uExitIntInfo = 0;
3500 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3501
3502 /*
3503 * Cause the VM-exit whether or not the vector has been stored
3504 * in the VM-exit interruption-information field.
3505 */
3506 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3507 }
3508
3509 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3510}
3511
3512
3513/**
3514 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3515 * an event.
3516 *
3517 * @returns VBox strict status code.
3518 * @param pVCpu The cross context virtual CPU structure.
3519 */
3520IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3521{
3522 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3523 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3524 {
3525 /*
3526 * The NMI-unblocking due to IRET field need not be set for double faults.
3527 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3528 */
3529 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3530 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3531 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3532 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3533 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3534 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3535 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3536 }
3537
3538 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3539}
3540
3541
3542/**
3543 * VMX VM-exit handler for VM-exit due to delivery of an events.
3544 *
3545 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3546 * all the relevant VM-exit information.
3547 *
3548 * @returns VBox strict status code.
3549 * @param pVCpu The cross context virtual CPU structure.
3550 * @param pExitInfo Pointer to the VM-exit information.
3551 * @param pExitEventInfo Pointer to the VM-exit event information.
3552 */
3553IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3554{
3555 Assert(pExitInfo);
3556 Assert(pExitEventInfo);
3557 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3558 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3559
3560 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3561 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3562 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3563 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3564 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3565 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3566}
3567
3568
3569/**
3570 * VMX VM-exit handler for VM-exits due to delivery of an event.
3571 *
3572 * @returns VBox strict status code.
3573 * @param pVCpu The cross context virtual CPU structure.
3574 * @param uVector The interrupt / exception vector.
3575 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3576 * @param uErrCode The error code associated with the event.
3577 * @param uCr2 The CR2 value in case of a \#PF exception.
3578 * @param cbInstr The instruction length in bytes.
3579 */
3580IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3581 uint8_t cbInstr)
3582{
3583 /*
3584 * If the event is being injected as part of VM-entry, it is -not- subject to event
3585 * intercepts in the nested-guest. However, secondary exceptions that occur during
3586 * injection of any event -are- subject to event interception.
3587 *
3588 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3589 */
3590 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3591 {
3592 /*
3593 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3594 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3595 *
3596 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3597 */
3598 if ( uVector == X86_XCPT_NMI
3599 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3600 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3601 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3602 else
3603 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3604
3605 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3606 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3607 }
3608
3609 /*
3610 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3611 * If not, the caller will continue delivery of the external interrupt as it would
3612 * normally. The interrupt is no longer pending in the interrupt controller at this
3613 * point.
3614 */
3615 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3616 {
3617 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3618 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3619 }
3620
3621 /*
3622 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3623 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3624 * interrupts.
3625 */
3626 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3627 bool fIntercept;
3628 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3629 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3630 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3631 else
3632 {
3633 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3634 fIntercept = false;
3635 }
3636
3637 /*
3638 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3639 * relevant VM-exit information and cause the VM-exit.
3640 */
3641 if (fIntercept)
3642 {
3643 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3644
3645 /* Construct the rest of the event related information fields and cause the VM-exit. */
3646 uint64_t u64ExitQual;
3647 if (uVector == X86_XCPT_PF)
3648 {
3649 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3650 u64ExitQual = uCr2;
3651 }
3652 else if (uVector == X86_XCPT_DB)
3653 {
3654 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3655 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3656 }
3657 else
3658 u64ExitQual = 0;
3659
3660 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3661 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3662 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3663 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3664 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3665 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3666 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3667 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3668 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3669 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3670
3671 /*
3672 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3673 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3674 * length.
3675 */
3676 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3677 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3678 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3679 else
3680 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3681
3682 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3683 }
3684
3685 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3686}
3687
3688
3689#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3690/**
3691 * VMX VM-exit handler for EPT violation.
3692 *
3693 * @param pVCpu The cross context virtual CPU structure.
3694 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3695 * @param fEptAccess The EPT paging structure bits.
3696 * @param GCPhysAddr The physical address causing the EPT violation.
3697 * @param GCPtrAddr The linear address causing the EPT violation.
3698 * @param cbInstr The VM-exit instruction length.
3699 */
3700IEM_STATIC VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint64_t fEptAccess, RTGCPHYS GCPhysAddr,
3701 uint64_t GCPtrAddr, bool fLinearAddrValid, uint8_t cbInstr)
3702{
3703 /*
3704 * If the linear address isn't valid (can happen when loading PDPTEs
3705 * as part of MOV CR execution) the linear address field is undefined.
3706 * While we can leave it this way, it's preferrable to zero it for consistency.
3707 */
3708 Assert(fLinearAddrValid || GCPtrAddr == 0);
3709
3710 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3711 uint8_t const fSupportsAccessDirty = fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY;
3712
3713 uint8_t const fDataRead = ((fAccess & IEM_ACCESS_DATA_R) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3714 uint8_t const fDataWrite = ((fAccess & IEM_ACCESS_DATA_RW) == IEM_ACCESS_DATA_RW) | fSupportsAccessDirty;
3715 uint8_t const fInstrFetch = (fAccess & IEM_ACCESS_INSTRUCTION) == IEM_ACCESS_INSTRUCTION;
3716 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3717 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3718 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3719 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3720
3721 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
3722 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
3723 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
3724 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
3725 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
3726 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
3727 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fLinearAddrValid)
3728 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
3729
3730 /** @todo bit 8 of Exit Qualification!
3731 * If the access causing the EPT violation is to a guest-physical address that is
3732 * the translation of a linear address.
3733 * - OR -
3734 * if the access causing the EPT violation is to a paging-structure entry as part
3735 * of a page walk or the update of an accessed or dirty bit.
3736 *
3737 * Caller needs to be able to distinguish this... */
3738
3739#ifdef VBOX_STRICT
3740 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
3741 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
3742 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
3743 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
3744 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3745 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3746 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
3747#endif
3748
3749 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3750 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
3751 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3752
3753 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
3754}
3755#endif
3756
3757
3758/**
3759 * VMX VM-exit handler for APIC accesses.
3760 *
3761 * @param pVCpu The cross context virtual CPU structure.
3762 * @param offAccess The offset of the register being accessed.
3763 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3764 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3765 */
3766IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3767{
3768 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3769
3770 VMXAPICACCESS enmAccess;
3771 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3772 if (fInEventDelivery)
3773 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3774 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3775 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3776 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3777 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3778 else
3779 enmAccess = VMXAPICACCESS_LINEAR_READ;
3780
3781 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3782 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3783 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3784}
3785
3786
3787/**
3788 * VMX VM-exit handler for APIC accesses.
3789 *
3790 * This is intended for APIC accesses where the caller provides all the
3791 * relevant VM-exit information.
3792 *
3793 * @returns VBox strict status code.
3794 * @param pVCpu The cross context virtual CPU structure.
3795 * @param pExitInfo Pointer to the VM-exit information.
3796 * @param pExitEventInfo Pointer to the VM-exit event information.
3797 */
3798IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3799 PCVMXVEXITEVENTINFO pExitEventInfo)
3800{
3801 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3802 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3803 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3804 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3805 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3806 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3807 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3808 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3809 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3810}
3811
3812
3813/**
3814 * VMX VM-exit handler for APIC-write VM-exits.
3815 *
3816 * @param pVCpu The cross context virtual CPU structure.
3817 * @param offApic The write to the virtual-APIC page offset that caused this
3818 * VM-exit.
3819 */
3820IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3821{
3822 Assert(offApic < XAPIC_OFF_END + 4);
3823 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3824 offApic &= UINT16_C(0xfff);
3825 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3826}
3827
3828
3829/**
3830 * Sets virtual-APIC write emulation as pending.
3831 *
3832 * @param pVCpu The cross context virtual CPU structure.
3833 * @param offApic The offset in the virtual-APIC page that was written.
3834 */
3835DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3836{
3837 Assert(offApic < XAPIC_OFF_END + 4);
3838
3839 /*
3840 * Record the currently updated APIC offset, as we need this later for figuring
3841 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3842 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3843 */
3844 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3845
3846 /*
3847 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3848 * virtualization or APIC-write emulation).
3849 */
3850 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3851 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3852}
3853
3854
3855/**
3856 * Clears any pending virtual-APIC write emulation.
3857 *
3858 * @returns The virtual-APIC offset that was written before clearing it.
3859 * @param pVCpu The cross context virtual CPU structure.
3860 */
3861DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3862{
3863 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3864 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3865 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3866 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3867 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3868 return offVirtApicWrite;
3869}
3870
3871
3872/**
3873 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3874 *
3875 * @returns The register from the virtual-APIC page.
3876 * @param pVCpu The cross context virtual CPU structure.
3877 * @param offReg The offset of the register being read.
3878 */
3879IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3880{
3881 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3882
3883 uint32_t uReg = 0;
3884 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3885 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3886 AssertMsgStmt(RT_SUCCESS(rc),
3887 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3888 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3889 uReg = 0);
3890 return uReg;
3891}
3892
3893
3894/**
3895 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3896 *
3897 * @returns The register from the virtual-APIC page.
3898 * @param pVCpu The cross context virtual CPU structure.
3899 * @param offReg The offset of the register being read.
3900 */
3901IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3902{
3903 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3904
3905 uint64_t uReg = 0;
3906 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3907 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3908 AssertMsgStmt(RT_SUCCESS(rc),
3909 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3910 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3911 uReg = 0);
3912 return uReg;
3913}
3914
3915
3916/**
3917 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3918 *
3919 * @param pVCpu The cross context virtual CPU structure.
3920 * @param offReg The offset of the register being written.
3921 * @param uReg The register value to write.
3922 */
3923IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3924{
3925 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3926
3927 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3928 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3929 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3930 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3931}
3932
3933
3934/**
3935 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3936 *
3937 * @param pVCpu The cross context virtual CPU structure.
3938 * @param offReg The offset of the register being written.
3939 * @param uReg The register value to write.
3940 */
3941IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3942{
3943 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3944
3945 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3946 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3947 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3948 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3949}
3950
3951
3952/**
3953 * Sets the vector in a virtual-APIC 256-bit sparse register.
3954 *
3955 * @param pVCpu The cross context virtual CPU structure.
3956 * @param offReg The offset of the 256-bit spare register.
3957 * @param uVector The vector to set.
3958 *
3959 * @remarks This is based on our APIC device code.
3960 */
3961IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3962{
3963 /* Determine the vector offset within the chunk. */
3964 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3965
3966 /* Read the chunk at the offset. */
3967 uint32_t uReg;
3968 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3969 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3970 if (RT_SUCCESS(rc))
3971 {
3972 /* Modify the chunk. */
3973 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3974 uReg |= RT_BIT(idxVectorBit);
3975
3976 /* Write the chunk. */
3977 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3978 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3979 uVector, offReg, GCPhysVirtApic, rc));
3980 }
3981 else
3982 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3983 uVector, offReg, GCPhysVirtApic, rc));
3984}
3985
3986
3987/**
3988 * Clears the vector in a virtual-APIC 256-bit sparse register.
3989 *
3990 * @param pVCpu The cross context virtual CPU structure.
3991 * @param offReg The offset of the 256-bit spare register.
3992 * @param uVector The vector to clear.
3993 *
3994 * @remarks This is based on our APIC device code.
3995 */
3996IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3997{
3998 /* Determine the vector offset within the chunk. */
3999 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4000
4001 /* Read the chunk at the offset. */
4002 uint32_t uReg;
4003 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4004 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4005 if (RT_SUCCESS(rc))
4006 {
4007 /* Modify the chunk. */
4008 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4009 uReg &= ~RT_BIT(idxVectorBit);
4010
4011 /* Write the chunk. */
4012 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4013 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4014 uVector, offReg, GCPhysVirtApic, rc));
4015 }
4016 else
4017 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4018 uVector, offReg, GCPhysVirtApic, rc));
4019}
4020
4021
4022/**
4023 * Checks if a memory access to the APIC-access page must causes an APIC-access
4024 * VM-exit.
4025 *
4026 * @param pVCpu The cross context virtual CPU structure.
4027 * @param offAccess The offset of the register being accessed.
4028 * @param cbAccess The size of the access in bytes.
4029 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4030 * IEM_ACCESS_TYPE_WRITE).
4031 *
4032 * @remarks This must not be used for MSR-based APIC-access page accesses!
4033 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4034 */
4035IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4036{
4037 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4038 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4039
4040 /*
4041 * We must cause a VM-exit if any of the following are true:
4042 * - TPR shadowing isn't active.
4043 * - The access size exceeds 32-bits.
4044 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4045 *
4046 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4047 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4048 */
4049 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4050 || cbAccess > sizeof(uint32_t)
4051 || ((offAccess + cbAccess - 1) & 0xc)
4052 || offAccess >= XAPIC_OFF_END + 4)
4053 return true;
4054
4055 /*
4056 * If the access is part of an operation where we have already
4057 * virtualized a virtual-APIC write, we must cause a VM-exit.
4058 */
4059 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4060 return true;
4061
4062 /*
4063 * Check write accesses to the APIC-access page that cause VM-exits.
4064 */
4065 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4066 {
4067 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4068 {
4069 /*
4070 * With APIC-register virtualization, a write access to any of the
4071 * following registers are virtualized. Accessing any other register
4072 * causes a VM-exit.
4073 */
4074 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4075 switch (offAlignedAccess)
4076 {
4077 case XAPIC_OFF_ID:
4078 case XAPIC_OFF_TPR:
4079 case XAPIC_OFF_EOI:
4080 case XAPIC_OFF_LDR:
4081 case XAPIC_OFF_DFR:
4082 case XAPIC_OFF_SVR:
4083 case XAPIC_OFF_ESR:
4084 case XAPIC_OFF_ICR_LO:
4085 case XAPIC_OFF_ICR_HI:
4086 case XAPIC_OFF_LVT_TIMER:
4087 case XAPIC_OFF_LVT_THERMAL:
4088 case XAPIC_OFF_LVT_PERF:
4089 case XAPIC_OFF_LVT_LINT0:
4090 case XAPIC_OFF_LVT_LINT1:
4091 case XAPIC_OFF_LVT_ERROR:
4092 case XAPIC_OFF_TIMER_ICR:
4093 case XAPIC_OFF_TIMER_DCR:
4094 break;
4095 default:
4096 return true;
4097 }
4098 }
4099 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4100 {
4101 /*
4102 * With virtual-interrupt delivery, a write access to any of the
4103 * following registers are virtualized. Accessing any other register
4104 * causes a VM-exit.
4105 *
4106 * Note! The specification does not allow writing to offsets in-between
4107 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4108 */
4109 switch (offAccess)
4110 {
4111 case XAPIC_OFF_TPR:
4112 case XAPIC_OFF_EOI:
4113 case XAPIC_OFF_ICR_LO:
4114 break;
4115 default:
4116 return true;
4117 }
4118 }
4119 else
4120 {
4121 /*
4122 * Without APIC-register virtualization or virtual-interrupt delivery,
4123 * only TPR accesses are virtualized.
4124 */
4125 if (offAccess == XAPIC_OFF_TPR)
4126 { /* likely */ }
4127 else
4128 return true;
4129 }
4130 }
4131 else
4132 {
4133 /*
4134 * Check read accesses to the APIC-access page that cause VM-exits.
4135 */
4136 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4137 {
4138 /*
4139 * With APIC-register virtualization, a read access to any of the
4140 * following registers are virtualized. Accessing any other register
4141 * causes a VM-exit.
4142 */
4143 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4144 switch (offAlignedAccess)
4145 {
4146 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4147 case XAPIC_OFF_ID:
4148 case XAPIC_OFF_VERSION:
4149 case XAPIC_OFF_TPR:
4150 case XAPIC_OFF_EOI:
4151 case XAPIC_OFF_LDR:
4152 case XAPIC_OFF_DFR:
4153 case XAPIC_OFF_SVR:
4154 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4155 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4156 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4157 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4158 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4159 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4160 case XAPIC_OFF_ESR:
4161 case XAPIC_OFF_ICR_LO:
4162 case XAPIC_OFF_ICR_HI:
4163 case XAPIC_OFF_LVT_TIMER:
4164 case XAPIC_OFF_LVT_THERMAL:
4165 case XAPIC_OFF_LVT_PERF:
4166 case XAPIC_OFF_LVT_LINT0:
4167 case XAPIC_OFF_LVT_LINT1:
4168 case XAPIC_OFF_LVT_ERROR:
4169 case XAPIC_OFF_TIMER_ICR:
4170 case XAPIC_OFF_TIMER_DCR:
4171 break;
4172 default:
4173 return true;
4174 }
4175 }
4176 else
4177 {
4178 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4179 if (offAccess == XAPIC_OFF_TPR)
4180 { /* likely */ }
4181 else
4182 return true;
4183 }
4184 }
4185
4186 /* The APIC access is virtualized, does not cause a VM-exit. */
4187 return false;
4188}
4189
4190
4191/**
4192 * Virtualizes a memory-based APIC access where the address is not used to access
4193 * memory.
4194 *
4195 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4196 * page-faults but do not use the address to access memory.
4197 *
4198 * @param pVCpu The cross context virtual CPU structure.
4199 * @param pGCPhysAccess Pointer to the guest-physical address used.
4200 */
4201IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4202{
4203 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4204 Assert(pGCPhysAccess);
4205
4206 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4207 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4208 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4209
4210 if (GCPhysAccess == GCPhysApic)
4211 {
4212 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4213 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4214 uint16_t const cbAccess = 1;
4215 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4216 if (fIntercept)
4217 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4218
4219 *pGCPhysAccess = GCPhysApic | offAccess;
4220 return VINF_VMX_MODIFIES_BEHAVIOR;
4221 }
4222
4223 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4224}
4225
4226
4227/**
4228 * Virtualizes a memory-based APIC access.
4229 *
4230 * @returns VBox strict status code.
4231 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4232 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4233 *
4234 * @param pVCpu The cross context virtual CPU structure.
4235 * @param offAccess The offset of the register being accessed (within the
4236 * APIC-access page).
4237 * @param cbAccess The size of the access in bytes.
4238 * @param pvData Pointer to the data being written or where to store the data
4239 * being read.
4240 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4241 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4242 */
4243IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4244 uint32_t fAccess)
4245{
4246 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4247 Assert(pvData);
4248 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4249 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4250 || (fAccess & IEM_ACCESS_INSTRUCTION));
4251
4252 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4253 if (fIntercept)
4254 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4255
4256 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4257 {
4258 /*
4259 * A write access to the APIC-access page that is virtualized (rather than
4260 * causing a VM-exit) writes data to the virtual-APIC page.
4261 */
4262 uint32_t const u32Data = *(uint32_t *)pvData;
4263 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4264
4265 /*
4266 * Record the currently updated APIC offset, as we need this later for figuring
4267 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4268 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4269 *
4270 * After completion of the current operation, we need to perform TPR virtualization,
4271 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4272 *
4273 * The current operation may be a REP-prefixed string instruction, execution of any
4274 * other instruction, or delivery of an event through the IDT.
4275 *
4276 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4277 * performed now but later after completion of the current operation.
4278 *
4279 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4280 */
4281 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4282 }
4283 else
4284 {
4285 /*
4286 * A read access from the APIC-access page that is virtualized (rather than
4287 * causing a VM-exit) returns data from the virtual-APIC page.
4288 *
4289 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4290 */
4291 Assert(cbAccess <= 4);
4292 Assert(offAccess < XAPIC_OFF_END + 4);
4293 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4294
4295 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4296 u32Data &= s_auAccessSizeMasks[cbAccess];
4297 *(uint32_t *)pvData = u32Data;
4298 }
4299
4300 return VINF_VMX_MODIFIES_BEHAVIOR;
4301}
4302
4303
4304/**
4305 * Virtualizes an MSR-based APIC read access.
4306 *
4307 * @returns VBox strict status code.
4308 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4309 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4310 * handled by the x2APIC device.
4311 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4312 * not within the range of valid MSRs, caller must raise \#GP(0).
4313 * @param pVCpu The cross context virtual CPU structure.
4314 * @param idMsr The x2APIC MSR being read.
4315 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4316 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4317 */
4318IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4319{
4320 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4321 Assert(pu64Value);
4322
4323 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4324 {
4325 if ( idMsr >= MSR_IA32_X2APIC_START
4326 && idMsr <= MSR_IA32_X2APIC_END)
4327 {
4328 uint16_t const offReg = (idMsr & 0xff) << 4;
4329 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4330 *pu64Value = u64Value;
4331 return VINF_VMX_MODIFIES_BEHAVIOR;
4332 }
4333 return VERR_OUT_OF_RANGE;
4334 }
4335
4336 if (idMsr == MSR_IA32_X2APIC_TPR)
4337 {
4338 uint16_t const offReg = (idMsr & 0xff) << 4;
4339 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4340 *pu64Value = u64Value;
4341 return VINF_VMX_MODIFIES_BEHAVIOR;
4342 }
4343
4344 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4345}
4346
4347
4348/**
4349 * Virtualizes an MSR-based APIC write access.
4350 *
4351 * @returns VBox strict status code.
4352 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4353 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4354 * not within the range of valid MSRs, caller must raise \#GP(0).
4355 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4356 *
4357 * @param pVCpu The cross context virtual CPU structure.
4358 * @param idMsr The x2APIC MSR being written.
4359 * @param u64Value The value of the x2APIC MSR being written.
4360 */
4361IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4362{
4363 /*
4364 * Check if the access is to be virtualized.
4365 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4366 */
4367 if ( idMsr == MSR_IA32_X2APIC_TPR
4368 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4369 && ( idMsr == MSR_IA32_X2APIC_EOI
4370 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4371 {
4372 /* Validate the MSR write depending on the register. */
4373 switch (idMsr)
4374 {
4375 case MSR_IA32_X2APIC_TPR:
4376 case MSR_IA32_X2APIC_SELF_IPI:
4377 {
4378 if (u64Value & UINT64_C(0xffffffffffffff00))
4379 return VERR_OUT_OF_RANGE;
4380 break;
4381 }
4382 case MSR_IA32_X2APIC_EOI:
4383 {
4384 if (u64Value != 0)
4385 return VERR_OUT_OF_RANGE;
4386 break;
4387 }
4388 }
4389
4390 /* Write the MSR to the virtual-APIC page. */
4391 uint16_t const offReg = (idMsr & 0xff) << 4;
4392 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4393
4394 /*
4395 * Record the currently updated APIC offset, as we need this later for figuring
4396 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4397 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4398 */
4399 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4400
4401 return VINF_VMX_MODIFIES_BEHAVIOR;
4402 }
4403
4404 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4405}
4406
4407
4408/**
4409 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4410 *
4411 * @returns VBox status code.
4412 * @retval VINF_SUCCESS when the highest set bit is found.
4413 * @retval VERR_NOT_FOUND when no bit is set.
4414 *
4415 * @param pVCpu The cross context virtual CPU structure.
4416 * @param offReg The offset of the APIC 256-bit sparse register.
4417 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4418 * set in the register. Only valid when VINF_SUCCESS is
4419 * returned.
4420 *
4421 * @remarks The format of the 256-bit sparse register here mirrors that found in
4422 * real APIC hardware.
4423 */
4424static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4425{
4426 Assert(offReg < XAPIC_OFF_END + 4);
4427 Assert(pidxHighestBit);
4428
4429 /*
4430 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4431 * However, in each fragment only the first 4 bytes are used.
4432 */
4433 uint8_t const cFrags = 8;
4434 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4435 {
4436 uint16_t const offFrag = iFrag * 16;
4437 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4438 if (!u32Frag)
4439 continue;
4440
4441 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4442 Assert(idxHighestBit > 0);
4443 --idxHighestBit;
4444 Assert(idxHighestBit <= UINT8_MAX);
4445 *pidxHighestBit = idxHighestBit;
4446 return VINF_SUCCESS;
4447 }
4448 return VERR_NOT_FOUND;
4449}
4450
4451
4452/**
4453 * Evaluates pending virtual interrupts.
4454 *
4455 * @param pVCpu The cross context virtual CPU structure.
4456 */
4457IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4458{
4459 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4460
4461 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4462 {
4463 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4464 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4465
4466 if ((uRvi >> 4) > (uPpr >> 4))
4467 {
4468 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4469 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4470 }
4471 else
4472 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4473 }
4474}
4475
4476
4477/**
4478 * Performs PPR virtualization.
4479 *
4480 * @returns VBox strict status code.
4481 * @param pVCpu The cross context virtual CPU structure.
4482 */
4483IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4484{
4485 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4486 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4487
4488 /*
4489 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4490 * or EOI-virtualization.
4491 *
4492 * See Intel spec. 29.1.3 "PPR Virtualization".
4493 */
4494 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4495 uint32_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4496
4497 uint32_t uPpr;
4498 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4499 uPpr = uTpr & 0xff;
4500 else
4501 uPpr = uSvi & 0xf0;
4502
4503 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4504 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4505}
4506
4507
4508/**
4509 * Performs VMX TPR virtualization.
4510 *
4511 * @returns VBox strict status code.
4512 * @param pVCpu The cross context virtual CPU structure.
4513 */
4514IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4515{
4516 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4517
4518 /*
4519 * We should have already performed the virtual-APIC write to the TPR offset
4520 * in the virtual-APIC page. We now perform TPR virtualization.
4521 *
4522 * See Intel spec. 29.1.2 "TPR Virtualization".
4523 */
4524 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4525 {
4526 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4527 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4528
4529 /*
4530 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4531 * See Intel spec. 29.1.2 "TPR Virtualization".
4532 */
4533 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4534 {
4535 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4536 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4537 }
4538 }
4539 else
4540 {
4541 iemVmxPprVirtualization(pVCpu);
4542 iemVmxEvalPendingVirtIntrs(pVCpu);
4543 }
4544
4545 return VINF_SUCCESS;
4546}
4547
4548
4549/**
4550 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4551 * not.
4552 *
4553 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4554 * @param pVCpu The cross context virtual CPU structure.
4555 * @param uVector The interrupt that was acknowledged using an EOI.
4556 */
4557IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4558{
4559 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4560 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4561
4562 if (uVector < 64)
4563 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4564 if (uVector < 128)
4565 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4566 if (uVector < 192)
4567 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4568 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4569}
4570
4571
4572/**
4573 * Performs EOI virtualization.
4574 *
4575 * @returns VBox strict status code.
4576 * @param pVCpu The cross context virtual CPU structure.
4577 */
4578IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4579{
4580 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4581 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4582
4583 /*
4584 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4585 * and get the next guest-interrupt that's in-service (if any).
4586 *
4587 * See Intel spec. 29.1.4 "EOI Virtualization".
4588 */
4589 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4590 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4591 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4592
4593 uint8_t uVector = uSvi;
4594 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4595
4596 uVector = 0;
4597 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4598
4599 if (uVector)
4600 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4601 else
4602 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4603
4604 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4605 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4606
4607 iemVmxPprVirtualization(pVCpu);
4608 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4609 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4610 iemVmxEvalPendingVirtIntrs(pVCpu);
4611 return VINF_SUCCESS;
4612}
4613
4614
4615/**
4616 * Performs self-IPI virtualization.
4617 *
4618 * @returns VBox strict status code.
4619 * @param pVCpu The cross context virtual CPU structure.
4620 */
4621IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4622{
4623 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4624 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4625
4626 /*
4627 * We should have already performed the virtual-APIC write to the self-IPI offset
4628 * in the virtual-APIC page. We now perform self-IPI virtualization.
4629 *
4630 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4631 */
4632 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4633 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4634 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4635 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4636 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4637 if (uVector > uRvi)
4638 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4639 iemVmxEvalPendingVirtIntrs(pVCpu);
4640 return VINF_SUCCESS;
4641}
4642
4643
4644/**
4645 * Performs VMX APIC-write emulation.
4646 *
4647 * @returns VBox strict status code.
4648 * @param pVCpu The cross context virtual CPU structure.
4649 */
4650IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4651{
4652 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4653
4654 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4655 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4656
4657 /*
4658 * Perform APIC-write emulation based on the virtual-APIC register written.
4659 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4660 */
4661 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4662 VBOXSTRICTRC rcStrict;
4663 switch (offApicWrite)
4664 {
4665 case XAPIC_OFF_TPR:
4666 {
4667 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4668 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4669 uTpr &= UINT32_C(0x000000ff);
4670 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4671 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4672 rcStrict = iemVmxTprVirtualization(pVCpu);
4673 break;
4674 }
4675
4676 case XAPIC_OFF_EOI:
4677 {
4678 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4679 {
4680 /* Clear VEOI and perform EOI virtualization. */
4681 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4682 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4683 rcStrict = iemVmxEoiVirtualization(pVCpu);
4684 }
4685 else
4686 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4687 break;
4688 }
4689
4690 case XAPIC_OFF_ICR_LO:
4691 {
4692 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4693 {
4694 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4695 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4696 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4697 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4698 if ( !(uIcrLo & fIcrLoMb0)
4699 && (uIcrLo & fIcrLoMb1))
4700 {
4701 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4702 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4703 }
4704 else
4705 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4706 }
4707 else
4708 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4709 break;
4710 }
4711
4712 case XAPIC_OFF_ICR_HI:
4713 {
4714 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4715 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4716 uIcrHi &= UINT32_C(0xff000000);
4717 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4718 rcStrict = VINF_SUCCESS;
4719 break;
4720 }
4721
4722 default:
4723 {
4724 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4725 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4726 break;
4727 }
4728 }
4729
4730 return rcStrict;
4731}
4732
4733
4734/**
4735 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4736 *
4737 * @param pVCpu The cross context virtual CPU structure.
4738 * @param pszInstr The VMX instruction name (for logging purposes).
4739 */
4740DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4741{
4742 /*
4743 * Guest Control Registers, Debug Registers, and MSRs.
4744 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4745 */
4746 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4747 const char * const pszFailure = "VM-exit";
4748 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4749
4750 /* CR0 reserved bits. */
4751 {
4752 /* CR0 MB1 bits. */
4753 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4754 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4755 if (fUnrestrictedGuest)
4756 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4757 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4758 { /* likely */ }
4759 else
4760 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4761
4762 /* CR0 MBZ bits. */
4763 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4764 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4765 { /* likely */ }
4766 else
4767 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4768
4769 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4770 if ( !fUnrestrictedGuest
4771 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4772 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4773 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4774 }
4775
4776 /* CR4 reserved bits. */
4777 {
4778 /* CR4 MB1 bits. */
4779 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4780 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4781 { /* likely */ }
4782 else
4783 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4784
4785 /* CR4 MBZ bits. */
4786 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4787 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4788 { /* likely */ }
4789 else
4790 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4791 }
4792
4793 /* DEBUGCTL MSR. */
4794 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4795 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4796 { /* likely */ }
4797 else
4798 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4799
4800 /* 64-bit CPU checks. */
4801 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4802 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4803 {
4804 if (fGstInLongMode)
4805 {
4806 /* PAE must be set. */
4807 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4808 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4809 { /* likely */ }
4810 else
4811 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4812 }
4813 else
4814 {
4815 /* PCIDE should not be set. */
4816 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4817 { /* likely */ }
4818 else
4819 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4820 }
4821
4822 /* CR3. */
4823 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4824 { /* likely */ }
4825 else
4826 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4827
4828 /* DR7. */
4829 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4830 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4831 { /* likely */ }
4832 else
4833 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4834
4835 /* SYSENTER ESP and SYSENTER EIP. */
4836 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4837 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4838 { /* likely */ }
4839 else
4840 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4841 }
4842
4843 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4844 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4845
4846 /* PAT MSR. */
4847 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4848 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4849 { /* likely */ }
4850 else
4851 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4852
4853 /* EFER MSR. */
4854 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4855 {
4856 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4857 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4858 { /* likely */ }
4859 else
4860 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4861
4862 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4863 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4864 if ( fGstLma == fGstInLongMode
4865 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4866 || fGstLma == fGstLme))
4867 { /* likely */ }
4868 else
4869 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4870 }
4871
4872 /* We don't support IA32_BNDCFGS MSR yet. */
4873 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4874
4875 NOREF(pszInstr);
4876 NOREF(pszFailure);
4877 return VINF_SUCCESS;
4878}
4879
4880
4881/**
4882 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4883 *
4884 * @param pVCpu The cross context virtual CPU structure.
4885 * @param pszInstr The VMX instruction name (for logging purposes).
4886 */
4887DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4888{
4889 /*
4890 * Segment registers.
4891 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4892 */
4893 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4894 const char * const pszFailure = "VM-exit";
4895 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4896 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4897 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4898
4899 /* Selectors. */
4900 if ( !fGstInV86Mode
4901 && !fUnrestrictedGuest
4902 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4903 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4904
4905 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4906 {
4907 CPUMSELREG SelReg;
4908 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4909 if (RT_LIKELY(rc == VINF_SUCCESS))
4910 { /* likely */ }
4911 else
4912 return rc;
4913
4914 /*
4915 * Virtual-8086 mode checks.
4916 */
4917 if (fGstInV86Mode)
4918 {
4919 /* Base address. */
4920 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4921 { /* likely */ }
4922 else
4923 {
4924 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4925 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4926 }
4927
4928 /* Limit. */
4929 if (SelReg.u32Limit == 0xffff)
4930 { /* likely */ }
4931 else
4932 {
4933 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4934 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4935 }
4936
4937 /* Attribute. */
4938 if (SelReg.Attr.u == 0xf3)
4939 { /* likely */ }
4940 else
4941 {
4942 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4943 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4944 }
4945
4946 /* We're done; move to checking the next segment. */
4947 continue;
4948 }
4949
4950 /* Checks done by 64-bit CPUs. */
4951 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4952 {
4953 /* Base address. */
4954 if ( iSegReg == X86_SREG_FS
4955 || iSegReg == X86_SREG_GS)
4956 {
4957 if (X86_IS_CANONICAL(SelReg.u64Base))
4958 { /* likely */ }
4959 else
4960 {
4961 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4962 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4963 }
4964 }
4965 else if (iSegReg == X86_SREG_CS)
4966 {
4967 if (!RT_HI_U32(SelReg.u64Base))
4968 { /* likely */ }
4969 else
4970 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
4971 }
4972 else
4973 {
4974 if ( SelReg.Attr.n.u1Unusable
4975 || !RT_HI_U32(SelReg.u64Base))
4976 { /* likely */ }
4977 else
4978 {
4979 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4980 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4981 }
4982 }
4983 }
4984
4985 /*
4986 * Checks outside Virtual-8086 mode.
4987 */
4988 uint8_t const uSegType = SelReg.Attr.n.u4Type;
4989 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
4990 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
4991 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
4992 uint8_t const fPresent = SelReg.Attr.n.u1Present;
4993 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
4994 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
4995 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
4996
4997 /* Code or usable segment. */
4998 if ( iSegReg == X86_SREG_CS
4999 || fUsable)
5000 {
5001 /* Reserved bits (bits 31:17 and bits 11:8). */
5002 if (!(SelReg.Attr.u & 0xfffe0f00))
5003 { /* likely */ }
5004 else
5005 {
5006 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5007 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5008 }
5009
5010 /* Descriptor type. */
5011 if (fCodeDataSeg)
5012 { /* likely */ }
5013 else
5014 {
5015 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5016 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5017 }
5018
5019 /* Present. */
5020 if (fPresent)
5021 { /* likely */ }
5022 else
5023 {
5024 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5025 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5026 }
5027
5028 /* Granularity. */
5029 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5030 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5031 { /* likely */ }
5032 else
5033 {
5034 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5035 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5036 }
5037 }
5038
5039 if (iSegReg == X86_SREG_CS)
5040 {
5041 /* Segment Type and DPL. */
5042 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5043 && fUnrestrictedGuest)
5044 {
5045 if (uDpl == 0)
5046 { /* likely */ }
5047 else
5048 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5049 }
5050 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5051 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5052 {
5053 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5054 if (uDpl == AttrSs.n.u2Dpl)
5055 { /* likely */ }
5056 else
5057 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5058 }
5059 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5060 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5061 {
5062 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5063 if (uDpl <= AttrSs.n.u2Dpl)
5064 { /* likely */ }
5065 else
5066 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5067 }
5068 else
5069 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5070
5071 /* Def/Big. */
5072 if ( fGstInLongMode
5073 && fSegLong)
5074 {
5075 if (uDefBig == 0)
5076 { /* likely */ }
5077 else
5078 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5079 }
5080 }
5081 else if (iSegReg == X86_SREG_SS)
5082 {
5083 /* Segment Type. */
5084 if ( !fUsable
5085 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5086 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5087 { /* likely */ }
5088 else
5089 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5090
5091 /* DPL. */
5092 if (!fUnrestrictedGuest)
5093 {
5094 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5095 { /* likely */ }
5096 else
5097 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5098 }
5099 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5100 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5101 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5102 {
5103 if (uDpl == 0)
5104 { /* likely */ }
5105 else
5106 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5107 }
5108 }
5109 else
5110 {
5111 /* DS, ES, FS, GS. */
5112 if (fUsable)
5113 {
5114 /* Segment type. */
5115 if (uSegType & X86_SEL_TYPE_ACCESSED)
5116 { /* likely */ }
5117 else
5118 {
5119 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5120 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5121 }
5122
5123 if ( !(uSegType & X86_SEL_TYPE_CODE)
5124 || (uSegType & X86_SEL_TYPE_READ))
5125 { /* likely */ }
5126 else
5127 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5128
5129 /* DPL. */
5130 if ( !fUnrestrictedGuest
5131 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5132 {
5133 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5134 { /* likely */ }
5135 else
5136 {
5137 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5138 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5139 }
5140 }
5141 }
5142 }
5143 }
5144
5145 /*
5146 * LDTR.
5147 */
5148 {
5149 CPUMSELREG Ldtr;
5150 Ldtr.Sel = pVmcs->GuestLdtr;
5151 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5152 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5153 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5154
5155 if (!Ldtr.Attr.n.u1Unusable)
5156 {
5157 /* Selector. */
5158 if (!(Ldtr.Sel & X86_SEL_LDT))
5159 { /* likely */ }
5160 else
5161 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5162
5163 /* Base. */
5164 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5165 {
5166 if (X86_IS_CANONICAL(Ldtr.u64Base))
5167 { /* likely */ }
5168 else
5169 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5170 }
5171
5172 /* Attributes. */
5173 /* Reserved bits (bits 31:17 and bits 11:8). */
5174 if (!(Ldtr.Attr.u & 0xfffe0f00))
5175 { /* likely */ }
5176 else
5177 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5178
5179 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5180 { /* likely */ }
5181 else
5182 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5183
5184 if (!Ldtr.Attr.n.u1DescType)
5185 { /* likely */ }
5186 else
5187 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5188
5189 if (Ldtr.Attr.n.u1Present)
5190 { /* likely */ }
5191 else
5192 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5193
5194 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5195 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5196 { /* likely */ }
5197 else
5198 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5199 }
5200 }
5201
5202 /*
5203 * TR.
5204 */
5205 {
5206 CPUMSELREG Tr;
5207 Tr.Sel = pVmcs->GuestTr;
5208 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5209 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5210 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5211
5212 /* Selector. */
5213 if (!(Tr.Sel & X86_SEL_LDT))
5214 { /* likely */ }
5215 else
5216 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5217
5218 /* Base. */
5219 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5220 {
5221 if (X86_IS_CANONICAL(Tr.u64Base))
5222 { /* likely */ }
5223 else
5224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5225 }
5226
5227 /* Attributes. */
5228 /* Reserved bits (bits 31:17 and bits 11:8). */
5229 if (!(Tr.Attr.u & 0xfffe0f00))
5230 { /* likely */ }
5231 else
5232 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5233
5234 if (!Tr.Attr.n.u1Unusable)
5235 { /* likely */ }
5236 else
5237 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5238
5239 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5240 || ( !fGstInLongMode
5241 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5242 { /* likely */ }
5243 else
5244 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5245
5246 if (!Tr.Attr.n.u1DescType)
5247 { /* likely */ }
5248 else
5249 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5250
5251 if (Tr.Attr.n.u1Present)
5252 { /* likely */ }
5253 else
5254 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5255
5256 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5257 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5258 { /* likely */ }
5259 else
5260 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5261 }
5262
5263 NOREF(pszInstr);
5264 NOREF(pszFailure);
5265 return VINF_SUCCESS;
5266}
5267
5268
5269/**
5270 * Checks guest GDTR and IDTR as part of VM-entry.
5271 *
5272 * @param pVCpu The cross context virtual CPU structure.
5273 * @param pszInstr The VMX instruction name (for logging purposes).
5274 */
5275DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5276{
5277 /*
5278 * GDTR and IDTR.
5279 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5280 */
5281 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5282 const char *const pszFailure = "VM-exit";
5283
5284 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5285 {
5286 /* Base. */
5287 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5288 { /* likely */ }
5289 else
5290 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5291
5292 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5293 { /* likely */ }
5294 else
5295 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5296 }
5297
5298 /* Limit. */
5299 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5300 { /* likely */ }
5301 else
5302 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5303
5304 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5305 { /* likely */ }
5306 else
5307 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5308
5309 NOREF(pszInstr);
5310 NOREF(pszFailure);
5311 return VINF_SUCCESS;
5312}
5313
5314
5315/**
5316 * Checks guest RIP and RFLAGS as part of VM-entry.
5317 *
5318 * @param pVCpu The cross context virtual CPU structure.
5319 * @param pszInstr The VMX instruction name (for logging purposes).
5320 */
5321DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5322{
5323 /*
5324 * RIP and RFLAGS.
5325 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5326 */
5327 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5328 const char *const pszFailure = "VM-exit";
5329 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5330
5331 /* RIP. */
5332 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5333 {
5334 X86DESCATTR AttrCs;
5335 AttrCs.u = pVmcs->u32GuestCsAttr;
5336 if ( !fGstInLongMode
5337 || !AttrCs.n.u1Long)
5338 {
5339 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5340 { /* likely */ }
5341 else
5342 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5343 }
5344
5345 if ( fGstInLongMode
5346 && AttrCs.n.u1Long)
5347 {
5348 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5349 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5350 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5351 { /* likely */ }
5352 else
5353 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5354 }
5355 }
5356
5357 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5358 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5359 : pVmcs->u64GuestRFlags.s.Lo;
5360 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5361 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5362 { /* likely */ }
5363 else
5364 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5365
5366 if ( fGstInLongMode
5367 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5368 {
5369 if (!(uGuestRFlags & X86_EFL_VM))
5370 { /* likely */ }
5371 else
5372 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5373 }
5374
5375 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5376 {
5377 if (uGuestRFlags & X86_EFL_IF)
5378 { /* likely */ }
5379 else
5380 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5381 }
5382
5383 NOREF(pszInstr);
5384 NOREF(pszFailure);
5385 return VINF_SUCCESS;
5386}
5387
5388
5389/**
5390 * Checks guest non-register state as part of VM-entry.
5391 *
5392 * @param pVCpu The cross context virtual CPU structure.
5393 * @param pszInstr The VMX instruction name (for logging purposes).
5394 */
5395DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5396{
5397 /*
5398 * Guest non-register state.
5399 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5400 */
5401 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5402 const char *const pszFailure = "VM-exit";
5403
5404 /*
5405 * Activity state.
5406 */
5407 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5408 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5409 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5410 { /* likely */ }
5411 else
5412 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5413
5414 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5415 if ( !AttrSs.n.u2Dpl
5416 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5417 { /* likely */ }
5418 else
5419 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5420
5421 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5422 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5423 {
5424 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5425 { /* likely */ }
5426 else
5427 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5428 }
5429
5430 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5431 {
5432 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5433 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5434 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5435 switch (pVmcs->u32GuestActivityState)
5436 {
5437 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5438 {
5439 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5440 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5441 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5442 && ( uVector == X86_XCPT_DB
5443 || uVector == X86_XCPT_MC))
5444 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5445 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5446 { /* likely */ }
5447 else
5448 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5449 break;
5450 }
5451
5452 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5453 {
5454 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5455 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5456 && uVector == X86_XCPT_MC))
5457 { /* likely */ }
5458 else
5459 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5460 break;
5461 }
5462
5463 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5464 default:
5465 break;
5466 }
5467 }
5468
5469 /*
5470 * Interruptibility state.
5471 */
5472 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5473 { /* likely */ }
5474 else
5475 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5476
5477 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5478 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5479 { /* likely */ }
5480 else
5481 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5482
5483 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5484 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5485 { /* likely */ }
5486 else
5487 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5488
5489 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5490 {
5491 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5492 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5493 {
5494 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5495 { /* likely */ }
5496 else
5497 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5498 }
5499 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5500 {
5501 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5502 { /* likely */ }
5503 else
5504 {
5505 /*
5506 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5507 * We update the Exit qualification only when blocking-by-STI is set
5508 * without blocking-by-MovSS being set. Although in practise it does not
5509 * make much difference since the order of checks are implementation defined.
5510 */
5511 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5512 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5513 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5514 }
5515
5516 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5517 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5518 { /* likely */ }
5519 else
5520 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5521 }
5522 }
5523
5524 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5525 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5526 { /* likely */ }
5527 else
5528 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5529
5530 /* We don't support SGX yet. So enclave-interruption must not be set. */
5531 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5532 { /* likely */ }
5533 else
5534 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5535
5536 /*
5537 * Pending debug exceptions.
5538 */
5539 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5540 ? pVmcs->u64GuestPendingDbgXcpts.u
5541 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5542 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5543 { /* likely */ }
5544 else
5545 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5546
5547 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5548 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5549 {
5550 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5551 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5552 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5553 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5554
5555 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5556 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5557 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5558 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5559 }
5560
5561 /* We don't support RTM (Real-time Transactional Memory) yet. */
5562 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5563 { /* likely */ }
5564 else
5565 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5566
5567 /*
5568 * VMCS link pointer.
5569 */
5570 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5571 {
5572 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5573 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5574 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5575 { /* likely */ }
5576 else
5577 {
5578 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5579 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5580 }
5581
5582 /* Validate the address. */
5583 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5584 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5585 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5586 { /* likely */ }
5587 else
5588 {
5589 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5590 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5591 }
5592 }
5593
5594 NOREF(pszInstr);
5595 NOREF(pszFailure);
5596 return VINF_SUCCESS;
5597}
5598
5599
5600/**
5601 * Checks guest PDPTEs as part of VM-entry.
5602 *
5603 * @param pVCpu The cross context virtual CPU structure.
5604 * @param pfPdpesMapped Where to store whether PAE PDPTEs (and PDPT) have been
5605 * mapped as part of checking guest state.
5606 * @param pszInstr The VMX instruction name (for logging purposes).
5607 */
5608IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, bool *pfPdpesMapped, const char *pszInstr)
5609{
5610 /*
5611 * Guest PDPTEs.
5612 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5613 */
5614 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5615 const char * const pszFailure = "VM-exit";
5616 *pfPdpesMapped = false;
5617
5618 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
5619 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5620 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5621 {
5622#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5623 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
5624 {
5625 /* Get PDPTEs from the VMCS. */
5626 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
5627 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
5628 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
5629 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
5630 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
5631
5632 /* Check validity of the PDPTEs. */
5633 bool const fValid = PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]);
5634 if (fValid)
5635 { /* likely */ }
5636 else
5637 {
5638 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5639 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5640 }
5641 }
5642 else
5643#endif
5644 {
5645 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
5646 if (rc == VINF_SUCCESS)
5647 *pfPdpesMapped = true;
5648 else
5649 {
5650 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5651 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5652 }
5653 }
5654 }
5655
5656 NOREF(pszInstr);
5657 NOREF(pszFailure);
5658 return VINF_SUCCESS;
5659}
5660
5661
5662/**
5663 * Checks guest-state as part of VM-entry.
5664 *
5665 * @returns VBox status code.
5666 * @param pVCpu The cross context virtual CPU structure.
5667 * @param pfPdpesMapped Where to store whether PAE PDPTEs (and PDPT) have been
5668 * mapped as part of checking guest state.
5669 * @param pszInstr The VMX instruction name (for logging purposes).
5670 */
5671IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, bool *pfPdpesMapped, const char *pszInstr)
5672{
5673 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5674 if (RT_SUCCESS(rc))
5675 {
5676 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5677 if (RT_SUCCESS(rc))
5678 {
5679 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5680 if (RT_SUCCESS(rc))
5681 {
5682 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5683 if (RT_SUCCESS(rc))
5684 {
5685 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5686 if (RT_SUCCESS(rc))
5687 return iemVmxVmentryCheckGuestPdptes(pVCpu, pfPdpesMapped, pszInstr);
5688 }
5689 }
5690 }
5691 }
5692 return rc;
5693}
5694
5695
5696/**
5697 * Checks host-state as part of VM-entry.
5698 *
5699 * @returns VBox status code.
5700 * @param pVCpu The cross context virtual CPU structure.
5701 * @param pszInstr The VMX instruction name (for logging purposes).
5702 */
5703IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5704{
5705 /*
5706 * Host Control Registers and MSRs.
5707 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5708 */
5709 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5710 const char * const pszFailure = "VMFail";
5711
5712 /* CR0 reserved bits. */
5713 {
5714 /* CR0 MB1 bits. */
5715 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5716 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5717 { /* likely */ }
5718 else
5719 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5720
5721 /* CR0 MBZ bits. */
5722 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5723 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5724 { /* likely */ }
5725 else
5726 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5727 }
5728
5729 /* CR4 reserved bits. */
5730 {
5731 /* CR4 MB1 bits. */
5732 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5733 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5734 { /* likely */ }
5735 else
5736 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5737
5738 /* CR4 MBZ bits. */
5739 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5740 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5741 { /* likely */ }
5742 else
5743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5744 }
5745
5746 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5747 {
5748 /* CR3 reserved bits. */
5749 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5750 { /* likely */ }
5751 else
5752 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5753
5754 /* SYSENTER ESP and SYSENTER EIP. */
5755 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5756 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5757 { /* likely */ }
5758 else
5759 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5760 }
5761
5762 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5763 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5764
5765 /* PAT MSR. */
5766 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5767 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5768 { /* likely */ }
5769 else
5770 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5771
5772 /* EFER MSR. */
5773 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5774 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5775 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5776 { /* likely */ }
5777 else
5778 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5779
5780 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5781 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5782 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5783 if ( fHostInLongMode == fHostLma
5784 && fHostInLongMode == fHostLme)
5785 { /* likely */ }
5786 else
5787 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5788
5789 /*
5790 * Host Segment and Descriptor-Table Registers.
5791 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5792 */
5793 /* Selector RPL and TI. */
5794 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5795 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5796 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5797 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5798 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5799 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5800 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5801 { /* likely */ }
5802 else
5803 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5804
5805 /* CS and TR selectors cannot be 0. */
5806 if ( pVmcs->HostCs
5807 && pVmcs->HostTr)
5808 { /* likely */ }
5809 else
5810 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5811
5812 /* SS cannot be 0 if 32-bit host. */
5813 if ( fHostInLongMode
5814 || pVmcs->HostSs)
5815 { /* likely */ }
5816 else
5817 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5818
5819 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5820 {
5821 /* FS, GS, GDTR, IDTR, TR base address. */
5822 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5823 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5824 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5825 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5826 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5827 { /* likely */ }
5828 else
5829 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5830 }
5831
5832 /*
5833 * Host address-space size for 64-bit CPUs.
5834 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5835 */
5836 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5837 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5838 {
5839 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5840
5841 /* Logical processor in IA-32e mode. */
5842 if (fCpuInLongMode)
5843 {
5844 if (fHostInLongMode)
5845 {
5846 /* PAE must be set. */
5847 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5848 { /* likely */ }
5849 else
5850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5851
5852 /* RIP must be canonical. */
5853 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5854 { /* likely */ }
5855 else
5856 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5857 }
5858 else
5859 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5860 }
5861 else
5862 {
5863 /* Logical processor is outside IA-32e mode. */
5864 if ( !fGstInLongMode
5865 && !fHostInLongMode)
5866 {
5867 /* PCIDE should not be set. */
5868 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5869 { /* likely */ }
5870 else
5871 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5872
5873 /* The high 32-bits of RIP MBZ. */
5874 if (!pVmcs->u64HostRip.s.Hi)
5875 { /* likely */ }
5876 else
5877 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5878 }
5879 else
5880 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5881 }
5882 }
5883 else
5884 {
5885 /* Host address-space size for 32-bit CPUs. */
5886 if ( !fGstInLongMode
5887 && !fHostInLongMode)
5888 { /* likely */ }
5889 else
5890 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5891 }
5892
5893 NOREF(pszInstr);
5894 NOREF(pszFailure);
5895 return VINF_SUCCESS;
5896}
5897
5898
5899#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5900/**
5901 * Checks the EPT pointer VMCS field as part of VM-entry.
5902 *
5903 * @returns VBox status code.
5904 * @param pVCpu The cross context virtual CPU structure.
5905 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
5906 * updated on success). Optional, can be NULL.
5907 */
5908IEM_STATIC int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, VMXVDIAG *penmVmxDiag)
5909{
5910 VMXVDIAG enmVmxDiag;
5911 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5912
5913 /* Reserved bits. */
5914 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
5915 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
5916 if (pVmcs->u64EptPtr.u & fValidMask)
5917 {
5918 /* Memory Type. */
5919 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
5920 uint8_t const fMemType = RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_MEMTYPE);
5921 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
5922 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
5923 || ( fMemType == VMX_EPTP_MEMTYPE_UC
5924 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
5925 {
5926 /*
5927 * Page walk length (PML4).
5928 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
5929 * of 5 but that seems to be removed from the latest specs. leaving only PML4
5930 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
5931 */
5932 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
5933 if (RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
5934 {
5935 /* Access and dirty bits support in EPT structures. */
5936 if ( !RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_ACCESS_DIRTY)
5937 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
5938 return VINF_SUCCESS;
5939
5940 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
5941 }
5942 else
5943 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
5944 }
5945 else
5946 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
5947 }
5948 else
5949 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
5950
5951 if (penmVmxDiag)
5952 *penmVmxDiag = enmVmxDiag;
5953 return VERR_VMX_VMENTRY_FAILED;
5954}
5955#endif
5956
5957
5958/**
5959 * Checks VMCS controls fields as part of VM-entry.
5960 *
5961 * @returns VBox status code.
5962 * @param pVCpu The cross context virtual CPU structure.
5963 * @param pszInstr The VMX instruction name (for logging purposes).
5964 *
5965 * @remarks This may update secondary-processor based VM-execution control fields
5966 * in the current VMCS if necessary.
5967 */
5968IEM_STATIC int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr)
5969{
5970 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5971 const char * const pszFailure = "VMFail";
5972
5973 /*
5974 * VM-execution controls.
5975 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
5976 */
5977 {
5978 /* Pin-based VM-execution controls. */
5979 {
5980 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
5981 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
5982 { /* likely */ }
5983 else
5984 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
5985
5986 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
5987 { /* likely */ }
5988 else
5989 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
5990 }
5991
5992 /* Processor-based VM-execution controls. */
5993 {
5994 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
5995 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
5996 { /* likely */ }
5997 else
5998 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
5999
6000 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6001 { /* likely */ }
6002 else
6003 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6004 }
6005
6006 /* Secondary processor-based VM-execution controls. */
6007 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6008 {
6009 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6010 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6011 { /* likely */ }
6012 else
6013 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6014
6015 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6016 { /* likely */ }
6017 else
6018 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6019 }
6020 else
6021 Assert(!pVmcs->u32ProcCtls2);
6022
6023 /* CR3-target count. */
6024 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6025 { /* likely */ }
6026 else
6027 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6028
6029 /* I/O bitmaps physical addresses. */
6030 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6031 {
6032 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6033 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6034 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6035 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6036 { /* likely */ }
6037 else
6038 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6039
6040 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6041 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6042 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6043 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6044 { /* likely */ }
6045 else
6046 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6047 }
6048
6049 /* MSR bitmap physical address. */
6050 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6051 {
6052 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6053 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6054 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6055 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6056 { /* likely */ }
6057 else
6058 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6059 }
6060
6061 /* TPR shadow related controls. */
6062 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6063 {
6064 /* Virtual-APIC page physical address. */
6065 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6066 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6067 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6068 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6069 { /* likely */ }
6070 else
6071 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6072
6073 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6074 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6075 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6076 { /* likely */ }
6077 else
6078 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6079
6080 /* The rest done XXX document */
6081 }
6082 else
6083 {
6084 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6085 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6086 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6087 { /* likely */ }
6088 else
6089 {
6090 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6091 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6092 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6093 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6094 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6095 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6096 }
6097 }
6098
6099 /* NMI exiting and virtual-NMIs. */
6100 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6101 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6102 { /* likely */ }
6103 else
6104 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6105
6106 /* Virtual-NMIs and NMI-window exiting. */
6107 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6108 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6109 { /* likely */ }
6110 else
6111 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6112
6113 /* Virtualize APIC accesses. */
6114 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6115 {
6116 /* APIC-access physical address. */
6117 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6118 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6119 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6120 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6121 { /* likely */ }
6122 else
6123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6124
6125 /*
6126 * Disallow APIC-access page and virtual-APIC page from being the same address.
6127 * Note! This is not an Intel requirement, but one imposed by our implementation.
6128 */
6129 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6130 * redirecting accesses between the APIC-access page and the virtual-APIC
6131 * page. If any nested hypervisor requires this, we can implement it later. */
6132 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6133 {
6134 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6135 if (GCPhysVirtApic != GCPhysApicAccess)
6136 { /* likely */ }
6137 else
6138 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6139 }
6140 }
6141
6142 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6143 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6144 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6145 { /* likely */ }
6146 else
6147 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6148
6149 /* Virtual-interrupt delivery requires external interrupt exiting. */
6150 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6151 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6152 { /* likely */ }
6153 else
6154 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6155
6156 /* VPID. */
6157 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6158 || pVmcs->u16Vpid != 0)
6159 { /* likely */ }
6160 else
6161 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6162
6163#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6164 /* Extended-Page-Table Pointer (EPTP). */
6165 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6166 {
6167 VMXVDIAG enmVmxDiag;
6168 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, &enmVmxDiag);
6169 if (RT_SUCCESS(rc))
6170 { /* likely */ }
6171 else
6172 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6173 }
6174#else
6175 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6176#endif
6177
6178 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6179 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6180 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6181 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6182 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6183 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6184 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6185
6186 /* VMCS shadowing. */
6187 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6188 {
6189 /* VMREAD-bitmap physical address. */
6190 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6191 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6192 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6193 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6194 { /* likely */ }
6195 else
6196 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6197
6198 /* VMWRITE-bitmap physical address. */
6199 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6200 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6201 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6202 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6203 { /* likely */ }
6204 else
6205 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6206 }
6207 }
6208
6209 /*
6210 * VM-exit controls.
6211 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6212 */
6213 {
6214 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6215 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6216 { /* likely */ }
6217 else
6218 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6219
6220 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6221 { /* likely */ }
6222 else
6223 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6224
6225 /* Save preemption timer without activating it. */
6226 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6227 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6228 { /* likely */ }
6229 else
6230 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6231
6232 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6233 if (pVmcs->u32ExitMsrStoreCount)
6234 {
6235 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6236 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6237 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6238 { /* likely */ }
6239 else
6240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6241 }
6242
6243 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6244 if (pVmcs->u32ExitMsrLoadCount)
6245 {
6246 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6247 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6248 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6249 { /* likely */ }
6250 else
6251 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6252 }
6253 }
6254
6255 /*
6256 * VM-entry controls.
6257 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6258 */
6259 {
6260 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6261 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6262 { /* likely */ }
6263 else
6264 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6265
6266 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6267 { /* likely */ }
6268 else
6269 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6270
6271 /* Event injection. */
6272 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6273 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6274 {
6275 /* Type and vector. */
6276 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6277 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6278 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6279 if ( !uRsvd
6280 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6281 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6282 { /* likely */ }
6283 else
6284 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6285
6286 /* Exception error code. */
6287 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6288 {
6289 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6290 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6291 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6292 { /* likely */ }
6293 else
6294 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6295
6296 /* Exceptions that provide an error code. */
6297 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6298 && ( uVector == X86_XCPT_DF
6299 || uVector == X86_XCPT_TS
6300 || uVector == X86_XCPT_NP
6301 || uVector == X86_XCPT_SS
6302 || uVector == X86_XCPT_GP
6303 || uVector == X86_XCPT_PF
6304 || uVector == X86_XCPT_AC))
6305 { /* likely */ }
6306 else
6307 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6308
6309 /* Exception error-code reserved bits. */
6310 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6311 { /* likely */ }
6312 else
6313 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6314
6315 /* Injecting a software interrupt, software exception or privileged software exception. */
6316 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6317 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6318 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6319 {
6320 /* Instruction length must be in the range 0-15. */
6321 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6322 { /* likely */ }
6323 else
6324 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6325
6326 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6327 if ( pVmcs->u32EntryInstrLen != 0
6328 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6329 { /* likely */ }
6330 else
6331 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6332 }
6333 }
6334 }
6335
6336 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6337 if (pVmcs->u32EntryMsrLoadCount)
6338 {
6339 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6340 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6341 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6342 { /* likely */ }
6343 else
6344 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6345 }
6346
6347 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6348 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6349 }
6350
6351 NOREF(pszInstr);
6352 NOREF(pszFailure);
6353 return VINF_SUCCESS;
6354}
6355
6356
6357/**
6358 * Loads the guest control registers, debug register and some MSRs as part of
6359 * VM-entry.
6360 *
6361 * @param pVCpu The cross context virtual CPU structure.
6362 */
6363IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6364{
6365 /*
6366 * Load guest control registers, debug registers and MSRs.
6367 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6368 */
6369 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6370
6371 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6372 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6373 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6374 CPUMSetGuestCR0(pVCpu, uGstCr0);
6375 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6376 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6377
6378 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6379 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6380
6381 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6382 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6383 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6384
6385 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6386 {
6387 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6388
6389 /* EFER MSR. */
6390 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6391 {
6392 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6393 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6394 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6395 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6396 if (fGstInLongMode)
6397 {
6398 /* If the nested-guest is in long mode, LMA and LME are both set. */
6399 Assert(fGstPaging);
6400 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6401 }
6402 else
6403 {
6404 /*
6405 * If the nested-guest is outside long mode:
6406 * - With paging: LMA is cleared, LME is cleared.
6407 * - Without paging: LMA is cleared, LME is left unmodified.
6408 */
6409 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6410 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6411 }
6412 }
6413 /* else: see below. */
6414 }
6415
6416 /* PAT MSR. */
6417 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6418 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6419
6420 /* EFER MSR. */
6421 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6422 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6423
6424 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6425 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6426
6427 /* We don't support IA32_BNDCFGS MSR yet. */
6428 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6429
6430 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6431}
6432
6433
6434/**
6435 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6436 *
6437 * @param pVCpu The cross context virtual CPU structure.
6438 */
6439IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6440{
6441 /*
6442 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6443 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6444 */
6445 /* CS, SS, ES, DS, FS, GS. */
6446 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6447 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6448 {
6449 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6450 CPUMSELREG VmcsSelReg;
6451 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6452 AssertRC(rc); NOREF(rc);
6453 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6454 {
6455 pGstSelReg->Sel = VmcsSelReg.Sel;
6456 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6457 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6458 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6459 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6460 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6461 }
6462 else
6463 {
6464 pGstSelReg->Sel = VmcsSelReg.Sel;
6465 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6466 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6467 switch (iSegReg)
6468 {
6469 case X86_SREG_CS:
6470 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6471 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6472 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6473 break;
6474
6475 case X86_SREG_SS:
6476 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6477 pGstSelReg->u32Limit = 0;
6478 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6479 break;
6480
6481 case X86_SREG_ES:
6482 case X86_SREG_DS:
6483 pGstSelReg->u64Base = 0;
6484 pGstSelReg->u32Limit = 0;
6485 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6486 break;
6487
6488 case X86_SREG_FS:
6489 case X86_SREG_GS:
6490 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6491 pGstSelReg->u32Limit = 0;
6492 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6493 break;
6494 }
6495 Assert(pGstSelReg->Attr.n.u1Unusable);
6496 }
6497 }
6498
6499 /* LDTR. */
6500 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6501 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6502 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6503 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6504 {
6505 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6506 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6507 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6508 }
6509 else
6510 {
6511 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6512 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6513 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6514 }
6515
6516 /* TR. */
6517 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6518 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6519 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6520 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6521 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6522 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6523 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6524
6525 /* GDTR. */
6526 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6527 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6528
6529 /* IDTR. */
6530 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6531 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6532}
6533
6534
6535/**
6536 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6537 *
6538 * @returns VBox status code.
6539 * @param pVCpu The cross context virtual CPU structure.
6540 * @param pszInstr The VMX instruction name (for logging purposes).
6541 */
6542IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6543{
6544 /*
6545 * Load guest MSRs.
6546 * See Intel spec. 26.4 "Loading MSRs".
6547 */
6548 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6549 const char *const pszFailure = "VM-exit";
6550
6551 /*
6552 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6553 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6554 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6555 */
6556 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6557 if (!cMsrs)
6558 return VINF_SUCCESS;
6559
6560 /*
6561 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6562 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6563 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6564 */
6565 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6566 if (fIsMsrCountValid)
6567 { /* likely */ }
6568 else
6569 {
6570 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6571 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6572 }
6573
6574 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6575 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6576 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6577 if (RT_SUCCESS(rc))
6578 {
6579 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6580 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6581 {
6582 if ( !pMsr->u32Reserved
6583 && pMsr->u32Msr != MSR_K8_FS_BASE
6584 && pMsr->u32Msr != MSR_K8_GS_BASE
6585 && pMsr->u32Msr != MSR_K6_EFER
6586 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6587 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6588 {
6589 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6590 if (rcStrict == VINF_SUCCESS)
6591 continue;
6592
6593 /*
6594 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6595 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6596 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6597 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6598 * MSR in ring-0 if possible, or come up with a better, generic solution.
6599 */
6600 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6601 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6602 ? kVmxVDiag_Vmentry_MsrLoadRing3
6603 : kVmxVDiag_Vmentry_MsrLoad;
6604 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6605 }
6606 else
6607 {
6608 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6609 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6610 }
6611 }
6612 }
6613 else
6614 {
6615 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6616 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6617 }
6618
6619 NOREF(pszInstr);
6620 NOREF(pszFailure);
6621 return VINF_SUCCESS;
6622}
6623
6624
6625/**
6626 * Loads the guest-state non-register state as part of VM-entry.
6627 *
6628 * @returns VBox status code.
6629 * @param pVCpu The cross context virtual CPU structure.
6630 *
6631 * @remarks This must be called only after loading the nested-guest register state
6632 * (especially nested-guest RIP).
6633 */
6634IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu)
6635{
6636 /*
6637 * Load guest non-register state.
6638 * See Intel spec. 26.6 "Special Features of VM Entry"
6639 */
6640 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6641
6642 /*
6643 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6644 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6645 *
6646 * See Intel spec. 26.6.1 "Interruptibility State".
6647 */
6648 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6649 if ( !fEntryVectoring
6650 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6651 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6652 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6653 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6654
6655 /* NMI blocking. */
6656 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6657 {
6658 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6659 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6660 else
6661 {
6662 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6663 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6664 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6665 }
6666 }
6667 else
6668 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6669
6670 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6671
6672 /*
6673 * Load the PAE PDPTEs from the VMCS when using EPT with PAE paging.
6674 */
6675 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6676 {
6677 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
6678 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
6679 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
6680 {
6681 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6682 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6683 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6684 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6685 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6686 AssertCompile(RT_ELEMENTS(aPaePdptes) == RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes));
6687 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes); i++)
6688 pVCpu->cpum.GstCtx.aPaePdpes[i].u = aPaePdptes[i].u;
6689 }
6690
6691 /*
6692 * Set PGM's copy of the EPT pointer.
6693 * The EPTP has already been validated while checking guest state.
6694 */
6695 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
6696 }
6697
6698 /* VPID is irrelevant. We don't support VPID yet. */
6699
6700 /* Clear address-range monitoring. */
6701 EMMonitorWaitClear(pVCpu);
6702}
6703
6704
6705/**
6706 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
6707 *
6708 * @param pVCpu The cross context virtual CPU structure.
6709 * @param pszInstr The VMX instruction name (for logging purposes).
6710 *
6711 * @remarks This assumes various VMCS related data structure pointers have already
6712 * been verified prior to calling this function.
6713 */
6714IEM_STATIC int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr)
6715{
6716 const char *const pszFailure = "VM-exit";
6717 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6718
6719 /*
6720 * Virtualize APIC accesses.
6721 */
6722 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6723 {
6724 /* APIC-access physical address. */
6725 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6726
6727 /*
6728 * Register the handler for the APIC-access page.
6729 *
6730 * We don't deregister the APIC-access page handler during the VM-exit as a different
6731 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6732 *
6733 * We leave the page registered until the first access that happens outside VMX non-root
6734 * mode. Guest software is allowed to access structures such as the APIC-access page
6735 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6736 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6737 *
6738 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6739 */
6740 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6741 {
6742 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6743 PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
6744 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6745 pVCpu0->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6746 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6747 if (RT_SUCCESS(rc))
6748 { /* likely */ }
6749 else
6750 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6751 }
6752 }
6753
6754 /*
6755 * VMCS shadowing.
6756 */
6757 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6758 {
6759 /* Read the VMREAD-bitmap. */
6760 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6761 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
6762 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
6763 if (RT_SUCCESS(rc))
6764 { /* likely */ }
6765 else
6766 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6767
6768 /* Read the VMWRITE-bitmap. */
6769 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
6770 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
6771 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
6772 if (RT_SUCCESS(rc))
6773 { /* likely */ }
6774 else
6775 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6776 }
6777
6778 /*
6779 * I/O bitmaps.
6780 */
6781 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6782 {
6783 /* Read the IO bitmap A. */
6784 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6785 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
6786 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
6787 if (RT_SUCCESS(rc))
6788 { /* likely */ }
6789 else
6790 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
6791
6792 /* Read the IO bitmap B. */
6793 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6794 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
6795 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
6796 if (RT_SUCCESS(rc))
6797 { /* likely */ }
6798 else
6799 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
6800 }
6801
6802 /*
6803 * TPR shadow and Virtual-APIC page.
6804 */
6805 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6806 {
6807 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6808 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6809 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6810 {
6811 /* Read the VTPR from the virtual-APIC page. */
6812 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6813 uint8_t u8VTpr;
6814 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6815 if (RT_SUCCESS(rc))
6816 { /* likely */ }
6817 else
6818 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6819
6820 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6821 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6822 { /* likely */ }
6823 else
6824 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6825 }
6826 }
6827
6828 /*
6829 * VMCS link pointer.
6830 */
6831 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6832 {
6833 /* Read the VMCS-link pointer from guest memory. */
6834 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6835 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
6836 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
6837 if (RT_SUCCESS(rc))
6838 { /* likely */ }
6839 else
6840 {
6841 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6842 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6843 }
6844
6845 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6846 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6847 { /* likely */ }
6848 else
6849 {
6850 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6851 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6852 }
6853
6854 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6855 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6856 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
6857 { /* likely */ }
6858 else
6859 {
6860 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6861 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6862 }
6863
6864 /* Update our cache of the guest physical address of the shadow VMCS. */
6865 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6866 }
6867
6868 /*
6869 * MSR bitmap.
6870 */
6871 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6872 {
6873 /* Read the MSR bitmap. */
6874 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6875 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
6876 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
6877 if (RT_SUCCESS(rc))
6878 { /* likely */ }
6879 else
6880 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6881 }
6882
6883 NOREF(pszFailure);
6884 NOREF(pszInstr);
6885 return VINF_SUCCESS;
6886}
6887
6888
6889/**
6890 * Loads the guest-state as part of VM-entry.
6891 *
6892 * @returns VBox status code.
6893 * @param pVCpu The cross context virtual CPU structure.
6894 * @param pszInstr The VMX instruction name (for logging purposes).
6895 *
6896 * @remarks This must be done after all the necessary steps prior to loading of
6897 * guest-state (e.g. checking various VMCS state).
6898 */
6899IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6900{
6901 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
6902 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6903
6904 /* Load guest segment registers. */
6905 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6906
6907 /*
6908 * Load guest RIP, RSP and RFLAGS.
6909 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6910 */
6911 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6912 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6913 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6914 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6915
6916 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6917 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6918 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6919
6920 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
6921 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6922
6923 /* Load VMX related structures and state referenced by the VMCS. */
6924 int rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
6925 if (rc == VINF_SUCCESS)
6926 { /* likely */ }
6927 else
6928 return rc;
6929
6930 NOREF(pszInstr);
6931 return VINF_SUCCESS;
6932}
6933
6934
6935/**
6936 * Returns whether there are is a pending debug exception on VM-entry.
6937 *
6938 * @param pVCpu The cross context virtual CPU structure.
6939 * @param pszInstr The VMX instruction name (for logging purposes).
6940 */
6941IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6942{
6943 /*
6944 * Pending debug exceptions.
6945 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6946 */
6947 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6948 Assert(pVmcs);
6949
6950 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6951 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6952 if (fPendingDbgXcpt)
6953 {
6954 uint8_t uEntryIntInfoType;
6955 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6956 if (fEntryVectoring)
6957 {
6958 switch (uEntryIntInfoType)
6959 {
6960 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6961 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6962 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6963 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6964 fPendingDbgXcpt = false;
6965 break;
6966
6967 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6968 {
6969 /*
6970 * Whether the pending debug exception for software exceptions other than
6971 * #BP and #OF is delivered after injecting the exception or is discard
6972 * is CPU implementation specific. We will discard them (easier).
6973 */
6974 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6975 if ( uVector != X86_XCPT_BP
6976 && uVector != X86_XCPT_OF)
6977 fPendingDbgXcpt = false;
6978 RT_FALL_THRU();
6979 }
6980 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6981 {
6982 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6983 fPendingDbgXcpt = false;
6984 break;
6985 }
6986 }
6987 }
6988 else
6989 {
6990 /*
6991 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6992 * pending debug exception is held pending or is discarded is CPU implementation
6993 * specific. We will discard them (easier).
6994 */
6995 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6996 fPendingDbgXcpt = false;
6997
6998 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
6999 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7000 fPendingDbgXcpt = false;
7001 }
7002 }
7003
7004 NOREF(pszInstr);
7005 return fPendingDbgXcpt;
7006}
7007
7008
7009/**
7010 * Set up the monitor-trap flag (MTF).
7011 *
7012 * @param pVCpu The cross context virtual CPU structure.
7013 * @param pszInstr The VMX instruction name (for logging purposes).
7014 */
7015IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
7016{
7017 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7018 Assert(pVmcs);
7019 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7020 {
7021 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7022 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7023 }
7024 else
7025 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7026 NOREF(pszInstr);
7027}
7028
7029
7030/**
7031 * Sets up NMI-window exiting.
7032 *
7033 * @param pVCpu The cross context virtual CPU structure.
7034 * @param pszInstr The VMX instruction name (for logging purposes).
7035 */
7036IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
7037{
7038 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7039 Assert(pVmcs);
7040 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7041 {
7042 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7043 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7044 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7045 }
7046 else
7047 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7048 NOREF(pszInstr);
7049}
7050
7051
7052/**
7053 * Sets up interrupt-window exiting.
7054 *
7055 * @param pVCpu The cross context virtual CPU structure.
7056 * @param pszInstr The VMX instruction name (for logging purposes).
7057 */
7058IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
7059{
7060 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7061 Assert(pVmcs);
7062 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7063 {
7064 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7065 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7066 }
7067 else
7068 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7069 NOREF(pszInstr);
7070}
7071
7072
7073/**
7074 * Set up the VMX-preemption timer.
7075 *
7076 * @param pVCpu The cross context virtual CPU structure.
7077 * @param pszInstr The VMX instruction name (for logging purposes).
7078 */
7079IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
7080{
7081 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7082 Assert(pVmcs);
7083 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7084 {
7085 /*
7086 * If the timer is 0, we must cause a VM-exit before executing the first
7087 * nested-guest instruction. So we can flag as though the timer has already
7088 * expired and we will check and cause a VM-exit at the right priority elsewhere
7089 * in the code.
7090 */
7091 uint64_t uEntryTick;
7092 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7093 if (uPreemptTimer)
7094 {
7095 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7096 AssertRC(rc);
7097 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7098 }
7099 else
7100 {
7101 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7102 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7103 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7104 }
7105
7106 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7107 }
7108 else
7109 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7110
7111 NOREF(pszInstr);
7112}
7113
7114
7115/**
7116 * Injects an event using TRPM given a VM-entry interruption info. and related
7117 * fields.
7118 *
7119 * @param pVCpu The cross context virtual CPU structure.
7120 * @param pszInstr The VMX instruction name (for logging purposes).
7121 * @param uEntryIntInfo The VM-entry interruption info.
7122 * @param uErrCode The error code associated with the event if any.
7123 * @param cbInstr The VM-entry instruction length (for software
7124 * interrupts and software exceptions). Pass 0
7125 * otherwise.
7126 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7127 */
7128IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7129 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7130{
7131 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7132
7133 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7134 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7135 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7136
7137 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7138
7139 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7140 AssertRC(rc);
7141 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7142
7143 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7144 {
7145 TRPMSetErrorCode(pVCpu, uErrCode);
7146 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7147 }
7148
7149 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7150 {
7151 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7152 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7153 }
7154 else
7155 {
7156 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7157 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7158 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7159 {
7160 TRPMSetInstrLength(pVCpu, cbInstr);
7161 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7162 }
7163 }
7164
7165 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7166 {
7167 TRPMSetTrapDueToIcebp(pVCpu);
7168 Log(("%s: Injecting: icebp\n", pszInstr));
7169 }
7170
7171 NOREF(pszInstr);
7172}
7173
7174
7175/**
7176 * Performs event injection (if any) as part of VM-entry.
7177 *
7178 * @param pVCpu The cross context virtual CPU structure.
7179 * @param pszInstr The VMX instruction name (for logging purposes).
7180 */
7181IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7182{
7183 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7184
7185 /*
7186 * Inject events.
7187 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7188 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7189 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7190 * the actually delivery of this event.
7191 *
7192 * See Intel spec. 26.5 "Event Injection".
7193 */
7194 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7195 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7196
7197 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7198 if (fEntryIntInfoValid)
7199 {
7200 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7201 {
7202 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7203 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7204 }
7205 else
7206 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7207 pVCpu->cpum.GstCtx.cr2);
7208
7209 /*
7210 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7211 *
7212 * However, we do it here on VM-entry as well because while it isn't visible to guest
7213 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7214 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7215 *
7216 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7217 */
7218 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7219 }
7220 else
7221 {
7222 /*
7223 * Inject any pending guest debug exception.
7224 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7225 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7226 */
7227 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7228 if (fPendingDbgXcpt)
7229 {
7230 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7231 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7232 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7233 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7234 0 /* GCPtrFaultAddress */);
7235 }
7236 }
7237
7238 NOREF(pszInstr);
7239}
7240
7241
7242/**
7243 * Initializes all read-only VMCS fields as part of VM-entry.
7244 *
7245 * @param pVCpu The cross context virtual CPU structure.
7246 */
7247IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7248{
7249 /*
7250 * Any VMCS field which we do not establish on every VM-exit but may potentially
7251 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7252 * specified to be undefined, needs to be initialized here.
7253 *
7254 * Thus, it is especially important to clear the Exit qualification field
7255 * since it must be zero for VM-exits where it is not used. Similarly, the
7256 * VM-exit interruption information field's valid bit needs to be cleared for
7257 * the same reasons.
7258 */
7259 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7260 Assert(pVmcs);
7261
7262 /* 16-bit (none currently). */
7263 /* 32-bit. */
7264 pVmcs->u32RoVmInstrError = 0;
7265 pVmcs->u32RoExitReason = 0;
7266 pVmcs->u32RoExitIntInfo = 0;
7267 pVmcs->u32RoExitIntErrCode = 0;
7268 pVmcs->u32RoIdtVectoringInfo = 0;
7269 pVmcs->u32RoIdtVectoringErrCode = 0;
7270 pVmcs->u32RoExitInstrLen = 0;
7271 pVmcs->u32RoExitInstrInfo = 0;
7272
7273 /* 64-bit. */
7274 pVmcs->u64RoGuestPhysAddr.u = 0;
7275
7276 /* Natural-width. */
7277 pVmcs->u64RoExitQual.u = 0;
7278 pVmcs->u64RoIoRcx.u = 0;
7279 pVmcs->u64RoIoRsi.u = 0;
7280 pVmcs->u64RoIoRdi.u = 0;
7281 pVmcs->u64RoIoRip.u = 0;
7282 pVmcs->u64RoGuestLinearAddr.u = 0;
7283}
7284
7285
7286/**
7287 * VMLAUNCH/VMRESUME instruction execution worker.
7288 *
7289 * @returns Strict VBox status code.
7290 * @param pVCpu The cross context virtual CPU structure.
7291 * @param cbInstr The instruction length in bytes.
7292 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7293 * VMXINSTRID_VMRESUME).
7294 *
7295 * @remarks Common VMX instruction checks are already expected to by the caller,
7296 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7297 */
7298IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7299{
7300# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7301 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7302 return VINF_EM_RAW_EMULATE_INSTR;
7303# else
7304 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7305 || uInstrId == VMXINSTRID_VMRESUME);
7306 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7307
7308 /* Nested-guest intercept. */
7309 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7310 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7311
7312 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7313
7314 /*
7315 * Basic VM-entry checks.
7316 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7317 * The checks following that do not have to follow a specific order.
7318 *
7319 * See Intel spec. 26.1 "Basic VM-entry Checks".
7320 */
7321
7322 /* CPL. */
7323 if (pVCpu->iem.s.uCpl == 0)
7324 { /* likely */ }
7325 else
7326 {
7327 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7328 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7329 return iemRaiseGeneralProtectionFault0(pVCpu);
7330 }
7331
7332 /* Current VMCS valid. */
7333 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7334 { /* likely */ }
7335 else
7336 {
7337 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7338 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7339 iemVmxVmFailInvalid(pVCpu);
7340 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7341 return VINF_SUCCESS;
7342 }
7343
7344 /* Current VMCS is not a shadow VMCS. */
7345 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7346 { /* likely */ }
7347 else
7348 {
7349 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7350 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7351 iemVmxVmFailInvalid(pVCpu);
7352 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7353 return VINF_SUCCESS;
7354 }
7355
7356 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7357 * use block-by-STI here which is not quite correct. */
7358 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7359 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7360 { /* likely */ }
7361 else
7362 {
7363 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7364 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7365 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7366 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7367 return VINF_SUCCESS;
7368 }
7369
7370 if (uInstrId == VMXINSTRID_VMLAUNCH)
7371 {
7372 /* VMLAUNCH with non-clear VMCS. */
7373 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7374 { /* likely */ }
7375 else
7376 {
7377 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7378 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7379 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7380 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7381 return VINF_SUCCESS;
7382 }
7383 }
7384 else
7385 {
7386 /* VMRESUME with non-launched VMCS. */
7387 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7388 { /* likely */ }
7389 else
7390 {
7391 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7392 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7393 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7394 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7395 return VINF_SUCCESS;
7396 }
7397 }
7398
7399 /*
7400 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7401 * while entering VMX non-root mode. We do some of this while checking VM-execution
7402 * controls. The nested hypervisor should not make assumptions and cannot expect
7403 * predictable behavior if changes to these structures are made in guest memory while
7404 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7405 * modify them anyway as we cache them in host memory.
7406 *
7407 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7408 */
7409 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7410 Assert(pVmcs);
7411 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7412
7413 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7414 if (RT_SUCCESS(rc))
7415 {
7416 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7417 if (RT_SUCCESS(rc))
7418 {
7419 /*
7420 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7421 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7422 * ones that may occur during VM-entry below).
7423 */
7424 iemVmxVmentryInitReadOnlyFields(pVCpu);
7425
7426 /*
7427 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7428 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7429 * VM-exit when required.
7430 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7431 */
7432 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7433
7434 bool fPdpesMapped;
7435 rc = iemVmxVmentryCheckGuestState(pVCpu, &fPdpesMapped, pszInstr);
7436 if (RT_SUCCESS(rc))
7437 {
7438 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7439 if (RT_SUCCESS(rc))
7440 {
7441 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7442 if (RT_SUCCESS(rc))
7443 {
7444 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7445
7446 /* VMLAUNCH instruction must update the VMCS launch state. */
7447 if (uInstrId == VMXINSTRID_VMLAUNCH)
7448 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7449
7450 /* Perform the VMX transition (PGM updates). */
7451 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu, fPdpesMapped);
7452 if (rcStrict == VINF_SUCCESS)
7453 { /* likely */ }
7454 else if (RT_SUCCESS(rcStrict))
7455 {
7456 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7457 VBOXSTRICTRC_VAL(rcStrict)));
7458 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7459 }
7460 else
7461 {
7462 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7463 return rcStrict;
7464 }
7465
7466 /* Paranoia. */
7467 Assert(rcStrict == VINF_SUCCESS);
7468
7469 /* We've now entered nested-guest execution. */
7470 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7471
7472 /*
7473 * The priority of potential VM-exits during VM-entry is important.
7474 * The priorities of VM-exits and events are listed from highest
7475 * to lowest as follows:
7476 *
7477 * 1. Event injection.
7478 * 2. Trap on task-switch (T flag set in TSS).
7479 * 3. TPR below threshold / APIC-write.
7480 * 4. SMI, INIT.
7481 * 5. MTF exit.
7482 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7483 * 7. VMX-preemption timer.
7484 * 9. NMI-window exit.
7485 * 10. NMI injection.
7486 * 11. Interrupt-window exit.
7487 * 12. Virtual-interrupt injection.
7488 * 13. Interrupt injection.
7489 * 14. Process next instruction (fetch, decode, execute).
7490 */
7491
7492 /* Setup VMX-preemption timer. */
7493 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7494
7495 /* Setup monitor-trap flag. */
7496 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7497
7498 /* Setup NMI-window exiting. */
7499 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7500
7501 /* Setup interrupt-window exiting. */
7502 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7503
7504 /*
7505 * Inject any event that the nested hypervisor wants to inject.
7506 * Note! We cannot immediately perform the event injection here as we may have
7507 * pending PGM operations to perform due to switching page tables and/or
7508 * mode.
7509 */
7510 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7511
7512# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7513 /* Reschedule to IEM-only execution of the nested-guest. */
7514 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7515 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7516 if (rcSched != VINF_SUCCESS)
7517 iemSetPassUpStatus(pVCpu, rcSched);
7518# endif
7519
7520 /* Finally, done. */
7521 Log3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",
7522 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7523 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7524 pVCpu->cpum.GstCtx.msrEFER));
7525 return VINF_SUCCESS;
7526 }
7527 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7528 pVmcs->u64RoExitQual.u);
7529 }
7530 }
7531 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7532 pVmcs->u64RoExitQual.u);
7533 }
7534
7535 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7536 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7537 return VINF_SUCCESS;
7538 }
7539
7540 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7541 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7542 return VINF_SUCCESS;
7543# endif
7544}
7545
7546
7547/**
7548 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7549 * (causes a VM-exit) or not.
7550 *
7551 * @returns @c true if the instruction is intercepted, @c false otherwise.
7552 * @param pVCpu The cross context virtual CPU structure.
7553 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7554 * VMX_EXIT_WRMSR).
7555 * @param idMsr The MSR.
7556 */
7557IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7558{
7559 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7560 Assert( uExitReason == VMX_EXIT_RDMSR
7561 || uExitReason == VMX_EXIT_WRMSR);
7562
7563 /* Consult the MSR bitmap if the feature is supported. */
7564 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7565 Assert(pVmcs);
7566 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7567 {
7568 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7569 if (uExitReason == VMX_EXIT_RDMSR)
7570 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7571 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7572 }
7573
7574 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7575 return true;
7576}
7577
7578
7579/**
7580 * VMREAD instruction execution worker that does not perform any validation checks.
7581 *
7582 * Callers are expected to have performed the necessary checks and to ensure the
7583 * VMREAD will succeed.
7584 *
7585 * @param pVmcs Pointer to the virtual VMCS.
7586 * @param pu64Dst Where to write the VMCS value.
7587 * @param u64VmcsField The VMCS field.
7588 *
7589 * @remarks May be called with interrupts disabled.
7590 */
7591IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7592{
7593 VMXVMCSFIELD VmcsField;
7594 VmcsField.u = u64VmcsField;
7595 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7596 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7597 uint8_t const uWidthType = (uWidth << 2) | uType;
7598 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7599 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7600 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7601 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
7602 uWidth, uType, uIndex, uIndex));
7603 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7604
7605 /*
7606 * Read the VMCS component based on the field's effective width.
7607 *
7608 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7609 * indicates high bits (little endian).
7610 *
7611 * Note! The caller is responsible to trim the result and update registers
7612 * or memory locations are required. Here we just zero-extend to the largest
7613 * type (i.e. 64-bits).
7614 */
7615 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7616 uint8_t const *pbField = pbVmcs + offField;
7617 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7618 switch (uEffWidth)
7619 {
7620 case VMX_VMCSFIELD_WIDTH_64BIT:
7621 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7622 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7623 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7624 }
7625}
7626
7627
7628/**
7629 * VMREAD common (memory/register) instruction execution worker.
7630 *
7631 * @returns Strict VBox status code.
7632 * @param pVCpu The cross context virtual CPU structure.
7633 * @param cbInstr The instruction length in bytes.
7634 * @param pu64Dst Where to write the VMCS value (only updated when
7635 * VINF_SUCCESS is returned).
7636 * @param u64VmcsField The VMCS field.
7637 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7638 * NULL.
7639 */
7640IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7641 PCVMXVEXITINFO pExitInfo)
7642{
7643 /* Nested-guest intercept. */
7644 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7645 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7646 {
7647 if (pExitInfo)
7648 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7649 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7650 }
7651
7652 /* CPL. */
7653 if (pVCpu->iem.s.uCpl == 0)
7654 { /* likely */ }
7655 else
7656 {
7657 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7658 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7659 return iemRaiseGeneralProtectionFault0(pVCpu);
7660 }
7661
7662 /* VMCS pointer in root mode. */
7663 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7664 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7665 { /* likely */ }
7666 else
7667 {
7668 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7669 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7670 iemVmxVmFailInvalid(pVCpu);
7671 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7672 return VINF_SUCCESS;
7673 }
7674
7675 /* VMCS-link pointer in non-root mode. */
7676 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7677 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7678 { /* likely */ }
7679 else
7680 {
7681 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7682 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7683 iemVmxVmFailInvalid(pVCpu);
7684 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7685 return VINF_SUCCESS;
7686 }
7687
7688 /* Supported VMCS field. */
7689 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7690 { /* likely */ }
7691 else
7692 {
7693 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7694 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7695 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7696 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7697 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7698 return VINF_SUCCESS;
7699 }
7700
7701 /*
7702 * Reading from the current or shadow VMCS.
7703 */
7704 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7705 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7706 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7707 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7708 return VINF_SUCCESS;
7709}
7710
7711
7712/**
7713 * VMREAD (64-bit register) instruction execution worker.
7714 *
7715 * @returns Strict VBox status code.
7716 * @param pVCpu The cross context virtual CPU structure.
7717 * @param cbInstr The instruction length in bytes.
7718 * @param pu64Dst Where to store the VMCS field's value.
7719 * @param u64VmcsField The VMCS field.
7720 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7721 * NULL.
7722 */
7723IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7724 PCVMXVEXITINFO pExitInfo)
7725{
7726 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7727 if (rcStrict == VINF_SUCCESS)
7728 {
7729 iemVmxVmreadSuccess(pVCpu, cbInstr);
7730 return VINF_SUCCESS;
7731 }
7732
7733 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7734 return rcStrict;
7735}
7736
7737
7738/**
7739 * VMREAD (32-bit register) instruction execution worker.
7740 *
7741 * @returns Strict VBox status code.
7742 * @param pVCpu The cross context virtual CPU structure.
7743 * @param cbInstr The instruction length in bytes.
7744 * @param pu32Dst Where to store the VMCS field's value.
7745 * @param u32VmcsField The VMCS field.
7746 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7747 * NULL.
7748 */
7749IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7750 PCVMXVEXITINFO pExitInfo)
7751{
7752 uint64_t u64Dst;
7753 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7754 if (rcStrict == VINF_SUCCESS)
7755 {
7756 *pu32Dst = u64Dst;
7757 iemVmxVmreadSuccess(pVCpu, cbInstr);
7758 return VINF_SUCCESS;
7759 }
7760
7761 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7762 return rcStrict;
7763}
7764
7765
7766/**
7767 * VMREAD (memory) instruction execution worker.
7768 *
7769 * @returns Strict VBox status code.
7770 * @param pVCpu The cross context virtual CPU structure.
7771 * @param cbInstr The instruction length in bytes.
7772 * @param iEffSeg The effective segment register to use with @a u64Val.
7773 * Pass UINT8_MAX if it is a register access.
7774 * @param GCPtrDst The guest linear address to store the VMCS field's
7775 * value.
7776 * @param u64VmcsField The VMCS field.
7777 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7778 * NULL.
7779 */
7780IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7781 PCVMXVEXITINFO pExitInfo)
7782{
7783 uint64_t u64Dst;
7784 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7785 if (rcStrict == VINF_SUCCESS)
7786 {
7787 /*
7788 * Write the VMCS field's value to the location specified in guest-memory.
7789 */
7790 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7791 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7792 else
7793 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7794 if (rcStrict == VINF_SUCCESS)
7795 {
7796 iemVmxVmreadSuccess(pVCpu, cbInstr);
7797 return VINF_SUCCESS;
7798 }
7799
7800 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7801 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7802 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7803 return rcStrict;
7804 }
7805
7806 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7807 return rcStrict;
7808}
7809
7810
7811/**
7812 * VMWRITE instruction execution worker that does not perform any validation
7813 * checks.
7814 *
7815 * Callers are expected to have performed the necessary checks and to ensure the
7816 * VMWRITE will succeed.
7817 *
7818 * @param pVmcs Pointer to the virtual VMCS.
7819 * @param u64Val The value to write.
7820 * @param u64VmcsField The VMCS field.
7821 *
7822 * @remarks May be called with interrupts disabled.
7823 */
7824IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7825{
7826 VMXVMCSFIELD VmcsField;
7827 VmcsField.u = u64VmcsField;
7828 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7829 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7830 uint8_t const uWidthType = (uWidth << 2) | uType;
7831 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7832 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7833 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7834 Assert(offField < VMX_V_VMCS_SIZE);
7835 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7836
7837 /*
7838 * Write the VMCS component based on the field's effective width.
7839 *
7840 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7841 * indicates high bits (little endian).
7842 */
7843 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7844 uint8_t *pbField = pbVmcs + offField;
7845 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7846 switch (uEffWidth)
7847 {
7848 case VMX_VMCSFIELD_WIDTH_64BIT:
7849 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7850 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7851 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7852 }
7853}
7854
7855
7856/**
7857 * VMWRITE instruction execution worker.
7858 *
7859 * @returns Strict VBox status code.
7860 * @param pVCpu The cross context virtual CPU structure.
7861 * @param cbInstr The instruction length in bytes.
7862 * @param iEffSeg The effective segment register to use with @a u64Val.
7863 * Pass UINT8_MAX if it is a register access.
7864 * @param u64Val The value to write (or guest linear address to the
7865 * value), @a iEffSeg will indicate if it's a memory
7866 * operand.
7867 * @param u64VmcsField The VMCS field.
7868 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7869 * NULL.
7870 */
7871IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7872 PCVMXVEXITINFO pExitInfo)
7873{
7874 /* Nested-guest intercept. */
7875 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7876 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7877 {
7878 if (pExitInfo)
7879 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7880 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7881 }
7882
7883 /* CPL. */
7884 if (pVCpu->iem.s.uCpl == 0)
7885 { /* likely */ }
7886 else
7887 {
7888 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7889 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7890 return iemRaiseGeneralProtectionFault0(pVCpu);
7891 }
7892
7893 /* VMCS pointer in root mode. */
7894 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7895 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7896 { /* likely */ }
7897 else
7898 {
7899 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7900 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7901 iemVmxVmFailInvalid(pVCpu);
7902 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7903 return VINF_SUCCESS;
7904 }
7905
7906 /* VMCS-link pointer in non-root mode. */
7907 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7908 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7909 { /* likely */ }
7910 else
7911 {
7912 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7913 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7914 iemVmxVmFailInvalid(pVCpu);
7915 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7916 return VINF_SUCCESS;
7917 }
7918
7919 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7920 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7921 if (!fIsRegOperand)
7922 {
7923 /* Read the value from the specified guest memory location. */
7924 VBOXSTRICTRC rcStrict;
7925 RTGCPTR const GCPtrVal = u64Val;
7926 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7927 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7928 else
7929 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7930 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7931 {
7932 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7933 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7934 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7935 return rcStrict;
7936 }
7937 }
7938 else
7939 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7940
7941 /* Supported VMCS field. */
7942 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7943 { /* likely */ }
7944 else
7945 {
7946 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7947 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7948 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7949 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7950 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7951 return VINF_SUCCESS;
7952 }
7953
7954 /* Read-only VMCS field. */
7955 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7956 if ( !fIsFieldReadOnly
7957 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7958 { /* likely */ }
7959 else
7960 {
7961 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7962 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7963 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7964 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7965 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7966 return VINF_SUCCESS;
7967 }
7968
7969 /*
7970 * Write to the current or shadow VMCS.
7971 */
7972 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7973 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7974 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7975 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7976 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7977
7978 /* Notify HM that the VMCS content might have changed. */
7979 if (!fInVmxNonRootMode)
7980 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7981
7982 iemVmxVmSucceed(pVCpu);
7983 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7984 return VINF_SUCCESS;
7985}
7986
7987
7988/**
7989 * VMCLEAR instruction execution worker.
7990 *
7991 * @returns Strict VBox status code.
7992 * @param pVCpu The cross context virtual CPU structure.
7993 * @param cbInstr The instruction length in bytes.
7994 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7995 * @param GCPtrVmcs The linear address of the VMCS pointer.
7996 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7997 *
7998 * @remarks Common VMX instruction checks are already expected to by the caller,
7999 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8000 */
8001IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8002 PCVMXVEXITINFO pExitInfo)
8003{
8004 /* Nested-guest intercept. */
8005 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8006 {
8007 if (pExitInfo)
8008 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8009 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8010 }
8011
8012 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8013
8014 /* CPL. */
8015 if (pVCpu->iem.s.uCpl == 0)
8016 { /* likely */ }
8017 else
8018 {
8019 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8020 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8021 return iemRaiseGeneralProtectionFault0(pVCpu);
8022 }
8023
8024 /* Get the VMCS pointer from the location specified by the source memory operand. */
8025 RTGCPHYS GCPhysVmcs;
8026 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8027 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8028 { /* likely */ }
8029 else
8030 {
8031 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8032 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8033 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8034 return rcStrict;
8035 }
8036
8037 /* VMCS pointer alignment. */
8038 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8039 { /* likely */ }
8040 else
8041 {
8042 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8043 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8044 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8045 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8046 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8047 return VINF_SUCCESS;
8048 }
8049
8050 /* VMCS physical-address width limits. */
8051 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8052 { /* likely */ }
8053 else
8054 {
8055 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8056 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8057 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8058 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8059 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8060 return VINF_SUCCESS;
8061 }
8062
8063 /* VMCS is not the VMXON region. */
8064 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8065 { /* likely */ }
8066 else
8067 {
8068 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8069 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8070 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8071 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8072 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8073 return VINF_SUCCESS;
8074 }
8075
8076 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8077 restriction imposed by our implementation. */
8078 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8079 { /* likely */ }
8080 else
8081 {
8082 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8083 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8084 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8085 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8086 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8087 return VINF_SUCCESS;
8088 }
8089
8090 /*
8091 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8092 *
8093 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8094 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8095 * to 'clear'.
8096 */
8097 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8098 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8099 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8100 {
8101 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8102 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8103 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8104 }
8105 else
8106 {
8107 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8108 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8109 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8110 if (RT_FAILURE(rcStrict))
8111 return rcStrict;
8112 }
8113
8114 iemVmxVmSucceed(pVCpu);
8115 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8116 return VINF_SUCCESS;
8117}
8118
8119
8120/**
8121 * VMPTRST instruction execution worker.
8122 *
8123 * @returns Strict VBox status code.
8124 * @param pVCpu The cross context virtual CPU structure.
8125 * @param cbInstr The instruction length in bytes.
8126 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8127 * @param GCPtrVmcs The linear address of where to store the current VMCS
8128 * pointer.
8129 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8130 *
8131 * @remarks Common VMX instruction checks are already expected to by the caller,
8132 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8133 */
8134IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8135 PCVMXVEXITINFO pExitInfo)
8136{
8137 /* Nested-guest intercept. */
8138 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8139 {
8140 if (pExitInfo)
8141 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8142 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8143 }
8144
8145 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8146
8147 /* CPL. */
8148 if (pVCpu->iem.s.uCpl == 0)
8149 { /* likely */ }
8150 else
8151 {
8152 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8153 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8154 return iemRaiseGeneralProtectionFault0(pVCpu);
8155 }
8156
8157 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8158 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8159 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8160 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8161 {
8162 iemVmxVmSucceed(pVCpu);
8163 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8164 return rcStrict;
8165 }
8166
8167 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8168 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8169 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8170 return rcStrict;
8171}
8172
8173
8174/**
8175 * VMPTRLD instruction execution worker.
8176 *
8177 * @returns Strict VBox status code.
8178 * @param pVCpu The cross context virtual CPU structure.
8179 * @param cbInstr The instruction length in bytes.
8180 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8181 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8182 *
8183 * @remarks Common VMX instruction checks are already expected to by the caller,
8184 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8185 */
8186IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8187 PCVMXVEXITINFO pExitInfo)
8188{
8189 /* Nested-guest intercept. */
8190 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8191 {
8192 if (pExitInfo)
8193 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8194 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8195 }
8196
8197 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8198
8199 /* CPL. */
8200 if (pVCpu->iem.s.uCpl == 0)
8201 { /* likely */ }
8202 else
8203 {
8204 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8205 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8206 return iemRaiseGeneralProtectionFault0(pVCpu);
8207 }
8208
8209 /* Get the VMCS pointer from the location specified by the source memory operand. */
8210 RTGCPHYS GCPhysVmcs;
8211 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8212 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8213 { /* likely */ }
8214 else
8215 {
8216 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8217 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8218 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8219 return rcStrict;
8220 }
8221
8222 /* VMCS pointer alignment. */
8223 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8224 { /* likely */ }
8225 else
8226 {
8227 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8228 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8229 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8230 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8231 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8232 return VINF_SUCCESS;
8233 }
8234
8235 /* VMCS physical-address width limits. */
8236 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8237 { /* likely */ }
8238 else
8239 {
8240 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8241 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8242 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8243 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8244 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8245 return VINF_SUCCESS;
8246 }
8247
8248 /* VMCS is not the VMXON region. */
8249 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8250 { /* likely */ }
8251 else
8252 {
8253 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8254 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8255 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8256 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8257 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8258 return VINF_SUCCESS;
8259 }
8260
8261 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8262 restriction imposed by our implementation. */
8263 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8264 { /* likely */ }
8265 else
8266 {
8267 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8268 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8269 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8270 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8271 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8272 return VINF_SUCCESS;
8273 }
8274
8275 /* Read just the VMCS revision from the VMCS. */
8276 VMXVMCSREVID VmcsRevId;
8277 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8278 if (RT_SUCCESS(rc))
8279 { /* likely */ }
8280 else
8281 {
8282 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8283 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8284 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8285 return rc;
8286 }
8287
8288 /*
8289 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8290 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8291 */
8292 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8293 && ( !VmcsRevId.n.fIsShadowVmcs
8294 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8295 { /* likely */ }
8296 else
8297 {
8298 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8299 {
8300 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8301 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8302 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8303 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8304 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8305 return VINF_SUCCESS;
8306 }
8307
8308 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8309 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8310 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8311 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8312 return VINF_SUCCESS;
8313 }
8314
8315 /*
8316 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8317 * the cache of an existing, current VMCS back to guest memory before loading a new,
8318 * different current VMCS.
8319 */
8320 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8321 {
8322 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8323 {
8324 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8325 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8326 }
8327
8328 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8329 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8330 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8331 if (RT_SUCCESS(rc))
8332 {
8333 /* Notify HM that a new, current VMCS is loaded. */
8334 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8335 }
8336 else
8337 {
8338 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8339 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8340 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8341 return rc;
8342 }
8343 }
8344
8345 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8346 iemVmxVmSucceed(pVCpu);
8347 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8348 return VINF_SUCCESS;
8349}
8350
8351
8352/**
8353 * INVVPID instruction execution worker.
8354 *
8355 * @returns Strict VBox status code.
8356 * @param pVCpu The cross context virtual CPU structure.
8357 * @param cbInstr The instruction length in bytes.
8358 * @param iEffSeg The segment of the invvpid descriptor.
8359 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8360 * @param u64InvvpidType The invalidation type.
8361 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8362 * NULL.
8363 *
8364 * @remarks Common VMX instruction checks are already expected to by the caller,
8365 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8366 */
8367IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8368 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8369{
8370 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8371 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8372 return iemRaiseUndefinedOpcode(pVCpu);
8373
8374 /* Nested-guest intercept. */
8375 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8376 {
8377 if (pExitInfo)
8378 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8379 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8380 }
8381
8382 /* CPL. */
8383 if (pVCpu->iem.s.uCpl != 0)
8384 {
8385 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8386 return iemRaiseGeneralProtectionFault0(pVCpu);
8387 }
8388
8389 /*
8390 * Validate INVVPID invalidation type.
8391 *
8392 * The instruction specifies exactly ONE of the supported invalidation types.
8393 *
8394 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8395 * supported. In theory, it's possible for a CPU to not support flushing individual
8396 * addresses but all the other types or any other combination. We do not take any
8397 * shortcuts here by assuming the types we currently expose to the guest.
8398 */
8399 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8400 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8401 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8402 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8403 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8404 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8405 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8406 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8407 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8408 { /* likely */ }
8409 else
8410 {
8411 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8412 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8413 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8414 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8415 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8416 return VINF_SUCCESS;
8417 }
8418
8419 /*
8420 * Fetch the invvpid descriptor from guest memory.
8421 */
8422 RTUINT128U uDesc;
8423 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8424 if (rcStrict == VINF_SUCCESS)
8425 {
8426 /*
8427 * Validate the descriptor.
8428 */
8429 if (uDesc.s.Lo > 0xfff)
8430 {
8431 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8432 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8433 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8434 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8435 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8436 return VINF_SUCCESS;
8437 }
8438
8439 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8440 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8441 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8442 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8443 switch (u64InvvpidType)
8444 {
8445 case VMXTLBFLUSHVPID_INDIV_ADDR:
8446 {
8447 if (uVpid != 0)
8448 {
8449 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8450 {
8451 /* Invalidate mappings for the linear address tagged with VPID. */
8452 /** @todo PGM support for VPID? Currently just flush everything. */
8453 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8454 iemVmxVmSucceed(pVCpu);
8455 }
8456 else
8457 {
8458 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8459 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8460 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8461 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8462 }
8463 }
8464 else
8465 {
8466 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8467 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8468 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8469 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8470 }
8471 break;
8472 }
8473
8474 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8475 {
8476 if (uVpid != 0)
8477 {
8478 /* Invalidate all mappings with VPID. */
8479 /** @todo PGM support for VPID? Currently just flush everything. */
8480 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8481 iemVmxVmSucceed(pVCpu);
8482 }
8483 else
8484 {
8485 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8486 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8487 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8488 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8489 }
8490 break;
8491 }
8492
8493 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8494 {
8495 /* Invalidate all mappings with non-zero VPIDs. */
8496 /** @todo PGM support for VPID? Currently just flush everything. */
8497 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8498 iemVmxVmSucceed(pVCpu);
8499 break;
8500 }
8501
8502 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8503 {
8504 if (uVpid != 0)
8505 {
8506 /* Invalidate all mappings with VPID except global translations. */
8507 /** @todo PGM support for VPID? Currently just flush everything. */
8508 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8509 iemVmxVmSucceed(pVCpu);
8510 }
8511 else
8512 {
8513 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8514 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8515 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8516 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8517 }
8518 break;
8519 }
8520 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8521 }
8522 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8523 }
8524 return rcStrict;
8525}
8526
8527
8528/**
8529 * VMXON instruction execution worker.
8530 *
8531 * @returns Strict VBox status code.
8532 * @param pVCpu The cross context virtual CPU structure.
8533 * @param cbInstr The instruction length in bytes.
8534 * @param iEffSeg The effective segment register to use with @a
8535 * GCPtrVmxon.
8536 * @param GCPtrVmxon The linear address of the VMXON pointer.
8537 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8538 *
8539 * @remarks Common VMX instruction checks are already expected to by the caller,
8540 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8541 */
8542IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8543 PCVMXVEXITINFO pExitInfo)
8544{
8545 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8546 {
8547 /* CPL. */
8548 if (pVCpu->iem.s.uCpl == 0)
8549 { /* likely */ }
8550 else
8551 {
8552 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8553 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8554 return iemRaiseGeneralProtectionFault0(pVCpu);
8555 }
8556
8557 /* A20M (A20 Masked) mode. */
8558 if (PGMPhysIsA20Enabled(pVCpu))
8559 { /* likely */ }
8560 else
8561 {
8562 Log(("vmxon: A20M mode -> #GP(0)\n"));
8563 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8564 return iemRaiseGeneralProtectionFault0(pVCpu);
8565 }
8566
8567 /* CR0. */
8568 {
8569 /* CR0 MB1 bits. */
8570 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8571 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8572 { /* likely */ }
8573 else
8574 {
8575 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8576 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8577 return iemRaiseGeneralProtectionFault0(pVCpu);
8578 }
8579
8580 /* CR0 MBZ bits. */
8581 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8582 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8583 { /* likely */ }
8584 else
8585 {
8586 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8587 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8588 return iemRaiseGeneralProtectionFault0(pVCpu);
8589 }
8590 }
8591
8592 /* CR4. */
8593 {
8594 /* CR4 MB1 bits. */
8595 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8596 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8597 { /* likely */ }
8598 else
8599 {
8600 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8601 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8602 return iemRaiseGeneralProtectionFault0(pVCpu);
8603 }
8604
8605 /* CR4 MBZ bits. */
8606 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8607 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8608 { /* likely */ }
8609 else
8610 {
8611 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8612 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8613 return iemRaiseGeneralProtectionFault0(pVCpu);
8614 }
8615 }
8616
8617 /* Feature control MSR's LOCK and VMXON bits. */
8618 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
8619 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8620 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8621 { /* likely */ }
8622 else
8623 {
8624 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8625 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8626 return iemRaiseGeneralProtectionFault0(pVCpu);
8627 }
8628
8629 /* Get the VMXON pointer from the location specified by the source memory operand. */
8630 RTGCPHYS GCPhysVmxon;
8631 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8632 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8633 { /* likely */ }
8634 else
8635 {
8636 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8637 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8638 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8639 return rcStrict;
8640 }
8641
8642 /* VMXON region pointer alignment. */
8643 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8644 { /* likely */ }
8645 else
8646 {
8647 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8648 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8649 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8650 iemVmxVmFailInvalid(pVCpu);
8651 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8652 return VINF_SUCCESS;
8653 }
8654
8655 /* VMXON physical-address width limits. */
8656 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8657 { /* likely */ }
8658 else
8659 {
8660 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8661 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8662 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8663 iemVmxVmFailInvalid(pVCpu);
8664 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8665 return VINF_SUCCESS;
8666 }
8667
8668 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8669 restriction imposed by our implementation. */
8670 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8671 { /* likely */ }
8672 else
8673 {
8674 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8675 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8676 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8677 iemVmxVmFailInvalid(pVCpu);
8678 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8679 return VINF_SUCCESS;
8680 }
8681
8682 /* Read the VMCS revision ID from the VMXON region. */
8683 VMXVMCSREVID VmcsRevId;
8684 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8685 if (RT_SUCCESS(rc))
8686 { /* likely */ }
8687 else
8688 {
8689 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8690 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8691 return rc;
8692 }
8693
8694 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8695 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8696 { /* likely */ }
8697 else
8698 {
8699 /* Revision ID mismatch. */
8700 if (!VmcsRevId.n.fIsShadowVmcs)
8701 {
8702 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8703 VmcsRevId.n.u31RevisionId));
8704 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8705 iemVmxVmFailInvalid(pVCpu);
8706 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8707 return VINF_SUCCESS;
8708 }
8709
8710 /* Shadow VMCS disallowed. */
8711 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8712 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8713 iemVmxVmFailInvalid(pVCpu);
8714 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8715 return VINF_SUCCESS;
8716 }
8717
8718 /*
8719 * Record that we're in VMX operation, block INIT, block and disable A20M.
8720 */
8721 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8722 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8723 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8724
8725 /* Clear address-range monitoring. */
8726 EMMonitorWaitClear(pVCpu);
8727 /** @todo NSTVMX: Intel PT. */
8728
8729 iemVmxVmSucceed(pVCpu);
8730 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8731 return VINF_SUCCESS;
8732 }
8733 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8734 {
8735 /* Nested-guest intercept. */
8736 if (pExitInfo)
8737 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8738 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8739 }
8740
8741 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8742
8743 /* CPL. */
8744 if (pVCpu->iem.s.uCpl > 0)
8745 {
8746 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8747 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8748 return iemRaiseGeneralProtectionFault0(pVCpu);
8749 }
8750
8751 /* VMXON when already in VMX root mode. */
8752 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8753 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8754 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8755 return VINF_SUCCESS;
8756}
8757
8758
8759/**
8760 * Implements 'VMXOFF'.
8761 *
8762 * @remarks Common VMX instruction checks are already expected to by the caller,
8763 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8764 */
8765IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8766{
8767 /* Nested-guest intercept. */
8768 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8769 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8770
8771 /* CPL. */
8772 if (pVCpu->iem.s.uCpl == 0)
8773 { /* likely */ }
8774 else
8775 {
8776 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8777 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8778 return iemRaiseGeneralProtectionFault0(pVCpu);
8779 }
8780
8781 /* Dual monitor treatment of SMIs and SMM. */
8782 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8783 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8784 { /* likely */ }
8785 else
8786 {
8787 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8788 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8789 return VINF_SUCCESS;
8790 }
8791
8792 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8793 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8794 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8795
8796 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8797 { /** @todo NSTVMX: Unblock SMI. */ }
8798
8799 EMMonitorWaitClear(pVCpu);
8800 /** @todo NSTVMX: Unblock and enable A20M. */
8801
8802 iemVmxVmSucceed(pVCpu);
8803 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8804 return VINF_SUCCESS;
8805}
8806
8807
8808/**
8809 * Implements 'VMXON'.
8810 */
8811IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8812{
8813 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8814}
8815
8816
8817/**
8818 * Implements 'VMLAUNCH'.
8819 */
8820IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8821{
8822 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8823}
8824
8825
8826/**
8827 * Implements 'VMRESUME'.
8828 */
8829IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8830{
8831 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8832}
8833
8834
8835/**
8836 * Implements 'VMPTRLD'.
8837 */
8838IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8839{
8840 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8841}
8842
8843
8844/**
8845 * Implements 'VMPTRST'.
8846 */
8847IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8848{
8849 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8850}
8851
8852
8853/**
8854 * Implements 'VMCLEAR'.
8855 */
8856IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8857{
8858 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8859}
8860
8861
8862/**
8863 * Implements 'VMWRITE' register.
8864 */
8865IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8866{
8867 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8868}
8869
8870
8871/**
8872 * Implements 'VMWRITE' memory.
8873 */
8874IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8875{
8876 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8877}
8878
8879
8880/**
8881 * Implements 'VMREAD' register (64-bit).
8882 */
8883IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8884{
8885 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8886}
8887
8888
8889/**
8890 * Implements 'VMREAD' register (32-bit).
8891 */
8892IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8893{
8894 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8895}
8896
8897
8898/**
8899 * Implements 'VMREAD' memory, 64-bit register.
8900 */
8901IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8902{
8903 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8904}
8905
8906
8907/**
8908 * Implements 'VMREAD' memory, 32-bit register.
8909 */
8910IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8911{
8912 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8913}
8914
8915
8916/**
8917 * Implements 'INVVPID'.
8918 */
8919IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8920{
8921 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8922}
8923
8924
8925/**
8926 * Implements VMX's implementation of PAUSE.
8927 */
8928IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8929{
8930 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8931 {
8932 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8933 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8934 return rcStrict;
8935 }
8936
8937 /*
8938 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8939 * a VM-exit, the instruction operates normally.
8940 */
8941 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8942 return VINF_SUCCESS;
8943}
8944
8945#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8946
8947
8948/**
8949 * Implements 'VMCALL'.
8950 */
8951IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8952{
8953#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8954 /* Nested-guest intercept. */
8955 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8956 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8957#endif
8958
8959 /* Join forces with vmmcall. */
8960 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8961}
8962
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