VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 92561

Last change on this file since 92561 was 92546, checked in by vboxsync, 3 years ago

VMM/IEM: Nested VMX: bugref:10092 Just check for RT_SUCCESS for PGMGstMapPaePdpesAtCr3.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 92546 2021-11-22 12:13:32Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165
166/*********************************************************************************************************************************
167* Global Variables *
168*********************************************************************************************************************************/
169/** @todo NSTVMX: The following VM-exit intercepts are pending:
170 * VMX_EXIT_IO_SMI
171 * VMX_EXIT_SMI
172 * VMX_EXIT_GETSEC
173 * VMX_EXIT_RSM
174 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176 * VMX_EXIT_EPT_VIOLATION
177 * VMX_EXIT_EPT_MISCONFIG
178 * VMX_EXIT_INVEPT
179 * VMX_EXIT_RDRAND
180 * VMX_EXIT_VMFUNC
181 * VMX_EXIT_ENCLS
182 * VMX_EXIT_RDSEED
183 * VMX_EXIT_PML_FULL
184 * VMX_EXIT_XSAVES
185 * VMX_EXIT_XRSTORS
186 */
187/**
188 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
189 *
190 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
191 * second dimension is the Index, see VMXVMCSFIELD.
192 */
193uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
194{
195 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
196 {
197 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
198 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
199 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
200 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
201 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203 /* 27 */ UINT16_MAX,
204 },
205 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206 {
207 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 26-27 */ UINT16_MAX, UINT16_MAX
227 },
228 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
233 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
234 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
235 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
236 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
237 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
239 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
240 },
241 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
242 {
243 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
244 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
245 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
246 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
247 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
248 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
249 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
250 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
251 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
252 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
253 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
254 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
255 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
256 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
257 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
258 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
259 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
260 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
261 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
262 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
263 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
264 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
265 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
266 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
267 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
268 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
269 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
270 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
271 },
272 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
273 {
274 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
275 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
276 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
277 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
278 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
279 },
280 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
281 {
282 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
283 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
284 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
285 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
286 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
287 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
288 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
289 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
290 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
291 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
292 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
293 /* 11 */ UINT16_MAX,
294 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
295 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
296 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
297 },
298 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
299 {
300 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
301 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
302 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
303 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
304 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
307 },
308 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
309 {
310 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
311 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
312 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
313 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
314 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
315 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
316 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
317 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
318 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
319 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
320 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
321 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
322 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
323 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
324 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
325 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
326 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
327 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
328 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
329 /* 26-27 */ UINT16_MAX, UINT16_MAX
330 },
331 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
332 {
333 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
334 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
335 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
336 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
337 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
338 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
339 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
340 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
341 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
342 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
343 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
344 },
345 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
346 {
347 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
348 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
349 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
350 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
351 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
352 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
353 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
354 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
355 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
356 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
357 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
358 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
359 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
360 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
361 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
362 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
363 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
364 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
365 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
366 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
367 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
368 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
369 /* 22 */ UINT16_MAX,
370 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
371 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
372 },
373 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
374 {
375 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
376 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
377 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
378 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
379 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
380 },
381 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
382 {
383 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
384 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
385 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
386 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
387 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
388 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
389 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
390 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
391 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
392 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
393 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
394 },
395 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
396 {
397 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
398 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
399 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
400 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
401 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
402 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
403 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
404 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
405 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
406 },
407 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
408 {
409 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
410 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
411 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
412 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
413 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
414 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
415 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
416 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
417 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
418 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
419 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
420 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
421 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
422 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
423 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
424 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
425 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
426 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
427 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
428 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
429 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
430 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
431 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
432 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
433 },
434 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
435 {
436 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
437 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
438 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
439 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
440 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
441 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
442 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
443 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
444 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
445 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
446 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
447 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
448 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
449 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
450 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
451 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
452 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
453 }
454};
455
456
457/**
458 * Gets a host selector from the VMCS.
459 *
460 * @param pVmcs Pointer to the virtual VMCS.
461 * @param iSelReg The index of the segment register (X86_SREG_XXX).
462 */
463DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
464{
465 Assert(iSegReg < X86_SREG_COUNT);
466 RTSEL HostSel;
467 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
468 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
469 uint8_t const uWidthType = (uWidth << 2) | uType;
470 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
471 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
472 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
473 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
474 uint8_t const *pbField = pbVmcs + offField;
475 HostSel = *(uint16_t *)pbField;
476 return HostSel;
477}
478
479
480/**
481 * Sets a guest segment register in the VMCS.
482 *
483 * @param pVmcs Pointer to the virtual VMCS.
484 * @param iSegReg The index of the segment register (X86_SREG_XXX).
485 * @param pSelReg Pointer to the segment register.
486 */
487IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
488{
489 Assert(pSelReg);
490 Assert(iSegReg < X86_SREG_COUNT);
491
492 /* Selector. */
493 {
494 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
495 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
496 uint8_t const uWidthType = (uWidth << 2) | uType;
497 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
498 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
499 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
500 uint8_t *pbVmcs = (uint8_t *)pVmcs;
501 uint8_t *pbField = pbVmcs + offField;
502 *(uint16_t *)pbField = pSelReg->Sel;
503 }
504
505 /* Limit. */
506 {
507 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
508 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
509 uint8_t const uWidthType = (uWidth << 2) | uType;
510 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
511 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
512 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
513 uint8_t *pbVmcs = (uint8_t *)pVmcs;
514 uint8_t *pbField = pbVmcs + offField;
515 *(uint32_t *)pbField = pSelReg->u32Limit;
516 }
517
518 /* Base. */
519 {
520 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
521 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
522 uint8_t const uWidthType = (uWidth << 2) | uType;
523 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
524 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
525 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
526 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
527 uint8_t const *pbField = pbVmcs + offField;
528 *(uint64_t *)pbField = pSelReg->u64Base;
529 }
530
531 /* Attributes. */
532 {
533 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
534 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
535 | X86DESCATTR_UNUSABLE;
536 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
537 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
538 uint8_t const uWidthType = (uWidth << 2) | uType;
539 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
540 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
541 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
542 uint8_t *pbVmcs = (uint8_t *)pVmcs;
543 uint8_t *pbField = pbVmcs + offField;
544 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
545 }
546}
547
548
549/**
550 * Gets a guest segment register from the VMCS.
551 *
552 * @returns VBox status code.
553 * @param pVmcs Pointer to the virtual VMCS.
554 * @param iSegReg The index of the segment register (X86_SREG_XXX).
555 * @param pSelReg Where to store the segment register (only updated when
556 * VINF_SUCCESS is returned).
557 *
558 * @remarks Warning! This does not validate the contents of the retrieved segment
559 * register.
560 */
561IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
562{
563 Assert(pSelReg);
564 Assert(iSegReg < X86_SREG_COUNT);
565
566 /* Selector. */
567 uint16_t u16Sel;
568 {
569 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
570 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571 uint8_t const uWidthType = (uWidth << 2) | uType;
572 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
573 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
576 uint8_t const *pbField = pbVmcs + offField;
577 u16Sel = *(uint16_t *)pbField;
578 }
579
580 /* Limit. */
581 uint32_t u32Limit;
582 {
583 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
584 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585 uint8_t const uWidthType = (uWidth << 2) | uType;
586 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
587 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
590 uint8_t const *pbField = pbVmcs + offField;
591 u32Limit = *(uint32_t *)pbField;
592 }
593
594 /* Base. */
595 uint64_t u64Base;
596 {
597 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
598 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
599 uint8_t const uWidthType = (uWidth << 2) | uType;
600 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
601 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
602 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
603 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
604 uint8_t const *pbField = pbVmcs + offField;
605 u64Base = *(uint64_t *)pbField;
606 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
607 }
608
609 /* Attributes. */
610 uint32_t u32Attr;
611 {
612 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
613 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
614 uint8_t const uWidthType = (uWidth << 2) | uType;
615 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
616 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
617 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
618 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
619 uint8_t const *pbField = pbVmcs + offField;
620 u32Attr = *(uint32_t *)pbField;
621 }
622
623 pSelReg->Sel = u16Sel;
624 pSelReg->ValidSel = u16Sel;
625 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
626 pSelReg->u32Limit = u32Limit;
627 pSelReg->u64Base = u64Base;
628 pSelReg->Attr.u = u32Attr;
629 return VINF_SUCCESS;
630}
631
632
633/**
634 * Converts an IEM exception event type to a VMX event type.
635 *
636 * @returns The VMX event type.
637 * @param uVector The interrupt / exception vector.
638 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
639 */
640DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
641{
642 /* Paranoia (callers may use these interchangeably). */
643 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
644 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
645 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
646 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
647 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
648 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
649 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
650 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
651 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
652 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
653 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
654 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
655
656 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
657 {
658 if (uVector == X86_XCPT_NMI)
659 return VMX_EXIT_INT_INFO_TYPE_NMI;
660 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
661 }
662
663 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
664 {
665 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
666 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
667 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
668 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
669 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
670 }
671
672 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
673 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
674}
675
676
677/**
678 * Sets the Exit qualification VMCS field.
679 *
680 * @param pVCpu The cross context virtual CPU structure.
681 * @param u64ExitQual The Exit qualification.
682 */
683DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
684{
685 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
686}
687
688
689/**
690 * Sets the VM-exit interruption information field.
691 *
692 * @param pVCpu The cross context virtual CPU structure.
693 * @param uExitIntInfo The VM-exit interruption information.
694 */
695DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
696{
697 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
698}
699
700
701/**
702 * Sets the VM-exit interruption error code.
703 *
704 * @param pVCpu The cross context virtual CPU structure.
705 * @param uErrCode The error code.
706 */
707DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
708{
709 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
710}
711
712
713/**
714 * Sets the IDT-vectoring information field.
715 *
716 * @param pVCpu The cross context virtual CPU structure.
717 * @param uIdtVectorInfo The IDT-vectoring information.
718 */
719DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
720{
721 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
722}
723
724
725/**
726 * Sets the IDT-vectoring error code field.
727 *
728 * @param pVCpu The cross context virtual CPU structure.
729 * @param uErrCode The error code.
730 */
731DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
732{
733 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
734}
735
736
737/**
738 * Sets the VM-exit guest-linear address VMCS field.
739 *
740 * @param pVCpu The cross context virtual CPU structure.
741 * @param uGuestLinearAddr The VM-exit guest-linear address.
742 */
743DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
744{
745 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
746}
747
748
749/**
750 * Sets the VM-exit guest-physical address VMCS field.
751 *
752 * @param pVCpu The cross context virtual CPU structure.
753 * @param uGuestPhysAddr The VM-exit guest-physical address.
754 */
755DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
756{
757 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
758}
759
760
761/**
762 * Sets the VM-exit instruction length VMCS field.
763 *
764 * @param pVCpu The cross context virtual CPU structure.
765 * @param cbInstr The VM-exit instruction length in bytes.
766 *
767 * @remarks Callers may clear this field to 0. Hence, this function does not check
768 * the validity of the instruction length.
769 */
770DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
771{
772 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
773}
774
775
776/**
777 * Sets the VM-exit instruction info. VMCS field.
778 *
779 * @param pVCpu The cross context virtual CPU structure.
780 * @param uExitInstrInfo The VM-exit instruction information.
781 */
782DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
783{
784 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
785}
786
787
788/**
789 * Sets the guest pending-debug exceptions field.
790 *
791 * @param pVCpu The cross context virtual CPU structure.
792 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
793 */
794DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
795{
796 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
797 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
798}
799
800
801/**
802 * Implements VMSucceed for VMX instruction success.
803 *
804 * @param pVCpu The cross context virtual CPU structure.
805 */
806DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
807{
808 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
809}
810
811
812/**
813 * Implements VMFailInvalid for VMX instruction failure.
814 *
815 * @param pVCpu The cross context virtual CPU structure.
816 */
817DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
818{
819 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
820}
821
822
823/**
824 * Implements VMFail for VMX instruction failure.
825 *
826 * @param pVCpu The cross context virtual CPU structure.
827 * @param enmInsErr The VM instruction error.
828 */
829DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
830{
831 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
832}
833
834
835/**
836 * Checks if the given auto-load/store MSR area count is valid for the
837 * implementation.
838 *
839 * @returns @c true if it's within the valid limit, @c false otherwise.
840 * @param pVCpu The cross context virtual CPU structure.
841 * @param uMsrCount The MSR area count to check.
842 */
843DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
844{
845 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
846 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
847 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
848 if (uMsrCount <= cMaxSupportedMsrs)
849 return true;
850 return false;
851}
852
853
854/**
855 * Flushes the current VMCS contents back to guest memory.
856 *
857 * @returns VBox status code.
858 * @param pVCpu The cross context virtual CPU structure.
859 */
860DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
861{
862 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
863 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
864 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
865 return rc;
866}
867
868
869/**
870 * Populates the current VMCS contents from guest memory.
871 *
872 * @returns VBox status code.
873 * @param pVCpu The cross context virtual CPU structure.
874 */
875DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
876{
877 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
878 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
879 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
880 return rc;
881}
882
883
884/**
885 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
886 *
887 * @param pVCpu The cross context virtual CPU structure.
888 */
889DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
890{
891 iemVmxVmSucceed(pVCpu);
892 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
893}
894
895
896/**
897 * Gets the instruction diagnostic for segment base checks during VM-entry of a
898 * nested-guest.
899 *
900 * @param iSegReg The segment index (X86_SREG_XXX).
901 */
902IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
903{
904 switch (iSegReg)
905 {
906 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
907 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
908 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
909 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
910 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
911 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
912 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
913 }
914}
915
916
917/**
918 * Gets the instruction diagnostic for segment base checks during VM-entry of a
919 * nested-guest that is in Virtual-8086 mode.
920 *
921 * @param iSegReg The segment index (X86_SREG_XXX).
922 */
923IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
924{
925 switch (iSegReg)
926 {
927 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
928 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
929 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
930 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
931 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
932 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
933 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
934 }
935}
936
937
938/**
939 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
940 * nested-guest that is in Virtual-8086 mode.
941 *
942 * @param iSegReg The segment index (X86_SREG_XXX).
943 */
944IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
945{
946 switch (iSegReg)
947 {
948 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
949 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
950 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
951 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
952 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
953 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
954 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
955 }
956}
957
958
959/**
960 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
961 * nested-guest that is in Virtual-8086 mode.
962 *
963 * @param iSegReg The segment index (X86_SREG_XXX).
964 */
965IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
966{
967 switch (iSegReg)
968 {
969 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
970 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
971 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
972 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
973 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
974 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
975 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
976 }
977}
978
979
980/**
981 * Gets the instruction diagnostic for segment attributes reserved bits failure
982 * during VM-entry of a nested-guest.
983 *
984 * @param iSegReg The segment index (X86_SREG_XXX).
985 */
986IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
987{
988 switch (iSegReg)
989 {
990 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
991 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
992 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
993 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
994 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
995 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
996 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
997 }
998}
999
1000
1001/**
1002 * Gets the instruction diagnostic for segment attributes descriptor-type
1003 * (code/segment or system) failure during VM-entry of a nested-guest.
1004 *
1005 * @param iSegReg The segment index (X86_SREG_XXX).
1006 */
1007IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1008{
1009 switch (iSegReg)
1010 {
1011 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1012 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1013 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1014 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1015 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1016 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1017 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1018 }
1019}
1020
1021
1022/**
1023 * Gets the instruction diagnostic for segment attributes descriptor-type
1024 * (code/segment or system) failure during VM-entry of a nested-guest.
1025 *
1026 * @param iSegReg The segment index (X86_SREG_XXX).
1027 */
1028IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1029{
1030 switch (iSegReg)
1031 {
1032 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1033 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1034 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1035 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1036 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1037 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1038 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1039 }
1040}
1041
1042
1043/**
1044 * Gets the instruction diagnostic for segment attribute granularity failure during
1045 * VM-entry of a nested-guest.
1046 *
1047 * @param iSegReg The segment index (X86_SREG_XXX).
1048 */
1049IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1050{
1051 switch (iSegReg)
1052 {
1053 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1054 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1055 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1056 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1057 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1058 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1059 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1060 }
1061}
1062
1063/**
1064 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1065 * VM-entry of a nested-guest.
1066 *
1067 * @param iSegReg The segment index (X86_SREG_XXX).
1068 */
1069IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1070{
1071 switch (iSegReg)
1072 {
1073 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1074 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1075 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1076 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1077 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1078 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1079 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1080 }
1081}
1082
1083
1084/**
1085 * Gets the instruction diagnostic for segment attribute type accessed failure
1086 * during VM-entry of a nested-guest.
1087 *
1088 * @param iSegReg The segment index (X86_SREG_XXX).
1089 */
1090IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1091{
1092 switch (iSegReg)
1093 {
1094 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1095 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1096 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1097 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1098 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1099 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1100 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1101 }
1102}
1103
1104
1105/**
1106 * Saves the guest control registers, debug registers and some MSRs are part of
1107 * VM-exit.
1108 *
1109 * @param pVCpu The cross context virtual CPU structure.
1110 */
1111IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1112{
1113 /*
1114 * Saves the guest control registers, debug registers and some MSRs.
1115 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1116 */
1117 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1118
1119 /* Save control registers. */
1120 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1121 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1122 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1123
1124 /* Save SYSENTER CS, ESP, EIP. */
1125 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1126 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1127 {
1128 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1129 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1130 }
1131 else
1132 {
1133 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1134 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1135 }
1136
1137 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1138 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1139 {
1140 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1141 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1142 }
1143
1144 /* Save PAT MSR. */
1145 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1146 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1147
1148 /* Save EFER MSR. */
1149 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1150 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1151
1152 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1153 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1154
1155 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1156}
1157
1158
1159/**
1160 * Saves the guest force-flags in preparation of entering the nested-guest.
1161 *
1162 * @param pVCpu The cross context virtual CPU structure.
1163 */
1164IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1165{
1166 /* We shouldn't be called multiple times during VM-entry. */
1167 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1168
1169 /* MTF should not be set outside VMX non-root mode. */
1170 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1171
1172 /*
1173 * Preserve the required force-flags.
1174 *
1175 * We cache and clear force-flags that would affect the execution of the
1176 * nested-guest. Cached flags are then restored while returning to the guest
1177 * if necessary.
1178 *
1179 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1180 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1181 * instruction. Interrupt inhibition for any nested-guest instruction
1182 * is supplied by the guest-interruptibility state VMCS field and will
1183 * be set up as part of loading the guest state.
1184 *
1185 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1186 * successful VM-entry (due to invalid guest-state) need to continue
1187 * blocking NMIs if it was in effect before VM-entry.
1188 *
1189 * - MTF need not be preserved as it's used only in VMX non-root mode and
1190 * is supplied through the VM-execution controls.
1191 *
1192 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1193 * we will be able to generate interrupts that may cause VM-exits for
1194 * the nested-guest.
1195 */
1196 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1197}
1198
1199
1200/**
1201 * Restores the guest force-flags in preparation of exiting the nested-guest.
1202 *
1203 * @param pVCpu The cross context virtual CPU structure.
1204 */
1205IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1206{
1207 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1208 {
1209 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1210 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1211 }
1212}
1213
1214
1215/**
1216 * Performs the VMX transition to/from VMX non-root mode.
1217 *
1218 * @param pVCpu The cross context virtual CPU structure.
1219 * @param fPdpesMapped Whether the PAE PDPTEs (and PDPT) have been mapped.
1220*/
1221IEM_STATIC int iemVmxTransition(PVMCPUCC pVCpu, bool fPdpesMapped)
1222{
1223 /*
1224 * Inform PGM about paging mode changes.
1225 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1226 * see comment in iemMemPageTranslateAndCheckAccess().
1227 */
1228 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1229 true /* fForce */);
1230 AssertRCReturn(rc, rc);
1231
1232 /* Inform CPUM (recompiler), can later be removed. */
1233 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1234
1235 /*
1236 * Flush the TLB with new CR3. This is required in case the PGM mode change
1237 * above doesn't actually change anything.
1238 */
1239 if (rc == VINF_SUCCESS)
1240 {
1241 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* fGlobal */, fPdpesMapped);
1242 AssertRCReturn(rc, rc);
1243 }
1244
1245 /* Re-initialize IEM cache/state after the drastic mode switch. */
1246 iemReInitExec(pVCpu);
1247 return rc;
1248}
1249
1250
1251/**
1252 * Calculates the current VMX-preemption timer value.
1253 *
1254 * @returns The current VMX-preemption timer value.
1255 * @param pVCpu The cross context virtual CPU structure.
1256 */
1257IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1258{
1259 /*
1260 * Assume the following:
1261 * PreemptTimerShift = 5
1262 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1263 * EntryTick = 50000 (TSC at time of VM-entry)
1264 *
1265 * CurTick Delta PreemptTimerVal
1266 * ----------------------------------
1267 * 60000 10000 2
1268 * 80000 30000 1
1269 * 90000 40000 0 -> VM-exit.
1270 *
1271 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1272 * The saved VMX-preemption timer value is calculated as follows:
1273 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1274 * E.g.:
1275 * Delta = 10000
1276 * Tmp = 10000 / (2 * 10000) = 0.5
1277 * NewPt = 2 - 0.5 = 2
1278 * Delta = 30000
1279 * Tmp = 30000 / (2 * 10000) = 1.5
1280 * NewPt = 2 - 1.5 = 1
1281 * Delta = 40000
1282 * Tmp = 40000 / 20000 = 2
1283 * NewPt = 2 - 2 = 0
1284 */
1285 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1286 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1287 if (uVmcsPreemptVal > 0)
1288 {
1289 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1290 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1291 uint64_t const uDelta = uCurTick - uEntryTick;
1292 uint32_t const uPreemptTimer = uVmcsPreemptVal
1293 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1294 return uPreemptTimer;
1295 }
1296 return 0;
1297}
1298
1299
1300/**
1301 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1302 *
1303 * @param pVCpu The cross context virtual CPU structure.
1304 */
1305IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1306{
1307 /*
1308 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1309 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1310 */
1311 /* CS, SS, ES, DS, FS, GS. */
1312 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1313 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1314 {
1315 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1316 if (!pSelReg->Attr.n.u1Unusable)
1317 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1318 else
1319 {
1320 /*
1321 * For unusable segments the attributes are undefined except for CS and SS.
1322 * For the rest we don't bother preserving anything but the unusable bit.
1323 */
1324 switch (iSegReg)
1325 {
1326 case X86_SREG_CS:
1327 pVmcs->GuestCs = pSelReg->Sel;
1328 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1329 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1330 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1331 | X86DESCATTR_UNUSABLE);
1332 break;
1333
1334 case X86_SREG_SS:
1335 pVmcs->GuestSs = pSelReg->Sel;
1336 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1337 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1338 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1339 break;
1340
1341 case X86_SREG_DS:
1342 pVmcs->GuestDs = pSelReg->Sel;
1343 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1344 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1345 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1346 break;
1347
1348 case X86_SREG_ES:
1349 pVmcs->GuestEs = pSelReg->Sel;
1350 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1351 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1352 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1353 break;
1354
1355 case X86_SREG_FS:
1356 pVmcs->GuestFs = pSelReg->Sel;
1357 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1358 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1359 break;
1360
1361 case X86_SREG_GS:
1362 pVmcs->GuestGs = pSelReg->Sel;
1363 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1364 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1365 break;
1366 }
1367 }
1368 }
1369
1370 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1371 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1372 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1373 | X86DESCATTR_UNUSABLE;
1374 /* LDTR. */
1375 {
1376 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1377 pVmcs->GuestLdtr = pSelReg->Sel;
1378 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1379 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1380 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1381 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1382 }
1383
1384 /* TR. */
1385 {
1386 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1387 pVmcs->GuestTr = pSelReg->Sel;
1388 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1389 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1390 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1391 }
1392
1393 /* GDTR. */
1394 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1395 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1396
1397 /* IDTR. */
1398 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1399 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1400}
1401
1402
1403/**
1404 * Saves guest non-register state as part of VM-exit.
1405 *
1406 * @param pVCpu The cross context virtual CPU structure.
1407 * @param uExitReason The VM-exit reason.
1408 */
1409IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1410{
1411 /*
1412 * Save guest non-register state.
1413 * See Intel spec. 27.3.4 "Saving Non-Register State".
1414 */
1415 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1416
1417 /*
1418 * Activity state.
1419 * Most VM-exits will occur in the active state. However, if the first instruction
1420 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1421 * the VM-exit will be from the HLT activity state.
1422 *
1423 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1424 */
1425 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1426 * not? */
1427 EMSTATE const enmActivityState = EMGetState(pVCpu);
1428 switch (enmActivityState)
1429 {
1430 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1431 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1432 }
1433
1434 /*
1435 * Interruptibility-state.
1436 */
1437 /* NMI. */
1438 pVmcs->u32GuestIntrState = 0;
1439 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1440 {
1441 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1442 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1443 }
1444 else
1445 {
1446 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1447 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1448 }
1449
1450 /* Blocking-by-STI. */
1451 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1452 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1453 {
1454 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1455 * currently. */
1456 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1457 }
1458 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1459
1460 /*
1461 * Pending debug exceptions.
1462 *
1463 * For VM-exits where it is not applicable, we can safely zero out the field.
1464 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1465 */
1466 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1467 && uExitReason != VMX_EXIT_SMI
1468 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1469 && !VMXIsVmexitTrapLike(uExitReason))
1470 {
1471 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1472 * block-by-MovSS is in effect. */
1473 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1474 }
1475
1476 /*
1477 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1478 *
1479 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1480 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1481 */
1482 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1483 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1484 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1485
1486 /*
1487 * PAE PDPTEs.
1488 *
1489 * If EPT is enabled and PAE paging was used at the time of the VM-exit,
1490 * the PDPTEs are saved from the VMCS. Otherwise they're undefined but
1491 * we zero them for consistency.
1492 */
1493 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1494 {
1495 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
1496 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1497 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
1498 {
1499 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1500 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1501 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1502 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1503 }
1504 else
1505 {
1506 pVmcs->u64GuestPdpte0.u = 0;
1507 pVmcs->u64GuestPdpte1.u = 0;
1508 pVmcs->u64GuestPdpte2.u = 0;
1509 pVmcs->u64GuestPdpte3.u = 0;
1510 }
1511
1512 /* Clear PGM's copy of the EPT pointer for added safety. */
1513 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1514 }
1515 else
1516 {
1517 pVmcs->u64GuestPdpte0.u = 0;
1518 pVmcs->u64GuestPdpte1.u = 0;
1519 pVmcs->u64GuestPdpte2.u = 0;
1520 pVmcs->u64GuestPdpte3.u = 0;
1521 }
1522}
1523
1524
1525/**
1526 * Saves the guest-state as part of VM-exit.
1527 *
1528 * @returns VBox status code.
1529 * @param pVCpu The cross context virtual CPU structure.
1530 * @param uExitReason The VM-exit reason.
1531 */
1532IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1533{
1534 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1535 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1536
1537 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1538 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1539 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1540
1541 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1542}
1543
1544
1545/**
1546 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1547 *
1548 * @returns VBox status code.
1549 * @param pVCpu The cross context virtual CPU structure.
1550 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1551 */
1552IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1553{
1554 /*
1555 * Save guest MSRs.
1556 * See Intel spec. 27.4 "Saving MSRs".
1557 */
1558 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1559 const char * const pszFailure = "VMX-abort";
1560
1561 /*
1562 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1563 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1564 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1565 */
1566 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1567 if (!cMsrs)
1568 return VINF_SUCCESS;
1569
1570 /*
1571 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1572 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1573 * implementation causes a VMX-abort followed by a triple-fault.
1574 */
1575 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1576 if (fIsMsrCountValid)
1577 { /* likely */ }
1578 else
1579 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1580
1581 /*
1582 * Optimization if the nested hypervisor is using the same guest-physical page for both
1583 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1584 */
1585 PVMXAUTOMSR pMsrArea;
1586 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1587 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1588 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1589 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1590 else
1591 {
1592 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1593 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1594 if (RT_SUCCESS(rc))
1595 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1596 else
1597 {
1598 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1599 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1600 }
1601 }
1602
1603 /*
1604 * Update VM-exit MSR store area.
1605 */
1606 PVMXAUTOMSR pMsr = pMsrArea;
1607 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1608 {
1609 if ( !pMsr->u32Reserved
1610 && pMsr->u32Msr != MSR_IA32_SMBASE
1611 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1612 {
1613 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1614 if (rcStrict == VINF_SUCCESS)
1615 continue;
1616
1617 /*
1618 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1619 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1620 * recording the MSR index in the auxiliary info. field and indicated further by our
1621 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1622 * if possible, or come up with a better, generic solution.
1623 */
1624 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1625 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1626 ? kVmxVDiag_Vmexit_MsrStoreRing3
1627 : kVmxVDiag_Vmexit_MsrStore;
1628 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1629 }
1630 else
1631 {
1632 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1633 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1634 }
1635 }
1636
1637 /*
1638 * Commit the VM-exit MSR store are to guest memory.
1639 */
1640 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1641 if (RT_SUCCESS(rc))
1642 return VINF_SUCCESS;
1643
1644 NOREF(uExitReason);
1645 NOREF(pszFailure);
1646
1647 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1648 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1649}
1650
1651
1652/**
1653 * Performs a VMX abort (due to an fatal error during VM-exit).
1654 *
1655 * @returns Strict VBox status code.
1656 * @param pVCpu The cross context virtual CPU structure.
1657 * @param enmAbort The VMX abort reason.
1658 */
1659IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1660{
1661 /*
1662 * Perform the VMX abort.
1663 * See Intel spec. 27.7 "VMX Aborts".
1664 */
1665 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1666
1667 /* We don't support SMX yet. */
1668 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1669 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1670 {
1671 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1672 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1673 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1674 }
1675
1676 return VINF_EM_TRIPLE_FAULT;
1677}
1678
1679
1680/**
1681 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1682 *
1683 * @param pVCpu The cross context virtual CPU structure.
1684 */
1685IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1686{
1687 /*
1688 * Load host control registers, debug registers and MSRs.
1689 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1690 */
1691 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1692 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1693
1694 /* CR0. */
1695 {
1696 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1697 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1698 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1699 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1700 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1701 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1702 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1703
1704 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1705 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1706 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1707 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1708 }
1709
1710 /* CR4. */
1711 {
1712 /* CR4 fixed bits are not modified. */
1713 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1714 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1715 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1716 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1717 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1718 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1719 if (fHostInLongMode)
1720 uValidHostCr4 |= X86_CR4_PAE;
1721 else
1722 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1723
1724 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1725 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1726 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1727 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1728 }
1729
1730 /* CR3 (host value validated while checking host-state during VM-entry). */
1731 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1732
1733 /* DR7. */
1734 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1735
1736 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1737
1738 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1739 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1740 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1741 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1742
1743 /* FS, GS bases are loaded later while we load host segment registers. */
1744
1745 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1746 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1747 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1748 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1749 {
1750 if (fHostInLongMode)
1751 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1752 else
1753 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1754 }
1755
1756 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1757
1758 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1759 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1760 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1761
1762 /* We don't support IA32_BNDCFGS MSR yet. */
1763}
1764
1765
1766/**
1767 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1768 *
1769 * @param pVCpu The cross context virtual CPU structure.
1770 */
1771IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1772{
1773 /*
1774 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1775 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1776 *
1777 * Warning! Be careful to not touch fields that are reserved by VT-x,
1778 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1779 */
1780 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1781 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1782
1783 /* CS, SS, ES, DS, FS, GS. */
1784 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1785 {
1786 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1787 bool const fUnusable = RT_BOOL(HostSel == 0);
1788 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1789
1790 /* Selector. */
1791 pSelReg->Sel = HostSel;
1792 pSelReg->ValidSel = HostSel;
1793 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1794
1795 /* Limit. */
1796 pSelReg->u32Limit = 0xffffffff;
1797
1798 /* Base. */
1799 pSelReg->u64Base = 0;
1800
1801 /* Attributes. */
1802 if (iSegReg == X86_SREG_CS)
1803 {
1804 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1805 pSelReg->Attr.n.u1DescType = 1;
1806 pSelReg->Attr.n.u2Dpl = 0;
1807 pSelReg->Attr.n.u1Present = 1;
1808 pSelReg->Attr.n.u1Long = fHostInLongMode;
1809 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1810 pSelReg->Attr.n.u1Granularity = 1;
1811 Assert(!pSelReg->Attr.n.u1Unusable);
1812 Assert(!fUnusable);
1813 }
1814 else
1815 {
1816 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1817 pSelReg->Attr.n.u1DescType = 1;
1818 pSelReg->Attr.n.u2Dpl = 0;
1819 pSelReg->Attr.n.u1Present = 1;
1820 pSelReg->Attr.n.u1DefBig = 1;
1821 pSelReg->Attr.n.u1Granularity = 1;
1822 pSelReg->Attr.n.u1Unusable = fUnusable;
1823 }
1824 }
1825
1826 /* FS base. */
1827 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1828 || fHostInLongMode)
1829 {
1830 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1831 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1832 }
1833
1834 /* GS base. */
1835 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1836 || fHostInLongMode)
1837 {
1838 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1839 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1840 }
1841
1842 /* TR. */
1843 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1844 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1845 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1846 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1847 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1848 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1849 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1850 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1851 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1852 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1853 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1854 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1855 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1856
1857 /* LDTR (Warning! do not touch the base and limits here). */
1858 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1859 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1860 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1861 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1862
1863 /* GDTR. */
1864 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1865 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1866 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1867
1868 /* IDTR.*/
1869 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1870 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1871 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1872}
1873
1874
1875/**
1876 * Checks the host PAE PDPTEs assuming we are switching to a PAE mode host.
1877 *
1878 * @param pVCpu The cross context virtual CPU structure.
1879 * @param uExitReason The VMX instruction name (for logging purposes).
1880 *
1881 * @remarks Caller must ensure the preconditions are met before calling this
1882 * function as failure here will trigger VMX aborts!
1883 */
1884IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPUCC pVCpu, uint32_t uExitReason)
1885{
1886 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1887 const char * const pszFailure = "VMX-abort";
1888 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
1889 if (RT_SUCCESS(rc))
1890 return rc;
1891 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpte);
1892}
1893
1894
1895/**
1896 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1897 *
1898 * @returns VBox status code.
1899 * @param pVCpu The cross context virtual CPU structure.
1900 * @param uExitReason The VMX instruction name (for logging purposes).
1901 */
1902IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1903{
1904 /*
1905 * Load host MSRs.
1906 * See Intel spec. 27.6 "Loading MSRs".
1907 */
1908 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1909 const char * const pszFailure = "VMX-abort";
1910
1911 /*
1912 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1913 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1914 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1915 */
1916 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1917 if (!cMsrs)
1918 return VINF_SUCCESS;
1919
1920 /*
1921 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1922 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1923 * implementation causes a VMX-abort followed by a triple-fault.
1924 */
1925 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1926 if (fIsMsrCountValid)
1927 { /* likely */ }
1928 else
1929 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1930
1931 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1932 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1933 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1934 if (RT_SUCCESS(rc))
1935 {
1936 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1937 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1938 {
1939 if ( !pMsr->u32Reserved
1940 && pMsr->u32Msr != MSR_K8_FS_BASE
1941 && pMsr->u32Msr != MSR_K8_GS_BASE
1942 && pMsr->u32Msr != MSR_K6_EFER
1943 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1944 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1945 {
1946 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1947 if (rcStrict == VINF_SUCCESS)
1948 continue;
1949
1950 /*
1951 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1952 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1953 * recording the MSR index in the auxiliary info. field and indicated further by our
1954 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1955 * if possible, or come up with a better, generic solution.
1956 */
1957 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1958 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1959 ? kVmxVDiag_Vmexit_MsrLoadRing3
1960 : kVmxVDiag_Vmexit_MsrLoad;
1961 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1962 }
1963 else
1964 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1965 }
1966 }
1967 else
1968 {
1969 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1970 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1971 }
1972
1973 NOREF(uExitReason);
1974 NOREF(pszFailure);
1975 return VINF_SUCCESS;
1976}
1977
1978
1979/**
1980 * Loads the host state as part of VM-exit.
1981 *
1982 * @returns Strict VBox status code.
1983 * @param pVCpu The cross context virtual CPU structure.
1984 * @param uExitReason The VM-exit reason (for logging purposes).
1985 */
1986IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
1987{
1988 /*
1989 * Load host state.
1990 * See Intel spec. 27.5 "Loading Host State".
1991 */
1992 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1993 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1994
1995 /* We cannot return from a long-mode guest to a host that is not in long mode. */
1996 if ( CPUMIsGuestInLongMode(pVCpu)
1997 && !fHostInLongMode)
1998 {
1999 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2000 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2001 }
2002
2003 /*
2004 * Check host PAE PDPTEs prior to loading the host state.
2005 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2006 */
2007 bool fPdpesMapped;
2008 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2009 && !fHostInLongMode
2010 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2011 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2012 {
2013 int const rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2014 if (RT_FAILURE(rc))
2015 {
2016 Log(("VM-exit attempting to load invalid PDPTEs -> VMX-Abort\n"));
2017 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2018 }
2019 fPdpesMapped = true;
2020 }
2021 else
2022 fPdpesMapped = false;
2023
2024 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2025 iemVmxVmexitLoadHostSegRegs(pVCpu);
2026
2027 /*
2028 * Load host RIP, RSP and RFLAGS.
2029 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2030 */
2031 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2032 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2033 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2034
2035 /* Clear address range monitoring. */
2036 EMMonitorWaitClear(pVCpu);
2037
2038 /* Perform the VMX transition (PGM updates). */
2039 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu, fPdpesMapped);
2040 if (rcStrict == VINF_SUCCESS)
2041 { /* likely */ }
2042 else if (RT_SUCCESS(rcStrict))
2043 {
2044 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2045 uExitReason));
2046 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2047 }
2048 else
2049 {
2050 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2051 return VBOXSTRICTRC_VAL(rcStrict);
2052 }
2053
2054 Assert(rcStrict == VINF_SUCCESS);
2055
2056 /* Load MSRs from the VM-exit auto-load MSR area. */
2057 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2058 if (RT_FAILURE(rc))
2059 {
2060 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2061 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2062 }
2063 return VINF_SUCCESS;
2064}
2065
2066
2067/**
2068 * Gets VM-exit instruction information along with any displacement for an
2069 * instruction VM-exit.
2070 *
2071 * @returns The VM-exit instruction information.
2072 * @param pVCpu The cross context virtual CPU structure.
2073 * @param uExitReason The VM-exit reason.
2074 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2075 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2076 * NULL.
2077 */
2078IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2079{
2080 RTGCPTR GCPtrDisp;
2081 VMXEXITINSTRINFO ExitInstrInfo;
2082 ExitInstrInfo.u = 0;
2083
2084 /*
2085 * Get and parse the ModR/M byte from our decoded opcodes.
2086 */
2087 uint8_t bRm;
2088 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2089 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2090 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2091 {
2092 /*
2093 * ModR/M indicates register addressing.
2094 *
2095 * The primary/secondary register operands are reported in the iReg1 or iReg2
2096 * fields depending on whether it is a read/write form.
2097 */
2098 uint8_t idxReg1;
2099 uint8_t idxReg2;
2100 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2101 {
2102 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2103 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2104 }
2105 else
2106 {
2107 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2108 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2109 }
2110 ExitInstrInfo.All.u2Scaling = 0;
2111 ExitInstrInfo.All.iReg1 = idxReg1;
2112 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2113 ExitInstrInfo.All.fIsRegOperand = 1;
2114 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2115 ExitInstrInfo.All.iSegReg = 0;
2116 ExitInstrInfo.All.iIdxReg = 0;
2117 ExitInstrInfo.All.fIdxRegInvalid = 1;
2118 ExitInstrInfo.All.iBaseReg = 0;
2119 ExitInstrInfo.All.fBaseRegInvalid = 1;
2120 ExitInstrInfo.All.iReg2 = idxReg2;
2121
2122 /* Displacement not applicable for register addressing. */
2123 GCPtrDisp = 0;
2124 }
2125 else
2126 {
2127 /*
2128 * ModR/M indicates memory addressing.
2129 */
2130 uint8_t uScale = 0;
2131 bool fBaseRegValid = false;
2132 bool fIdxRegValid = false;
2133 uint8_t iBaseReg = 0;
2134 uint8_t iIdxReg = 0;
2135 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2136 {
2137 /*
2138 * Parse the ModR/M, displacement for 16-bit addressing mode.
2139 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2140 */
2141 uint16_t u16Disp = 0;
2142 uint8_t const offDisp = offModRm + sizeof(bRm);
2143 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2144 {
2145 /* Displacement without any registers. */
2146 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2147 }
2148 else
2149 {
2150 /* Register (index and base). */
2151 switch (bRm & X86_MODRM_RM_MASK)
2152 {
2153 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2154 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2155 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2156 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2157 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2158 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2159 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2160 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2161 }
2162
2163 /* Register + displacement. */
2164 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2165 {
2166 case 0: break;
2167 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2168 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2169 default:
2170 {
2171 /* Register addressing, handled at the beginning. */
2172 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2173 break;
2174 }
2175 }
2176 }
2177
2178 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2179 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2180 }
2181 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2182 {
2183 /*
2184 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2185 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2186 */
2187 uint32_t u32Disp = 0;
2188 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2189 {
2190 /* Displacement without any registers. */
2191 uint8_t const offDisp = offModRm + sizeof(bRm);
2192 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2193 }
2194 else
2195 {
2196 /* Register (and perhaps scale, index and base). */
2197 uint8_t offDisp = offModRm + sizeof(bRm);
2198 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2199 if (iBaseReg == 4)
2200 {
2201 /* An SIB byte follows the ModR/M byte, parse it. */
2202 uint8_t bSib;
2203 uint8_t const offSib = offModRm + sizeof(bRm);
2204 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2205
2206 /* A displacement may follow SIB, update its offset. */
2207 offDisp += sizeof(bSib);
2208
2209 /* Get the scale. */
2210 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2211
2212 /* Get the index register. */
2213 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2214 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2215
2216 /* Get the base register. */
2217 iBaseReg = bSib & X86_SIB_BASE_MASK;
2218 fBaseRegValid = true;
2219 if (iBaseReg == 5)
2220 {
2221 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2222 {
2223 /* Mod is 0 implies a 32-bit displacement with no base. */
2224 fBaseRegValid = false;
2225 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2226 }
2227 else
2228 {
2229 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2230 iBaseReg = X86_GREG_xBP;
2231 }
2232 }
2233 }
2234
2235 /* Register + displacement. */
2236 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2237 {
2238 case 0: /* Handled above */ break;
2239 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2240 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2241 default:
2242 {
2243 /* Register addressing, handled at the beginning. */
2244 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2245 break;
2246 }
2247 }
2248 }
2249
2250 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2251 }
2252 else
2253 {
2254 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2255
2256 /*
2257 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2258 * See Intel instruction spec. 2.2 "IA-32e Mode".
2259 */
2260 uint64_t u64Disp = 0;
2261 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2262 if (fRipRelativeAddr)
2263 {
2264 /*
2265 * RIP-relative addressing mode.
2266 *
2267 * The displacement is 32-bit signed implying an offset range of +/-2G.
2268 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2269 */
2270 uint8_t const offDisp = offModRm + sizeof(bRm);
2271 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2272 }
2273 else
2274 {
2275 uint8_t offDisp = offModRm + sizeof(bRm);
2276
2277 /*
2278 * Register (and perhaps scale, index and base).
2279 *
2280 * REX.B extends the most-significant bit of the base register. However, REX.B
2281 * is ignored while determining whether an SIB follows the opcode. Hence, we
2282 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2283 *
2284 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2285 */
2286 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2287 if (iBaseReg == 4)
2288 {
2289 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2290 uint8_t bSib;
2291 uint8_t const offSib = offModRm + sizeof(bRm);
2292 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2293
2294 /* Displacement may follow SIB, update its offset. */
2295 offDisp += sizeof(bSib);
2296
2297 /* Get the scale. */
2298 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2299
2300 /* Get the index. */
2301 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2302 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2303
2304 /* Get the base. */
2305 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2306 fBaseRegValid = true;
2307 if (iBaseReg == 5)
2308 {
2309 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2310 {
2311 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2312 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2313 }
2314 else
2315 {
2316 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2317 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2318 }
2319 }
2320 }
2321 iBaseReg |= pVCpu->iem.s.uRexB;
2322
2323 /* Register + displacement. */
2324 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2325 {
2326 case 0: /* Handled above */ break;
2327 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2328 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2329 default:
2330 {
2331 /* Register addressing, handled at the beginning. */
2332 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2333 break;
2334 }
2335 }
2336 }
2337
2338 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2339 }
2340
2341 /*
2342 * The primary or secondary register operand is reported in iReg2 depending
2343 * on whether the primary operand is in read/write form.
2344 */
2345 uint8_t idxReg2;
2346 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2347 {
2348 idxReg2 = bRm & X86_MODRM_RM_MASK;
2349 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2350 idxReg2 |= pVCpu->iem.s.uRexB;
2351 }
2352 else
2353 {
2354 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2355 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2356 idxReg2 |= pVCpu->iem.s.uRexReg;
2357 }
2358 ExitInstrInfo.All.u2Scaling = uScale;
2359 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2360 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2361 ExitInstrInfo.All.fIsRegOperand = 0;
2362 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2363 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2364 ExitInstrInfo.All.iIdxReg = iIdxReg;
2365 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2366 ExitInstrInfo.All.iBaseReg = iBaseReg;
2367 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2368 ExitInstrInfo.All.iReg2 = idxReg2;
2369 }
2370
2371 /*
2372 * Handle exceptions to the norm for certain instructions.
2373 * (e.g. some instructions convey an instruction identity in place of iReg2).
2374 */
2375 switch (uExitReason)
2376 {
2377 case VMX_EXIT_GDTR_IDTR_ACCESS:
2378 {
2379 Assert(VMXINSTRID_IS_VALID(uInstrId));
2380 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2381 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2382 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2383 break;
2384 }
2385
2386 case VMX_EXIT_LDTR_TR_ACCESS:
2387 {
2388 Assert(VMXINSTRID_IS_VALID(uInstrId));
2389 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2390 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2391 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2392 break;
2393 }
2394
2395 case VMX_EXIT_RDRAND:
2396 case VMX_EXIT_RDSEED:
2397 {
2398 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2399 break;
2400 }
2401 }
2402
2403 /* Update displacement and return the constructed VM-exit instruction information field. */
2404 if (pGCPtrDisp)
2405 *pGCPtrDisp = GCPtrDisp;
2406
2407 return ExitInstrInfo.u;
2408}
2409
2410
2411/**
2412 * VMX VM-exit handler.
2413 *
2414 * @returns Strict VBox status code.
2415 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2416 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2417 * triple-fault.
2418 *
2419 * @param pVCpu The cross context virtual CPU structure.
2420 * @param uExitReason The VM-exit reason.
2421 * @param u64ExitQual The Exit qualification.
2422 */
2423IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2424{
2425# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2426 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2427 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2428 return VERR_IEM_IPE_7;
2429# else
2430 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2431
2432 /*
2433 * Import all the guest-CPU state.
2434 *
2435 * HM on returning to guest execution would have to reset up a whole lot of state
2436 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2437 * the state and flag reloading the entire state on re-entry. So import the entire
2438 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2439 */
2440 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2441
2442 /*
2443 * Ensure VM-entry interruption information valid bit is cleared.
2444 *
2445 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2446 * by invalid-guest state or machine-check exceptions) also clear this bit.
2447 *
2448 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2449 */
2450 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2451 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2452
2453 /*
2454 * Update the VM-exit reason and Exit qualification.
2455 * Other VMCS read-only data fields are expected to be updated by the caller already.
2456 */
2457 pVmcs->u32RoExitReason = uExitReason;
2458 pVmcs->u64RoExitQual.u = u64ExitQual;
2459
2460 Log3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2461 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2462 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2463
2464 /*
2465 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2466 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2467 */
2468 {
2469 uint8_t uVector;
2470 uint32_t fFlags;
2471 uint32_t uErrCode;
2472 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2473 if (fInEventDelivery)
2474 {
2475 /*
2476 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2477 * caused by a triple-fault or the original event results in a double-fault that
2478 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2479 * original event information into the IDT-vectoring information fields.
2480 *
2481 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2482 */
2483 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2484 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2485 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2486 {
2487 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2488 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2489 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2490 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2491 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2492 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2493 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2494 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2495 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2496 pVCpu->cpum.GstCtx.cr2));
2497 }
2498 }
2499 }
2500
2501 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2502 Assert(pVmcs->u64RoIoRcx.u == 0);
2503 Assert(pVmcs->u64RoIoRsi.u == 0);
2504 Assert(pVmcs->u64RoIoRdi.u == 0);
2505 Assert(pVmcs->u64RoIoRip.u == 0);
2506
2507 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2508 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2509 {
2510 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2511 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2512 }
2513
2514 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2515 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2516
2517 /*
2518 * Save the guest state back into the VMCS.
2519 * We only need to save the state when the VM-entry was successful.
2520 */
2521 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2522 if (!fVmentryFailed)
2523 {
2524 /*
2525 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2526 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2527 *
2528 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2529 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2530 * as guest-CPU state would not been modified. Hence for now, we do this only when
2531 * the VM-entry succeeded.
2532 */
2533 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2534 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2535 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2536 {
2537 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2538 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2539 else
2540 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2541 }
2542
2543 /*
2544 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2545 * occurs in enclave mode/SMM which we don't support yet.
2546 *
2547 * If we ever add support for it, we can pass just the lower bits to the functions
2548 * below, till then an assert should suffice.
2549 */
2550 Assert(!RT_HI_U16(uExitReason));
2551
2552 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2553 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2554 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2555 if (RT_SUCCESS(rc))
2556 { /* likely */ }
2557 else
2558 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2559
2560 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2561 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2562 }
2563 else
2564 {
2565 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2566 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2567 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2568 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2569 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2570 }
2571
2572 /*
2573 * Stop any running VMX-preemption timer if necessary.
2574 */
2575 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2576 CPUMStopGuestVmxPremptTimer(pVCpu);
2577
2578 /*
2579 * Clear any pending VMX nested-guest force-flags.
2580 * These force-flags have no effect on (outer) guest execution and will
2581 * be re-evaluated and setup on the next nested-guest VM-entry.
2582 */
2583 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2584
2585 /* Restore the host (outer guest) state. */
2586 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2587 if (RT_SUCCESS(rcStrict))
2588 {
2589 Assert(rcStrict == VINF_SUCCESS);
2590 rcStrict = VINF_VMX_VMEXIT;
2591 }
2592 else
2593 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2594
2595 /* We're no longer in nested-guest execution mode. */
2596 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2597
2598 /* Notify HM that the current VMCS fields have been modified. */
2599 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2600
2601 /* Notify HM that we've completed the VM-exit. */
2602 HMNotifyVmxNstGstVmexit(pVCpu);
2603
2604# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2605 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2606 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2607 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2608 if (rcSched != VINF_SUCCESS)
2609 iemSetPassUpStatus(pVCpu, rcSched);
2610# endif
2611 return rcStrict;
2612# endif
2613}
2614
2615
2616/**
2617 * VMX VM-exit handler for VM-exits due to instruction execution.
2618 *
2619 * This is intended for instructions where the caller provides all the relevant
2620 * VM-exit information.
2621 *
2622 * @returns Strict VBox status code.
2623 * @param pVCpu The cross context virtual CPU structure.
2624 * @param pExitInfo Pointer to the VM-exit information.
2625 */
2626IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2627{
2628 /*
2629 * For instructions where any of the following fields are not applicable:
2630 * - Exit qualification must be cleared.
2631 * - VM-exit instruction info. is undefined.
2632 * - Guest-linear address is undefined.
2633 * - Guest-physical address is undefined.
2634 *
2635 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2636 * instruction execution. For VM-exits that are not due to instruction execution this
2637 * field is undefined.
2638 *
2639 * In our implementation in IEM, all undefined fields are generally cleared. However,
2640 * if the caller supplies information (from say the physical CPU directly) it is
2641 * then possible that the undefined fields are not cleared.
2642 *
2643 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2644 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2645 */
2646 Assert(pExitInfo);
2647 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2648 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2649 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2650
2651 /* Update all the relevant fields from the VM-exit instruction information struct. */
2652 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2653 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2654 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2655 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2656
2657 /* Perform the VM-exit. */
2658 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2659}
2660
2661
2662/**
2663 * VMX VM-exit handler for VM-exits due to instruction execution.
2664 *
2665 * This is intended for instructions that only provide the VM-exit instruction
2666 * length.
2667 *
2668 * @param pVCpu The cross context virtual CPU structure.
2669 * @param uExitReason The VM-exit reason.
2670 * @param cbInstr The instruction length in bytes.
2671 */
2672IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2673{
2674 VMXVEXITINFO ExitInfo;
2675 RT_ZERO(ExitInfo);
2676 ExitInfo.uReason = uExitReason;
2677 ExitInfo.cbInstr = cbInstr;
2678
2679#ifdef VBOX_STRICT
2680 /*
2681 * To prevent us from shooting ourselves in the foot.
2682 * The follow instructions should convey more than just the instruction length.
2683 */
2684 switch (uExitReason)
2685 {
2686 case VMX_EXIT_INVEPT:
2687 case VMX_EXIT_INVPCID:
2688 case VMX_EXIT_INVVPID:
2689 case VMX_EXIT_LDTR_TR_ACCESS:
2690 case VMX_EXIT_GDTR_IDTR_ACCESS:
2691 case VMX_EXIT_VMCLEAR:
2692 case VMX_EXIT_VMPTRLD:
2693 case VMX_EXIT_VMPTRST:
2694 case VMX_EXIT_VMREAD:
2695 case VMX_EXIT_VMWRITE:
2696 case VMX_EXIT_VMXON:
2697 case VMX_EXIT_XRSTORS:
2698 case VMX_EXIT_XSAVES:
2699 case VMX_EXIT_RDRAND:
2700 case VMX_EXIT_RDSEED:
2701 case VMX_EXIT_IO_INSTR:
2702 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2703 break;
2704 }
2705#endif
2706
2707 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2708}
2709
2710
2711/**
2712 * VMX VM-exit handler for VM-exits due to instruction execution.
2713 *
2714 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2715 * instruction information and Exit qualification fields.
2716 *
2717 * @param pVCpu The cross context virtual CPU structure.
2718 * @param uExitReason The VM-exit reason.
2719 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2720 * @param cbInstr The instruction length in bytes.
2721 *
2722 * @remarks Do not use this for INS/OUTS instruction.
2723 */
2724IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2725{
2726 VMXVEXITINFO ExitInfo;
2727 RT_ZERO(ExitInfo);
2728 ExitInfo.uReason = uExitReason;
2729 ExitInfo.cbInstr = cbInstr;
2730
2731 /*
2732 * Update the Exit qualification field with displacement bytes.
2733 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2734 */
2735 switch (uExitReason)
2736 {
2737 case VMX_EXIT_INVEPT:
2738 case VMX_EXIT_INVPCID:
2739 case VMX_EXIT_INVVPID:
2740 case VMX_EXIT_LDTR_TR_ACCESS:
2741 case VMX_EXIT_GDTR_IDTR_ACCESS:
2742 case VMX_EXIT_VMCLEAR:
2743 case VMX_EXIT_VMPTRLD:
2744 case VMX_EXIT_VMPTRST:
2745 case VMX_EXIT_VMREAD:
2746 case VMX_EXIT_VMWRITE:
2747 case VMX_EXIT_VMXON:
2748 case VMX_EXIT_XRSTORS:
2749 case VMX_EXIT_XSAVES:
2750 case VMX_EXIT_RDRAND:
2751 case VMX_EXIT_RDSEED:
2752 {
2753 /* Construct the VM-exit instruction information. */
2754 RTGCPTR GCPtrDisp;
2755 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2756
2757 /* Update the VM-exit instruction information. */
2758 ExitInfo.InstrInfo.u = uInstrInfo;
2759
2760 /* Update the Exit qualification. */
2761 ExitInfo.u64Qual = GCPtrDisp;
2762 break;
2763 }
2764
2765 default:
2766 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2767 break;
2768 }
2769
2770 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2771}
2772
2773
2774/**
2775 * VMX VM-exit handler for VM-exits due to INVLPG.
2776 *
2777 * @returns Strict VBox status code.
2778 * @param pVCpu The cross context virtual CPU structure.
2779 * @param GCPtrPage The guest-linear address of the page being invalidated.
2780 * @param cbInstr The instruction length in bytes.
2781 */
2782IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2783{
2784 VMXVEXITINFO ExitInfo;
2785 RT_ZERO(ExitInfo);
2786 ExitInfo.uReason = VMX_EXIT_INVLPG;
2787 ExitInfo.cbInstr = cbInstr;
2788 ExitInfo.u64Qual = GCPtrPage;
2789 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2790
2791 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2792}
2793
2794
2795/**
2796 * VMX VM-exit handler for VM-exits due to LMSW.
2797 *
2798 * @returns Strict VBox status code.
2799 * @param pVCpu The cross context virtual CPU structure.
2800 * @param uGuestCr0 The current guest CR0.
2801 * @param pu16NewMsw The machine-status word specified in LMSW's source
2802 * operand. This will be updated depending on the VMX
2803 * guest/host CR0 mask if LMSW is not intercepted.
2804 * @param GCPtrEffDst The guest-linear address of the source operand in case
2805 * of a memory operand. For register operand, pass
2806 * NIL_RTGCPTR.
2807 * @param cbInstr The instruction length in bytes.
2808 */
2809IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2810 uint8_t cbInstr)
2811{
2812 Assert(pu16NewMsw);
2813
2814 uint16_t const uNewMsw = *pu16NewMsw;
2815 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2816 {
2817 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2818
2819 VMXVEXITINFO ExitInfo;
2820 RT_ZERO(ExitInfo);
2821 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2822 ExitInfo.cbInstr = cbInstr;
2823
2824 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2825 if (fMemOperand)
2826 {
2827 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2828 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2829 }
2830
2831 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2832 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2833 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2834 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2835
2836 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2837 }
2838
2839 /*
2840 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2841 * CR0 guest/host mask must be left unmodified.
2842 *
2843 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2844 */
2845 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2846 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2847 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2848
2849 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2850}
2851
2852
2853/**
2854 * VMX VM-exit handler for VM-exits due to CLTS.
2855 *
2856 * @returns Strict VBox status code.
2857 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2858 * VM-exit but must not modify the guest CR0.TS bit.
2859 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2860 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2861 * CR0 fixed bits in VMX operation).
2862 * @param pVCpu The cross context virtual CPU structure.
2863 * @param cbInstr The instruction length in bytes.
2864 */
2865IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2866{
2867 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2868 uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2869
2870 /*
2871 * If CR0.TS is owned by the host:
2872 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2873 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2874 * CLTS instruction completes without clearing CR0.TS.
2875 *
2876 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2877 */
2878 if (fGstHostMask & X86_CR0_TS)
2879 {
2880 if (fReadShadow & X86_CR0_TS)
2881 {
2882 Log2(("clts: Guest intercept -> VM-exit\n"));
2883
2884 VMXVEXITINFO ExitInfo;
2885 RT_ZERO(ExitInfo);
2886 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2887 ExitInfo.cbInstr = cbInstr;
2888 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2889 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2890 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2891 }
2892
2893 return VINF_VMX_MODIFIES_BEHAVIOR;
2894 }
2895
2896 /*
2897 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2898 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2899 */
2900 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2901}
2902
2903
2904/**
2905 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2906 * (CR0/CR4 write).
2907 *
2908 * @returns Strict VBox status code.
2909 * @param pVCpu The cross context virtual CPU structure.
2910 * @param iCrReg The control register (either CR0 or CR4).
2911 * @param uGuestCrX The current guest CR0/CR4.
2912 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2913 * VM-exit is caused.
2914 * @param iGReg The general register from which the CR0/CR4 value is being
2915 * loaded.
2916 * @param cbInstr The instruction length in bytes.
2917 */
2918IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2919 uint8_t cbInstr)
2920{
2921 Assert(puNewCrX);
2922 Assert(iCrReg == 0 || iCrReg == 4);
2923 Assert(iGReg < X86_GREG_COUNT);
2924
2925 uint64_t const uNewCrX = *puNewCrX;
2926 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2927 {
2928 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2929
2930 VMXVEXITINFO ExitInfo;
2931 RT_ZERO(ExitInfo);
2932 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2933 ExitInfo.cbInstr = cbInstr;
2934 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2935 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2936 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2937 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2938 }
2939
2940 /*
2941 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2942 * must not be modified the instruction.
2943 *
2944 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2945 */
2946 uint64_t uGuestCrX;
2947 uint64_t fGstHostMask;
2948 if (iCrReg == 0)
2949 {
2950 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2951 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2952 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2953 }
2954 else
2955 {
2956 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2957 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2958 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2959 }
2960
2961 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2962 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2963}
2964
2965
2966/**
2967 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2968 *
2969 * @returns VBox strict status code.
2970 * @param pVCpu The cross context virtual CPU structure.
2971 * @param iGReg The general register to which the CR3 value is being stored.
2972 * @param cbInstr The instruction length in bytes.
2973 */
2974IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
2975{
2976 Assert(iGReg < X86_GREG_COUNT);
2977 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
2978
2979 /*
2980 * If the CR3-store exiting control is set, we must cause a VM-exit.
2981 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2982 */
2983 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
2984 {
2985 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
2986
2987 VMXVEXITINFO ExitInfo;
2988 RT_ZERO(ExitInfo);
2989 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2990 ExitInfo.cbInstr = cbInstr;
2991 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
2992 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
2993 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2994 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2995 }
2996
2997 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2998}
2999
3000
3001/**
3002 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3003 *
3004 * @returns VBox strict status code.
3005 * @param pVCpu The cross context virtual CPU structure.
3006 * @param uNewCr3 The new CR3 value.
3007 * @param iGReg The general register from which the CR3 value is being
3008 * loaded.
3009 * @param cbInstr The instruction length in bytes.
3010 */
3011IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3012{
3013 Assert(iGReg < X86_GREG_COUNT);
3014
3015 /*
3016 * If the CR3-load exiting control is set and the new CR3 value does not
3017 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3018 *
3019 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3020 */
3021 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3022 {
3023 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3024
3025 VMXVEXITINFO ExitInfo;
3026 RT_ZERO(ExitInfo);
3027 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3028 ExitInfo.cbInstr = cbInstr;
3029 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3030 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3031 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3032 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3033 }
3034
3035 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3036}
3037
3038
3039/**
3040 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3041 *
3042 * @returns VBox strict status code.
3043 * @param pVCpu The cross context virtual CPU structure.
3044 * @param iGReg The general register to which the CR8 value is being stored.
3045 * @param cbInstr The instruction length in bytes.
3046 */
3047IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3048{
3049 Assert(iGReg < X86_GREG_COUNT);
3050
3051 /*
3052 * If the CR8-store exiting control is set, we must cause a VM-exit.
3053 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3054 */
3055 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3056 {
3057 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3058
3059 VMXVEXITINFO ExitInfo;
3060 RT_ZERO(ExitInfo);
3061 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3062 ExitInfo.cbInstr = cbInstr;
3063 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3064 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3065 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3066 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3067 }
3068
3069 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3070}
3071
3072
3073/**
3074 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3075 *
3076 * @returns VBox strict status code.
3077 * @param pVCpu The cross context virtual CPU structure.
3078 * @param iGReg The general register from which the CR8 value is being
3079 * loaded.
3080 * @param cbInstr The instruction length in bytes.
3081 */
3082IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3083{
3084 Assert(iGReg < X86_GREG_COUNT);
3085
3086 /*
3087 * If the CR8-load exiting control is set, we must cause a VM-exit.
3088 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3089 */
3090 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3091 {
3092 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3093
3094 VMXVEXITINFO ExitInfo;
3095 RT_ZERO(ExitInfo);
3096 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3097 ExitInfo.cbInstr = cbInstr;
3098 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3099 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3100 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3101 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3102 }
3103
3104 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3105}
3106
3107
3108/**
3109 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3110 * GReg,DRx' (DRx read).
3111 *
3112 * @returns VBox strict status code.
3113 * @param pVCpu The cross context virtual CPU structure.
3114 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3115 * VMXINSTRID_MOV_FROM_DRX).
3116 * @param iDrReg The debug register being accessed.
3117 * @param iGReg The general register to/from which the DRx value is being
3118 * store/loaded.
3119 * @param cbInstr The instruction length in bytes.
3120 */
3121IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3122 uint8_t cbInstr)
3123{
3124 Assert(iDrReg <= 7);
3125 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3126 Assert(iGReg < X86_GREG_COUNT);
3127
3128 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3129 {
3130 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3131 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3132 VMXVEXITINFO ExitInfo;
3133 RT_ZERO(ExitInfo);
3134 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3135 ExitInfo.cbInstr = cbInstr;
3136 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3137 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3138 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3139 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3140 }
3141
3142 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3143}
3144
3145
3146/**
3147 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3148 *
3149 * @returns VBox strict status code.
3150 * @param pVCpu The cross context virtual CPU structure.
3151 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3152 * VMXINSTRID_IO_OUT).
3153 * @param u16Port The I/O port being accessed.
3154 * @param fImm Whether the I/O port was encoded using an immediate operand
3155 * or the implicit DX register.
3156 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3157 * @param cbInstr The instruction length in bytes.
3158 */
3159IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3160 uint8_t cbInstr)
3161{
3162 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3163 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3164
3165 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3166 if (fIntercept)
3167 {
3168 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3169 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3170 VMXVEXITINFO ExitInfo;
3171 RT_ZERO(ExitInfo);
3172 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3173 ExitInfo.cbInstr = cbInstr;
3174 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3175 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3176 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3177 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3178 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3179 }
3180
3181 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3182}
3183
3184
3185/**
3186 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3187 *
3188 * @returns VBox strict status code.
3189 * @param pVCpu The cross context virtual CPU structure.
3190 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3191 * VMXINSTRID_IO_OUTS).
3192 * @param u16Port The I/O port being accessed.
3193 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3194 * @param fRep Whether the instruction has a REP prefix or not.
3195 * @param ExitInstrInfo The VM-exit instruction info. field.
3196 * @param cbInstr The instruction length in bytes.
3197 */
3198IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3199 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3200{
3201 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3202 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3203 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3204 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3205 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3206
3207 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3208 if (fIntercept)
3209 {
3210 /*
3211 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3212 */
3213 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3214 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3215 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3216 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3217 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3218
3219 uint32_t uDirection;
3220 uint64_t uGuestLinearAddr;
3221 if (uInstrId == VMXINSTRID_IO_INS)
3222 {
3223 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3224 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3225 }
3226 else
3227 {
3228 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3229 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3230 }
3231
3232 /*
3233 * If the segment is unusable, the guest-linear address in undefined.
3234 * We shall clear it for consistency.
3235 *
3236 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3237 */
3238 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3239 uGuestLinearAddr = 0;
3240
3241 VMXVEXITINFO ExitInfo;
3242 RT_ZERO(ExitInfo);
3243 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3244 ExitInfo.cbInstr = cbInstr;
3245 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3246 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3247 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3248 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3249 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3250 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3251 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3252 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3253 ExitInfo.InstrInfo = ExitInstrInfo;
3254 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3255 }
3256
3257 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3258}
3259
3260
3261/**
3262 * VMX VM-exit handler for VM-exits due to MWAIT.
3263 *
3264 * @returns VBox strict status code.
3265 * @param pVCpu The cross context virtual CPU structure.
3266 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3267 * @param cbInstr The instruction length in bytes.
3268 */
3269IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3270{
3271 VMXVEXITINFO ExitInfo;
3272 RT_ZERO(ExitInfo);
3273 ExitInfo.uReason = VMX_EXIT_MWAIT;
3274 ExitInfo.cbInstr = cbInstr;
3275 ExitInfo.u64Qual = fMonitorHwArmed;
3276 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3277}
3278
3279
3280/**
3281 * VMX VM-exit handler for VM-exits due to PAUSE.
3282 *
3283 * @returns VBox strict status code.
3284 * @param pVCpu The cross context virtual CPU structure.
3285 * @param cbInstr The instruction length in bytes.
3286 */
3287IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3288{
3289 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3290
3291 /*
3292 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3293 * "PAUSE-loop exiting" control.
3294 *
3295 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3296 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3297 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3298 * a VM-exit.
3299 *
3300 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3301 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3302 */
3303 bool fIntercept = false;
3304 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3305 fIntercept = true;
3306 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3307 && pVCpu->iem.s.uCpl == 0)
3308 {
3309 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3310
3311 /*
3312 * A previous-PAUSE-tick value of 0 is used to identify the first time
3313 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3314 * consider this to be the first execution of PAUSE in a loop according
3315 * to the Intel.
3316 *
3317 * All subsequent records for the previous-PAUSE-tick we ensure that it
3318 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3319 */
3320 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3321 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3322 uint64_t const uTick = TMCpuTickGet(pVCpu);
3323 uint32_t const uPleGap = pVmcs->u32PleGap;
3324 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3325 if ( *puPrevPauseTick == 0
3326 || uTick - *puPrevPauseTick > uPleGap)
3327 *puFirstPauseLoopTick = uTick;
3328 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3329 fIntercept = true;
3330
3331 *puPrevPauseTick = uTick | 1;
3332 }
3333
3334 if (fIntercept)
3335 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3336
3337 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3338}
3339
3340
3341/**
3342 * VMX VM-exit handler for VM-exits due to task switches.
3343 *
3344 * @returns VBox strict status code.
3345 * @param pVCpu The cross context virtual CPU structure.
3346 * @param enmTaskSwitch The cause of the task switch.
3347 * @param SelNewTss The selector of the new TSS.
3348 * @param cbInstr The instruction length in bytes.
3349 */
3350IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3351{
3352 /*
3353 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3354 *
3355 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3356 * instruction or delivery of the exception generated by one of these instructions
3357 * lead to a task switch through a task gate in the IDT, we need to provide the
3358 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3359 * leaves the VM-exit instruction length field undefined.
3360 *
3361 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3362 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3363 */
3364 Assert(cbInstr <= 15);
3365
3366 uint8_t uType;
3367 switch (enmTaskSwitch)
3368 {
3369 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3370 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3371 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3372 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3373 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3374 }
3375
3376 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3377 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3378 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3379 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3380}
3381
3382
3383/**
3384 * VMX VM-exit handler for trap-like VM-exits.
3385 *
3386 * @returns VBox strict status code.
3387 * @param pVCpu The cross context virtual CPU structure.
3388 * @param pExitInfo Pointer to the VM-exit information.
3389 * @param pExitEventInfo Pointer to the VM-exit event information.
3390 */
3391IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3392{
3393 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3394 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3395 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3396}
3397
3398
3399/**
3400 * VMX VM-exit handler for VM-exits due to task switches.
3401 *
3402 * This is intended for task switches where the caller provides all the relevant
3403 * VM-exit information.
3404 *
3405 * @returns VBox strict status code.
3406 * @param pVCpu The cross context virtual CPU structure.
3407 * @param pExitInfo Pointer to the VM-exit information.
3408 * @param pExitEventInfo Pointer to the VM-exit event information.
3409 */
3410IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3411 PCVMXVEXITEVENTINFO pExitEventInfo)
3412{
3413 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3414 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3415 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3416 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3417 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3418}
3419
3420
3421/**
3422 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3423 *
3424 * @returns VBox strict status code.
3425 * @param pVCpu The cross context virtual CPU structure.
3426 */
3427IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3428{
3429 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3430 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3431
3432 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3433 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3434
3435 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3436 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3437 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3438
3439 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3440 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3441}
3442
3443
3444/**
3445 * VMX VM-exit handler for VM-exits due to external interrupts.
3446 *
3447 * @returns VBox strict status code.
3448 * @param pVCpu The cross context virtual CPU structure.
3449 * @param uVector The external interrupt vector (pass 0 if the interrupt
3450 * is still pending since we typically won't know the
3451 * vector).
3452 * @param fIntPending Whether the external interrupt is pending or
3453 * acknowledged in the interrupt controller.
3454 */
3455IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3456{
3457 Assert(!fIntPending || uVector == 0);
3458
3459 /* The VM-exit is subject to "External interrupt exiting" being set. */
3460 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3461 {
3462 if (fIntPending)
3463 {
3464 /*
3465 * If the interrupt is pending and we don't need to acknowledge the
3466 * interrupt on VM-exit, cause the VM-exit immediately.
3467 *
3468 * See Intel spec 25.2 "Other Causes Of VM Exits".
3469 */
3470 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3471 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3472
3473 /*
3474 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3475 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3476 * acknowledged that the interrupt has been consumed. Callers would have to call
3477 * us again after getting the vector (and ofc, with fIntPending with false).
3478 */
3479 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3480 }
3481
3482 /*
3483 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3484 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3485 * all set, we need to record the vector of the external interrupt in the
3486 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3487 *
3488 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3489 */
3490 uint32_t uExitIntInfo;
3491 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3492 {
3493 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3494 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3495 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3496 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3497 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3498 }
3499 else
3500 uExitIntInfo = 0;
3501 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3502
3503 /*
3504 * Cause the VM-exit whether or not the vector has been stored
3505 * in the VM-exit interruption-information field.
3506 */
3507 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3508 }
3509
3510 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3511}
3512
3513
3514/**
3515 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3516 * an event.
3517 *
3518 * @returns VBox strict status code.
3519 * @param pVCpu The cross context virtual CPU structure.
3520 */
3521IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3522{
3523 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3524 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3525 {
3526 /*
3527 * The NMI-unblocking due to IRET field need not be set for double faults.
3528 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3529 */
3530 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3531 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3532 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3533 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3534 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3535 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3536 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3537 }
3538
3539 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3540}
3541
3542
3543/**
3544 * VMX VM-exit handler for VM-exit due to delivery of an events.
3545 *
3546 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3547 * all the relevant VM-exit information.
3548 *
3549 * @returns VBox strict status code.
3550 * @param pVCpu The cross context virtual CPU structure.
3551 * @param pExitInfo Pointer to the VM-exit information.
3552 * @param pExitEventInfo Pointer to the VM-exit event information.
3553 */
3554IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3555{
3556 Assert(pExitInfo);
3557 Assert(pExitEventInfo);
3558 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3559 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3560
3561 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3562 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3563 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3564 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3565 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3566 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3567}
3568
3569
3570/**
3571 * VMX VM-exit handler for VM-exits due to delivery of an event.
3572 *
3573 * @returns VBox strict status code.
3574 * @param pVCpu The cross context virtual CPU structure.
3575 * @param uVector The interrupt / exception vector.
3576 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3577 * @param uErrCode The error code associated with the event.
3578 * @param uCr2 The CR2 value in case of a \#PF exception.
3579 * @param cbInstr The instruction length in bytes.
3580 */
3581IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3582 uint8_t cbInstr)
3583{
3584 /*
3585 * If the event is being injected as part of VM-entry, it is -not- subject to event
3586 * intercepts in the nested-guest. However, secondary exceptions that occur during
3587 * injection of any event -are- subject to event interception.
3588 *
3589 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3590 */
3591 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3592 {
3593 /*
3594 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3595 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3596 *
3597 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3598 */
3599 if ( uVector == X86_XCPT_NMI
3600 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3601 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3602 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3603 else
3604 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3605
3606 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3607 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3608 }
3609
3610 /*
3611 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3612 * If not, the caller will continue delivery of the external interrupt as it would
3613 * normally. The interrupt is no longer pending in the interrupt controller at this
3614 * point.
3615 */
3616 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3617 {
3618 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3619 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3620 }
3621
3622 /*
3623 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3624 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3625 * interrupts.
3626 */
3627 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3628 bool fIntercept;
3629 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3630 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3631 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3632 else
3633 {
3634 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3635 fIntercept = false;
3636 }
3637
3638 /*
3639 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3640 * relevant VM-exit information and cause the VM-exit.
3641 */
3642 if (fIntercept)
3643 {
3644 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3645
3646 /* Construct the rest of the event related information fields and cause the VM-exit. */
3647 uint64_t u64ExitQual;
3648 if (uVector == X86_XCPT_PF)
3649 {
3650 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3651 u64ExitQual = uCr2;
3652 }
3653 else if (uVector == X86_XCPT_DB)
3654 {
3655 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3656 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3657 }
3658 else
3659 u64ExitQual = 0;
3660
3661 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3662 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3663 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3664 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3665 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3666 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3667 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3668 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3669 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3670 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3671
3672 /*
3673 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3674 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3675 * length.
3676 */
3677 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3678 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3679 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3680 else
3681 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3682
3683 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3684 }
3685
3686 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3687}
3688
3689
3690#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3691/**
3692 * VMX VM-exit handler for EPT violation.
3693 *
3694 * @param pVCpu The cross context virtual CPU structure.
3695 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3696 * @param fEptAccess The EPT paging structure bits.
3697 * @param GCPhysAddr The physical address causing the EPT violation.
3698 * @param GCPtrAddr The linear address causing the EPT violation.
3699 * @param cbInstr The VM-exit instruction length.
3700 */
3701IEM_STATIC VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint64_t fEptAccess, RTGCPHYS GCPhysAddr,
3702 uint64_t GCPtrAddr, bool fLinearAddrValid, uint8_t cbInstr)
3703{
3704 /*
3705 * If the linear address isn't valid (can happen when loading PDPTEs
3706 * as part of MOV CR execution) the linear address field is undefined.
3707 * While we can leave it this way, it's preferrable to zero it for consistency.
3708 */
3709 Assert(fLinearAddrValid || GCPtrAddr == 0);
3710
3711 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3712 uint8_t const fSupportsAccessDirty = fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY;
3713
3714 uint8_t const fDataRead = ((fAccess & IEM_ACCESS_DATA_R) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3715 uint8_t const fDataWrite = ((fAccess & IEM_ACCESS_DATA_RW) == IEM_ACCESS_DATA_RW) | fSupportsAccessDirty;
3716 uint8_t const fInstrFetch = (fAccess & IEM_ACCESS_INSTRUCTION) == IEM_ACCESS_INSTRUCTION;
3717 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3718 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3719 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3720 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3721
3722 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
3723 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
3724 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
3725 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
3726 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
3727 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
3728 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fLinearAddrValid)
3729 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
3730
3731 /** @todo bit 8 of Exit Qualification!
3732 * If the access causing the EPT violation is to a guest-physical address that is
3733 * the translation of a linear address.
3734 * - OR -
3735 * if the access causing the EPT violation is to a paging-structure entry as part
3736 * of a page walk or the update of an accessed or dirty bit.
3737 *
3738 * Caller needs to be able to distinguish this... */
3739
3740#ifdef VBOX_STRICT
3741 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
3742 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
3743 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
3744 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
3745 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3746 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3747 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
3748#endif
3749
3750 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3751 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
3752 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3753
3754 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
3755}
3756#endif
3757
3758
3759/**
3760 * VMX VM-exit handler for APIC accesses.
3761 *
3762 * @param pVCpu The cross context virtual CPU structure.
3763 * @param offAccess The offset of the register being accessed.
3764 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3765 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3766 */
3767IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3768{
3769 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3770
3771 VMXAPICACCESS enmAccess;
3772 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3773 if (fInEventDelivery)
3774 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3775 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3776 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3777 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3778 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3779 else
3780 enmAccess = VMXAPICACCESS_LINEAR_READ;
3781
3782 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3783 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3784 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3785}
3786
3787
3788/**
3789 * VMX VM-exit handler for APIC accesses.
3790 *
3791 * This is intended for APIC accesses where the caller provides all the
3792 * relevant VM-exit information.
3793 *
3794 * @returns VBox strict status code.
3795 * @param pVCpu The cross context virtual CPU structure.
3796 * @param pExitInfo Pointer to the VM-exit information.
3797 * @param pExitEventInfo Pointer to the VM-exit event information.
3798 */
3799IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3800 PCVMXVEXITEVENTINFO pExitEventInfo)
3801{
3802 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3803 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3804 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3805 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3806 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3807 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3808 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3809 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3810 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3811}
3812
3813
3814/**
3815 * VMX VM-exit handler for APIC-write VM-exits.
3816 *
3817 * @param pVCpu The cross context virtual CPU structure.
3818 * @param offApic The write to the virtual-APIC page offset that caused this
3819 * VM-exit.
3820 */
3821IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3822{
3823 Assert(offApic < XAPIC_OFF_END + 4);
3824 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3825 offApic &= UINT16_C(0xfff);
3826 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3827}
3828
3829
3830/**
3831 * Sets virtual-APIC write emulation as pending.
3832 *
3833 * @param pVCpu The cross context virtual CPU structure.
3834 * @param offApic The offset in the virtual-APIC page that was written.
3835 */
3836DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3837{
3838 Assert(offApic < XAPIC_OFF_END + 4);
3839
3840 /*
3841 * Record the currently updated APIC offset, as we need this later for figuring
3842 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3843 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3844 */
3845 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3846
3847 /*
3848 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3849 * virtualization or APIC-write emulation).
3850 */
3851 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3852 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3853}
3854
3855
3856/**
3857 * Clears any pending virtual-APIC write emulation.
3858 *
3859 * @returns The virtual-APIC offset that was written before clearing it.
3860 * @param pVCpu The cross context virtual CPU structure.
3861 */
3862DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3863{
3864 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3865 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3866 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3867 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3868 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3869 return offVirtApicWrite;
3870}
3871
3872
3873/**
3874 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3875 *
3876 * @returns The register from the virtual-APIC page.
3877 * @param pVCpu The cross context virtual CPU structure.
3878 * @param offReg The offset of the register being read.
3879 */
3880IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3881{
3882 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3883
3884 uint32_t uReg = 0;
3885 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3886 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3887 AssertMsgStmt(RT_SUCCESS(rc),
3888 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3889 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3890 uReg = 0);
3891 return uReg;
3892}
3893
3894
3895/**
3896 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3897 *
3898 * @returns The register from the virtual-APIC page.
3899 * @param pVCpu The cross context virtual CPU structure.
3900 * @param offReg The offset of the register being read.
3901 */
3902IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3903{
3904 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3905
3906 uint64_t uReg = 0;
3907 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3908 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3909 AssertMsgStmt(RT_SUCCESS(rc),
3910 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3911 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3912 uReg = 0);
3913 return uReg;
3914}
3915
3916
3917/**
3918 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3919 *
3920 * @param pVCpu The cross context virtual CPU structure.
3921 * @param offReg The offset of the register being written.
3922 * @param uReg The register value to write.
3923 */
3924IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3925{
3926 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3927
3928 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3929 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3930 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3931 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3932}
3933
3934
3935/**
3936 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3937 *
3938 * @param pVCpu The cross context virtual CPU structure.
3939 * @param offReg The offset of the register being written.
3940 * @param uReg The register value to write.
3941 */
3942IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3943{
3944 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3945
3946 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3947 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3948 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3949 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3950}
3951
3952
3953/**
3954 * Sets the vector in a virtual-APIC 256-bit sparse register.
3955 *
3956 * @param pVCpu The cross context virtual CPU structure.
3957 * @param offReg The offset of the 256-bit spare register.
3958 * @param uVector The vector to set.
3959 *
3960 * @remarks This is based on our APIC device code.
3961 */
3962IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3963{
3964 /* Determine the vector offset within the chunk. */
3965 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3966
3967 /* Read the chunk at the offset. */
3968 uint32_t uReg;
3969 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3970 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3971 if (RT_SUCCESS(rc))
3972 {
3973 /* Modify the chunk. */
3974 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3975 uReg |= RT_BIT(idxVectorBit);
3976
3977 /* Write the chunk. */
3978 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3979 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3980 uVector, offReg, GCPhysVirtApic, rc));
3981 }
3982 else
3983 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3984 uVector, offReg, GCPhysVirtApic, rc));
3985}
3986
3987
3988/**
3989 * Clears the vector in a virtual-APIC 256-bit sparse register.
3990 *
3991 * @param pVCpu The cross context virtual CPU structure.
3992 * @param offReg The offset of the 256-bit spare register.
3993 * @param uVector The vector to clear.
3994 *
3995 * @remarks This is based on our APIC device code.
3996 */
3997IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3998{
3999 /* Determine the vector offset within the chunk. */
4000 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4001
4002 /* Read the chunk at the offset. */
4003 uint32_t uReg;
4004 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4005 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4006 if (RT_SUCCESS(rc))
4007 {
4008 /* Modify the chunk. */
4009 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4010 uReg &= ~RT_BIT(idxVectorBit);
4011
4012 /* Write the chunk. */
4013 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4014 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4015 uVector, offReg, GCPhysVirtApic, rc));
4016 }
4017 else
4018 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4019 uVector, offReg, GCPhysVirtApic, rc));
4020}
4021
4022
4023/**
4024 * Checks if a memory access to the APIC-access page must causes an APIC-access
4025 * VM-exit.
4026 *
4027 * @param pVCpu The cross context virtual CPU structure.
4028 * @param offAccess The offset of the register being accessed.
4029 * @param cbAccess The size of the access in bytes.
4030 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4031 * IEM_ACCESS_TYPE_WRITE).
4032 *
4033 * @remarks This must not be used for MSR-based APIC-access page accesses!
4034 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4035 */
4036IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4037{
4038 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4039 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4040
4041 /*
4042 * We must cause a VM-exit if any of the following are true:
4043 * - TPR shadowing isn't active.
4044 * - The access size exceeds 32-bits.
4045 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4046 *
4047 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4048 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4049 */
4050 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4051 || cbAccess > sizeof(uint32_t)
4052 || ((offAccess + cbAccess - 1) & 0xc)
4053 || offAccess >= XAPIC_OFF_END + 4)
4054 return true;
4055
4056 /*
4057 * If the access is part of an operation where we have already
4058 * virtualized a virtual-APIC write, we must cause a VM-exit.
4059 */
4060 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4061 return true;
4062
4063 /*
4064 * Check write accesses to the APIC-access page that cause VM-exits.
4065 */
4066 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4067 {
4068 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4069 {
4070 /*
4071 * With APIC-register virtualization, a write access to any of the
4072 * following registers are virtualized. Accessing any other register
4073 * causes a VM-exit.
4074 */
4075 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4076 switch (offAlignedAccess)
4077 {
4078 case XAPIC_OFF_ID:
4079 case XAPIC_OFF_TPR:
4080 case XAPIC_OFF_EOI:
4081 case XAPIC_OFF_LDR:
4082 case XAPIC_OFF_DFR:
4083 case XAPIC_OFF_SVR:
4084 case XAPIC_OFF_ESR:
4085 case XAPIC_OFF_ICR_LO:
4086 case XAPIC_OFF_ICR_HI:
4087 case XAPIC_OFF_LVT_TIMER:
4088 case XAPIC_OFF_LVT_THERMAL:
4089 case XAPIC_OFF_LVT_PERF:
4090 case XAPIC_OFF_LVT_LINT0:
4091 case XAPIC_OFF_LVT_LINT1:
4092 case XAPIC_OFF_LVT_ERROR:
4093 case XAPIC_OFF_TIMER_ICR:
4094 case XAPIC_OFF_TIMER_DCR:
4095 break;
4096 default:
4097 return true;
4098 }
4099 }
4100 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4101 {
4102 /*
4103 * With virtual-interrupt delivery, a write access to any of the
4104 * following registers are virtualized. Accessing any other register
4105 * causes a VM-exit.
4106 *
4107 * Note! The specification does not allow writing to offsets in-between
4108 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4109 */
4110 switch (offAccess)
4111 {
4112 case XAPIC_OFF_TPR:
4113 case XAPIC_OFF_EOI:
4114 case XAPIC_OFF_ICR_LO:
4115 break;
4116 default:
4117 return true;
4118 }
4119 }
4120 else
4121 {
4122 /*
4123 * Without APIC-register virtualization or virtual-interrupt delivery,
4124 * only TPR accesses are virtualized.
4125 */
4126 if (offAccess == XAPIC_OFF_TPR)
4127 { /* likely */ }
4128 else
4129 return true;
4130 }
4131 }
4132 else
4133 {
4134 /*
4135 * Check read accesses to the APIC-access page that cause VM-exits.
4136 */
4137 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4138 {
4139 /*
4140 * With APIC-register virtualization, a read access to any of the
4141 * following registers are virtualized. Accessing any other register
4142 * causes a VM-exit.
4143 */
4144 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4145 switch (offAlignedAccess)
4146 {
4147 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4148 case XAPIC_OFF_ID:
4149 case XAPIC_OFF_VERSION:
4150 case XAPIC_OFF_TPR:
4151 case XAPIC_OFF_EOI:
4152 case XAPIC_OFF_LDR:
4153 case XAPIC_OFF_DFR:
4154 case XAPIC_OFF_SVR:
4155 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4156 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4157 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4158 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4159 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4160 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4161 case XAPIC_OFF_ESR:
4162 case XAPIC_OFF_ICR_LO:
4163 case XAPIC_OFF_ICR_HI:
4164 case XAPIC_OFF_LVT_TIMER:
4165 case XAPIC_OFF_LVT_THERMAL:
4166 case XAPIC_OFF_LVT_PERF:
4167 case XAPIC_OFF_LVT_LINT0:
4168 case XAPIC_OFF_LVT_LINT1:
4169 case XAPIC_OFF_LVT_ERROR:
4170 case XAPIC_OFF_TIMER_ICR:
4171 case XAPIC_OFF_TIMER_DCR:
4172 break;
4173 default:
4174 return true;
4175 }
4176 }
4177 else
4178 {
4179 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4180 if (offAccess == XAPIC_OFF_TPR)
4181 { /* likely */ }
4182 else
4183 return true;
4184 }
4185 }
4186
4187 /* The APIC access is virtualized, does not cause a VM-exit. */
4188 return false;
4189}
4190
4191
4192/**
4193 * Virtualizes a memory-based APIC access where the address is not used to access
4194 * memory.
4195 *
4196 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4197 * page-faults but do not use the address to access memory.
4198 *
4199 * @param pVCpu The cross context virtual CPU structure.
4200 * @param pGCPhysAccess Pointer to the guest-physical address used.
4201 */
4202IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4203{
4204 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4205 Assert(pGCPhysAccess);
4206
4207 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4208 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4209 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4210
4211 if (GCPhysAccess == GCPhysApic)
4212 {
4213 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4214 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4215 uint16_t const cbAccess = 1;
4216 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4217 if (fIntercept)
4218 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4219
4220 *pGCPhysAccess = GCPhysApic | offAccess;
4221 return VINF_VMX_MODIFIES_BEHAVIOR;
4222 }
4223
4224 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4225}
4226
4227
4228/**
4229 * Virtualizes a memory-based APIC access.
4230 *
4231 * @returns VBox strict status code.
4232 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4233 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4234 *
4235 * @param pVCpu The cross context virtual CPU structure.
4236 * @param offAccess The offset of the register being accessed (within the
4237 * APIC-access page).
4238 * @param cbAccess The size of the access in bytes.
4239 * @param pvData Pointer to the data being written or where to store the data
4240 * being read.
4241 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4242 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4243 */
4244IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4245 uint32_t fAccess)
4246{
4247 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4248 Assert(pvData);
4249 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4250 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4251 || (fAccess & IEM_ACCESS_INSTRUCTION));
4252
4253 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4254 if (fIntercept)
4255 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4256
4257 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4258 {
4259 /*
4260 * A write access to the APIC-access page that is virtualized (rather than
4261 * causing a VM-exit) writes data to the virtual-APIC page.
4262 */
4263 uint32_t const u32Data = *(uint32_t *)pvData;
4264 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4265
4266 /*
4267 * Record the currently updated APIC offset, as we need this later for figuring
4268 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4269 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4270 *
4271 * After completion of the current operation, we need to perform TPR virtualization,
4272 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4273 *
4274 * The current operation may be a REP-prefixed string instruction, execution of any
4275 * other instruction, or delivery of an event through the IDT.
4276 *
4277 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4278 * performed now but later after completion of the current operation.
4279 *
4280 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4281 */
4282 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4283 }
4284 else
4285 {
4286 /*
4287 * A read access from the APIC-access page that is virtualized (rather than
4288 * causing a VM-exit) returns data from the virtual-APIC page.
4289 *
4290 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4291 */
4292 Assert(cbAccess <= 4);
4293 Assert(offAccess < XAPIC_OFF_END + 4);
4294 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4295
4296 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4297 u32Data &= s_auAccessSizeMasks[cbAccess];
4298 *(uint32_t *)pvData = u32Data;
4299 }
4300
4301 return VINF_VMX_MODIFIES_BEHAVIOR;
4302}
4303
4304
4305/**
4306 * Virtualizes an MSR-based APIC read access.
4307 *
4308 * @returns VBox strict status code.
4309 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4310 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4311 * handled by the x2APIC device.
4312 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4313 * not within the range of valid MSRs, caller must raise \#GP(0).
4314 * @param pVCpu The cross context virtual CPU structure.
4315 * @param idMsr The x2APIC MSR being read.
4316 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4317 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4318 */
4319IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4320{
4321 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4322 Assert(pu64Value);
4323
4324 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4325 {
4326 if ( idMsr >= MSR_IA32_X2APIC_START
4327 && idMsr <= MSR_IA32_X2APIC_END)
4328 {
4329 uint16_t const offReg = (idMsr & 0xff) << 4;
4330 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4331 *pu64Value = u64Value;
4332 return VINF_VMX_MODIFIES_BEHAVIOR;
4333 }
4334 return VERR_OUT_OF_RANGE;
4335 }
4336
4337 if (idMsr == MSR_IA32_X2APIC_TPR)
4338 {
4339 uint16_t const offReg = (idMsr & 0xff) << 4;
4340 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4341 *pu64Value = u64Value;
4342 return VINF_VMX_MODIFIES_BEHAVIOR;
4343 }
4344
4345 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4346}
4347
4348
4349/**
4350 * Virtualizes an MSR-based APIC write access.
4351 *
4352 * @returns VBox strict status code.
4353 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4354 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4355 * not within the range of valid MSRs, caller must raise \#GP(0).
4356 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4357 *
4358 * @param pVCpu The cross context virtual CPU structure.
4359 * @param idMsr The x2APIC MSR being written.
4360 * @param u64Value The value of the x2APIC MSR being written.
4361 */
4362IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4363{
4364 /*
4365 * Check if the access is to be virtualized.
4366 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4367 */
4368 if ( idMsr == MSR_IA32_X2APIC_TPR
4369 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4370 && ( idMsr == MSR_IA32_X2APIC_EOI
4371 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4372 {
4373 /* Validate the MSR write depending on the register. */
4374 switch (idMsr)
4375 {
4376 case MSR_IA32_X2APIC_TPR:
4377 case MSR_IA32_X2APIC_SELF_IPI:
4378 {
4379 if (u64Value & UINT64_C(0xffffffffffffff00))
4380 return VERR_OUT_OF_RANGE;
4381 break;
4382 }
4383 case MSR_IA32_X2APIC_EOI:
4384 {
4385 if (u64Value != 0)
4386 return VERR_OUT_OF_RANGE;
4387 break;
4388 }
4389 }
4390
4391 /* Write the MSR to the virtual-APIC page. */
4392 uint16_t const offReg = (idMsr & 0xff) << 4;
4393 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4394
4395 /*
4396 * Record the currently updated APIC offset, as we need this later for figuring
4397 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4398 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4399 */
4400 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4401
4402 return VINF_VMX_MODIFIES_BEHAVIOR;
4403 }
4404
4405 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4406}
4407
4408
4409/**
4410 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4411 *
4412 * @returns VBox status code.
4413 * @retval VINF_SUCCESS when the highest set bit is found.
4414 * @retval VERR_NOT_FOUND when no bit is set.
4415 *
4416 * @param pVCpu The cross context virtual CPU structure.
4417 * @param offReg The offset of the APIC 256-bit sparse register.
4418 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4419 * set in the register. Only valid when VINF_SUCCESS is
4420 * returned.
4421 *
4422 * @remarks The format of the 256-bit sparse register here mirrors that found in
4423 * real APIC hardware.
4424 */
4425static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4426{
4427 Assert(offReg < XAPIC_OFF_END + 4);
4428 Assert(pidxHighestBit);
4429
4430 /*
4431 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4432 * However, in each fragment only the first 4 bytes are used.
4433 */
4434 uint8_t const cFrags = 8;
4435 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4436 {
4437 uint16_t const offFrag = iFrag * 16;
4438 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4439 if (!u32Frag)
4440 continue;
4441
4442 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4443 Assert(idxHighestBit > 0);
4444 --idxHighestBit;
4445 Assert(idxHighestBit <= UINT8_MAX);
4446 *pidxHighestBit = idxHighestBit;
4447 return VINF_SUCCESS;
4448 }
4449 return VERR_NOT_FOUND;
4450}
4451
4452
4453/**
4454 * Evaluates pending virtual interrupts.
4455 *
4456 * @param pVCpu The cross context virtual CPU structure.
4457 */
4458IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4459{
4460 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4461
4462 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4463 {
4464 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4465 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4466
4467 if ((uRvi >> 4) > (uPpr >> 4))
4468 {
4469 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4470 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4471 }
4472 else
4473 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4474 }
4475}
4476
4477
4478/**
4479 * Performs PPR virtualization.
4480 *
4481 * @returns VBox strict status code.
4482 * @param pVCpu The cross context virtual CPU structure.
4483 */
4484IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4485{
4486 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4487 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4488
4489 /*
4490 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4491 * or EOI-virtualization.
4492 *
4493 * See Intel spec. 29.1.3 "PPR Virtualization".
4494 */
4495 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4496 uint32_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4497
4498 uint32_t uPpr;
4499 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4500 uPpr = uTpr & 0xff;
4501 else
4502 uPpr = uSvi & 0xf0;
4503
4504 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4505 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4506}
4507
4508
4509/**
4510 * Performs VMX TPR virtualization.
4511 *
4512 * @returns VBox strict status code.
4513 * @param pVCpu The cross context virtual CPU structure.
4514 */
4515IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4516{
4517 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4518
4519 /*
4520 * We should have already performed the virtual-APIC write to the TPR offset
4521 * in the virtual-APIC page. We now perform TPR virtualization.
4522 *
4523 * See Intel spec. 29.1.2 "TPR Virtualization".
4524 */
4525 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4526 {
4527 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4528 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4529
4530 /*
4531 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4532 * See Intel spec. 29.1.2 "TPR Virtualization".
4533 */
4534 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4535 {
4536 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4537 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4538 }
4539 }
4540 else
4541 {
4542 iemVmxPprVirtualization(pVCpu);
4543 iemVmxEvalPendingVirtIntrs(pVCpu);
4544 }
4545
4546 return VINF_SUCCESS;
4547}
4548
4549
4550/**
4551 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4552 * not.
4553 *
4554 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4555 * @param pVCpu The cross context virtual CPU structure.
4556 * @param uVector The interrupt that was acknowledged using an EOI.
4557 */
4558IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4559{
4560 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4561 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4562
4563 if (uVector < 64)
4564 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4565 if (uVector < 128)
4566 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4567 if (uVector < 192)
4568 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4569 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4570}
4571
4572
4573/**
4574 * Performs EOI virtualization.
4575 *
4576 * @returns VBox strict status code.
4577 * @param pVCpu The cross context virtual CPU structure.
4578 */
4579IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4580{
4581 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4582 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4583
4584 /*
4585 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4586 * and get the next guest-interrupt that's in-service (if any).
4587 *
4588 * See Intel spec. 29.1.4 "EOI Virtualization".
4589 */
4590 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4591 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4592 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4593
4594 uint8_t uVector = uSvi;
4595 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4596
4597 uVector = 0;
4598 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4599
4600 if (uVector)
4601 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4602 else
4603 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4604
4605 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4606 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4607
4608 iemVmxPprVirtualization(pVCpu);
4609 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4610 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4611 iemVmxEvalPendingVirtIntrs(pVCpu);
4612 return VINF_SUCCESS;
4613}
4614
4615
4616/**
4617 * Performs self-IPI virtualization.
4618 *
4619 * @returns VBox strict status code.
4620 * @param pVCpu The cross context virtual CPU structure.
4621 */
4622IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4623{
4624 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4625 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4626
4627 /*
4628 * We should have already performed the virtual-APIC write to the self-IPI offset
4629 * in the virtual-APIC page. We now perform self-IPI virtualization.
4630 *
4631 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4632 */
4633 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4634 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4635 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4636 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4637 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4638 if (uVector > uRvi)
4639 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4640 iemVmxEvalPendingVirtIntrs(pVCpu);
4641 return VINF_SUCCESS;
4642}
4643
4644
4645/**
4646 * Performs VMX APIC-write emulation.
4647 *
4648 * @returns VBox strict status code.
4649 * @param pVCpu The cross context virtual CPU structure.
4650 */
4651IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4652{
4653 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4654
4655 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4656 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4657
4658 /*
4659 * Perform APIC-write emulation based on the virtual-APIC register written.
4660 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4661 */
4662 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4663 VBOXSTRICTRC rcStrict;
4664 switch (offApicWrite)
4665 {
4666 case XAPIC_OFF_TPR:
4667 {
4668 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4669 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4670 uTpr &= UINT32_C(0x000000ff);
4671 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4672 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4673 rcStrict = iemVmxTprVirtualization(pVCpu);
4674 break;
4675 }
4676
4677 case XAPIC_OFF_EOI:
4678 {
4679 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4680 {
4681 /* Clear VEOI and perform EOI virtualization. */
4682 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4683 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4684 rcStrict = iemVmxEoiVirtualization(pVCpu);
4685 }
4686 else
4687 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4688 break;
4689 }
4690
4691 case XAPIC_OFF_ICR_LO:
4692 {
4693 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4694 {
4695 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4696 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4697 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4698 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4699 if ( !(uIcrLo & fIcrLoMb0)
4700 && (uIcrLo & fIcrLoMb1))
4701 {
4702 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4703 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4704 }
4705 else
4706 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4707 }
4708 else
4709 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4710 break;
4711 }
4712
4713 case XAPIC_OFF_ICR_HI:
4714 {
4715 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4716 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4717 uIcrHi &= UINT32_C(0xff000000);
4718 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4719 rcStrict = VINF_SUCCESS;
4720 break;
4721 }
4722
4723 default:
4724 {
4725 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4726 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4727 break;
4728 }
4729 }
4730
4731 return rcStrict;
4732}
4733
4734
4735/**
4736 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4737 *
4738 * @param pVCpu The cross context virtual CPU structure.
4739 * @param pszInstr The VMX instruction name (for logging purposes).
4740 */
4741DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4742{
4743 /*
4744 * Guest Control Registers, Debug Registers, and MSRs.
4745 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4746 */
4747 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4748 const char * const pszFailure = "VM-exit";
4749 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4750
4751 /* CR0 reserved bits. */
4752 {
4753 /* CR0 MB1 bits. */
4754 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4755 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4756 if (fUnrestrictedGuest)
4757 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4758 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4759 { /* likely */ }
4760 else
4761 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4762
4763 /* CR0 MBZ bits. */
4764 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4765 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4766 { /* likely */ }
4767 else
4768 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4769
4770 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4771 if ( !fUnrestrictedGuest
4772 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4773 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4774 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4775 }
4776
4777 /* CR4 reserved bits. */
4778 {
4779 /* CR4 MB1 bits. */
4780 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4781 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4782 { /* likely */ }
4783 else
4784 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4785
4786 /* CR4 MBZ bits. */
4787 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4788 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4789 { /* likely */ }
4790 else
4791 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4792 }
4793
4794 /* DEBUGCTL MSR. */
4795 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4796 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4797 { /* likely */ }
4798 else
4799 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4800
4801 /* 64-bit CPU checks. */
4802 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4803 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4804 {
4805 if (fGstInLongMode)
4806 {
4807 /* PAE must be set. */
4808 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4809 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4810 { /* likely */ }
4811 else
4812 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4813 }
4814 else
4815 {
4816 /* PCIDE should not be set. */
4817 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4818 { /* likely */ }
4819 else
4820 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4821 }
4822
4823 /* CR3. */
4824 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4825 { /* likely */ }
4826 else
4827 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4828
4829 /* DR7. */
4830 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4831 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4832 { /* likely */ }
4833 else
4834 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4835
4836 /* SYSENTER ESP and SYSENTER EIP. */
4837 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4838 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4839 { /* likely */ }
4840 else
4841 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4842 }
4843
4844 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4845 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4846
4847 /* PAT MSR. */
4848 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4849 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4850 { /* likely */ }
4851 else
4852 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4853
4854 /* EFER MSR. */
4855 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4856 {
4857 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4858 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4859 { /* likely */ }
4860 else
4861 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4862
4863 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4864 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4865 if ( fGstLma == fGstInLongMode
4866 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4867 || fGstLma == fGstLme))
4868 { /* likely */ }
4869 else
4870 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4871 }
4872
4873 /* We don't support IA32_BNDCFGS MSR yet. */
4874 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4875
4876 NOREF(pszInstr);
4877 NOREF(pszFailure);
4878 return VINF_SUCCESS;
4879}
4880
4881
4882/**
4883 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4884 *
4885 * @param pVCpu The cross context virtual CPU structure.
4886 * @param pszInstr The VMX instruction name (for logging purposes).
4887 */
4888DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4889{
4890 /*
4891 * Segment registers.
4892 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4893 */
4894 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4895 const char * const pszFailure = "VM-exit";
4896 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4897 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4898 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4899
4900 /* Selectors. */
4901 if ( !fGstInV86Mode
4902 && !fUnrestrictedGuest
4903 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4904 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4905
4906 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4907 {
4908 CPUMSELREG SelReg;
4909 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4910 if (RT_LIKELY(rc == VINF_SUCCESS))
4911 { /* likely */ }
4912 else
4913 return rc;
4914
4915 /*
4916 * Virtual-8086 mode checks.
4917 */
4918 if (fGstInV86Mode)
4919 {
4920 /* Base address. */
4921 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4922 { /* likely */ }
4923 else
4924 {
4925 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4926 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4927 }
4928
4929 /* Limit. */
4930 if (SelReg.u32Limit == 0xffff)
4931 { /* likely */ }
4932 else
4933 {
4934 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4935 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4936 }
4937
4938 /* Attribute. */
4939 if (SelReg.Attr.u == 0xf3)
4940 { /* likely */ }
4941 else
4942 {
4943 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4944 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4945 }
4946
4947 /* We're done; move to checking the next segment. */
4948 continue;
4949 }
4950
4951 /* Checks done by 64-bit CPUs. */
4952 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4953 {
4954 /* Base address. */
4955 if ( iSegReg == X86_SREG_FS
4956 || iSegReg == X86_SREG_GS)
4957 {
4958 if (X86_IS_CANONICAL(SelReg.u64Base))
4959 { /* likely */ }
4960 else
4961 {
4962 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4963 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4964 }
4965 }
4966 else if (iSegReg == X86_SREG_CS)
4967 {
4968 if (!RT_HI_U32(SelReg.u64Base))
4969 { /* likely */ }
4970 else
4971 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
4972 }
4973 else
4974 {
4975 if ( SelReg.Attr.n.u1Unusable
4976 || !RT_HI_U32(SelReg.u64Base))
4977 { /* likely */ }
4978 else
4979 {
4980 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4981 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4982 }
4983 }
4984 }
4985
4986 /*
4987 * Checks outside Virtual-8086 mode.
4988 */
4989 uint8_t const uSegType = SelReg.Attr.n.u4Type;
4990 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
4991 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
4992 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
4993 uint8_t const fPresent = SelReg.Attr.n.u1Present;
4994 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
4995 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
4996 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
4997
4998 /* Code or usable segment. */
4999 if ( iSegReg == X86_SREG_CS
5000 || fUsable)
5001 {
5002 /* Reserved bits (bits 31:17 and bits 11:8). */
5003 if (!(SelReg.Attr.u & 0xfffe0f00))
5004 { /* likely */ }
5005 else
5006 {
5007 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5008 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5009 }
5010
5011 /* Descriptor type. */
5012 if (fCodeDataSeg)
5013 { /* likely */ }
5014 else
5015 {
5016 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5017 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5018 }
5019
5020 /* Present. */
5021 if (fPresent)
5022 { /* likely */ }
5023 else
5024 {
5025 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5026 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5027 }
5028
5029 /* Granularity. */
5030 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5031 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5032 { /* likely */ }
5033 else
5034 {
5035 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5036 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5037 }
5038 }
5039
5040 if (iSegReg == X86_SREG_CS)
5041 {
5042 /* Segment Type and DPL. */
5043 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5044 && fUnrestrictedGuest)
5045 {
5046 if (uDpl == 0)
5047 { /* likely */ }
5048 else
5049 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5050 }
5051 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5052 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5053 {
5054 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5055 if (uDpl == AttrSs.n.u2Dpl)
5056 { /* likely */ }
5057 else
5058 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5059 }
5060 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5061 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5062 {
5063 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5064 if (uDpl <= AttrSs.n.u2Dpl)
5065 { /* likely */ }
5066 else
5067 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5068 }
5069 else
5070 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5071
5072 /* Def/Big. */
5073 if ( fGstInLongMode
5074 && fSegLong)
5075 {
5076 if (uDefBig == 0)
5077 { /* likely */ }
5078 else
5079 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5080 }
5081 }
5082 else if (iSegReg == X86_SREG_SS)
5083 {
5084 /* Segment Type. */
5085 if ( !fUsable
5086 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5087 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5088 { /* likely */ }
5089 else
5090 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5091
5092 /* DPL. */
5093 if (!fUnrestrictedGuest)
5094 {
5095 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5096 { /* likely */ }
5097 else
5098 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5099 }
5100 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5101 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5102 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5103 {
5104 if (uDpl == 0)
5105 { /* likely */ }
5106 else
5107 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5108 }
5109 }
5110 else
5111 {
5112 /* DS, ES, FS, GS. */
5113 if (fUsable)
5114 {
5115 /* Segment type. */
5116 if (uSegType & X86_SEL_TYPE_ACCESSED)
5117 { /* likely */ }
5118 else
5119 {
5120 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5121 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5122 }
5123
5124 if ( !(uSegType & X86_SEL_TYPE_CODE)
5125 || (uSegType & X86_SEL_TYPE_READ))
5126 { /* likely */ }
5127 else
5128 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5129
5130 /* DPL. */
5131 if ( !fUnrestrictedGuest
5132 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5133 {
5134 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5135 { /* likely */ }
5136 else
5137 {
5138 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5139 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5140 }
5141 }
5142 }
5143 }
5144 }
5145
5146 /*
5147 * LDTR.
5148 */
5149 {
5150 CPUMSELREG Ldtr;
5151 Ldtr.Sel = pVmcs->GuestLdtr;
5152 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5153 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5154 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5155
5156 if (!Ldtr.Attr.n.u1Unusable)
5157 {
5158 /* Selector. */
5159 if (!(Ldtr.Sel & X86_SEL_LDT))
5160 { /* likely */ }
5161 else
5162 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5163
5164 /* Base. */
5165 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5166 {
5167 if (X86_IS_CANONICAL(Ldtr.u64Base))
5168 { /* likely */ }
5169 else
5170 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5171 }
5172
5173 /* Attributes. */
5174 /* Reserved bits (bits 31:17 and bits 11:8). */
5175 if (!(Ldtr.Attr.u & 0xfffe0f00))
5176 { /* likely */ }
5177 else
5178 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5179
5180 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5181 { /* likely */ }
5182 else
5183 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5184
5185 if (!Ldtr.Attr.n.u1DescType)
5186 { /* likely */ }
5187 else
5188 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5189
5190 if (Ldtr.Attr.n.u1Present)
5191 { /* likely */ }
5192 else
5193 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5194
5195 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5196 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5197 { /* likely */ }
5198 else
5199 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5200 }
5201 }
5202
5203 /*
5204 * TR.
5205 */
5206 {
5207 CPUMSELREG Tr;
5208 Tr.Sel = pVmcs->GuestTr;
5209 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5210 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5211 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5212
5213 /* Selector. */
5214 if (!(Tr.Sel & X86_SEL_LDT))
5215 { /* likely */ }
5216 else
5217 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5218
5219 /* Base. */
5220 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5221 {
5222 if (X86_IS_CANONICAL(Tr.u64Base))
5223 { /* likely */ }
5224 else
5225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5226 }
5227
5228 /* Attributes. */
5229 /* Reserved bits (bits 31:17 and bits 11:8). */
5230 if (!(Tr.Attr.u & 0xfffe0f00))
5231 { /* likely */ }
5232 else
5233 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5234
5235 if (!Tr.Attr.n.u1Unusable)
5236 { /* likely */ }
5237 else
5238 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5239
5240 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5241 || ( !fGstInLongMode
5242 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5243 { /* likely */ }
5244 else
5245 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5246
5247 if (!Tr.Attr.n.u1DescType)
5248 { /* likely */ }
5249 else
5250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5251
5252 if (Tr.Attr.n.u1Present)
5253 { /* likely */ }
5254 else
5255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5256
5257 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5258 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5259 { /* likely */ }
5260 else
5261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5262 }
5263
5264 NOREF(pszInstr);
5265 NOREF(pszFailure);
5266 return VINF_SUCCESS;
5267}
5268
5269
5270/**
5271 * Checks guest GDTR and IDTR as part of VM-entry.
5272 *
5273 * @param pVCpu The cross context virtual CPU structure.
5274 * @param pszInstr The VMX instruction name (for logging purposes).
5275 */
5276DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5277{
5278 /*
5279 * GDTR and IDTR.
5280 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5281 */
5282 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5283 const char *const pszFailure = "VM-exit";
5284
5285 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5286 {
5287 /* Base. */
5288 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5289 { /* likely */ }
5290 else
5291 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5292
5293 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5294 { /* likely */ }
5295 else
5296 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5297 }
5298
5299 /* Limit. */
5300 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5301 { /* likely */ }
5302 else
5303 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5304
5305 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5306 { /* likely */ }
5307 else
5308 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5309
5310 NOREF(pszInstr);
5311 NOREF(pszFailure);
5312 return VINF_SUCCESS;
5313}
5314
5315
5316/**
5317 * Checks guest RIP and RFLAGS as part of VM-entry.
5318 *
5319 * @param pVCpu The cross context virtual CPU structure.
5320 * @param pszInstr The VMX instruction name (for logging purposes).
5321 */
5322DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5323{
5324 /*
5325 * RIP and RFLAGS.
5326 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5327 */
5328 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5329 const char *const pszFailure = "VM-exit";
5330 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5331
5332 /* RIP. */
5333 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5334 {
5335 X86DESCATTR AttrCs;
5336 AttrCs.u = pVmcs->u32GuestCsAttr;
5337 if ( !fGstInLongMode
5338 || !AttrCs.n.u1Long)
5339 {
5340 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5341 { /* likely */ }
5342 else
5343 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5344 }
5345
5346 if ( fGstInLongMode
5347 && AttrCs.n.u1Long)
5348 {
5349 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5350 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5351 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5352 { /* likely */ }
5353 else
5354 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5355 }
5356 }
5357
5358 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5359 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5360 : pVmcs->u64GuestRFlags.s.Lo;
5361 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5362 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5363 { /* likely */ }
5364 else
5365 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5366
5367 if ( fGstInLongMode
5368 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5369 {
5370 if (!(uGuestRFlags & X86_EFL_VM))
5371 { /* likely */ }
5372 else
5373 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5374 }
5375
5376 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5377 {
5378 if (uGuestRFlags & X86_EFL_IF)
5379 { /* likely */ }
5380 else
5381 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5382 }
5383
5384 NOREF(pszInstr);
5385 NOREF(pszFailure);
5386 return VINF_SUCCESS;
5387}
5388
5389
5390/**
5391 * Checks guest non-register state as part of VM-entry.
5392 *
5393 * @param pVCpu The cross context virtual CPU structure.
5394 * @param pszInstr The VMX instruction name (for logging purposes).
5395 */
5396DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5397{
5398 /*
5399 * Guest non-register state.
5400 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5401 */
5402 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5403 const char *const pszFailure = "VM-exit";
5404
5405 /*
5406 * Activity state.
5407 */
5408 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5409 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5410 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5411 { /* likely */ }
5412 else
5413 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5414
5415 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5416 if ( !AttrSs.n.u2Dpl
5417 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5418 { /* likely */ }
5419 else
5420 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5421
5422 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5423 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5424 {
5425 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5426 { /* likely */ }
5427 else
5428 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5429 }
5430
5431 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5432 {
5433 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5434 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5435 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5436 switch (pVmcs->u32GuestActivityState)
5437 {
5438 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5439 {
5440 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5441 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5442 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5443 && ( uVector == X86_XCPT_DB
5444 || uVector == X86_XCPT_MC))
5445 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5446 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5447 { /* likely */ }
5448 else
5449 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5450 break;
5451 }
5452
5453 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5454 {
5455 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5456 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5457 && uVector == X86_XCPT_MC))
5458 { /* likely */ }
5459 else
5460 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5461 break;
5462 }
5463
5464 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5465 default:
5466 break;
5467 }
5468 }
5469
5470 /*
5471 * Interruptibility state.
5472 */
5473 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5474 { /* likely */ }
5475 else
5476 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5477
5478 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5479 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5480 { /* likely */ }
5481 else
5482 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5483
5484 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5485 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5486 { /* likely */ }
5487 else
5488 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5489
5490 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5491 {
5492 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5493 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5494 {
5495 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5496 { /* likely */ }
5497 else
5498 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5499 }
5500 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5501 {
5502 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5503 { /* likely */ }
5504 else
5505 {
5506 /*
5507 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5508 * We update the Exit qualification only when blocking-by-STI is set
5509 * without blocking-by-MovSS being set. Although in practise it does not
5510 * make much difference since the order of checks are implementation defined.
5511 */
5512 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5513 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5514 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5515 }
5516
5517 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5518 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5519 { /* likely */ }
5520 else
5521 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5522 }
5523 }
5524
5525 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5526 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5527 { /* likely */ }
5528 else
5529 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5530
5531 /* We don't support SGX yet. So enclave-interruption must not be set. */
5532 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5533 { /* likely */ }
5534 else
5535 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5536
5537 /*
5538 * Pending debug exceptions.
5539 */
5540 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5541 ? pVmcs->u64GuestPendingDbgXcpts.u
5542 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5543 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5544 { /* likely */ }
5545 else
5546 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5547
5548 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5549 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5550 {
5551 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5552 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5553 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5554 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5555
5556 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5557 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5558 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5559 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5560 }
5561
5562 /* We don't support RTM (Real-time Transactional Memory) yet. */
5563 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5564 { /* likely */ }
5565 else
5566 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5567
5568 /*
5569 * VMCS link pointer.
5570 */
5571 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5572 {
5573 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5574 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5575 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5576 { /* likely */ }
5577 else
5578 {
5579 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5580 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5581 }
5582
5583 /* Validate the address. */
5584 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5585 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5586 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5587 { /* likely */ }
5588 else
5589 {
5590 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5591 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5592 }
5593 }
5594
5595 NOREF(pszInstr);
5596 NOREF(pszFailure);
5597 return VINF_SUCCESS;
5598}
5599
5600
5601/**
5602 * Checks guest PDPTEs as part of VM-entry.
5603 *
5604 * @param pVCpu The cross context virtual CPU structure.
5605 * @param pfPdpesMapped Where to store whether PAE PDPTEs (and PDPT) have been
5606 * mapped as part of checking guest state.
5607 * @param pszInstr The VMX instruction name (for logging purposes).
5608 */
5609IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, bool *pfPdpesMapped, const char *pszInstr)
5610{
5611 /*
5612 * Guest PDPTEs.
5613 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5614 */
5615 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5616 const char * const pszFailure = "VM-exit";
5617 *pfPdpesMapped = false;
5618
5619 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
5620 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
5621 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
5622 {
5623#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5624 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
5625 {
5626 /* Get PDPTEs from the VMCS. */
5627 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
5628 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
5629 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
5630 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
5631 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
5632
5633 /* Check validity of the PDPTEs. */
5634 bool const fValid = PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]);
5635 if (fValid)
5636 { /* likely */ }
5637 else
5638 {
5639 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5640 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5641 }
5642 }
5643 else
5644#endif
5645 {
5646 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
5647 if (RT_SUCCESS(rc))
5648 *pfPdpesMapped = true;
5649 else
5650 {
5651 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5652 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5653 }
5654 }
5655 }
5656
5657 NOREF(pszInstr);
5658 NOREF(pszFailure);
5659 return VINF_SUCCESS;
5660}
5661
5662
5663/**
5664 * Checks guest-state as part of VM-entry.
5665 *
5666 * @returns VBox status code.
5667 * @param pVCpu The cross context virtual CPU structure.
5668 * @param pfPdpesMapped Where to store whether PAE PDPTEs (and PDPT) have been
5669 * mapped as part of checking guest state.
5670 * @param pszInstr The VMX instruction name (for logging purposes).
5671 */
5672IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, bool *pfPdpesMapped, const char *pszInstr)
5673{
5674 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5675 if (RT_SUCCESS(rc))
5676 {
5677 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5678 if (RT_SUCCESS(rc))
5679 {
5680 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5681 if (RT_SUCCESS(rc))
5682 {
5683 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5684 if (RT_SUCCESS(rc))
5685 {
5686 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5687 if (RT_SUCCESS(rc))
5688 return iemVmxVmentryCheckGuestPdptes(pVCpu, pfPdpesMapped, pszInstr);
5689 }
5690 }
5691 }
5692 }
5693 return rc;
5694}
5695
5696
5697/**
5698 * Checks host-state as part of VM-entry.
5699 *
5700 * @returns VBox status code.
5701 * @param pVCpu The cross context virtual CPU structure.
5702 * @param pszInstr The VMX instruction name (for logging purposes).
5703 */
5704IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5705{
5706 /*
5707 * Host Control Registers and MSRs.
5708 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5709 */
5710 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5711 const char * const pszFailure = "VMFail";
5712
5713 /* CR0 reserved bits. */
5714 {
5715 /* CR0 MB1 bits. */
5716 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5717 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5718 { /* likely */ }
5719 else
5720 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5721
5722 /* CR0 MBZ bits. */
5723 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5724 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5725 { /* likely */ }
5726 else
5727 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5728 }
5729
5730 /* CR4 reserved bits. */
5731 {
5732 /* CR4 MB1 bits. */
5733 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5734 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5735 { /* likely */ }
5736 else
5737 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5738
5739 /* CR4 MBZ bits. */
5740 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5741 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5742 { /* likely */ }
5743 else
5744 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5745 }
5746
5747 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5748 {
5749 /* CR3 reserved bits. */
5750 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5751 { /* likely */ }
5752 else
5753 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5754
5755 /* SYSENTER ESP and SYSENTER EIP. */
5756 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5757 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5758 { /* likely */ }
5759 else
5760 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5761 }
5762
5763 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5764 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5765
5766 /* PAT MSR. */
5767 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5768 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5769 { /* likely */ }
5770 else
5771 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5772
5773 /* EFER MSR. */
5774 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5775 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5776 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5777 { /* likely */ }
5778 else
5779 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5780
5781 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5782 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5783 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5784 if ( fHostInLongMode == fHostLma
5785 && fHostInLongMode == fHostLme)
5786 { /* likely */ }
5787 else
5788 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5789
5790 /*
5791 * Host Segment and Descriptor-Table Registers.
5792 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5793 */
5794 /* Selector RPL and TI. */
5795 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5796 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5797 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5798 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5799 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5800 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5801 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5802 { /* likely */ }
5803 else
5804 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5805
5806 /* CS and TR selectors cannot be 0. */
5807 if ( pVmcs->HostCs
5808 && pVmcs->HostTr)
5809 { /* likely */ }
5810 else
5811 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5812
5813 /* SS cannot be 0 if 32-bit host. */
5814 if ( fHostInLongMode
5815 || pVmcs->HostSs)
5816 { /* likely */ }
5817 else
5818 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5819
5820 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5821 {
5822 /* FS, GS, GDTR, IDTR, TR base address. */
5823 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5824 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5825 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5826 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5827 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5828 { /* likely */ }
5829 else
5830 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5831 }
5832
5833 /*
5834 * Host address-space size for 64-bit CPUs.
5835 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5836 */
5837 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5838 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5839 {
5840 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5841
5842 /* Logical processor in IA-32e mode. */
5843 if (fCpuInLongMode)
5844 {
5845 if (fHostInLongMode)
5846 {
5847 /* PAE must be set. */
5848 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5849 { /* likely */ }
5850 else
5851 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5852
5853 /* RIP must be canonical. */
5854 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5855 { /* likely */ }
5856 else
5857 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5858 }
5859 else
5860 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5861 }
5862 else
5863 {
5864 /* Logical processor is outside IA-32e mode. */
5865 if ( !fGstInLongMode
5866 && !fHostInLongMode)
5867 {
5868 /* PCIDE should not be set. */
5869 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5870 { /* likely */ }
5871 else
5872 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5873
5874 /* The high 32-bits of RIP MBZ. */
5875 if (!pVmcs->u64HostRip.s.Hi)
5876 { /* likely */ }
5877 else
5878 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5879 }
5880 else
5881 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5882 }
5883 }
5884 else
5885 {
5886 /* Host address-space size for 32-bit CPUs. */
5887 if ( !fGstInLongMode
5888 && !fHostInLongMode)
5889 { /* likely */ }
5890 else
5891 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5892 }
5893
5894 NOREF(pszInstr);
5895 NOREF(pszFailure);
5896 return VINF_SUCCESS;
5897}
5898
5899
5900#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5901/**
5902 * Checks the EPT pointer VMCS field as part of VM-entry.
5903 *
5904 * @returns VBox status code.
5905 * @param pVCpu The cross context virtual CPU structure.
5906 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
5907 * updated on success). Optional, can be NULL.
5908 */
5909IEM_STATIC int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, VMXVDIAG *penmVmxDiag)
5910{
5911 VMXVDIAG enmVmxDiag;
5912 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5913
5914 /* Reserved bits. */
5915 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
5916 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
5917 if (pVmcs->u64EptPtr.u & fValidMask)
5918 {
5919 /* Memory Type. */
5920 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
5921 uint8_t const fMemType = RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_MEMTYPE);
5922 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
5923 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
5924 || ( fMemType == VMX_EPTP_MEMTYPE_UC
5925 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
5926 {
5927 /*
5928 * Page walk length (PML4).
5929 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
5930 * of 5 but that seems to be removed from the latest specs. leaving only PML4
5931 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
5932 */
5933 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
5934 if (RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
5935 {
5936 /* Access and dirty bits support in EPT structures. */
5937 if ( !RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_ACCESS_DIRTY)
5938 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
5939 return VINF_SUCCESS;
5940
5941 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
5942 }
5943 else
5944 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
5945 }
5946 else
5947 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
5948 }
5949 else
5950 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
5951
5952 if (penmVmxDiag)
5953 *penmVmxDiag = enmVmxDiag;
5954 return VERR_VMX_VMENTRY_FAILED;
5955}
5956#endif
5957
5958
5959/**
5960 * Checks VMCS controls fields as part of VM-entry.
5961 *
5962 * @returns VBox status code.
5963 * @param pVCpu The cross context virtual CPU structure.
5964 * @param pszInstr The VMX instruction name (for logging purposes).
5965 *
5966 * @remarks This may update secondary-processor based VM-execution control fields
5967 * in the current VMCS if necessary.
5968 */
5969IEM_STATIC int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr)
5970{
5971 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5972 const char * const pszFailure = "VMFail";
5973
5974 /*
5975 * VM-execution controls.
5976 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
5977 */
5978 {
5979 /* Pin-based VM-execution controls. */
5980 {
5981 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
5982 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
5983 { /* likely */ }
5984 else
5985 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
5986
5987 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
5988 { /* likely */ }
5989 else
5990 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
5991 }
5992
5993 /* Processor-based VM-execution controls. */
5994 {
5995 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
5996 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
5997 { /* likely */ }
5998 else
5999 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6000
6001 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6002 { /* likely */ }
6003 else
6004 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6005 }
6006
6007 /* Secondary processor-based VM-execution controls. */
6008 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6009 {
6010 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6011 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6012 { /* likely */ }
6013 else
6014 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6015
6016 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6017 { /* likely */ }
6018 else
6019 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6020 }
6021 else
6022 Assert(!pVmcs->u32ProcCtls2);
6023
6024 /* CR3-target count. */
6025 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6026 { /* likely */ }
6027 else
6028 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6029
6030 /* I/O bitmaps physical addresses. */
6031 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6032 {
6033 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6034 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6035 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6036 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6037 { /* likely */ }
6038 else
6039 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6040
6041 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6042 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6043 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6044 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6045 { /* likely */ }
6046 else
6047 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6048 }
6049
6050 /* MSR bitmap physical address. */
6051 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6052 {
6053 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6054 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6055 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6056 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6057 { /* likely */ }
6058 else
6059 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6060 }
6061
6062 /* TPR shadow related controls. */
6063 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6064 {
6065 /* Virtual-APIC page physical address. */
6066 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6067 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6068 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6069 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6070 { /* likely */ }
6071 else
6072 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6073
6074 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6075 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6076 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6077 { /* likely */ }
6078 else
6079 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6080
6081 /* The rest done XXX document */
6082 }
6083 else
6084 {
6085 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6086 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6087 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6088 { /* likely */ }
6089 else
6090 {
6091 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6092 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6093 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6094 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6095 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6096 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6097 }
6098 }
6099
6100 /* NMI exiting and virtual-NMIs. */
6101 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6102 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6103 { /* likely */ }
6104 else
6105 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6106
6107 /* Virtual-NMIs and NMI-window exiting. */
6108 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6109 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6110 { /* likely */ }
6111 else
6112 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6113
6114 /* Virtualize APIC accesses. */
6115 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6116 {
6117 /* APIC-access physical address. */
6118 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6119 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6120 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6121 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6122 { /* likely */ }
6123 else
6124 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6125
6126 /*
6127 * Disallow APIC-access page and virtual-APIC page from being the same address.
6128 * Note! This is not an Intel requirement, but one imposed by our implementation.
6129 */
6130 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6131 * redirecting accesses between the APIC-access page and the virtual-APIC
6132 * page. If any nested hypervisor requires this, we can implement it later. */
6133 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6134 {
6135 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6136 if (GCPhysVirtApic != GCPhysApicAccess)
6137 { /* likely */ }
6138 else
6139 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6140 }
6141 }
6142
6143 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6144 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6145 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6146 { /* likely */ }
6147 else
6148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6149
6150 /* Virtual-interrupt delivery requires external interrupt exiting. */
6151 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6152 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6153 { /* likely */ }
6154 else
6155 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6156
6157 /* VPID. */
6158 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6159 || pVmcs->u16Vpid != 0)
6160 { /* likely */ }
6161 else
6162 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6163
6164#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6165 /* Extended-Page-Table Pointer (EPTP). */
6166 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6167 {
6168 VMXVDIAG enmVmxDiag;
6169 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, &enmVmxDiag);
6170 if (RT_SUCCESS(rc))
6171 { /* likely */ }
6172 else
6173 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6174 }
6175#else
6176 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6177#endif
6178
6179 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6180 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6181 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6182 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6183 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6184 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6185 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6186
6187 /* VMCS shadowing. */
6188 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6189 {
6190 /* VMREAD-bitmap physical address. */
6191 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6192 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6193 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6194 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6195 { /* likely */ }
6196 else
6197 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6198
6199 /* VMWRITE-bitmap physical address. */
6200 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6201 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6202 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6203 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6204 { /* likely */ }
6205 else
6206 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6207 }
6208 }
6209
6210 /*
6211 * VM-exit controls.
6212 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6213 */
6214 {
6215 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6216 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6217 { /* likely */ }
6218 else
6219 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6220
6221 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6222 { /* likely */ }
6223 else
6224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6225
6226 /* Save preemption timer without activating it. */
6227 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6228 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6229 { /* likely */ }
6230 else
6231 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6232
6233 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6234 if (pVmcs->u32ExitMsrStoreCount)
6235 {
6236 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6237 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6238 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6239 { /* likely */ }
6240 else
6241 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6242 }
6243
6244 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6245 if (pVmcs->u32ExitMsrLoadCount)
6246 {
6247 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6248 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6249 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6250 { /* likely */ }
6251 else
6252 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6253 }
6254 }
6255
6256 /*
6257 * VM-entry controls.
6258 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6259 */
6260 {
6261 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6262 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6263 { /* likely */ }
6264 else
6265 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6266
6267 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6268 { /* likely */ }
6269 else
6270 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6271
6272 /* Event injection. */
6273 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6274 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6275 {
6276 /* Type and vector. */
6277 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6278 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6279 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6280 if ( !uRsvd
6281 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6282 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6283 { /* likely */ }
6284 else
6285 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6286
6287 /* Exception error code. */
6288 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6289 {
6290 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6291 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6292 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6293 { /* likely */ }
6294 else
6295 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6296
6297 /* Exceptions that provide an error code. */
6298 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6299 && ( uVector == X86_XCPT_DF
6300 || uVector == X86_XCPT_TS
6301 || uVector == X86_XCPT_NP
6302 || uVector == X86_XCPT_SS
6303 || uVector == X86_XCPT_GP
6304 || uVector == X86_XCPT_PF
6305 || uVector == X86_XCPT_AC))
6306 { /* likely */ }
6307 else
6308 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6309
6310 /* Exception error-code reserved bits. */
6311 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6312 { /* likely */ }
6313 else
6314 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6315
6316 /* Injecting a software interrupt, software exception or privileged software exception. */
6317 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6318 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6319 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6320 {
6321 /* Instruction length must be in the range 0-15. */
6322 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6323 { /* likely */ }
6324 else
6325 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6326
6327 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6328 if ( pVmcs->u32EntryInstrLen != 0
6329 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6330 { /* likely */ }
6331 else
6332 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6333 }
6334 }
6335 }
6336
6337 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6338 if (pVmcs->u32EntryMsrLoadCount)
6339 {
6340 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6341 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6342 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6343 { /* likely */ }
6344 else
6345 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6346 }
6347
6348 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6349 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6350 }
6351
6352 NOREF(pszInstr);
6353 NOREF(pszFailure);
6354 return VINF_SUCCESS;
6355}
6356
6357
6358/**
6359 * Loads the guest control registers, debug register and some MSRs as part of
6360 * VM-entry.
6361 *
6362 * @param pVCpu The cross context virtual CPU structure.
6363 */
6364IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6365{
6366 /*
6367 * Load guest control registers, debug registers and MSRs.
6368 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6369 */
6370 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6371
6372 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6373 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6374 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6375 CPUMSetGuestCR0(pVCpu, uGstCr0);
6376 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6377 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6378
6379 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6380 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6381
6382 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6383 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6384 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6385
6386 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6387 {
6388 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6389
6390 /* EFER MSR. */
6391 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6392 {
6393 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6394 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6395 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6396 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6397 if (fGstInLongMode)
6398 {
6399 /* If the nested-guest is in long mode, LMA and LME are both set. */
6400 Assert(fGstPaging);
6401 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6402 }
6403 else
6404 {
6405 /*
6406 * If the nested-guest is outside long mode:
6407 * - With paging: LMA is cleared, LME is cleared.
6408 * - Without paging: LMA is cleared, LME is left unmodified.
6409 */
6410 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6411 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6412 }
6413 }
6414 /* else: see below. */
6415 }
6416
6417 /* PAT MSR. */
6418 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6419 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6420
6421 /* EFER MSR. */
6422 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6423 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6424
6425 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6426 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6427
6428 /* We don't support IA32_BNDCFGS MSR yet. */
6429 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6430
6431 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6432}
6433
6434
6435/**
6436 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6437 *
6438 * @param pVCpu The cross context virtual CPU structure.
6439 */
6440IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6441{
6442 /*
6443 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6444 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6445 */
6446 /* CS, SS, ES, DS, FS, GS. */
6447 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6448 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6449 {
6450 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6451 CPUMSELREG VmcsSelReg;
6452 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6453 AssertRC(rc); NOREF(rc);
6454 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6455 {
6456 pGstSelReg->Sel = VmcsSelReg.Sel;
6457 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6458 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6459 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6460 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6461 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6462 }
6463 else
6464 {
6465 pGstSelReg->Sel = VmcsSelReg.Sel;
6466 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6467 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6468 switch (iSegReg)
6469 {
6470 case X86_SREG_CS:
6471 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6472 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6473 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6474 break;
6475
6476 case X86_SREG_SS:
6477 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6478 pGstSelReg->u32Limit = 0;
6479 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6480 break;
6481
6482 case X86_SREG_ES:
6483 case X86_SREG_DS:
6484 pGstSelReg->u64Base = 0;
6485 pGstSelReg->u32Limit = 0;
6486 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6487 break;
6488
6489 case X86_SREG_FS:
6490 case X86_SREG_GS:
6491 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6492 pGstSelReg->u32Limit = 0;
6493 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6494 break;
6495 }
6496 Assert(pGstSelReg->Attr.n.u1Unusable);
6497 }
6498 }
6499
6500 /* LDTR. */
6501 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6502 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6503 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6504 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6505 {
6506 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6507 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6508 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6509 }
6510 else
6511 {
6512 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6513 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6514 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6515 }
6516
6517 /* TR. */
6518 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6519 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6520 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6521 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6522 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6523 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6524 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6525
6526 /* GDTR. */
6527 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6528 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6529
6530 /* IDTR. */
6531 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6532 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6533}
6534
6535
6536/**
6537 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6538 *
6539 * @returns VBox status code.
6540 * @param pVCpu The cross context virtual CPU structure.
6541 * @param pszInstr The VMX instruction name (for logging purposes).
6542 */
6543IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6544{
6545 /*
6546 * Load guest MSRs.
6547 * See Intel spec. 26.4 "Loading MSRs".
6548 */
6549 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6550 const char *const pszFailure = "VM-exit";
6551
6552 /*
6553 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6554 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6555 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6556 */
6557 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6558 if (!cMsrs)
6559 return VINF_SUCCESS;
6560
6561 /*
6562 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6563 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6564 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6565 */
6566 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6567 if (fIsMsrCountValid)
6568 { /* likely */ }
6569 else
6570 {
6571 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6572 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6573 }
6574
6575 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6576 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6577 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6578 if (RT_SUCCESS(rc))
6579 {
6580 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6581 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6582 {
6583 if ( !pMsr->u32Reserved
6584 && pMsr->u32Msr != MSR_K8_FS_BASE
6585 && pMsr->u32Msr != MSR_K8_GS_BASE
6586 && pMsr->u32Msr != MSR_K6_EFER
6587 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6588 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6589 {
6590 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6591 if (rcStrict == VINF_SUCCESS)
6592 continue;
6593
6594 /*
6595 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6596 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6597 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6598 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6599 * MSR in ring-0 if possible, or come up with a better, generic solution.
6600 */
6601 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6602 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6603 ? kVmxVDiag_Vmentry_MsrLoadRing3
6604 : kVmxVDiag_Vmentry_MsrLoad;
6605 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6606 }
6607 else
6608 {
6609 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6610 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6611 }
6612 }
6613 }
6614 else
6615 {
6616 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6617 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6618 }
6619
6620 NOREF(pszInstr);
6621 NOREF(pszFailure);
6622 return VINF_SUCCESS;
6623}
6624
6625
6626/**
6627 * Loads the guest-state non-register state as part of VM-entry.
6628 *
6629 * @returns VBox status code.
6630 * @param pVCpu The cross context virtual CPU structure.
6631 *
6632 * @remarks This must be called only after loading the nested-guest register state
6633 * (especially nested-guest RIP).
6634 */
6635IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu)
6636{
6637 /*
6638 * Load guest non-register state.
6639 * See Intel spec. 26.6 "Special Features of VM Entry"
6640 */
6641 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6642
6643 /*
6644 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6645 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6646 *
6647 * See Intel spec. 26.6.1 "Interruptibility State".
6648 */
6649 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6650 if ( !fEntryVectoring
6651 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6652 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6653 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6654 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6655
6656 /* NMI blocking. */
6657 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6658 {
6659 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6660 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6661 else
6662 {
6663 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6664 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6665 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6666 }
6667 }
6668 else
6669 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6670
6671 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6672
6673 /*
6674 * Load the PAE PDPTEs from the VMCS when using EPT with PAE paging.
6675 */
6676 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6677 {
6678 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
6679 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
6680 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
6681 {
6682 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6683 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6684 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6685 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6686 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6687 AssertCompile(RT_ELEMENTS(aPaePdptes) == RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes));
6688 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes); i++)
6689 pVCpu->cpum.GstCtx.aPaePdpes[i].u = aPaePdptes[i].u;
6690 }
6691
6692 /*
6693 * Set PGM's copy of the EPT pointer.
6694 * The EPTP has already been validated while checking guest state.
6695 */
6696 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
6697 }
6698
6699 /* VPID is irrelevant. We don't support VPID yet. */
6700
6701 /* Clear address-range monitoring. */
6702 EMMonitorWaitClear(pVCpu);
6703}
6704
6705
6706/**
6707 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
6708 *
6709 * @param pVCpu The cross context virtual CPU structure.
6710 * @param pszInstr The VMX instruction name (for logging purposes).
6711 *
6712 * @remarks This assumes various VMCS related data structure pointers have already
6713 * been verified prior to calling this function.
6714 */
6715IEM_STATIC int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr)
6716{
6717 const char *const pszFailure = "VM-exit";
6718 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6719
6720 /*
6721 * Virtualize APIC accesses.
6722 */
6723 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6724 {
6725 /* APIC-access physical address. */
6726 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6727
6728 /*
6729 * Register the handler for the APIC-access page.
6730 *
6731 * We don't deregister the APIC-access page handler during the VM-exit as a different
6732 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6733 *
6734 * We leave the page registered until the first access that happens outside VMX non-root
6735 * mode. Guest software is allowed to access structures such as the APIC-access page
6736 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6737 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6738 *
6739 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6740 */
6741 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6742 {
6743 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6744 PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
6745 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6746 pVCpu0->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6747 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6748 if (RT_SUCCESS(rc))
6749 { /* likely */ }
6750 else
6751 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6752 }
6753 }
6754
6755 /*
6756 * VMCS shadowing.
6757 */
6758 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6759 {
6760 /* Read the VMREAD-bitmap. */
6761 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6762 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
6763 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
6764 if (RT_SUCCESS(rc))
6765 { /* likely */ }
6766 else
6767 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6768
6769 /* Read the VMWRITE-bitmap. */
6770 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
6771 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
6772 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
6773 if (RT_SUCCESS(rc))
6774 { /* likely */ }
6775 else
6776 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6777 }
6778
6779 /*
6780 * I/O bitmaps.
6781 */
6782 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6783 {
6784 /* Read the IO bitmap A. */
6785 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6786 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
6787 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
6788 if (RT_SUCCESS(rc))
6789 { /* likely */ }
6790 else
6791 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
6792
6793 /* Read the IO bitmap B. */
6794 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6795 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
6796 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
6797 if (RT_SUCCESS(rc))
6798 { /* likely */ }
6799 else
6800 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
6801 }
6802
6803 /*
6804 * TPR shadow and Virtual-APIC page.
6805 */
6806 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6807 {
6808 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6809 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6810 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6811 {
6812 /* Read the VTPR from the virtual-APIC page. */
6813 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6814 uint8_t u8VTpr;
6815 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6816 if (RT_SUCCESS(rc))
6817 { /* likely */ }
6818 else
6819 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6820
6821 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6822 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6823 { /* likely */ }
6824 else
6825 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6826 }
6827 }
6828
6829 /*
6830 * VMCS link pointer.
6831 */
6832 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6833 {
6834 /* Read the VMCS-link pointer from guest memory. */
6835 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6836 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
6837 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
6838 if (RT_SUCCESS(rc))
6839 { /* likely */ }
6840 else
6841 {
6842 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6843 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6844 }
6845
6846 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6847 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6848 { /* likely */ }
6849 else
6850 {
6851 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6852 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6853 }
6854
6855 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6856 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6857 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
6858 { /* likely */ }
6859 else
6860 {
6861 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6862 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6863 }
6864
6865 /* Update our cache of the guest physical address of the shadow VMCS. */
6866 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6867 }
6868
6869 /*
6870 * MSR bitmap.
6871 */
6872 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6873 {
6874 /* Read the MSR bitmap. */
6875 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6876 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
6877 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
6878 if (RT_SUCCESS(rc))
6879 { /* likely */ }
6880 else
6881 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6882 }
6883
6884 NOREF(pszFailure);
6885 NOREF(pszInstr);
6886 return VINF_SUCCESS;
6887}
6888
6889
6890/**
6891 * Loads the guest-state as part of VM-entry.
6892 *
6893 * @returns VBox status code.
6894 * @param pVCpu The cross context virtual CPU structure.
6895 * @param pszInstr The VMX instruction name (for logging purposes).
6896 *
6897 * @remarks This must be done after all the necessary steps prior to loading of
6898 * guest-state (e.g. checking various VMCS state).
6899 */
6900IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6901{
6902 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
6903 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6904
6905 /* Load guest segment registers. */
6906 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6907
6908 /*
6909 * Load guest RIP, RSP and RFLAGS.
6910 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6911 */
6912 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6913 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6914 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6915 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6916
6917 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6918 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6919 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6920
6921 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
6922 iemVmxVmentryLoadGuestNonRegState(pVCpu);
6923
6924 /* Load VMX related structures and state referenced by the VMCS. */
6925 int rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
6926 if (rc == VINF_SUCCESS)
6927 { /* likely */ }
6928 else
6929 return rc;
6930
6931 NOREF(pszInstr);
6932 return VINF_SUCCESS;
6933}
6934
6935
6936/**
6937 * Returns whether there are is a pending debug exception on VM-entry.
6938 *
6939 * @param pVCpu The cross context virtual CPU structure.
6940 * @param pszInstr The VMX instruction name (for logging purposes).
6941 */
6942IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6943{
6944 /*
6945 * Pending debug exceptions.
6946 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6947 */
6948 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6949 Assert(pVmcs);
6950
6951 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6952 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6953 if (fPendingDbgXcpt)
6954 {
6955 uint8_t uEntryIntInfoType;
6956 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6957 if (fEntryVectoring)
6958 {
6959 switch (uEntryIntInfoType)
6960 {
6961 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6962 case VMX_ENTRY_INT_INFO_TYPE_NMI:
6963 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6964 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6965 fPendingDbgXcpt = false;
6966 break;
6967
6968 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
6969 {
6970 /*
6971 * Whether the pending debug exception for software exceptions other than
6972 * #BP and #OF is delivered after injecting the exception or is discard
6973 * is CPU implementation specific. We will discard them (easier).
6974 */
6975 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
6976 if ( uVector != X86_XCPT_BP
6977 && uVector != X86_XCPT_OF)
6978 fPendingDbgXcpt = false;
6979 RT_FALL_THRU();
6980 }
6981 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
6982 {
6983 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6984 fPendingDbgXcpt = false;
6985 break;
6986 }
6987 }
6988 }
6989 else
6990 {
6991 /*
6992 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
6993 * pending debug exception is held pending or is discarded is CPU implementation
6994 * specific. We will discard them (easier).
6995 */
6996 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
6997 fPendingDbgXcpt = false;
6998
6999 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7000 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7001 fPendingDbgXcpt = false;
7002 }
7003 }
7004
7005 NOREF(pszInstr);
7006 return fPendingDbgXcpt;
7007}
7008
7009
7010/**
7011 * Set up the monitor-trap flag (MTF).
7012 *
7013 * @param pVCpu The cross context virtual CPU structure.
7014 * @param pszInstr The VMX instruction name (for logging purposes).
7015 */
7016IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
7017{
7018 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7019 Assert(pVmcs);
7020 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7021 {
7022 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7023 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7024 }
7025 else
7026 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7027 NOREF(pszInstr);
7028}
7029
7030
7031/**
7032 * Sets up NMI-window exiting.
7033 *
7034 * @param pVCpu The cross context virtual CPU structure.
7035 * @param pszInstr The VMX instruction name (for logging purposes).
7036 */
7037IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
7038{
7039 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7040 Assert(pVmcs);
7041 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7042 {
7043 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7044 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7045 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7046 }
7047 else
7048 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7049 NOREF(pszInstr);
7050}
7051
7052
7053/**
7054 * Sets up interrupt-window exiting.
7055 *
7056 * @param pVCpu The cross context virtual CPU structure.
7057 * @param pszInstr The VMX instruction name (for logging purposes).
7058 */
7059IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
7060{
7061 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7062 Assert(pVmcs);
7063 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7064 {
7065 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7066 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7067 }
7068 else
7069 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7070 NOREF(pszInstr);
7071}
7072
7073
7074/**
7075 * Set up the VMX-preemption timer.
7076 *
7077 * @param pVCpu The cross context virtual CPU structure.
7078 * @param pszInstr The VMX instruction name (for logging purposes).
7079 */
7080IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
7081{
7082 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7083 Assert(pVmcs);
7084 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7085 {
7086 /*
7087 * If the timer is 0, we must cause a VM-exit before executing the first
7088 * nested-guest instruction. So we can flag as though the timer has already
7089 * expired and we will check and cause a VM-exit at the right priority elsewhere
7090 * in the code.
7091 */
7092 uint64_t uEntryTick;
7093 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7094 if (uPreemptTimer)
7095 {
7096 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7097 AssertRC(rc);
7098 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7099 }
7100 else
7101 {
7102 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7103 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7104 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7105 }
7106
7107 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7108 }
7109 else
7110 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7111
7112 NOREF(pszInstr);
7113}
7114
7115
7116/**
7117 * Injects an event using TRPM given a VM-entry interruption info. and related
7118 * fields.
7119 *
7120 * @param pVCpu The cross context virtual CPU structure.
7121 * @param pszInstr The VMX instruction name (for logging purposes).
7122 * @param uEntryIntInfo The VM-entry interruption info.
7123 * @param uErrCode The error code associated with the event if any.
7124 * @param cbInstr The VM-entry instruction length (for software
7125 * interrupts and software exceptions). Pass 0
7126 * otherwise.
7127 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7128 */
7129IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7130 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7131{
7132 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7133
7134 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7135 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7136 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7137
7138 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7139
7140 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7141 AssertRC(rc);
7142 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7143
7144 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7145 {
7146 TRPMSetErrorCode(pVCpu, uErrCode);
7147 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7148 }
7149
7150 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7151 {
7152 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7153 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7154 }
7155 else
7156 {
7157 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7158 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7159 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7160 {
7161 TRPMSetInstrLength(pVCpu, cbInstr);
7162 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7163 }
7164 }
7165
7166 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7167 {
7168 TRPMSetTrapDueToIcebp(pVCpu);
7169 Log(("%s: Injecting: icebp\n", pszInstr));
7170 }
7171
7172 NOREF(pszInstr);
7173}
7174
7175
7176/**
7177 * Performs event injection (if any) as part of VM-entry.
7178 *
7179 * @param pVCpu The cross context virtual CPU structure.
7180 * @param pszInstr The VMX instruction name (for logging purposes).
7181 */
7182IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7183{
7184 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7185
7186 /*
7187 * Inject events.
7188 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7189 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7190 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7191 * the actually delivery of this event.
7192 *
7193 * See Intel spec. 26.5 "Event Injection".
7194 */
7195 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7196 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7197
7198 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7199 if (fEntryIntInfoValid)
7200 {
7201 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7202 {
7203 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7204 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7205 }
7206 else
7207 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7208 pVCpu->cpum.GstCtx.cr2);
7209
7210 /*
7211 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7212 *
7213 * However, we do it here on VM-entry as well because while it isn't visible to guest
7214 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7215 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7216 *
7217 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7218 */
7219 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7220 }
7221 else
7222 {
7223 /*
7224 * Inject any pending guest debug exception.
7225 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7226 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7227 */
7228 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7229 if (fPendingDbgXcpt)
7230 {
7231 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7232 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7233 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7234 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7235 0 /* GCPtrFaultAddress */);
7236 }
7237 }
7238
7239 NOREF(pszInstr);
7240}
7241
7242
7243/**
7244 * Initializes all read-only VMCS fields as part of VM-entry.
7245 *
7246 * @param pVCpu The cross context virtual CPU structure.
7247 */
7248IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7249{
7250 /*
7251 * Any VMCS field which we do not establish on every VM-exit but may potentially
7252 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7253 * specified to be undefined, needs to be initialized here.
7254 *
7255 * Thus, it is especially important to clear the Exit qualification field
7256 * since it must be zero for VM-exits where it is not used. Similarly, the
7257 * VM-exit interruption information field's valid bit needs to be cleared for
7258 * the same reasons.
7259 */
7260 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7261 Assert(pVmcs);
7262
7263 /* 16-bit (none currently). */
7264 /* 32-bit. */
7265 pVmcs->u32RoVmInstrError = 0;
7266 pVmcs->u32RoExitReason = 0;
7267 pVmcs->u32RoExitIntInfo = 0;
7268 pVmcs->u32RoExitIntErrCode = 0;
7269 pVmcs->u32RoIdtVectoringInfo = 0;
7270 pVmcs->u32RoIdtVectoringErrCode = 0;
7271 pVmcs->u32RoExitInstrLen = 0;
7272 pVmcs->u32RoExitInstrInfo = 0;
7273
7274 /* 64-bit. */
7275 pVmcs->u64RoGuestPhysAddr.u = 0;
7276
7277 /* Natural-width. */
7278 pVmcs->u64RoExitQual.u = 0;
7279 pVmcs->u64RoIoRcx.u = 0;
7280 pVmcs->u64RoIoRsi.u = 0;
7281 pVmcs->u64RoIoRdi.u = 0;
7282 pVmcs->u64RoIoRip.u = 0;
7283 pVmcs->u64RoGuestLinearAddr.u = 0;
7284}
7285
7286
7287/**
7288 * VMLAUNCH/VMRESUME instruction execution worker.
7289 *
7290 * @returns Strict VBox status code.
7291 * @param pVCpu The cross context virtual CPU structure.
7292 * @param cbInstr The instruction length in bytes.
7293 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7294 * VMXINSTRID_VMRESUME).
7295 *
7296 * @remarks Common VMX instruction checks are already expected to by the caller,
7297 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7298 */
7299IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7300{
7301# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7302 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7303 return VINF_EM_RAW_EMULATE_INSTR;
7304# else
7305 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7306 || uInstrId == VMXINSTRID_VMRESUME);
7307 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7308
7309 /* Nested-guest intercept. */
7310 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7311 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7312
7313 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7314
7315 /*
7316 * Basic VM-entry checks.
7317 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7318 * The checks following that do not have to follow a specific order.
7319 *
7320 * See Intel spec. 26.1 "Basic VM-entry Checks".
7321 */
7322
7323 /* CPL. */
7324 if (pVCpu->iem.s.uCpl == 0)
7325 { /* likely */ }
7326 else
7327 {
7328 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7329 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7330 return iemRaiseGeneralProtectionFault0(pVCpu);
7331 }
7332
7333 /* Current VMCS valid. */
7334 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7335 { /* likely */ }
7336 else
7337 {
7338 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7339 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7340 iemVmxVmFailInvalid(pVCpu);
7341 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7342 return VINF_SUCCESS;
7343 }
7344
7345 /* Current VMCS is not a shadow VMCS. */
7346 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7347 { /* likely */ }
7348 else
7349 {
7350 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7351 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7352 iemVmxVmFailInvalid(pVCpu);
7353 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7354 return VINF_SUCCESS;
7355 }
7356
7357 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7358 * use block-by-STI here which is not quite correct. */
7359 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7360 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7361 { /* likely */ }
7362 else
7363 {
7364 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7365 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7366 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7367 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7368 return VINF_SUCCESS;
7369 }
7370
7371 if (uInstrId == VMXINSTRID_VMLAUNCH)
7372 {
7373 /* VMLAUNCH with non-clear VMCS. */
7374 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7375 { /* likely */ }
7376 else
7377 {
7378 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7379 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7380 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7381 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7382 return VINF_SUCCESS;
7383 }
7384 }
7385 else
7386 {
7387 /* VMRESUME with non-launched VMCS. */
7388 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7389 { /* likely */ }
7390 else
7391 {
7392 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7393 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7394 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7395 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7396 return VINF_SUCCESS;
7397 }
7398 }
7399
7400 /*
7401 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7402 * while entering VMX non-root mode. We do some of this while checking VM-execution
7403 * controls. The nested hypervisor should not make assumptions and cannot expect
7404 * predictable behavior if changes to these structures are made in guest memory while
7405 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7406 * modify them anyway as we cache them in host memory.
7407 *
7408 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7409 */
7410 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7411 Assert(pVmcs);
7412 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7413
7414 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7415 if (RT_SUCCESS(rc))
7416 {
7417 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7418 if (RT_SUCCESS(rc))
7419 {
7420 /*
7421 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7422 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7423 * ones that may occur during VM-entry below).
7424 */
7425 iemVmxVmentryInitReadOnlyFields(pVCpu);
7426
7427 /*
7428 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7429 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7430 * VM-exit when required.
7431 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7432 */
7433 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7434
7435 bool fPdpesMapped;
7436 rc = iemVmxVmentryCheckGuestState(pVCpu, &fPdpesMapped, pszInstr);
7437 if (RT_SUCCESS(rc))
7438 {
7439 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7440 if (RT_SUCCESS(rc))
7441 {
7442 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7443 if (RT_SUCCESS(rc))
7444 {
7445 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7446
7447 /* VMLAUNCH instruction must update the VMCS launch state. */
7448 if (uInstrId == VMXINSTRID_VMLAUNCH)
7449 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7450
7451 /* Perform the VMX transition (PGM updates). */
7452 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu, fPdpesMapped);
7453 if (rcStrict == VINF_SUCCESS)
7454 { /* likely */ }
7455 else if (RT_SUCCESS(rcStrict))
7456 {
7457 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7458 VBOXSTRICTRC_VAL(rcStrict)));
7459 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7460 }
7461 else
7462 {
7463 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7464 return rcStrict;
7465 }
7466
7467 /* Paranoia. */
7468 Assert(rcStrict == VINF_SUCCESS);
7469
7470 /* We've now entered nested-guest execution. */
7471 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7472
7473 /*
7474 * The priority of potential VM-exits during VM-entry is important.
7475 * The priorities of VM-exits and events are listed from highest
7476 * to lowest as follows:
7477 *
7478 * 1. Event injection.
7479 * 2. Trap on task-switch (T flag set in TSS).
7480 * 3. TPR below threshold / APIC-write.
7481 * 4. SMI, INIT.
7482 * 5. MTF exit.
7483 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7484 * 7. VMX-preemption timer.
7485 * 9. NMI-window exit.
7486 * 10. NMI injection.
7487 * 11. Interrupt-window exit.
7488 * 12. Virtual-interrupt injection.
7489 * 13. Interrupt injection.
7490 * 14. Process next instruction (fetch, decode, execute).
7491 */
7492
7493 /* Setup VMX-preemption timer. */
7494 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7495
7496 /* Setup monitor-trap flag. */
7497 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7498
7499 /* Setup NMI-window exiting. */
7500 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7501
7502 /* Setup interrupt-window exiting. */
7503 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7504
7505 /*
7506 * Inject any event that the nested hypervisor wants to inject.
7507 * Note! We cannot immediately perform the event injection here as we may have
7508 * pending PGM operations to perform due to switching page tables and/or
7509 * mode.
7510 */
7511 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7512
7513# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7514 /* Reschedule to IEM-only execution of the nested-guest. */
7515 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7516 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7517 if (rcSched != VINF_SUCCESS)
7518 iemSetPassUpStatus(pVCpu, rcSched);
7519# endif
7520
7521 /* Finally, done. */
7522 Log3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",
7523 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7524 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7525 pVCpu->cpum.GstCtx.msrEFER));
7526 return VINF_SUCCESS;
7527 }
7528 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7529 pVmcs->u64RoExitQual.u);
7530 }
7531 }
7532 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7533 pVmcs->u64RoExitQual.u);
7534 }
7535
7536 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7537 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7538 return VINF_SUCCESS;
7539 }
7540
7541 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7542 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7543 return VINF_SUCCESS;
7544# endif
7545}
7546
7547
7548/**
7549 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7550 * (causes a VM-exit) or not.
7551 *
7552 * @returns @c true if the instruction is intercepted, @c false otherwise.
7553 * @param pVCpu The cross context virtual CPU structure.
7554 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7555 * VMX_EXIT_WRMSR).
7556 * @param idMsr The MSR.
7557 */
7558IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7559{
7560 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7561 Assert( uExitReason == VMX_EXIT_RDMSR
7562 || uExitReason == VMX_EXIT_WRMSR);
7563
7564 /* Consult the MSR bitmap if the feature is supported. */
7565 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7566 Assert(pVmcs);
7567 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7568 {
7569 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7570 if (uExitReason == VMX_EXIT_RDMSR)
7571 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7572 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7573 }
7574
7575 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7576 return true;
7577}
7578
7579
7580/**
7581 * VMREAD instruction execution worker that does not perform any validation checks.
7582 *
7583 * Callers are expected to have performed the necessary checks and to ensure the
7584 * VMREAD will succeed.
7585 *
7586 * @param pVmcs Pointer to the virtual VMCS.
7587 * @param pu64Dst Where to write the VMCS value.
7588 * @param u64VmcsField The VMCS field.
7589 *
7590 * @remarks May be called with interrupts disabled.
7591 */
7592IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7593{
7594 VMXVMCSFIELD VmcsField;
7595 VmcsField.u = u64VmcsField;
7596 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7597 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7598 uint8_t const uWidthType = (uWidth << 2) | uType;
7599 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7600 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7601 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7602 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
7603 uWidth, uType, uIndex, uIndex));
7604 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7605
7606 /*
7607 * Read the VMCS component based on the field's effective width.
7608 *
7609 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7610 * indicates high bits (little endian).
7611 *
7612 * Note! The caller is responsible to trim the result and update registers
7613 * or memory locations are required. Here we just zero-extend to the largest
7614 * type (i.e. 64-bits).
7615 */
7616 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7617 uint8_t const *pbField = pbVmcs + offField;
7618 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7619 switch (uEffWidth)
7620 {
7621 case VMX_VMCSFIELD_WIDTH_64BIT:
7622 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7623 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7624 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7625 }
7626}
7627
7628
7629/**
7630 * VMREAD common (memory/register) instruction execution worker.
7631 *
7632 * @returns Strict VBox status code.
7633 * @param pVCpu The cross context virtual CPU structure.
7634 * @param cbInstr The instruction length in bytes.
7635 * @param pu64Dst Where to write the VMCS value (only updated when
7636 * VINF_SUCCESS is returned).
7637 * @param u64VmcsField The VMCS field.
7638 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7639 * NULL.
7640 */
7641IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7642 PCVMXVEXITINFO pExitInfo)
7643{
7644 /* Nested-guest intercept. */
7645 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7646 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7647 {
7648 if (pExitInfo)
7649 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7650 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7651 }
7652
7653 /* CPL. */
7654 if (pVCpu->iem.s.uCpl == 0)
7655 { /* likely */ }
7656 else
7657 {
7658 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7659 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7660 return iemRaiseGeneralProtectionFault0(pVCpu);
7661 }
7662
7663 /* VMCS pointer in root mode. */
7664 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7665 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7666 { /* likely */ }
7667 else
7668 {
7669 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7670 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7671 iemVmxVmFailInvalid(pVCpu);
7672 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7673 return VINF_SUCCESS;
7674 }
7675
7676 /* VMCS-link pointer in non-root mode. */
7677 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7678 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7679 { /* likely */ }
7680 else
7681 {
7682 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7683 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7684 iemVmxVmFailInvalid(pVCpu);
7685 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7686 return VINF_SUCCESS;
7687 }
7688
7689 /* Supported VMCS field. */
7690 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7691 { /* likely */ }
7692 else
7693 {
7694 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7695 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7696 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7697 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7698 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7699 return VINF_SUCCESS;
7700 }
7701
7702 /*
7703 * Reading from the current or shadow VMCS.
7704 */
7705 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7706 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7707 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7708 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7709 return VINF_SUCCESS;
7710}
7711
7712
7713/**
7714 * VMREAD (64-bit register) instruction execution worker.
7715 *
7716 * @returns Strict VBox status code.
7717 * @param pVCpu The cross context virtual CPU structure.
7718 * @param cbInstr The instruction length in bytes.
7719 * @param pu64Dst Where to store the VMCS field's value.
7720 * @param u64VmcsField The VMCS field.
7721 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7722 * NULL.
7723 */
7724IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7725 PCVMXVEXITINFO pExitInfo)
7726{
7727 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7728 if (rcStrict == VINF_SUCCESS)
7729 {
7730 iemVmxVmreadSuccess(pVCpu, cbInstr);
7731 return VINF_SUCCESS;
7732 }
7733
7734 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7735 return rcStrict;
7736}
7737
7738
7739/**
7740 * VMREAD (32-bit register) instruction execution worker.
7741 *
7742 * @returns Strict VBox status code.
7743 * @param pVCpu The cross context virtual CPU structure.
7744 * @param cbInstr The instruction length in bytes.
7745 * @param pu32Dst Where to store the VMCS field's value.
7746 * @param u32VmcsField The VMCS field.
7747 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7748 * NULL.
7749 */
7750IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7751 PCVMXVEXITINFO pExitInfo)
7752{
7753 uint64_t u64Dst;
7754 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7755 if (rcStrict == VINF_SUCCESS)
7756 {
7757 *pu32Dst = u64Dst;
7758 iemVmxVmreadSuccess(pVCpu, cbInstr);
7759 return VINF_SUCCESS;
7760 }
7761
7762 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7763 return rcStrict;
7764}
7765
7766
7767/**
7768 * VMREAD (memory) instruction execution worker.
7769 *
7770 * @returns Strict VBox status code.
7771 * @param pVCpu The cross context virtual CPU structure.
7772 * @param cbInstr The instruction length in bytes.
7773 * @param iEffSeg The effective segment register to use with @a u64Val.
7774 * Pass UINT8_MAX if it is a register access.
7775 * @param GCPtrDst The guest linear address to store the VMCS field's
7776 * value.
7777 * @param u64VmcsField The VMCS field.
7778 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7779 * NULL.
7780 */
7781IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7782 PCVMXVEXITINFO pExitInfo)
7783{
7784 uint64_t u64Dst;
7785 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7786 if (rcStrict == VINF_SUCCESS)
7787 {
7788 /*
7789 * Write the VMCS field's value to the location specified in guest-memory.
7790 */
7791 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7792 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7793 else
7794 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7795 if (rcStrict == VINF_SUCCESS)
7796 {
7797 iemVmxVmreadSuccess(pVCpu, cbInstr);
7798 return VINF_SUCCESS;
7799 }
7800
7801 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7802 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7803 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7804 return rcStrict;
7805 }
7806
7807 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7808 return rcStrict;
7809}
7810
7811
7812/**
7813 * VMWRITE instruction execution worker that does not perform any validation
7814 * checks.
7815 *
7816 * Callers are expected to have performed the necessary checks and to ensure the
7817 * VMWRITE will succeed.
7818 *
7819 * @param pVmcs Pointer to the virtual VMCS.
7820 * @param u64Val The value to write.
7821 * @param u64VmcsField The VMCS field.
7822 *
7823 * @remarks May be called with interrupts disabled.
7824 */
7825IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7826{
7827 VMXVMCSFIELD VmcsField;
7828 VmcsField.u = u64VmcsField;
7829 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7830 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7831 uint8_t const uWidthType = (uWidth << 2) | uType;
7832 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7833 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7834 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7835 Assert(offField < VMX_V_VMCS_SIZE);
7836 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7837
7838 /*
7839 * Write the VMCS component based on the field's effective width.
7840 *
7841 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7842 * indicates high bits (little endian).
7843 */
7844 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7845 uint8_t *pbField = pbVmcs + offField;
7846 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7847 switch (uEffWidth)
7848 {
7849 case VMX_VMCSFIELD_WIDTH_64BIT:
7850 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7851 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7852 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7853 }
7854}
7855
7856
7857/**
7858 * VMWRITE instruction execution worker.
7859 *
7860 * @returns Strict VBox status code.
7861 * @param pVCpu The cross context virtual CPU structure.
7862 * @param cbInstr The instruction length in bytes.
7863 * @param iEffSeg The effective segment register to use with @a u64Val.
7864 * Pass UINT8_MAX if it is a register access.
7865 * @param u64Val The value to write (or guest linear address to the
7866 * value), @a iEffSeg will indicate if it's a memory
7867 * operand.
7868 * @param u64VmcsField The VMCS field.
7869 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7870 * NULL.
7871 */
7872IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7873 PCVMXVEXITINFO pExitInfo)
7874{
7875 /* Nested-guest intercept. */
7876 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7877 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7878 {
7879 if (pExitInfo)
7880 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7881 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7882 }
7883
7884 /* CPL. */
7885 if (pVCpu->iem.s.uCpl == 0)
7886 { /* likely */ }
7887 else
7888 {
7889 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7890 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7891 return iemRaiseGeneralProtectionFault0(pVCpu);
7892 }
7893
7894 /* VMCS pointer in root mode. */
7895 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7896 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7897 { /* likely */ }
7898 else
7899 {
7900 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7901 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7902 iemVmxVmFailInvalid(pVCpu);
7903 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7904 return VINF_SUCCESS;
7905 }
7906
7907 /* VMCS-link pointer in non-root mode. */
7908 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7909 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7910 { /* likely */ }
7911 else
7912 {
7913 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7914 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7915 iemVmxVmFailInvalid(pVCpu);
7916 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7917 return VINF_SUCCESS;
7918 }
7919
7920 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7921 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7922 if (!fIsRegOperand)
7923 {
7924 /* Read the value from the specified guest memory location. */
7925 VBOXSTRICTRC rcStrict;
7926 RTGCPTR const GCPtrVal = u64Val;
7927 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7928 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7929 else
7930 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7931 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7932 {
7933 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7934 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7935 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7936 return rcStrict;
7937 }
7938 }
7939 else
7940 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7941
7942 /* Supported VMCS field. */
7943 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7944 { /* likely */ }
7945 else
7946 {
7947 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7948 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7949 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7950 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7951 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7952 return VINF_SUCCESS;
7953 }
7954
7955 /* Read-only VMCS field. */
7956 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7957 if ( !fIsFieldReadOnly
7958 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
7959 { /* likely */ }
7960 else
7961 {
7962 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
7963 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
7964 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7965 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
7966 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7967 return VINF_SUCCESS;
7968 }
7969
7970 /*
7971 * Write to the current or shadow VMCS.
7972 */
7973 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
7974 PVMXVVMCS pVmcs = !fInVmxNonRootMode
7975 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7976 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7977 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
7978
7979 /* Notify HM that the VMCS content might have changed. */
7980 if (!fInVmxNonRootMode)
7981 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
7982
7983 iemVmxVmSucceed(pVCpu);
7984 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7985 return VINF_SUCCESS;
7986}
7987
7988
7989/**
7990 * VMCLEAR instruction execution worker.
7991 *
7992 * @returns Strict VBox status code.
7993 * @param pVCpu The cross context virtual CPU structure.
7994 * @param cbInstr The instruction length in bytes.
7995 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
7996 * @param GCPtrVmcs The linear address of the VMCS pointer.
7997 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
7998 *
7999 * @remarks Common VMX instruction checks are already expected to by the caller,
8000 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8001 */
8002IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8003 PCVMXVEXITINFO pExitInfo)
8004{
8005 /* Nested-guest intercept. */
8006 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8007 {
8008 if (pExitInfo)
8009 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8010 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8011 }
8012
8013 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8014
8015 /* CPL. */
8016 if (pVCpu->iem.s.uCpl == 0)
8017 { /* likely */ }
8018 else
8019 {
8020 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8021 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8022 return iemRaiseGeneralProtectionFault0(pVCpu);
8023 }
8024
8025 /* Get the VMCS pointer from the location specified by the source memory operand. */
8026 RTGCPHYS GCPhysVmcs;
8027 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8028 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8029 { /* likely */ }
8030 else
8031 {
8032 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8033 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8034 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8035 return rcStrict;
8036 }
8037
8038 /* VMCS pointer alignment. */
8039 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8040 { /* likely */ }
8041 else
8042 {
8043 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8044 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8045 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8046 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8047 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8048 return VINF_SUCCESS;
8049 }
8050
8051 /* VMCS physical-address width limits. */
8052 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8053 { /* likely */ }
8054 else
8055 {
8056 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8057 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8058 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8059 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8060 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8061 return VINF_SUCCESS;
8062 }
8063
8064 /* VMCS is not the VMXON region. */
8065 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8066 { /* likely */ }
8067 else
8068 {
8069 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8070 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8071 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8072 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8073 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8074 return VINF_SUCCESS;
8075 }
8076
8077 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8078 restriction imposed by our implementation. */
8079 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8080 { /* likely */ }
8081 else
8082 {
8083 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8084 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8085 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8086 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8087 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8088 return VINF_SUCCESS;
8089 }
8090
8091 /*
8092 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8093 *
8094 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8095 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8096 * to 'clear'.
8097 */
8098 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8099 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8100 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8101 {
8102 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8103 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8104 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8105 }
8106 else
8107 {
8108 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8109 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8110 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8111 if (RT_FAILURE(rcStrict))
8112 return rcStrict;
8113 }
8114
8115 iemVmxVmSucceed(pVCpu);
8116 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8117 return VINF_SUCCESS;
8118}
8119
8120
8121/**
8122 * VMPTRST instruction execution worker.
8123 *
8124 * @returns Strict VBox status code.
8125 * @param pVCpu The cross context virtual CPU structure.
8126 * @param cbInstr The instruction length in bytes.
8127 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8128 * @param GCPtrVmcs The linear address of where to store the current VMCS
8129 * pointer.
8130 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8131 *
8132 * @remarks Common VMX instruction checks are already expected to by the caller,
8133 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8134 */
8135IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8136 PCVMXVEXITINFO pExitInfo)
8137{
8138 /* Nested-guest intercept. */
8139 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8140 {
8141 if (pExitInfo)
8142 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8143 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8144 }
8145
8146 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8147
8148 /* CPL. */
8149 if (pVCpu->iem.s.uCpl == 0)
8150 { /* likely */ }
8151 else
8152 {
8153 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8154 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8155 return iemRaiseGeneralProtectionFault0(pVCpu);
8156 }
8157
8158 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8159 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8160 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8161 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8162 {
8163 iemVmxVmSucceed(pVCpu);
8164 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8165 return rcStrict;
8166 }
8167
8168 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8169 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8170 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8171 return rcStrict;
8172}
8173
8174
8175/**
8176 * VMPTRLD instruction execution worker.
8177 *
8178 * @returns Strict VBox status code.
8179 * @param pVCpu The cross context virtual CPU structure.
8180 * @param cbInstr The instruction length in bytes.
8181 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8182 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8183 *
8184 * @remarks Common VMX instruction checks are already expected to by the caller,
8185 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8186 */
8187IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8188 PCVMXVEXITINFO pExitInfo)
8189{
8190 /* Nested-guest intercept. */
8191 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8192 {
8193 if (pExitInfo)
8194 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8195 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8196 }
8197
8198 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8199
8200 /* CPL. */
8201 if (pVCpu->iem.s.uCpl == 0)
8202 { /* likely */ }
8203 else
8204 {
8205 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8206 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8207 return iemRaiseGeneralProtectionFault0(pVCpu);
8208 }
8209
8210 /* Get the VMCS pointer from the location specified by the source memory operand. */
8211 RTGCPHYS GCPhysVmcs;
8212 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8213 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8214 { /* likely */ }
8215 else
8216 {
8217 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8218 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8219 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8220 return rcStrict;
8221 }
8222
8223 /* VMCS pointer alignment. */
8224 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8225 { /* likely */ }
8226 else
8227 {
8228 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8229 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8230 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8231 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8232 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8233 return VINF_SUCCESS;
8234 }
8235
8236 /* VMCS physical-address width limits. */
8237 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8238 { /* likely */ }
8239 else
8240 {
8241 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8242 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8243 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8244 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8245 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8246 return VINF_SUCCESS;
8247 }
8248
8249 /* VMCS is not the VMXON region. */
8250 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8251 { /* likely */ }
8252 else
8253 {
8254 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8255 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8256 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8257 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8258 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8259 return VINF_SUCCESS;
8260 }
8261
8262 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8263 restriction imposed by our implementation. */
8264 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8265 { /* likely */ }
8266 else
8267 {
8268 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8269 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8270 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8271 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8272 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8273 return VINF_SUCCESS;
8274 }
8275
8276 /* Read just the VMCS revision from the VMCS. */
8277 VMXVMCSREVID VmcsRevId;
8278 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8279 if (RT_SUCCESS(rc))
8280 { /* likely */ }
8281 else
8282 {
8283 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8284 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8285 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8286 return rc;
8287 }
8288
8289 /*
8290 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8291 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8292 */
8293 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8294 && ( !VmcsRevId.n.fIsShadowVmcs
8295 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8296 { /* likely */ }
8297 else
8298 {
8299 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8300 {
8301 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8302 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8303 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8304 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8305 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8306 return VINF_SUCCESS;
8307 }
8308
8309 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8310 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8311 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8312 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8313 return VINF_SUCCESS;
8314 }
8315
8316 /*
8317 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8318 * the cache of an existing, current VMCS back to guest memory before loading a new,
8319 * different current VMCS.
8320 */
8321 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8322 {
8323 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8324 {
8325 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8326 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8327 }
8328
8329 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8330 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8331 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8332 if (RT_SUCCESS(rc))
8333 {
8334 /* Notify HM that a new, current VMCS is loaded. */
8335 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8336 }
8337 else
8338 {
8339 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8340 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8341 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8342 return rc;
8343 }
8344 }
8345
8346 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8347 iemVmxVmSucceed(pVCpu);
8348 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8349 return VINF_SUCCESS;
8350}
8351
8352
8353/**
8354 * INVVPID instruction execution worker.
8355 *
8356 * @returns Strict VBox status code.
8357 * @param pVCpu The cross context virtual CPU structure.
8358 * @param cbInstr The instruction length in bytes.
8359 * @param iEffSeg The segment of the invvpid descriptor.
8360 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8361 * @param u64InvvpidType The invalidation type.
8362 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8363 * NULL.
8364 *
8365 * @remarks Common VMX instruction checks are already expected to by the caller,
8366 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8367 */
8368IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8369 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8370{
8371 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8372 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8373 return iemRaiseUndefinedOpcode(pVCpu);
8374
8375 /* Nested-guest intercept. */
8376 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8377 {
8378 if (pExitInfo)
8379 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8380 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8381 }
8382
8383 /* CPL. */
8384 if (pVCpu->iem.s.uCpl != 0)
8385 {
8386 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8387 return iemRaiseGeneralProtectionFault0(pVCpu);
8388 }
8389
8390 /*
8391 * Validate INVVPID invalidation type.
8392 *
8393 * The instruction specifies exactly ONE of the supported invalidation types.
8394 *
8395 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8396 * supported. In theory, it's possible for a CPU to not support flushing individual
8397 * addresses but all the other types or any other combination. We do not take any
8398 * shortcuts here by assuming the types we currently expose to the guest.
8399 */
8400 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8401 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8402 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8403 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8404 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8405 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8406 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8407 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8408 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8409 { /* likely */ }
8410 else
8411 {
8412 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8413 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8414 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8415 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8416 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8417 return VINF_SUCCESS;
8418 }
8419
8420 /*
8421 * Fetch the invvpid descriptor from guest memory.
8422 */
8423 RTUINT128U uDesc;
8424 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8425 if (rcStrict == VINF_SUCCESS)
8426 {
8427 /*
8428 * Validate the descriptor.
8429 */
8430 if (uDesc.s.Lo > 0xfff)
8431 {
8432 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8433 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8434 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8435 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8436 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8437 return VINF_SUCCESS;
8438 }
8439
8440 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8441 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8442 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8443 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8444 switch (u64InvvpidType)
8445 {
8446 case VMXTLBFLUSHVPID_INDIV_ADDR:
8447 {
8448 if (uVpid != 0)
8449 {
8450 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8451 {
8452 /* Invalidate mappings for the linear address tagged with VPID. */
8453 /** @todo PGM support for VPID? Currently just flush everything. */
8454 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8455 iemVmxVmSucceed(pVCpu);
8456 }
8457 else
8458 {
8459 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8460 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8461 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8462 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8463 }
8464 }
8465 else
8466 {
8467 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8468 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8469 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8470 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8471 }
8472 break;
8473 }
8474
8475 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8476 {
8477 if (uVpid != 0)
8478 {
8479 /* Invalidate all mappings with VPID. */
8480 /** @todo PGM support for VPID? Currently just flush everything. */
8481 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8482 iemVmxVmSucceed(pVCpu);
8483 }
8484 else
8485 {
8486 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8487 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8488 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8489 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8490 }
8491 break;
8492 }
8493
8494 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8495 {
8496 /* Invalidate all mappings with non-zero VPIDs. */
8497 /** @todo PGM support for VPID? Currently just flush everything. */
8498 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8499 iemVmxVmSucceed(pVCpu);
8500 break;
8501 }
8502
8503 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8504 {
8505 if (uVpid != 0)
8506 {
8507 /* Invalidate all mappings with VPID except global translations. */
8508 /** @todo PGM support for VPID? Currently just flush everything. */
8509 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */, false /* fPdpesMapped */);
8510 iemVmxVmSucceed(pVCpu);
8511 }
8512 else
8513 {
8514 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8515 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8516 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8517 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8518 }
8519 break;
8520 }
8521 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8522 }
8523 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8524 }
8525 return rcStrict;
8526}
8527
8528
8529/**
8530 * VMXON instruction execution worker.
8531 *
8532 * @returns Strict VBox status code.
8533 * @param pVCpu The cross context virtual CPU structure.
8534 * @param cbInstr The instruction length in bytes.
8535 * @param iEffSeg The effective segment register to use with @a
8536 * GCPtrVmxon.
8537 * @param GCPtrVmxon The linear address of the VMXON pointer.
8538 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8539 *
8540 * @remarks Common VMX instruction checks are already expected to by the caller,
8541 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8542 */
8543IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8544 PCVMXVEXITINFO pExitInfo)
8545{
8546 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8547 {
8548 /* CPL. */
8549 if (pVCpu->iem.s.uCpl == 0)
8550 { /* likely */ }
8551 else
8552 {
8553 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8554 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8555 return iemRaiseGeneralProtectionFault0(pVCpu);
8556 }
8557
8558 /* A20M (A20 Masked) mode. */
8559 if (PGMPhysIsA20Enabled(pVCpu))
8560 { /* likely */ }
8561 else
8562 {
8563 Log(("vmxon: A20M mode -> #GP(0)\n"));
8564 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8565 return iemRaiseGeneralProtectionFault0(pVCpu);
8566 }
8567
8568 /* CR0. */
8569 {
8570 /* CR0 MB1 bits. */
8571 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8572 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8573 { /* likely */ }
8574 else
8575 {
8576 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8577 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8578 return iemRaiseGeneralProtectionFault0(pVCpu);
8579 }
8580
8581 /* CR0 MBZ bits. */
8582 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8583 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8584 { /* likely */ }
8585 else
8586 {
8587 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8588 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8589 return iemRaiseGeneralProtectionFault0(pVCpu);
8590 }
8591 }
8592
8593 /* CR4. */
8594 {
8595 /* CR4 MB1 bits. */
8596 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8597 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8598 { /* likely */ }
8599 else
8600 {
8601 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8602 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8603 return iemRaiseGeneralProtectionFault0(pVCpu);
8604 }
8605
8606 /* CR4 MBZ bits. */
8607 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8608 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8609 { /* likely */ }
8610 else
8611 {
8612 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8613 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8614 return iemRaiseGeneralProtectionFault0(pVCpu);
8615 }
8616 }
8617
8618 /* Feature control MSR's LOCK and VMXON bits. */
8619 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
8620 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8621 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8622 { /* likely */ }
8623 else
8624 {
8625 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8626 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8627 return iemRaiseGeneralProtectionFault0(pVCpu);
8628 }
8629
8630 /* Get the VMXON pointer from the location specified by the source memory operand. */
8631 RTGCPHYS GCPhysVmxon;
8632 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8633 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8634 { /* likely */ }
8635 else
8636 {
8637 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8638 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8639 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8640 return rcStrict;
8641 }
8642
8643 /* VMXON region pointer alignment. */
8644 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8645 { /* likely */ }
8646 else
8647 {
8648 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8649 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8650 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8651 iemVmxVmFailInvalid(pVCpu);
8652 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8653 return VINF_SUCCESS;
8654 }
8655
8656 /* VMXON physical-address width limits. */
8657 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8658 { /* likely */ }
8659 else
8660 {
8661 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8662 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8663 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8664 iemVmxVmFailInvalid(pVCpu);
8665 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8666 return VINF_SUCCESS;
8667 }
8668
8669 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8670 restriction imposed by our implementation. */
8671 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8672 { /* likely */ }
8673 else
8674 {
8675 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8676 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8677 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8678 iemVmxVmFailInvalid(pVCpu);
8679 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8680 return VINF_SUCCESS;
8681 }
8682
8683 /* Read the VMCS revision ID from the VMXON region. */
8684 VMXVMCSREVID VmcsRevId;
8685 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8686 if (RT_SUCCESS(rc))
8687 { /* likely */ }
8688 else
8689 {
8690 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8691 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8692 return rc;
8693 }
8694
8695 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8696 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8697 { /* likely */ }
8698 else
8699 {
8700 /* Revision ID mismatch. */
8701 if (!VmcsRevId.n.fIsShadowVmcs)
8702 {
8703 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8704 VmcsRevId.n.u31RevisionId));
8705 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8706 iemVmxVmFailInvalid(pVCpu);
8707 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8708 return VINF_SUCCESS;
8709 }
8710
8711 /* Shadow VMCS disallowed. */
8712 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8713 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8714 iemVmxVmFailInvalid(pVCpu);
8715 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8716 return VINF_SUCCESS;
8717 }
8718
8719 /*
8720 * Record that we're in VMX operation, block INIT, block and disable A20M.
8721 */
8722 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8723 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8724 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8725
8726 /* Clear address-range monitoring. */
8727 EMMonitorWaitClear(pVCpu);
8728 /** @todo NSTVMX: Intel PT. */
8729
8730 iemVmxVmSucceed(pVCpu);
8731 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8732 return VINF_SUCCESS;
8733 }
8734 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8735 {
8736 /* Nested-guest intercept. */
8737 if (pExitInfo)
8738 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8739 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8740 }
8741
8742 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8743
8744 /* CPL. */
8745 if (pVCpu->iem.s.uCpl > 0)
8746 {
8747 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8748 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8749 return iemRaiseGeneralProtectionFault0(pVCpu);
8750 }
8751
8752 /* VMXON when already in VMX root mode. */
8753 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8754 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8755 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8756 return VINF_SUCCESS;
8757}
8758
8759
8760/**
8761 * Implements 'VMXOFF'.
8762 *
8763 * @remarks Common VMX instruction checks are already expected to by the caller,
8764 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8765 */
8766IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8767{
8768 /* Nested-guest intercept. */
8769 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8770 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8771
8772 /* CPL. */
8773 if (pVCpu->iem.s.uCpl == 0)
8774 { /* likely */ }
8775 else
8776 {
8777 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8778 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8779 return iemRaiseGeneralProtectionFault0(pVCpu);
8780 }
8781
8782 /* Dual monitor treatment of SMIs and SMM. */
8783 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8784 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8785 { /* likely */ }
8786 else
8787 {
8788 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8789 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8790 return VINF_SUCCESS;
8791 }
8792
8793 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8794 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8795 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8796
8797 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8798 { /** @todo NSTVMX: Unblock SMI. */ }
8799
8800 EMMonitorWaitClear(pVCpu);
8801 /** @todo NSTVMX: Unblock and enable A20M. */
8802
8803 iemVmxVmSucceed(pVCpu);
8804 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8805 return VINF_SUCCESS;
8806}
8807
8808
8809/**
8810 * Implements 'VMXON'.
8811 */
8812IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8813{
8814 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8815}
8816
8817
8818/**
8819 * Implements 'VMLAUNCH'.
8820 */
8821IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8822{
8823 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8824}
8825
8826
8827/**
8828 * Implements 'VMRESUME'.
8829 */
8830IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8831{
8832 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8833}
8834
8835
8836/**
8837 * Implements 'VMPTRLD'.
8838 */
8839IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8840{
8841 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8842}
8843
8844
8845/**
8846 * Implements 'VMPTRST'.
8847 */
8848IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8849{
8850 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8851}
8852
8853
8854/**
8855 * Implements 'VMCLEAR'.
8856 */
8857IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8858{
8859 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8860}
8861
8862
8863/**
8864 * Implements 'VMWRITE' register.
8865 */
8866IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8867{
8868 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8869}
8870
8871
8872/**
8873 * Implements 'VMWRITE' memory.
8874 */
8875IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8876{
8877 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8878}
8879
8880
8881/**
8882 * Implements 'VMREAD' register (64-bit).
8883 */
8884IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8885{
8886 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8887}
8888
8889
8890/**
8891 * Implements 'VMREAD' register (32-bit).
8892 */
8893IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8894{
8895 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8896}
8897
8898
8899/**
8900 * Implements 'VMREAD' memory, 64-bit register.
8901 */
8902IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8903{
8904 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8905}
8906
8907
8908/**
8909 * Implements 'VMREAD' memory, 32-bit register.
8910 */
8911IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8912{
8913 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8914}
8915
8916
8917/**
8918 * Implements 'INVVPID'.
8919 */
8920IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8921{
8922 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8923}
8924
8925
8926/**
8927 * Implements VMX's implementation of PAUSE.
8928 */
8929IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8930{
8931 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8932 {
8933 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8934 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8935 return rcStrict;
8936 }
8937
8938 /*
8939 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8940 * a VM-exit, the instruction operates normally.
8941 */
8942 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8943 return VINF_SUCCESS;
8944}
8945
8946#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8947
8948
8949/**
8950 * Implements 'VMCALL'.
8951 */
8952IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8953{
8954#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8955 /* Nested-guest intercept. */
8956 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8957 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8958#endif
8959
8960 /* Join forces with vmmcall. */
8961 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8962}
8963
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