IEMAllCImplVmxInstr.cpp.h@ 92566

Last change on this file since 92566 was 92566, checked in by vboxsync, 3 years ago
VMM/IEM: Nested VMX: bugref:10092 We need to declare we have entered/exited VMX non-root mode prior to loading guest state since PGM (and others in future) might need this information while loading guest state.
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1	/* $Id: IEMAllCImplVmxInstr.cpp.h 92566 2021-11-23 15:29:41Z vboxsync $ */
2	/** @file
3	* IEM - VT-x instruction implementation.
4	*/
5
6	/*
7	* Copyright (C) 2011-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Defined Constants And Macros *
21	*********************************************************************************************************************************/
22	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23	/**
24	* Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25	* relative offsets.
26	*/
27	# ifdef IEM_WITH_CODE_TLB
28	# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29	# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30	# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31	# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32	# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33	# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34	# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35	# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36	# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37	# else /* !IEM_WITH_CODE_TLB */
38	# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39	do \
40	{ \
41	Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42	(a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43	} while (0)
44
45	# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47	# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48	do \
49	{ \
50	Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51	uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52	uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53	(a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54	} while (0)
55
56	# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57	do \
58	{ \
59	Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60	(a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61	} while (0)
62
63	# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64	do \
65	{ \
66	Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67	uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68	uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69	uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70	uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71	(a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72	} while (0)
73
74	# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75	do \
76	{ \
77	Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78	(a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79	} while (0)
80
81	# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82	do \
83	{ \
84	Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85	(a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86	} while (0)
87
88	# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89	do \
90	{ \
91	Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92	uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93	uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94	uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95	uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96	(a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97	} while (0)
98	# endif /* !IEM_WITH_CODE_TLB */
99
100	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103	/** Whether a shadow VMCS is present for the given VCPU. */
104	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106	/** Gets the VMXON region pointer. */
107	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112	/** Whether a current VMCS is present for the given VCPU. */
113	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117	do \
118	{ \
119	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121	} while (0)
122
123	/** Clears any current VMCS for the given VCPU. */
124	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125	do \
126	{ \
127	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128	} while (0)
129
130	/** Check for VMX instructions requiring to be in VMX operation.
131	* @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132	# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133	do \
134	{ \
135	if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136	{ /* likely */ } \
137	else \
138	{ \
139	Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141	return iemRaiseUndefinedOpcode(a_pVCpu); \
142	} \
143	} while (0)
144
145	/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146	# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147	do \
148	{ \
149	LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150	HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152	return VERR_VMX_VMENTRY_FAILED; \
153	} while (0)
154
155	/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156	# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157	do \
158	{ \
159	LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160	HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162	return VERR_VMX_VMEXIT_FAILED; \
163	} while (0)
164
165
166	/*********************************************************************************************************************************
167	* Global Variables *
168	*********************************************************************************************************************************/
169	/** @todo NSTVMX: The following VM-exit intercepts are pending:
170	* VMX_EXIT_IO_SMI
171	* VMX_EXIT_SMI
172	* VMX_EXIT_GETSEC
173	* VMX_EXIT_RSM
174	* VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
175	* VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
176	* VMX_EXIT_EPT_VIOLATION
177	* VMX_EXIT_EPT_MISCONFIG
178	* VMX_EXIT_INVEPT
179	* VMX_EXIT_RDRAND
180	* VMX_EXIT_VMFUNC
181	* VMX_EXIT_ENCLS
182	* VMX_EXIT_RDSEED
183	* VMX_EXIT_PML_FULL
184	* VMX_EXIT_XSAVES
185	* VMX_EXIT_XRSTORS
186	*/
187	/**
188	* Map of VMCS field encodings to their virtual-VMCS structure offsets.
189	*
190	* The first array dimension is VMCS field encoding of Width OR'ed with Type and the
191	* second dimension is the Index, see VMXVMCSFIELD.
192	*/
193	uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
194	{
195	/* VMX_VMCSFIELD_WIDTH_16BIT \| VMX_VMCSFIELD_TYPE_CONTROL: */
196	{
197	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
198	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
199	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
200	/* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
201	/* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
202	/* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
203	/* 27 */ UINT16_MAX,
204	},
205	/* VMX_VMCSFIELD_WIDTH_16BIT \| VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
206	{
207	/* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208	/* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209	/* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210	/* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
211	},
212	/* VMX_VMCSFIELD_WIDTH_16BIT \| VMX_VMCSFIELD_TYPE_GUEST_STATE: */
213	{
214	/* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
215	/* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
216	/* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
217	/* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
218	/* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
219	/* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
220	/* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
221	/* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
222	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
223	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
224	/* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225	/* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226	/* 26-27 */ UINT16_MAX, UINT16_MAX
227	},
228	/* VMX_VMCSFIELD_WIDTH_16BIT \| VMX_VMCSFIELD_TYPE_HOST_STATE: */
229	{
230	/* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
231	/* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
232	/* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
233	/* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
234	/* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
235	/* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
236	/* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
237	/* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238	/* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
239	/* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
240	},
241	/* VMX_VMCSFIELD_WIDTH_64BIT \| VMX_VMCSFIELD_TYPE_CONTROL: */
242	{
243	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
244	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
245	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
246	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
247	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
248	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
249	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
250	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
251	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
252	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
253	/* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
254	/* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
255	/* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
256	/* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
257	/* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
258	/* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
259	/* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
260	/* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
261	/* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
262	/* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
263	/* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
264	/* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
265	/* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
266	/* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
267	/* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
268	/* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
269	/* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
270	/* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
271	},
272	/* VMX_VMCSFIELD_WIDTH_64BIT \| VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
273	{
274	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
275	/* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
276	/* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
277	/* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
278	/* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
279	},
280	/* VMX_VMCSFIELD_WIDTH_64BIT \| VMX_VMCSFIELD_TYPE_GUEST_STATE: */
281	{
282	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
283	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
284	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
285	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
286	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
287	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
288	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
289	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
290	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
291	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
292	/* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
293	/* 11 */ UINT16_MAX,
294	/* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
295	/* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
296	/* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
297	},
298	/* VMX_VMCSFIELD_WIDTH_64BIT \| VMX_VMCSFIELD_TYPE_HOST_STATE: */
299	{
300	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
301	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
302	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
303	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
304	/* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305	/* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306	/* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
307	},
308	/* VMX_VMCSFIELD_WIDTH_32BIT \| VMX_VMCSFIELD_TYPE_CONTROL: */
309	{
310	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
311	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
312	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
313	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
314	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
315	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
316	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
317	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
318	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
319	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
320	/* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
321	/* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
322	/* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
323	/* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
324	/* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
325	/* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
326	/* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
327	/* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
328	/* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
329	/* 26-27 */ UINT16_MAX, UINT16_MAX
330	},
331	/* VMX_VMCSFIELD_WIDTH_32BIT \| VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
332	{
333	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
334	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
335	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
336	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
337	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
338	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
339	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
340	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
341	/* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
342	/* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
343	/* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
344	},
345	/* VMX_VMCSFIELD_WIDTH_32BIT \| VMX_VMCSFIELD_TYPE_GUEST_STATE: */
346	{
347	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
348	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
349	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
350	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
351	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
352	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
353	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
354	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
355	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
356	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
357	/* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
358	/* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
359	/* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
360	/* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
361	/* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
362	/* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
363	/* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
364	/* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
365	/* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
366	/* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
367	/* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
368	/* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
369	/* 22 */ UINT16_MAX,
370	/* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
371	/* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
372	},
373	/* VMX_VMCSFIELD_WIDTH_32BIT \| VMX_VMCSFIELD_TYPE_HOST_STATE: */
374	{
375	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
376	/* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
377	/* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
378	/* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
379	/* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
380	},
381	/* VMX_VMCSFIELD_WIDTH_NATURAL \| VMX_VMCSFIELD_TYPE_CONTROL: */
382	{
383	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
384	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
385	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
386	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
387	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
388	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
389	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
390	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
391	/* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
392	/* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
393	/* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
394	},
395	/* VMX_VMCSFIELD_WIDTH_NATURAL \| VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
396	{
397	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
398	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
399	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
400	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
401	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
402	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
403	/* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
404	/* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
405	/* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
406	},
407	/* VMX_VMCSFIELD_WIDTH_NATURAL \| VMX_VMCSFIELD_TYPE_GUEST_STATE: */
408	{
409	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
410	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
411	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
412	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
413	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
414	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
415	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
416	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
417	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
418	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
419	/* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
420	/* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
421	/* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
422	/* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
423	/* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
424	/* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
425	/* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
426	/* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
427	/* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
428	/* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
429	/* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
430	/* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
431	/* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
432	/* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
433	},
434	/* VMX_VMCSFIELD_WIDTH_NATURAL \| VMX_VMCSFIELD_TYPE_HOST_STATE: */
435	{
436	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
437	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
438	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
439	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
440	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
441	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
442	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
443	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
444	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
445	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
446	/* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
447	/* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
448	/* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
449	/* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
450	/* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
451	/* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
452	/* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
453	}
454	};
455
456
457	/**
458	* Gets a host selector from the VMCS.
459	*
460	* @param pVmcs Pointer to the virtual VMCS.
461	* @param iSelReg The index of the segment register (X86_SREG_XXX).
462	*/
463	DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
464	{
465	Assert(iSegReg < X86_SREG_COUNT);
466	RTSEL HostSel;
467	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
468	uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
469	uint8_t const uWidthType = (uWidth << 2) \| uType;
470	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
471	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
472	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
473	uint8_t const pbVmcs = (uint8_t )pVmcs;
474	uint8_t const *pbField = pbVmcs + offField;
475	HostSel = (uint16_t )pbField;
476	return HostSel;
477	}
478
479
480	/**
481	* Sets a guest segment register in the VMCS.
482	*
483	* @param pVmcs Pointer to the virtual VMCS.
484	* @param iSegReg The index of the segment register (X86_SREG_XXX).
485	* @param pSelReg Pointer to the segment register.
486	*/
487	IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
488	{
489	Assert(pSelReg);
490	Assert(iSegReg < X86_SREG_COUNT);
491
492	/* Selector. */
493	{
494	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
495	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
496	uint8_t const uWidthType = (uWidth << 2) \| uType;
497	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
498	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
499	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
500	uint8_t pbVmcs = (uint8_t )pVmcs;
501	uint8_t *pbField = pbVmcs + offField;
502	(uint16_t )pbField = pSelReg->Sel;
503	}
504
505	/* Limit. */
506	{
507	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
508	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
509	uint8_t const uWidthType = (uWidth << 2) \| uType;
510	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
511	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
512	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
513	uint8_t pbVmcs = (uint8_t )pVmcs;
514	uint8_t *pbField = pbVmcs + offField;
515	(uint32_t )pbField = pSelReg->u32Limit;
516	}
517
518	/* Base. */
519	{
520	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
521	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
522	uint8_t const uWidthType = (uWidth << 2) \| uType;
523	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
524	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
525	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
526	uint8_t const pbVmcs = (uint8_t )pVmcs;
527	uint8_t const *pbField = pbVmcs + offField;
528	(uint64_t )pbField = pSelReg->u64Base;
529	}
530
531	/* Attributes. */
532	{
533	uint32_t const fValidAttrMask = X86DESCATTR_TYPE \| X86DESCATTR_DT \| X86DESCATTR_DPL \| X86DESCATTR_P
534	\| X86DESCATTR_AVL \| X86DESCATTR_L \| X86DESCATTR_D \| X86DESCATTR_G
535	\| X86DESCATTR_UNUSABLE;
536	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
537	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
538	uint8_t const uWidthType = (uWidth << 2) \| uType;
539	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
540	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
541	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
542	uint8_t pbVmcs = (uint8_t )pVmcs;
543	uint8_t *pbField = pbVmcs + offField;
544	(uint32_t )pbField = pSelReg->Attr.u & fValidAttrMask;
545	}
546	}
547
548
549	/**
550	* Gets a guest segment register from the VMCS.
551	*
552	* @returns VBox status code.
553	* @param pVmcs Pointer to the virtual VMCS.
554	* @param iSegReg The index of the segment register (X86_SREG_XXX).
555	* @param pSelReg Where to store the segment register (only updated when
556	* VINF_SUCCESS is returned).
557	*
558	* @remarks Warning! This does not validate the contents of the retrieved segment
559	* register.
560	*/
561	IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
562	{
563	Assert(pSelReg);
564	Assert(iSegReg < X86_SREG_COUNT);
565
566	/* Selector. */
567	uint16_t u16Sel;
568	{
569	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
570	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
571	uint8_t const uWidthType = (uWidth << 2) \| uType;
572	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
573	AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
574	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
575	uint8_t const pbVmcs = (uint8_t )pVmcs;
576	uint8_t const *pbField = pbVmcs + offField;
577	u16Sel = (uint16_t )pbField;
578	}
579
580	/* Limit. */
581	uint32_t u32Limit;
582	{
583	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
584	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
585	uint8_t const uWidthType = (uWidth << 2) \| uType;
586	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
587	AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
588	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
589	uint8_t const pbVmcs = (uint8_t )pVmcs;
590	uint8_t const *pbField = pbVmcs + offField;
591	u32Limit = (uint32_t )pbField;
592	}
593
594	/* Base. */
595	uint64_t u64Base;
596	{
597	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
598	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
599	uint8_t const uWidthType = (uWidth << 2) \| uType;
600	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
601	AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
602	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
603	uint8_t const pbVmcs = (uint8_t )pVmcs;
604	uint8_t const *pbField = pbVmcs + offField;
605	u64Base = (uint64_t )pbField;
606	/** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
607	}
608
609	/* Attributes. */
610	uint32_t u32Attr;
611	{
612	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
613	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
614	uint8_t const uWidthType = (uWidth << 2) \| uType;
615	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
616	AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
617	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
618	uint8_t const pbVmcs = (uint8_t )pVmcs;
619	uint8_t const *pbField = pbVmcs + offField;
620	u32Attr = (uint32_t )pbField;
621	}
622
623	pSelReg->Sel = u16Sel;
624	pSelReg->ValidSel = u16Sel;
625	pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
626	pSelReg->u32Limit = u32Limit;
627	pSelReg->u64Base = u64Base;
628	pSelReg->Attr.u = u32Attr;
629	return VINF_SUCCESS;
630	}
631
632
633	/**
634	* Converts an IEM exception event type to a VMX event type.
635	*
636	* @returns The VMX event type.
637	* @param uVector The interrupt / exception vector.
638	* @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
639	*/
640	DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
641	{
642	/* Paranoia (callers may use these interchangeably). */
643	AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
644	AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
645	AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
646	AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
647	AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
648	AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
649	AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
650	AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
651	AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
652	AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
653	AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
654	AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
655
656	if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
657	{
658	if (uVector == X86_XCPT_NMI)
659	return VMX_EXIT_INT_INFO_TYPE_NMI;
660	return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
661	}
662
663	if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
664	{
665	if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR \| IEM_XCPT_FLAGS_OF_INSTR))
666	return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
667	if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
668	return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
669	return VMX_EXIT_INT_INFO_TYPE_SW_INT;
670	}
671
672	Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
673	return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
674	}
675
676
677	/**
678	* Determines whether the guest is using PAE paging given the VMCS.
679	*
680	* @returns @c true if PAE paging mode is used, @c false otherwise.
681	* @param pVmcs Pointer to the virtual VMCS.
682	*/
683	DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
684	{
685	return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
686	&& (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
687	&& (pVmcs->u64GuestCr0.u & X86_CR0_PG));
688	}
689
690
691	/**
692	* Sets the Exit qualification VMCS field.
693	*
694	* @param pVCpu The cross context virtual CPU structure.
695	* @param u64ExitQual The Exit qualification.
696	*/
697	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
698	{
699	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
700	}
701
702
703	/**
704	* Sets the VM-exit interruption information field.
705	*
706	* @param pVCpu The cross context virtual CPU structure.
707	* @param uExitIntInfo The VM-exit interruption information.
708	*/
709	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
710	{
711	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
712	}
713
714
715	/**
716	* Sets the VM-exit interruption error code.
717	*
718	* @param pVCpu The cross context virtual CPU structure.
719	* @param uErrCode The error code.
720	*/
721	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
722	{
723	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
724	}
725
726
727	/**
728	* Sets the IDT-vectoring information field.
729	*
730	* @param pVCpu The cross context virtual CPU structure.
731	* @param uIdtVectorInfo The IDT-vectoring information.
732	*/
733	DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
734	{
735	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
736	}
737
738
739	/**
740	* Sets the IDT-vectoring error code field.
741	*
742	* @param pVCpu The cross context virtual CPU structure.
743	* @param uErrCode The error code.
744	*/
745	DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
746	{
747	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
748	}
749
750
751	/**
752	* Sets the VM-exit guest-linear address VMCS field.
753	*
754	* @param pVCpu The cross context virtual CPU structure.
755	* @param uGuestLinearAddr The VM-exit guest-linear address.
756	*/
757	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
758	{
759	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
760	}
761
762
763	/**
764	* Sets the VM-exit guest-physical address VMCS field.
765	*
766	* @param pVCpu The cross context virtual CPU structure.
767	* @param uGuestPhysAddr The VM-exit guest-physical address.
768	*/
769	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
770	{
771	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
772	}
773
774
775	/**
776	* Sets the VM-exit instruction length VMCS field.
777	*
778	* @param pVCpu The cross context virtual CPU structure.
779	* @param cbInstr The VM-exit instruction length in bytes.
780	*
781	* @remarks Callers may clear this field to 0. Hence, this function does not check
782	* the validity of the instruction length.
783	*/
784	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
785	{
786	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
787	}
788
789
790	/**
791	* Sets the VM-exit instruction info. VMCS field.
792	*
793	* @param pVCpu The cross context virtual CPU structure.
794	* @param uExitInstrInfo The VM-exit instruction information.
795	*/
796	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
797	{
798	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
799	}
800
801
802	/**
803	* Sets the guest pending-debug exceptions field.
804	*
805	* @param pVCpu The cross context virtual CPU structure.
806	* @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
807	*/
808	DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
809	{
810	Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
811	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
812	}
813
814
815	/**
816	* Implements VMSucceed for VMX instruction success.
817	*
818	* @param pVCpu The cross context virtual CPU structure.
819	*/
820	DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
821	{
822	return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
823	}
824
825
826	/**
827	* Implements VMFailInvalid for VMX instruction failure.
828	*
829	* @param pVCpu The cross context virtual CPU structure.
830	*/
831	DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
832	{
833	return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
834	}
835
836
837	/**
838	* Implements VMFail for VMX instruction failure.
839	*
840	* @param pVCpu The cross context virtual CPU structure.
841	* @param enmInsErr The VM instruction error.
842	*/
843	DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
844	{
845	return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
846	}
847
848
849	/**
850	* Checks if the given auto-load/store MSR area count is valid for the
851	* implementation.
852	*
853	* @returns @c true if it's within the valid limit, @c false otherwise.
854	* @param pVCpu The cross context virtual CPU structure.
855	* @param uMsrCount The MSR area count to check.
856	*/
857	DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
858	{
859	uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
860	uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
861	Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
862	if (uMsrCount <= cMaxSupportedMsrs)
863	return true;
864	return false;
865	}
866
867
868	/**
869	* Flushes the current VMCS contents back to guest memory.
870	*
871	* @returns VBox status code.
872	* @param pVCpu The cross context virtual CPU structure.
873	*/
874	DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
875	{
876	Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
877	int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
878	&pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
879	return rc;
880	}
881
882
883	/**
884	* Populates the current VMCS contents from guest memory.
885	*
886	* @returns VBox status code.
887	* @param pVCpu The cross context virtual CPU structure.
888	*/
889	DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
890	{
891	Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
892	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
893	IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
894	return rc;
895	}
896
897
898	/**
899	* Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
900	*
901	* @param pVCpu The cross context virtual CPU structure.
902	*/
903	DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
904	{
905	iemVmxVmSucceed(pVCpu);
906	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
907	}
908
909
910	/**
911	* Gets the instruction diagnostic for segment base checks during VM-entry of a
912	* nested-guest.
913	*
914	* @param iSegReg The segment index (X86_SREG_XXX).
915	*/
916	IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
917	{
918	switch (iSegReg)
919	{
920	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
921	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
922	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
923	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
924	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
925	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
926	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
927	}
928	}
929
930
931	/**
932	* Gets the instruction diagnostic for segment base checks during VM-entry of a
933	* nested-guest that is in Virtual-8086 mode.
934	*
935	* @param iSegReg The segment index (X86_SREG_XXX).
936	*/
937	IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
938	{
939	switch (iSegReg)
940	{
941	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
942	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
943	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
944	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
945	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
946	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
947	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
948	}
949	}
950
951
952	/**
953	* Gets the instruction diagnostic for segment limit checks during VM-entry of a
954	* nested-guest that is in Virtual-8086 mode.
955	*
956	* @param iSegReg The segment index (X86_SREG_XXX).
957	*/
958	IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
959	{
960	switch (iSegReg)
961	{
962	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
963	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
964	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
965	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
966	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
967	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
968	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
969	}
970	}
971
972
973	/**
974	* Gets the instruction diagnostic for segment attribute checks during VM-entry of a
975	* nested-guest that is in Virtual-8086 mode.
976	*
977	* @param iSegReg The segment index (X86_SREG_XXX).
978	*/
979	IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
980	{
981	switch (iSegReg)
982	{
983	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
984	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
985	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
986	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
987	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
988	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
989	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
990	}
991	}
992
993
994	/**
995	* Gets the instruction diagnostic for segment attributes reserved bits failure
996	* during VM-entry of a nested-guest.
997	*
998	* @param iSegReg The segment index (X86_SREG_XXX).
999	*/
1000	IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1001	{
1002	switch (iSegReg)
1003	{
1004	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1005	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1006	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1007	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1008	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1009	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1010	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1011	}
1012	}
1013
1014
1015	/**
1016	* Gets the instruction diagnostic for segment attributes descriptor-type
1017	* (code/segment or system) failure during VM-entry of a nested-guest.
1018	*
1019	* @param iSegReg The segment index (X86_SREG_XXX).
1020	*/
1021	IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1022	{
1023	switch (iSegReg)
1024	{
1025	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1026	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1027	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1028	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1029	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1030	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1031	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1032	}
1033	}
1034
1035
1036	/**
1037	* Gets the instruction diagnostic for segment attributes descriptor-type
1038	* (code/segment or system) failure during VM-entry of a nested-guest.
1039	*
1040	* @param iSegReg The segment index (X86_SREG_XXX).
1041	*/
1042	IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1043	{
1044	switch (iSegReg)
1045	{
1046	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1047	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1048	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1049	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1050	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1051	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1052	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1053	}
1054	}
1055
1056
1057	/**
1058	* Gets the instruction diagnostic for segment attribute granularity failure during
1059	* VM-entry of a nested-guest.
1060	*
1061	* @param iSegReg The segment index (X86_SREG_XXX).
1062	*/
1063	IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1064	{
1065	switch (iSegReg)
1066	{
1067	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1068	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1069	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1070	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1071	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1072	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1073	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1074	}
1075	}
1076
1077	/**
1078	* Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1079	* VM-entry of a nested-guest.
1080	*
1081	* @param iSegReg The segment index (X86_SREG_XXX).
1082	*/
1083	IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1084	{
1085	switch (iSegReg)
1086	{
1087	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1088	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1089	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1090	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1091	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1092	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1093	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1094	}
1095	}
1096
1097
1098	/**
1099	* Gets the instruction diagnostic for segment attribute type accessed failure
1100	* during VM-entry of a nested-guest.
1101	*
1102	* @param iSegReg The segment index (X86_SREG_XXX).
1103	*/
1104	IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1105	{
1106	switch (iSegReg)
1107	{
1108	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1109	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1110	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1111	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1112	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1113	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1114	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1115	}
1116	}
1117
1118
1119	/**
1120	* Saves the guest control registers, debug registers and some MSRs are part of
1121	* VM-exit.
1122	*
1123	* @param pVCpu The cross context virtual CPU structure.
1124	*/
1125	IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1126	{
1127	/*
1128	* Saves the guest control registers, debug registers and some MSRs.
1129	* See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1130	*/
1131	PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1132
1133	/* Save control registers. */
1134	pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1135	pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1136	pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1137
1138	/* Save SYSENTER CS, ESP, EIP. */
1139	pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1140	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1141	{
1142	pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1143	pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1144	}
1145	else
1146	{
1147	pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1148	pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1149	}
1150
1151	/* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1152	if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1153	{
1154	pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1155	/** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1156	}
1157
1158	/* Save PAT MSR. */
1159	if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1160	pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1161
1162	/* Save EFER MSR. */
1163	if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1164	pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1165
1166	/* We don't support clearing IA32_BNDCFGS MSR yet. */
1167	Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1168
1169	/* Nothing to do for SMBASE register - We don't support SMM yet. */
1170	}
1171
1172
1173	/**
1174	* Saves the guest force-flags in preparation of entering the nested-guest.
1175	*
1176	* @param pVCpu The cross context virtual CPU structure.
1177	*/
1178	IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1179	{
1180	/* We shouldn't be called multiple times during VM-entry. */
1181	Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1182
1183	/* MTF should not be set outside VMX non-root mode. */
1184	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1185
1186	/*
1187	* Preserve the required force-flags.
1188	*
1189	* We cache and clear force-flags that would affect the execution of the
1190	* nested-guest. Cached flags are then restored while returning to the guest
1191	* if necessary.
1192	*
1193	* - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1194	* interrupts until the completion of the current VMLAUNCH/VMRESUME
1195	* instruction. Interrupt inhibition for any nested-guest instruction
1196	* is supplied by the guest-interruptibility state VMCS field and will
1197	* be set up as part of loading the guest state.
1198	*
1199	* - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1200	* successful VM-entry (due to invalid guest-state) need to continue
1201	* blocking NMIs if it was in effect before VM-entry.
1202	*
1203	* - MTF need not be preserved as it's used only in VMX non-root mode and
1204	* is supplied through the VM-execution controls.
1205	*
1206	* The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1207	* we will be able to generate interrupts that may cause VM-exits for
1208	* the nested-guest.
1209	*/
1210	pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1211	}
1212
1213
1214	/**
1215	* Restores the guest force-flags in preparation of exiting the nested-guest.
1216	*
1217	* @param pVCpu The cross context virtual CPU structure.
1218	*/
1219	IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1220	{
1221	if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1222	{
1223	VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1224	pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1225	}
1226	}
1227
1228
1229	/**
1230	* Performs the VMX transition to/from VMX non-root mode.
1231	*
1232	* @param pVCpu The cross context virtual CPU structure.
1233	* @param fPdpesMapped Whether the PAE PDPTEs (and PDPT) have been mapped.
1234	*/
1235	IEM_STATIC int iemVmxTransition(PVMCPUCC pVCpu, bool fPdpesMapped)
1236	{
1237	/*
1238	* Inform PGM about paging mode changes.
1239	* We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1240	* see comment in iemMemPageTranslateAndCheckAccess().
1241	*/
1242	int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 \| X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1243	true /* fForce */);
1244	AssertRCReturn(rc, rc);
1245
1246	/* Inform CPUM (recompiler), can later be removed. */
1247	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1248
1249	/*
1250	* Flush the TLB with new CR3. This is required in case the PGM mode change
1251	* above doesn't actually change anything.
1252	*/
1253	if (rc == VINF_SUCCESS)
1254	{
1255	rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* fGlobal */, fPdpesMapped);
1256	AssertRCReturn(rc, rc);
1257	}
1258
1259	/* Re-initialize IEM cache/state after the drastic mode switch. */
1260	iemReInitExec(pVCpu);
1261	return rc;
1262	}
1263
1264
1265	/**
1266	* Calculates the current VMX-preemption timer value.
1267	*
1268	* @returns The current VMX-preemption timer value.
1269	* @param pVCpu The cross context virtual CPU structure.
1270	*/
1271	IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1272	{
1273	/*
1274	* Assume the following:
1275	* PreemptTimerShift = 5
1276	* VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1277	* EntryTick = 50000 (TSC at time of VM-entry)
1278	*
1279	* CurTick Delta PreemptTimerVal
1280	* ----------------------------------
1281	* 60000 10000 2
1282	* 80000 30000 1
1283	* 90000 40000 0 -> VM-exit.
1284	*
1285	* If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1286	* The saved VMX-preemption timer value is calculated as follows:
1287	* PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1288	* E.g.:
1289	* Delta = 10000
1290	* Tmp = 10000 / (2 * 10000) = 0.5
1291	* NewPt = 2 - 0.5 = 2
1292	* Delta = 30000
1293	* Tmp = 30000 / (2 * 10000) = 1.5
1294	* NewPt = 2 - 1.5 = 1
1295	* Delta = 40000
1296	* Tmp = 40000 / 20000 = 2
1297	* NewPt = 2 - 2 = 0
1298	*/
1299	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1300	uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1301	if (uVmcsPreemptVal > 0)
1302	{
1303	uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1304	uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1305	uint64_t const uDelta = uCurTick - uEntryTick;
1306	uint32_t const uPreemptTimer = uVmcsPreemptVal
1307	- ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1308	return uPreemptTimer;
1309	}
1310	return 0;
1311	}
1312
1313
1314	/**
1315	* Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1316	*
1317	* @param pVCpu The cross context virtual CPU structure.
1318	*/
1319	IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1320	{
1321	/*
1322	* Save guest segment registers, GDTR, IDTR, LDTR, TR.
1323	* See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1324	*/
1325	/* CS, SS, ES, DS, FS, GS. */
1326	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1327	for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1328	{
1329	PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1330	if (!pSelReg->Attr.n.u1Unusable)
1331	iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1332	else
1333	{
1334	/*
1335	* For unusable segments the attributes are undefined except for CS and SS.
1336	* For the rest we don't bother preserving anything but the unusable bit.
1337	*/
1338	switch (iSegReg)
1339	{
1340	case X86_SREG_CS:
1341	pVmcs->GuestCs = pSelReg->Sel;
1342	pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1343	pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1344	pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L \| X86DESCATTR_D \| X86DESCATTR_G
1345	\| X86DESCATTR_UNUSABLE);
1346	break;
1347
1348	case X86_SREG_SS:
1349	pVmcs->GuestSs = pSelReg->Sel;
1350	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1351	pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1352	pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL \| X86DESCATTR_UNUSABLE);
1353	break;
1354
1355	case X86_SREG_DS:
1356	pVmcs->GuestDs = pSelReg->Sel;
1357	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1358	pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1359	pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1360	break;
1361
1362	case X86_SREG_ES:
1363	pVmcs->GuestEs = pSelReg->Sel;
1364	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1365	pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1366	pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1367	break;
1368
1369	case X86_SREG_FS:
1370	pVmcs->GuestFs = pSelReg->Sel;
1371	pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1372	pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1373	break;
1374
1375	case X86_SREG_GS:
1376	pVmcs->GuestGs = pSelReg->Sel;
1377	pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1378	pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1379	break;
1380	}
1381	}
1382	}
1383
1384	/* Segment attribute bits 31:17 and 11:8 MBZ. */
1385	uint32_t const fValidAttrMask = X86DESCATTR_TYPE \| X86DESCATTR_DT \| X86DESCATTR_DPL \| X86DESCATTR_P
1386	\| X86DESCATTR_AVL \| X86DESCATTR_L \| X86DESCATTR_D \| X86DESCATTR_G
1387	\| X86DESCATTR_UNUSABLE;
1388	/* LDTR. */
1389	{
1390	PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1391	pVmcs->GuestLdtr = pSelReg->Sel;
1392	pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1393	Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1394	pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1395	pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1396	}
1397
1398	/* TR. */
1399	{
1400	PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1401	pVmcs->GuestTr = pSelReg->Sel;
1402	pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1403	pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1404	pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1405	}
1406
1407	/* GDTR. */
1408	pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1409	pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1410
1411	/* IDTR. */
1412	pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1413	pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1414	}
1415
1416
1417	/**
1418	* Saves guest non-register state as part of VM-exit.
1419	*
1420	* @param pVCpu The cross context virtual CPU structure.
1421	* @param uExitReason The VM-exit reason.
1422	*/
1423	IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1424	{
1425	/*
1426	* Save guest non-register state.
1427	* See Intel spec. 27.3.4 "Saving Non-Register State".
1428	*/
1429	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1430
1431	/*
1432	* Activity state.
1433	* Most VM-exits will occur in the active state. However, if the first instruction
1434	* following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1435	* the VM-exit will be from the HLT activity state.
1436	*
1437	* See Intel spec. 25.5.2 "Monitor Trap Flag".
1438	*/
1439	/** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1440	* not? */
1441	EMSTATE const enmActivityState = EMGetState(pVCpu);
1442	switch (enmActivityState)
1443	{
1444	case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1445	default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1446	}
1447
1448	/*
1449	* Interruptibility-state.
1450	*/
1451	/* NMI. */
1452	pVmcs->u32GuestIntrState = 0;
1453	if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1454	{
1455	if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1456	pVmcs->u32GuestIntrState \|= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1457	}
1458	else
1459	{
1460	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1461	pVmcs->u32GuestIntrState \|= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1462	}
1463
1464	/* Blocking-by-STI. */
1465	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1466	&& pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1467	{
1468	/** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1469	* currently. */
1470	pVmcs->u32GuestIntrState \|= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1471	}
1472	/* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1473
1474	/*
1475	* Pending debug exceptions.
1476	*
1477	* For VM-exits where it is not applicable, we can safely zero out the field.
1478	* For VM-exits where it is applicable, it's expected to be updated by the caller already.
1479	*/
1480	if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1481	&& uExitReason != VMX_EXIT_SMI
1482	&& uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1483	&& !VMXIsVmexitTrapLike(uExitReason))
1484	{
1485	/** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1486	* block-by-MovSS is in effect. */
1487	pVmcs->u64GuestPendingDbgXcpts.u = 0;
1488	}
1489
1490	/*
1491	* Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1492	*
1493	* For VMX-preemption timer VM-exits, we should have already written back 0 if the
1494	* feature is supported back into the VMCS, and thus there is nothing further to do here.
1495	*/
1496	if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1497	&& (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1498	pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1499
1500	/*
1501	* PAE PDPTEs.
1502	*
1503	* If EPT is enabled and PAE paging was used at the time of the VM-exit,
1504	* the PDPTEs are saved from the VMCS. Otherwise they're undefined but
1505	* we zero them for consistency.
1506	*/
1507	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1508	{
1509	if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
1510	&& (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1511	&& (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
1512	{
1513	pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1514	pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1515	pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1516	pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1517	}
1518	else
1519	{
1520	pVmcs->u64GuestPdpte0.u = 0;
1521	pVmcs->u64GuestPdpte1.u = 0;
1522	pVmcs->u64GuestPdpte2.u = 0;
1523	pVmcs->u64GuestPdpte3.u = 0;
1524	}
1525
1526	/* Clear PGM's copy of the EPT pointer for added safety. */
1527	PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1528	}
1529	else
1530	{
1531	pVmcs->u64GuestPdpte0.u = 0;
1532	pVmcs->u64GuestPdpte1.u = 0;
1533	pVmcs->u64GuestPdpte2.u = 0;
1534	pVmcs->u64GuestPdpte3.u = 0;
1535	}
1536	}
1537
1538
1539	/**
1540	* Saves the guest-state as part of VM-exit.
1541	*
1542	* @returns VBox status code.
1543	* @param pVCpu The cross context virtual CPU structure.
1544	* @param uExitReason The VM-exit reason.
1545	*/
1546	IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1547	{
1548	iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1549	iemVmxVmexitSaveGuestSegRegs(pVCpu);
1550
1551	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1552	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1553	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1554
1555	iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1556	}
1557
1558
1559	/**
1560	* Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1561	*
1562	* @returns VBox status code.
1563	* @param pVCpu The cross context virtual CPU structure.
1564	* @param uExitReason The VM-exit reason (for diagnostic purposes).
1565	*/
1566	IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1567	{
1568	/*
1569	* Save guest MSRs.
1570	* See Intel spec. 27.4 "Saving MSRs".
1571	*/
1572	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1573	const char * const pszFailure = "VMX-abort";
1574
1575	/*
1576	* The VM-exit MSR-store area address need not be a valid guest-physical address if the
1577	* VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1578	* See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1579	*/
1580	uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1581	if (!cMsrs)
1582	return VINF_SUCCESS;
1583
1584	/*
1585	* Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1586	* is exceeded including possibly raising #MC exceptions during VMX transition. Our
1587	* implementation causes a VMX-abort followed by a triple-fault.
1588	*/
1589	bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1590	if (fIsMsrCountValid)
1591	{ /* likely */ }
1592	else
1593	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1594
1595	/*
1596	* Optimization if the nested hypervisor is using the same guest-physical page for both
1597	* the VM-entry MSR-load area as well as the VM-exit MSR store area.
1598	*/
1599	PVMXAUTOMSR pMsrArea;
1600	RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1601	RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1602	if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1603	pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1604	else
1605	{
1606	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1607	GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1608	if (RT_SUCCESS(rc))
1609	pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1610	else
1611	{
1612	AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1613	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1614	}
1615	}
1616
1617	/*
1618	* Update VM-exit MSR store area.
1619	*/
1620	PVMXAUTOMSR pMsr = pMsrArea;
1621	for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1622	{
1623	if ( !pMsr->u32Reserved
1624	&& pMsr->u32Msr != MSR_IA32_SMBASE
1625	&& pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1626	{
1627	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1628	if (rcStrict == VINF_SUCCESS)
1629	continue;
1630
1631	/*
1632	* If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1633	* If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1634	* recording the MSR index in the auxiliary info. field and indicated further by our
1635	* own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1636	* if possible, or come up with a better, generic solution.
1637	*/
1638	pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1639	VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1640	? kVmxVDiag_Vmexit_MsrStoreRing3
1641	: kVmxVDiag_Vmexit_MsrStore;
1642	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1643	}
1644	else
1645	{
1646	pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1647	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1648	}
1649	}
1650
1651	/*
1652	* Commit the VM-exit MSR store are to guest memory.
1653	*/
1654	int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1655	if (RT_SUCCESS(rc))
1656	return VINF_SUCCESS;
1657
1658	NOREF(uExitReason);
1659	NOREF(pszFailure);
1660
1661	AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1662	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1663	}
1664
1665
1666	/**
1667	* Performs a VMX abort (due to an fatal error during VM-exit).
1668	*
1669	* @returns Strict VBox status code.
1670	* @param pVCpu The cross context virtual CPU structure.
1671	* @param enmAbort The VMX abort reason.
1672	*/
1673	IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1674	{
1675	/*
1676	* Perform the VMX abort.
1677	* See Intel spec. 27.7 "VMX Aborts".
1678	*/
1679	LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1680
1681	/* We don't support SMX yet. */
1682	pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1683	if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1684	{
1685	RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1686	uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1687	PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1688	}
1689
1690	return VINF_EM_TRIPLE_FAULT;
1691	}
1692
1693
1694	/**
1695	* Loads host control registers, debug registers and MSRs as part of VM-exit.
1696	*
1697	* @param pVCpu The cross context virtual CPU structure.
1698	*/
1699	IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1700	{
1701	/*
1702	* Load host control registers, debug registers and MSRs.
1703	* See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1704	*/
1705	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1706	bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1707
1708	/* CR0. */
1709	{
1710	/* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1711	uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1712	uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1713	uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK \| uCr0Mb1 \| ~uCr0Mb0;
1714	uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1715	uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1716	uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) \| (uGuestCr0 & fCr0IgnMask);
1717
1718	/* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1719	Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1720	Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1721	CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1722	}
1723
1724	/* CR4. */
1725	{
1726	/* CR4 fixed bits are not modified. */
1727	uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1728	uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1729	uint64_t const fCr4IgnMask = uCr4Mb1 \| ~uCr4Mb0;
1730	uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1731	uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1732	uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) \| (uGuestCr4 & fCr4IgnMask);
1733	if (fHostInLongMode)
1734	uValidHostCr4 \|= X86_CR4_PAE;
1735	else
1736	uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1737
1738	/* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1739	Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1740	Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1741	CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1742	}
1743
1744	/* CR3 (host value validated while checking host-state during VM-entry). */
1745	pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1746
1747	/* DR7. */
1748	pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1749
1750	/** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1751
1752	/* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1753	pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1754	pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1755	pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1756
1757	/* FS, GS bases are loaded later while we load host segment registers. */
1758
1759	/* EFER MSR (host value validated while checking host-state during VM-entry). */
1760	if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1761	pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1762	else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1763	{
1764	if (fHostInLongMode)
1765	pVCpu->cpum.GstCtx.msrEFER \|= (MSR_K6_EFER_LMA \| MSR_K6_EFER_LME);
1766	else
1767	pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA \| MSR_K6_EFER_LME);
1768	}
1769
1770	/* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1771
1772	/* PAT MSR (host value is validated while checking host-state during VM-entry). */
1773	if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1774	pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1775
1776	/* We don't support IA32_BNDCFGS MSR yet. */
1777	}
1778
1779
1780	/**
1781	* Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1782	*
1783	* @param pVCpu The cross context virtual CPU structure.
1784	*/
1785	IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1786	{
1787	/*
1788	* Load host segment registers, GDTR, IDTR, LDTR and TR.
1789	* See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1790	*
1791	* Warning! Be careful to not touch fields that are reserved by VT-x,
1792	* e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1793	*/
1794	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1795	bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1796
1797	/* CS, SS, ES, DS, FS, GS. */
1798	for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1799	{
1800	RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1801	bool const fUnusable = RT_BOOL(HostSel == 0);
1802	PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1803
1804	/* Selector. */
1805	pSelReg->Sel = HostSel;
1806	pSelReg->ValidSel = HostSel;
1807	pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1808
1809	/* Limit. */
1810	pSelReg->u32Limit = 0xffffffff;
1811
1812	/* Base. */
1813	pSelReg->u64Base = 0;
1814
1815	/* Attributes. */
1816	if (iSegReg == X86_SREG_CS)
1817	{
1818	pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE \| X86_SEL_TYPE_READ \| X86_SEL_TYPE_ACCESSED;
1819	pSelReg->Attr.n.u1DescType = 1;
1820	pSelReg->Attr.n.u2Dpl = 0;
1821	pSelReg->Attr.n.u1Present = 1;
1822	pSelReg->Attr.n.u1Long = fHostInLongMode;
1823	pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1824	pSelReg->Attr.n.u1Granularity = 1;
1825	Assert(!pSelReg->Attr.n.u1Unusable);
1826	Assert(!fUnusable);
1827	}
1828	else
1829	{
1830	pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW \| X86_SEL_TYPE_ACCESSED;
1831	pSelReg->Attr.n.u1DescType = 1;
1832	pSelReg->Attr.n.u2Dpl = 0;
1833	pSelReg->Attr.n.u1Present = 1;
1834	pSelReg->Attr.n.u1DefBig = 1;
1835	pSelReg->Attr.n.u1Granularity = 1;
1836	pSelReg->Attr.n.u1Unusable = fUnusable;
1837	}
1838	}
1839
1840	/* FS base. */
1841	if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1842	\|\| fHostInLongMode)
1843	{
1844	Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1845	pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1846	}
1847
1848	/* GS base. */
1849	if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1850	\|\| fHostInLongMode)
1851	{
1852	Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1853	pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1854	}
1855
1856	/* TR. */
1857	Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1858	Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1859	pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1860	pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1861	pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1862	pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1863	pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1864	pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1865	pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1866	pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1867	pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1868	pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1869	pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1870
1871	/* LDTR (Warning! do not touch the base and limits here). */
1872	pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1873	pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1874	pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1875	pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1876
1877	/* GDTR. */
1878	Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1879	pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1880	pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1881
1882	/* IDTR.*/
1883	Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1884	pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1885	pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1886	}
1887
1888
1889	/**
1890	* Checks the host PAE PDPTEs assuming we are switching to a PAE mode host.
1891	*
1892	* @param pVCpu The cross context virtual CPU structure.
1893	* @param uExitReason The VMX instruction name (for logging purposes).
1894	*
1895	* @remarks Caller must ensure the preconditions are met before calling this
1896	* function as failure here will trigger VMX aborts!
1897	*/
1898	IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPUCC pVCpu, uint32_t uExitReason)
1899	{
1900	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1901	const char * const pszFailure = "VMX-abort";
1902	int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
1903	if (RT_SUCCESS(rc))
1904	return rc;
1905	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpte);
1906	}
1907
1908
1909	/**
1910	* Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1911	*
1912	* @returns VBox status code.
1913	* @param pVCpu The cross context virtual CPU structure.
1914	* @param uExitReason The VMX instruction name (for logging purposes).
1915	*/
1916	IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1917	{
1918	/*
1919	* Load host MSRs.
1920	* See Intel spec. 27.6 "Loading MSRs".
1921	*/
1922	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1923	const char * const pszFailure = "VMX-abort";
1924
1925	/*
1926	* The VM-exit MSR-load area address need not be a valid guest-physical address if the
1927	* VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1928	* See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1929	*/
1930	uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1931	if (!cMsrs)
1932	return VINF_SUCCESS;
1933
1934	/*
1935	* Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1936	* is exceeded including possibly raising #MC exceptions during VMX transition. Our
1937	* implementation causes a VMX-abort followed by a triple-fault.
1938	*/
1939	bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1940	if (fIsMsrCountValid)
1941	{ /* likely */ }
1942	else
1943	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1944
1945	RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1946	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1947	GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1948	if (RT_SUCCESS(rc))
1949	{
1950	PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1951	for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1952	{
1953	if ( !pMsr->u32Reserved
1954	&& pMsr->u32Msr != MSR_K8_FS_BASE
1955	&& pMsr->u32Msr != MSR_K8_GS_BASE
1956	&& pMsr->u32Msr != MSR_K6_EFER
1957	&& pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1958	&& pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1959	{
1960	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1961	if (rcStrict == VINF_SUCCESS)
1962	continue;
1963
1964	/*
1965	* If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1966	* If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1967	* recording the MSR index in the auxiliary info. field and indicated further by our
1968	* own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1969	* if possible, or come up with a better, generic solution.
1970	*/
1971	pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1972	VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1973	? kVmxVDiag_Vmexit_MsrLoadRing3
1974	: kVmxVDiag_Vmexit_MsrLoad;
1975	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1976	}
1977	else
1978	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1979	}
1980	}
1981	else
1982	{
1983	AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1984	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1985	}
1986
1987	NOREF(uExitReason);
1988	NOREF(pszFailure);
1989	return VINF_SUCCESS;
1990	}
1991
1992
1993	/**
1994	* Loads the host state as part of VM-exit.
1995	*
1996	* @returns Strict VBox status code.
1997	* @param pVCpu The cross context virtual CPU structure.
1998	* @param uExitReason The VM-exit reason (for logging purposes).
1999	*/
2000	IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
2001	{
2002	/*
2003	* Load host state.
2004	* See Intel spec. 27.5 "Loading Host State".
2005	*/
2006	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2007	bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2008
2009	/* We cannot return from a long-mode guest to a host that is not in long mode. */
2010	if ( CPUMIsGuestInLongMode(pVCpu)
2011	&& !fHostInLongMode)
2012	{
2013	Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2014	return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2015	}
2016
2017	/*
2018	* Check host PAE PDPTEs prior to loading the host state.
2019	* See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2020	*/
2021	bool fPdpesMapped;
2022	if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2023	&& !fHostInLongMode
2024	&& ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2025	\|\| pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2026	{
2027	int const rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2028	if (RT_FAILURE(rc))
2029	{
2030	Log(("VM-exit attempting to load invalid PDPTEs -> VMX-Abort\n"));
2031	return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2032	}
2033	fPdpesMapped = true;
2034	}
2035	else
2036	fPdpesMapped = false;
2037
2038	iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2039	iemVmxVmexitLoadHostSegRegs(pVCpu);
2040
2041	/*
2042	* Load host RIP, RSP and RFLAGS.
2043	* See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2044	*/
2045	pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2046	pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2047	pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2048
2049	/* Clear address range monitoring. */
2050	EMMonitorWaitClear(pVCpu);
2051
2052	/* Perform the VMX transition (PGM updates). */
2053	VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu, fPdpesMapped);
2054	if (rcStrict == VINF_SUCCESS)
2055	{ /* likely */ }
2056	else if (RT_SUCCESS(rcStrict))
2057	{
2058	Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2059	uExitReason));
2060	rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2061	}
2062	else
2063	{
2064	Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2065	return VBOXSTRICTRC_VAL(rcStrict);
2066	}
2067
2068	Assert(rcStrict == VINF_SUCCESS);
2069
2070	/* Load MSRs from the VM-exit auto-load MSR area. */
2071	int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2072	if (RT_FAILURE(rc))
2073	{
2074	Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2075	return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2076	}
2077	return VINF_SUCCESS;
2078	}
2079
2080
2081	/**
2082	* Gets VM-exit instruction information along with any displacement for an
2083	* instruction VM-exit.
2084	*
2085	* @returns The VM-exit instruction information.
2086	* @param pVCpu The cross context virtual CPU structure.
2087	* @param uExitReason The VM-exit reason.
2088	* @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2089	* @param pGCPtrDisp Where to store the displacement field. Optional, can be
2090	* NULL.
2091	*/
2092	IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2093	{
2094	RTGCPTR GCPtrDisp;
2095	VMXEXITINSTRINFO ExitInstrInfo;
2096	ExitInstrInfo.u = 0;
2097
2098	/*
2099	* Get and parse the ModR/M byte from our decoded opcodes.
2100	*/
2101	uint8_t bRm;
2102	uint8_t const offModRm = pVCpu->iem.s.offModRm;
2103	IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2104	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2105	{
2106	/*
2107	* ModR/M indicates register addressing.
2108	*
2109	* The primary/secondary register operands are reported in the iReg1 or iReg2
2110	* fields depending on whether it is a read/write form.
2111	*/
2112	uint8_t idxReg1;
2113	uint8_t idxReg2;
2114	if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2115	{
2116	idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg;
2117	idxReg2 = (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB;
2118	}
2119	else
2120	{
2121	idxReg1 = (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB;
2122	idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg;
2123	}
2124	ExitInstrInfo.All.u2Scaling = 0;
2125	ExitInstrInfo.All.iReg1 = idxReg1;
2126	ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2127	ExitInstrInfo.All.fIsRegOperand = 1;
2128	ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2129	ExitInstrInfo.All.iSegReg = 0;
2130	ExitInstrInfo.All.iIdxReg = 0;
2131	ExitInstrInfo.All.fIdxRegInvalid = 1;
2132	ExitInstrInfo.All.iBaseReg = 0;
2133	ExitInstrInfo.All.fBaseRegInvalid = 1;
2134	ExitInstrInfo.All.iReg2 = idxReg2;
2135
2136	/* Displacement not applicable for register addressing. */
2137	GCPtrDisp = 0;
2138	}
2139	else
2140	{
2141	/*
2142	* ModR/M indicates memory addressing.
2143	*/
2144	uint8_t uScale = 0;
2145	bool fBaseRegValid = false;
2146	bool fIdxRegValid = false;
2147	uint8_t iBaseReg = 0;
2148	uint8_t iIdxReg = 0;
2149	if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2150	{
2151	/*
2152	* Parse the ModR/M, displacement for 16-bit addressing mode.
2153	* See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2154	*/
2155	uint16_t u16Disp = 0;
2156	uint8_t const offDisp = offModRm + sizeof(bRm);
2157	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 6)
2158	{
2159	/* Displacement without any registers. */
2160	IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2161	}
2162	else
2163	{
2164	/* Register (index and base). */
2165	switch (bRm & X86_MODRM_RM_MASK)
2166	{
2167	case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2168	case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2169	case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2170	case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2171	case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2172	case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2173	case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2174	case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2175	}
2176
2177	/* Register + displacement. */
2178	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2179	{
2180	case 0: break;
2181	case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2182	case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2183	default:
2184	{
2185	/* Register addressing, handled at the beginning. */
2186	AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2187	break;
2188	}
2189	}
2190	}
2191
2192	Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2193	GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2194	}
2195	else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2196	{
2197	/*
2198	* Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2199	* See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2200	*/
2201	uint32_t u32Disp = 0;
2202	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
2203	{
2204	/* Displacement without any registers. */
2205	uint8_t const offDisp = offModRm + sizeof(bRm);
2206	IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2207	}
2208	else
2209	{
2210	/* Register (and perhaps scale, index and base). */
2211	uint8_t offDisp = offModRm + sizeof(bRm);
2212	iBaseReg = (bRm & X86_MODRM_RM_MASK);
2213	if (iBaseReg == 4)
2214	{
2215	/* An SIB byte follows the ModR/M byte, parse it. */
2216	uint8_t bSib;
2217	uint8_t const offSib = offModRm + sizeof(bRm);
2218	IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2219
2220	/* A displacement may follow SIB, update its offset. */
2221	offDisp += sizeof(bSib);
2222
2223	/* Get the scale. */
2224	uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2225
2226	/* Get the index register. */
2227	iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2228	fIdxRegValid = RT_BOOL(iIdxReg != 4);
2229
2230	/* Get the base register. */
2231	iBaseReg = bSib & X86_SIB_BASE_MASK;
2232	fBaseRegValid = true;
2233	if (iBaseReg == 5)
2234	{
2235	if ((bRm & X86_MODRM_MOD_MASK) == 0)
2236	{
2237	/* Mod is 0 implies a 32-bit displacement with no base. */
2238	fBaseRegValid = false;
2239	IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2240	}
2241	else
2242	{
2243	/* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2244	iBaseReg = X86_GREG_xBP;
2245	}
2246	}
2247	}
2248
2249	/* Register + displacement. */
2250	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2251	{
2252	case 0: /* Handled above */ break;
2253	case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2254	case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2255	default:
2256	{
2257	/* Register addressing, handled at the beginning. */
2258	AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2259	break;
2260	}
2261	}
2262	}
2263
2264	GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2265	}
2266	else
2267	{
2268	Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2269
2270	/*
2271	* Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2272	* See Intel instruction spec. 2.2 "IA-32e Mode".
2273	*/
2274	uint64_t u64Disp = 0;
2275	bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5);
2276	if (fRipRelativeAddr)
2277	{
2278	/*
2279	* RIP-relative addressing mode.
2280	*
2281	* The displacement is 32-bit signed implying an offset range of +/-2G.
2282	* See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2283	*/
2284	uint8_t const offDisp = offModRm + sizeof(bRm);
2285	IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2286	}
2287	else
2288	{
2289	uint8_t offDisp = offModRm + sizeof(bRm);
2290
2291	/*
2292	* Register (and perhaps scale, index and base).
2293	*
2294	* REX.B extends the most-significant bit of the base register. However, REX.B
2295	* is ignored while determining whether an SIB follows the opcode. Hence, we
2296	* shall OR any REX.B bit -after- inspecting for an SIB byte below.
2297	*
2298	* See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2299	*/
2300	iBaseReg = (bRm & X86_MODRM_RM_MASK);
2301	if (iBaseReg == 4)
2302	{
2303	/* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2304	uint8_t bSib;
2305	uint8_t const offSib = offModRm + sizeof(bRm);
2306	IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2307
2308	/* Displacement may follow SIB, update its offset. */
2309	offDisp += sizeof(bSib);
2310
2311	/* Get the scale. */
2312	uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2313
2314	/* Get the index. */
2315	iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) \| pVCpu->iem.s.uRexIndex;
2316	fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2317
2318	/* Get the base. */
2319	iBaseReg = (bSib & X86_SIB_BASE_MASK);
2320	fBaseRegValid = true;
2321	if (iBaseReg == 5)
2322	{
2323	if ((bRm & X86_MODRM_MOD_MASK) == 0)
2324	{
2325	/* Mod is 0 implies a signed 32-bit displacement with no base. */
2326	IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2327	}
2328	else
2329	{
2330	/* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2331	iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2332	}
2333	}
2334	}
2335	iBaseReg \|= pVCpu->iem.s.uRexB;
2336
2337	/* Register + displacement. */
2338	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2339	{
2340	case 0: /* Handled above */ break;
2341	case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2342	case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2343	default:
2344	{
2345	/* Register addressing, handled at the beginning. */
2346	AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2347	break;
2348	}
2349	}
2350	}
2351
2352	GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2353	}
2354
2355	/*
2356	* The primary or secondary register operand is reported in iReg2 depending
2357	* on whether the primary operand is in read/write form.
2358	*/
2359	uint8_t idxReg2;
2360	if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2361	{
2362	idxReg2 = bRm & X86_MODRM_RM_MASK;
2363	if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2364	idxReg2 \|= pVCpu->iem.s.uRexB;
2365	}
2366	else
2367	{
2368	idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2369	if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2370	idxReg2 \|= pVCpu->iem.s.uRexReg;
2371	}
2372	ExitInstrInfo.All.u2Scaling = uScale;
2373	ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2374	ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2375	ExitInstrInfo.All.fIsRegOperand = 0;
2376	ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2377	ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2378	ExitInstrInfo.All.iIdxReg = iIdxReg;
2379	ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2380	ExitInstrInfo.All.iBaseReg = iBaseReg;
2381	ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2382	ExitInstrInfo.All.iReg2 = idxReg2;
2383	}
2384
2385	/*
2386	* Handle exceptions to the norm for certain instructions.
2387	* (e.g. some instructions convey an instruction identity in place of iReg2).
2388	*/
2389	switch (uExitReason)
2390	{
2391	case VMX_EXIT_GDTR_IDTR_ACCESS:
2392	{
2393	Assert(VMXINSTRID_IS_VALID(uInstrId));
2394	Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2395	ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2396	ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2397	break;
2398	}
2399
2400	case VMX_EXIT_LDTR_TR_ACCESS:
2401	{
2402	Assert(VMXINSTRID_IS_VALID(uInstrId));
2403	Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2404	ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2405	ExitInstrInfo.LdtTr.u2Undef0 = 0;
2406	break;
2407	}
2408
2409	case VMX_EXIT_RDRAND:
2410	case VMX_EXIT_RDSEED:
2411	{
2412	Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2413	break;
2414	}
2415	}
2416
2417	/* Update displacement and return the constructed VM-exit instruction information field. */
2418	if (pGCPtrDisp)
2419	*pGCPtrDisp = GCPtrDisp;
2420
2421	return ExitInstrInfo.u;
2422	}
2423
2424
2425	/**
2426	* VMX VM-exit handler.
2427	*
2428	* @returns Strict VBox status code.
2429	* @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2430	* @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2431	* triple-fault.
2432	*
2433	* @param pVCpu The cross context virtual CPU structure.
2434	* @param uExitReason The VM-exit reason.
2435	* @param u64ExitQual The Exit qualification.
2436	*/
2437	IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2438	{
2439	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2440	RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2441	AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2442	return VERR_IEM_IPE_7;
2443	# else
2444	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2445
2446	/*
2447	* Import all the guest-CPU state.
2448	*
2449	* HM on returning to guest execution would have to reset up a whole lot of state
2450	* anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2451	* the state and flag reloading the entire state on re-entry. So import the entire
2452	* state here, see HMNotifyVmxNstGstVmexit() for more comments.
2453	*/
2454	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2455
2456	/*
2457	* Ensure VM-entry interruption information valid bit is cleared.
2458	*
2459	* We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2460	* by invalid-guest state or machine-check exceptions) also clear this bit.
2461	*
2462	* See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2463	*/
2464	if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2465	pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2466
2467	/*
2468	* Update the VM-exit reason and Exit qualification.
2469	* Other VMCS read-only data fields are expected to be updated by the caller already.
2470	*/
2471	pVmcs->u32RoExitReason = uExitReason;
2472	pVmcs->u64RoExitQual.u = u64ExitQual;
2473
2474	Log3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2475	pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2476	pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2477
2478	/*
2479	* Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2480	* See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2481	*/
2482	{
2483	uint8_t uVector;
2484	uint32_t fFlags;
2485	uint32_t uErrCode;
2486	bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2487	if (fInEventDelivery)
2488	{
2489	/*
2490	* A VM-exit is not considered to occur during event delivery when the VM-exit is
2491	* caused by a triple-fault or the original event results in a double-fault that
2492	* causes the VM exit directly (exception bitmap). Therefore, we must not set the
2493	* original event information into the IDT-vectoring information fields.
2494	*
2495	* See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2496	*/
2497	if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2498	&& ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2499	\|\| !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2500	{
2501	uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2502	uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2503	uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2504	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2505	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2506	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2507	iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2508	iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2509	LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2510	pVCpu->cpum.GstCtx.cr2));
2511	}
2512	}
2513	}
2514
2515	/* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2516	Assert(pVmcs->u64RoIoRcx.u == 0);
2517	Assert(pVmcs->u64RoIoRsi.u == 0);
2518	Assert(pVmcs->u64RoIoRdi.u == 0);
2519	Assert(pVmcs->u64RoIoRip.u == 0);
2520
2521	/* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2522	if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2523	{
2524	Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2525	Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2526	}
2527
2528	/* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2529	Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI \|\| VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2530
2531	/*
2532	* Save the guest state back into the VMCS.
2533	* We only need to save the state when the VM-entry was successful.
2534	*/
2535	bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2536	if (!fVmentryFailed)
2537	{
2538	/*
2539	* If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2540	* See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2541	*
2542	* It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2543	* If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2544	* as guest-CPU state would not been modified. Hence for now, we do this only when
2545	* the VM-entry succeeded.
2546	*/
2547	/** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2548	* hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2549	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2550	{
2551	if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2552	pVmcs->u32EntryCtls \|= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2553	else
2554	pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2555	}
2556
2557	/*
2558	* The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2559	* occurs in enclave mode/SMM which we don't support yet.
2560	*
2561	* If we ever add support for it, we can pass just the lower bits to the functions
2562	* below, till then an assert should suffice.
2563	*/
2564	Assert(!RT_HI_U16(uExitReason));
2565
2566	/* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2567	iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2568	int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2569	if (RT_SUCCESS(rc))
2570	{ /* likely */ }
2571	else
2572	return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2573
2574	/* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2575	pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2576	}
2577	else
2578	{
2579	/* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2580	uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2581	if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2582	\|\| uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2583	iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2584	}
2585
2586	/*
2587	* Stop any running VMX-preemption timer if necessary.
2588	*/
2589	if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2590	CPUMStopGuestVmxPremptTimer(pVCpu);
2591
2592	/*
2593	* Clear any pending VMX nested-guest force-flags.
2594	* These force-flags have no effect on (outer) guest execution and will
2595	* be re-evaluated and setup on the next nested-guest VM-entry.
2596	*/
2597	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2598
2599	/*
2600	* We're no longer in nested-guest execution mode.
2601	*
2602	* It is important to do this prior to loading the host state because
2603	* PGM looks at fInVmxNonRootMode to determine if it needs to perform
2604	* second-level address translation while switching to host CR3.
2605	*/
2606	pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2607
2608	/* Restore the host (outer guest) state. */
2609	VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2610	if (RT_SUCCESS(rcStrict))
2611	{
2612	Assert(rcStrict == VINF_SUCCESS);
2613	rcStrict = VINF_VMX_VMEXIT;
2614	}
2615	else
2616	Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2617
2618	/* Notify HM that the current VMCS fields have been modified. */
2619	HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2620
2621	/* Notify HM that we've completed the VM-exit. */
2622	HMNotifyVmxNstGstVmexit(pVCpu);
2623
2624	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2625	/* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2626	Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2627	int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2628	if (rcSched != VINF_SUCCESS)
2629	iemSetPassUpStatus(pVCpu, rcSched);
2630	# endif
2631	return rcStrict;
2632	# endif
2633	}
2634
2635
2636	/**
2637	* VMX VM-exit handler for VM-exits due to instruction execution.
2638	*
2639	* This is intended for instructions where the caller provides all the relevant
2640	* VM-exit information.
2641	*
2642	* @returns Strict VBox status code.
2643	* @param pVCpu The cross context virtual CPU structure.
2644	* @param pExitInfo Pointer to the VM-exit information.
2645	*/
2646	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2647	{
2648	/*
2649	* For instructions where any of the following fields are not applicable:
2650	* - Exit qualification must be cleared.
2651	* - VM-exit instruction info. is undefined.
2652	* - Guest-linear address is undefined.
2653	* - Guest-physical address is undefined.
2654	*
2655	* The VM-exit instruction length is mandatory for all VM-exits that are caused by
2656	* instruction execution. For VM-exits that are not due to instruction execution this
2657	* field is undefined.
2658	*
2659	* In our implementation in IEM, all undefined fields are generally cleared. However,
2660	* if the caller supplies information (from say the physical CPU directly) it is
2661	* then possible that the undefined fields are not cleared.
2662	*
2663	* See Intel spec. 27.2.1 "Basic VM-Exit Information".
2664	* See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2665	*/
2666	Assert(pExitInfo);
2667	AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2668	AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2669	("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2670
2671	/* Update all the relevant fields from the VM-exit instruction information struct. */
2672	iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2673	iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2674	iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2675	iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2676
2677	/* Perform the VM-exit. */
2678	return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2679	}
2680
2681
2682	/**
2683	* VMX VM-exit handler for VM-exits due to instruction execution.
2684	*
2685	* This is intended for instructions that only provide the VM-exit instruction
2686	* length.
2687	*
2688	* @param pVCpu The cross context virtual CPU structure.
2689	* @param uExitReason The VM-exit reason.
2690	* @param cbInstr The instruction length in bytes.
2691	*/
2692	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2693	{
2694	VMXVEXITINFO ExitInfo;
2695	RT_ZERO(ExitInfo);
2696	ExitInfo.uReason = uExitReason;
2697	ExitInfo.cbInstr = cbInstr;
2698
2699	#ifdef VBOX_STRICT
2700	/*
2701	* To prevent us from shooting ourselves in the foot.
2702	* The follow instructions should convey more than just the instruction length.
2703	*/
2704	switch (uExitReason)
2705	{
2706	case VMX_EXIT_INVEPT:
2707	case VMX_EXIT_INVPCID:
2708	case VMX_EXIT_INVVPID:
2709	case VMX_EXIT_LDTR_TR_ACCESS:
2710	case VMX_EXIT_GDTR_IDTR_ACCESS:
2711	case VMX_EXIT_VMCLEAR:
2712	case VMX_EXIT_VMPTRLD:
2713	case VMX_EXIT_VMPTRST:
2714	case VMX_EXIT_VMREAD:
2715	case VMX_EXIT_VMWRITE:
2716	case VMX_EXIT_VMXON:
2717	case VMX_EXIT_XRSTORS:
2718	case VMX_EXIT_XSAVES:
2719	case VMX_EXIT_RDRAND:
2720	case VMX_EXIT_RDSEED:
2721	case VMX_EXIT_IO_INSTR:
2722	AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2723	break;
2724	}
2725	#endif
2726
2727	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2728	}
2729
2730
2731	/**
2732	* VMX VM-exit handler for VM-exits due to instruction execution.
2733	*
2734	* This is intended for instructions that have a ModR/M byte and update the VM-exit
2735	* instruction information and Exit qualification fields.
2736	*
2737	* @param pVCpu The cross context virtual CPU structure.
2738	* @param uExitReason The VM-exit reason.
2739	* @param uInstrid The instruction identity (VMXINSTRID_XXX).
2740	* @param cbInstr The instruction length in bytes.
2741	*
2742	* @remarks Do not use this for INS/OUTS instruction.
2743	*/
2744	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2745	{
2746	VMXVEXITINFO ExitInfo;
2747	RT_ZERO(ExitInfo);
2748	ExitInfo.uReason = uExitReason;
2749	ExitInfo.cbInstr = cbInstr;
2750
2751	/*
2752	* Update the Exit qualification field with displacement bytes.
2753	* See Intel spec. 27.2.1 "Basic VM-Exit Information".
2754	*/
2755	switch (uExitReason)
2756	{
2757	case VMX_EXIT_INVEPT:
2758	case VMX_EXIT_INVPCID:
2759	case VMX_EXIT_INVVPID:
2760	case VMX_EXIT_LDTR_TR_ACCESS:
2761	case VMX_EXIT_GDTR_IDTR_ACCESS:
2762	case VMX_EXIT_VMCLEAR:
2763	case VMX_EXIT_VMPTRLD:
2764	case VMX_EXIT_VMPTRST:
2765	case VMX_EXIT_VMREAD:
2766	case VMX_EXIT_VMWRITE:
2767	case VMX_EXIT_VMXON:
2768	case VMX_EXIT_XRSTORS:
2769	case VMX_EXIT_XSAVES:
2770	case VMX_EXIT_RDRAND:
2771	case VMX_EXIT_RDSEED:
2772	{
2773	/* Construct the VM-exit instruction information. */
2774	RTGCPTR GCPtrDisp;
2775	uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2776
2777	/* Update the VM-exit instruction information. */
2778	ExitInfo.InstrInfo.u = uInstrInfo;
2779
2780	/* Update the Exit qualification. */
2781	ExitInfo.u64Qual = GCPtrDisp;
2782	break;
2783	}
2784
2785	default:
2786	AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2787	break;
2788	}
2789
2790	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2791	}
2792
2793
2794	/**
2795	* VMX VM-exit handler for VM-exits due to INVLPG.
2796	*
2797	* @returns Strict VBox status code.
2798	* @param pVCpu The cross context virtual CPU structure.
2799	* @param GCPtrPage The guest-linear address of the page being invalidated.
2800	* @param cbInstr The instruction length in bytes.
2801	*/
2802	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2803	{
2804	VMXVEXITINFO ExitInfo;
2805	RT_ZERO(ExitInfo);
2806	ExitInfo.uReason = VMX_EXIT_INVLPG;
2807	ExitInfo.cbInstr = cbInstr;
2808	ExitInfo.u64Qual = GCPtrPage;
2809	Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode \|\| !RT_HI_U32(ExitInfo.u64Qual));
2810
2811	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2812	}
2813
2814
2815	/**
2816	* VMX VM-exit handler for VM-exits due to LMSW.
2817	*
2818	* @returns Strict VBox status code.
2819	* @param pVCpu The cross context virtual CPU structure.
2820	* @param uGuestCr0 The current guest CR0.
2821	* @param pu16NewMsw The machine-status word specified in LMSW's source
2822	* operand. This will be updated depending on the VMX
2823	* guest/host CR0 mask if LMSW is not intercepted.
2824	* @param GCPtrEffDst The guest-linear address of the source operand in case
2825	* of a memory operand. For register operand, pass
2826	* NIL_RTGCPTR.
2827	* @param cbInstr The instruction length in bytes.
2828	*/
2829	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2830	uint8_t cbInstr)
2831	{
2832	Assert(pu16NewMsw);
2833
2834	uint16_t const uNewMsw = *pu16NewMsw;
2835	if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2836	{
2837	Log2(("lmsw: Guest intercept -> VM-exit\n"));
2838
2839	VMXVEXITINFO ExitInfo;
2840	RT_ZERO(ExitInfo);
2841	ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2842	ExitInfo.cbInstr = cbInstr;
2843
2844	bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2845	if (fMemOperand)
2846	{
2847	Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode \|\| !RT_HI_U32(GCPtrEffDst));
2848	ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2849	}
2850
2851	ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2852	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2853	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2854	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2855
2856	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2857	}
2858
2859	/*
2860	* If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2861	* CR0 guest/host mask must be left unmodified.
2862	*
2863	* See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2864	*/
2865	uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2866	uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS);
2867	*pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) \| (uNewMsw & ~fGstHostLmswMask);
2868
2869	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2870	}
2871
2872
2873	/**
2874	* VMX VM-exit handler for VM-exits due to CLTS.
2875	*
2876	* @returns Strict VBox status code.
2877	* @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2878	* VM-exit but must not modify the guest CR0.TS bit.
2879	* @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2880	* VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2881	* CR0 fixed bits in VMX operation).
2882	* @param pVCpu The cross context virtual CPU structure.
2883	* @param cbInstr The instruction length in bytes.
2884	*/
2885	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2886	{
2887	uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2888	uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2889
2890	/*
2891	* If CR0.TS is owned by the host:
2892	* - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2893	* - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2894	* CLTS instruction completes without clearing CR0.TS.
2895	*
2896	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2897	*/
2898	if (fGstHostMask & X86_CR0_TS)
2899	{
2900	if (fReadShadow & X86_CR0_TS)
2901	{
2902	Log2(("clts: Guest intercept -> VM-exit\n"));
2903
2904	VMXVEXITINFO ExitInfo;
2905	RT_ZERO(ExitInfo);
2906	ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2907	ExitInfo.cbInstr = cbInstr;
2908	ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2909	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2910	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2911	}
2912
2913	return VINF_VMX_MODIFIES_BEHAVIOR;
2914	}
2915
2916	/*
2917	* If CR0.TS is not owned by the host, the CLTS instructions operates normally
2918	* and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2919	*/
2920	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2921	}
2922
2923
2924	/**
2925	* VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2926	* (CR0/CR4 write).
2927	*
2928	* @returns Strict VBox status code.
2929	* @param pVCpu The cross context virtual CPU structure.
2930	* @param iCrReg The control register (either CR0 or CR4).
2931	* @param uGuestCrX The current guest CR0/CR4.
2932	* @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2933	* VM-exit is caused.
2934	* @param iGReg The general register from which the CR0/CR4 value is being
2935	* loaded.
2936	* @param cbInstr The instruction length in bytes.
2937	*/
2938	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2939	uint8_t cbInstr)
2940	{
2941	Assert(puNewCrX);
2942	Assert(iCrReg == 0 \|\| iCrReg == 4);
2943	Assert(iGReg < X86_GREG_COUNT);
2944
2945	uint64_t const uNewCrX = *puNewCrX;
2946	if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2947	{
2948	Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2949
2950	VMXVEXITINFO ExitInfo;
2951	RT_ZERO(ExitInfo);
2952	ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2953	ExitInfo.cbInstr = cbInstr;
2954	ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2955	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2956	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2957	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2958	}
2959
2960	/*
2961	* If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2962	* must not be modified the instruction.
2963	*
2964	* See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2965	*/
2966	uint64_t uGuestCrX;
2967	uint64_t fGstHostMask;
2968	if (iCrReg == 0)
2969	{
2970	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2971	uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2972	fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2973	}
2974	else
2975	{
2976	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2977	uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2978	fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2979	}
2980
2981	puNewCrX = (uGuestCrX & fGstHostMask) \| (puNewCrX & ~fGstHostMask);
2982	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2983	}
2984
2985
2986	/**
2987	* VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2988	*
2989	* @returns VBox strict status code.
2990	* @param pVCpu The cross context virtual CPU structure.
2991	* @param iGReg The general register to which the CR3 value is being stored.
2992	* @param cbInstr The instruction length in bytes.
2993	*/
2994	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
2995	{
2996	Assert(iGReg < X86_GREG_COUNT);
2997	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
2998
2999	/*
3000	* If the CR3-store exiting control is set, we must cause a VM-exit.
3001	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3002	*/
3003	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3004	{
3005	Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3006
3007	VMXVEXITINFO ExitInfo;
3008	RT_ZERO(ExitInfo);
3009	ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3010	ExitInfo.cbInstr = cbInstr;
3011	ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3012	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3013	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3014	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3015	}
3016
3017	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3018	}
3019
3020
3021	/**
3022	* VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3023	*
3024	* @returns VBox strict status code.
3025	* @param pVCpu The cross context virtual CPU structure.
3026	* @param uNewCr3 The new CR3 value.
3027	* @param iGReg The general register from which the CR3 value is being
3028	* loaded.
3029	* @param cbInstr The instruction length in bytes.
3030	*/
3031	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3032	{
3033	Assert(iGReg < X86_GREG_COUNT);
3034
3035	/*
3036	* If the CR3-load exiting control is set and the new CR3 value does not
3037	* match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3038	*
3039	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3040	*/
3041	if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3042	{
3043	Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3044
3045	VMXVEXITINFO ExitInfo;
3046	RT_ZERO(ExitInfo);
3047	ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3048	ExitInfo.cbInstr = cbInstr;
3049	ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3050	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3051	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3052	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3053	}
3054
3055	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3056	}
3057
3058
3059	/**
3060	* VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3061	*
3062	* @returns VBox strict status code.
3063	* @param pVCpu The cross context virtual CPU structure.
3064	* @param iGReg The general register to which the CR8 value is being stored.
3065	* @param cbInstr The instruction length in bytes.
3066	*/
3067	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3068	{
3069	Assert(iGReg < X86_GREG_COUNT);
3070
3071	/*
3072	* If the CR8-store exiting control is set, we must cause a VM-exit.
3073	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3074	*/
3075	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3076	{
3077	Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3078
3079	VMXVEXITINFO ExitInfo;
3080	RT_ZERO(ExitInfo);
3081	ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3082	ExitInfo.cbInstr = cbInstr;
3083	ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3084	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3085	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3086	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3087	}
3088
3089	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3090	}
3091
3092
3093	/**
3094	* VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3095	*
3096	* @returns VBox strict status code.
3097	* @param pVCpu The cross context virtual CPU structure.
3098	* @param iGReg The general register from which the CR8 value is being
3099	* loaded.
3100	* @param cbInstr The instruction length in bytes.
3101	*/
3102	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3103	{
3104	Assert(iGReg < X86_GREG_COUNT);
3105
3106	/*
3107	* If the CR8-load exiting control is set, we must cause a VM-exit.
3108	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3109	*/
3110	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3111	{
3112	Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3113
3114	VMXVEXITINFO ExitInfo;
3115	RT_ZERO(ExitInfo);
3116	ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3117	ExitInfo.cbInstr = cbInstr;
3118	ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3119	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3120	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3121	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3122	}
3123
3124	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3125	}
3126
3127
3128	/**
3129	* VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3130	* GReg,DRx' (DRx read).
3131	*
3132	* @returns VBox strict status code.
3133	* @param pVCpu The cross context virtual CPU structure.
3134	* @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3135	* VMXINSTRID_MOV_FROM_DRX).
3136	* @param iDrReg The debug register being accessed.
3137	* @param iGReg The general register to/from which the DRx value is being
3138	* store/loaded.
3139	* @param cbInstr The instruction length in bytes.
3140	*/
3141	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3142	uint8_t cbInstr)
3143	{
3144	Assert(iDrReg <= 7);
3145	Assert(uInstrId == VMXINSTRID_MOV_TO_DRX \|\| uInstrId == VMXINSTRID_MOV_FROM_DRX);
3146	Assert(iGReg < X86_GREG_COUNT);
3147
3148	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3149	{
3150	uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3151	: VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3152	VMXVEXITINFO ExitInfo;
3153	RT_ZERO(ExitInfo);
3154	ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3155	ExitInfo.cbInstr = cbInstr;
3156	ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3157	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3158	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3159	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3160	}
3161
3162	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3163	}
3164
3165
3166	/**
3167	* VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3168	*
3169	* @returns VBox strict status code.
3170	* @param pVCpu The cross context virtual CPU structure.
3171	* @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3172	* VMXINSTRID_IO_OUT).
3173	* @param u16Port The I/O port being accessed.
3174	* @param fImm Whether the I/O port was encoded using an immediate operand
3175	* or the implicit DX register.
3176	* @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3177	* @param cbInstr The instruction length in bytes.
3178	*/
3179	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3180	uint8_t cbInstr)
3181	{
3182	Assert(uInstrId == VMXINSTRID_IO_IN \|\| uInstrId == VMXINSTRID_IO_OUT);
3183	Assert(cbAccess == 1 \|\| cbAccess == 2 \|\| cbAccess == 4);
3184
3185	bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3186	if (fIntercept)
3187	{
3188	uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3189	: VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3190	VMXVEXITINFO ExitInfo;
3191	RT_ZERO(ExitInfo);
3192	ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3193	ExitInfo.cbInstr = cbInstr;
3194	ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3195	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3196	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3197	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3198	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3199	}
3200
3201	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3202	}
3203
3204
3205	/**
3206	* VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3207	*
3208	* @returns VBox strict status code.
3209	* @param pVCpu The cross context virtual CPU structure.
3210	* @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3211	* VMXINSTRID_IO_OUTS).
3212	* @param u16Port The I/O port being accessed.
3213	* @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3214	* @param fRep Whether the instruction has a REP prefix or not.
3215	* @param ExitInstrInfo The VM-exit instruction info. field.
3216	* @param cbInstr The instruction length in bytes.
3217	*/
3218	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3219	VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3220	{
3221	Assert(uInstrId == VMXINSTRID_IO_INS \|\| uInstrId == VMXINSTRID_IO_OUTS);
3222	Assert(cbAccess == 1 \|\| cbAccess == 2 \|\| cbAccess == 4);
3223	Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3224	Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 \|\| ExitInstrInfo.StrIo.u3AddrSize == 1 \|\| ExitInstrInfo.StrIo.u3AddrSize == 2);
3225	Assert(uInstrId != VMXINSTRID_IO_INS \|\| ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3226
3227	bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3228	if (fIntercept)
3229	{
3230	/*
3231	* Figure out the guest-linear address and the direction bit (INS/OUTS).
3232	*/
3233	/** @todo r=ramshankar: Is there something in IEM that already does this? */
3234	static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3235	uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3236	uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3237	uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3238
3239	uint32_t uDirection;
3240	uint64_t uGuestLinearAddr;
3241	if (uInstrId == VMXINSTRID_IO_INS)
3242	{
3243	uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3244	uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3245	}
3246	else
3247	{
3248	uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3249	uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3250	}
3251
3252	/*
3253	* If the segment is unusable, the guest-linear address in undefined.
3254	* We shall clear it for consistency.
3255	*
3256	* See Intel spec. 27.2.1 "Basic VM-Exit Information".
3257	*/
3258	if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3259	uGuestLinearAddr = 0;
3260
3261	VMXVEXITINFO ExitInfo;
3262	RT_ZERO(ExitInfo);
3263	ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3264	ExitInfo.cbInstr = cbInstr;
3265	ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3266	ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3267	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3268	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3269	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3270	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3271	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3272	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3273	ExitInfo.InstrInfo = ExitInstrInfo;
3274	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3275	}
3276
3277	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3278	}
3279
3280
3281	/**
3282	* VMX VM-exit handler for VM-exits due to MWAIT.
3283	*
3284	* @returns VBox strict status code.
3285	* @param pVCpu The cross context virtual CPU structure.
3286	* @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3287	* @param cbInstr The instruction length in bytes.
3288	*/
3289	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3290	{
3291	VMXVEXITINFO ExitInfo;
3292	RT_ZERO(ExitInfo);
3293	ExitInfo.uReason = VMX_EXIT_MWAIT;
3294	ExitInfo.cbInstr = cbInstr;
3295	ExitInfo.u64Qual = fMonitorHwArmed;
3296	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3297	}
3298
3299
3300	/**
3301	* VMX VM-exit handler for VM-exits due to PAUSE.
3302	*
3303	* @returns VBox strict status code.
3304	* @param pVCpu The cross context virtual CPU structure.
3305	* @param cbInstr The instruction length in bytes.
3306	*/
3307	IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3308	{
3309	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3310
3311	/*
3312	* The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3313	* "PAUSE-loop exiting" control.
3314	*
3315	* The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3316	* the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3317	* of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3318	* a VM-exit.
3319	*
3320	* See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3321	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3322	*/
3323	bool fIntercept = false;
3324	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3325	fIntercept = true;
3326	else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3327	&& pVCpu->iem.s.uCpl == 0)
3328	{
3329	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3330
3331	/*
3332	* A previous-PAUSE-tick value of 0 is used to identify the first time
3333	* execution of a PAUSE instruction after VM-entry at CPL 0. We must
3334	* consider this to be the first execution of PAUSE in a loop according
3335	* to the Intel.
3336	*
3337	* All subsequent records for the previous-PAUSE-tick we ensure that it
3338	* cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3339	*/
3340	uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3341	uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3342	uint64_t const uTick = TMCpuTickGet(pVCpu);
3343	uint32_t const uPleGap = pVmcs->u32PleGap;
3344	uint32_t const uPleWindow = pVmcs->u32PleWindow;
3345	if ( *puPrevPauseTick == 0
3346	\|\| uTick - *puPrevPauseTick > uPleGap)
3347	*puFirstPauseLoopTick = uTick;
3348	else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3349	fIntercept = true;
3350
3351	*puPrevPauseTick = uTick \| 1;
3352	}
3353
3354	if (fIntercept)
3355	return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3356
3357	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3358	}
3359
3360
3361	/**
3362	* VMX VM-exit handler for VM-exits due to task switches.
3363	*
3364	* @returns VBox strict status code.
3365	* @param pVCpu The cross context virtual CPU structure.
3366	* @param enmTaskSwitch The cause of the task switch.
3367	* @param SelNewTss The selector of the new TSS.
3368	* @param cbInstr The instruction length in bytes.
3369	*/
3370	IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3371	{
3372	/*
3373	* Task-switch VM-exits are unconditional and provide the Exit qualification.
3374	*
3375	* If the cause of the task switch is due to execution of CALL, IRET or the JMP
3376	* instruction or delivery of the exception generated by one of these instructions
3377	* lead to a task switch through a task gate in the IDT, we need to provide the
3378	* VM-exit instruction length. Any other means of invoking a task switch VM-exit
3379	* leaves the VM-exit instruction length field undefined.
3380	*
3381	* See Intel spec. 25.2 "Other Causes Of VM Exits".
3382	* See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3383	*/
3384	Assert(cbInstr <= 15);
3385
3386	uint8_t uType;
3387	switch (enmTaskSwitch)
3388	{
3389	case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3390	case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3391	case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3392	case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3393	IEM_NOT_REACHED_DEFAULT_CASE_RET();
3394	}
3395
3396	uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3397	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3398	iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3399	return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3400	}
3401
3402
3403	/**
3404	* VMX VM-exit handler for trap-like VM-exits.
3405	*
3406	* @returns VBox strict status code.
3407	* @param pVCpu The cross context virtual CPU structure.
3408	* @param pExitInfo Pointer to the VM-exit information.
3409	* @param pExitEventInfo Pointer to the VM-exit event information.
3410	*/
3411	IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3412	{
3413	Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3414	iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3415	return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3416	}
3417
3418
3419	/**
3420	* VMX VM-exit handler for VM-exits due to task switches.
3421	*
3422	* This is intended for task switches where the caller provides all the relevant
3423	* VM-exit information.
3424	*
3425	* @returns VBox strict status code.
3426	* @param pVCpu The cross context virtual CPU structure.
3427	* @param pExitInfo Pointer to the VM-exit information.
3428	* @param pExitEventInfo Pointer to the VM-exit event information.
3429	*/
3430	IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3431	PCVMXVEXITEVENTINFO pExitEventInfo)
3432	{
3433	Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3434	iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3435	iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3436	iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3437	return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3438	}
3439
3440
3441	/**
3442	* VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3443	*
3444	* @returns VBox strict status code.
3445	* @param pVCpu The cross context virtual CPU structure.
3446	*/
3447	IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3448	{
3449	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3450	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3451
3452	/* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3453	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3454
3455	/* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3456	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3457	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3458
3459	/* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3460	return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3461	}
3462
3463
3464	/**
3465	* VMX VM-exit handler for VM-exits due to external interrupts.
3466	*
3467	* @returns VBox strict status code.
3468	* @param pVCpu The cross context virtual CPU structure.
3469	* @param uVector The external interrupt vector (pass 0 if the interrupt
3470	* is still pending since we typically won't know the
3471	* vector).
3472	* @param fIntPending Whether the external interrupt is pending or
3473	* acknowledged in the interrupt controller.
3474	*/
3475	IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3476	{
3477	Assert(!fIntPending \|\| uVector == 0);
3478
3479	/* The VM-exit is subject to "External interrupt exiting" being set. */
3480	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3481	{
3482	if (fIntPending)
3483	{
3484	/*
3485	* If the interrupt is pending and we don't need to acknowledge the
3486	* interrupt on VM-exit, cause the VM-exit immediately.
3487	*
3488	* See Intel spec 25.2 "Other Causes Of VM Exits".
3489	*/
3490	if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3491	return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3492
3493	/*
3494	* If the interrupt is pending and we -do- need to acknowledge the interrupt
3495	* on VM-exit, postpone VM-exit till after the interrupt controller has been
3496	* acknowledged that the interrupt has been consumed. Callers would have to call
3497	* us again after getting the vector (and ofc, with fIntPending with false).
3498	*/
3499	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3500	}
3501
3502	/*
3503	* If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3504	* "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3505	* all set, we need to record the vector of the external interrupt in the
3506	* VM-exit interruption information field. Otherwise, mark this field as invalid.
3507	*
3508	* See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3509	*/
3510	uint32_t uExitIntInfo;
3511	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3512	{
3513	bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3514	uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3515	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3516	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3517	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3518	}
3519	else
3520	uExitIntInfo = 0;
3521	iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3522
3523	/*
3524	* Cause the VM-exit whether or not the vector has been stored
3525	* in the VM-exit interruption-information field.
3526	*/
3527	return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3528	}
3529
3530	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3531	}
3532
3533
3534	/**
3535	* VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3536	* an event.
3537	*
3538	* @returns VBox strict status code.
3539	* @param pVCpu The cross context virtual CPU structure.
3540	*/
3541	IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3542	{
3543	uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3544	if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3545	{
3546	/*
3547	* The NMI-unblocking due to IRET field need not be set for double faults.
3548	* See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3549	*/
3550	uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3551	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3552	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3553	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3554	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3555	iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3556	return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3557	}
3558
3559	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3560	}
3561
3562
3563	/**
3564	* VMX VM-exit handler for VM-exit due to delivery of an events.
3565	*
3566	* This is intended for VM-exit due to exceptions or NMIs where the caller provides
3567	* all the relevant VM-exit information.
3568	*
3569	* @returns VBox strict status code.
3570	* @param pVCpu The cross context virtual CPU structure.
3571	* @param pExitInfo Pointer to the VM-exit information.
3572	* @param pExitEventInfo Pointer to the VM-exit event information.
3573	*/
3574	IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3575	{
3576	Assert(pExitInfo);
3577	Assert(pExitEventInfo);
3578	Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3579	Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3580
3581	iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3582	iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3583	iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3584	iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3585	iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3586	return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3587	}
3588
3589
3590	/**
3591	* VMX VM-exit handler for VM-exits due to delivery of an event.
3592	*
3593	* @returns VBox strict status code.
3594	* @param pVCpu The cross context virtual CPU structure.
3595	* @param uVector The interrupt / exception vector.
3596	* @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3597	* @param uErrCode The error code associated with the event.
3598	* @param uCr2 The CR2 value in case of a \#PF exception.
3599	* @param cbInstr The instruction length in bytes.
3600	*/
3601	IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3602	uint8_t cbInstr)
3603	{
3604	/*
3605	* If the event is being injected as part of VM-entry, it is -not- subject to event
3606	* intercepts in the nested-guest. However, secondary exceptions that occur during
3607	* injection of any event -are- subject to event interception.
3608	*
3609	* See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3610	*/
3611	if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3612	{
3613	/*
3614	* If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3615	* virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3616	*
3617	* See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3618	*/
3619	if ( uVector == X86_XCPT_NMI
3620	&& (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3621	&& (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3622	pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3623	else
3624	Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3625
3626	CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3627	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3628	}
3629
3630	/*
3631	* We are injecting an external interrupt, check if we need to cause a VM-exit now.
3632	* If not, the caller will continue delivery of the external interrupt as it would
3633	* normally. The interrupt is no longer pending in the interrupt controller at this
3634	* point.
3635	*/
3636	if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3637	{
3638	Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3639	return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3640	}
3641
3642	/*
3643	* Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3644	* and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3645	* interrupts.
3646	*/
3647	Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_T_SOFT_INT));
3648	bool fIntercept;
3649	if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3650	\|\| (fFlags & (IEM_XCPT_FLAGS_BP_INSTR \| IEM_XCPT_FLAGS_OF_INSTR \| IEM_XCPT_FLAGS_ICEBP_INSTR)))
3651	fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3652	else
3653	{
3654	/* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3655	fIntercept = false;
3656	}
3657
3658	/*
3659	* Now that we've determined whether the event causes a VM-exit, we need to construct the
3660	* relevant VM-exit information and cause the VM-exit.
3661	*/
3662	if (fIntercept)
3663	{
3664	Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3665
3666	/* Construct the rest of the event related information fields and cause the VM-exit. */
3667	uint64_t u64ExitQual;
3668	if (uVector == X86_XCPT_PF)
3669	{
3670	Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3671	u64ExitQual = uCr2;
3672	}
3673	else if (uVector == X86_XCPT_DB)
3674	{
3675	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3676	u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3677	}
3678	else
3679	u64ExitQual = 0;
3680
3681	uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3682	bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3683	uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3684	uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3685	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3686	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3687	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3688	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3689	iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3690	iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3691
3692	/*
3693	* For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3694	* software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3695	* length.
3696	*/
3697	if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3698	\|\| (fFlags & (IEM_XCPT_FLAGS_BP_INSTR \| IEM_XCPT_FLAGS_OF_INSTR \| IEM_XCPT_FLAGS_ICEBP_INSTR)))
3699	iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3700	else
3701	iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3702
3703	return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3704	}
3705
3706	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3707	}
3708
3709
3710	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3711	/**
3712	* VMX VM-exit handler for EPT violation.
3713	*
3714	* @param pVCpu The cross context virtual CPU structure.
3715	* @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3716	* @param fEptAccess The EPT paging structure bits.
3717	* @param GCPhysAddr The physical address causing the EPT violation.
3718	* @param GCPtrAddr The linear address causing the EPT violation.
3719	* @param cbInstr The VM-exit instruction length.
3720	*/
3721	IEM_STATIC VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint64_t fEptAccess, RTGCPHYS GCPhysAddr,
3722	uint64_t GCPtrAddr, bool fLinearAddrValid, uint8_t cbInstr)
3723	{
3724	/*
3725	* If the linear address isn't valid (can happen when loading PDPTEs
3726	* as part of MOV CR execution) the linear address field is undefined.
3727	* While we can leave it this way, it's preferrable to zero it for consistency.
3728	*/
3729	Assert(fLinearAddrValid \|\| GCPtrAddr == 0);
3730
3731	uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3732	uint8_t const fSupportsAccessDirty = fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY;
3733
3734	uint8_t const fDataRead = ((fAccess & IEM_ACCESS_DATA_R) == IEM_ACCESS_DATA_R) \| fSupportsAccessDirty;
3735	uint8_t const fDataWrite = ((fAccess & IEM_ACCESS_DATA_RW) == IEM_ACCESS_DATA_RW) \| fSupportsAccessDirty;
3736	uint8_t const fInstrFetch = (fAccess & IEM_ACCESS_INSTRUCTION) == IEM_ACCESS_INSTRUCTION;
3737	bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3738	bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3739	bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3740	bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3741
3742	uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
3743	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
3744	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
3745	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
3746	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
3747	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
3748	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fLinearAddrValid)
3749	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
3750
3751	/** @todo bit 8 of Exit Qualification!
3752	* If the access causing the EPT violation is to a guest-physical address that is
3753	* the translation of a linear address.
3754	* - OR -
3755	* if the access causing the EPT violation is to a paging-structure entry as part
3756	* of a page walk or the update of an accessed or dirty bit.
3757	*
3758	* Caller needs to be able to distinguish this... */
3759
3760	#ifdef VBOX_STRICT
3761	uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
3762	uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
3763	Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
3764	Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
3765	Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3766	Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3767	Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
3768	#endif
3769
3770	iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3771	iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
3772	iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3773
3774	return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
3775	}
3776	#endif
3777
3778
3779	/**
3780	* VMX VM-exit handler for APIC accesses.
3781	*
3782	* @param pVCpu The cross context virtual CPU structure.
3783	* @param offAccess The offset of the register being accessed.
3784	* @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3785	* IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3786	*/
3787	IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3788	{
3789	Assert((fAccess & IEM_ACCESS_TYPE_READ) \|\| (fAccess & IEM_ACCESS_TYPE_WRITE) \|\| (fAccess & IEM_ACCESS_INSTRUCTION));
3790
3791	VMXAPICACCESS enmAccess;
3792	bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3793	if (fInEventDelivery)
3794	enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3795	else if (fAccess & IEM_ACCESS_INSTRUCTION)
3796	enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3797	else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3798	enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3799	else
3800	enmAccess = VMXAPICACCESS_LINEAR_READ;
3801
3802	uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3803	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3804	return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3805	}
3806
3807
3808	/**
3809	* VMX VM-exit handler for APIC accesses.
3810	*
3811	* This is intended for APIC accesses where the caller provides all the
3812	* relevant VM-exit information.
3813	*
3814	* @returns VBox strict status code.
3815	* @param pVCpu The cross context virtual CPU structure.
3816	* @param pExitInfo Pointer to the VM-exit information.
3817	* @param pExitEventInfo Pointer to the VM-exit event information.
3818	*/
3819	IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3820	PCVMXVEXITEVENTINFO pExitEventInfo)
3821	{
3822	/* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3823	Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3824	Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3825	iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3826	iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3827	iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3828	iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3829	iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3830	return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3831	}
3832
3833
3834	/**
3835	* VMX VM-exit handler for APIC-write VM-exits.
3836	*
3837	* @param pVCpu The cross context virtual CPU structure.
3838	* @param offApic The write to the virtual-APIC page offset that caused this
3839	* VM-exit.
3840	*/
3841	IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3842	{
3843	Assert(offApic < XAPIC_OFF_END + 4);
3844	/* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3845	offApic &= UINT16_C(0xfff);
3846	return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3847	}
3848
3849
3850	/**
3851	* Sets virtual-APIC write emulation as pending.
3852	*
3853	* @param pVCpu The cross context virtual CPU structure.
3854	* @param offApic The offset in the virtual-APIC page that was written.
3855	*/
3856	DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3857	{
3858	Assert(offApic < XAPIC_OFF_END + 4);
3859
3860	/*
3861	* Record the currently updated APIC offset, as we need this later for figuring
3862	* out whether to perform TPR, EOI or self-IPI virtualization as well as well
3863	* as for supplying the exit qualification when causing an APIC-write VM-exit.
3864	*/
3865	pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3866
3867	/*
3868	* Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3869	* virtualization or APIC-write emulation).
3870	*/
3871	if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3872	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3873	}
3874
3875
3876	/**
3877	* Clears any pending virtual-APIC write emulation.
3878	*
3879	* @returns The virtual-APIC offset that was written before clearing it.
3880	* @param pVCpu The cross context virtual CPU structure.
3881	*/
3882	DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3883	{
3884	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3885	uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3886	pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3887	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3888	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3889	return offVirtApicWrite;
3890	}
3891
3892
3893	/**
3894	* Reads a 32-bit register from the virtual-APIC page at the given offset.
3895	*
3896	* @returns The register from the virtual-APIC page.
3897	* @param pVCpu The cross context virtual CPU structure.
3898	* @param offReg The offset of the register being read.
3899	*/
3900	IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3901	{
3902	Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3903
3904	uint32_t uReg = 0;
3905	RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3906	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3907	AssertMsgStmt(RT_SUCCESS(rc),
3908	("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3909	sizeof(uReg), offReg, GCPhysVirtApic, rc),
3910	uReg = 0);
3911	return uReg;
3912	}
3913
3914
3915	/**
3916	* Reads a 64-bit register from the virtual-APIC page at the given offset.
3917	*
3918	* @returns The register from the virtual-APIC page.
3919	* @param pVCpu The cross context virtual CPU structure.
3920	* @param offReg The offset of the register being read.
3921	*/
3922	IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3923	{
3924	Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3925
3926	uint64_t uReg = 0;
3927	RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3928	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3929	AssertMsgStmt(RT_SUCCESS(rc),
3930	("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3931	sizeof(uReg), offReg, GCPhysVirtApic, rc),
3932	uReg = 0);
3933	return uReg;
3934	}
3935
3936
3937	/**
3938	* Writes a 32-bit register to the virtual-APIC page at the given offset.
3939	*
3940	* @param pVCpu The cross context virtual CPU structure.
3941	* @param offReg The offset of the register being written.
3942	* @param uReg The register value to write.
3943	*/
3944	IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3945	{
3946	Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3947
3948	RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3949	int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3950	AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3951	sizeof(uReg), offReg, GCPhysVirtApic, rc));
3952	}
3953
3954
3955	/**
3956	* Writes a 64-bit register to the virtual-APIC page at the given offset.
3957	*
3958	* @param pVCpu The cross context virtual CPU structure.
3959	* @param offReg The offset of the register being written.
3960	* @param uReg The register value to write.
3961	*/
3962	IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3963	{
3964	Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3965
3966	RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3967	int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3968	AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3969	sizeof(uReg), offReg, GCPhysVirtApic, rc));
3970	}
3971
3972
3973	/**
3974	* Sets the vector in a virtual-APIC 256-bit sparse register.
3975	*
3976	* @param pVCpu The cross context virtual CPU structure.
3977	* @param offReg The offset of the 256-bit spare register.
3978	* @param uVector The vector to set.
3979	*
3980	* @remarks This is based on our APIC device code.
3981	*/
3982	IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3983	{
3984	/* Determine the vector offset within the chunk. */
3985	uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3986
3987	/* Read the chunk at the offset. */
3988	uint32_t uReg;
3989	RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3990	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3991	if (RT_SUCCESS(rc))
3992	{
3993	/* Modify the chunk. */
3994	uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3995	uReg \|= RT_BIT(idxVectorBit);
3996
3997	/* Write the chunk. */
3998	rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
3999	AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4000	uVector, offReg, GCPhysVirtApic, rc));
4001	}
4002	else
4003	AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4004	uVector, offReg, GCPhysVirtApic, rc));
4005	}
4006
4007
4008	/**
4009	* Clears the vector in a virtual-APIC 256-bit sparse register.
4010	*
4011	* @param pVCpu The cross context virtual CPU structure.
4012	* @param offReg The offset of the 256-bit spare register.
4013	* @param uVector The vector to clear.
4014	*
4015	* @remarks This is based on our APIC device code.
4016	*/
4017	IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
4018	{
4019	/* Determine the vector offset within the chunk. */
4020	uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4021
4022	/* Read the chunk at the offset. */
4023	uint32_t uReg;
4024	RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4025	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4026	if (RT_SUCCESS(rc))
4027	{
4028	/* Modify the chunk. */
4029	uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4030	uReg &= ~RT_BIT(idxVectorBit);
4031
4032	/* Write the chunk. */
4033	rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4034	AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4035	uVector, offReg, GCPhysVirtApic, rc));
4036	}
4037	else
4038	AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4039	uVector, offReg, GCPhysVirtApic, rc));
4040	}
4041
4042
4043	/**
4044	* Checks if a memory access to the APIC-access page must causes an APIC-access
4045	* VM-exit.
4046	*
4047	* @param pVCpu The cross context virtual CPU structure.
4048	* @param offAccess The offset of the register being accessed.
4049	* @param cbAccess The size of the access in bytes.
4050	* @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4051	* IEM_ACCESS_TYPE_WRITE).
4052	*
4053	* @remarks This must not be used for MSR-based APIC-access page accesses!
4054	* @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4055	*/
4056	IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4057	{
4058	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4059	Assert(fAccess == IEM_ACCESS_TYPE_READ \|\| fAccess == IEM_ACCESS_TYPE_WRITE);
4060
4061	/*
4062	* We must cause a VM-exit if any of the following are true:
4063	* - TPR shadowing isn't active.
4064	* - The access size exceeds 32-bits.
4065	* - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4066	*
4067	* See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4068	* See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4069	*/
4070	if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4071	\|\| cbAccess > sizeof(uint32_t)
4072	\|\| ((offAccess + cbAccess - 1) & 0xc)
4073	\|\| offAccess >= XAPIC_OFF_END + 4)
4074	return true;
4075
4076	/*
4077	* If the access is part of an operation where we have already
4078	* virtualized a virtual-APIC write, we must cause a VM-exit.
4079	*/
4080	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4081	return true;
4082
4083	/*
4084	* Check write accesses to the APIC-access page that cause VM-exits.
4085	*/
4086	if (fAccess & IEM_ACCESS_TYPE_WRITE)
4087	{
4088	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4089	{
4090	/*
4091	* With APIC-register virtualization, a write access to any of the
4092	* following registers are virtualized. Accessing any other register
4093	* causes a VM-exit.
4094	*/
4095	uint16_t const offAlignedAccess = offAccess & 0xfffc;
4096	switch (offAlignedAccess)
4097	{
4098	case XAPIC_OFF_ID:
4099	case XAPIC_OFF_TPR:
4100	case XAPIC_OFF_EOI:
4101	case XAPIC_OFF_LDR:
4102	case XAPIC_OFF_DFR:
4103	case XAPIC_OFF_SVR:
4104	case XAPIC_OFF_ESR:
4105	case XAPIC_OFF_ICR_LO:
4106	case XAPIC_OFF_ICR_HI:
4107	case XAPIC_OFF_LVT_TIMER:
4108	case XAPIC_OFF_LVT_THERMAL:
4109	case XAPIC_OFF_LVT_PERF:
4110	case XAPIC_OFF_LVT_LINT0:
4111	case XAPIC_OFF_LVT_LINT1:
4112	case XAPIC_OFF_LVT_ERROR:
4113	case XAPIC_OFF_TIMER_ICR:
4114	case XAPIC_OFF_TIMER_DCR:
4115	break;
4116	default:
4117	return true;
4118	}
4119	}
4120	else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4121	{
4122	/*
4123	* With virtual-interrupt delivery, a write access to any of the
4124	* following registers are virtualized. Accessing any other register
4125	* causes a VM-exit.
4126	*
4127	* Note! The specification does not allow writing to offsets in-between
4128	* these registers (e.g. TPR + 1 byte) unlike read accesses.
4129	*/
4130	switch (offAccess)
4131	{
4132	case XAPIC_OFF_TPR:
4133	case XAPIC_OFF_EOI:
4134	case XAPIC_OFF_ICR_LO:
4135	break;
4136	default:
4137	return true;
4138	}
4139	}
4140	else
4141	{
4142	/*
4143	* Without APIC-register virtualization or virtual-interrupt delivery,
4144	* only TPR accesses are virtualized.
4145	*/
4146	if (offAccess == XAPIC_OFF_TPR)
4147	{ /* likely */ }
4148	else
4149	return true;
4150	}
4151	}
4152	else
4153	{
4154	/*
4155	* Check read accesses to the APIC-access page that cause VM-exits.
4156	*/
4157	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4158	{
4159	/*
4160	* With APIC-register virtualization, a read access to any of the
4161	* following registers are virtualized. Accessing any other register
4162	* causes a VM-exit.
4163	*/
4164	uint16_t const offAlignedAccess = offAccess & 0xfffc;
4165	switch (offAlignedAccess)
4166	{
4167	/** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4168	case XAPIC_OFF_ID:
4169	case XAPIC_OFF_VERSION:
4170	case XAPIC_OFF_TPR:
4171	case XAPIC_OFF_EOI:
4172	case XAPIC_OFF_LDR:
4173	case XAPIC_OFF_DFR:
4174	case XAPIC_OFF_SVR:
4175	case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4176	case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4177	case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4178	case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4179	case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4180	case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4181	case XAPIC_OFF_ESR:
4182	case XAPIC_OFF_ICR_LO:
4183	case XAPIC_OFF_ICR_HI:
4184	case XAPIC_OFF_LVT_TIMER:
4185	case XAPIC_OFF_LVT_THERMAL:
4186	case XAPIC_OFF_LVT_PERF:
4187	case XAPIC_OFF_LVT_LINT0:
4188	case XAPIC_OFF_LVT_LINT1:
4189	case XAPIC_OFF_LVT_ERROR:
4190	case XAPIC_OFF_TIMER_ICR:
4191	case XAPIC_OFF_TIMER_DCR:
4192	break;
4193	default:
4194	return true;
4195	}
4196	}
4197	else
4198	{
4199	/* Without APIC-register virtualization, only TPR accesses are virtualized. */
4200	if (offAccess == XAPIC_OFF_TPR)
4201	{ /* likely */ }
4202	else
4203	return true;
4204	}
4205	}
4206
4207	/* The APIC access is virtualized, does not cause a VM-exit. */
4208	return false;
4209	}
4210
4211
4212	/**
4213	* Virtualizes a memory-based APIC access where the address is not used to access
4214	* memory.
4215	*
4216	* This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4217	* page-faults but do not use the address to access memory.
4218	*
4219	* @param pVCpu The cross context virtual CPU structure.
4220	* @param pGCPhysAccess Pointer to the guest-physical address used.
4221	*/
4222	IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4223	{
4224	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4225	Assert(pGCPhysAccess);
4226
4227	RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4228	RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4229	Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4230
4231	if (GCPhysAccess == GCPhysApic)
4232	{
4233	uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4234	uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4235	uint16_t const cbAccess = 1;
4236	bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4237	if (fIntercept)
4238	return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4239
4240	*pGCPhysAccess = GCPhysApic \| offAccess;
4241	return VINF_VMX_MODIFIES_BEHAVIOR;
4242	}
4243
4244	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4245	}
4246
4247
4248	/**
4249	* Virtualizes a memory-based APIC access.
4250	*
4251	* @returns VBox strict status code.
4252	* @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4253	* @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4254	*
4255	* @param pVCpu The cross context virtual CPU structure.
4256	* @param offAccess The offset of the register being accessed (within the
4257	* APIC-access page).
4258	* @param cbAccess The size of the access in bytes.
4259	* @param pvData Pointer to the data being written or where to store the data
4260	* being read.
4261	* @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4262	* IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4263	*/
4264	IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4265	uint32_t fAccess)
4266	{
4267	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4268	Assert(pvData);
4269	Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4270	\|\| (fAccess & IEM_ACCESS_TYPE_WRITE)
4271	\|\| (fAccess & IEM_ACCESS_INSTRUCTION));
4272
4273	bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4274	if (fIntercept)
4275	return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4276
4277	if (fAccess & IEM_ACCESS_TYPE_WRITE)
4278	{
4279	/*
4280	* A write access to the APIC-access page that is virtualized (rather than
4281	* causing a VM-exit) writes data to the virtual-APIC page.
4282	*/
4283	uint32_t const u32Data = (uint32_t )pvData;
4284	iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4285
4286	/*
4287	* Record the currently updated APIC offset, as we need this later for figuring
4288	* out whether to perform TPR, EOI or self-IPI virtualization as well as well
4289	* as for supplying the exit qualification when causing an APIC-write VM-exit.
4290	*
4291	* After completion of the current operation, we need to perform TPR virtualization,
4292	* EOI virtualization or APIC-write VM-exit depending on which register was written.
4293	*
4294	* The current operation may be a REP-prefixed string instruction, execution of any
4295	* other instruction, or delivery of an event through the IDT.
4296	*
4297	* Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4298	* performed now but later after completion of the current operation.
4299	*
4300	* See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4301	*/
4302	iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4303	}
4304	else
4305	{
4306	/*
4307	* A read access from the APIC-access page that is virtualized (rather than
4308	* causing a VM-exit) returns data from the virtual-APIC page.
4309	*
4310	* See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4311	*/
4312	Assert(cbAccess <= 4);
4313	Assert(offAccess < XAPIC_OFF_END + 4);
4314	static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4315
4316	uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4317	u32Data &= s_auAccessSizeMasks[cbAccess];
4318	(uint32_t )pvData = u32Data;
4319	}
4320
4321	return VINF_VMX_MODIFIES_BEHAVIOR;
4322	}
4323
4324
4325	/**
4326	* Virtualizes an MSR-based APIC read access.
4327	*
4328	* @returns VBox strict status code.
4329	* @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4330	* @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4331	* handled by the x2APIC device.
4332	* @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4333	* not within the range of valid MSRs, caller must raise \#GP(0).
4334	* @param pVCpu The cross context virtual CPU structure.
4335	* @param idMsr The x2APIC MSR being read.
4336	* @param pu64Value Where to store the read x2APIC MSR value (only valid when
4337	* VINF_VMX_MODIFIES_BEHAVIOR is returned).
4338	*/
4339	IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4340	{
4341	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4342	Assert(pu64Value);
4343
4344	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4345	{
4346	if ( idMsr >= MSR_IA32_X2APIC_START
4347	&& idMsr <= MSR_IA32_X2APIC_END)
4348	{
4349	uint16_t const offReg = (idMsr & 0xff) << 4;
4350	uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4351	*pu64Value = u64Value;
4352	return VINF_VMX_MODIFIES_BEHAVIOR;
4353	}
4354	return VERR_OUT_OF_RANGE;
4355	}
4356
4357	if (idMsr == MSR_IA32_X2APIC_TPR)
4358	{
4359	uint16_t const offReg = (idMsr & 0xff) << 4;
4360	uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4361	*pu64Value = u64Value;
4362	return VINF_VMX_MODIFIES_BEHAVIOR;
4363	}
4364
4365	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4366	}
4367
4368
4369	/**
4370	* Virtualizes an MSR-based APIC write access.
4371	*
4372	* @returns VBox strict status code.
4373	* @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4374	* @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4375	* not within the range of valid MSRs, caller must raise \#GP(0).
4376	* @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4377	*
4378	* @param pVCpu The cross context virtual CPU structure.
4379	* @param idMsr The x2APIC MSR being written.
4380	* @param u64Value The value of the x2APIC MSR being written.
4381	*/
4382	IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4383	{
4384	/*
4385	* Check if the access is to be virtualized.
4386	* See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4387	*/
4388	if ( idMsr == MSR_IA32_X2APIC_TPR
4389	\|\| ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4390	&& ( idMsr == MSR_IA32_X2APIC_EOI
4391	\|\| idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4392	{
4393	/* Validate the MSR write depending on the register. */
4394	switch (idMsr)
4395	{
4396	case MSR_IA32_X2APIC_TPR:
4397	case MSR_IA32_X2APIC_SELF_IPI:
4398	{
4399	if (u64Value & UINT64_C(0xffffffffffffff00))
4400	return VERR_OUT_OF_RANGE;
4401	break;
4402	}
4403	case MSR_IA32_X2APIC_EOI:
4404	{
4405	if (u64Value != 0)
4406	return VERR_OUT_OF_RANGE;
4407	break;
4408	}
4409	}
4410
4411	/* Write the MSR to the virtual-APIC page. */
4412	uint16_t const offReg = (idMsr & 0xff) << 4;
4413	iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4414
4415	/*
4416	* Record the currently updated APIC offset, as we need this later for figuring
4417	* out whether to perform TPR, EOI or self-IPI virtualization as well as well
4418	* as for supplying the exit qualification when causing an APIC-write VM-exit.
4419	*/
4420	iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4421
4422	return VINF_VMX_MODIFIES_BEHAVIOR;
4423	}
4424
4425	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4426	}
4427
4428
4429	/**
4430	* Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4431	*
4432	* @returns VBox status code.
4433	* @retval VINF_SUCCESS when the highest set bit is found.
4434	* @retval VERR_NOT_FOUND when no bit is set.
4435	*
4436	* @param pVCpu The cross context virtual CPU structure.
4437	* @param offReg The offset of the APIC 256-bit sparse register.
4438	* @param pidxHighestBit Where to store the highest bit (most significant bit)
4439	* set in the register. Only valid when VINF_SUCCESS is
4440	* returned.
4441	*
4442	* @remarks The format of the 256-bit sparse register here mirrors that found in
4443	* real APIC hardware.
4444	*/
4445	static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4446	{
4447	Assert(offReg < XAPIC_OFF_END + 4);
4448	Assert(pidxHighestBit);
4449
4450	/*
4451	* There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4452	* However, in each fragment only the first 4 bytes are used.
4453	*/
4454	uint8_t const cFrags = 8;
4455	for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4456	{
4457	uint16_t const offFrag = iFrag * 16;
4458	uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4459	if (!u32Frag)
4460	continue;
4461
4462	unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4463	Assert(idxHighestBit > 0);
4464	--idxHighestBit;
4465	Assert(idxHighestBit <= UINT8_MAX);
4466	*pidxHighestBit = idxHighestBit;
4467	return VINF_SUCCESS;
4468	}
4469	return VERR_NOT_FOUND;
4470	}
4471
4472
4473	/**
4474	* Evaluates pending virtual interrupts.
4475	*
4476	* @param pVCpu The cross context virtual CPU structure.
4477	*/
4478	IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4479	{
4480	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4481
4482	if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4483	{
4484	uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4485	uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4486
4487	if ((uRvi >> 4) > (uPpr >> 4))
4488	{
4489	Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4490	VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4491	}
4492	else
4493	Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4494	}
4495	}
4496
4497
4498	/**
4499	* Performs PPR virtualization.
4500	*
4501	* @returns VBox strict status code.
4502	* @param pVCpu The cross context virtual CPU structure.
4503	*/
4504	IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4505	{
4506	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4507	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4508
4509	/*
4510	* PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4511	* or EOI-virtualization.
4512	*
4513	* See Intel spec. 29.1.3 "PPR Virtualization".
4514	*/
4515	uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4516	uint32_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4517
4518	uint32_t uPpr;
4519	if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4520	uPpr = uTpr & 0xff;
4521	else
4522	uPpr = uSvi & 0xf0;
4523
4524	Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4525	iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4526	}
4527
4528
4529	/**
4530	* Performs VMX TPR virtualization.
4531	*
4532	* @returns VBox strict status code.
4533	* @param pVCpu The cross context virtual CPU structure.
4534	*/
4535	IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4536	{
4537	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4538
4539	/*
4540	* We should have already performed the virtual-APIC write to the TPR offset
4541	* in the virtual-APIC page. We now perform TPR virtualization.
4542	*
4543	* See Intel spec. 29.1.2 "TPR Virtualization".
4544	*/
4545	if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4546	{
4547	uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4548	uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4549
4550	/*
4551	* If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4552	* See Intel spec. 29.1.2 "TPR Virtualization".
4553	*/
4554	if (((uTpr >> 4) & 0xf) < uTprThreshold)
4555	{
4556	Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4557	return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4558	}
4559	}
4560	else
4561	{
4562	iemVmxPprVirtualization(pVCpu);
4563	iemVmxEvalPendingVirtIntrs(pVCpu);
4564	}
4565
4566	return VINF_SUCCESS;
4567	}
4568
4569
4570	/**
4571	* Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4572	* not.
4573	*
4574	* @returns @c true if the EOI write is intercepted, @c false otherwise.
4575	* @param pVCpu The cross context virtual CPU structure.
4576	* @param uVector The interrupt that was acknowledged using an EOI.
4577	*/
4578	IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4579	{
4580	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4581	Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4582
4583	if (uVector < 64)
4584	return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4585	if (uVector < 128)
4586	return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4587	if (uVector < 192)
4588	return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4589	return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4590	}
4591
4592
4593	/**
4594	* Performs EOI virtualization.
4595	*
4596	* @returns VBox strict status code.
4597	* @param pVCpu The cross context virtual CPU structure.
4598	*/
4599	IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4600	{
4601	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4602	Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4603
4604	/*
4605	* Clear the interrupt guest-interrupt as no longer in-service (ISR)
4606	* and get the next guest-interrupt that's in-service (if any).
4607	*
4608	* See Intel spec. 29.1.4 "EOI Virtualization".
4609	*/
4610	uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4611	uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4612	Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4613
4614	uint8_t uVector = uSvi;
4615	iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4616
4617	uVector = 0;
4618	iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4619
4620	if (uVector)
4621	Log2(("eoi_virt: next interrupt %#x\n", uVector));
4622	else
4623	Log2(("eoi_virt: no interrupt pending in ISR\n"));
4624
4625	/* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4626	pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4627
4628	iemVmxPprVirtualization(pVCpu);
4629	if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4630	return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4631	iemVmxEvalPendingVirtIntrs(pVCpu);
4632	return VINF_SUCCESS;
4633	}
4634
4635
4636	/**
4637	* Performs self-IPI virtualization.
4638	*
4639	* @returns VBox strict status code.
4640	* @param pVCpu The cross context virtual CPU structure.
4641	*/
4642	IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4643	{
4644	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4645	Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4646
4647	/*
4648	* We should have already performed the virtual-APIC write to the self-IPI offset
4649	* in the virtual-APIC page. We now perform self-IPI virtualization.
4650	*
4651	* See Intel spec. 29.1.5 "Self-IPI Virtualization".
4652	*/
4653	uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4654	Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4655	iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4656	uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4657	uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4658	if (uVector > uRvi)
4659	pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4660	iemVmxEvalPendingVirtIntrs(pVCpu);
4661	return VINF_SUCCESS;
4662	}
4663
4664
4665	/**
4666	* Performs VMX APIC-write emulation.
4667	*
4668	* @returns VBox strict status code.
4669	* @param pVCpu The cross context virtual CPU structure.
4670	*/
4671	IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4672	{
4673	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4674
4675	/* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4676	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4677
4678	/*
4679	* Perform APIC-write emulation based on the virtual-APIC register written.
4680	* See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4681	*/
4682	uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4683	VBOXSTRICTRC rcStrict;
4684	switch (offApicWrite)
4685	{
4686	case XAPIC_OFF_TPR:
4687	{
4688	/* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4689	uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4690	uTpr &= UINT32_C(0x000000ff);
4691	iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4692	Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4693	rcStrict = iemVmxTprVirtualization(pVCpu);
4694	break;
4695	}
4696
4697	case XAPIC_OFF_EOI:
4698	{
4699	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4700	{
4701	/* Clear VEOI and perform EOI virtualization. */
4702	iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4703	Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4704	rcStrict = iemVmxEoiVirtualization(pVCpu);
4705	}
4706	else
4707	rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4708	break;
4709	}
4710
4711	case XAPIC_OFF_ICR_LO:
4712	{
4713	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4714	{
4715	/* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4716	uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4717	uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4718	uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4719	if ( !(uIcrLo & fIcrLoMb0)
4720	&& (uIcrLo & fIcrLoMb1))
4721	{
4722	Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4723	rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4724	}
4725	else
4726	rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4727	}
4728	else
4729	rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4730	break;
4731	}
4732
4733	case XAPIC_OFF_ICR_HI:
4734	{
4735	/* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4736	uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4737	uIcrHi &= UINT32_C(0xff000000);
4738	iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4739	rcStrict = VINF_SUCCESS;
4740	break;
4741	}
4742
4743	default:
4744	{
4745	/* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4746	rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4747	break;
4748	}
4749	}
4750
4751	return rcStrict;
4752	}
4753
4754
4755	/**
4756	* Checks guest control registers, debug registers and MSRs as part of VM-entry.
4757	*
4758	* @param pVCpu The cross context virtual CPU structure.
4759	* @param pszInstr The VMX instruction name (for logging purposes).
4760	*/
4761	DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4762	{
4763	/*
4764	* Guest Control Registers, Debug Registers, and MSRs.
4765	* See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4766	*/
4767	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4768	const char * const pszFailure = "VM-exit";
4769	bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4770
4771	/* CR0 reserved bits. */
4772	{
4773	/* CR0 MB1 bits. */
4774	uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4775	Assert(!(u64Cr0Fixed0 & (X86_CR0_NW \| X86_CR0_CD)));
4776	if (fUnrestrictedGuest)
4777	u64Cr0Fixed0 &= ~(X86_CR0_PE \| X86_CR0_PG);
4778	if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4779	{ /* likely */ }
4780	else
4781	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4782
4783	/* CR0 MBZ bits. */
4784	uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4785	if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4786	{ /* likely */ }
4787	else
4788	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4789
4790	/* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4791	if ( !fUnrestrictedGuest
4792	&& (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4793	&& !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4794	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4795	}
4796
4797	/* CR4 reserved bits. */
4798	{
4799	/* CR4 MB1 bits. */
4800	uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4801	if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4802	{ /* likely */ }
4803	else
4804	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4805
4806	/* CR4 MBZ bits. */
4807	uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4808	if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4809	{ /* likely */ }
4810	else
4811	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4812	}
4813
4814	/* DEBUGCTL MSR. */
4815	if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4816	\|\| !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4817	{ /* likely */ }
4818	else
4819	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4820
4821	/* 64-bit CPU checks. */
4822	bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4823	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4824	{
4825	if (fGstInLongMode)
4826	{
4827	/* PAE must be set. */
4828	if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4829	&& (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4830	{ /* likely */ }
4831	else
4832	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4833	}
4834	else
4835	{
4836	/* PCIDE should not be set. */
4837	if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4838	{ /* likely */ }
4839	else
4840	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4841	}
4842
4843	/* CR3. */
4844	if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4845	{ /* likely */ }
4846	else
4847	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4848
4849	/* DR7. */
4850	if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4851	\|\| !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4852	{ /* likely */ }
4853	else
4854	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4855
4856	/* SYSENTER ESP and SYSENTER EIP. */
4857	if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4858	&& X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4859	{ /* likely */ }
4860	else
4861	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4862	}
4863
4864	/* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4865	Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4866
4867	/* PAT MSR. */
4868	if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4869	\|\| CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4870	{ /* likely */ }
4871	else
4872	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4873
4874	/* EFER MSR. */
4875	if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4876	{
4877	uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4878	if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4879	{ /* likely */ }
4880	else
4881	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4882
4883	bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4884	bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4885	if ( fGstLma == fGstInLongMode
4886	&& ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4887	\|\| fGstLma == fGstLme))
4888	{ /* likely */ }
4889	else
4890	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4891	}
4892
4893	/* We don't support IA32_BNDCFGS MSR yet. */
4894	Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4895
4896	NOREF(pszInstr);
4897	NOREF(pszFailure);
4898	return VINF_SUCCESS;
4899	}
4900
4901
4902	/**
4903	* Checks guest segment registers, LDTR and TR as part of VM-entry.
4904	*
4905	* @param pVCpu The cross context virtual CPU structure.
4906	* @param pszInstr The VMX instruction name (for logging purposes).
4907	*/
4908	DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4909	{
4910	/*
4911	* Segment registers.
4912	* See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4913	*/
4914	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4915	const char * const pszFailure = "VM-exit";
4916	bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4917	bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4918	bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4919
4920	/* Selectors. */
4921	if ( !fGstInV86Mode
4922	&& !fUnrestrictedGuest
4923	&& (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4924	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4925
4926	for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4927	{
4928	CPUMSELREG SelReg;
4929	int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4930	if (RT_LIKELY(rc == VINF_SUCCESS))
4931	{ /* likely */ }
4932	else
4933	return rc;
4934
4935	/*
4936	* Virtual-8086 mode checks.
4937	*/
4938	if (fGstInV86Mode)
4939	{
4940	/* Base address. */
4941	if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4942	{ /* likely */ }
4943	else
4944	{
4945	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4946	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4947	}
4948
4949	/* Limit. */
4950	if (SelReg.u32Limit == 0xffff)
4951	{ /* likely */ }
4952	else
4953	{
4954	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4955	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4956	}
4957
4958	/* Attribute. */
4959	if (SelReg.Attr.u == 0xf3)
4960	{ /* likely */ }
4961	else
4962	{
4963	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4964	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4965	}
4966
4967	/* We're done; move to checking the next segment. */
4968	continue;
4969	}
4970
4971	/* Checks done by 64-bit CPUs. */
4972	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4973	{
4974	/* Base address. */
4975	if ( iSegReg == X86_SREG_FS
4976	\|\| iSegReg == X86_SREG_GS)
4977	{
4978	if (X86_IS_CANONICAL(SelReg.u64Base))
4979	{ /* likely */ }
4980	else
4981	{
4982	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4983	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4984	}
4985	}
4986	else if (iSegReg == X86_SREG_CS)
4987	{
4988	if (!RT_HI_U32(SelReg.u64Base))
4989	{ /* likely */ }
4990	else
4991	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
4992	}
4993	else
4994	{
4995	if ( SelReg.Attr.n.u1Unusable
4996	\|\| !RT_HI_U32(SelReg.u64Base))
4997	{ /* likely */ }
4998	else
4999	{
5000	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5001	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5002	}
5003	}
5004	}
5005
5006	/*
5007	* Checks outside Virtual-8086 mode.
5008	*/
5009	uint8_t const uSegType = SelReg.Attr.n.u4Type;
5010	uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5011	uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5012	uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5013	uint8_t const fPresent = SelReg.Attr.n.u1Present;
5014	uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5015	uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5016	uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5017
5018	/* Code or usable segment. */
5019	if ( iSegReg == X86_SREG_CS
5020	\|\| fUsable)
5021	{
5022	/* Reserved bits (bits 31:17 and bits 11:8). */
5023	if (!(SelReg.Attr.u & 0xfffe0f00))
5024	{ /* likely */ }
5025	else
5026	{
5027	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5028	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5029	}
5030
5031	/* Descriptor type. */
5032	if (fCodeDataSeg)
5033	{ /* likely */ }
5034	else
5035	{
5036	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5037	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5038	}
5039
5040	/* Present. */
5041	if (fPresent)
5042	{ /* likely */ }
5043	else
5044	{
5045	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5046	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5047	}
5048
5049	/* Granularity. */
5050	if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff \|\| !uGranularity)
5051	&& ((SelReg.u32Limit & 0xfff00000) == 0x00000000 \|\| uGranularity))
5052	{ /* likely */ }
5053	else
5054	{
5055	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5056	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5057	}
5058	}
5059
5060	if (iSegReg == X86_SREG_CS)
5061	{
5062	/* Segment Type and DPL. */
5063	if ( uSegType == (X86_SEL_TYPE_RW \| X86_SEL_TYPE_ACCESSED)
5064	&& fUnrestrictedGuest)
5065	{
5066	if (uDpl == 0)
5067	{ /* likely */ }
5068	else
5069	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5070	}
5071	else if ( uSegType == (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
5072	\|\| uSegType == (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_READ \| X86_SEL_TYPE_ACCESSED))
5073	{
5074	X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5075	if (uDpl == AttrSs.n.u2Dpl)
5076	{ /* likely */ }
5077	else
5078	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5079	}
5080	else if ((uSegType & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF \| X86_SEL_TYPE_ACCESSED))
5081	== (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF \| X86_SEL_TYPE_ACCESSED))
5082	{
5083	X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5084	if (uDpl <= AttrSs.n.u2Dpl)
5085	{ /* likely */ }
5086	else
5087	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5088	}
5089	else
5090	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5091
5092	/* Def/Big. */
5093	if ( fGstInLongMode
5094	&& fSegLong)
5095	{
5096	if (uDefBig == 0)
5097	{ /* likely */ }
5098	else
5099	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5100	}
5101	}
5102	else if (iSegReg == X86_SREG_SS)
5103	{
5104	/* Segment Type. */
5105	if ( !fUsable
5106	\|\| uSegType == (X86_SEL_TYPE_RW \| X86_SEL_TYPE_ACCESSED)
5107	\|\| uSegType == (X86_SEL_TYPE_DOWN \| X86_SEL_TYPE_RW \| X86_SEL_TYPE_ACCESSED))
5108	{ /* likely */ }
5109	else
5110	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5111
5112	/* DPL. */
5113	if (!fUnrestrictedGuest)
5114	{
5115	if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5116	{ /* likely */ }
5117	else
5118	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5119	}
5120	X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5121	if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW \| X86_SEL_TYPE_ACCESSED)
5122	\|\| !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5123	{
5124	if (uDpl == 0)
5125	{ /* likely */ }
5126	else
5127	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5128	}
5129	}
5130	else
5131	{
5132	/* DS, ES, FS, GS. */
5133	if (fUsable)
5134	{
5135	/* Segment type. */
5136	if (uSegType & X86_SEL_TYPE_ACCESSED)
5137	{ /* likely */ }
5138	else
5139	{
5140	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5141	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5142	}
5143
5144	if ( !(uSegType & X86_SEL_TYPE_CODE)
5145	\|\| (uSegType & X86_SEL_TYPE_READ))
5146	{ /* likely */ }
5147	else
5148	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5149
5150	/* DPL. */
5151	if ( !fUnrestrictedGuest
5152	&& uSegType <= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_READ \| X86_SEL_TYPE_ACCESSED))
5153	{
5154	if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5155	{ /* likely */ }
5156	else
5157	{
5158	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5159	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5160	}
5161	}
5162	}
5163	}
5164	}
5165
5166	/*
5167	* LDTR.
5168	*/
5169	{
5170	CPUMSELREG Ldtr;
5171	Ldtr.Sel = pVmcs->GuestLdtr;
5172	Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5173	Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5174	Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5175
5176	if (!Ldtr.Attr.n.u1Unusable)
5177	{
5178	/* Selector. */
5179	if (!(Ldtr.Sel & X86_SEL_LDT))
5180	{ /* likely */ }
5181	else
5182	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5183
5184	/* Base. */
5185	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5186	{
5187	if (X86_IS_CANONICAL(Ldtr.u64Base))
5188	{ /* likely */ }
5189	else
5190	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5191	}
5192
5193	/* Attributes. */
5194	/* Reserved bits (bits 31:17 and bits 11:8). */
5195	if (!(Ldtr.Attr.u & 0xfffe0f00))
5196	{ /* likely */ }
5197	else
5198	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5199
5200	if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5201	{ /* likely */ }
5202	else
5203	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5204
5205	if (!Ldtr.Attr.n.u1DescType)
5206	{ /* likely */ }
5207	else
5208	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5209
5210	if (Ldtr.Attr.n.u1Present)
5211	{ /* likely */ }
5212	else
5213	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5214
5215	if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff \|\| !Ldtr.Attr.n.u1Granularity)
5216	&& ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 \|\| Ldtr.Attr.n.u1Granularity))
5217	{ /* likely */ }
5218	else
5219	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5220	}
5221	}
5222
5223	/*
5224	* TR.
5225	*/
5226	{
5227	CPUMSELREG Tr;
5228	Tr.Sel = pVmcs->GuestTr;
5229	Tr.u32Limit = pVmcs->u32GuestTrLimit;
5230	Tr.u64Base = pVmcs->u64GuestTrBase.u;
5231	Tr.Attr.u = pVmcs->u32GuestTrAttr;
5232
5233	/* Selector. */
5234	if (!(Tr.Sel & X86_SEL_LDT))
5235	{ /* likely */ }
5236	else
5237	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5238
5239	/* Base. */
5240	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5241	{
5242	if (X86_IS_CANONICAL(Tr.u64Base))
5243	{ /* likely */ }
5244	else
5245	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5246	}
5247
5248	/* Attributes. */
5249	/* Reserved bits (bits 31:17 and bits 11:8). */
5250	if (!(Tr.Attr.u & 0xfffe0f00))
5251	{ /* likely */ }
5252	else
5253	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5254
5255	if (!Tr.Attr.n.u1Unusable)
5256	{ /* likely */ }
5257	else
5258	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5259
5260	if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5261	\|\| ( !fGstInLongMode
5262	&& Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5263	{ /* likely */ }
5264	else
5265	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5266
5267	if (!Tr.Attr.n.u1DescType)
5268	{ /* likely */ }
5269	else
5270	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5271
5272	if (Tr.Attr.n.u1Present)
5273	{ /* likely */ }
5274	else
5275	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5276
5277	if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff \|\| !Tr.Attr.n.u1Granularity)
5278	&& ((Tr.u32Limit & 0xfff00000) == 0x00000000 \|\| Tr.Attr.n.u1Granularity))
5279	{ /* likely */ }
5280	else
5281	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5282	}
5283
5284	NOREF(pszInstr);
5285	NOREF(pszFailure);
5286	return VINF_SUCCESS;
5287	}
5288
5289
5290	/**
5291	* Checks guest GDTR and IDTR as part of VM-entry.
5292	*
5293	* @param pVCpu The cross context virtual CPU structure.
5294	* @param pszInstr The VMX instruction name (for logging purposes).
5295	*/
5296	DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5297	{
5298	/*
5299	* GDTR and IDTR.
5300	* See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5301	*/
5302	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5303	const char *const pszFailure = "VM-exit";
5304
5305	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5306	{
5307	/* Base. */
5308	if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5309	{ /* likely */ }
5310	else
5311	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5312
5313	if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5314	{ /* likely */ }
5315	else
5316	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5317	}
5318
5319	/* Limit. */
5320	if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5321	{ /* likely */ }
5322	else
5323	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5324
5325	if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5326	{ /* likely */ }
5327	else
5328	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5329
5330	NOREF(pszInstr);
5331	NOREF(pszFailure);
5332	return VINF_SUCCESS;
5333	}
5334
5335
5336	/**
5337	* Checks guest RIP and RFLAGS as part of VM-entry.
5338	*
5339	* @param pVCpu The cross context virtual CPU structure.
5340	* @param pszInstr The VMX instruction name (for logging purposes).
5341	*/
5342	DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5343	{
5344	/*
5345	* RIP and RFLAGS.
5346	* See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5347	*/
5348	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5349	const char *const pszFailure = "VM-exit";
5350	bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5351
5352	/* RIP. */
5353	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5354	{
5355	X86DESCATTR AttrCs;
5356	AttrCs.u = pVmcs->u32GuestCsAttr;
5357	if ( !fGstInLongMode
5358	\|\| !AttrCs.n.u1Long)
5359	{
5360	if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5361	{ /* likely */ }
5362	else
5363	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5364	}
5365
5366	if ( fGstInLongMode
5367	&& AttrCs.n.u1Long)
5368	{
5369	Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5370	if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5371	&& X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5372	{ /* likely */ }
5373	else
5374	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5375	}
5376	}
5377
5378	/* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5379	uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5380	: pVmcs->u64GuestRFlags.s.Lo;
5381	if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK \| X86_EFL_RA1_MASK))
5382	&& (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5383	{ /* likely */ }
5384	else
5385	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5386
5387	if ( fGstInLongMode
5388	\|\| !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5389	{
5390	if (!(uGuestRFlags & X86_EFL_VM))
5391	{ /* likely */ }
5392	else
5393	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5394	}
5395
5396	if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5397	{
5398	if (uGuestRFlags & X86_EFL_IF)
5399	{ /* likely */ }
5400	else
5401	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5402	}
5403
5404	NOREF(pszInstr);
5405	NOREF(pszFailure);
5406	return VINF_SUCCESS;
5407	}
5408
5409
5410	/**
5411	* Checks guest non-register state as part of VM-entry.
5412	*
5413	* @param pVCpu The cross context virtual CPU structure.
5414	* @param pszInstr The VMX instruction name (for logging purposes).
5415	*/
5416	DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5417	{
5418	/*
5419	* Guest non-register state.
5420	* See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5421	*/
5422	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5423	const char *const pszFailure = "VM-exit";
5424
5425	/*
5426	* Activity state.
5427	*/
5428	uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5429	uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5430	if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5431	{ /* likely */ }
5432	else
5433	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5434
5435	X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5436	if ( !AttrSs.n.u2Dpl
5437	\|\| pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5438	{ /* likely */ }
5439	else
5440	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5441
5442	if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5443	\|\| pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5444	{
5445	if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5446	{ /* likely */ }
5447	else
5448	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5449	}
5450
5451	if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5452	{
5453	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5454	uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5455	AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5456	switch (pVmcs->u32GuestActivityState)
5457	{
5458	case VMX_VMCS_GUEST_ACTIVITY_HLT:
5459	{
5460	if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5461	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5462	\|\| ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5463	&& ( uVector == X86_XCPT_DB
5464	\|\| uVector == X86_XCPT_MC))
5465	\|\| ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5466	&& uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5467	{ /* likely */ }
5468	else
5469	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5470	break;
5471	}
5472
5473	case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5474	{
5475	if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5476	\|\| ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5477	&& uVector == X86_XCPT_MC))
5478	{ /* likely */ }
5479	else
5480	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5481	break;
5482	}
5483
5484	case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5485	default:
5486	break;
5487	}
5488	}
5489
5490	/*
5491	* Interruptibility state.
5492	*/
5493	if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5494	{ /* likely */ }
5495	else
5496	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5497
5498	if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS \| VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5499	!= (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS \| VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5500	{ /* likely */ }
5501	else
5502	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5503
5504	if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5505	\|\| !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5506	{ /* likely */ }
5507	else
5508	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5509
5510	if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5511	{
5512	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5513	if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5514	{
5515	if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS \| VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5516	{ /* likely */ }
5517	else
5518	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5519	}
5520	else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5521	{
5522	if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS \| VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5523	{ /* likely */ }
5524	else
5525	{
5526	/*
5527	* We don't support injecting NMIs when blocking-by-STI would be in effect.
5528	* We update the Exit qualification only when blocking-by-STI is set
5529	* without blocking-by-MovSS being set. Although in practise it does not
5530	* make much difference since the order of checks are implementation defined.
5531	*/
5532	if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5533	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5534	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5535	}
5536
5537	if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5538	\|\| !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5539	{ /* likely */ }
5540	else
5541	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5542	}
5543	}
5544
5545	/* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5546	if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5547	{ /* likely */ }
5548	else
5549	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5550
5551	/* We don't support SGX yet. So enclave-interruption must not be set. */
5552	if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5553	{ /* likely */ }
5554	else
5555	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5556
5557	/*
5558	* Pending debug exceptions.
5559	*/
5560	uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5561	? pVmcs->u64GuestPendingDbgXcpts.u
5562	: pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5563	if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5564	{ /* likely */ }
5565	else
5566	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5567
5568	if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS \| VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5569	\|\| pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5570	{
5571	if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5572	&& !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5573	&& !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5574	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5575
5576	if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5577	\|\| (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5578	&& (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5579	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5580	}
5581
5582	/* We don't support RTM (Real-time Transactional Memory) yet. */
5583	if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5584	{ /* likely */ }
5585	else
5586	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5587
5588	/*
5589	* VMCS link pointer.
5590	*/
5591	if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5592	{
5593	RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5594	/* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5595	if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5596	{ /* likely */ }
5597	else
5598	{
5599	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5600	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5601	}
5602
5603	/* Validate the address. */
5604	if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5605	&& !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5606	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5607	{ /* likely */ }
5608	else
5609	{
5610	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5611	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5612	}
5613	}
5614
5615	NOREF(pszInstr);
5616	NOREF(pszFailure);
5617	return VINF_SUCCESS;
5618	}
5619
5620
5621	/**
5622	* Checks guest PDPTEs as part of VM-entry.
5623	*
5624	* @param pVCpu The cross context virtual CPU structure.
5625	* @param pszInstr The VMX instruction name (for logging purposes).
5626	*/
5627	IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr)
5628	{
5629	/*
5630	* Guest PDPTEs.
5631	* See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5632	*/
5633	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5634	const char * const pszFailure = "VM-exit";
5635
5636	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5637	/*
5638	* When EPT is used, we only validate the PAE PDPTEs provided in the VMCS.
5639	* Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
5640	*/
5641	if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
5642	&& (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
5643	{
5644	/* Get PDPTEs from the VMCS. */
5645	X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
5646	aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
5647	aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
5648	aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
5649	aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
5650
5651	/* Check validity of the PDPTEs. */
5652	bool const fValid = PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]);
5653	if (fValid)
5654	{ /* likely */ }
5655	else
5656	{
5657	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5658	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5659	}
5660	}
5661	#endif
5662
5663	NOREF(pszInstr);
5664	NOREF(pszFailure);
5665	return VINF_SUCCESS;
5666	}
5667
5668
5669	/**
5670	* Checks guest-state as part of VM-entry.
5671	*
5672	* @returns VBox status code.
5673	* @param pVCpu The cross context virtual CPU structure.
5674	* @param pfPdpesMapped Where to store whether PAE PDPTEs (and PDPT) have been
5675	* mapped as part of checking guest state.
5676	* @param pszInstr The VMX instruction name (for logging purposes).
5677	*/
5678	IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr)
5679	{
5680	int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5681	if (RT_SUCCESS(rc))
5682	{
5683	rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5684	if (RT_SUCCESS(rc))
5685	{
5686	rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5687	if (RT_SUCCESS(rc))
5688	{
5689	rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5690	if (RT_SUCCESS(rc))
5691	{
5692	rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5693	if (RT_SUCCESS(rc))
5694	return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5695	}
5696	}
5697	}
5698	}
5699	return rc;
5700	}
5701
5702
5703	/**
5704	* Checks host-state as part of VM-entry.
5705	*
5706	* @returns VBox status code.
5707	* @param pVCpu The cross context virtual CPU structure.
5708	* @param pszInstr The VMX instruction name (for logging purposes).
5709	*/
5710	IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5711	{
5712	/*
5713	* Host Control Registers and MSRs.
5714	* See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5715	*/
5716	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5717	const char * const pszFailure = "VMFail";
5718
5719	/* CR0 reserved bits. */
5720	{
5721	/* CR0 MB1 bits. */
5722	uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5723	if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5724	{ /* likely */ }
5725	else
5726	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5727
5728	/* CR0 MBZ bits. */
5729	uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5730	if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5731	{ /* likely */ }
5732	else
5733	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5734	}
5735
5736	/* CR4 reserved bits. */
5737	{
5738	/* CR4 MB1 bits. */
5739	uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5740	if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5741	{ /* likely */ }
5742	else
5743	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5744
5745	/* CR4 MBZ bits. */
5746	uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5747	if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5748	{ /* likely */ }
5749	else
5750	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5751	}
5752
5753	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5754	{
5755	/* CR3 reserved bits. */
5756	if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5757	{ /* likely */ }
5758	else
5759	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5760
5761	/* SYSENTER ESP and SYSENTER EIP. */
5762	if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5763	&& X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5764	{ /* likely */ }
5765	else
5766	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5767	}
5768
5769	/* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5770	Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5771
5772	/* PAT MSR. */
5773	if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5774	\|\| CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5775	{ /* likely */ }
5776	else
5777	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5778
5779	/* EFER MSR. */
5780	uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5781	if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5782	\|\| !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5783	{ /* likely */ }
5784	else
5785	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5786
5787	bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5788	bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5789	bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5790	if ( fHostInLongMode == fHostLma
5791	&& fHostInLongMode == fHostLme)
5792	{ /* likely */ }
5793	else
5794	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5795
5796	/*
5797	* Host Segment and Descriptor-Table Registers.
5798	* See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5799	*/
5800	/* Selector RPL and TI. */
5801	if ( !(pVmcs->HostCs & (X86_SEL_RPL \| X86_SEL_LDT))
5802	&& !(pVmcs->HostSs & (X86_SEL_RPL \| X86_SEL_LDT))
5803	&& !(pVmcs->HostDs & (X86_SEL_RPL \| X86_SEL_LDT))
5804	&& !(pVmcs->HostEs & (X86_SEL_RPL \| X86_SEL_LDT))
5805	&& !(pVmcs->HostFs & (X86_SEL_RPL \| X86_SEL_LDT))
5806	&& !(pVmcs->HostGs & (X86_SEL_RPL \| X86_SEL_LDT))
5807	&& !(pVmcs->HostTr & (X86_SEL_RPL \| X86_SEL_LDT)))
5808	{ /* likely */ }
5809	else
5810	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5811
5812	/* CS and TR selectors cannot be 0. */
5813	if ( pVmcs->HostCs
5814	&& pVmcs->HostTr)
5815	{ /* likely */ }
5816	else
5817	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5818
5819	/* SS cannot be 0 if 32-bit host. */
5820	if ( fHostInLongMode
5821	\|\| pVmcs->HostSs)
5822	{ /* likely */ }
5823	else
5824	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5825
5826	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5827	{
5828	/* FS, GS, GDTR, IDTR, TR base address. */
5829	if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5830	&& X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5831	&& X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5832	&& X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5833	&& X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5834	{ /* likely */ }
5835	else
5836	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5837	}
5838
5839	/*
5840	* Host address-space size for 64-bit CPUs.
5841	* See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5842	*/
5843	bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5844	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5845	{
5846	bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5847
5848	/* Logical processor in IA-32e mode. */
5849	if (fCpuInLongMode)
5850	{
5851	if (fHostInLongMode)
5852	{
5853	/* PAE must be set. */
5854	if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5855	{ /* likely */ }
5856	else
5857	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5858
5859	/* RIP must be canonical. */
5860	if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5861	{ /* likely */ }
5862	else
5863	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5864	}
5865	else
5866	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5867	}
5868	else
5869	{
5870	/* Logical processor is outside IA-32e mode. */
5871	if ( !fGstInLongMode
5872	&& !fHostInLongMode)
5873	{
5874	/* PCIDE should not be set. */
5875	if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5876	{ /* likely */ }
5877	else
5878	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5879
5880	/* The high 32-bits of RIP MBZ. */
5881	if (!pVmcs->u64HostRip.s.Hi)
5882	{ /* likely */ }
5883	else
5884	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5885	}
5886	else
5887	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5888	}
5889	}
5890	else
5891	{
5892	/* Host address-space size for 32-bit CPUs. */
5893	if ( !fGstInLongMode
5894	&& !fHostInLongMode)
5895	{ /* likely */ }
5896	else
5897	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5898	}
5899
5900	NOREF(pszInstr);
5901	NOREF(pszFailure);
5902	return VINF_SUCCESS;
5903	}
5904
5905
5906	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5907	/**
5908	* Checks the EPT pointer VMCS field as part of VM-entry.
5909	*
5910	* @returns VBox status code.
5911	* @param pVCpu The cross context virtual CPU structure.
5912	* @param penmVmxDiag Where to store the diagnostic reason on failure (not
5913	* updated on success). Optional, can be NULL.
5914	*/
5915	IEM_STATIC int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, VMXVDIAG *penmVmxDiag)
5916	{
5917	VMXVDIAG enmVmxDiag;
5918	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5919
5920	/* Reserved bits. */
5921	uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
5922	uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
5923	if (pVmcs->u64EptPtr.u & fValidMask)
5924	{
5925	/* Memory Type. */
5926	uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
5927	uint8_t const fMemType = RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_MEMTYPE);
5928	if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
5929	&& RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
5930	\|\| ( fMemType == VMX_EPTP_MEMTYPE_UC
5931	&& RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
5932	{
5933	/*
5934	* Page walk length (PML4).
5935	* Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
5936	* of 5 but that seems to be removed from the latest specs. leaving only PML4
5937	* as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
5938	*/
5939	Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
5940	if (RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
5941	{
5942	/* Access and dirty bits support in EPT structures. */
5943	if ( !RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_ACCESS_DIRTY)
5944	\|\| RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
5945	return VINF_SUCCESS;
5946
5947	enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
5948	}
5949	else
5950	enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
5951	}
5952	else
5953	enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
5954	}
5955	else
5956	enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
5957
5958	if (penmVmxDiag)
5959	*penmVmxDiag = enmVmxDiag;
5960	return VERR_VMX_VMENTRY_FAILED;
5961	}
5962	#endif
5963
5964
5965	/**
5966	* Checks VMCS controls fields as part of VM-entry.
5967	*
5968	* @returns VBox status code.
5969	* @param pVCpu The cross context virtual CPU structure.
5970	* @param pszInstr The VMX instruction name (for logging purposes).
5971	*
5972	* @remarks This may update secondary-processor based VM-execution control fields
5973	* in the current VMCS if necessary.
5974	*/
5975	IEM_STATIC int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr)
5976	{
5977	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5978	const char * const pszFailure = "VMFail";
5979
5980	/*
5981	* VM-execution controls.
5982	* See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
5983	*/
5984	{
5985	/* Pin-based VM-execution controls. */
5986	{
5987	VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
5988	if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
5989	{ /* likely */ }
5990	else
5991	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
5992
5993	if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
5994	{ /* likely */ }
5995	else
5996	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
5997	}
5998
5999	/* Processor-based VM-execution controls. */
6000	{
6001	VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6002	if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6003	{ /* likely */ }
6004	else
6005	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6006
6007	if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6008	{ /* likely */ }
6009	else
6010	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6011	}
6012
6013	/* Secondary processor-based VM-execution controls. */
6014	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6015	{
6016	VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6017	if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6018	{ /* likely */ }
6019	else
6020	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6021
6022	if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6023	{ /* likely */ }
6024	else
6025	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6026	}
6027	else
6028	Assert(!pVmcs->u32ProcCtls2);
6029
6030	/* CR3-target count. */
6031	if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6032	{ /* likely */ }
6033	else
6034	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6035
6036	/* I/O bitmaps physical addresses. */
6037	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6038	{
6039	RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6040	if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6041	&& !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6042	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6043	{ /* likely */ }
6044	else
6045	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6046
6047	RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6048	if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6049	&& !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6050	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6051	{ /* likely */ }
6052	else
6053	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6054	}
6055
6056	/* MSR bitmap physical address. */
6057	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6058	{
6059	RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6060	if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6061	&& !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6062	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6063	{ /* likely */ }
6064	else
6065	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6066	}
6067
6068	/* TPR shadow related controls. */
6069	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6070	{
6071	/* Virtual-APIC page physical address. */
6072	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6073	if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6074	&& !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6075	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6076	{ /* likely */ }
6077	else
6078	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6079
6080	/* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6081	if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6082	\|\| (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6083	{ /* likely */ }
6084	else
6085	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6086
6087	/* The rest done XXX document */
6088	}
6089	else
6090	{
6091	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6092	&& !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6093	&& !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6094	{ /* likely */ }
6095	else
6096	{
6097	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6098	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6099	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6100	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6101	Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6102	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6103	}
6104	}
6105
6106	/* NMI exiting and virtual-NMIs. */
6107	if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6108	\|\| !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6109	{ /* likely */ }
6110	else
6111	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6112
6113	/* Virtual-NMIs and NMI-window exiting. */
6114	if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6115	\|\| !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6116	{ /* likely */ }
6117	else
6118	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6119
6120	/* Virtualize APIC accesses. */
6121	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6122	{
6123	/* APIC-access physical address. */
6124	RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6125	if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6126	&& !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6127	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6128	{ /* likely */ }
6129	else
6130	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6131
6132	/*
6133	* Disallow APIC-access page and virtual-APIC page from being the same address.
6134	* Note! This is not an Intel requirement, but one imposed by our implementation.
6135	*/
6136	/** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6137	* redirecting accesses between the APIC-access page and the virtual-APIC
6138	* page. If any nested hypervisor requires this, we can implement it later. */
6139	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6140	{
6141	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6142	if (GCPhysVirtApic != GCPhysApicAccess)
6143	{ /* likely */ }
6144	else
6145	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6146	}
6147	}
6148
6149	/* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6150	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6151	\|\| !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6152	{ /* likely */ }
6153	else
6154	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6155
6156	/* Virtual-interrupt delivery requires external interrupt exiting. */
6157	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6158	\|\| (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6159	{ /* likely */ }
6160	else
6161	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6162
6163	/* VPID. */
6164	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6165	\|\| pVmcs->u16Vpid != 0)
6166	{ /* likely */ }
6167	else
6168	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6169
6170	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6171	/* Extended-Page-Table Pointer (EPTP). */
6172	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6173	{
6174	VMXVDIAG enmVmxDiag;
6175	int const rc = iemVmxVmentryCheckEptPtr(pVCpu, &enmVmxDiag);
6176	if (RT_SUCCESS(rc))
6177	{ /* likely */ }
6178	else
6179	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6180	}
6181	#else
6182	Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6183	#endif
6184
6185	Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6186	Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6187	Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6188	Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6189	Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6190	Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6191	Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6192
6193	/* VMCS shadowing. */
6194	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6195	{
6196	/* VMREAD-bitmap physical address. */
6197	RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6198	if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6199	&& !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6200	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6201	{ /* likely */ }
6202	else
6203	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6204
6205	/* VMWRITE-bitmap physical address. */
6206	RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6207	if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6208	&& !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6209	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6210	{ /* likely */ }
6211	else
6212	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6213	}
6214	}
6215
6216	/*
6217	* VM-exit controls.
6218	* See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6219	*/
6220	{
6221	VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6222	if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6223	{ /* likely */ }
6224	else
6225	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6226
6227	if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6228	{ /* likely */ }
6229	else
6230	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6231
6232	/* Save preemption timer without activating it. */
6233	if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6234	\|\| !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6235	{ /* likely */ }
6236	else
6237	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6238
6239	/* VM-exit MSR-store count and VM-exit MSR-store area address. */
6240	if (pVmcs->u32ExitMsrStoreCount)
6241	{
6242	if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6243	&& !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6244	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6245	{ /* likely */ }
6246	else
6247	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6248	}
6249
6250	/* VM-exit MSR-load count and VM-exit MSR-load area address. */
6251	if (pVmcs->u32ExitMsrLoadCount)
6252	{
6253	if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6254	&& !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6255	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6256	{ /* likely */ }
6257	else
6258	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6259	}
6260	}
6261
6262	/*
6263	* VM-entry controls.
6264	* See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6265	*/
6266	{
6267	VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6268	if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6269	{ /* likely */ }
6270	else
6271	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6272
6273	if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6274	{ /* likely */ }
6275	else
6276	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6277
6278	/* Event injection. */
6279	uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6280	if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6281	{
6282	/* Type and vector. */
6283	uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6284	uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6285	uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6286	if ( !uRsvd
6287	&& VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6288	&& VMXIsEntryIntInfoVectorValid(uVector, uType))
6289	{ /* likely */ }
6290	else
6291	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6292
6293	/* Exception error code. */
6294	if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6295	{
6296	/* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6297	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6298	\|\| (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6299	{ /* likely */ }
6300	else
6301	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6302
6303	/* Exceptions that provide an error code. */
6304	if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6305	&& ( uVector == X86_XCPT_DF
6306	\|\| uVector == X86_XCPT_TS
6307	\|\| uVector == X86_XCPT_NP
6308	\|\| uVector == X86_XCPT_SS
6309	\|\| uVector == X86_XCPT_GP
6310	\|\| uVector == X86_XCPT_PF
6311	\|\| uVector == X86_XCPT_AC))
6312	{ /* likely */ }
6313	else
6314	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6315
6316	/* Exception error-code reserved bits. */
6317	if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6318	{ /* likely */ }
6319	else
6320	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6321
6322	/* Injecting a software interrupt, software exception or privileged software exception. */
6323	if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6324	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6325	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6326	{
6327	/* Instruction length must be in the range 0-15. */
6328	if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6329	{ /* likely */ }
6330	else
6331	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6332
6333	/* However, instruction length of 0 is allowed only when its CPU feature is present. */
6334	if ( pVmcs->u32EntryInstrLen != 0
6335	\|\| IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6336	{ /* likely */ }
6337	else
6338	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6339	}
6340	}
6341	}
6342
6343	/* VM-entry MSR-load count and VM-entry MSR-load area address. */
6344	if (pVmcs->u32EntryMsrLoadCount)
6345	{
6346	if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6347	&& !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6348	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6349	{ /* likely */ }
6350	else
6351	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6352	}
6353
6354	Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6355	Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6356	}
6357
6358	NOREF(pszInstr);
6359	NOREF(pszFailure);
6360	return VINF_SUCCESS;
6361	}
6362
6363
6364	/**
6365	* Loads the guest control registers, debug register and some MSRs as part of
6366	* VM-entry.
6367	*
6368	* @param pVCpu The cross context virtual CPU structure.
6369	*/
6370	IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6371	{
6372	/*
6373	* Load guest control registers, debug registers and MSRs.
6374	* See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6375	*/
6376	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6377
6378	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6379	uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6380	\| (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6381	CPUMSetGuestCR0(pVCpu, uGstCr0);
6382	CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6383	pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6384
6385	if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6386	pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) \| VMX_ENTRY_GUEST_DR7_MB1_MASK;
6387
6388	pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6389	pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6390	pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6391
6392	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6393	{
6394	/* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6395
6396	/* EFER MSR. */
6397	if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6398	{
6399	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6400	uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6401	bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6402	bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6403	if (fGstInLongMode)
6404	{
6405	/* If the nested-guest is in long mode, LMA and LME are both set. */
6406	Assert(fGstPaging);
6407	pVCpu->cpum.GstCtx.msrEFER = uHostEfer \| (MSR_K6_EFER_LMA \| MSR_K6_EFER_LME);
6408	}
6409	else
6410	{
6411	/*
6412	* If the nested-guest is outside long mode:
6413	* - With paging: LMA is cleared, LME is cleared.
6414	* - Without paging: LMA is cleared, LME is left unmodified.
6415	*/
6416	uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA \| (fGstPaging ? MSR_K6_EFER_LME : 0);
6417	pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6418	}
6419	}
6420	/* else: see below. */
6421	}
6422
6423	/* PAT MSR. */
6424	if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6425	pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6426
6427	/* EFER MSR. */
6428	if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6429	pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6430
6431	/* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6432	Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6433
6434	/* We don't support IA32_BNDCFGS MSR yet. */
6435	Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6436
6437	/* Nothing to do for SMBASE register - We don't support SMM yet. */
6438	}
6439
6440
6441	/**
6442	* Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6443	*
6444	* @param pVCpu The cross context virtual CPU structure.
6445	*/
6446	IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6447	{
6448	/*
6449	* Load guest segment registers, GDTR, IDTR, LDTR and TR.
6450	* See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6451	*/
6452	/* CS, SS, ES, DS, FS, GS. */
6453	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6454	for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6455	{
6456	PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6457	CPUMSELREG VmcsSelReg;
6458	int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6459	AssertRC(rc); NOREF(rc);
6460	if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6461	{
6462	pGstSelReg->Sel = VmcsSelReg.Sel;
6463	pGstSelReg->ValidSel = VmcsSelReg.Sel;
6464	pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6465	pGstSelReg->u64Base = VmcsSelReg.u64Base;
6466	pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6467	pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6468	}
6469	else
6470	{
6471	pGstSelReg->Sel = VmcsSelReg.Sel;
6472	pGstSelReg->ValidSel = VmcsSelReg.Sel;
6473	pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6474	switch (iSegReg)
6475	{
6476	case X86_SREG_CS:
6477	pGstSelReg->u64Base = VmcsSelReg.u64Base;
6478	pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6479	pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6480	break;
6481
6482	case X86_SREG_SS:
6483	pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6484	pGstSelReg->u32Limit = 0;
6485	pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) \| X86DESCATTR_D \| X86DESCATTR_UNUSABLE;
6486	break;
6487
6488	case X86_SREG_ES:
6489	case X86_SREG_DS:
6490	pGstSelReg->u64Base = 0;
6491	pGstSelReg->u32Limit = 0;
6492	pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6493	break;
6494
6495	case X86_SREG_FS:
6496	case X86_SREG_GS:
6497	pGstSelReg->u64Base = VmcsSelReg.u64Base;
6498	pGstSelReg->u32Limit = 0;
6499	pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6500	break;
6501	}
6502	Assert(pGstSelReg->Attr.n.u1Unusable);
6503	}
6504	}
6505
6506	/* LDTR. */
6507	pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6508	pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6509	pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6510	if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6511	{
6512	pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6513	pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6514	pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6515	}
6516	else
6517	{
6518	pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6519	pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6520	pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6521	}
6522
6523	/* TR. */
6524	Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6525	pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6526	pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6527	pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6528	pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6529	pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6530	pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6531
6532	/* GDTR. */
6533	pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6534	pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6535
6536	/* IDTR. */
6537	pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6538	pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6539	}
6540
6541
6542	/**
6543	* Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6544	*
6545	* @returns VBox status code.
6546	* @param pVCpu The cross context virtual CPU structure.
6547	* @param pszInstr The VMX instruction name (for logging purposes).
6548	*/
6549	IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6550	{
6551	/*
6552	* Load guest MSRs.
6553	* See Intel spec. 26.4 "Loading MSRs".
6554	*/
6555	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6556	const char *const pszFailure = "VM-exit";
6557
6558	/*
6559	* The VM-entry MSR-load area address need not be a valid guest-physical address if the
6560	* VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6561	* See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6562	*/
6563	uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6564	if (!cMsrs)
6565	return VINF_SUCCESS;
6566
6567	/*
6568	* Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6569	* exceeded including possibly raising #MC exceptions during VMX transition. Our
6570	* implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6571	*/
6572	bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6573	if (fIsMsrCountValid)
6574	{ /* likely */ }
6575	else
6576	{
6577	iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6578	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6579	}
6580
6581	RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6582	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6583	GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6584	if (RT_SUCCESS(rc))
6585	{
6586	PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6587	for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6588	{
6589	if ( !pMsr->u32Reserved
6590	&& pMsr->u32Msr != MSR_K8_FS_BASE
6591	&& pMsr->u32Msr != MSR_K8_GS_BASE
6592	&& pMsr->u32Msr != MSR_K6_EFER
6593	&& pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6594	&& pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6595	{
6596	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6597	if (rcStrict == VINF_SUCCESS)
6598	continue;
6599
6600	/*
6601	* If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6602	* If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6603	* recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6604	* further by our own, specific diagnostic code. Later, we can try implement handling of the
6605	* MSR in ring-0 if possible, or come up with a better, generic solution.
6606	*/
6607	iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6608	VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6609	? kVmxVDiag_Vmentry_MsrLoadRing3
6610	: kVmxVDiag_Vmentry_MsrLoad;
6611	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6612	}
6613	else
6614	{
6615	iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6616	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6617	}
6618	}
6619	}
6620	else
6621	{
6622	AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6623	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6624	}
6625
6626	NOREF(pszInstr);
6627	NOREF(pszFailure);
6628	return VINF_SUCCESS;
6629	}
6630
6631
6632	/**
6633	* Loads the guest-state non-register state as part of VM-entry.
6634	*
6635	* @returns VBox status code.
6636	* @param pVCpu The cross context virtual CPU structure.
6637	* @param pszInstr The VMX instruction name (for logging purposes).
6638	*
6639	* @remarks This must be called only after loading the nested-guest register state
6640	* (especially nested-guest RIP).
6641	*/
6642	IEM_STATIC int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
6643	{
6644	/*
6645	* Load guest non-register state.
6646	* See Intel spec. 26.6 "Special Features of VM Entry"
6647	*/
6648	const char *const pszFailure = "VM-exit";
6649	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6650
6651	/*
6652	* If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6653	* If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6654	*
6655	* See Intel spec. 26.6.1 "Interruptibility State".
6656	*/
6657	bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6658	if ( !fEntryVectoring
6659	&& (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI \| VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6660	EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6661	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6662	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6663
6664	/* NMI blocking. */
6665	if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6666	{
6667	if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6668	pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6669	else
6670	{
6671	pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6672	if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6673	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6674	}
6675	}
6676	else
6677	pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6678
6679	/* SMI blocking is irrelevant. We don't support SMIs yet. */
6680
6681	/*
6682	* Load the guest's PAE PDPTEs.
6683	*/
6684	if (iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
6685	{
6686	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6687	{
6688	/*
6689	* With EPT, we've already validated these while checking the guest state.
6690	* Just load them directly from the VMCS here.
6691	*/
6692	X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6693	aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6694	aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6695	aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6696	aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6697	AssertCompile(RT_ELEMENTS(aPaePdptes) == RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes));
6698	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes); i++)
6699	pVCpu->cpum.GstCtx.aPaePdpes[i].u = aPaePdptes[i].u;
6700	}
6701	else
6702	{
6703	/*
6704	* Without EPT, we must load the PAE PDPTEs referenced by CR3.
6705	* This involves loading (and mapping) CR3 and validating them now.
6706	*/
6707	int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
6708	if (RT_SUCCESS(rc))
6709	{ /* likely */ }
6710	else
6711	{
6712	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6713	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6714	}
6715	}
6716	}
6717
6718	/*
6719	* Set PGM's copy of the EPT pointer.
6720	* The EPTP has already been validated while checking guest state.
6721	*/
6722	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6723	PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
6724
6725	/* VPID is irrelevant. We don't support VPID yet. */
6726
6727	/* Clear address-range monitoring. */
6728	EMMonitorWaitClear(pVCpu);
6729
6730	return VINF_SUCCESS;
6731	}
6732
6733
6734	/**
6735	* Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
6736	*
6737	* @param pVCpu The cross context virtual CPU structure.
6738	* @param pszInstr The VMX instruction name (for logging purposes).
6739	*
6740	* @remarks This assumes various VMCS related data structure pointers have already
6741	* been verified prior to calling this function.
6742	*/
6743	IEM_STATIC int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr)
6744	{
6745	const char *const pszFailure = "VM-exit";
6746	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6747
6748	/*
6749	* Virtualize APIC accesses.
6750	*/
6751	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6752	{
6753	/* APIC-access physical address. */
6754	RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6755
6756	/*
6757	* Register the handler for the APIC-access page.
6758	*
6759	* We don't deregister the APIC-access page handler during the VM-exit as a different
6760	* nested-VCPU might be using the same guest-physical address for its APIC-access page.
6761	*
6762	* We leave the page registered until the first access that happens outside VMX non-root
6763	* mode. Guest software is allowed to access structures such as the APIC-access page
6764	* only when no logical processor with a current VMCS references it in VMX non-root mode,
6765	* otherwise it can lead to unpredictable behavior including guest triple-faults.
6766	*
6767	* See Intel spec. 24.11.4 "Software Access to Related Structures".
6768	*/
6769	if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6770	{
6771	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6772	PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
6773	int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6774	pVCpu0->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6775	NIL_RTR0PTR /* pvUserR0 /, NIL_RTRCPTR / pvUserRC /, NULL / pszDesc */);
6776	if (RT_SUCCESS(rc))
6777	{ /* likely */ }
6778	else
6779	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6780	}
6781	}
6782
6783	/*
6784	* VMCS shadowing.
6785	*/
6786	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6787	{
6788	/* Read the VMREAD-bitmap. */
6789	RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6790	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
6791	GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
6792	if (RT_SUCCESS(rc))
6793	{ /* likely */ }
6794	else
6795	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6796
6797	/* Read the VMWRITE-bitmap. */
6798	RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
6799	rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
6800	GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
6801	if (RT_SUCCESS(rc))
6802	{ /* likely */ }
6803	else
6804	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6805	}
6806
6807	/*
6808	* I/O bitmaps.
6809	*/
6810	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6811	{
6812	/* Read the IO bitmap A. */
6813	RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6814	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
6815	GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
6816	if (RT_SUCCESS(rc))
6817	{ /* likely */ }
6818	else
6819	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
6820
6821	/* Read the IO bitmap B. */
6822	RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6823	rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
6824	GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
6825	if (RT_SUCCESS(rc))
6826	{ /* likely */ }
6827	else
6828	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
6829	}
6830
6831	/*
6832	* TPR shadow and Virtual-APIC page.
6833	*/
6834	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6835	{
6836	/* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6837	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6838	&& !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6839	{
6840	/* Read the VTPR from the virtual-APIC page. */
6841	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6842	uint8_t u8VTpr;
6843	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6844	if (RT_SUCCESS(rc))
6845	{ /* likely */ }
6846	else
6847	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6848
6849	/* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6850	if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6851	{ /* likely */ }
6852	else
6853	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6854	}
6855	}
6856
6857	/*
6858	* VMCS link pointer.
6859	*/
6860	if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6861	{
6862	/* Read the VMCS-link pointer from guest memory. */
6863	RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6864	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
6865	GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
6866	if (RT_SUCCESS(rc))
6867	{ /* likely */ }
6868	else
6869	{
6870	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6871	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6872	}
6873
6874	/* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6875	if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6876	{ /* likely */ }
6877	else
6878	{
6879	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6880	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6881	}
6882
6883	/* Verify the shadow bit is set if VMCS shadowing is enabled . */
6884	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6885	\|\| pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
6886	{ /* likely */ }
6887	else
6888	{
6889	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6890	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6891	}
6892
6893	/* Update our cache of the guest physical address of the shadow VMCS. */
6894	pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6895	}
6896
6897	/*
6898	* MSR bitmap.
6899	*/
6900	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6901	{
6902	/* Read the MSR bitmap. */
6903	RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6904	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
6905	GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
6906	if (RT_SUCCESS(rc))
6907	{ /* likely */ }
6908	else
6909	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6910	}
6911
6912	NOREF(pszFailure);
6913	NOREF(pszInstr);
6914	return VINF_SUCCESS;
6915	}
6916
6917
6918	/**
6919	* Loads the guest-state as part of VM-entry.
6920	*
6921	* @returns VBox status code.
6922	* @param pVCpu The cross context virtual CPU structure.
6923	* @param pszInstr The VMX instruction name (for logging purposes).
6924	*
6925	* @remarks This must be done after all the necessary steps prior to loading of
6926	* guest-state (e.g. checking various VMCS state).
6927	*/
6928	IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6929	{
6930	/* Load guest control registers, MSRs (that are directly part of the VMCS). */
6931	iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6932
6933	/* Load guest segment registers. */
6934	iemVmxVmentryLoadGuestSegRegs(pVCpu);
6935
6936	/*
6937	* Load guest RIP, RSP and RFLAGS.
6938	* See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6939	*/
6940	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6941	pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6942	pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6943	pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6944
6945	/* Initialize the PAUSE-loop controls as part of VM-entry. */
6946	pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6947	pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6948
6949	/* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
6950	int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
6951	if (rc == VINF_SUCCESS)
6952	{ /* likely */ }
6953	else
6954	return rc;
6955
6956	/* Load VMX related structures and state referenced by the VMCS. */
6957	rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
6958	if (rc == VINF_SUCCESS)
6959	{ /* likely */ }
6960	else
6961	return rc;
6962
6963	NOREF(pszInstr);
6964	return VINF_SUCCESS;
6965	}
6966
6967
6968	/**
6969	* Returns whether there are is a pending debug exception on VM-entry.
6970	*
6971	* @param pVCpu The cross context virtual CPU structure.
6972	* @param pszInstr The VMX instruction name (for logging purposes).
6973	*/
6974	IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6975	{
6976	/*
6977	* Pending debug exceptions.
6978	* See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6979	*/
6980	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6981	Assert(pVmcs);
6982
6983	bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6984	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6985	if (fPendingDbgXcpt)
6986	{
6987	uint8_t uEntryIntInfoType;
6988	bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6989	if (fEntryVectoring)
6990	{
6991	switch (uEntryIntInfoType)
6992	{
6993	case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6994	case VMX_ENTRY_INT_INFO_TYPE_NMI:
6995	case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
6996	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
6997	fPendingDbgXcpt = false;
6998	break;
6999
7000	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7001	{
7002	/*
7003	* Whether the pending debug exception for software exceptions other than
7004	* #BP and #OF is delivered after injecting the exception or is discard
7005	* is CPU implementation specific. We will discard them (easier).
7006	*/
7007	uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7008	if ( uVector != X86_XCPT_BP
7009	&& uVector != X86_XCPT_OF)
7010	fPendingDbgXcpt = false;
7011	RT_FALL_THRU();
7012	}
7013	case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7014	{
7015	if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7016	fPendingDbgXcpt = false;
7017	break;
7018	}
7019	}
7020	}
7021	else
7022	{
7023	/*
7024	* When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7025	* pending debug exception is held pending or is discarded is CPU implementation
7026	* specific. We will discard them (easier).
7027	*/
7028	if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7029	fPendingDbgXcpt = false;
7030
7031	/* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7032	if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN \| VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7033	fPendingDbgXcpt = false;
7034	}
7035	}
7036
7037	NOREF(pszInstr);
7038	return fPendingDbgXcpt;
7039	}
7040
7041
7042	/**
7043	* Set up the monitor-trap flag (MTF).
7044	*
7045	* @param pVCpu The cross context virtual CPU structure.
7046	* @param pszInstr The VMX instruction name (for logging purposes).
7047	*/
7048	IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
7049	{
7050	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7051	Assert(pVmcs);
7052	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7053	{
7054	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7055	Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7056	}
7057	else
7058	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7059	NOREF(pszInstr);
7060	}
7061
7062
7063	/**
7064	* Sets up NMI-window exiting.
7065	*
7066	* @param pVCpu The cross context virtual CPU structure.
7067	* @param pszInstr The VMX instruction name (for logging purposes).
7068	*/
7069	IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
7070	{
7071	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7072	Assert(pVmcs);
7073	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7074	{
7075	Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7076	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7077	Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7078	}
7079	else
7080	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7081	NOREF(pszInstr);
7082	}
7083
7084
7085	/**
7086	* Sets up interrupt-window exiting.
7087	*
7088	* @param pVCpu The cross context virtual CPU structure.
7089	* @param pszInstr The VMX instruction name (for logging purposes).
7090	*/
7091	IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
7092	{
7093	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7094	Assert(pVmcs);
7095	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7096	{
7097	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7098	Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7099	}
7100	else
7101	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7102	NOREF(pszInstr);
7103	}
7104
7105
7106	/**
7107	* Set up the VMX-preemption timer.
7108	*
7109	* @param pVCpu The cross context virtual CPU structure.
7110	* @param pszInstr The VMX instruction name (for logging purposes).
7111	*/
7112	IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
7113	{
7114	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7115	Assert(pVmcs);
7116	if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7117	{
7118	/*
7119	* If the timer is 0, we must cause a VM-exit before executing the first
7120	* nested-guest instruction. So we can flag as though the timer has already
7121	* expired and we will check and cause a VM-exit at the right priority elsewhere
7122	* in the code.
7123	*/
7124	uint64_t uEntryTick;
7125	uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7126	if (uPreemptTimer)
7127	{
7128	int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7129	AssertRC(rc);
7130	Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7131	}
7132	else
7133	{
7134	uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7135	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7136	Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7137	}
7138
7139	pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7140	}
7141	else
7142	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7143
7144	NOREF(pszInstr);
7145	}
7146
7147
7148	/**
7149	* Injects an event using TRPM given a VM-entry interruption info. and related
7150	* fields.
7151	*
7152	* @param pVCpu The cross context virtual CPU structure.
7153	* @param pszInstr The VMX instruction name (for logging purposes).
7154	* @param uEntryIntInfo The VM-entry interruption info.
7155	* @param uErrCode The error code associated with the event if any.
7156	* @param cbInstr The VM-entry instruction length (for software
7157	* interrupts and software exceptions). Pass 0
7158	* otherwise.
7159	* @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7160	*/
7161	IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7162	uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7163	{
7164	Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7165
7166	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7167	uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7168	TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7169
7170	Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7171
7172	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7173	AssertRC(rc);
7174	Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7175
7176	if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7177	{
7178	TRPMSetErrorCode(pVCpu, uErrCode);
7179	Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7180	}
7181
7182	if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7183	{
7184	TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7185	Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7186	}
7187	else
7188	{
7189	if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7190	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7191	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7192	{
7193	TRPMSetInstrLength(pVCpu, cbInstr);
7194	Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7195	}
7196	}
7197
7198	if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7199	{
7200	TRPMSetTrapDueToIcebp(pVCpu);
7201	Log(("%s: Injecting: icebp\n", pszInstr));
7202	}
7203
7204	NOREF(pszInstr);
7205	}
7206
7207
7208	/**
7209	* Performs event injection (if any) as part of VM-entry.
7210	*
7211	* @param pVCpu The cross context virtual CPU structure.
7212	* @param pszInstr The VMX instruction name (for logging purposes).
7213	*/
7214	IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7215	{
7216	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7217
7218	/*
7219	* Inject events.
7220	* The event that is going to be made pending for injection is not subject to VMX intercepts,
7221	* thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7222	* of the current event -are- subject to intercepts, hence this flag will be flipped during
7223	* the actually delivery of this event.
7224	*
7225	* See Intel spec. 26.5 "Event Injection".
7226	*/
7227	uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7228	bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7229
7230	CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7231	if (fEntryIntInfoValid)
7232	{
7233	if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7234	{
7235	Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7236	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7237	}
7238	else
7239	iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7240	pVCpu->cpum.GstCtx.cr2);
7241
7242	/*
7243	* We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7244	*
7245	* However, we do it here on VM-entry as well because while it isn't visible to guest
7246	* software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7247	* execution using hardware-assisted VMX, it will not be try to inject the event again.
7248	*
7249	* See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7250	*/
7251	pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7252	}
7253	else
7254	{
7255	/*
7256	* Inject any pending guest debug exception.
7257	* Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7258	* See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7259	*/
7260	bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7261	if (fPendingDbgXcpt)
7262	{
7263	uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7264	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7265	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7266	iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7267	0 /* GCPtrFaultAddress */);
7268	}
7269	}
7270
7271	NOREF(pszInstr);
7272	}
7273
7274
7275	/**
7276	* Initializes all read-only VMCS fields as part of VM-entry.
7277	*
7278	* @param pVCpu The cross context virtual CPU structure.
7279	*/
7280	IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7281	{
7282	/*
7283	* Any VMCS field which we do not establish on every VM-exit but may potentially
7284	* be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7285	* specified to be undefined, needs to be initialized here.
7286	*
7287	* Thus, it is especially important to clear the Exit qualification field
7288	* since it must be zero for VM-exits where it is not used. Similarly, the
7289	* VM-exit interruption information field's valid bit needs to be cleared for
7290	* the same reasons.
7291	*/
7292	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7293	Assert(pVmcs);
7294
7295	/* 16-bit (none currently). */
7296	/* 32-bit. */
7297	pVmcs->u32RoVmInstrError = 0;
7298	pVmcs->u32RoExitReason = 0;
7299	pVmcs->u32RoExitIntInfo = 0;
7300	pVmcs->u32RoExitIntErrCode = 0;
7301	pVmcs->u32RoIdtVectoringInfo = 0;
7302	pVmcs->u32RoIdtVectoringErrCode = 0;
7303	pVmcs->u32RoExitInstrLen = 0;
7304	pVmcs->u32RoExitInstrInfo = 0;
7305
7306	/* 64-bit. */
7307	pVmcs->u64RoGuestPhysAddr.u = 0;
7308
7309	/* Natural-width. */
7310	pVmcs->u64RoExitQual.u = 0;
7311	pVmcs->u64RoIoRcx.u = 0;
7312	pVmcs->u64RoIoRsi.u = 0;
7313	pVmcs->u64RoIoRdi.u = 0;
7314	pVmcs->u64RoIoRip.u = 0;
7315	pVmcs->u64RoGuestLinearAddr.u = 0;
7316	}
7317
7318
7319	/**
7320	* VMLAUNCH/VMRESUME instruction execution worker.
7321	*
7322	* @returns Strict VBox status code.
7323	* @param pVCpu The cross context virtual CPU structure.
7324	* @param cbInstr The instruction length in bytes.
7325	* @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7326	* VMXINSTRID_VMRESUME).
7327	*
7328	* @remarks Common VMX instruction checks are already expected to by the caller,
7329	* i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7330	*/
7331	IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7332	{
7333	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7334	RT_NOREF3(pVCpu, cbInstr, uInstrId);
7335	return VINF_EM_RAW_EMULATE_INSTR;
7336	# else
7337	Assert( uInstrId == VMXINSTRID_VMLAUNCH
7338	\|\| uInstrId == VMXINSTRID_VMRESUME);
7339	const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7340
7341	/* Nested-guest intercept. */
7342	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7343	return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7344
7345	Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7346
7347	/*
7348	* Basic VM-entry checks.
7349	* The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7350	* The checks following that do not have to follow a specific order.
7351	*
7352	* See Intel spec. 26.1 "Basic VM-entry Checks".
7353	*/
7354
7355	/* CPL. */
7356	if (pVCpu->iem.s.uCpl == 0)
7357	{ /* likely */ }
7358	else
7359	{
7360	Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7361	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7362	return iemRaiseGeneralProtectionFault0(pVCpu);
7363	}
7364
7365	/* Current VMCS valid. */
7366	if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7367	{ /* likely */ }
7368	else
7369	{
7370	Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7371	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7372	iemVmxVmFailInvalid(pVCpu);
7373	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7374	return VINF_SUCCESS;
7375	}
7376
7377	/* Current VMCS is not a shadow VMCS. */
7378	if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7379	{ /* likely */ }
7380	else
7381	{
7382	Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7383	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7384	iemVmxVmFailInvalid(pVCpu);
7385	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7386	return VINF_SUCCESS;
7387	}
7388
7389	/** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7390	* use block-by-STI here which is not quite correct. */
7391	if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7392	\|\| pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7393	{ /* likely */ }
7394	else
7395	{
7396	Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7397	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7398	iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7399	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7400	return VINF_SUCCESS;
7401	}
7402
7403	if (uInstrId == VMXINSTRID_VMLAUNCH)
7404	{
7405	/* VMLAUNCH with non-clear VMCS. */
7406	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7407	{ /* likely */ }
7408	else
7409	{
7410	Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7411	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7412	iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7413	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7414	return VINF_SUCCESS;
7415	}
7416	}
7417	else
7418	{
7419	/* VMRESUME with non-launched VMCS. */
7420	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7421	{ /* likely */ }
7422	else
7423	{
7424	Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7425	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7426	iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7427	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7428	return VINF_SUCCESS;
7429	}
7430	}
7431
7432	/*
7433	* We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7434	* while entering VMX non-root mode. We do some of this while checking VM-execution
7435	* controls. The nested hypervisor should not make assumptions and cannot expect
7436	* predictable behavior if changes to these structures are made in guest memory while
7437	* executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7438	* modify them anyway as we cache them in host memory.
7439	*
7440	* See Intel spec. 24.11.4 "Software Access to Related Structures".
7441	*/
7442	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7443	Assert(pVmcs);
7444	Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7445
7446	int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7447	if (RT_SUCCESS(rc))
7448	{
7449	rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7450	if (RT_SUCCESS(rc))
7451	{
7452	/*
7453	* Initialize read-only VMCS fields before VM-entry since we don't update all of them
7454	* for every VM-exit. This needs to be done before invoking a VM-exit (even those
7455	* ones that may occur during VM-entry below).
7456	*/
7457	iemVmxVmentryInitReadOnlyFields(pVCpu);
7458
7459	/*
7460	* Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7461	* So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7462	* VM-exit when required.
7463	* See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7464	*/
7465	iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7466
7467	rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7468	if (RT_SUCCESS(rc))
7469	{
7470	/*
7471	* We've now entered nested-guest execution.
7472	*
7473	* It is important do this prior to loading the guest state because
7474	* as part of loading the guest state, PGM (and perhaps other components
7475	* in the future) relies on detecting whether VMX non-root mode has been
7476	* entered.
7477	*/
7478	pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7479
7480	rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7481	if (RT_SUCCESS(rc))
7482	{
7483	rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7484	if (RT_SUCCESS(rc))
7485	{
7486	Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7487
7488	/* VMLAUNCH instruction must update the VMCS launch state. */
7489	if (uInstrId == VMXINSTRID_VMLAUNCH)
7490	pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7491
7492	/* We would have mapped PAE PDPTEs when PAE paging is used without EPT. */
7493	bool const fPdpesMapped = !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7494	&& iemVmxVmcsIsGuestPaePagingEnabled(pVmcs);
7495
7496	/* Perform the VMX transition (PGM updates). */
7497	VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu, fPdpesMapped);
7498	if (rcStrict == VINF_SUCCESS)
7499	{ /* likely */ }
7500	else if (RT_SUCCESS(rcStrict))
7501	{
7502	Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7503	VBOXSTRICTRC_VAL(rcStrict)));
7504	rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7505	}
7506	else
7507	{
7508	Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7509	return rcStrict;
7510	}
7511
7512	/* Paranoia. */
7513	Assert(rcStrict == VINF_SUCCESS);
7514
7515	/*
7516	* The priority of potential VM-exits during VM-entry is important.
7517	* The priorities of VM-exits and events are listed from highest
7518	* to lowest as follows:
7519	*
7520	* 1. Event injection.
7521	* 2. Trap on task-switch (T flag set in TSS).
7522	* 3. TPR below threshold / APIC-write.
7523	* 4. SMI, INIT.
7524	* 5. MTF exit.
7525	* 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7526	* 7. VMX-preemption timer.
7527	* 9. NMI-window exit.
7528	* 10. NMI injection.
7529	* 11. Interrupt-window exit.
7530	* 12. Virtual-interrupt injection.
7531	* 13. Interrupt injection.
7532	* 14. Process next instruction (fetch, decode, execute).
7533	*/
7534
7535	/* Setup VMX-preemption timer. */
7536	iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7537
7538	/* Setup monitor-trap flag. */
7539	iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7540
7541	/* Setup NMI-window exiting. */
7542	iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7543
7544	/* Setup interrupt-window exiting. */
7545	iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7546
7547	/*
7548	* Inject any event that the nested hypervisor wants to inject.
7549	* Note! We cannot immediately perform the event injection here as we may have
7550	* pending PGM operations to perform due to switching page tables and/or
7551	* mode.
7552	*/
7553	iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7554
7555	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7556	/* Reschedule to IEM-only execution of the nested-guest. */
7557	Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7558	int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7559	if (rcSched != VINF_SUCCESS)
7560	iemSetPassUpStatus(pVCpu, rcSched);
7561	# endif
7562
7563	/* Finally, done. */
7564	Log3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",
7565	pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7566	pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7567	pVCpu->cpum.GstCtx.msrEFER));
7568	return VINF_SUCCESS;
7569	}
7570	return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD \| VMX_EXIT_REASON_ENTRY_FAILED,
7571	pVmcs->u64RoExitQual.u);
7572	}
7573	}
7574	return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE \| VMX_EXIT_REASON_ENTRY_FAILED,
7575	pVmcs->u64RoExitQual.u);
7576	}
7577
7578	iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7579	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7580	return VINF_SUCCESS;
7581	}
7582
7583	iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7584	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7585	return VINF_SUCCESS;
7586	# endif
7587	}
7588
7589
7590	/**
7591	* Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7592	* (causes a VM-exit) or not.
7593	*
7594	* @returns @c true if the instruction is intercepted, @c false otherwise.
7595	* @param pVCpu The cross context virtual CPU structure.
7596	* @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7597	* VMX_EXIT_WRMSR).
7598	* @param idMsr The MSR.
7599	*/
7600	IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7601	{
7602	Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7603	Assert( uExitReason == VMX_EXIT_RDMSR
7604	\|\| uExitReason == VMX_EXIT_WRMSR);
7605
7606	/* Consult the MSR bitmap if the feature is supported. */
7607	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7608	Assert(pVmcs);
7609	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7610	{
7611	uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7612	if (uExitReason == VMX_EXIT_RDMSR)
7613	return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7614	return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7615	}
7616
7617	/* Without MSR bitmaps, all MSR accesses are intercepted. */
7618	return true;
7619	}
7620
7621
7622	/**
7623	* VMREAD instruction execution worker that does not perform any validation checks.
7624	*
7625	* Callers are expected to have performed the necessary checks and to ensure the
7626	* VMREAD will succeed.
7627	*
7628	* @param pVmcs Pointer to the virtual VMCS.
7629	* @param pu64Dst Where to write the VMCS value.
7630	* @param u64VmcsField The VMCS field.
7631	*
7632	* @remarks May be called with interrupts disabled.
7633	*/
7634	IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7635	{
7636	VMXVMCSFIELD VmcsField;
7637	VmcsField.u = u64VmcsField;
7638	uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7639	uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7640	uint8_t const uWidthType = (uWidth << 2) \| uType;
7641	uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7642	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7643	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7644	AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
7645	uWidth, uType, uIndex, uIndex));
7646	AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7647
7648	/*
7649	* Read the VMCS component based on the field's effective width.
7650	*
7651	* The effective width is 64-bit fields adjusted to 32-bits if the access-type
7652	* indicates high bits (little endian).
7653	*
7654	* Note! The caller is responsible to trim the result and update registers
7655	* or memory locations are required. Here we just zero-extend to the largest
7656	* type (i.e. 64-bits).
7657	*/
7658	uint8_t const pbVmcs = (uint8_t const )pVmcs;
7659	uint8_t const *pbField = pbVmcs + offField;
7660	uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7661	switch (uEffWidth)
7662	{
7663	case VMX_VMCSFIELD_WIDTH_64BIT:
7664	case VMX_VMCSFIELD_WIDTH_NATURAL: pu64Dst = (uint64_t const *)pbField; break;
7665	case VMX_VMCSFIELD_WIDTH_32BIT: pu64Dst = (uint32_t const *)pbField; break;
7666	case VMX_VMCSFIELD_WIDTH_16BIT: pu64Dst = (uint16_t const *)pbField; break;
7667	}
7668	}
7669
7670
7671	/**
7672	* VMREAD common (memory/register) instruction execution worker.
7673	*
7674	* @returns Strict VBox status code.
7675	* @param pVCpu The cross context virtual CPU structure.
7676	* @param cbInstr The instruction length in bytes.
7677	* @param pu64Dst Where to write the VMCS value (only updated when
7678	* VINF_SUCCESS is returned).
7679	* @param u64VmcsField The VMCS field.
7680	* @param pExitInfo Pointer to the VM-exit information. Optional, can be
7681	* NULL.
7682	*/
7683	IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7684	PCVMXVEXITINFO pExitInfo)
7685	{
7686	/* Nested-guest intercept. */
7687	if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7688	&& CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7689	{
7690	if (pExitInfo)
7691	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7692	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7693	}
7694
7695	/* CPL. */
7696	if (pVCpu->iem.s.uCpl == 0)
7697	{ /* likely */ }
7698	else
7699	{
7700	Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7701	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7702	return iemRaiseGeneralProtectionFault0(pVCpu);
7703	}
7704
7705	/* VMCS pointer in root mode. */
7706	if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7707	\|\| IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7708	{ /* likely */ }
7709	else
7710	{
7711	Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7712	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7713	iemVmxVmFailInvalid(pVCpu);
7714	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7715	return VINF_SUCCESS;
7716	}
7717
7718	/* VMCS-link pointer in non-root mode. */
7719	if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7720	\|\| IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7721	{ /* likely */ }
7722	else
7723	{
7724	Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7725	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7726	iemVmxVmFailInvalid(pVCpu);
7727	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7728	return VINF_SUCCESS;
7729	}
7730
7731	/* Supported VMCS field. */
7732	if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7733	{ /* likely */ }
7734	else
7735	{
7736	Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7737	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7738	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7739	iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7740	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7741	return VINF_SUCCESS;
7742	}
7743
7744	/*
7745	* Reading from the current or shadow VMCS.
7746	*/
7747	PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7748	? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7749	: &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7750	iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7751	return VINF_SUCCESS;
7752	}
7753
7754
7755	/**
7756	* VMREAD (64-bit register) instruction execution worker.
7757	*
7758	* @returns Strict VBox status code.
7759	* @param pVCpu The cross context virtual CPU structure.
7760	* @param cbInstr The instruction length in bytes.
7761	* @param pu64Dst Where to store the VMCS field's value.
7762	* @param u64VmcsField The VMCS field.
7763	* @param pExitInfo Pointer to the VM-exit information. Optional, can be
7764	* NULL.
7765	*/
7766	IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7767	PCVMXVEXITINFO pExitInfo)
7768	{
7769	VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7770	if (rcStrict == VINF_SUCCESS)
7771	{
7772	iemVmxVmreadSuccess(pVCpu, cbInstr);
7773	return VINF_SUCCESS;
7774	}
7775
7776	Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7777	return rcStrict;
7778	}
7779
7780
7781	/**
7782	* VMREAD (32-bit register) instruction execution worker.
7783	*
7784	* @returns Strict VBox status code.
7785	* @param pVCpu The cross context virtual CPU structure.
7786	* @param cbInstr The instruction length in bytes.
7787	* @param pu32Dst Where to store the VMCS field's value.
7788	* @param u32VmcsField The VMCS field.
7789	* @param pExitInfo Pointer to the VM-exit information. Optional, can be
7790	* NULL.
7791	*/
7792	IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7793	PCVMXVEXITINFO pExitInfo)
7794	{
7795	uint64_t u64Dst;
7796	VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7797	if (rcStrict == VINF_SUCCESS)
7798	{
7799	*pu32Dst = u64Dst;
7800	iemVmxVmreadSuccess(pVCpu, cbInstr);
7801	return VINF_SUCCESS;
7802	}
7803
7804	Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7805	return rcStrict;
7806	}
7807
7808
7809	/**
7810	* VMREAD (memory) instruction execution worker.
7811	*
7812	* @returns Strict VBox status code.
7813	* @param pVCpu The cross context virtual CPU structure.
7814	* @param cbInstr The instruction length in bytes.
7815	* @param iEffSeg The effective segment register to use with @a u64Val.
7816	* Pass UINT8_MAX if it is a register access.
7817	* @param GCPtrDst The guest linear address to store the VMCS field's
7818	* value.
7819	* @param u64VmcsField The VMCS field.
7820	* @param pExitInfo Pointer to the VM-exit information. Optional, can be
7821	* NULL.
7822	*/
7823	IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7824	PCVMXVEXITINFO pExitInfo)
7825	{
7826	uint64_t u64Dst;
7827	VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7828	if (rcStrict == VINF_SUCCESS)
7829	{
7830	/*
7831	* Write the VMCS field's value to the location specified in guest-memory.
7832	*/
7833	if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7834	rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7835	else
7836	rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7837	if (rcStrict == VINF_SUCCESS)
7838	{
7839	iemVmxVmreadSuccess(pVCpu, cbInstr);
7840	return VINF_SUCCESS;
7841	}
7842
7843	Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7844	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7845	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7846	return rcStrict;
7847	}
7848
7849	Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7850	return rcStrict;
7851	}
7852
7853
7854	/**
7855	* VMWRITE instruction execution worker that does not perform any validation
7856	* checks.
7857	*
7858	* Callers are expected to have performed the necessary checks and to ensure the
7859	* VMWRITE will succeed.
7860	*
7861	* @param pVmcs Pointer to the virtual VMCS.
7862	* @param u64Val The value to write.
7863	* @param u64VmcsField The VMCS field.
7864	*
7865	* @remarks May be called with interrupts disabled.
7866	*/
7867	IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7868	{
7869	VMXVMCSFIELD VmcsField;
7870	VmcsField.u = u64VmcsField;
7871	uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7872	uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7873	uint8_t const uWidthType = (uWidth << 2) \| uType;
7874	uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7875	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7876	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7877	Assert(offField < VMX_V_VMCS_SIZE);
7878	AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7879
7880	/*
7881	* Write the VMCS component based on the field's effective width.
7882	*
7883	* The effective width is 64-bit fields adjusted to 32-bits if the access-type
7884	* indicates high bits (little endian).
7885	*/
7886	uint8_t pbVmcs = (uint8_t )pVmcs;
7887	uint8_t *pbField = pbVmcs + offField;
7888	uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7889	switch (uEffWidth)
7890	{
7891	case VMX_VMCSFIELD_WIDTH_64BIT:
7892	case VMX_VMCSFIELD_WIDTH_NATURAL: (uint64_t )pbField = u64Val; break;
7893	case VMX_VMCSFIELD_WIDTH_32BIT: (uint32_t )pbField = u64Val; break;
7894	case VMX_VMCSFIELD_WIDTH_16BIT: (uint16_t )pbField = u64Val; break;
7895	}
7896	}
7897
7898
7899	/**
7900	* VMWRITE instruction execution worker.
7901	*
7902	* @returns Strict VBox status code.
7903	* @param pVCpu The cross context virtual CPU structure.
7904	* @param cbInstr The instruction length in bytes.
7905	* @param iEffSeg The effective segment register to use with @a u64Val.
7906	* Pass UINT8_MAX if it is a register access.
7907	* @param u64Val The value to write (or guest linear address to the
7908	* value), @a iEffSeg will indicate if it's a memory
7909	* operand.
7910	* @param u64VmcsField The VMCS field.
7911	* @param pExitInfo Pointer to the VM-exit information. Optional, can be
7912	* NULL.
7913	*/
7914	IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7915	PCVMXVEXITINFO pExitInfo)
7916	{
7917	/* Nested-guest intercept. */
7918	if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7919	&& CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7920	{
7921	if (pExitInfo)
7922	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7923	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7924	}
7925
7926	/* CPL. */
7927	if (pVCpu->iem.s.uCpl == 0)
7928	{ /* likely */ }
7929	else
7930	{
7931	Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7932	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7933	return iemRaiseGeneralProtectionFault0(pVCpu);
7934	}
7935
7936	/* VMCS pointer in root mode. */
7937	if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7938	\|\| IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7939	{ /* likely */ }
7940	else
7941	{
7942	Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7943	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7944	iemVmxVmFailInvalid(pVCpu);
7945	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7946	return VINF_SUCCESS;
7947	}
7948
7949	/* VMCS-link pointer in non-root mode. */
7950	if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7951	\|\| IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7952	{ /* likely */ }
7953	else
7954	{
7955	Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7956	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7957	iemVmxVmFailInvalid(pVCpu);
7958	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7959	return VINF_SUCCESS;
7960	}
7961
7962	/* If the VMWRITE instruction references memory, access the specified memory operand. */
7963	bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7964	if (!fIsRegOperand)
7965	{
7966	/* Read the value from the specified guest memory location. */
7967	VBOXSTRICTRC rcStrict;
7968	RTGCPTR const GCPtrVal = u64Val;
7969	if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7970	rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7971	else
7972	rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7973	if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7974	{
7975	Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7976	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7977	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7978	return rcStrict;
7979	}
7980	}
7981	else
7982	Assert(!pExitInfo \|\| pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7983
7984	/* Supported VMCS field. */
7985	if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7986	{ /* likely */ }
7987	else
7988	{
7989	Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7990	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7991	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7992	iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7993	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7994	return VINF_SUCCESS;
7995	}
7996
7997	/* Read-only VMCS field. */
7998	bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
7999	if ( !fIsFieldReadOnly
8000	\|\| IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8001	{ /* likely */ }
8002	else
8003	{
8004	Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8005	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8006	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8007	iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8008	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8009	return VINF_SUCCESS;
8010	}
8011
8012	/*
8013	* Write to the current or shadow VMCS.
8014	*/
8015	bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8016	PVMXVVMCS pVmcs = !fInVmxNonRootMode
8017	? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8018	: &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8019	iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8020
8021	/* Notify HM that the VMCS content might have changed. */
8022	if (!fInVmxNonRootMode)
8023	HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8024
8025	iemVmxVmSucceed(pVCpu);
8026	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8027	return VINF_SUCCESS;
8028	}
8029
8030
8031	/**
8032	* VMCLEAR instruction execution worker.
8033	*
8034	* @returns Strict VBox status code.
8035	* @param pVCpu The cross context virtual CPU structure.
8036	* @param cbInstr The instruction length in bytes.
8037	* @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8038	* @param GCPtrVmcs The linear address of the VMCS pointer.
8039	* @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8040	*
8041	* @remarks Common VMX instruction checks are already expected to by the caller,
8042	* i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8043	*/
8044	IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8045	PCVMXVEXITINFO pExitInfo)
8046	{
8047	/* Nested-guest intercept. */
8048	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8049	{
8050	if (pExitInfo)
8051	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8052	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8053	}
8054
8055	Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8056
8057	/* CPL. */
8058	if (pVCpu->iem.s.uCpl == 0)
8059	{ /* likely */ }
8060	else
8061	{
8062	Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8063	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8064	return iemRaiseGeneralProtectionFault0(pVCpu);
8065	}
8066
8067	/* Get the VMCS pointer from the location specified by the source memory operand. */
8068	RTGCPHYS GCPhysVmcs;
8069	VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8070	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8071	{ /* likely */ }
8072	else
8073	{
8074	Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8075	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8076	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8077	return rcStrict;
8078	}
8079
8080	/* VMCS pointer alignment. */
8081	if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8082	{ /* likely */ }
8083	else
8084	{
8085	Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8086	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8087	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8088	iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8089	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8090	return VINF_SUCCESS;
8091	}
8092
8093	/* VMCS physical-address width limits. */
8094	if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8095	{ /* likely */ }
8096	else
8097	{
8098	Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8099	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8100	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8101	iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8102	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8103	return VINF_SUCCESS;
8104	}
8105
8106	/* VMCS is not the VMXON region. */
8107	if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8108	{ /* likely */ }
8109	else
8110	{
8111	Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8112	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8113	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8114	iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8115	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8116	return VINF_SUCCESS;
8117	}
8118
8119	/* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8120	restriction imposed by our implementation. */
8121	if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8122	{ /* likely */ }
8123	else
8124	{
8125	Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8126	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8127	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8128	iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8129	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8130	return VINF_SUCCESS;
8131	}
8132
8133	/*
8134	* VMCLEAR allows committing and clearing any valid VMCS pointer.
8135	*
8136	* If the current VMCS is the one being cleared, set its state to 'clear' and commit
8137	* to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8138	* to 'clear'.
8139	*/
8140	uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8141	if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8142	&& IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8143	{
8144	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8145	iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8146	IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8147	}
8148	else
8149	{
8150	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8151	rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8152	(const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8153	if (RT_FAILURE(rcStrict))
8154	return rcStrict;
8155	}
8156
8157	iemVmxVmSucceed(pVCpu);
8158	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8159	return VINF_SUCCESS;
8160	}
8161
8162
8163	/**
8164	* VMPTRST instruction execution worker.
8165	*
8166	* @returns Strict VBox status code.
8167	* @param pVCpu The cross context virtual CPU structure.
8168	* @param cbInstr The instruction length in bytes.
8169	* @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8170	* @param GCPtrVmcs The linear address of where to store the current VMCS
8171	* pointer.
8172	* @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8173	*
8174	* @remarks Common VMX instruction checks are already expected to by the caller,
8175	* i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8176	*/
8177	IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8178	PCVMXVEXITINFO pExitInfo)
8179	{
8180	/* Nested-guest intercept. */
8181	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8182	{
8183	if (pExitInfo)
8184	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8185	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8186	}
8187
8188	Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8189
8190	/* CPL. */
8191	if (pVCpu->iem.s.uCpl == 0)
8192	{ /* likely */ }
8193	else
8194	{
8195	Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8196	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8197	return iemRaiseGeneralProtectionFault0(pVCpu);
8198	}
8199
8200	/* Set the VMCS pointer to the location specified by the destination memory operand. */
8201	AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8202	VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8203	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8204	{
8205	iemVmxVmSucceed(pVCpu);
8206	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8207	return rcStrict;
8208	}
8209
8210	Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8211	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8212	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8213	return rcStrict;
8214	}
8215
8216
8217	/**
8218	* VMPTRLD instruction execution worker.
8219	*
8220	* @returns Strict VBox status code.
8221	* @param pVCpu The cross context virtual CPU structure.
8222	* @param cbInstr The instruction length in bytes.
8223	* @param GCPtrVmcs The linear address of the current VMCS pointer.
8224	* @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8225	*
8226	* @remarks Common VMX instruction checks are already expected to by the caller,
8227	* i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8228	*/
8229	IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8230	PCVMXVEXITINFO pExitInfo)
8231	{
8232	/* Nested-guest intercept. */
8233	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8234	{
8235	if (pExitInfo)
8236	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8237	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8238	}
8239
8240	Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8241
8242	/* CPL. */
8243	if (pVCpu->iem.s.uCpl == 0)
8244	{ /* likely */ }
8245	else
8246	{
8247	Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8248	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8249	return iemRaiseGeneralProtectionFault0(pVCpu);
8250	}
8251
8252	/* Get the VMCS pointer from the location specified by the source memory operand. */
8253	RTGCPHYS GCPhysVmcs;
8254	VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8255	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8256	{ /* likely */ }
8257	else
8258	{
8259	Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8260	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8261	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8262	return rcStrict;
8263	}
8264
8265	/* VMCS pointer alignment. */
8266	if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8267	{ /* likely */ }
8268	else
8269	{
8270	Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8271	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8272	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8273	iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8274	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8275	return VINF_SUCCESS;
8276	}
8277
8278	/* VMCS physical-address width limits. */
8279	if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8280	{ /* likely */ }
8281	else
8282	{
8283	Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8284	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8285	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8286	iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8287	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8288	return VINF_SUCCESS;
8289	}
8290
8291	/* VMCS is not the VMXON region. */
8292	if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8293	{ /* likely */ }
8294	else
8295	{
8296	Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8297	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8298	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8299	iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8300	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8301	return VINF_SUCCESS;
8302	}
8303
8304	/* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8305	restriction imposed by our implementation. */
8306	if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8307	{ /* likely */ }
8308	else
8309	{
8310	Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8311	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8312	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8313	iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8314	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8315	return VINF_SUCCESS;
8316	}
8317
8318	/* Read just the VMCS revision from the VMCS. */
8319	VMXVMCSREVID VmcsRevId;
8320	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8321	if (RT_SUCCESS(rc))
8322	{ /* likely */ }
8323	else
8324	{
8325	Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8326	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8327	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8328	return rc;
8329	}
8330
8331	/*
8332	* Verify the VMCS revision specified by the guest matches what we reported to the guest.
8333	* Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8334	*/
8335	if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8336	&& ( !VmcsRevId.n.fIsShadowVmcs
8337	\|\| IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8338	{ /* likely */ }
8339	else
8340	{
8341	if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8342	{
8343	Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8344	VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8345	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8346	iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8347	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8348	return VINF_SUCCESS;
8349	}
8350
8351	Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8352	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8353	iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8354	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8355	return VINF_SUCCESS;
8356	}
8357
8358	/*
8359	* We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8360	* the cache of an existing, current VMCS back to guest memory before loading a new,
8361	* different current VMCS.
8362	*/
8363	if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8364	{
8365	if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8366	{
8367	iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8368	IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8369	}
8370
8371	/* Set the new VMCS as the current VMCS and read it from guest memory. */
8372	IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8373	rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8374	if (RT_SUCCESS(rc))
8375	{
8376	/* Notify HM that a new, current VMCS is loaded. */
8377	HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8378	}
8379	else
8380	{
8381	Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8382	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8383	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8384	return rc;
8385	}
8386	}
8387
8388	Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8389	iemVmxVmSucceed(pVCpu);
8390	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8391	return VINF_SUCCESS;
8392	}
8393
8394
8395	/**
8396	* INVVPID instruction execution worker.
8397	*
8398	* @returns Strict VBox status code.
8399	* @param pVCpu The cross context virtual CPU structure.
8400	* @param cbInstr The instruction length in bytes.
8401	* @param iEffSeg The segment of the invvpid descriptor.
8402	* @param GCPtrInvvpidDesc The address of invvpid descriptor.
8403	* @param u64InvvpidType The invalidation type.
8404	* @param pExitInfo Pointer to the VM-exit information. Optional, can be
8405	* NULL.
8406	*
8407	* @remarks Common VMX instruction checks are already expected to by the caller,
8408	* i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8409	*/
8410	IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8411	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8412	{
8413	/* Check if INVVPID instruction is supported, otherwise raise #UD. */
8414	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8415	return iemRaiseUndefinedOpcode(pVCpu);
8416
8417	/* Nested-guest intercept. */
8418	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8419	{
8420	if (pExitInfo)
8421	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8422	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8423	}
8424
8425	/* CPL. */
8426	if (pVCpu->iem.s.uCpl != 0)
8427	{
8428	Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8429	return iemRaiseGeneralProtectionFault0(pVCpu);
8430	}
8431
8432	/*
8433	* Validate INVVPID invalidation type.
8434	*
8435	* The instruction specifies exactly ONE of the supported invalidation types.
8436	*
8437	* Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8438	* supported. In theory, it's possible for a CPU to not support flushing individual
8439	* addresses but all the other types or any other combination. We do not take any
8440	* shortcuts here by assuming the types we currently expose to the guest.
8441	*/
8442	uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8443	uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8444	uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8445	uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8446	uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8447	if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8448	\|\| (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8449	\|\| (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8450	\|\| (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8451	{ /* likely */ }
8452	else
8453	{
8454	Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8455	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8456	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8457	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8458	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8459	return VINF_SUCCESS;
8460	}
8461
8462	/*
8463	* Fetch the invvpid descriptor from guest memory.
8464	*/
8465	RTUINT128U uDesc;
8466	VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8467	if (rcStrict == VINF_SUCCESS)
8468	{
8469	/*
8470	* Validate the descriptor.
8471	*/
8472	if (uDesc.s.Lo > 0xfff)
8473	{
8474	Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8475	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8476	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8477	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8478	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8479	return VINF_SUCCESS;
8480	}
8481
8482	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8483	RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8484	uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8485	uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8486	switch (u64InvvpidType)
8487	{
8488	case VMXTLBFLUSHVPID_INDIV_ADDR:
8489	{
8490	if (uVpid != 0)
8491	{
8492	if (IEM_IS_CANONICAL(GCPtrInvAddr))
8493	{
8494	/* Invalidate mappings for the linear address tagged with VPID. */
8495	/** @todo PGM support for VPID? Currently just flush everything. */
8496	PGMFlushTLB(pVCpu, uCr3, true /* fGlobal /, false / fPdpesMapped */);
8497	iemVmxVmSucceed(pVCpu);
8498	}
8499	else
8500	{
8501	Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8502	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8503	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8504	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8505	}
8506	}
8507	else
8508	{
8509	Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8510	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8511	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8512	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8513	}
8514	break;
8515	}
8516
8517	case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8518	{
8519	if (uVpid != 0)
8520	{
8521	/* Invalidate all mappings with VPID. */
8522	/** @todo PGM support for VPID? Currently just flush everything. */
8523	PGMFlushTLB(pVCpu, uCr3, true /* fGlobal /, false / fPdpesMapped */);
8524	iemVmxVmSucceed(pVCpu);
8525	}
8526	else
8527	{
8528	Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8529	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8530	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8531	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8532	}
8533	break;
8534	}
8535
8536	case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8537	{
8538	/* Invalidate all mappings with non-zero VPIDs. */
8539	/** @todo PGM support for VPID? Currently just flush everything. */
8540	PGMFlushTLB(pVCpu, uCr3, true /* fGlobal /, false / fPdpesMapped */);
8541	iemVmxVmSucceed(pVCpu);
8542	break;
8543	}
8544
8545	case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8546	{
8547	if (uVpid != 0)
8548	{
8549	/* Invalidate all mappings with VPID except global translations. */
8550	/** @todo PGM support for VPID? Currently just flush everything. */
8551	PGMFlushTLB(pVCpu, uCr3, true /* fGlobal /, false / fPdpesMapped */);
8552	iemVmxVmSucceed(pVCpu);
8553	}
8554	else
8555	{
8556	Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8557	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8558	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8559	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8560	}
8561	break;
8562	}
8563	IEM_NOT_REACHED_DEFAULT_CASE_RET();
8564	}
8565	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8566	}
8567	return rcStrict;
8568	}
8569
8570
8571	/**
8572	* VMXON instruction execution worker.
8573	*
8574	* @returns Strict VBox status code.
8575	* @param pVCpu The cross context virtual CPU structure.
8576	* @param cbInstr The instruction length in bytes.
8577	* @param iEffSeg The effective segment register to use with @a
8578	* GCPtrVmxon.
8579	* @param GCPtrVmxon The linear address of the VMXON pointer.
8580	* @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8581	*
8582	* @remarks Common VMX instruction checks are already expected to by the caller,
8583	* i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8584	*/
8585	IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8586	PCVMXVEXITINFO pExitInfo)
8587	{
8588	if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8589	{
8590	/* CPL. */
8591	if (pVCpu->iem.s.uCpl == 0)
8592	{ /* likely */ }
8593	else
8594	{
8595	Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8596	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8597	return iemRaiseGeneralProtectionFault0(pVCpu);
8598	}
8599
8600	/* A20M (A20 Masked) mode. */
8601	if (PGMPhysIsA20Enabled(pVCpu))
8602	{ /* likely */ }
8603	else
8604	{
8605	Log(("vmxon: A20M mode -> #GP(0)\n"));
8606	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8607	return iemRaiseGeneralProtectionFault0(pVCpu);
8608	}
8609
8610	/* CR0. */
8611	{
8612	/* CR0 MB1 bits. */
8613	uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8614	if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8615	{ /* likely */ }
8616	else
8617	{
8618	Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8619	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8620	return iemRaiseGeneralProtectionFault0(pVCpu);
8621	}
8622
8623	/* CR0 MBZ bits. */
8624	uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8625	if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8626	{ /* likely */ }
8627	else
8628	{
8629	Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8630	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8631	return iemRaiseGeneralProtectionFault0(pVCpu);
8632	}
8633	}
8634
8635	/* CR4. */
8636	{
8637	/* CR4 MB1 bits. */
8638	uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8639	if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8640	{ /* likely */ }
8641	else
8642	{
8643	Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8644	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8645	return iemRaiseGeneralProtectionFault0(pVCpu);
8646	}
8647
8648	/* CR4 MBZ bits. */
8649	uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8650	if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8651	{ /* likely */ }
8652	else
8653	{
8654	Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8655	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8656	return iemRaiseGeneralProtectionFault0(pVCpu);
8657	}
8658	}
8659
8660	/* Feature control MSR's LOCK and VMXON bits. */
8661	uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
8662	if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON))
8663	== (MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON))
8664	{ /* likely */ }
8665	else
8666	{
8667	Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8668	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8669	return iemRaiseGeneralProtectionFault0(pVCpu);
8670	}
8671
8672	/* Get the VMXON pointer from the location specified by the source memory operand. */
8673	RTGCPHYS GCPhysVmxon;
8674	VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8675	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8676	{ /* likely */ }
8677	else
8678	{
8679	Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8680	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8681	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8682	return rcStrict;
8683	}
8684
8685	/* VMXON region pointer alignment. */
8686	if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8687	{ /* likely */ }
8688	else
8689	{
8690	Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8691	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8692	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8693	iemVmxVmFailInvalid(pVCpu);
8694	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8695	return VINF_SUCCESS;
8696	}
8697
8698	/* VMXON physical-address width limits. */
8699	if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8700	{ /* likely */ }
8701	else
8702	{
8703	Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8704	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8705	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8706	iemVmxVmFailInvalid(pVCpu);
8707	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8708	return VINF_SUCCESS;
8709	}
8710
8711	/* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8712	restriction imposed by our implementation. */
8713	if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8714	{ /* likely */ }
8715	else
8716	{
8717	Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8718	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8719	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8720	iemVmxVmFailInvalid(pVCpu);
8721	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8722	return VINF_SUCCESS;
8723	}
8724
8725	/* Read the VMCS revision ID from the VMXON region. */
8726	VMXVMCSREVID VmcsRevId;
8727	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8728	if (RT_SUCCESS(rc))
8729	{ /* likely */ }
8730	else
8731	{
8732	Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8733	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8734	return rc;
8735	}
8736
8737	/* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8738	if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8739	{ /* likely */ }
8740	else
8741	{
8742	/* Revision ID mismatch. */
8743	if (!VmcsRevId.n.fIsShadowVmcs)
8744	{
8745	Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8746	VmcsRevId.n.u31RevisionId));
8747	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8748	iemVmxVmFailInvalid(pVCpu);
8749	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8750	return VINF_SUCCESS;
8751	}
8752
8753	/* Shadow VMCS disallowed. */
8754	Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8755	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8756	iemVmxVmFailInvalid(pVCpu);
8757	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8758	return VINF_SUCCESS;
8759	}
8760
8761	/*
8762	* Record that we're in VMX operation, block INIT, block and disable A20M.
8763	*/
8764	pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8765	IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8766	pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8767
8768	/* Clear address-range monitoring. */
8769	EMMonitorWaitClear(pVCpu);
8770	/** @todo NSTVMX: Intel PT. */
8771
8772	iemVmxVmSucceed(pVCpu);
8773	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8774	return VINF_SUCCESS;
8775	}
8776	else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8777	{
8778	/* Nested-guest intercept. */
8779	if (pExitInfo)
8780	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8781	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8782	}
8783
8784	Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8785
8786	/* CPL. */
8787	if (pVCpu->iem.s.uCpl > 0)
8788	{
8789	Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8790	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8791	return iemRaiseGeneralProtectionFault0(pVCpu);
8792	}
8793
8794	/* VMXON when already in VMX root mode. */
8795	iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8796	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8797	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8798	return VINF_SUCCESS;
8799	}
8800
8801
8802	/**
8803	* Implements 'VMXOFF'.
8804	*
8805	* @remarks Common VMX instruction checks are already expected to by the caller,
8806	* i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8807	*/
8808	IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8809	{
8810	/* Nested-guest intercept. */
8811	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8812	return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8813
8814	/* CPL. */
8815	if (pVCpu->iem.s.uCpl == 0)
8816	{ /* likely */ }
8817	else
8818	{
8819	Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8820	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8821	return iemRaiseGeneralProtectionFault0(pVCpu);
8822	}
8823
8824	/* Dual monitor treatment of SMIs and SMM. */
8825	uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8826	if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8827	{ /* likely */ }
8828	else
8829	{
8830	iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8831	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8832	return VINF_SUCCESS;
8833	}
8834
8835	/* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8836	pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8837	Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8838
8839	if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8840	{ /** @todo NSTVMX: Unblock SMI. */ }
8841
8842	EMMonitorWaitClear(pVCpu);
8843	/** @todo NSTVMX: Unblock and enable A20M. */
8844
8845	iemVmxVmSucceed(pVCpu);
8846	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8847	return VINF_SUCCESS;
8848	}
8849
8850
8851	/**
8852	* Implements 'VMXON'.
8853	*/
8854	IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8855	{
8856	return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8857	}
8858
8859
8860	/**
8861	* Implements 'VMLAUNCH'.
8862	*/
8863	IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8864	{
8865	return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8866	}
8867
8868
8869	/**
8870	* Implements 'VMRESUME'.
8871	*/
8872	IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8873	{
8874	return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8875	}
8876
8877
8878	/**
8879	* Implements 'VMPTRLD'.
8880	*/
8881	IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8882	{
8883	return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8884	}
8885
8886
8887	/**
8888	* Implements 'VMPTRST'.
8889	*/
8890	IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8891	{
8892	return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8893	}
8894
8895
8896	/**
8897	* Implements 'VMCLEAR'.
8898	*/
8899	IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8900	{
8901	return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8902	}
8903
8904
8905	/**
8906	* Implements 'VMWRITE' register.
8907	*/
8908	IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8909	{
8910	return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg /, u64Val, u64VmcsField, NULL / pExitInfo */);
8911	}
8912
8913
8914	/**
8915	* Implements 'VMWRITE' memory.
8916	*/
8917	IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8918	{
8919	return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8920	}
8921
8922
8923	/**
8924	* Implements 'VMREAD' register (64-bit).
8925	*/
8926	IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8927	{
8928	return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8929	}
8930
8931
8932	/**
8933	* Implements 'VMREAD' register (32-bit).
8934	*/
8935	IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8936	{
8937	return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8938	}
8939
8940
8941	/**
8942	* Implements 'VMREAD' memory, 64-bit register.
8943	*/
8944	IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8945	{
8946	return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8947	}
8948
8949
8950	/**
8951	* Implements 'VMREAD' memory, 32-bit register.
8952	*/
8953	IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8954	{
8955	return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8956	}
8957
8958
8959	/**
8960	* Implements 'INVVPID'.
8961	*/
8962	IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8963	{
8964	return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8965	}
8966
8967
8968	/**
8969	* Implements VMX's implementation of PAUSE.
8970	*/
8971	IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8972	{
8973	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8974	{
8975	VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8976	if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8977	return rcStrict;
8978	}
8979
8980	/*
8981	* Outside VMX non-root operation or if the PAUSE instruction does not cause
8982	* a VM-exit, the instruction operates normally.
8983	*/
8984	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8985	return VINF_SUCCESS;
8986	}
8987
8988	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8989
8990
8991	/**
8992	* Implements 'VMCALL'.
8993	*/
8994	IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8995	{
8996	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8997	/* Nested-guest intercept. */
8998	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8999	return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9000	#endif
9001
9002	/* Join forces with vmmcall. */
9003	return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9004	}
9005

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 92566

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