VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 92685

Last change on this file since 92685 was 92685, checked in by vboxsync, 3 years ago

VMM: Nested VMX: bugref:10092 Started with constructing EPT-violation VM-exit for iemInitDecoderAndPrefetchOpcodes.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 92685 2021-12-02 05:59:39Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason and logs. */
156# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 } while (0)
163
164/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
165# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
166 do \
167 { \
168 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
169 return VERR_VMX_VMEXIT_FAILED; \
170 } while (0)
171
172
173/*********************************************************************************************************************************
174* Global Variables *
175*********************************************************************************************************************************/
176/** @todo NSTVMX: The following VM-exit intercepts are pending:
177 * VMX_EXIT_IO_SMI
178 * VMX_EXIT_SMI
179 * VMX_EXIT_GETSEC
180 * VMX_EXIT_RSM
181 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
182 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
183 * VMX_EXIT_EPT_VIOLATION
184 * VMX_EXIT_EPT_MISCONFIG
185 * VMX_EXIT_INVEPT
186 * VMX_EXIT_RDRAND
187 * VMX_EXIT_VMFUNC
188 * VMX_EXIT_ENCLS
189 * VMX_EXIT_RDSEED
190 * VMX_EXIT_PML_FULL
191 * VMX_EXIT_XSAVES
192 * VMX_EXIT_XRSTORS
193 */
194/**
195 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
196 *
197 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
198 * second dimension is the Index, see VMXVMCSFIELD.
199 */
200uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
201{
202 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
203 {
204 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
205 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
206 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
207 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
209 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
210 /* 27 */ UINT16_MAX,
211 },
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
213 {
214 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
215 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
216 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
217 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
218 },
219 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
220 {
221 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
222 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
223 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
224 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
225 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
226 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
227 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
228 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
229 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
230 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
231 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
232 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
233 /* 26-27 */ UINT16_MAX, UINT16_MAX
234 },
235 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
236 {
237 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
238 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
239 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
240 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
241 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
242 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
243 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
244 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
245 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
246 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
247 },
248 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
249 {
250 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
251 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
252 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
253 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
254 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
255 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
256 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
257 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
258 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
259 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
260 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
261 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
262 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
263 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
264 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
265 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
266 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
267 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
268 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
269 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
270 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
271 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
272 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
273 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
274 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
275 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
276 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
277 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
278 },
279 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
280 {
281 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
282 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
283 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
284 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
285 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
286 },
287 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
288 {
289 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
290 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
291 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
292 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
293 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
294 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
295 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
296 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
297 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
298 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
299 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
300 /* 11 */ UINT16_MAX,
301 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
302 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
303 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
304 },
305 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
306 {
307 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
308 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
309 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
310 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
311 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
312 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
313 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
314 },
315 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
316 {
317 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
318 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
319 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
320 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
321 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
322 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
323 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
324 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
325 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
326 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
327 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
328 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
329 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
330 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
331 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
332 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
333 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
334 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
335 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 26-27 */ UINT16_MAX, UINT16_MAX
337 },
338 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
339 {
340 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
341 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
342 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
343 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
344 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
345 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
346 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
347 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
348 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
349 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
350 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
351 },
352 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
353 {
354 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
355 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
356 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
357 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
358 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
359 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
360 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
361 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
362 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
363 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
364 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
365 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
366 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
367 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
368 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
369 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
370 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
371 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
372 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
373 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
374 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
375 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
376 /* 22 */ UINT16_MAX,
377 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
378 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
379 },
380 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
381 {
382 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
383 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
386 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
387 },
388 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
389 {
390 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
391 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
392 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
393 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
394 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
395 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
396 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
397 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
398 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
399 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
400 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
401 },
402 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
403 {
404 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
405 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
406 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
407 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
408 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
409 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
410 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
411 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
412 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
413 },
414 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
415 {
416 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
417 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
418 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
419 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
420 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
421 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
422 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
423 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
424 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
425 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
426 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
427 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
428 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
429 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
430 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
431 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
432 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
433 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
434 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
435 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
436 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
437 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
438 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
439 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
440 },
441 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
442 {
443 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
444 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
445 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
446 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
447 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
448 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
449 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
450 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
451 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
452 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
453 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
454 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
455 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
456 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
457 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
458 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
459 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
460 }
461};
462
463
464/**
465 * Gets a host selector from the VMCS.
466 *
467 * @param pVmcs Pointer to the virtual VMCS.
468 * @param iSelReg The index of the segment register (X86_SREG_XXX).
469 */
470DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
471{
472 Assert(iSegReg < X86_SREG_COUNT);
473 RTSEL HostSel;
474 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
475 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
476 uint8_t const uWidthType = (uWidth << 2) | uType;
477 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
478 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
479 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
480 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
481 uint8_t const *pbField = pbVmcs + offField;
482 HostSel = *(uint16_t *)pbField;
483 return HostSel;
484}
485
486
487/**
488 * Sets a guest segment register in the VMCS.
489 *
490 * @param pVmcs Pointer to the virtual VMCS.
491 * @param iSegReg The index of the segment register (X86_SREG_XXX).
492 * @param pSelReg Pointer to the segment register.
493 */
494IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
495{
496 Assert(pSelReg);
497 Assert(iSegReg < X86_SREG_COUNT);
498
499 /* Selector. */
500 {
501 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
502 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
503 uint8_t const uWidthType = (uWidth << 2) | uType;
504 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
505 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
506 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
507 uint8_t *pbVmcs = (uint8_t *)pVmcs;
508 uint8_t *pbField = pbVmcs + offField;
509 *(uint16_t *)pbField = pSelReg->Sel;
510 }
511
512 /* Limit. */
513 {
514 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
515 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
516 uint8_t const uWidthType = (uWidth << 2) | uType;
517 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
518 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
519 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
520 uint8_t *pbVmcs = (uint8_t *)pVmcs;
521 uint8_t *pbField = pbVmcs + offField;
522 *(uint32_t *)pbField = pSelReg->u32Limit;
523 }
524
525 /* Base. */
526 {
527 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
528 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
529 uint8_t const uWidthType = (uWidth << 2) | uType;
530 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
531 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
532 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
533 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
534 uint8_t const *pbField = pbVmcs + offField;
535 *(uint64_t *)pbField = pSelReg->u64Base;
536 }
537
538 /* Attributes. */
539 {
540 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
541 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
542 | X86DESCATTR_UNUSABLE;
543 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
544 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
545 uint8_t const uWidthType = (uWidth << 2) | uType;
546 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
547 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
548 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
549 uint8_t *pbVmcs = (uint8_t *)pVmcs;
550 uint8_t *pbField = pbVmcs + offField;
551 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
552 }
553}
554
555
556/**
557 * Gets a guest segment register from the VMCS.
558 *
559 * @returns VBox status code.
560 * @param pVmcs Pointer to the virtual VMCS.
561 * @param iSegReg The index of the segment register (X86_SREG_XXX).
562 * @param pSelReg Where to store the segment register (only updated when
563 * VINF_SUCCESS is returned).
564 *
565 * @remarks Warning! This does not validate the contents of the retrieved segment
566 * register.
567 */
568IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
569{
570 Assert(pSelReg);
571 Assert(iSegReg < X86_SREG_COUNT);
572
573 /* Selector. */
574 uint16_t u16Sel;
575 {
576 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
577 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
578 uint8_t const uWidthType = (uWidth << 2) | uType;
579 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
580 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
581 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
582 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
583 uint8_t const *pbField = pbVmcs + offField;
584 u16Sel = *(uint16_t *)pbField;
585 }
586
587 /* Limit. */
588 uint32_t u32Limit;
589 {
590 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
591 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
592 uint8_t const uWidthType = (uWidth << 2) | uType;
593 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
594 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
595 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
596 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
597 uint8_t const *pbField = pbVmcs + offField;
598 u32Limit = *(uint32_t *)pbField;
599 }
600
601 /* Base. */
602 uint64_t u64Base;
603 {
604 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
605 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
606 uint8_t const uWidthType = (uWidth << 2) | uType;
607 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
608 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
609 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
610 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
611 uint8_t const *pbField = pbVmcs + offField;
612 u64Base = *(uint64_t *)pbField;
613 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
614 }
615
616 /* Attributes. */
617 uint32_t u32Attr;
618 {
619 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
620 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
621 uint8_t const uWidthType = (uWidth << 2) | uType;
622 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
623 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
624 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
625 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
626 uint8_t const *pbField = pbVmcs + offField;
627 u32Attr = *(uint32_t *)pbField;
628 }
629
630 pSelReg->Sel = u16Sel;
631 pSelReg->ValidSel = u16Sel;
632 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
633 pSelReg->u32Limit = u32Limit;
634 pSelReg->u64Base = u64Base;
635 pSelReg->Attr.u = u32Attr;
636 return VINF_SUCCESS;
637}
638
639
640/**
641 * Converts an IEM exception event type to a VMX event type.
642 *
643 * @returns The VMX event type.
644 * @param uVector The interrupt / exception vector.
645 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
646 */
647DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
648{
649 /* Paranoia (callers may use these interchangeably). */
650 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
651 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
652 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
653 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
654 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
655 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
656 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
657 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
658 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
659 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
660 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
661 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
662
663 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
664 {
665 if (uVector == X86_XCPT_NMI)
666 return VMX_EXIT_INT_INFO_TYPE_NMI;
667 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
668 }
669
670 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
671 {
672 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
673 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
674 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
675 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
676 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
677 }
678
679 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
680 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
681}
682
683
684/**
685 * Determines whether the guest is using PAE paging given the VMCS.
686 *
687 * @returns @c true if PAE paging mode is used, @c false otherwise.
688 * @param pVmcs Pointer to the virtual VMCS.
689 */
690DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
691{
692 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
693 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
694 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
695}
696
697
698/**
699 * Sets the Exit qualification VMCS field.
700 *
701 * @param pVCpu The cross context virtual CPU structure.
702 * @param u64ExitQual The Exit qualification.
703 */
704DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
705{
706 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
707}
708
709
710/**
711 * Sets the VM-exit interruption information field.
712 *
713 * @param pVCpu The cross context virtual CPU structure.
714 * @param uExitIntInfo The VM-exit interruption information.
715 */
716DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
717{
718 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
719}
720
721
722/**
723 * Sets the VM-exit interruption error code.
724 *
725 * @param pVCpu The cross context virtual CPU structure.
726 * @param uErrCode The error code.
727 */
728DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
729{
730 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
731}
732
733
734/**
735 * Sets the IDT-vectoring information field.
736 *
737 * @param pVCpu The cross context virtual CPU structure.
738 * @param uIdtVectorInfo The IDT-vectoring information.
739 */
740DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
741{
742 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
743}
744
745
746/**
747 * Sets the IDT-vectoring error code field.
748 *
749 * @param pVCpu The cross context virtual CPU structure.
750 * @param uErrCode The error code.
751 */
752DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
753{
754 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
755}
756
757
758/**
759 * Sets the VM-exit guest-linear address VMCS field.
760 *
761 * @param pVCpu The cross context virtual CPU structure.
762 * @param uGuestLinearAddr The VM-exit guest-linear address.
763 */
764DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
765{
766 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
767}
768
769
770/**
771 * Sets the VM-exit guest-physical address VMCS field.
772 *
773 * @param pVCpu The cross context virtual CPU structure.
774 * @param uGuestPhysAddr The VM-exit guest-physical address.
775 */
776DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
777{
778 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
779}
780
781
782/**
783 * Sets the VM-exit instruction length VMCS field.
784 *
785 * @param pVCpu The cross context virtual CPU structure.
786 * @param cbInstr The VM-exit instruction length in bytes.
787 *
788 * @remarks Callers may clear this field to 0. Hence, this function does not check
789 * the validity of the instruction length.
790 */
791DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
792{
793 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
794}
795
796
797/**
798 * Sets the VM-exit instruction info. VMCS field.
799 *
800 * @param pVCpu The cross context virtual CPU structure.
801 * @param uExitInstrInfo The VM-exit instruction information.
802 */
803DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
804{
805 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
806}
807
808
809/**
810 * Sets the guest pending-debug exceptions field.
811 *
812 * @param pVCpu The cross context virtual CPU structure.
813 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
814 */
815DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
816{
817 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
818 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
819}
820
821
822/**
823 * Implements VMSucceed for VMX instruction success.
824 *
825 * @param pVCpu The cross context virtual CPU structure.
826 */
827DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
828{
829 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
830}
831
832
833/**
834 * Implements VMFailInvalid for VMX instruction failure.
835 *
836 * @param pVCpu The cross context virtual CPU structure.
837 */
838DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
839{
840 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
841}
842
843
844/**
845 * Implements VMFail for VMX instruction failure.
846 *
847 * @param pVCpu The cross context virtual CPU structure.
848 * @param enmInsErr The VM instruction error.
849 */
850DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
851{
852 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
853}
854
855
856/**
857 * Checks if the given auto-load/store MSR area count is valid for the
858 * implementation.
859 *
860 * @returns @c true if it's within the valid limit, @c false otherwise.
861 * @param pVCpu The cross context virtual CPU structure.
862 * @param uMsrCount The MSR area count to check.
863 */
864DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
865{
866 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
867 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
868 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
869 if (uMsrCount <= cMaxSupportedMsrs)
870 return true;
871 return false;
872}
873
874
875/**
876 * Flushes the current VMCS contents back to guest memory.
877 *
878 * @returns VBox status code.
879 * @param pVCpu The cross context virtual CPU structure.
880 */
881DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
882{
883 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
884 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
885 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
886 return rc;
887}
888
889
890/**
891 * Populates the current VMCS contents from guest memory.
892 *
893 * @returns VBox status code.
894 * @param pVCpu The cross context virtual CPU structure.
895 */
896DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
897{
898 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
899 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
900 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
901 return rc;
902}
903
904
905/**
906 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
907 *
908 * @param pVCpu The cross context virtual CPU structure.
909 */
910DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
911{
912 iemVmxVmSucceed(pVCpu);
913 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
914}
915
916
917/**
918 * Gets the instruction diagnostic for segment base checks during VM-entry of a
919 * nested-guest.
920 *
921 * @param iSegReg The segment index (X86_SREG_XXX).
922 */
923IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
924{
925 switch (iSegReg)
926 {
927 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
928 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
929 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
930 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
931 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
932 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
933 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
934 }
935}
936
937
938/**
939 * Gets the instruction diagnostic for segment base checks during VM-entry of a
940 * nested-guest that is in Virtual-8086 mode.
941 *
942 * @param iSegReg The segment index (X86_SREG_XXX).
943 */
944IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
945{
946 switch (iSegReg)
947 {
948 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
949 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
950 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
951 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
952 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
953 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
954 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
955 }
956}
957
958
959/**
960 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
961 * nested-guest that is in Virtual-8086 mode.
962 *
963 * @param iSegReg The segment index (X86_SREG_XXX).
964 */
965IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
966{
967 switch (iSegReg)
968 {
969 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
970 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
971 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
972 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
973 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
974 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
975 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
976 }
977}
978
979
980/**
981 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
982 * nested-guest that is in Virtual-8086 mode.
983 *
984 * @param iSegReg The segment index (X86_SREG_XXX).
985 */
986IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
987{
988 switch (iSegReg)
989 {
990 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
991 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
992 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
993 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
994 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
995 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
996 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
997 }
998}
999
1000
1001/**
1002 * Gets the instruction diagnostic for segment attributes reserved bits failure
1003 * during VM-entry of a nested-guest.
1004 *
1005 * @param iSegReg The segment index (X86_SREG_XXX).
1006 */
1007IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1008{
1009 switch (iSegReg)
1010 {
1011 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1012 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1013 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1014 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1015 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1016 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1017 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1018 }
1019}
1020
1021
1022/**
1023 * Gets the instruction diagnostic for segment attributes descriptor-type
1024 * (code/segment or system) failure during VM-entry of a nested-guest.
1025 *
1026 * @param iSegReg The segment index (X86_SREG_XXX).
1027 */
1028IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1029{
1030 switch (iSegReg)
1031 {
1032 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1033 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1034 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1035 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1036 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1037 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1038 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1039 }
1040}
1041
1042
1043/**
1044 * Gets the instruction diagnostic for segment attributes descriptor-type
1045 * (code/segment or system) failure during VM-entry of a nested-guest.
1046 *
1047 * @param iSegReg The segment index (X86_SREG_XXX).
1048 */
1049IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1050{
1051 switch (iSegReg)
1052 {
1053 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1054 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1055 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1056 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1057 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1058 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1059 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1060 }
1061}
1062
1063
1064/**
1065 * Gets the instruction diagnostic for segment attribute granularity failure during
1066 * VM-entry of a nested-guest.
1067 *
1068 * @param iSegReg The segment index (X86_SREG_XXX).
1069 */
1070IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1071{
1072 switch (iSegReg)
1073 {
1074 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1075 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1076 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1077 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1078 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1079 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1080 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1081 }
1082}
1083
1084/**
1085 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1086 * VM-entry of a nested-guest.
1087 *
1088 * @param iSegReg The segment index (X86_SREG_XXX).
1089 */
1090IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1091{
1092 switch (iSegReg)
1093 {
1094 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1095 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1096 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1097 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1098 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1099 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1100 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1101 }
1102}
1103
1104
1105/**
1106 * Gets the instruction diagnostic for segment attribute type accessed failure
1107 * during VM-entry of a nested-guest.
1108 *
1109 * @param iSegReg The segment index (X86_SREG_XXX).
1110 */
1111IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1112{
1113 switch (iSegReg)
1114 {
1115 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1116 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1117 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1118 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1119 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1120 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1121 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1122 }
1123}
1124
1125
1126/**
1127 * Saves the guest control registers, debug registers and some MSRs are part of
1128 * VM-exit.
1129 *
1130 * @param pVCpu The cross context virtual CPU structure.
1131 */
1132IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1133{
1134 /*
1135 * Saves the guest control registers, debug registers and some MSRs.
1136 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1137 */
1138 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1139
1140 /* Save control registers. */
1141 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1142 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1143 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1144
1145 /* Save SYSENTER CS, ESP, EIP. */
1146 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1147 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1148 {
1149 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1150 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1151 }
1152 else
1153 {
1154 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1155 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1156 }
1157
1158 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1159 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1160 {
1161 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1162 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1163 }
1164
1165 /* Save PAT MSR. */
1166 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1167 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1168
1169 /* Save EFER MSR. */
1170 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1171 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1172
1173 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1174 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1175
1176 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1177}
1178
1179
1180/**
1181 * Saves the guest force-flags in preparation of entering the nested-guest.
1182 *
1183 * @param pVCpu The cross context virtual CPU structure.
1184 */
1185IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1186{
1187 /* We shouldn't be called multiple times during VM-entry. */
1188 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1189
1190 /* MTF should not be set outside VMX non-root mode. */
1191 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1192
1193 /*
1194 * Preserve the required force-flags.
1195 *
1196 * We cache and clear force-flags that would affect the execution of the
1197 * nested-guest. Cached flags are then restored while returning to the guest
1198 * if necessary.
1199 *
1200 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1201 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1202 * instruction. Interrupt inhibition for any nested-guest instruction
1203 * is supplied by the guest-interruptibility state VMCS field and will
1204 * be set up as part of loading the guest state.
1205 *
1206 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1207 * successful VM-entry (due to invalid guest-state) need to continue
1208 * blocking NMIs if it was in effect before VM-entry.
1209 *
1210 * - MTF need not be preserved as it's used only in VMX non-root mode and
1211 * is supplied through the VM-execution controls.
1212 *
1213 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1214 * we will be able to generate interrupts that may cause VM-exits for
1215 * the nested-guest.
1216 */
1217 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1218}
1219
1220
1221/**
1222 * Restores the guest force-flags in preparation of exiting the nested-guest.
1223 *
1224 * @param pVCpu The cross context virtual CPU structure.
1225 */
1226IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1227{
1228 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1229 {
1230 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1231 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1232 }
1233}
1234
1235
1236/**
1237 * Performs the VMX transition to/from VMX non-root mode.
1238 *
1239 * @param pVCpu The cross context virtual CPU structure.
1240*/
1241IEM_STATIC int iemVmxTransition(PVMCPUCC pVCpu)
1242{
1243 /*
1244 * Inform PGM about paging mode changes.
1245 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1246 * see comment in iemMemPageTranslateAndCheckAccess().
1247 */
1248 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1249 true /* fForce */);
1250 AssertRCReturn(rc, rc);
1251
1252 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1253 IEMTlbInvalidateAll(pVCpu, false /*fVmm*/);
1254
1255 /* Inform CPUM (recompiler), can later be removed. */
1256 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1257
1258 /* Re-initialize IEM cache/state after the drastic mode switch. */
1259 iemReInitExec(pVCpu);
1260 return rc;
1261}
1262
1263
1264/**
1265 * Calculates the current VMX-preemption timer value.
1266 *
1267 * @returns The current VMX-preemption timer value.
1268 * @param pVCpu The cross context virtual CPU structure.
1269 */
1270IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1271{
1272 /*
1273 * Assume the following:
1274 * PreemptTimerShift = 5
1275 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1276 * EntryTick = 50000 (TSC at time of VM-entry)
1277 *
1278 * CurTick Delta PreemptTimerVal
1279 * ----------------------------------
1280 * 60000 10000 2
1281 * 80000 30000 1
1282 * 90000 40000 0 -> VM-exit.
1283 *
1284 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1285 * The saved VMX-preemption timer value is calculated as follows:
1286 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1287 * E.g.:
1288 * Delta = 10000
1289 * Tmp = 10000 / (2 * 10000) = 0.5
1290 * NewPt = 2 - 0.5 = 2
1291 * Delta = 30000
1292 * Tmp = 30000 / (2 * 10000) = 1.5
1293 * NewPt = 2 - 1.5 = 1
1294 * Delta = 40000
1295 * Tmp = 40000 / 20000 = 2
1296 * NewPt = 2 - 2 = 0
1297 */
1298 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1299 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1300 if (uVmcsPreemptVal > 0)
1301 {
1302 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1303 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1304 uint64_t const uDelta = uCurTick - uEntryTick;
1305 uint32_t const uPreemptTimer = uVmcsPreemptVal
1306 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1307 return uPreemptTimer;
1308 }
1309 return 0;
1310}
1311
1312
1313/**
1314 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1315 *
1316 * @param pVCpu The cross context virtual CPU structure.
1317 */
1318IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1319{
1320 /*
1321 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1322 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1323 */
1324 /* CS, SS, ES, DS, FS, GS. */
1325 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1326 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1327 {
1328 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1329 if (!pSelReg->Attr.n.u1Unusable)
1330 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1331 else
1332 {
1333 /*
1334 * For unusable segments the attributes are undefined except for CS and SS.
1335 * For the rest we don't bother preserving anything but the unusable bit.
1336 */
1337 switch (iSegReg)
1338 {
1339 case X86_SREG_CS:
1340 pVmcs->GuestCs = pSelReg->Sel;
1341 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1342 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1343 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1344 | X86DESCATTR_UNUSABLE);
1345 break;
1346
1347 case X86_SREG_SS:
1348 pVmcs->GuestSs = pSelReg->Sel;
1349 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1350 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1351 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1352 break;
1353
1354 case X86_SREG_DS:
1355 pVmcs->GuestDs = pSelReg->Sel;
1356 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1357 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1358 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1359 break;
1360
1361 case X86_SREG_ES:
1362 pVmcs->GuestEs = pSelReg->Sel;
1363 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1364 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1365 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1366 break;
1367
1368 case X86_SREG_FS:
1369 pVmcs->GuestFs = pSelReg->Sel;
1370 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1371 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1372 break;
1373
1374 case X86_SREG_GS:
1375 pVmcs->GuestGs = pSelReg->Sel;
1376 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1377 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1378 break;
1379 }
1380 }
1381 }
1382
1383 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1384 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1385 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1386 | X86DESCATTR_UNUSABLE;
1387 /* LDTR. */
1388 {
1389 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1390 pVmcs->GuestLdtr = pSelReg->Sel;
1391 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1392 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1393 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1394 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1395 }
1396
1397 /* TR. */
1398 {
1399 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1400 pVmcs->GuestTr = pSelReg->Sel;
1401 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1402 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1403 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1404 }
1405
1406 /* GDTR. */
1407 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1408 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1409
1410 /* IDTR. */
1411 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1412 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1413}
1414
1415
1416/**
1417 * Saves guest non-register state as part of VM-exit.
1418 *
1419 * @param pVCpu The cross context virtual CPU structure.
1420 * @param uExitReason The VM-exit reason.
1421 */
1422IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1423{
1424 /*
1425 * Save guest non-register state.
1426 * See Intel spec. 27.3.4 "Saving Non-Register State".
1427 */
1428 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1429
1430 /*
1431 * Activity state.
1432 * Most VM-exits will occur in the active state. However, if the first instruction
1433 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1434 * the VM-exit will be from the HLT activity state.
1435 *
1436 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1437 */
1438 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1439 * not? */
1440 EMSTATE const enmActivityState = EMGetState(pVCpu);
1441 switch (enmActivityState)
1442 {
1443 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1444 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1445 }
1446
1447 /*
1448 * Interruptibility-state.
1449 */
1450 /* NMI. */
1451 pVmcs->u32GuestIntrState = 0;
1452 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1453 {
1454 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1455 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1456 }
1457 else
1458 {
1459 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1460 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1461 }
1462
1463 /* Blocking-by-STI. */
1464 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1465 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1466 {
1467 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1468 * currently. */
1469 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1470 }
1471 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1472
1473 /*
1474 * Pending debug exceptions.
1475 *
1476 * For VM-exits where it is not applicable, we can safely zero out the field.
1477 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1478 */
1479 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1480 && uExitReason != VMX_EXIT_SMI
1481 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1482 && !VMXIsVmexitTrapLike(uExitReason))
1483 {
1484 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1485 * block-by-MovSS is in effect. */
1486 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1487 }
1488
1489 /*
1490 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1491 *
1492 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1493 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1494 */
1495 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1496 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1497 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1498
1499 /*
1500 * PAE PDPTEs.
1501 *
1502 * If EPT is enabled and PAE paging was used at the time of the VM-exit,
1503 * the PDPTEs are saved from the VMCS. Otherwise they're undefined but
1504 * we zero them for consistency.
1505 */
1506 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1507 {
1508 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
1509 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1510 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
1511 {
1512 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1513 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1514 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1515 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1516 }
1517 else
1518 {
1519 pVmcs->u64GuestPdpte0.u = 0;
1520 pVmcs->u64GuestPdpte1.u = 0;
1521 pVmcs->u64GuestPdpte2.u = 0;
1522 pVmcs->u64GuestPdpte3.u = 0;
1523 }
1524
1525 /* Clear PGM's copy of the EPT pointer for added safety. */
1526 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1527 }
1528 else
1529 {
1530 pVmcs->u64GuestPdpte0.u = 0;
1531 pVmcs->u64GuestPdpte1.u = 0;
1532 pVmcs->u64GuestPdpte2.u = 0;
1533 pVmcs->u64GuestPdpte3.u = 0;
1534 }
1535}
1536
1537
1538/**
1539 * Saves the guest-state as part of VM-exit.
1540 *
1541 * @returns VBox status code.
1542 * @param pVCpu The cross context virtual CPU structure.
1543 * @param uExitReason The VM-exit reason.
1544 */
1545IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1546{
1547 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1548 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1549
1550 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1551 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1552 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1553
1554 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1555}
1556
1557
1558/**
1559 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1560 *
1561 * @returns VBox status code.
1562 * @param pVCpu The cross context virtual CPU structure.
1563 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1564 */
1565IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1566{
1567 /*
1568 * Save guest MSRs.
1569 * See Intel spec. 27.4 "Saving MSRs".
1570 */
1571 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1572 const char * const pszFailure = "VMX-abort";
1573
1574 /*
1575 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1576 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1577 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1578 */
1579 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1580 if (!cMsrs)
1581 return VINF_SUCCESS;
1582
1583 /*
1584 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1585 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1586 * implementation causes a VMX-abort followed by a triple-fault.
1587 */
1588 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1589 if (fIsMsrCountValid)
1590 { /* likely */ }
1591 else
1592 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1593
1594 /*
1595 * Optimization if the nested hypervisor is using the same guest-physical page for both
1596 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1597 */
1598 PVMXAUTOMSR pMsrArea;
1599 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1600 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1601 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1602 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1603 else
1604 {
1605 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1606 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1607 if (RT_SUCCESS(rc))
1608 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1609 else
1610 {
1611 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1612 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1613 }
1614 }
1615
1616 /*
1617 * Update VM-exit MSR store area.
1618 */
1619 PVMXAUTOMSR pMsr = pMsrArea;
1620 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1621 {
1622 if ( !pMsr->u32Reserved
1623 && pMsr->u32Msr != MSR_IA32_SMBASE
1624 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1625 {
1626 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1627 if (rcStrict == VINF_SUCCESS)
1628 continue;
1629
1630 /*
1631 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1632 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1633 * recording the MSR index in the auxiliary info. field and indicated further by our
1634 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1635 * if possible, or come up with a better, generic solution.
1636 */
1637 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1638 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1639 ? kVmxVDiag_Vmexit_MsrStoreRing3
1640 : kVmxVDiag_Vmexit_MsrStore;
1641 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1642 }
1643 else
1644 {
1645 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1646 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1647 }
1648 }
1649
1650 /*
1651 * Commit the VM-exit MSR store are to guest memory.
1652 */
1653 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1654 if (RT_SUCCESS(rc))
1655 return VINF_SUCCESS;
1656
1657 NOREF(uExitReason);
1658 NOREF(pszFailure);
1659
1660 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1661 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1662}
1663
1664
1665/**
1666 * Performs a VMX abort (due to an fatal error during VM-exit).
1667 *
1668 * @returns Strict VBox status code.
1669 * @param pVCpu The cross context virtual CPU structure.
1670 * @param enmAbort The VMX abort reason.
1671 */
1672IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1673{
1674 /*
1675 * Perform the VMX abort.
1676 * See Intel spec. 27.7 "VMX Aborts".
1677 */
1678 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1679
1680 /* We don't support SMX yet. */
1681 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1682 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1683 {
1684 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1685 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1686 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1687 }
1688
1689 return VINF_EM_TRIPLE_FAULT;
1690}
1691
1692
1693/**
1694 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1695 *
1696 * @param pVCpu The cross context virtual CPU structure.
1697 */
1698IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1699{
1700 /*
1701 * Load host control registers, debug registers and MSRs.
1702 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1703 */
1704 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1705 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1706
1707 /* CR0. */
1708 {
1709 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1710 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1711 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1712 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1713 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1714 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1715 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1716
1717 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1718 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1719 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1720 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1721 }
1722
1723 /* CR4. */
1724 {
1725 /* CR4 fixed bits are not modified. */
1726 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1727 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1728 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1729 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1730 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1731 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1732 if (fHostInLongMode)
1733 uValidHostCr4 |= X86_CR4_PAE;
1734 else
1735 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1736
1737 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1738 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1739 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1740 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1741 }
1742
1743 /* CR3 (host value validated while checking host-state during VM-entry). */
1744 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1745
1746 /* DR7. */
1747 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1748
1749 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1750
1751 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1752 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1753 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1754 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1755
1756 /* FS, GS bases are loaded later while we load host segment registers. */
1757
1758 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1759 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1760 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1761 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1762 {
1763 if (fHostInLongMode)
1764 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1765 else
1766 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1767 }
1768
1769 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1770
1771 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1772 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1773 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1774
1775 /* We don't support IA32_BNDCFGS MSR yet. */
1776}
1777
1778
1779/**
1780 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1781 *
1782 * @param pVCpu The cross context virtual CPU structure.
1783 */
1784IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1785{
1786 /*
1787 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1788 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1789 *
1790 * Warning! Be careful to not touch fields that are reserved by VT-x,
1791 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1792 */
1793 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1794 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1795
1796 /* CS, SS, ES, DS, FS, GS. */
1797 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1798 {
1799 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1800 bool const fUnusable = RT_BOOL(HostSel == 0);
1801 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1802
1803 /* Selector. */
1804 pSelReg->Sel = HostSel;
1805 pSelReg->ValidSel = HostSel;
1806 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1807
1808 /* Limit. */
1809 pSelReg->u32Limit = 0xffffffff;
1810
1811 /* Base. */
1812 pSelReg->u64Base = 0;
1813
1814 /* Attributes. */
1815 if (iSegReg == X86_SREG_CS)
1816 {
1817 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1818 pSelReg->Attr.n.u1DescType = 1;
1819 pSelReg->Attr.n.u2Dpl = 0;
1820 pSelReg->Attr.n.u1Present = 1;
1821 pSelReg->Attr.n.u1Long = fHostInLongMode;
1822 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1823 pSelReg->Attr.n.u1Granularity = 1;
1824 Assert(!pSelReg->Attr.n.u1Unusable);
1825 Assert(!fUnusable);
1826 }
1827 else
1828 {
1829 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1830 pSelReg->Attr.n.u1DescType = 1;
1831 pSelReg->Attr.n.u2Dpl = 0;
1832 pSelReg->Attr.n.u1Present = 1;
1833 pSelReg->Attr.n.u1DefBig = 1;
1834 pSelReg->Attr.n.u1Granularity = 1;
1835 pSelReg->Attr.n.u1Unusable = fUnusable;
1836 }
1837 }
1838
1839 /* FS base. */
1840 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1841 || fHostInLongMode)
1842 {
1843 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1844 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1845 }
1846
1847 /* GS base. */
1848 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1849 || fHostInLongMode)
1850 {
1851 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1852 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1853 }
1854
1855 /* TR. */
1856 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1857 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1858 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1859 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1860 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1861 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1862 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1863 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1864 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1865 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1866 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1867 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1868 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1869
1870 /* LDTR (Warning! do not touch the base and limits here). */
1871 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1872 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1873 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1874 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1875
1876 /* GDTR. */
1877 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1878 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1879 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1880
1881 /* IDTR.*/
1882 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1883 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1884 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1885}
1886
1887
1888/**
1889 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1890 *
1891 * @returns VBox status code.
1892 * @param pVCpu The cross context virtual CPU structure.
1893 * @param uExitReason The VMX instruction name (for logging purposes).
1894 */
1895IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1896{
1897 /*
1898 * Load host MSRs.
1899 * See Intel spec. 27.6 "Loading MSRs".
1900 */
1901 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1902 const char * const pszFailure = "VMX-abort";
1903
1904 /*
1905 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1906 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1907 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1908 */
1909 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1910 if (!cMsrs)
1911 return VINF_SUCCESS;
1912
1913 /*
1914 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1915 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1916 * implementation causes a VMX-abort followed by a triple-fault.
1917 */
1918 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1919 if (fIsMsrCountValid)
1920 { /* likely */ }
1921 else
1922 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1923
1924 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1925 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1926 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1927 if (RT_SUCCESS(rc))
1928 {
1929 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1930 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1931 {
1932 if ( !pMsr->u32Reserved
1933 && pMsr->u32Msr != MSR_K8_FS_BASE
1934 && pMsr->u32Msr != MSR_K8_GS_BASE
1935 && pMsr->u32Msr != MSR_K6_EFER
1936 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1937 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1938 {
1939 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1940 if (rcStrict == VINF_SUCCESS)
1941 continue;
1942
1943 /*
1944 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1945 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1946 * recording the MSR index in the auxiliary info. field and indicated further by our
1947 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1948 * if possible, or come up with a better, generic solution.
1949 */
1950 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1951 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1952 ? kVmxVDiag_Vmexit_MsrLoadRing3
1953 : kVmxVDiag_Vmexit_MsrLoad;
1954 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1955 }
1956 else
1957 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1958 }
1959 }
1960 else
1961 {
1962 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1963 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1964 }
1965
1966 NOREF(uExitReason);
1967 NOREF(pszFailure);
1968 return VINF_SUCCESS;
1969}
1970
1971
1972/**
1973 * Loads the host state as part of VM-exit.
1974 *
1975 * @returns Strict VBox status code.
1976 * @param pVCpu The cross context virtual CPU structure.
1977 * @param uExitReason The VM-exit reason (for logging purposes).
1978 */
1979IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
1980{
1981 /*
1982 * Load host state.
1983 * See Intel spec. 27.5 "Loading Host State".
1984 */
1985 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1986 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1987
1988 /* We cannot return from a long-mode guest to a host that is not in long mode. */
1989 if ( CPUMIsGuestInLongMode(pVCpu)
1990 && !fHostInLongMode)
1991 {
1992 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
1993 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
1994 }
1995
1996 /*
1997 * Check host PAE PDPTEs prior to loading the host state.
1998 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1999 */
2000 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2001 && !fHostInLongMode
2002 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2003 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2004 {
2005 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2006 if (RT_SUCCESS(rc))
2007 { /* likely*/ }
2008 else
2009 {
2010 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2011 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2012 }
2013 }
2014
2015 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2016 iemVmxVmexitLoadHostSegRegs(pVCpu);
2017
2018 /*
2019 * Load host RIP, RSP and RFLAGS.
2020 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2021 */
2022 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2023 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2024 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2025
2026 /* Clear address range monitoring. */
2027 EMMonitorWaitClear(pVCpu);
2028
2029 /* Perform the VMX transition (PGM updates). */
2030 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2031 if (rcStrict == VINF_SUCCESS)
2032 { /* likely */ }
2033 else if (RT_SUCCESS(rcStrict))
2034 {
2035 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2036 uExitReason));
2037 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2038 }
2039 else
2040 {
2041 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2042 return VBOXSTRICTRC_VAL(rcStrict);
2043 }
2044
2045 Assert(rcStrict == VINF_SUCCESS);
2046
2047 /* Load MSRs from the VM-exit auto-load MSR area. */
2048 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2049 if (RT_FAILURE(rc))
2050 {
2051 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2052 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2053 }
2054 return VINF_SUCCESS;
2055}
2056
2057
2058/**
2059 * Gets VM-exit instruction information along with any displacement for an
2060 * instruction VM-exit.
2061 *
2062 * @returns The VM-exit instruction information.
2063 * @param pVCpu The cross context virtual CPU structure.
2064 * @param uExitReason The VM-exit reason.
2065 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2066 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2067 * NULL.
2068 */
2069IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2070{
2071 RTGCPTR GCPtrDisp;
2072 VMXEXITINSTRINFO ExitInstrInfo;
2073 ExitInstrInfo.u = 0;
2074
2075 /*
2076 * Get and parse the ModR/M byte from our decoded opcodes.
2077 */
2078 uint8_t bRm;
2079 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2080 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2081 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2082 {
2083 /*
2084 * ModR/M indicates register addressing.
2085 *
2086 * The primary/secondary register operands are reported in the iReg1 or iReg2
2087 * fields depending on whether it is a read/write form.
2088 */
2089 uint8_t idxReg1;
2090 uint8_t idxReg2;
2091 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2092 {
2093 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2094 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2095 }
2096 else
2097 {
2098 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2099 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2100 }
2101 ExitInstrInfo.All.u2Scaling = 0;
2102 ExitInstrInfo.All.iReg1 = idxReg1;
2103 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2104 ExitInstrInfo.All.fIsRegOperand = 1;
2105 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2106 ExitInstrInfo.All.iSegReg = 0;
2107 ExitInstrInfo.All.iIdxReg = 0;
2108 ExitInstrInfo.All.fIdxRegInvalid = 1;
2109 ExitInstrInfo.All.iBaseReg = 0;
2110 ExitInstrInfo.All.fBaseRegInvalid = 1;
2111 ExitInstrInfo.All.iReg2 = idxReg2;
2112
2113 /* Displacement not applicable for register addressing. */
2114 GCPtrDisp = 0;
2115 }
2116 else
2117 {
2118 /*
2119 * ModR/M indicates memory addressing.
2120 */
2121 uint8_t uScale = 0;
2122 bool fBaseRegValid = false;
2123 bool fIdxRegValid = false;
2124 uint8_t iBaseReg = 0;
2125 uint8_t iIdxReg = 0;
2126 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2127 {
2128 /*
2129 * Parse the ModR/M, displacement for 16-bit addressing mode.
2130 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2131 */
2132 uint16_t u16Disp = 0;
2133 uint8_t const offDisp = offModRm + sizeof(bRm);
2134 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2135 {
2136 /* Displacement without any registers. */
2137 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2138 }
2139 else
2140 {
2141 /* Register (index and base). */
2142 switch (bRm & X86_MODRM_RM_MASK)
2143 {
2144 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2145 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2146 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2147 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2148 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2149 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2150 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2151 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2152 }
2153
2154 /* Register + displacement. */
2155 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2156 {
2157 case 0: break;
2158 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2159 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2160 default:
2161 {
2162 /* Register addressing, handled at the beginning. */
2163 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2164 break;
2165 }
2166 }
2167 }
2168
2169 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2170 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2171 }
2172 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2173 {
2174 /*
2175 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2176 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2177 */
2178 uint32_t u32Disp = 0;
2179 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2180 {
2181 /* Displacement without any registers. */
2182 uint8_t const offDisp = offModRm + sizeof(bRm);
2183 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2184 }
2185 else
2186 {
2187 /* Register (and perhaps scale, index and base). */
2188 uint8_t offDisp = offModRm + sizeof(bRm);
2189 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2190 if (iBaseReg == 4)
2191 {
2192 /* An SIB byte follows the ModR/M byte, parse it. */
2193 uint8_t bSib;
2194 uint8_t const offSib = offModRm + sizeof(bRm);
2195 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2196
2197 /* A displacement may follow SIB, update its offset. */
2198 offDisp += sizeof(bSib);
2199
2200 /* Get the scale. */
2201 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2202
2203 /* Get the index register. */
2204 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2205 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2206
2207 /* Get the base register. */
2208 iBaseReg = bSib & X86_SIB_BASE_MASK;
2209 fBaseRegValid = true;
2210 if (iBaseReg == 5)
2211 {
2212 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2213 {
2214 /* Mod is 0 implies a 32-bit displacement with no base. */
2215 fBaseRegValid = false;
2216 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2217 }
2218 else
2219 {
2220 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2221 iBaseReg = X86_GREG_xBP;
2222 }
2223 }
2224 }
2225
2226 /* Register + displacement. */
2227 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2228 {
2229 case 0: /* Handled above */ break;
2230 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2231 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2232 default:
2233 {
2234 /* Register addressing, handled at the beginning. */
2235 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2236 break;
2237 }
2238 }
2239 }
2240
2241 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2242 }
2243 else
2244 {
2245 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2246
2247 /*
2248 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2249 * See Intel instruction spec. 2.2 "IA-32e Mode".
2250 */
2251 uint64_t u64Disp = 0;
2252 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2253 if (fRipRelativeAddr)
2254 {
2255 /*
2256 * RIP-relative addressing mode.
2257 *
2258 * The displacement is 32-bit signed implying an offset range of +/-2G.
2259 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2260 */
2261 uint8_t const offDisp = offModRm + sizeof(bRm);
2262 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2263 }
2264 else
2265 {
2266 uint8_t offDisp = offModRm + sizeof(bRm);
2267
2268 /*
2269 * Register (and perhaps scale, index and base).
2270 *
2271 * REX.B extends the most-significant bit of the base register. However, REX.B
2272 * is ignored while determining whether an SIB follows the opcode. Hence, we
2273 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2274 *
2275 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2276 */
2277 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2278 if (iBaseReg == 4)
2279 {
2280 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2281 uint8_t bSib;
2282 uint8_t const offSib = offModRm + sizeof(bRm);
2283 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2284
2285 /* Displacement may follow SIB, update its offset. */
2286 offDisp += sizeof(bSib);
2287
2288 /* Get the scale. */
2289 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2290
2291 /* Get the index. */
2292 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2293 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2294
2295 /* Get the base. */
2296 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2297 fBaseRegValid = true;
2298 if (iBaseReg == 5)
2299 {
2300 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2301 {
2302 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2303 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2304 }
2305 else
2306 {
2307 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2308 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2309 }
2310 }
2311 }
2312 iBaseReg |= pVCpu->iem.s.uRexB;
2313
2314 /* Register + displacement. */
2315 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2316 {
2317 case 0: /* Handled above */ break;
2318 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2319 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2320 default:
2321 {
2322 /* Register addressing, handled at the beginning. */
2323 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2324 break;
2325 }
2326 }
2327 }
2328
2329 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2330 }
2331
2332 /*
2333 * The primary or secondary register operand is reported in iReg2 depending
2334 * on whether the primary operand is in read/write form.
2335 */
2336 uint8_t idxReg2;
2337 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2338 {
2339 idxReg2 = bRm & X86_MODRM_RM_MASK;
2340 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2341 idxReg2 |= pVCpu->iem.s.uRexB;
2342 }
2343 else
2344 {
2345 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2346 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2347 idxReg2 |= pVCpu->iem.s.uRexReg;
2348 }
2349 ExitInstrInfo.All.u2Scaling = uScale;
2350 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2351 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2352 ExitInstrInfo.All.fIsRegOperand = 0;
2353 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2354 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2355 ExitInstrInfo.All.iIdxReg = iIdxReg;
2356 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2357 ExitInstrInfo.All.iBaseReg = iBaseReg;
2358 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2359 ExitInstrInfo.All.iReg2 = idxReg2;
2360 }
2361
2362 /*
2363 * Handle exceptions to the norm for certain instructions.
2364 * (e.g. some instructions convey an instruction identity in place of iReg2).
2365 */
2366 switch (uExitReason)
2367 {
2368 case VMX_EXIT_GDTR_IDTR_ACCESS:
2369 {
2370 Assert(VMXINSTRID_IS_VALID(uInstrId));
2371 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2372 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2373 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2374 break;
2375 }
2376
2377 case VMX_EXIT_LDTR_TR_ACCESS:
2378 {
2379 Assert(VMXINSTRID_IS_VALID(uInstrId));
2380 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2381 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2382 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2383 break;
2384 }
2385
2386 case VMX_EXIT_RDRAND:
2387 case VMX_EXIT_RDSEED:
2388 {
2389 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2390 break;
2391 }
2392 }
2393
2394 /* Update displacement and return the constructed VM-exit instruction information field. */
2395 if (pGCPtrDisp)
2396 *pGCPtrDisp = GCPtrDisp;
2397
2398 return ExitInstrInfo.u;
2399}
2400
2401
2402/**
2403 * VMX VM-exit handler.
2404 *
2405 * @returns Strict VBox status code.
2406 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2407 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2408 * triple-fault.
2409 *
2410 * @param pVCpu The cross context virtual CPU structure.
2411 * @param uExitReason The VM-exit reason.
2412 * @param u64ExitQual The Exit qualification.
2413 */
2414IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2415{
2416# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2417 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2418 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2419 return VERR_IEM_IPE_7;
2420# else
2421 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2422
2423 /*
2424 * Import all the guest-CPU state.
2425 *
2426 * HM on returning to guest execution would have to reset up a whole lot of state
2427 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2428 * the state and flag reloading the entire state on re-entry. So import the entire
2429 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2430 */
2431 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2432
2433 /*
2434 * Ensure VM-entry interruption information valid bit is cleared.
2435 *
2436 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2437 * by invalid-guest state or machine-check exceptions) also clear this bit.
2438 *
2439 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2440 */
2441 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2442 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2443
2444 /*
2445 * Update the VM-exit reason and Exit qualification.
2446 * Other VMCS read-only data fields are expected to be updated by the caller already.
2447 */
2448 pVmcs->u32RoExitReason = uExitReason;
2449 pVmcs->u64RoExitQual.u = u64ExitQual;
2450
2451 Log3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2452 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2453 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2454
2455 /*
2456 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2457 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2458 */
2459 {
2460 uint8_t uVector;
2461 uint32_t fFlags;
2462 uint32_t uErrCode;
2463 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2464 if (fInEventDelivery)
2465 {
2466 /*
2467 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2468 * caused by a triple-fault or the original event results in a double-fault that
2469 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2470 * original event information into the IDT-vectoring information fields.
2471 *
2472 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2473 */
2474 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2475 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2476 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2477 {
2478 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2479 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2480 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2481 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2482 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2483 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2484 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2485 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2486 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2487 pVCpu->cpum.GstCtx.cr2));
2488 }
2489 }
2490 }
2491
2492 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2493 Assert(pVmcs->u64RoIoRcx.u == 0);
2494 Assert(pVmcs->u64RoIoRsi.u == 0);
2495 Assert(pVmcs->u64RoIoRdi.u == 0);
2496 Assert(pVmcs->u64RoIoRip.u == 0);
2497
2498 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2499 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2500 {
2501 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2502 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2503 }
2504
2505 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2506 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2507
2508 /*
2509 * Save the guest state back into the VMCS.
2510 * We only need to save the state when the VM-entry was successful.
2511 */
2512 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2513 if (!fVmentryFailed)
2514 {
2515 /*
2516 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2517 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2518 *
2519 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2520 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2521 * as guest-CPU state would not been modified. Hence for now, we do this only when
2522 * the VM-entry succeeded.
2523 */
2524 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2525 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2526 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2527 {
2528 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2529 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2530 else
2531 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2532 }
2533
2534 /*
2535 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2536 * occurs in enclave mode/SMM which we don't support yet.
2537 *
2538 * If we ever add support for it, we can pass just the lower bits to the functions
2539 * below, till then an assert should suffice.
2540 */
2541 Assert(!RT_HI_U16(uExitReason));
2542
2543 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2544 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2545 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2546 if (RT_SUCCESS(rc))
2547 { /* likely */ }
2548 else
2549 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2550
2551 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2552 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2553 }
2554 else
2555 {
2556 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2557 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2558 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2559 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2560 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2561 }
2562
2563 /*
2564 * Stop any running VMX-preemption timer if necessary.
2565 */
2566 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2567 CPUMStopGuestVmxPremptTimer(pVCpu);
2568
2569 /*
2570 * Clear any pending VMX nested-guest force-flags.
2571 * These force-flags have no effect on (outer) guest execution and will
2572 * be re-evaluated and setup on the next nested-guest VM-entry.
2573 */
2574 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2575
2576 /*
2577 * We're no longer in nested-guest execution mode.
2578 *
2579 * It is important to do this prior to loading the host state because
2580 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2581 * second-level address translation while switching to host CR3.
2582 */
2583 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2584
2585 /* Restore the host (outer guest) state. */
2586 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2587 if (RT_SUCCESS(rcStrict))
2588 {
2589 Assert(rcStrict == VINF_SUCCESS);
2590 rcStrict = VINF_VMX_VMEXIT;
2591 }
2592 else
2593 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2594
2595 /* Notify HM that the current VMCS fields have been modified. */
2596 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2597
2598 /* Notify HM that we've completed the VM-exit. */
2599 HMNotifyVmxNstGstVmexit(pVCpu);
2600
2601# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2602 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2603 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2604 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2605 if (rcSched != VINF_SUCCESS)
2606 iemSetPassUpStatus(pVCpu, rcSched);
2607# endif
2608 return rcStrict;
2609# endif
2610}
2611
2612
2613/**
2614 * VMX VM-exit handler for VM-exits due to instruction execution.
2615 *
2616 * This is intended for instructions where the caller provides all the relevant
2617 * VM-exit information.
2618 *
2619 * @returns Strict VBox status code.
2620 * @param pVCpu The cross context virtual CPU structure.
2621 * @param pExitInfo Pointer to the VM-exit information.
2622 */
2623IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2624{
2625 /*
2626 * For instructions where any of the following fields are not applicable:
2627 * - Exit qualification must be cleared.
2628 * - VM-exit instruction info. is undefined.
2629 * - Guest-linear address is undefined.
2630 * - Guest-physical address is undefined.
2631 *
2632 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2633 * instruction execution. For VM-exits that are not due to instruction execution this
2634 * field is undefined.
2635 *
2636 * In our implementation in IEM, all undefined fields are generally cleared. However,
2637 * if the caller supplies information (from say the physical CPU directly) it is
2638 * then possible that the undefined fields are not cleared.
2639 *
2640 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2641 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2642 */
2643 Assert(pExitInfo);
2644 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2645 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2646 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2647
2648 /* Update all the relevant fields from the VM-exit instruction information struct. */
2649 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2650 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2651 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2652 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2653
2654 /* Perform the VM-exit. */
2655 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2656}
2657
2658
2659/**
2660 * VMX VM-exit handler for VM-exits due to instruction execution.
2661 *
2662 * This is intended for instructions that only provide the VM-exit instruction
2663 * length.
2664 *
2665 * @param pVCpu The cross context virtual CPU structure.
2666 * @param uExitReason The VM-exit reason.
2667 * @param cbInstr The instruction length in bytes.
2668 */
2669IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2670{
2671 VMXVEXITINFO ExitInfo;
2672 RT_ZERO(ExitInfo);
2673 ExitInfo.uReason = uExitReason;
2674 ExitInfo.cbInstr = cbInstr;
2675
2676#ifdef VBOX_STRICT
2677 /*
2678 * To prevent us from shooting ourselves in the foot.
2679 * The follow instructions should convey more than just the instruction length.
2680 */
2681 switch (uExitReason)
2682 {
2683 case VMX_EXIT_INVEPT:
2684 case VMX_EXIT_INVPCID:
2685 case VMX_EXIT_INVVPID:
2686 case VMX_EXIT_LDTR_TR_ACCESS:
2687 case VMX_EXIT_GDTR_IDTR_ACCESS:
2688 case VMX_EXIT_VMCLEAR:
2689 case VMX_EXIT_VMPTRLD:
2690 case VMX_EXIT_VMPTRST:
2691 case VMX_EXIT_VMREAD:
2692 case VMX_EXIT_VMWRITE:
2693 case VMX_EXIT_VMXON:
2694 case VMX_EXIT_XRSTORS:
2695 case VMX_EXIT_XSAVES:
2696 case VMX_EXIT_RDRAND:
2697 case VMX_EXIT_RDSEED:
2698 case VMX_EXIT_IO_INSTR:
2699 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2700 break;
2701 }
2702#endif
2703
2704 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2705}
2706
2707
2708/**
2709 * VMX VM-exit handler for VM-exits due to instruction execution.
2710 *
2711 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2712 * instruction information and Exit qualification fields.
2713 *
2714 * @param pVCpu The cross context virtual CPU structure.
2715 * @param uExitReason The VM-exit reason.
2716 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2717 * @param cbInstr The instruction length in bytes.
2718 *
2719 * @remarks Do not use this for INS/OUTS instruction.
2720 */
2721IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2722{
2723 VMXVEXITINFO ExitInfo;
2724 RT_ZERO(ExitInfo);
2725 ExitInfo.uReason = uExitReason;
2726 ExitInfo.cbInstr = cbInstr;
2727
2728 /*
2729 * Update the Exit qualification field with displacement bytes.
2730 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2731 */
2732 switch (uExitReason)
2733 {
2734 case VMX_EXIT_INVEPT:
2735 case VMX_EXIT_INVPCID:
2736 case VMX_EXIT_INVVPID:
2737 case VMX_EXIT_LDTR_TR_ACCESS:
2738 case VMX_EXIT_GDTR_IDTR_ACCESS:
2739 case VMX_EXIT_VMCLEAR:
2740 case VMX_EXIT_VMPTRLD:
2741 case VMX_EXIT_VMPTRST:
2742 case VMX_EXIT_VMREAD:
2743 case VMX_EXIT_VMWRITE:
2744 case VMX_EXIT_VMXON:
2745 case VMX_EXIT_XRSTORS:
2746 case VMX_EXIT_XSAVES:
2747 case VMX_EXIT_RDRAND:
2748 case VMX_EXIT_RDSEED:
2749 {
2750 /* Construct the VM-exit instruction information. */
2751 RTGCPTR GCPtrDisp;
2752 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2753
2754 /* Update the VM-exit instruction information. */
2755 ExitInfo.InstrInfo.u = uInstrInfo;
2756
2757 /* Update the Exit qualification. */
2758 ExitInfo.u64Qual = GCPtrDisp;
2759 break;
2760 }
2761
2762 default:
2763 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2764 break;
2765 }
2766
2767 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2768}
2769
2770
2771/**
2772 * VMX VM-exit handler for VM-exits due to INVLPG.
2773 *
2774 * @returns Strict VBox status code.
2775 * @param pVCpu The cross context virtual CPU structure.
2776 * @param GCPtrPage The guest-linear address of the page being invalidated.
2777 * @param cbInstr The instruction length in bytes.
2778 */
2779IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2780{
2781 VMXVEXITINFO ExitInfo;
2782 RT_ZERO(ExitInfo);
2783 ExitInfo.uReason = VMX_EXIT_INVLPG;
2784 ExitInfo.cbInstr = cbInstr;
2785 ExitInfo.u64Qual = GCPtrPage;
2786 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2787
2788 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2789}
2790
2791
2792/**
2793 * VMX VM-exit handler for VM-exits due to LMSW.
2794 *
2795 * @returns Strict VBox status code.
2796 * @param pVCpu The cross context virtual CPU structure.
2797 * @param uGuestCr0 The current guest CR0.
2798 * @param pu16NewMsw The machine-status word specified in LMSW's source
2799 * operand. This will be updated depending on the VMX
2800 * guest/host CR0 mask if LMSW is not intercepted.
2801 * @param GCPtrEffDst The guest-linear address of the source operand in case
2802 * of a memory operand. For register operand, pass
2803 * NIL_RTGCPTR.
2804 * @param cbInstr The instruction length in bytes.
2805 */
2806IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2807 uint8_t cbInstr)
2808{
2809 Assert(pu16NewMsw);
2810
2811 uint16_t const uNewMsw = *pu16NewMsw;
2812 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2813 {
2814 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2815
2816 VMXVEXITINFO ExitInfo;
2817 RT_ZERO(ExitInfo);
2818 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2819 ExitInfo.cbInstr = cbInstr;
2820
2821 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2822 if (fMemOperand)
2823 {
2824 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2825 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2826 }
2827
2828 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2829 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2830 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2831 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2832
2833 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2834 }
2835
2836 /*
2837 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2838 * CR0 guest/host mask must be left unmodified.
2839 *
2840 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2841 */
2842 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2843 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2844 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2845
2846 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2847}
2848
2849
2850/**
2851 * VMX VM-exit handler for VM-exits due to CLTS.
2852 *
2853 * @returns Strict VBox status code.
2854 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2855 * VM-exit but must not modify the guest CR0.TS bit.
2856 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2857 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2858 * CR0 fixed bits in VMX operation).
2859 * @param pVCpu The cross context virtual CPU structure.
2860 * @param cbInstr The instruction length in bytes.
2861 */
2862IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2863{
2864 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2865 uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2866
2867 /*
2868 * If CR0.TS is owned by the host:
2869 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2870 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2871 * CLTS instruction completes without clearing CR0.TS.
2872 *
2873 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2874 */
2875 if (fGstHostMask & X86_CR0_TS)
2876 {
2877 if (fReadShadow & X86_CR0_TS)
2878 {
2879 Log2(("clts: Guest intercept -> VM-exit\n"));
2880
2881 VMXVEXITINFO ExitInfo;
2882 RT_ZERO(ExitInfo);
2883 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2884 ExitInfo.cbInstr = cbInstr;
2885 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2886 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2887 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2888 }
2889
2890 return VINF_VMX_MODIFIES_BEHAVIOR;
2891 }
2892
2893 /*
2894 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2895 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2896 */
2897 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2898}
2899
2900
2901/**
2902 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2903 * (CR0/CR4 write).
2904 *
2905 * @returns Strict VBox status code.
2906 * @param pVCpu The cross context virtual CPU structure.
2907 * @param iCrReg The control register (either CR0 or CR4).
2908 * @param uGuestCrX The current guest CR0/CR4.
2909 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2910 * VM-exit is caused.
2911 * @param iGReg The general register from which the CR0/CR4 value is being
2912 * loaded.
2913 * @param cbInstr The instruction length in bytes.
2914 */
2915IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2916 uint8_t cbInstr)
2917{
2918 Assert(puNewCrX);
2919 Assert(iCrReg == 0 || iCrReg == 4);
2920 Assert(iGReg < X86_GREG_COUNT);
2921
2922 uint64_t const uNewCrX = *puNewCrX;
2923 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2924 {
2925 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2926
2927 VMXVEXITINFO ExitInfo;
2928 RT_ZERO(ExitInfo);
2929 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2930 ExitInfo.cbInstr = cbInstr;
2931 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2932 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2933 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2934 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2935 }
2936
2937 /*
2938 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2939 * must not be modified the instruction.
2940 *
2941 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2942 */
2943 uint64_t uGuestCrX;
2944 uint64_t fGstHostMask;
2945 if (iCrReg == 0)
2946 {
2947 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2948 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2949 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2950 }
2951 else
2952 {
2953 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2954 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2955 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2956 }
2957
2958 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2959 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2960}
2961
2962
2963/**
2964 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2965 *
2966 * @returns VBox strict status code.
2967 * @param pVCpu The cross context virtual CPU structure.
2968 * @param iGReg The general register to which the CR3 value is being stored.
2969 * @param cbInstr The instruction length in bytes.
2970 */
2971IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
2972{
2973 Assert(iGReg < X86_GREG_COUNT);
2974 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
2975
2976 /*
2977 * If the CR3-store exiting control is set, we must cause a VM-exit.
2978 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2979 */
2980 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
2981 {
2982 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
2983
2984 VMXVEXITINFO ExitInfo;
2985 RT_ZERO(ExitInfo);
2986 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2987 ExitInfo.cbInstr = cbInstr;
2988 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
2989 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
2990 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2991 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2992 }
2993
2994 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2995}
2996
2997
2998/**
2999 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3000 *
3001 * @returns VBox strict status code.
3002 * @param pVCpu The cross context virtual CPU structure.
3003 * @param uNewCr3 The new CR3 value.
3004 * @param iGReg The general register from which the CR3 value is being
3005 * loaded.
3006 * @param cbInstr The instruction length in bytes.
3007 */
3008IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3009{
3010 Assert(iGReg < X86_GREG_COUNT);
3011
3012 /*
3013 * If the CR3-load exiting control is set and the new CR3 value does not
3014 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3015 *
3016 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3017 */
3018 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3019 {
3020 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3021
3022 VMXVEXITINFO ExitInfo;
3023 RT_ZERO(ExitInfo);
3024 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3025 ExitInfo.cbInstr = cbInstr;
3026 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3027 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3028 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3029 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3030 }
3031
3032 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3033}
3034
3035
3036/**
3037 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3038 *
3039 * @returns VBox strict status code.
3040 * @param pVCpu The cross context virtual CPU structure.
3041 * @param iGReg The general register to which the CR8 value is being stored.
3042 * @param cbInstr The instruction length in bytes.
3043 */
3044IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3045{
3046 Assert(iGReg < X86_GREG_COUNT);
3047
3048 /*
3049 * If the CR8-store exiting control is set, we must cause a VM-exit.
3050 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3051 */
3052 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3053 {
3054 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3055
3056 VMXVEXITINFO ExitInfo;
3057 RT_ZERO(ExitInfo);
3058 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3059 ExitInfo.cbInstr = cbInstr;
3060 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3061 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3062 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3063 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3064 }
3065
3066 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3067}
3068
3069
3070/**
3071 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3072 *
3073 * @returns VBox strict status code.
3074 * @param pVCpu The cross context virtual CPU structure.
3075 * @param iGReg The general register from which the CR8 value is being
3076 * loaded.
3077 * @param cbInstr The instruction length in bytes.
3078 */
3079IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3080{
3081 Assert(iGReg < X86_GREG_COUNT);
3082
3083 /*
3084 * If the CR8-load exiting control is set, we must cause a VM-exit.
3085 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3086 */
3087 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3088 {
3089 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3090
3091 VMXVEXITINFO ExitInfo;
3092 RT_ZERO(ExitInfo);
3093 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3094 ExitInfo.cbInstr = cbInstr;
3095 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3096 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3097 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3098 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3099 }
3100
3101 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3102}
3103
3104
3105/**
3106 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3107 * GReg,DRx' (DRx read).
3108 *
3109 * @returns VBox strict status code.
3110 * @param pVCpu The cross context virtual CPU structure.
3111 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3112 * VMXINSTRID_MOV_FROM_DRX).
3113 * @param iDrReg The debug register being accessed.
3114 * @param iGReg The general register to/from which the DRx value is being
3115 * store/loaded.
3116 * @param cbInstr The instruction length in bytes.
3117 */
3118IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3119 uint8_t cbInstr)
3120{
3121 Assert(iDrReg <= 7);
3122 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3123 Assert(iGReg < X86_GREG_COUNT);
3124
3125 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3126 {
3127 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3128 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3129 VMXVEXITINFO ExitInfo;
3130 RT_ZERO(ExitInfo);
3131 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3132 ExitInfo.cbInstr = cbInstr;
3133 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3134 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3135 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3136 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3137 }
3138
3139 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3140}
3141
3142
3143/**
3144 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3145 *
3146 * @returns VBox strict status code.
3147 * @param pVCpu The cross context virtual CPU structure.
3148 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3149 * VMXINSTRID_IO_OUT).
3150 * @param u16Port The I/O port being accessed.
3151 * @param fImm Whether the I/O port was encoded using an immediate operand
3152 * or the implicit DX register.
3153 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3154 * @param cbInstr The instruction length in bytes.
3155 */
3156IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3157 uint8_t cbInstr)
3158{
3159 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3160 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3161
3162 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3163 if (fIntercept)
3164 {
3165 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3166 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3167 VMXVEXITINFO ExitInfo;
3168 RT_ZERO(ExitInfo);
3169 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3170 ExitInfo.cbInstr = cbInstr;
3171 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3172 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3173 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3174 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3175 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3176 }
3177
3178 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3179}
3180
3181
3182/**
3183 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3184 *
3185 * @returns VBox strict status code.
3186 * @param pVCpu The cross context virtual CPU structure.
3187 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3188 * VMXINSTRID_IO_OUTS).
3189 * @param u16Port The I/O port being accessed.
3190 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3191 * @param fRep Whether the instruction has a REP prefix or not.
3192 * @param ExitInstrInfo The VM-exit instruction info. field.
3193 * @param cbInstr The instruction length in bytes.
3194 */
3195IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3196 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3197{
3198 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3199 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3200 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3201 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3202 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3203
3204 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3205 if (fIntercept)
3206 {
3207 /*
3208 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3209 */
3210 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3211 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3212 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3213 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3214 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3215
3216 uint32_t uDirection;
3217 uint64_t uGuestLinearAddr;
3218 if (uInstrId == VMXINSTRID_IO_INS)
3219 {
3220 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3221 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3222 }
3223 else
3224 {
3225 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3226 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3227 }
3228
3229 /*
3230 * If the segment is unusable, the guest-linear address in undefined.
3231 * We shall clear it for consistency.
3232 *
3233 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3234 */
3235 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3236 uGuestLinearAddr = 0;
3237
3238 VMXVEXITINFO ExitInfo;
3239 RT_ZERO(ExitInfo);
3240 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3241 ExitInfo.cbInstr = cbInstr;
3242 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3243 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3244 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3245 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3246 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3247 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3248 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3249 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3250 ExitInfo.InstrInfo = ExitInstrInfo;
3251 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3252 }
3253
3254 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3255}
3256
3257
3258/**
3259 * VMX VM-exit handler for VM-exits due to MWAIT.
3260 *
3261 * @returns VBox strict status code.
3262 * @param pVCpu The cross context virtual CPU structure.
3263 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3264 * @param cbInstr The instruction length in bytes.
3265 */
3266IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3267{
3268 VMXVEXITINFO ExitInfo;
3269 RT_ZERO(ExitInfo);
3270 ExitInfo.uReason = VMX_EXIT_MWAIT;
3271 ExitInfo.cbInstr = cbInstr;
3272 ExitInfo.u64Qual = fMonitorHwArmed;
3273 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3274}
3275
3276
3277/**
3278 * VMX VM-exit handler for VM-exits due to PAUSE.
3279 *
3280 * @returns VBox strict status code.
3281 * @param pVCpu The cross context virtual CPU structure.
3282 * @param cbInstr The instruction length in bytes.
3283 */
3284IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3285{
3286 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3287
3288 /*
3289 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3290 * "PAUSE-loop exiting" control.
3291 *
3292 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3293 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3294 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3295 * a VM-exit.
3296 *
3297 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3298 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3299 */
3300 bool fIntercept = false;
3301 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3302 fIntercept = true;
3303 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3304 && pVCpu->iem.s.uCpl == 0)
3305 {
3306 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3307
3308 /*
3309 * A previous-PAUSE-tick value of 0 is used to identify the first time
3310 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3311 * consider this to be the first execution of PAUSE in a loop according
3312 * to the Intel.
3313 *
3314 * All subsequent records for the previous-PAUSE-tick we ensure that it
3315 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3316 */
3317 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3318 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3319 uint64_t const uTick = TMCpuTickGet(pVCpu);
3320 uint32_t const uPleGap = pVmcs->u32PleGap;
3321 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3322 if ( *puPrevPauseTick == 0
3323 || uTick - *puPrevPauseTick > uPleGap)
3324 *puFirstPauseLoopTick = uTick;
3325 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3326 fIntercept = true;
3327
3328 *puPrevPauseTick = uTick | 1;
3329 }
3330
3331 if (fIntercept)
3332 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3333
3334 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3335}
3336
3337
3338/**
3339 * VMX VM-exit handler for VM-exits due to task switches.
3340 *
3341 * @returns VBox strict status code.
3342 * @param pVCpu The cross context virtual CPU structure.
3343 * @param enmTaskSwitch The cause of the task switch.
3344 * @param SelNewTss The selector of the new TSS.
3345 * @param cbInstr The instruction length in bytes.
3346 */
3347IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3348{
3349 /*
3350 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3351 *
3352 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3353 * instruction or delivery of the exception generated by one of these instructions
3354 * lead to a task switch through a task gate in the IDT, we need to provide the
3355 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3356 * leaves the VM-exit instruction length field undefined.
3357 *
3358 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3359 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3360 */
3361 Assert(cbInstr <= 15);
3362
3363 uint8_t uType;
3364 switch (enmTaskSwitch)
3365 {
3366 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3367 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3368 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3369 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3370 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3371 }
3372
3373 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3374 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3375 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3376 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3377}
3378
3379
3380/**
3381 * VMX VM-exit handler for trap-like VM-exits.
3382 *
3383 * @returns VBox strict status code.
3384 * @param pVCpu The cross context virtual CPU structure.
3385 * @param pExitInfo Pointer to the VM-exit information.
3386 * @param pExitEventInfo Pointer to the VM-exit event information.
3387 */
3388IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3389{
3390 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3391 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3392 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3393}
3394
3395
3396/**
3397 * VMX VM-exit handler for VM-exits due to task switches.
3398 *
3399 * This is intended for task switches where the caller provides all the relevant
3400 * VM-exit information.
3401 *
3402 * @returns VBox strict status code.
3403 * @param pVCpu The cross context virtual CPU structure.
3404 * @param pExitInfo Pointer to the VM-exit information.
3405 * @param pExitEventInfo Pointer to the VM-exit event information.
3406 */
3407IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3408 PCVMXVEXITEVENTINFO pExitEventInfo)
3409{
3410 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3411 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3412 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3413 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3414 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3415}
3416
3417
3418/**
3419 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3420 *
3421 * @returns VBox strict status code.
3422 * @param pVCpu The cross context virtual CPU structure.
3423 */
3424IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3425{
3426 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3427 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3428
3429 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3430 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3431
3432 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3433 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3434 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3435
3436 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3437 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3438}
3439
3440
3441/**
3442 * VMX VM-exit handler for VM-exits due to external interrupts.
3443 *
3444 * @returns VBox strict status code.
3445 * @param pVCpu The cross context virtual CPU structure.
3446 * @param uVector The external interrupt vector (pass 0 if the interrupt
3447 * is still pending since we typically won't know the
3448 * vector).
3449 * @param fIntPending Whether the external interrupt is pending or
3450 * acknowledged in the interrupt controller.
3451 */
3452IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3453{
3454 Assert(!fIntPending || uVector == 0);
3455
3456 /* The VM-exit is subject to "External interrupt exiting" being set. */
3457 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3458 {
3459 if (fIntPending)
3460 {
3461 /*
3462 * If the interrupt is pending and we don't need to acknowledge the
3463 * interrupt on VM-exit, cause the VM-exit immediately.
3464 *
3465 * See Intel spec 25.2 "Other Causes Of VM Exits".
3466 */
3467 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3468 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3469
3470 /*
3471 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3472 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3473 * acknowledged that the interrupt has been consumed. Callers would have to call
3474 * us again after getting the vector (and ofc, with fIntPending with false).
3475 */
3476 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3477 }
3478
3479 /*
3480 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3481 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3482 * all set, we need to record the vector of the external interrupt in the
3483 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3484 *
3485 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3486 */
3487 uint32_t uExitIntInfo;
3488 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3489 {
3490 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3491 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3492 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3493 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3494 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3495 }
3496 else
3497 uExitIntInfo = 0;
3498 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3499
3500 /*
3501 * Cause the VM-exit whether or not the vector has been stored
3502 * in the VM-exit interruption-information field.
3503 */
3504 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3505 }
3506
3507 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3508}
3509
3510
3511/**
3512 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3513 * an event.
3514 *
3515 * @returns VBox strict status code.
3516 * @param pVCpu The cross context virtual CPU structure.
3517 */
3518IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3519{
3520 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3521 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3522 {
3523 /*
3524 * The NMI-unblocking due to IRET field need not be set for double faults.
3525 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3526 */
3527 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3528 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3529 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3530 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3531 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3532 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3533 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3534 }
3535
3536 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3537}
3538
3539
3540/**
3541 * VMX VM-exit handler for VM-exit due to delivery of an events.
3542 *
3543 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3544 * all the relevant VM-exit information.
3545 *
3546 * @returns VBox strict status code.
3547 * @param pVCpu The cross context virtual CPU structure.
3548 * @param pExitInfo Pointer to the VM-exit information.
3549 * @param pExitEventInfo Pointer to the VM-exit event information.
3550 */
3551IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3552{
3553 Assert(pExitInfo);
3554 Assert(pExitEventInfo);
3555 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3556 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3557
3558 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3559 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3560 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3561 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3562 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3563 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3564}
3565
3566
3567/**
3568 * VMX VM-exit handler for VM-exits due to delivery of an event.
3569 *
3570 * @returns VBox strict status code.
3571 * @param pVCpu The cross context virtual CPU structure.
3572 * @param uVector The interrupt / exception vector.
3573 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3574 * @param uErrCode The error code associated with the event.
3575 * @param uCr2 The CR2 value in case of a \#PF exception.
3576 * @param cbInstr The instruction length in bytes.
3577 */
3578IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3579 uint8_t cbInstr)
3580{
3581 /*
3582 * If the event is being injected as part of VM-entry, it is -not- subject to event
3583 * intercepts in the nested-guest. However, secondary exceptions that occur during
3584 * injection of any event -are- subject to event interception.
3585 *
3586 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3587 */
3588 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3589 {
3590 /*
3591 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3592 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3593 *
3594 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3595 */
3596 if ( uVector == X86_XCPT_NMI
3597 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3598 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3599 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3600 else
3601 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3602
3603 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3604 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3605 }
3606
3607 /*
3608 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3609 * If not, the caller will continue delivery of the external interrupt as it would
3610 * normally. The interrupt is no longer pending in the interrupt controller at this
3611 * point.
3612 */
3613 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3614 {
3615 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3616 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3617 }
3618
3619 /*
3620 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3621 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3622 * interrupts.
3623 */
3624 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3625 bool fIntercept;
3626 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3627 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3628 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3629 else
3630 {
3631 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3632 fIntercept = false;
3633 }
3634
3635 /*
3636 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3637 * relevant VM-exit information and cause the VM-exit.
3638 */
3639 if (fIntercept)
3640 {
3641 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3642
3643 /* Construct the rest of the event related information fields and cause the VM-exit. */
3644 uint64_t u64ExitQual;
3645 if (uVector == X86_XCPT_PF)
3646 {
3647 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3648 u64ExitQual = uCr2;
3649 }
3650 else if (uVector == X86_XCPT_DB)
3651 {
3652 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3653 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3654 }
3655 else
3656 u64ExitQual = 0;
3657
3658 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3659 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3660 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3661 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3662 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3663 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3664 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3665 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3666 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3667 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3668
3669 /*
3670 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3671 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3672 * length.
3673 */
3674 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3675 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3676 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3677 else
3678 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3679
3680 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3681 }
3682
3683 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3684}
3685
3686
3687/**
3688 * VMX VM-exit handler for EPT violation.
3689 *
3690 * @param pVCpu The cross context virtual CPU structure.
3691 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3692 * @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
3693 * @param fEptAccess The EPT paging structure bits.
3694 * @param GCPhysAddr The physical address causing the EPT violation.
3695 * @param fIsLinearAddrValid Whether translation of a linear address caused this
3696 * EPT violation. If @c false, GCPtrAddr must be 0.
3697 * @param GCPtrAddr The linear address causing the EPT violation.
3698 * @param cbInstr The VM-exit instruction length.
3699 */
3700IEM_STATIC VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail, uint64_t fEptAccess,
3701 RTGCPHYS GCPhysAddr, bool fLinearAddrValid, uint64_t GCPtrAddr, uint8_t cbInstr)
3702{
3703 /*
3704 * If the linear address isn't valid (can happen when loading PDPTEs
3705 * as part of MOV CR execution) the linear address field is undefined.
3706 * While we can leave it this way, it's preferrable to zero it for consistency.
3707 */
3708 Assert(fLinearAddrValid || GCPtrAddr == 0);
3709
3710 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3711 uint8_t const fSupportsAccessDirty = fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY;
3712
3713 uint8_t const fDataRead = ((fAccess & IEM_ACCESS_DATA_R) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3714 uint8_t const fDataWrite = ((fAccess & IEM_ACCESS_DATA_RW) == IEM_ACCESS_DATA_RW) | fSupportsAccessDirty;
3715 uint8_t const fInstrFetch = (fAccess & IEM_ACCESS_INSTRUCTION) == IEM_ACCESS_INSTRUCTION;
3716 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3717 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3718 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3719 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3720 bool const fLinearToPhysAddr = fLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
3721
3722 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
3723 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
3724 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
3725 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
3726 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
3727 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
3728 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fLinearAddrValid)
3729 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fLinearToPhysAddr)
3730 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
3731
3732#ifdef VBOX_STRICT
3733 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
3734 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
3735 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
3736 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
3737 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3738 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
3739#endif
3740
3741 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3742 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
3743 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3744
3745 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
3746}
3747
3748
3749/**
3750 * VMX VM-exit handler for EPT-induced VM-exits.
3751 *
3752 * @param pVCpu The cross context virtual CPU structure.
3753 * @param pWalk The page walk info.
3754 * @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
3755 * @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
3756 * @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
3757 * applicable.
3758 */
3759IEM_STATIC VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail,
3760 uint8_t cbInstr)
3761{
3762 Assert(pWalk->fIsSlat);
3763 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
3764 Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
3765 Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
3766
3767 if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
3768 {
3769 uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
3770 return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
3771 pWalk->GCPtr, cbInstr);
3772 }
3773 else
3774 {
3775 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
3776 /** @todo Do EPT misconfig. */
3777 return VERR_NOT_IMPLEMENTED;
3778 }
3779}
3780
3781
3782/**
3783 * VMX VM-exit handler for APIC accesses.
3784 *
3785 * @param pVCpu The cross context virtual CPU structure.
3786 * @param offAccess The offset of the register being accessed.
3787 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3788 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3789 */
3790IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3791{
3792 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3793
3794 VMXAPICACCESS enmAccess;
3795 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3796 if (fInEventDelivery)
3797 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3798 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3799 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3800 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3801 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3802 else
3803 enmAccess = VMXAPICACCESS_LINEAR_READ;
3804
3805 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3806 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3807 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3808}
3809
3810
3811/**
3812 * VMX VM-exit handler for APIC accesses.
3813 *
3814 * This is intended for APIC accesses where the caller provides all the
3815 * relevant VM-exit information.
3816 *
3817 * @returns VBox strict status code.
3818 * @param pVCpu The cross context virtual CPU structure.
3819 * @param pExitInfo Pointer to the VM-exit information.
3820 * @param pExitEventInfo Pointer to the VM-exit event information.
3821 */
3822IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3823 PCVMXVEXITEVENTINFO pExitEventInfo)
3824{
3825 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3826 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3827 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3828 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3829 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3830 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3831 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3832 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3833 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3834}
3835
3836
3837/**
3838 * VMX VM-exit handler for APIC-write VM-exits.
3839 *
3840 * @param pVCpu The cross context virtual CPU structure.
3841 * @param offApic The write to the virtual-APIC page offset that caused this
3842 * VM-exit.
3843 */
3844IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3845{
3846 Assert(offApic < XAPIC_OFF_END + 4);
3847 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3848 offApic &= UINT16_C(0xfff);
3849 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3850}
3851
3852
3853/**
3854 * Sets virtual-APIC write emulation as pending.
3855 *
3856 * @param pVCpu The cross context virtual CPU structure.
3857 * @param offApic The offset in the virtual-APIC page that was written.
3858 */
3859DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3860{
3861 Assert(offApic < XAPIC_OFF_END + 4);
3862
3863 /*
3864 * Record the currently updated APIC offset, as we need this later for figuring
3865 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3866 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3867 */
3868 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3869
3870 /*
3871 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3872 * virtualization or APIC-write emulation).
3873 */
3874 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3875 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3876}
3877
3878
3879/**
3880 * Clears any pending virtual-APIC write emulation.
3881 *
3882 * @returns The virtual-APIC offset that was written before clearing it.
3883 * @param pVCpu The cross context virtual CPU structure.
3884 */
3885DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3886{
3887 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3888 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3889 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3890 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3891 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3892 return offVirtApicWrite;
3893}
3894
3895
3896/**
3897 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3898 *
3899 * @returns The register from the virtual-APIC page.
3900 * @param pVCpu The cross context virtual CPU structure.
3901 * @param offReg The offset of the register being read.
3902 */
3903IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3904{
3905 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3906
3907 uint32_t uReg = 0;
3908 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3909 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3910 AssertMsgStmt(RT_SUCCESS(rc),
3911 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3912 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3913 uReg = 0);
3914 return uReg;
3915}
3916
3917
3918/**
3919 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3920 *
3921 * @returns The register from the virtual-APIC page.
3922 * @param pVCpu The cross context virtual CPU structure.
3923 * @param offReg The offset of the register being read.
3924 */
3925IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3926{
3927 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3928
3929 uint64_t uReg = 0;
3930 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3931 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3932 AssertMsgStmt(RT_SUCCESS(rc),
3933 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3934 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3935 uReg = 0);
3936 return uReg;
3937}
3938
3939
3940/**
3941 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3942 *
3943 * @param pVCpu The cross context virtual CPU structure.
3944 * @param offReg The offset of the register being written.
3945 * @param uReg The register value to write.
3946 */
3947IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3948{
3949 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3950
3951 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3952 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3953 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3954 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3955}
3956
3957
3958/**
3959 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3960 *
3961 * @param pVCpu The cross context virtual CPU structure.
3962 * @param offReg The offset of the register being written.
3963 * @param uReg The register value to write.
3964 */
3965IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3966{
3967 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3968
3969 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3970 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3971 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3972 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3973}
3974
3975
3976/**
3977 * Sets the vector in a virtual-APIC 256-bit sparse register.
3978 *
3979 * @param pVCpu The cross context virtual CPU structure.
3980 * @param offReg The offset of the 256-bit spare register.
3981 * @param uVector The vector to set.
3982 *
3983 * @remarks This is based on our APIC device code.
3984 */
3985IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
3986{
3987 /* Determine the vector offset within the chunk. */
3988 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
3989
3990 /* Read the chunk at the offset. */
3991 uint32_t uReg;
3992 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3993 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
3994 if (RT_SUCCESS(rc))
3995 {
3996 /* Modify the chunk. */
3997 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
3998 uReg |= RT_BIT(idxVectorBit);
3999
4000 /* Write the chunk. */
4001 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4002 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4003 uVector, offReg, GCPhysVirtApic, rc));
4004 }
4005 else
4006 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4007 uVector, offReg, GCPhysVirtApic, rc));
4008}
4009
4010
4011/**
4012 * Clears the vector in a virtual-APIC 256-bit sparse register.
4013 *
4014 * @param pVCpu The cross context virtual CPU structure.
4015 * @param offReg The offset of the 256-bit spare register.
4016 * @param uVector The vector to clear.
4017 *
4018 * @remarks This is based on our APIC device code.
4019 */
4020IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
4021{
4022 /* Determine the vector offset within the chunk. */
4023 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4024
4025 /* Read the chunk at the offset. */
4026 uint32_t uReg;
4027 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4028 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4029 if (RT_SUCCESS(rc))
4030 {
4031 /* Modify the chunk. */
4032 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4033 uReg &= ~RT_BIT(idxVectorBit);
4034
4035 /* Write the chunk. */
4036 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4037 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4038 uVector, offReg, GCPhysVirtApic, rc));
4039 }
4040 else
4041 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4042 uVector, offReg, GCPhysVirtApic, rc));
4043}
4044
4045
4046/**
4047 * Checks if a memory access to the APIC-access page must causes an APIC-access
4048 * VM-exit.
4049 *
4050 * @param pVCpu The cross context virtual CPU structure.
4051 * @param offAccess The offset of the register being accessed.
4052 * @param cbAccess The size of the access in bytes.
4053 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4054 * IEM_ACCESS_TYPE_WRITE).
4055 *
4056 * @remarks This must not be used for MSR-based APIC-access page accesses!
4057 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4058 */
4059IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4060{
4061 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4062 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4063
4064 /*
4065 * We must cause a VM-exit if any of the following are true:
4066 * - TPR shadowing isn't active.
4067 * - The access size exceeds 32-bits.
4068 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4069 *
4070 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4071 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4072 */
4073 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4074 || cbAccess > sizeof(uint32_t)
4075 || ((offAccess + cbAccess - 1) & 0xc)
4076 || offAccess >= XAPIC_OFF_END + 4)
4077 return true;
4078
4079 /*
4080 * If the access is part of an operation where we have already
4081 * virtualized a virtual-APIC write, we must cause a VM-exit.
4082 */
4083 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4084 return true;
4085
4086 /*
4087 * Check write accesses to the APIC-access page that cause VM-exits.
4088 */
4089 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4090 {
4091 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4092 {
4093 /*
4094 * With APIC-register virtualization, a write access to any of the
4095 * following registers are virtualized. Accessing any other register
4096 * causes a VM-exit.
4097 */
4098 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4099 switch (offAlignedAccess)
4100 {
4101 case XAPIC_OFF_ID:
4102 case XAPIC_OFF_TPR:
4103 case XAPIC_OFF_EOI:
4104 case XAPIC_OFF_LDR:
4105 case XAPIC_OFF_DFR:
4106 case XAPIC_OFF_SVR:
4107 case XAPIC_OFF_ESR:
4108 case XAPIC_OFF_ICR_LO:
4109 case XAPIC_OFF_ICR_HI:
4110 case XAPIC_OFF_LVT_TIMER:
4111 case XAPIC_OFF_LVT_THERMAL:
4112 case XAPIC_OFF_LVT_PERF:
4113 case XAPIC_OFF_LVT_LINT0:
4114 case XAPIC_OFF_LVT_LINT1:
4115 case XAPIC_OFF_LVT_ERROR:
4116 case XAPIC_OFF_TIMER_ICR:
4117 case XAPIC_OFF_TIMER_DCR:
4118 break;
4119 default:
4120 return true;
4121 }
4122 }
4123 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4124 {
4125 /*
4126 * With virtual-interrupt delivery, a write access to any of the
4127 * following registers are virtualized. Accessing any other register
4128 * causes a VM-exit.
4129 *
4130 * Note! The specification does not allow writing to offsets in-between
4131 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4132 */
4133 switch (offAccess)
4134 {
4135 case XAPIC_OFF_TPR:
4136 case XAPIC_OFF_EOI:
4137 case XAPIC_OFF_ICR_LO:
4138 break;
4139 default:
4140 return true;
4141 }
4142 }
4143 else
4144 {
4145 /*
4146 * Without APIC-register virtualization or virtual-interrupt delivery,
4147 * only TPR accesses are virtualized.
4148 */
4149 if (offAccess == XAPIC_OFF_TPR)
4150 { /* likely */ }
4151 else
4152 return true;
4153 }
4154 }
4155 else
4156 {
4157 /*
4158 * Check read accesses to the APIC-access page that cause VM-exits.
4159 */
4160 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4161 {
4162 /*
4163 * With APIC-register virtualization, a read access to any of the
4164 * following registers are virtualized. Accessing any other register
4165 * causes a VM-exit.
4166 */
4167 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4168 switch (offAlignedAccess)
4169 {
4170 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4171 case XAPIC_OFF_ID:
4172 case XAPIC_OFF_VERSION:
4173 case XAPIC_OFF_TPR:
4174 case XAPIC_OFF_EOI:
4175 case XAPIC_OFF_LDR:
4176 case XAPIC_OFF_DFR:
4177 case XAPIC_OFF_SVR:
4178 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4179 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4180 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4181 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4182 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4183 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4184 case XAPIC_OFF_ESR:
4185 case XAPIC_OFF_ICR_LO:
4186 case XAPIC_OFF_ICR_HI:
4187 case XAPIC_OFF_LVT_TIMER:
4188 case XAPIC_OFF_LVT_THERMAL:
4189 case XAPIC_OFF_LVT_PERF:
4190 case XAPIC_OFF_LVT_LINT0:
4191 case XAPIC_OFF_LVT_LINT1:
4192 case XAPIC_OFF_LVT_ERROR:
4193 case XAPIC_OFF_TIMER_ICR:
4194 case XAPIC_OFF_TIMER_DCR:
4195 break;
4196 default:
4197 return true;
4198 }
4199 }
4200 else
4201 {
4202 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4203 if (offAccess == XAPIC_OFF_TPR)
4204 { /* likely */ }
4205 else
4206 return true;
4207 }
4208 }
4209
4210 /* The APIC access is virtualized, does not cause a VM-exit. */
4211 return false;
4212}
4213
4214
4215/**
4216 * Virtualizes a memory-based APIC access where the address is not used to access
4217 * memory.
4218 *
4219 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4220 * page-faults but do not use the address to access memory.
4221 *
4222 * @param pVCpu The cross context virtual CPU structure.
4223 * @param pGCPhysAccess Pointer to the guest-physical address used.
4224 */
4225IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4226{
4227 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4228 Assert(pGCPhysAccess);
4229
4230 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4231 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4232 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4233
4234 if (GCPhysAccess == GCPhysApic)
4235 {
4236 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4237 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4238 uint16_t const cbAccess = 1;
4239 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4240 if (fIntercept)
4241 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4242
4243 *pGCPhysAccess = GCPhysApic | offAccess;
4244 return VINF_VMX_MODIFIES_BEHAVIOR;
4245 }
4246
4247 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4248}
4249
4250
4251/**
4252 * Virtualizes a memory-based APIC access.
4253 *
4254 * @returns VBox strict status code.
4255 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4256 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4257 *
4258 * @param pVCpu The cross context virtual CPU structure.
4259 * @param offAccess The offset of the register being accessed (within the
4260 * APIC-access page).
4261 * @param cbAccess The size of the access in bytes.
4262 * @param pvData Pointer to the data being written or where to store the data
4263 * being read.
4264 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4265 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4266 */
4267IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4268 uint32_t fAccess)
4269{
4270 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4271 Assert(pvData);
4272 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4273 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4274 || (fAccess & IEM_ACCESS_INSTRUCTION));
4275
4276 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4277 if (fIntercept)
4278 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4279
4280 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4281 {
4282 /*
4283 * A write access to the APIC-access page that is virtualized (rather than
4284 * causing a VM-exit) writes data to the virtual-APIC page.
4285 */
4286 uint32_t const u32Data = *(uint32_t *)pvData;
4287 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4288
4289 /*
4290 * Record the currently updated APIC offset, as we need this later for figuring
4291 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4292 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4293 *
4294 * After completion of the current operation, we need to perform TPR virtualization,
4295 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4296 *
4297 * The current operation may be a REP-prefixed string instruction, execution of any
4298 * other instruction, or delivery of an event through the IDT.
4299 *
4300 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4301 * performed now but later after completion of the current operation.
4302 *
4303 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4304 */
4305 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4306 }
4307 else
4308 {
4309 /*
4310 * A read access from the APIC-access page that is virtualized (rather than
4311 * causing a VM-exit) returns data from the virtual-APIC page.
4312 *
4313 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4314 */
4315 Assert(cbAccess <= 4);
4316 Assert(offAccess < XAPIC_OFF_END + 4);
4317 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4318
4319 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4320 u32Data &= s_auAccessSizeMasks[cbAccess];
4321 *(uint32_t *)pvData = u32Data;
4322 }
4323
4324 return VINF_VMX_MODIFIES_BEHAVIOR;
4325}
4326
4327
4328/**
4329 * Virtualizes an MSR-based APIC read access.
4330 *
4331 * @returns VBox strict status code.
4332 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4333 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4334 * handled by the x2APIC device.
4335 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4336 * not within the range of valid MSRs, caller must raise \#GP(0).
4337 * @param pVCpu The cross context virtual CPU structure.
4338 * @param idMsr The x2APIC MSR being read.
4339 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4340 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4341 */
4342IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4343{
4344 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4345 Assert(pu64Value);
4346
4347 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4348 {
4349 if ( idMsr >= MSR_IA32_X2APIC_START
4350 && idMsr <= MSR_IA32_X2APIC_END)
4351 {
4352 uint16_t const offReg = (idMsr & 0xff) << 4;
4353 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4354 *pu64Value = u64Value;
4355 return VINF_VMX_MODIFIES_BEHAVIOR;
4356 }
4357 return VERR_OUT_OF_RANGE;
4358 }
4359
4360 if (idMsr == MSR_IA32_X2APIC_TPR)
4361 {
4362 uint16_t const offReg = (idMsr & 0xff) << 4;
4363 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4364 *pu64Value = u64Value;
4365 return VINF_VMX_MODIFIES_BEHAVIOR;
4366 }
4367
4368 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4369}
4370
4371
4372/**
4373 * Virtualizes an MSR-based APIC write access.
4374 *
4375 * @returns VBox strict status code.
4376 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4377 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4378 * not within the range of valid MSRs, caller must raise \#GP(0).
4379 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4380 *
4381 * @param pVCpu The cross context virtual CPU structure.
4382 * @param idMsr The x2APIC MSR being written.
4383 * @param u64Value The value of the x2APIC MSR being written.
4384 */
4385IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4386{
4387 /*
4388 * Check if the access is to be virtualized.
4389 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4390 */
4391 if ( idMsr == MSR_IA32_X2APIC_TPR
4392 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4393 && ( idMsr == MSR_IA32_X2APIC_EOI
4394 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4395 {
4396 /* Validate the MSR write depending on the register. */
4397 switch (idMsr)
4398 {
4399 case MSR_IA32_X2APIC_TPR:
4400 case MSR_IA32_X2APIC_SELF_IPI:
4401 {
4402 if (u64Value & UINT64_C(0xffffffffffffff00))
4403 return VERR_OUT_OF_RANGE;
4404 break;
4405 }
4406 case MSR_IA32_X2APIC_EOI:
4407 {
4408 if (u64Value != 0)
4409 return VERR_OUT_OF_RANGE;
4410 break;
4411 }
4412 }
4413
4414 /* Write the MSR to the virtual-APIC page. */
4415 uint16_t const offReg = (idMsr & 0xff) << 4;
4416 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4417
4418 /*
4419 * Record the currently updated APIC offset, as we need this later for figuring
4420 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4421 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4422 */
4423 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4424
4425 return VINF_VMX_MODIFIES_BEHAVIOR;
4426 }
4427
4428 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4429}
4430
4431
4432/**
4433 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4434 *
4435 * @returns VBox status code.
4436 * @retval VINF_SUCCESS when the highest set bit is found.
4437 * @retval VERR_NOT_FOUND when no bit is set.
4438 *
4439 * @param pVCpu The cross context virtual CPU structure.
4440 * @param offReg The offset of the APIC 256-bit sparse register.
4441 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4442 * set in the register. Only valid when VINF_SUCCESS is
4443 * returned.
4444 *
4445 * @remarks The format of the 256-bit sparse register here mirrors that found in
4446 * real APIC hardware.
4447 */
4448static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4449{
4450 Assert(offReg < XAPIC_OFF_END + 4);
4451 Assert(pidxHighestBit);
4452
4453 /*
4454 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4455 * However, in each fragment only the first 4 bytes are used.
4456 */
4457 uint8_t const cFrags = 8;
4458 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4459 {
4460 uint16_t const offFrag = iFrag * 16;
4461 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4462 if (!u32Frag)
4463 continue;
4464
4465 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4466 Assert(idxHighestBit > 0);
4467 --idxHighestBit;
4468 Assert(idxHighestBit <= UINT8_MAX);
4469 *pidxHighestBit = idxHighestBit;
4470 return VINF_SUCCESS;
4471 }
4472 return VERR_NOT_FOUND;
4473}
4474
4475
4476/**
4477 * Evaluates pending virtual interrupts.
4478 *
4479 * @param pVCpu The cross context virtual CPU structure.
4480 */
4481IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4482{
4483 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4484
4485 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4486 {
4487 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4488 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4489
4490 if ((uRvi >> 4) > (uPpr >> 4))
4491 {
4492 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4493 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4494 }
4495 else
4496 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4497 }
4498}
4499
4500
4501/**
4502 * Performs PPR virtualization.
4503 *
4504 * @returns VBox strict status code.
4505 * @param pVCpu The cross context virtual CPU structure.
4506 */
4507IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4508{
4509 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4510 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4511
4512 /*
4513 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4514 * or EOI-virtualization.
4515 *
4516 * See Intel spec. 29.1.3 "PPR Virtualization".
4517 */
4518 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4519 uint32_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4520
4521 uint32_t uPpr;
4522 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4523 uPpr = uTpr & 0xff;
4524 else
4525 uPpr = uSvi & 0xf0;
4526
4527 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4528 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4529}
4530
4531
4532/**
4533 * Performs VMX TPR virtualization.
4534 *
4535 * @returns VBox strict status code.
4536 * @param pVCpu The cross context virtual CPU structure.
4537 */
4538IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4539{
4540 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4541
4542 /*
4543 * We should have already performed the virtual-APIC write to the TPR offset
4544 * in the virtual-APIC page. We now perform TPR virtualization.
4545 *
4546 * See Intel spec. 29.1.2 "TPR Virtualization".
4547 */
4548 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4549 {
4550 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4551 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4552
4553 /*
4554 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4555 * See Intel spec. 29.1.2 "TPR Virtualization".
4556 */
4557 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4558 {
4559 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4560 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4561 }
4562 }
4563 else
4564 {
4565 iemVmxPprVirtualization(pVCpu);
4566 iemVmxEvalPendingVirtIntrs(pVCpu);
4567 }
4568
4569 return VINF_SUCCESS;
4570}
4571
4572
4573/**
4574 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4575 * not.
4576 *
4577 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4578 * @param pVCpu The cross context virtual CPU structure.
4579 * @param uVector The interrupt that was acknowledged using an EOI.
4580 */
4581IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4582{
4583 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4584 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4585
4586 if (uVector < 64)
4587 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4588 if (uVector < 128)
4589 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4590 if (uVector < 192)
4591 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4592 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4593}
4594
4595
4596/**
4597 * Performs EOI virtualization.
4598 *
4599 * @returns VBox strict status code.
4600 * @param pVCpu The cross context virtual CPU structure.
4601 */
4602IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4603{
4604 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4605 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4606
4607 /*
4608 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4609 * and get the next guest-interrupt that's in-service (if any).
4610 *
4611 * See Intel spec. 29.1.4 "EOI Virtualization".
4612 */
4613 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4614 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4615 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4616
4617 uint8_t uVector = uSvi;
4618 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4619
4620 uVector = 0;
4621 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4622
4623 if (uVector)
4624 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4625 else
4626 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4627
4628 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4629 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4630
4631 iemVmxPprVirtualization(pVCpu);
4632 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4633 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4634 iemVmxEvalPendingVirtIntrs(pVCpu);
4635 return VINF_SUCCESS;
4636}
4637
4638
4639/**
4640 * Performs self-IPI virtualization.
4641 *
4642 * @returns VBox strict status code.
4643 * @param pVCpu The cross context virtual CPU structure.
4644 */
4645IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4646{
4647 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4648 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4649
4650 /*
4651 * We should have already performed the virtual-APIC write to the self-IPI offset
4652 * in the virtual-APIC page. We now perform self-IPI virtualization.
4653 *
4654 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4655 */
4656 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4657 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4658 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4659 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4660 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4661 if (uVector > uRvi)
4662 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4663 iemVmxEvalPendingVirtIntrs(pVCpu);
4664 return VINF_SUCCESS;
4665}
4666
4667
4668/**
4669 * Performs VMX APIC-write emulation.
4670 *
4671 * @returns VBox strict status code.
4672 * @param pVCpu The cross context virtual CPU structure.
4673 */
4674IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4675{
4676 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4677
4678 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4679 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4680
4681 /*
4682 * Perform APIC-write emulation based on the virtual-APIC register written.
4683 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4684 */
4685 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4686 VBOXSTRICTRC rcStrict;
4687 switch (offApicWrite)
4688 {
4689 case XAPIC_OFF_TPR:
4690 {
4691 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4692 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4693 uTpr &= UINT32_C(0x000000ff);
4694 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4695 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4696 rcStrict = iemVmxTprVirtualization(pVCpu);
4697 break;
4698 }
4699
4700 case XAPIC_OFF_EOI:
4701 {
4702 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4703 {
4704 /* Clear VEOI and perform EOI virtualization. */
4705 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4706 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4707 rcStrict = iemVmxEoiVirtualization(pVCpu);
4708 }
4709 else
4710 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4711 break;
4712 }
4713
4714 case XAPIC_OFF_ICR_LO:
4715 {
4716 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4717 {
4718 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4719 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4720 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4721 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4722 if ( !(uIcrLo & fIcrLoMb0)
4723 && (uIcrLo & fIcrLoMb1))
4724 {
4725 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4726 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4727 }
4728 else
4729 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4730 }
4731 else
4732 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4733 break;
4734 }
4735
4736 case XAPIC_OFF_ICR_HI:
4737 {
4738 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4739 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4740 uIcrHi &= UINT32_C(0xff000000);
4741 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4742 rcStrict = VINF_SUCCESS;
4743 break;
4744 }
4745
4746 default:
4747 {
4748 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4749 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4750 break;
4751 }
4752 }
4753
4754 return rcStrict;
4755}
4756
4757
4758/**
4759 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4760 *
4761 * @param pVCpu The cross context virtual CPU structure.
4762 * @param pszInstr The VMX instruction name (for logging purposes).
4763 */
4764DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4765{
4766 /*
4767 * Guest Control Registers, Debug Registers, and MSRs.
4768 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4769 */
4770 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4771 const char * const pszFailure = "VM-exit";
4772 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4773
4774 /* CR0 reserved bits. */
4775 {
4776 /* CR0 MB1 bits. */
4777 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4778 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4779 if (fUnrestrictedGuest)
4780 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4781 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4782 { /* likely */ }
4783 else
4784 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4785
4786 /* CR0 MBZ bits. */
4787 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4788 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4789 { /* likely */ }
4790 else
4791 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4792
4793 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4794 if ( !fUnrestrictedGuest
4795 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4796 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4797 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4798 }
4799
4800 /* CR4 reserved bits. */
4801 {
4802 /* CR4 MB1 bits. */
4803 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4804 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4805 { /* likely */ }
4806 else
4807 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4808
4809 /* CR4 MBZ bits. */
4810 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4811 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4812 { /* likely */ }
4813 else
4814 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4815 }
4816
4817 /* DEBUGCTL MSR. */
4818 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4819 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4820 { /* likely */ }
4821 else
4822 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4823
4824 /* 64-bit CPU checks. */
4825 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4826 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4827 {
4828 if (fGstInLongMode)
4829 {
4830 /* PAE must be set. */
4831 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4832 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4833 { /* likely */ }
4834 else
4835 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4836 }
4837 else
4838 {
4839 /* PCIDE should not be set. */
4840 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4841 { /* likely */ }
4842 else
4843 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4844 }
4845
4846 /* CR3. */
4847 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4848 { /* likely */ }
4849 else
4850 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4851
4852 /* DR7. */
4853 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4854 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4855 { /* likely */ }
4856 else
4857 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4858
4859 /* SYSENTER ESP and SYSENTER EIP. */
4860 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4861 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4862 { /* likely */ }
4863 else
4864 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4865 }
4866
4867 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4868 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4869
4870 /* PAT MSR. */
4871 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4872 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4873 { /* likely */ }
4874 else
4875 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4876
4877 /* EFER MSR. */
4878 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4879 {
4880 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4881 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4882 { /* likely */ }
4883 else
4884 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4885
4886 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4887 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4888 if ( fGstLma == fGstInLongMode
4889 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4890 || fGstLma == fGstLme))
4891 { /* likely */ }
4892 else
4893 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4894 }
4895
4896 /* We don't support IA32_BNDCFGS MSR yet. */
4897 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4898
4899 NOREF(pszInstr);
4900 NOREF(pszFailure);
4901 return VINF_SUCCESS;
4902}
4903
4904
4905/**
4906 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4907 *
4908 * @param pVCpu The cross context virtual CPU structure.
4909 * @param pszInstr The VMX instruction name (for logging purposes).
4910 */
4911DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4912{
4913 /*
4914 * Segment registers.
4915 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4916 */
4917 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4918 const char * const pszFailure = "VM-exit";
4919 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4920 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4921 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4922
4923 /* Selectors. */
4924 if ( !fGstInV86Mode
4925 && !fUnrestrictedGuest
4926 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4927 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4928
4929 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4930 {
4931 CPUMSELREG SelReg;
4932 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4933 if (RT_LIKELY(rc == VINF_SUCCESS))
4934 { /* likely */ }
4935 else
4936 return rc;
4937
4938 /*
4939 * Virtual-8086 mode checks.
4940 */
4941 if (fGstInV86Mode)
4942 {
4943 /* Base address. */
4944 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4945 { /* likely */ }
4946 else
4947 {
4948 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4949 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4950 }
4951
4952 /* Limit. */
4953 if (SelReg.u32Limit == 0xffff)
4954 { /* likely */ }
4955 else
4956 {
4957 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4958 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4959 }
4960
4961 /* Attribute. */
4962 if (SelReg.Attr.u == 0xf3)
4963 { /* likely */ }
4964 else
4965 {
4966 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4967 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4968 }
4969
4970 /* We're done; move to checking the next segment. */
4971 continue;
4972 }
4973
4974 /* Checks done by 64-bit CPUs. */
4975 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4976 {
4977 /* Base address. */
4978 if ( iSegReg == X86_SREG_FS
4979 || iSegReg == X86_SREG_GS)
4980 {
4981 if (X86_IS_CANONICAL(SelReg.u64Base))
4982 { /* likely */ }
4983 else
4984 {
4985 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
4986 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4987 }
4988 }
4989 else if (iSegReg == X86_SREG_CS)
4990 {
4991 if (!RT_HI_U32(SelReg.u64Base))
4992 { /* likely */ }
4993 else
4994 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
4995 }
4996 else
4997 {
4998 if ( SelReg.Attr.n.u1Unusable
4999 || !RT_HI_U32(SelReg.u64Base))
5000 { /* likely */ }
5001 else
5002 {
5003 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5004 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5005 }
5006 }
5007 }
5008
5009 /*
5010 * Checks outside Virtual-8086 mode.
5011 */
5012 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5013 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5014 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5015 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5016 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5017 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5018 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5019 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5020
5021 /* Code or usable segment. */
5022 if ( iSegReg == X86_SREG_CS
5023 || fUsable)
5024 {
5025 /* Reserved bits (bits 31:17 and bits 11:8). */
5026 if (!(SelReg.Attr.u & 0xfffe0f00))
5027 { /* likely */ }
5028 else
5029 {
5030 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5031 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5032 }
5033
5034 /* Descriptor type. */
5035 if (fCodeDataSeg)
5036 { /* likely */ }
5037 else
5038 {
5039 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5040 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5041 }
5042
5043 /* Present. */
5044 if (fPresent)
5045 { /* likely */ }
5046 else
5047 {
5048 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5049 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5050 }
5051
5052 /* Granularity. */
5053 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5054 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5055 { /* likely */ }
5056 else
5057 {
5058 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5059 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5060 }
5061 }
5062
5063 if (iSegReg == X86_SREG_CS)
5064 {
5065 /* Segment Type and DPL. */
5066 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5067 && fUnrestrictedGuest)
5068 {
5069 if (uDpl == 0)
5070 { /* likely */ }
5071 else
5072 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5073 }
5074 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5075 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5076 {
5077 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5078 if (uDpl == AttrSs.n.u2Dpl)
5079 { /* likely */ }
5080 else
5081 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5082 }
5083 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5084 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5085 {
5086 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5087 if (uDpl <= AttrSs.n.u2Dpl)
5088 { /* likely */ }
5089 else
5090 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5091 }
5092 else
5093 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5094
5095 /* Def/Big. */
5096 if ( fGstInLongMode
5097 && fSegLong)
5098 {
5099 if (uDefBig == 0)
5100 { /* likely */ }
5101 else
5102 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5103 }
5104 }
5105 else if (iSegReg == X86_SREG_SS)
5106 {
5107 /* Segment Type. */
5108 if ( !fUsable
5109 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5110 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5111 { /* likely */ }
5112 else
5113 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5114
5115 /* DPL. */
5116 if (!fUnrestrictedGuest)
5117 {
5118 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5119 { /* likely */ }
5120 else
5121 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5122 }
5123 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5124 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5125 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5126 {
5127 if (uDpl == 0)
5128 { /* likely */ }
5129 else
5130 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5131 }
5132 }
5133 else
5134 {
5135 /* DS, ES, FS, GS. */
5136 if (fUsable)
5137 {
5138 /* Segment type. */
5139 if (uSegType & X86_SEL_TYPE_ACCESSED)
5140 { /* likely */ }
5141 else
5142 {
5143 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5144 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5145 }
5146
5147 if ( !(uSegType & X86_SEL_TYPE_CODE)
5148 || (uSegType & X86_SEL_TYPE_READ))
5149 { /* likely */ }
5150 else
5151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5152
5153 /* DPL. */
5154 if ( !fUnrestrictedGuest
5155 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5156 {
5157 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5158 { /* likely */ }
5159 else
5160 {
5161 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5162 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5163 }
5164 }
5165 }
5166 }
5167 }
5168
5169 /*
5170 * LDTR.
5171 */
5172 {
5173 CPUMSELREG Ldtr;
5174 Ldtr.Sel = pVmcs->GuestLdtr;
5175 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5176 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5177 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5178
5179 if (!Ldtr.Attr.n.u1Unusable)
5180 {
5181 /* Selector. */
5182 if (!(Ldtr.Sel & X86_SEL_LDT))
5183 { /* likely */ }
5184 else
5185 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5186
5187 /* Base. */
5188 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5189 {
5190 if (X86_IS_CANONICAL(Ldtr.u64Base))
5191 { /* likely */ }
5192 else
5193 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5194 }
5195
5196 /* Attributes. */
5197 /* Reserved bits (bits 31:17 and bits 11:8). */
5198 if (!(Ldtr.Attr.u & 0xfffe0f00))
5199 { /* likely */ }
5200 else
5201 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5202
5203 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5204 { /* likely */ }
5205 else
5206 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5207
5208 if (!Ldtr.Attr.n.u1DescType)
5209 { /* likely */ }
5210 else
5211 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5212
5213 if (Ldtr.Attr.n.u1Present)
5214 { /* likely */ }
5215 else
5216 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5217
5218 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5219 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5220 { /* likely */ }
5221 else
5222 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5223 }
5224 }
5225
5226 /*
5227 * TR.
5228 */
5229 {
5230 CPUMSELREG Tr;
5231 Tr.Sel = pVmcs->GuestTr;
5232 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5233 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5234 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5235
5236 /* Selector. */
5237 if (!(Tr.Sel & X86_SEL_LDT))
5238 { /* likely */ }
5239 else
5240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5241
5242 /* Base. */
5243 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5244 {
5245 if (X86_IS_CANONICAL(Tr.u64Base))
5246 { /* likely */ }
5247 else
5248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5249 }
5250
5251 /* Attributes. */
5252 /* Reserved bits (bits 31:17 and bits 11:8). */
5253 if (!(Tr.Attr.u & 0xfffe0f00))
5254 { /* likely */ }
5255 else
5256 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5257
5258 if (!Tr.Attr.n.u1Unusable)
5259 { /* likely */ }
5260 else
5261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5262
5263 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5264 || ( !fGstInLongMode
5265 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5266 { /* likely */ }
5267 else
5268 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5269
5270 if (!Tr.Attr.n.u1DescType)
5271 { /* likely */ }
5272 else
5273 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5274
5275 if (Tr.Attr.n.u1Present)
5276 { /* likely */ }
5277 else
5278 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5279
5280 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5281 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5282 { /* likely */ }
5283 else
5284 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5285 }
5286
5287 NOREF(pszInstr);
5288 NOREF(pszFailure);
5289 return VINF_SUCCESS;
5290}
5291
5292
5293/**
5294 * Checks guest GDTR and IDTR as part of VM-entry.
5295 *
5296 * @param pVCpu The cross context virtual CPU structure.
5297 * @param pszInstr The VMX instruction name (for logging purposes).
5298 */
5299DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5300{
5301 /*
5302 * GDTR and IDTR.
5303 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5304 */
5305 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5306 const char *const pszFailure = "VM-exit";
5307
5308 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5309 {
5310 /* Base. */
5311 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5312 { /* likely */ }
5313 else
5314 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5315
5316 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5317 { /* likely */ }
5318 else
5319 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5320 }
5321
5322 /* Limit. */
5323 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5324 { /* likely */ }
5325 else
5326 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5327
5328 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5329 { /* likely */ }
5330 else
5331 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5332
5333 NOREF(pszInstr);
5334 NOREF(pszFailure);
5335 return VINF_SUCCESS;
5336}
5337
5338
5339/**
5340 * Checks guest RIP and RFLAGS as part of VM-entry.
5341 *
5342 * @param pVCpu The cross context virtual CPU structure.
5343 * @param pszInstr The VMX instruction name (for logging purposes).
5344 */
5345DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5346{
5347 /*
5348 * RIP and RFLAGS.
5349 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5350 */
5351 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5352 const char *const pszFailure = "VM-exit";
5353 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5354
5355 /* RIP. */
5356 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5357 {
5358 X86DESCATTR AttrCs;
5359 AttrCs.u = pVmcs->u32GuestCsAttr;
5360 if ( !fGstInLongMode
5361 || !AttrCs.n.u1Long)
5362 {
5363 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5364 { /* likely */ }
5365 else
5366 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5367 }
5368
5369 if ( fGstInLongMode
5370 && AttrCs.n.u1Long)
5371 {
5372 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5373 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5374 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5375 { /* likely */ }
5376 else
5377 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5378 }
5379 }
5380
5381 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5382 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5383 : pVmcs->u64GuestRFlags.s.Lo;
5384 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5385 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5386 { /* likely */ }
5387 else
5388 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5389
5390 if ( fGstInLongMode
5391 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5392 {
5393 if (!(uGuestRFlags & X86_EFL_VM))
5394 { /* likely */ }
5395 else
5396 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5397 }
5398
5399 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5400 {
5401 if (uGuestRFlags & X86_EFL_IF)
5402 { /* likely */ }
5403 else
5404 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5405 }
5406
5407 NOREF(pszInstr);
5408 NOREF(pszFailure);
5409 return VINF_SUCCESS;
5410}
5411
5412
5413/**
5414 * Checks guest non-register state as part of VM-entry.
5415 *
5416 * @param pVCpu The cross context virtual CPU structure.
5417 * @param pszInstr The VMX instruction name (for logging purposes).
5418 */
5419DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5420{
5421 /*
5422 * Guest non-register state.
5423 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5424 */
5425 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5426 const char *const pszFailure = "VM-exit";
5427
5428 /*
5429 * Activity state.
5430 */
5431 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5432 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5433 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5434 { /* likely */ }
5435 else
5436 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5437
5438 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5439 if ( !AttrSs.n.u2Dpl
5440 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5441 { /* likely */ }
5442 else
5443 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5444
5445 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5446 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5447 {
5448 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5449 { /* likely */ }
5450 else
5451 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5452 }
5453
5454 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5455 {
5456 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5457 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5458 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5459 switch (pVmcs->u32GuestActivityState)
5460 {
5461 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5462 {
5463 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5464 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5465 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5466 && ( uVector == X86_XCPT_DB
5467 || uVector == X86_XCPT_MC))
5468 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5469 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5470 { /* likely */ }
5471 else
5472 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5473 break;
5474 }
5475
5476 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5477 {
5478 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5479 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5480 && uVector == X86_XCPT_MC))
5481 { /* likely */ }
5482 else
5483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5484 break;
5485 }
5486
5487 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5488 default:
5489 break;
5490 }
5491 }
5492
5493 /*
5494 * Interruptibility state.
5495 */
5496 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5497 { /* likely */ }
5498 else
5499 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5500
5501 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5502 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5503 { /* likely */ }
5504 else
5505 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5506
5507 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5508 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5509 { /* likely */ }
5510 else
5511 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5512
5513 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5514 {
5515 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5516 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5517 {
5518 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5519 { /* likely */ }
5520 else
5521 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5522 }
5523 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5524 {
5525 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5526 { /* likely */ }
5527 else
5528 {
5529 /*
5530 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5531 * We update the Exit qualification only when blocking-by-STI is set
5532 * without blocking-by-MovSS being set. Although in practise it does not
5533 * make much difference since the order of checks are implementation defined.
5534 */
5535 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5536 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5537 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5538 }
5539
5540 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5541 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5542 { /* likely */ }
5543 else
5544 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5545 }
5546 }
5547
5548 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5549 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5550 { /* likely */ }
5551 else
5552 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5553
5554 /* We don't support SGX yet. So enclave-interruption must not be set. */
5555 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5556 { /* likely */ }
5557 else
5558 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5559
5560 /*
5561 * Pending debug exceptions.
5562 */
5563 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5564 ? pVmcs->u64GuestPendingDbgXcpts.u
5565 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5566 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5567 { /* likely */ }
5568 else
5569 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5570
5571 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5572 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5573 {
5574 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5575 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5576 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5577 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5578
5579 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5580 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5581 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5582 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5583 }
5584
5585 /* We don't support RTM (Real-time Transactional Memory) yet. */
5586 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5587 { /* likely */ }
5588 else
5589 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5590
5591 /*
5592 * VMCS link pointer.
5593 */
5594 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5595 {
5596 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5597 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5598 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5599 { /* likely */ }
5600 else
5601 {
5602 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5603 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5604 }
5605
5606 /* Validate the address. */
5607 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5608 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5609 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5610 { /* likely */ }
5611 else
5612 {
5613 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5614 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5615 }
5616 }
5617
5618 NOREF(pszInstr);
5619 NOREF(pszFailure);
5620 return VINF_SUCCESS;
5621}
5622
5623
5624#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5625/**
5626 * Checks guest PDPTEs as part of VM-entry.
5627 *
5628 * @param pVCpu The cross context virtual CPU structure.
5629 * @param pszInstr The VMX instruction name (for logging purposes).
5630 */
5631IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr)
5632{
5633 /*
5634 * Guest PDPTEs.
5635 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5636 */
5637 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5638 const char * const pszFailure = "VM-exit";
5639
5640 /*
5641 * When EPT is used, we only validate the PAE PDPTEs provided in the VMCS.
5642 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
5643 */
5644 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
5645 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
5646 {
5647 /* Get PDPTEs from the VMCS. */
5648 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
5649 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
5650 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
5651 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
5652 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
5653
5654 /* Check validity of the PDPTEs. */
5655 bool const fValid = PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]);
5656 if (fValid)
5657 { /* likely */ }
5658 else
5659 {
5660 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5661 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5662 }
5663 }
5664
5665 NOREF(pszFailure);
5666 NOREF(pszInstr);
5667 return VINF_SUCCESS;
5668}
5669#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
5670
5671
5672/**
5673 * Checks guest-state as part of VM-entry.
5674 *
5675 * @returns VBox status code.
5676 * @param pVCpu The cross context virtual CPU structure.
5677 * @param pszInstr The VMX instruction name (for logging purposes).
5678 */
5679IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr)
5680{
5681 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5682 if (RT_SUCCESS(rc))
5683 {
5684 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5685 if (RT_SUCCESS(rc))
5686 {
5687 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5688 if (RT_SUCCESS(rc))
5689 {
5690 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5691 if (RT_SUCCESS(rc))
5692 {
5693 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5694#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5695 if (RT_SUCCESS(rc))
5696 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5697#endif
5698 }
5699 }
5700 }
5701 }
5702 return rc;
5703}
5704
5705
5706/**
5707 * Checks host-state as part of VM-entry.
5708 *
5709 * @returns VBox status code.
5710 * @param pVCpu The cross context virtual CPU structure.
5711 * @param pszInstr The VMX instruction name (for logging purposes).
5712 */
5713IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5714{
5715 /*
5716 * Host Control Registers and MSRs.
5717 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5718 */
5719 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5720 const char * const pszFailure = "VMFail";
5721
5722 /* CR0 reserved bits. */
5723 {
5724 /* CR0 MB1 bits. */
5725 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5726 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5727 { /* likely */ }
5728 else
5729 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5730
5731 /* CR0 MBZ bits. */
5732 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5733 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5734 { /* likely */ }
5735 else
5736 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5737 }
5738
5739 /* CR4 reserved bits. */
5740 {
5741 /* CR4 MB1 bits. */
5742 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5743 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5744 { /* likely */ }
5745 else
5746 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5747
5748 /* CR4 MBZ bits. */
5749 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5750 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5751 { /* likely */ }
5752 else
5753 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5754 }
5755
5756 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5757 {
5758 /* CR3 reserved bits. */
5759 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5760 { /* likely */ }
5761 else
5762 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5763
5764 /* SYSENTER ESP and SYSENTER EIP. */
5765 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5766 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5767 { /* likely */ }
5768 else
5769 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5770 }
5771
5772 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5773 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5774
5775 /* PAT MSR. */
5776 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5777 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5778 { /* likely */ }
5779 else
5780 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5781
5782 /* EFER MSR. */
5783 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5784 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5785 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5786 { /* likely */ }
5787 else
5788 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5789
5790 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5791 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5792 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5793 if ( fHostInLongMode == fHostLma
5794 && fHostInLongMode == fHostLme)
5795 { /* likely */ }
5796 else
5797 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5798
5799 /*
5800 * Host Segment and Descriptor-Table Registers.
5801 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5802 */
5803 /* Selector RPL and TI. */
5804 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5805 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5806 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5807 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5808 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5809 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5810 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5811 { /* likely */ }
5812 else
5813 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5814
5815 /* CS and TR selectors cannot be 0. */
5816 if ( pVmcs->HostCs
5817 && pVmcs->HostTr)
5818 { /* likely */ }
5819 else
5820 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5821
5822 /* SS cannot be 0 if 32-bit host. */
5823 if ( fHostInLongMode
5824 || pVmcs->HostSs)
5825 { /* likely */ }
5826 else
5827 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5828
5829 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5830 {
5831 /* FS, GS, GDTR, IDTR, TR base address. */
5832 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5833 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5834 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5835 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5836 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5837 { /* likely */ }
5838 else
5839 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5840 }
5841
5842 /*
5843 * Host address-space size for 64-bit CPUs.
5844 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5845 */
5846 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5847 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5848 {
5849 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5850
5851 /* Logical processor in IA-32e mode. */
5852 if (fCpuInLongMode)
5853 {
5854 if (fHostInLongMode)
5855 {
5856 /* PAE must be set. */
5857 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5858 { /* likely */ }
5859 else
5860 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5861
5862 /* RIP must be canonical. */
5863 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5864 { /* likely */ }
5865 else
5866 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5867 }
5868 else
5869 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5870 }
5871 else
5872 {
5873 /* Logical processor is outside IA-32e mode. */
5874 if ( !fGstInLongMode
5875 && !fHostInLongMode)
5876 {
5877 /* PCIDE should not be set. */
5878 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5879 { /* likely */ }
5880 else
5881 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5882
5883 /* The high 32-bits of RIP MBZ. */
5884 if (!pVmcs->u64HostRip.s.Hi)
5885 { /* likely */ }
5886 else
5887 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5888 }
5889 else
5890 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5891 }
5892 }
5893 else
5894 {
5895 /* Host address-space size for 32-bit CPUs. */
5896 if ( !fGstInLongMode
5897 && !fHostInLongMode)
5898 { /* likely */ }
5899 else
5900 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5901 }
5902
5903 NOREF(pszInstr);
5904 NOREF(pszFailure);
5905 return VINF_SUCCESS;
5906}
5907
5908
5909#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5910/**
5911 * Checks the EPT pointer VMCS field as part of VM-entry.
5912 *
5913 * @returns VBox status code.
5914 * @param pVCpu The cross context virtual CPU structure.
5915 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
5916 * updated on success). Optional, can be NULL.
5917 */
5918IEM_STATIC int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, VMXVDIAG *penmVmxDiag)
5919{
5920 VMXVDIAG enmVmxDiag;
5921 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5922
5923 /* Reserved bits. */
5924 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
5925 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
5926 if (pVmcs->u64EptPtr.u & fValidMask)
5927 {
5928 /* Memory Type. */
5929 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
5930 uint8_t const fMemType = RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_MEMTYPE);
5931 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
5932 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
5933 || ( fMemType == VMX_EPTP_MEMTYPE_UC
5934 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
5935 {
5936 /*
5937 * Page walk length (PML4).
5938 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
5939 * of 5 but that seems to be removed from the latest specs. leaving only PML4
5940 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
5941 */
5942 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
5943 if (RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
5944 {
5945 /* Access and dirty bits support in EPT structures. */
5946 if ( !RT_BF_GET(pVmcs->u64EptPtr.u, VMX_BF_EPTP_ACCESS_DIRTY)
5947 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
5948 return VINF_SUCCESS;
5949
5950 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
5951 }
5952 else
5953 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
5954 }
5955 else
5956 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
5957 }
5958 else
5959 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
5960
5961 if (penmVmxDiag)
5962 *penmVmxDiag = enmVmxDiag;
5963 return VERR_VMX_VMENTRY_FAILED;
5964}
5965#endif
5966
5967
5968/**
5969 * Checks VMCS controls fields as part of VM-entry.
5970 *
5971 * @returns VBox status code.
5972 * @param pVCpu The cross context virtual CPU structure.
5973 * @param pszInstr The VMX instruction name (for logging purposes).
5974 *
5975 * @remarks This may update secondary-processor based VM-execution control fields
5976 * in the current VMCS if necessary.
5977 */
5978IEM_STATIC int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr)
5979{
5980 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5981 const char * const pszFailure = "VMFail";
5982
5983 /*
5984 * VM-execution controls.
5985 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
5986 */
5987 {
5988 /* Pin-based VM-execution controls. */
5989 {
5990 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
5991 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
5992 { /* likely */ }
5993 else
5994 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
5995
5996 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
5997 { /* likely */ }
5998 else
5999 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6000 }
6001
6002 /* Processor-based VM-execution controls. */
6003 {
6004 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6005 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6006 { /* likely */ }
6007 else
6008 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6009
6010 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6011 { /* likely */ }
6012 else
6013 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6014 }
6015
6016 /* Secondary processor-based VM-execution controls. */
6017 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6018 {
6019 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6020 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6021 { /* likely */ }
6022 else
6023 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6024
6025 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6026 { /* likely */ }
6027 else
6028 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6029 }
6030 else
6031 Assert(!pVmcs->u32ProcCtls2);
6032
6033 /* CR3-target count. */
6034 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6035 { /* likely */ }
6036 else
6037 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6038
6039 /* I/O bitmaps physical addresses. */
6040 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6041 {
6042 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6043 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6044 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6045 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6046 { /* likely */ }
6047 else
6048 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6049
6050 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6051 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6052 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6053 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6054 { /* likely */ }
6055 else
6056 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6057 }
6058
6059 /* MSR bitmap physical address. */
6060 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6061 {
6062 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6063 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6064 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6065 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6066 { /* likely */ }
6067 else
6068 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6069 }
6070
6071 /* TPR shadow related controls. */
6072 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6073 {
6074 /* Virtual-APIC page physical address. */
6075 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6076 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6077 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6078 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6079 { /* likely */ }
6080 else
6081 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6082
6083 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6084 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6085 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6086 { /* likely */ }
6087 else
6088 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6089
6090 /* The rest done XXX document */
6091 }
6092 else
6093 {
6094 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6095 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6096 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6097 { /* likely */ }
6098 else
6099 {
6100 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6101 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6102 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6103 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6104 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6105 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6106 }
6107 }
6108
6109 /* NMI exiting and virtual-NMIs. */
6110 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6111 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6112 { /* likely */ }
6113 else
6114 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6115
6116 /* Virtual-NMIs and NMI-window exiting. */
6117 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6118 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6119 { /* likely */ }
6120 else
6121 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6122
6123 /* Virtualize APIC accesses. */
6124 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6125 {
6126 /* APIC-access physical address. */
6127 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6128 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6129 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6130 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6131 { /* likely */ }
6132 else
6133 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6134
6135 /*
6136 * Disallow APIC-access page and virtual-APIC page from being the same address.
6137 * Note! This is not an Intel requirement, but one imposed by our implementation.
6138 */
6139 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6140 * redirecting accesses between the APIC-access page and the virtual-APIC
6141 * page. If any nested hypervisor requires this, we can implement it later. */
6142 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6143 {
6144 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6145 if (GCPhysVirtApic != GCPhysApicAccess)
6146 { /* likely */ }
6147 else
6148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6149 }
6150 }
6151
6152 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6153 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6154 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6155 { /* likely */ }
6156 else
6157 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6158
6159 /* Virtual-interrupt delivery requires external interrupt exiting. */
6160 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6161 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6162 { /* likely */ }
6163 else
6164 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6165
6166 /* VPID. */
6167 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6168 || pVmcs->u16Vpid != 0)
6169 { /* likely */ }
6170 else
6171 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6172
6173#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6174 /* Extended-Page-Table Pointer (EPTP). */
6175 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6176 {
6177 VMXVDIAG enmVmxDiag;
6178 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, &enmVmxDiag);
6179 if (RT_SUCCESS(rc))
6180 { /* likely */ }
6181 else
6182 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6183 }
6184#else
6185 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6186#endif
6187
6188 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6189 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6190 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6191 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6192 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6193 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6194 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6195
6196 /* VMCS shadowing. */
6197 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6198 {
6199 /* VMREAD-bitmap physical address. */
6200 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6201 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6202 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6203 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6204 { /* likely */ }
6205 else
6206 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6207
6208 /* VMWRITE-bitmap physical address. */
6209 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6210 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6211 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6212 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6213 { /* likely */ }
6214 else
6215 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6216 }
6217 }
6218
6219 /*
6220 * VM-exit controls.
6221 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6222 */
6223 {
6224 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6225 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6226 { /* likely */ }
6227 else
6228 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6229
6230 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6231 { /* likely */ }
6232 else
6233 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6234
6235 /* Save preemption timer without activating it. */
6236 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6237 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6238 { /* likely */ }
6239 else
6240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6241
6242 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6243 if (pVmcs->u32ExitMsrStoreCount)
6244 {
6245 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6246 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6247 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6248 { /* likely */ }
6249 else
6250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6251 }
6252
6253 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6254 if (pVmcs->u32ExitMsrLoadCount)
6255 {
6256 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6257 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6258 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6259 { /* likely */ }
6260 else
6261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6262 }
6263 }
6264
6265 /*
6266 * VM-entry controls.
6267 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6268 */
6269 {
6270 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6271 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6272 { /* likely */ }
6273 else
6274 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6275
6276 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6277 { /* likely */ }
6278 else
6279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6280
6281 /* Event injection. */
6282 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6283 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6284 {
6285 /* Type and vector. */
6286 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6287 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6288 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6289 if ( !uRsvd
6290 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6291 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6292 { /* likely */ }
6293 else
6294 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6295
6296 /* Exception error code. */
6297 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6298 {
6299 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6300 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6301 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6302 { /* likely */ }
6303 else
6304 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6305
6306 /* Exceptions that provide an error code. */
6307 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6308 && ( uVector == X86_XCPT_DF
6309 || uVector == X86_XCPT_TS
6310 || uVector == X86_XCPT_NP
6311 || uVector == X86_XCPT_SS
6312 || uVector == X86_XCPT_GP
6313 || uVector == X86_XCPT_PF
6314 || uVector == X86_XCPT_AC))
6315 { /* likely */ }
6316 else
6317 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6318
6319 /* Exception error-code reserved bits. */
6320 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6321 { /* likely */ }
6322 else
6323 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6324
6325 /* Injecting a software interrupt, software exception or privileged software exception. */
6326 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6327 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6328 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6329 {
6330 /* Instruction length must be in the range 0-15. */
6331 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6332 { /* likely */ }
6333 else
6334 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6335
6336 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6337 if ( pVmcs->u32EntryInstrLen != 0
6338 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6339 { /* likely */ }
6340 else
6341 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6342 }
6343 }
6344 }
6345
6346 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6347 if (pVmcs->u32EntryMsrLoadCount)
6348 {
6349 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6350 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6351 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6352 { /* likely */ }
6353 else
6354 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6355 }
6356
6357 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6358 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6359 }
6360
6361 NOREF(pszInstr);
6362 NOREF(pszFailure);
6363 return VINF_SUCCESS;
6364}
6365
6366
6367/**
6368 * Loads the guest control registers, debug register and some MSRs as part of
6369 * VM-entry.
6370 *
6371 * @param pVCpu The cross context virtual CPU structure.
6372 */
6373IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6374{
6375 /*
6376 * Load guest control registers, debug registers and MSRs.
6377 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6378 */
6379 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6380
6381 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6382 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6383 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6384 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6385 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6386 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6387
6388 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6389 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6390
6391 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6392 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6393 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6394
6395 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6396 {
6397 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6398
6399 /* EFER MSR. */
6400 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6401 {
6402 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6403 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6404 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6405 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6406 if (fGstInLongMode)
6407 {
6408 /* If the nested-guest is in long mode, LMA and LME are both set. */
6409 Assert(fGstPaging);
6410 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6411 }
6412 else
6413 {
6414 /*
6415 * If the nested-guest is outside long mode:
6416 * - With paging: LMA is cleared, LME is cleared.
6417 * - Without paging: LMA is cleared, LME is left unmodified.
6418 */
6419 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6420 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6421 }
6422 }
6423 /* else: see below. */
6424 }
6425
6426 /* PAT MSR. */
6427 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6428 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6429
6430 /* EFER MSR. */
6431 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6432 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6433
6434 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6435 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6436
6437 /* We don't support IA32_BNDCFGS MSR yet. */
6438 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6439
6440 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6441}
6442
6443
6444/**
6445 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6446 *
6447 * @param pVCpu The cross context virtual CPU structure.
6448 */
6449IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6450{
6451 /*
6452 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6453 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6454 */
6455 /* CS, SS, ES, DS, FS, GS. */
6456 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6457 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6458 {
6459 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6460 CPUMSELREG VmcsSelReg;
6461 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6462 AssertRC(rc); NOREF(rc);
6463 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6464 {
6465 pGstSelReg->Sel = VmcsSelReg.Sel;
6466 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6467 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6468 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6469 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6470 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6471 }
6472 else
6473 {
6474 pGstSelReg->Sel = VmcsSelReg.Sel;
6475 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6476 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6477 switch (iSegReg)
6478 {
6479 case X86_SREG_CS:
6480 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6481 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6482 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6483 break;
6484
6485 case X86_SREG_SS:
6486 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6487 pGstSelReg->u32Limit = 0;
6488 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6489 break;
6490
6491 case X86_SREG_ES:
6492 case X86_SREG_DS:
6493 pGstSelReg->u64Base = 0;
6494 pGstSelReg->u32Limit = 0;
6495 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6496 break;
6497
6498 case X86_SREG_FS:
6499 case X86_SREG_GS:
6500 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6501 pGstSelReg->u32Limit = 0;
6502 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6503 break;
6504 }
6505 Assert(pGstSelReg->Attr.n.u1Unusable);
6506 }
6507 }
6508
6509 /* LDTR. */
6510 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6511 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6512 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6513 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6514 {
6515 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6516 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6517 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6518 }
6519 else
6520 {
6521 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6522 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6523 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6524 }
6525
6526 /* TR. */
6527 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6528 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6529 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6530 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6531 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6532 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6533 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6534
6535 /* GDTR. */
6536 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6537 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6538
6539 /* IDTR. */
6540 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6541 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6542}
6543
6544
6545/**
6546 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6547 *
6548 * @returns VBox status code.
6549 * @param pVCpu The cross context virtual CPU structure.
6550 * @param pszInstr The VMX instruction name (for logging purposes).
6551 */
6552IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6553{
6554 /*
6555 * Load guest MSRs.
6556 * See Intel spec. 26.4 "Loading MSRs".
6557 */
6558 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6559 const char *const pszFailure = "VM-exit";
6560
6561 /*
6562 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6563 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6564 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6565 */
6566 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6567 if (!cMsrs)
6568 return VINF_SUCCESS;
6569
6570 /*
6571 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6572 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6573 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6574 */
6575 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6576 if (fIsMsrCountValid)
6577 { /* likely */ }
6578 else
6579 {
6580 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6581 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6582 }
6583
6584 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6585 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6586 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6587 if (RT_SUCCESS(rc))
6588 {
6589 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6590 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6591 {
6592 if ( !pMsr->u32Reserved
6593 && pMsr->u32Msr != MSR_K8_FS_BASE
6594 && pMsr->u32Msr != MSR_K8_GS_BASE
6595 && pMsr->u32Msr != MSR_K6_EFER
6596 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6597 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6598 {
6599 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6600 if (rcStrict == VINF_SUCCESS)
6601 continue;
6602
6603 /*
6604 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6605 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6606 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6607 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6608 * MSR in ring-0 if possible, or come up with a better, generic solution.
6609 */
6610 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6611 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6612 ? kVmxVDiag_Vmentry_MsrLoadRing3
6613 : kVmxVDiag_Vmentry_MsrLoad;
6614 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6615 }
6616 else
6617 {
6618 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6619 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6620 }
6621 }
6622 }
6623 else
6624 {
6625 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6626 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6627 }
6628
6629 NOREF(pszInstr);
6630 NOREF(pszFailure);
6631 return VINF_SUCCESS;
6632}
6633
6634
6635/**
6636 * Loads the guest-state non-register state as part of VM-entry.
6637 *
6638 * @returns VBox status code.
6639 * @param pVCpu The cross context virtual CPU structure.
6640 * @param pszInstr The VMX instruction name (for logging purposes).
6641 *
6642 * @remarks This must be called only after loading the nested-guest register state
6643 * (especially nested-guest RIP).
6644 */
6645IEM_STATIC int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
6646{
6647 /*
6648 * Load guest non-register state.
6649 * See Intel spec. 26.6 "Special Features of VM Entry"
6650 */
6651 const char *const pszFailure = "VM-exit";
6652 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6653
6654 /*
6655 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6656 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6657 *
6658 * See Intel spec. 26.6.1 "Interruptibility State".
6659 */
6660 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6661 if ( !fEntryVectoring
6662 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6663 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6664 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6665 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6666
6667 /* NMI blocking. */
6668 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6669 {
6670 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6671 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6672 else
6673 {
6674 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6675 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6676 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6677 }
6678 }
6679 else
6680 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6681
6682 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6683
6684 /*
6685 * Set PGM's copy of the EPT pointer.
6686 * The EPTP has already been validated while checking guest state.
6687 *
6688 * It is important to do this prior to mapping PAE PDPTEs (below).
6689 */
6690 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6691 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
6692
6693 /*
6694 * Load the guest's PAE PDPTEs.
6695 */
6696 if (iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
6697 {
6698 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6699 {
6700 /*
6701 * With EPT, we've already validated these while checking the guest state.
6702 * Just load them directly from the VMCS here.
6703 */
6704 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6705 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6706 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6707 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6708 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6709 AssertCompile(RT_ELEMENTS(aPaePdptes) == RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes));
6710 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes); i++)
6711 pVCpu->cpum.GstCtx.aPaePdpes[i].u = aPaePdptes[i].u;
6712 }
6713 else
6714 {
6715 /*
6716 * Without EPT, we must load the PAE PDPTEs referenced by CR3.
6717 * This involves loading (and mapping) CR3 and validating them now.
6718 */
6719 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
6720 if (RT_SUCCESS(rc))
6721 { /* likely */ }
6722 else
6723 {
6724 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6725 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6726 }
6727 }
6728 }
6729
6730 /* VPID is irrelevant. We don't support VPID yet. */
6731
6732 /* Clear address-range monitoring. */
6733 EMMonitorWaitClear(pVCpu);
6734
6735 return VINF_SUCCESS;
6736}
6737
6738
6739/**
6740 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
6741 *
6742 * @param pVCpu The cross context virtual CPU structure.
6743 * @param pszInstr The VMX instruction name (for logging purposes).
6744 *
6745 * @remarks This assumes various VMCS related data structure pointers have already
6746 * been verified prior to calling this function.
6747 */
6748IEM_STATIC int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr)
6749{
6750 const char *const pszFailure = "VM-exit";
6751 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6752
6753 /*
6754 * Virtualize APIC accesses.
6755 */
6756 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6757 {
6758 /* APIC-access physical address. */
6759 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6760
6761 /*
6762 * Register the handler for the APIC-access page.
6763 *
6764 * We don't deregister the APIC-access page handler during the VM-exit as a different
6765 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6766 *
6767 * We leave the page registered until the first access that happens outside VMX non-root
6768 * mode. Guest software is allowed to access structures such as the APIC-access page
6769 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6770 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6771 *
6772 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6773 */
6774 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6775 {
6776 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6777 PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
6778 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6779 pVCpu0->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6780 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6781 if (RT_SUCCESS(rc))
6782 { /* likely */ }
6783 else
6784 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6785 }
6786 }
6787
6788 /*
6789 * VMCS shadowing.
6790 */
6791 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6792 {
6793 /* Read the VMREAD-bitmap. */
6794 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6795 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
6796 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
6797 if (RT_SUCCESS(rc))
6798 { /* likely */ }
6799 else
6800 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6801
6802 /* Read the VMWRITE-bitmap. */
6803 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
6804 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
6805 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
6806 if (RT_SUCCESS(rc))
6807 { /* likely */ }
6808 else
6809 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6810 }
6811
6812 /*
6813 * I/O bitmaps.
6814 */
6815 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6816 {
6817 /* Read the IO bitmap A. */
6818 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6819 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
6820 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
6821 if (RT_SUCCESS(rc))
6822 { /* likely */ }
6823 else
6824 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
6825
6826 /* Read the IO bitmap B. */
6827 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6828 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
6829 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
6830 if (RT_SUCCESS(rc))
6831 { /* likely */ }
6832 else
6833 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
6834 }
6835
6836 /*
6837 * TPR shadow and Virtual-APIC page.
6838 */
6839 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6840 {
6841 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6842 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6843 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6844 {
6845 /* Read the VTPR from the virtual-APIC page. */
6846 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6847 uint8_t u8VTpr;
6848 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6849 if (RT_SUCCESS(rc))
6850 { /* likely */ }
6851 else
6852 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6853
6854 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6855 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6856 { /* likely */ }
6857 else
6858 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6859 }
6860 }
6861
6862 /*
6863 * VMCS link pointer.
6864 */
6865 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6866 {
6867 /* Read the VMCS-link pointer from guest memory. */
6868 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6869 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
6870 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
6871 if (RT_SUCCESS(rc))
6872 { /* likely */ }
6873 else
6874 {
6875 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6876 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6877 }
6878
6879 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6880 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6881 { /* likely */ }
6882 else
6883 {
6884 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6885 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6886 }
6887
6888 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6889 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6890 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
6891 { /* likely */ }
6892 else
6893 {
6894 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6895 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6896 }
6897
6898 /* Update our cache of the guest physical address of the shadow VMCS. */
6899 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6900 }
6901
6902 /*
6903 * MSR bitmap.
6904 */
6905 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6906 {
6907 /* Read the MSR bitmap. */
6908 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6909 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
6910 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
6911 if (RT_SUCCESS(rc))
6912 { /* likely */ }
6913 else
6914 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6915 }
6916
6917 NOREF(pszFailure);
6918 NOREF(pszInstr);
6919 return VINF_SUCCESS;
6920}
6921
6922
6923/**
6924 * Loads the guest-state as part of VM-entry.
6925 *
6926 * @returns VBox status code.
6927 * @param pVCpu The cross context virtual CPU structure.
6928 * @param pszInstr The VMX instruction name (for logging purposes).
6929 *
6930 * @remarks This must be done after all the necessary steps prior to loading of
6931 * guest-state (e.g. checking various VMCS state).
6932 */
6933IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6934{
6935 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
6936 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6937
6938 /* Load guest segment registers. */
6939 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6940
6941 /*
6942 * Load guest RIP, RSP and RFLAGS.
6943 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6944 */
6945 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6946 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6947 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6948 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6949
6950 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6951 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6952 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6953
6954 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
6955 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
6956 if (rc == VINF_SUCCESS)
6957 { /* likely */ }
6958 else
6959 return rc;
6960
6961 /* Load VMX related structures and state referenced by the VMCS. */
6962 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
6963 if (rc == VINF_SUCCESS)
6964 { /* likely */ }
6965 else
6966 return rc;
6967
6968 NOREF(pszInstr);
6969 return VINF_SUCCESS;
6970}
6971
6972
6973/**
6974 * Returns whether there are is a pending debug exception on VM-entry.
6975 *
6976 * @param pVCpu The cross context virtual CPU structure.
6977 * @param pszInstr The VMX instruction name (for logging purposes).
6978 */
6979IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6980{
6981 /*
6982 * Pending debug exceptions.
6983 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
6984 */
6985 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6986 Assert(pVmcs);
6987
6988 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
6989 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
6990 if (fPendingDbgXcpt)
6991 {
6992 uint8_t uEntryIntInfoType;
6993 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
6994 if (fEntryVectoring)
6995 {
6996 switch (uEntryIntInfoType)
6997 {
6998 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
6999 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7000 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7001 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7002 fPendingDbgXcpt = false;
7003 break;
7004
7005 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7006 {
7007 /*
7008 * Whether the pending debug exception for software exceptions other than
7009 * #BP and #OF is delivered after injecting the exception or is discard
7010 * is CPU implementation specific. We will discard them (easier).
7011 */
7012 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7013 if ( uVector != X86_XCPT_BP
7014 && uVector != X86_XCPT_OF)
7015 fPendingDbgXcpt = false;
7016 RT_FALL_THRU();
7017 }
7018 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7019 {
7020 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7021 fPendingDbgXcpt = false;
7022 break;
7023 }
7024 }
7025 }
7026 else
7027 {
7028 /*
7029 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7030 * pending debug exception is held pending or is discarded is CPU implementation
7031 * specific. We will discard them (easier).
7032 */
7033 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7034 fPendingDbgXcpt = false;
7035
7036 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7037 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7038 fPendingDbgXcpt = false;
7039 }
7040 }
7041
7042 NOREF(pszInstr);
7043 return fPendingDbgXcpt;
7044}
7045
7046
7047/**
7048 * Set up the monitor-trap flag (MTF).
7049 *
7050 * @param pVCpu The cross context virtual CPU structure.
7051 * @param pszInstr The VMX instruction name (for logging purposes).
7052 */
7053IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
7054{
7055 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7056 Assert(pVmcs);
7057 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7058 {
7059 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7060 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7061 }
7062 else
7063 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7064 NOREF(pszInstr);
7065}
7066
7067
7068/**
7069 * Sets up NMI-window exiting.
7070 *
7071 * @param pVCpu The cross context virtual CPU structure.
7072 * @param pszInstr The VMX instruction name (for logging purposes).
7073 */
7074IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
7075{
7076 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7077 Assert(pVmcs);
7078 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7079 {
7080 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7081 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7082 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7083 }
7084 else
7085 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7086 NOREF(pszInstr);
7087}
7088
7089
7090/**
7091 * Sets up interrupt-window exiting.
7092 *
7093 * @param pVCpu The cross context virtual CPU structure.
7094 * @param pszInstr The VMX instruction name (for logging purposes).
7095 */
7096IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
7097{
7098 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7099 Assert(pVmcs);
7100 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7101 {
7102 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7103 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7104 }
7105 else
7106 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7107 NOREF(pszInstr);
7108}
7109
7110
7111/**
7112 * Set up the VMX-preemption timer.
7113 *
7114 * @param pVCpu The cross context virtual CPU structure.
7115 * @param pszInstr The VMX instruction name (for logging purposes).
7116 */
7117IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
7118{
7119 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7120 Assert(pVmcs);
7121 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7122 {
7123 /*
7124 * If the timer is 0, we must cause a VM-exit before executing the first
7125 * nested-guest instruction. So we can flag as though the timer has already
7126 * expired and we will check and cause a VM-exit at the right priority elsewhere
7127 * in the code.
7128 */
7129 uint64_t uEntryTick;
7130 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7131 if (uPreemptTimer)
7132 {
7133 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7134 AssertRC(rc);
7135 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7136 }
7137 else
7138 {
7139 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7140 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7141 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7142 }
7143
7144 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7145 }
7146 else
7147 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7148
7149 NOREF(pszInstr);
7150}
7151
7152
7153/**
7154 * Injects an event using TRPM given a VM-entry interruption info. and related
7155 * fields.
7156 *
7157 * @param pVCpu The cross context virtual CPU structure.
7158 * @param pszInstr The VMX instruction name (for logging purposes).
7159 * @param uEntryIntInfo The VM-entry interruption info.
7160 * @param uErrCode The error code associated with the event if any.
7161 * @param cbInstr The VM-entry instruction length (for software
7162 * interrupts and software exceptions). Pass 0
7163 * otherwise.
7164 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7165 */
7166IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7167 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7168{
7169 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7170
7171 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7172 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7173 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7174
7175 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7176
7177 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7178 AssertRC(rc);
7179 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7180
7181 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7182 {
7183 TRPMSetErrorCode(pVCpu, uErrCode);
7184 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7185 }
7186
7187 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7188 {
7189 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7190 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7191 }
7192 else
7193 {
7194 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7195 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7196 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7197 {
7198 TRPMSetInstrLength(pVCpu, cbInstr);
7199 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7200 }
7201 }
7202
7203 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7204 {
7205 TRPMSetTrapDueToIcebp(pVCpu);
7206 Log(("%s: Injecting: icebp\n", pszInstr));
7207 }
7208
7209 NOREF(pszInstr);
7210}
7211
7212
7213/**
7214 * Performs event injection (if any) as part of VM-entry.
7215 *
7216 * @param pVCpu The cross context virtual CPU structure.
7217 * @param pszInstr The VMX instruction name (for logging purposes).
7218 */
7219IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7220{
7221 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7222
7223 /*
7224 * Inject events.
7225 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7226 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7227 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7228 * the actually delivery of this event.
7229 *
7230 * See Intel spec. 26.5 "Event Injection".
7231 */
7232 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7233 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7234
7235 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7236 if (fEntryIntInfoValid)
7237 {
7238 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7239 {
7240 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7241 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7242 }
7243 else
7244 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7245 pVCpu->cpum.GstCtx.cr2);
7246
7247 /*
7248 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7249 *
7250 * However, we do it here on VM-entry as well because while it isn't visible to guest
7251 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7252 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7253 *
7254 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7255 */
7256 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7257 }
7258 else
7259 {
7260 /*
7261 * Inject any pending guest debug exception.
7262 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7263 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7264 */
7265 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7266 if (fPendingDbgXcpt)
7267 {
7268 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7269 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7270 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7271 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7272 0 /* GCPtrFaultAddress */);
7273 }
7274 }
7275
7276 NOREF(pszInstr);
7277}
7278
7279
7280/**
7281 * Initializes all read-only VMCS fields as part of VM-entry.
7282 *
7283 * @param pVCpu The cross context virtual CPU structure.
7284 */
7285IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7286{
7287 /*
7288 * Any VMCS field which we do not establish on every VM-exit but may potentially
7289 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7290 * specified to be undefined, needs to be initialized here.
7291 *
7292 * Thus, it is especially important to clear the Exit qualification field
7293 * since it must be zero for VM-exits where it is not used. Similarly, the
7294 * VM-exit interruption information field's valid bit needs to be cleared for
7295 * the same reasons.
7296 */
7297 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7298 Assert(pVmcs);
7299
7300 /* 16-bit (none currently). */
7301 /* 32-bit. */
7302 pVmcs->u32RoVmInstrError = 0;
7303 pVmcs->u32RoExitReason = 0;
7304 pVmcs->u32RoExitIntInfo = 0;
7305 pVmcs->u32RoExitIntErrCode = 0;
7306 pVmcs->u32RoIdtVectoringInfo = 0;
7307 pVmcs->u32RoIdtVectoringErrCode = 0;
7308 pVmcs->u32RoExitInstrLen = 0;
7309 pVmcs->u32RoExitInstrInfo = 0;
7310
7311 /* 64-bit. */
7312 pVmcs->u64RoGuestPhysAddr.u = 0;
7313
7314 /* Natural-width. */
7315 pVmcs->u64RoExitQual.u = 0;
7316 pVmcs->u64RoIoRcx.u = 0;
7317 pVmcs->u64RoIoRsi.u = 0;
7318 pVmcs->u64RoIoRdi.u = 0;
7319 pVmcs->u64RoIoRip.u = 0;
7320 pVmcs->u64RoGuestLinearAddr.u = 0;
7321}
7322
7323
7324/**
7325 * VMLAUNCH/VMRESUME instruction execution worker.
7326 *
7327 * @returns Strict VBox status code.
7328 * @param pVCpu The cross context virtual CPU structure.
7329 * @param cbInstr The instruction length in bytes.
7330 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7331 * VMXINSTRID_VMRESUME).
7332 *
7333 * @remarks Common VMX instruction checks are already expected to by the caller,
7334 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7335 */
7336IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7337{
7338# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7339 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7340 return VINF_EM_RAW_EMULATE_INSTR;
7341# else
7342 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7343 || uInstrId == VMXINSTRID_VMRESUME);
7344 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7345
7346 /* Nested-guest intercept. */
7347 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7348 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7349
7350 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7351
7352 /*
7353 * Basic VM-entry checks.
7354 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7355 * The checks following that do not have to follow a specific order.
7356 *
7357 * See Intel spec. 26.1 "Basic VM-entry Checks".
7358 */
7359
7360 /* CPL. */
7361 if (pVCpu->iem.s.uCpl == 0)
7362 { /* likely */ }
7363 else
7364 {
7365 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7366 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7367 return iemRaiseGeneralProtectionFault0(pVCpu);
7368 }
7369
7370 /* Current VMCS valid. */
7371 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7372 { /* likely */ }
7373 else
7374 {
7375 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7376 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7377 iemVmxVmFailInvalid(pVCpu);
7378 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7379 return VINF_SUCCESS;
7380 }
7381
7382 /* Current VMCS is not a shadow VMCS. */
7383 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7384 { /* likely */ }
7385 else
7386 {
7387 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7388 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7389 iemVmxVmFailInvalid(pVCpu);
7390 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7391 return VINF_SUCCESS;
7392 }
7393
7394 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7395 * use block-by-STI here which is not quite correct. */
7396 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7397 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7398 { /* likely */ }
7399 else
7400 {
7401 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7402 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7403 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7404 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7405 return VINF_SUCCESS;
7406 }
7407
7408 if (uInstrId == VMXINSTRID_VMLAUNCH)
7409 {
7410 /* VMLAUNCH with non-clear VMCS. */
7411 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7412 { /* likely */ }
7413 else
7414 {
7415 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7416 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7417 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7418 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7419 return VINF_SUCCESS;
7420 }
7421 }
7422 else
7423 {
7424 /* VMRESUME with non-launched VMCS. */
7425 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7426 { /* likely */ }
7427 else
7428 {
7429 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7430 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7431 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7432 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7433 return VINF_SUCCESS;
7434 }
7435 }
7436
7437 /*
7438 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7439 * while entering VMX non-root mode. We do some of this while checking VM-execution
7440 * controls. The nested hypervisor should not make assumptions and cannot expect
7441 * predictable behavior if changes to these structures are made in guest memory while
7442 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7443 * modify them anyway as we cache them in host memory.
7444 *
7445 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7446 */
7447 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7448 Assert(pVmcs);
7449 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7450
7451 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7452 if (RT_SUCCESS(rc))
7453 {
7454 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7455 if (RT_SUCCESS(rc))
7456 {
7457 /*
7458 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7459 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7460 * ones that may occur during VM-entry below).
7461 */
7462 iemVmxVmentryInitReadOnlyFields(pVCpu);
7463
7464 /*
7465 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7466 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7467 * VM-exit when required.
7468 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7469 */
7470 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7471
7472 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7473 if (RT_SUCCESS(rc))
7474 {
7475 /*
7476 * We've now entered nested-guest execution.
7477 *
7478 * It is important do this prior to loading the guest state because
7479 * as part of loading the guest state, PGM (and perhaps other components
7480 * in the future) relies on detecting whether VMX non-root mode has been
7481 * entered.
7482 */
7483 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7484
7485 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7486 if (RT_SUCCESS(rc))
7487 {
7488 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7489 if (RT_SUCCESS(rc))
7490 {
7491 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7492
7493 /* VMLAUNCH instruction must update the VMCS launch state. */
7494 if (uInstrId == VMXINSTRID_VMLAUNCH)
7495 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7496
7497 /* Perform the VMX transition (PGM updates). */
7498 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7499 if (rcStrict == VINF_SUCCESS)
7500 { /* likely */ }
7501 else if (RT_SUCCESS(rcStrict))
7502 {
7503 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7504 VBOXSTRICTRC_VAL(rcStrict)));
7505 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7506 }
7507 else
7508 {
7509 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7510 return rcStrict;
7511 }
7512
7513 /* Paranoia. */
7514 Assert(rcStrict == VINF_SUCCESS);
7515
7516 /*
7517 * The priority of potential VM-exits during VM-entry is important.
7518 * The priorities of VM-exits and events are listed from highest
7519 * to lowest as follows:
7520 *
7521 * 1. Event injection.
7522 * 2. Trap on task-switch (T flag set in TSS).
7523 * 3. TPR below threshold / APIC-write.
7524 * 4. SMI, INIT.
7525 * 5. MTF exit.
7526 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7527 * 7. VMX-preemption timer.
7528 * 9. NMI-window exit.
7529 * 10. NMI injection.
7530 * 11. Interrupt-window exit.
7531 * 12. Virtual-interrupt injection.
7532 * 13. Interrupt injection.
7533 * 14. Process next instruction (fetch, decode, execute).
7534 */
7535
7536 /* Setup VMX-preemption timer. */
7537 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7538
7539 /* Setup monitor-trap flag. */
7540 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7541
7542 /* Setup NMI-window exiting. */
7543 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7544
7545 /* Setup interrupt-window exiting. */
7546 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7547
7548 /*
7549 * Inject any event that the nested hypervisor wants to inject.
7550 * Note! We cannot immediately perform the event injection here as we may have
7551 * pending PGM operations to perform due to switching page tables and/or
7552 * mode.
7553 */
7554 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7555
7556# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7557 /* Reschedule to IEM-only execution of the nested-guest. */
7558 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7559 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7560 if (rcSched != VINF_SUCCESS)
7561 iemSetPassUpStatus(pVCpu, rcSched);
7562# endif
7563
7564 /* Finally, done. */
7565 Log3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",
7566 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7567 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7568 pVCpu->cpum.GstCtx.msrEFER));
7569 return VINF_SUCCESS;
7570 }
7571 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED,
7572 pVmcs->u64RoExitQual.u);
7573 }
7574 }
7575 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED,
7576 pVmcs->u64RoExitQual.u);
7577 }
7578
7579 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7580 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7581 return VINF_SUCCESS;
7582 }
7583
7584 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7585 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7586 return VINF_SUCCESS;
7587# endif
7588}
7589
7590
7591/**
7592 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7593 * (causes a VM-exit) or not.
7594 *
7595 * @returns @c true if the instruction is intercepted, @c false otherwise.
7596 * @param pVCpu The cross context virtual CPU structure.
7597 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7598 * VMX_EXIT_WRMSR).
7599 * @param idMsr The MSR.
7600 */
7601IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7602{
7603 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7604 Assert( uExitReason == VMX_EXIT_RDMSR
7605 || uExitReason == VMX_EXIT_WRMSR);
7606
7607 /* Consult the MSR bitmap if the feature is supported. */
7608 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7609 Assert(pVmcs);
7610 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7611 {
7612 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7613 if (uExitReason == VMX_EXIT_RDMSR)
7614 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7615 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7616 }
7617
7618 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7619 return true;
7620}
7621
7622
7623/**
7624 * VMREAD instruction execution worker that does not perform any validation checks.
7625 *
7626 * Callers are expected to have performed the necessary checks and to ensure the
7627 * VMREAD will succeed.
7628 *
7629 * @param pVmcs Pointer to the virtual VMCS.
7630 * @param pu64Dst Where to write the VMCS value.
7631 * @param u64VmcsField The VMCS field.
7632 *
7633 * @remarks May be called with interrupts disabled.
7634 */
7635IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7636{
7637 VMXVMCSFIELD VmcsField;
7638 VmcsField.u = u64VmcsField;
7639 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7640 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7641 uint8_t const uWidthType = (uWidth << 2) | uType;
7642 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7643 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7644 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7645 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
7646 uWidth, uType, uIndex, uIndex));
7647 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7648
7649 /*
7650 * Read the VMCS component based on the field's effective width.
7651 *
7652 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7653 * indicates high bits (little endian).
7654 *
7655 * Note! The caller is responsible to trim the result and update registers
7656 * or memory locations are required. Here we just zero-extend to the largest
7657 * type (i.e. 64-bits).
7658 */
7659 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7660 uint8_t const *pbField = pbVmcs + offField;
7661 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7662 switch (uEffWidth)
7663 {
7664 case VMX_VMCSFIELD_WIDTH_64BIT:
7665 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7666 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7667 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7668 }
7669}
7670
7671
7672/**
7673 * VMREAD common (memory/register) instruction execution worker.
7674 *
7675 * @returns Strict VBox status code.
7676 * @param pVCpu The cross context virtual CPU structure.
7677 * @param cbInstr The instruction length in bytes.
7678 * @param pu64Dst Where to write the VMCS value (only updated when
7679 * VINF_SUCCESS is returned).
7680 * @param u64VmcsField The VMCS field.
7681 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7682 * NULL.
7683 */
7684IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7685 PCVMXVEXITINFO pExitInfo)
7686{
7687 /* Nested-guest intercept. */
7688 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7689 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7690 {
7691 if (pExitInfo)
7692 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7693 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7694 }
7695
7696 /* CPL. */
7697 if (pVCpu->iem.s.uCpl == 0)
7698 { /* likely */ }
7699 else
7700 {
7701 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7702 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7703 return iemRaiseGeneralProtectionFault0(pVCpu);
7704 }
7705
7706 /* VMCS pointer in root mode. */
7707 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7708 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7709 { /* likely */ }
7710 else
7711 {
7712 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7713 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7714 iemVmxVmFailInvalid(pVCpu);
7715 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7716 return VINF_SUCCESS;
7717 }
7718
7719 /* VMCS-link pointer in non-root mode. */
7720 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7721 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7722 { /* likely */ }
7723 else
7724 {
7725 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7726 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7727 iemVmxVmFailInvalid(pVCpu);
7728 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7729 return VINF_SUCCESS;
7730 }
7731
7732 /* Supported VMCS field. */
7733 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7734 { /* likely */ }
7735 else
7736 {
7737 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7738 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7739 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7740 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7741 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7742 return VINF_SUCCESS;
7743 }
7744
7745 /*
7746 * Reading from the current or shadow VMCS.
7747 */
7748 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7749 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7750 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7751 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7752 return VINF_SUCCESS;
7753}
7754
7755
7756/**
7757 * VMREAD (64-bit register) instruction execution worker.
7758 *
7759 * @returns Strict VBox status code.
7760 * @param pVCpu The cross context virtual CPU structure.
7761 * @param cbInstr The instruction length in bytes.
7762 * @param pu64Dst Where to store the VMCS field's value.
7763 * @param u64VmcsField The VMCS field.
7764 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7765 * NULL.
7766 */
7767IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7768 PCVMXVEXITINFO pExitInfo)
7769{
7770 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7771 if (rcStrict == VINF_SUCCESS)
7772 {
7773 iemVmxVmreadSuccess(pVCpu, cbInstr);
7774 return VINF_SUCCESS;
7775 }
7776
7777 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7778 return rcStrict;
7779}
7780
7781
7782/**
7783 * VMREAD (32-bit register) instruction execution worker.
7784 *
7785 * @returns Strict VBox status code.
7786 * @param pVCpu The cross context virtual CPU structure.
7787 * @param cbInstr The instruction length in bytes.
7788 * @param pu32Dst Where to store the VMCS field's value.
7789 * @param u32VmcsField The VMCS field.
7790 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7791 * NULL.
7792 */
7793IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7794 PCVMXVEXITINFO pExitInfo)
7795{
7796 uint64_t u64Dst;
7797 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7798 if (rcStrict == VINF_SUCCESS)
7799 {
7800 *pu32Dst = u64Dst;
7801 iemVmxVmreadSuccess(pVCpu, cbInstr);
7802 return VINF_SUCCESS;
7803 }
7804
7805 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7806 return rcStrict;
7807}
7808
7809
7810/**
7811 * VMREAD (memory) instruction execution worker.
7812 *
7813 * @returns Strict VBox status code.
7814 * @param pVCpu The cross context virtual CPU structure.
7815 * @param cbInstr The instruction length in bytes.
7816 * @param iEffSeg The effective segment register to use with @a u64Val.
7817 * Pass UINT8_MAX if it is a register access.
7818 * @param GCPtrDst The guest linear address to store the VMCS field's
7819 * value.
7820 * @param u64VmcsField The VMCS field.
7821 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7822 * NULL.
7823 */
7824IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7825 PCVMXVEXITINFO pExitInfo)
7826{
7827 uint64_t u64Dst;
7828 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7829 if (rcStrict == VINF_SUCCESS)
7830 {
7831 /*
7832 * Write the VMCS field's value to the location specified in guest-memory.
7833 */
7834 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7835 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7836 else
7837 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7838 if (rcStrict == VINF_SUCCESS)
7839 {
7840 iemVmxVmreadSuccess(pVCpu, cbInstr);
7841 return VINF_SUCCESS;
7842 }
7843
7844 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7845 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7846 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7847 return rcStrict;
7848 }
7849
7850 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7851 return rcStrict;
7852}
7853
7854
7855/**
7856 * VMWRITE instruction execution worker that does not perform any validation
7857 * checks.
7858 *
7859 * Callers are expected to have performed the necessary checks and to ensure the
7860 * VMWRITE will succeed.
7861 *
7862 * @param pVmcs Pointer to the virtual VMCS.
7863 * @param u64Val The value to write.
7864 * @param u64VmcsField The VMCS field.
7865 *
7866 * @remarks May be called with interrupts disabled.
7867 */
7868IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7869{
7870 VMXVMCSFIELD VmcsField;
7871 VmcsField.u = u64VmcsField;
7872 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7873 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7874 uint8_t const uWidthType = (uWidth << 2) | uType;
7875 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7876 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7877 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7878 Assert(offField < VMX_V_VMCS_SIZE);
7879 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7880
7881 /*
7882 * Write the VMCS component based on the field's effective width.
7883 *
7884 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7885 * indicates high bits (little endian).
7886 */
7887 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7888 uint8_t *pbField = pbVmcs + offField;
7889 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7890 switch (uEffWidth)
7891 {
7892 case VMX_VMCSFIELD_WIDTH_64BIT:
7893 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7894 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7895 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7896 }
7897}
7898
7899
7900/**
7901 * VMWRITE instruction execution worker.
7902 *
7903 * @returns Strict VBox status code.
7904 * @param pVCpu The cross context virtual CPU structure.
7905 * @param cbInstr The instruction length in bytes.
7906 * @param iEffSeg The effective segment register to use with @a u64Val.
7907 * Pass UINT8_MAX if it is a register access.
7908 * @param u64Val The value to write (or guest linear address to the
7909 * value), @a iEffSeg will indicate if it's a memory
7910 * operand.
7911 * @param u64VmcsField The VMCS field.
7912 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7913 * NULL.
7914 */
7915IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7916 PCVMXVEXITINFO pExitInfo)
7917{
7918 /* Nested-guest intercept. */
7919 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7920 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7921 {
7922 if (pExitInfo)
7923 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7924 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7925 }
7926
7927 /* CPL. */
7928 if (pVCpu->iem.s.uCpl == 0)
7929 { /* likely */ }
7930 else
7931 {
7932 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7933 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7934 return iemRaiseGeneralProtectionFault0(pVCpu);
7935 }
7936
7937 /* VMCS pointer in root mode. */
7938 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7939 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7940 { /* likely */ }
7941 else
7942 {
7943 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7944 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7945 iemVmxVmFailInvalid(pVCpu);
7946 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7947 return VINF_SUCCESS;
7948 }
7949
7950 /* VMCS-link pointer in non-root mode. */
7951 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7952 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7953 { /* likely */ }
7954 else
7955 {
7956 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7957 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7958 iemVmxVmFailInvalid(pVCpu);
7959 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7960 return VINF_SUCCESS;
7961 }
7962
7963 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7964 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7965 if (!fIsRegOperand)
7966 {
7967 /* Read the value from the specified guest memory location. */
7968 VBOXSTRICTRC rcStrict;
7969 RTGCPTR const GCPtrVal = u64Val;
7970 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7971 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7972 else
7973 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7974 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7975 {
7976 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7977 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7978 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7979 return rcStrict;
7980 }
7981 }
7982 else
7983 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
7984
7985 /* Supported VMCS field. */
7986 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7987 { /* likely */ }
7988 else
7989 {
7990 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7991 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
7992 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7993 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
7994 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7995 return VINF_SUCCESS;
7996 }
7997
7998 /* Read-only VMCS field. */
7999 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8000 if ( !fIsFieldReadOnly
8001 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8002 { /* likely */ }
8003 else
8004 {
8005 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8006 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8007 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8008 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8009 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8010 return VINF_SUCCESS;
8011 }
8012
8013 /*
8014 * Write to the current or shadow VMCS.
8015 */
8016 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8017 PVMXVVMCS pVmcs = !fInVmxNonRootMode
8018 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8019 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8020 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8021
8022 /* Notify HM that the VMCS content might have changed. */
8023 if (!fInVmxNonRootMode)
8024 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8025
8026 iemVmxVmSucceed(pVCpu);
8027 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8028 return VINF_SUCCESS;
8029}
8030
8031
8032/**
8033 * VMCLEAR instruction execution worker.
8034 *
8035 * @returns Strict VBox status code.
8036 * @param pVCpu The cross context virtual CPU structure.
8037 * @param cbInstr The instruction length in bytes.
8038 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8039 * @param GCPtrVmcs The linear address of the VMCS pointer.
8040 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8041 *
8042 * @remarks Common VMX instruction checks are already expected to by the caller,
8043 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8044 */
8045IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8046 PCVMXVEXITINFO pExitInfo)
8047{
8048 /* Nested-guest intercept. */
8049 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8050 {
8051 if (pExitInfo)
8052 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8053 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8054 }
8055
8056 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8057
8058 /* CPL. */
8059 if (pVCpu->iem.s.uCpl == 0)
8060 { /* likely */ }
8061 else
8062 {
8063 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8064 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8065 return iemRaiseGeneralProtectionFault0(pVCpu);
8066 }
8067
8068 /* Get the VMCS pointer from the location specified by the source memory operand. */
8069 RTGCPHYS GCPhysVmcs;
8070 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8071 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8072 { /* likely */ }
8073 else
8074 {
8075 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8076 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8077 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8078 return rcStrict;
8079 }
8080
8081 /* VMCS pointer alignment. */
8082 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8083 { /* likely */ }
8084 else
8085 {
8086 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8087 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8088 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8089 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8090 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8091 return VINF_SUCCESS;
8092 }
8093
8094 /* VMCS physical-address width limits. */
8095 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8096 { /* likely */ }
8097 else
8098 {
8099 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8100 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8101 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8102 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8103 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8104 return VINF_SUCCESS;
8105 }
8106
8107 /* VMCS is not the VMXON region. */
8108 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8109 { /* likely */ }
8110 else
8111 {
8112 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8113 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8114 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8115 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8116 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8117 return VINF_SUCCESS;
8118 }
8119
8120 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8121 restriction imposed by our implementation. */
8122 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8123 { /* likely */ }
8124 else
8125 {
8126 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8127 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8128 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8129 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8130 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8131 return VINF_SUCCESS;
8132 }
8133
8134 /*
8135 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8136 *
8137 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8138 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8139 * to 'clear'.
8140 */
8141 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8142 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8143 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8144 {
8145 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8146 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8147 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8148 }
8149 else
8150 {
8151 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8152 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8153 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8154 if (RT_FAILURE(rcStrict))
8155 return rcStrict;
8156 }
8157
8158 iemVmxVmSucceed(pVCpu);
8159 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8160 return VINF_SUCCESS;
8161}
8162
8163
8164/**
8165 * VMPTRST instruction execution worker.
8166 *
8167 * @returns Strict VBox status code.
8168 * @param pVCpu The cross context virtual CPU structure.
8169 * @param cbInstr The instruction length in bytes.
8170 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8171 * @param GCPtrVmcs The linear address of where to store the current VMCS
8172 * pointer.
8173 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8174 *
8175 * @remarks Common VMX instruction checks are already expected to by the caller,
8176 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8177 */
8178IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8179 PCVMXVEXITINFO pExitInfo)
8180{
8181 /* Nested-guest intercept. */
8182 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8183 {
8184 if (pExitInfo)
8185 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8186 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8187 }
8188
8189 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8190
8191 /* CPL. */
8192 if (pVCpu->iem.s.uCpl == 0)
8193 { /* likely */ }
8194 else
8195 {
8196 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8197 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8198 return iemRaiseGeneralProtectionFault0(pVCpu);
8199 }
8200
8201 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8202 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8203 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8204 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8205 {
8206 iemVmxVmSucceed(pVCpu);
8207 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8208 return rcStrict;
8209 }
8210
8211 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8212 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8213 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8214 return rcStrict;
8215}
8216
8217
8218/**
8219 * VMPTRLD instruction execution worker.
8220 *
8221 * @returns Strict VBox status code.
8222 * @param pVCpu The cross context virtual CPU structure.
8223 * @param cbInstr The instruction length in bytes.
8224 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8225 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8226 *
8227 * @remarks Common VMX instruction checks are already expected to by the caller,
8228 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8229 */
8230IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8231 PCVMXVEXITINFO pExitInfo)
8232{
8233 /* Nested-guest intercept. */
8234 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8235 {
8236 if (pExitInfo)
8237 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8238 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8239 }
8240
8241 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8242
8243 /* CPL. */
8244 if (pVCpu->iem.s.uCpl == 0)
8245 { /* likely */ }
8246 else
8247 {
8248 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8249 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8250 return iemRaiseGeneralProtectionFault0(pVCpu);
8251 }
8252
8253 /* Get the VMCS pointer from the location specified by the source memory operand. */
8254 RTGCPHYS GCPhysVmcs;
8255 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8256 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8257 { /* likely */ }
8258 else
8259 {
8260 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8261 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8262 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8263 return rcStrict;
8264 }
8265
8266 /* VMCS pointer alignment. */
8267 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8268 { /* likely */ }
8269 else
8270 {
8271 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8272 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8273 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8274 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8275 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8276 return VINF_SUCCESS;
8277 }
8278
8279 /* VMCS physical-address width limits. */
8280 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8281 { /* likely */ }
8282 else
8283 {
8284 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8285 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8286 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8287 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8288 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8289 return VINF_SUCCESS;
8290 }
8291
8292 /* VMCS is not the VMXON region. */
8293 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8294 { /* likely */ }
8295 else
8296 {
8297 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8298 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8299 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8300 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8301 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8302 return VINF_SUCCESS;
8303 }
8304
8305 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8306 restriction imposed by our implementation. */
8307 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8308 { /* likely */ }
8309 else
8310 {
8311 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8312 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8313 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8314 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8315 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8316 return VINF_SUCCESS;
8317 }
8318
8319 /* Read just the VMCS revision from the VMCS. */
8320 VMXVMCSREVID VmcsRevId;
8321 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8322 if (RT_SUCCESS(rc))
8323 { /* likely */ }
8324 else
8325 {
8326 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8327 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8328 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8329 return rc;
8330 }
8331
8332 /*
8333 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8334 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8335 */
8336 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8337 && ( !VmcsRevId.n.fIsShadowVmcs
8338 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8339 { /* likely */ }
8340 else
8341 {
8342 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8343 {
8344 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8345 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8346 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8347 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8348 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8349 return VINF_SUCCESS;
8350 }
8351
8352 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8353 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8354 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8355 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8356 return VINF_SUCCESS;
8357 }
8358
8359 /*
8360 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8361 * the cache of an existing, current VMCS back to guest memory before loading a new,
8362 * different current VMCS.
8363 */
8364 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8365 {
8366 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8367 {
8368 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8369 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8370 }
8371
8372 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8373 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8374 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8375 if (RT_SUCCESS(rc))
8376 {
8377 /* Notify HM that a new, current VMCS is loaded. */
8378 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8379 }
8380 else
8381 {
8382 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8383 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8384 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8385 return rc;
8386 }
8387 }
8388
8389 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8390 iemVmxVmSucceed(pVCpu);
8391 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8392 return VINF_SUCCESS;
8393}
8394
8395
8396/**
8397 * INVVPID instruction execution worker.
8398 *
8399 * @returns Strict VBox status code.
8400 * @param pVCpu The cross context virtual CPU structure.
8401 * @param cbInstr The instruction length in bytes.
8402 * @param iEffSeg The segment of the invvpid descriptor.
8403 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8404 * @param u64InvvpidType The invalidation type.
8405 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8406 * NULL.
8407 *
8408 * @remarks Common VMX instruction checks are already expected to by the caller,
8409 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8410 */
8411IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8412 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8413{
8414 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8415 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8416 return iemRaiseUndefinedOpcode(pVCpu);
8417
8418 /* Nested-guest intercept. */
8419 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8420 {
8421 if (pExitInfo)
8422 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8423 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8424 }
8425
8426 /* CPL. */
8427 if (pVCpu->iem.s.uCpl != 0)
8428 {
8429 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8430 return iemRaiseGeneralProtectionFault0(pVCpu);
8431 }
8432
8433 /*
8434 * Validate INVVPID invalidation type.
8435 *
8436 * The instruction specifies exactly ONE of the supported invalidation types.
8437 *
8438 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8439 * supported. In theory, it's possible for a CPU to not support flushing individual
8440 * addresses but all the other types or any other combination. We do not take any
8441 * shortcuts here by assuming the types we currently expose to the guest.
8442 */
8443 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8444 uint8_t const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8445 uint8_t const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8446 uint8_t const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8447 uint8_t const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8448 if ( (fTypeIndivAddr && u64InvvpidType == VMXTLBFLUSHVPID_INDIV_ADDR)
8449 || (fTypeSingleCtx && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
8450 || (fTypeAllCtx && u64InvvpidType == VMXTLBFLUSHVPID_ALL_CONTEXTS)
8451 || (fTypeSingleCtxRetainGlobals && u64InvvpidType == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS))
8452 { /* likely */ }
8453 else
8454 {
8455 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8456 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8457 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8458 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8459 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8460 return VINF_SUCCESS;
8461 }
8462
8463 /*
8464 * Fetch the invvpid descriptor from guest memory.
8465 */
8466 RTUINT128U uDesc;
8467 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8468 if (rcStrict == VINF_SUCCESS)
8469 {
8470 /*
8471 * Validate the descriptor.
8472 */
8473 if (uDesc.s.Lo > 0xfff)
8474 {
8475 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8476 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8477 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8478 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8479 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8480 return VINF_SUCCESS;
8481 }
8482
8483 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8484 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8485 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8486 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8487 switch (u64InvvpidType)
8488 {
8489 case VMXTLBFLUSHVPID_INDIV_ADDR:
8490 {
8491 if (uVpid != 0)
8492 {
8493 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8494 {
8495 /* Invalidate mappings for the linear address tagged with VPID. */
8496 /** @todo PGM support for VPID? Currently just flush everything. */
8497 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8498 iemVmxVmSucceed(pVCpu);
8499 }
8500 else
8501 {
8502 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8503 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8504 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8505 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8506 }
8507 }
8508 else
8509 {
8510 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8511 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8512 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8513 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8514 }
8515 break;
8516 }
8517
8518 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8519 {
8520 if (uVpid != 0)
8521 {
8522 /* Invalidate all mappings with VPID. */
8523 /** @todo PGM support for VPID? Currently just flush everything. */
8524 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8525 iemVmxVmSucceed(pVCpu);
8526 }
8527 else
8528 {
8529 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8530 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8531 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8532 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8533 }
8534 break;
8535 }
8536
8537 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8538 {
8539 /* Invalidate all mappings with non-zero VPIDs. */
8540 /** @todo PGM support for VPID? Currently just flush everything. */
8541 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8542 iemVmxVmSucceed(pVCpu);
8543 break;
8544 }
8545
8546 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8547 {
8548 if (uVpid != 0)
8549 {
8550 /* Invalidate all mappings with VPID except global translations. */
8551 /** @todo PGM support for VPID? Currently just flush everything. */
8552 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8553 iemVmxVmSucceed(pVCpu);
8554 }
8555 else
8556 {
8557 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8558 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8559 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8560 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8561 }
8562 break;
8563 }
8564 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8565 }
8566 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8567 }
8568 return rcStrict;
8569}
8570
8571
8572/**
8573 * VMXON instruction execution worker.
8574 *
8575 * @returns Strict VBox status code.
8576 * @param pVCpu The cross context virtual CPU structure.
8577 * @param cbInstr The instruction length in bytes.
8578 * @param iEffSeg The effective segment register to use with @a
8579 * GCPtrVmxon.
8580 * @param GCPtrVmxon The linear address of the VMXON pointer.
8581 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8582 *
8583 * @remarks Common VMX instruction checks are already expected to by the caller,
8584 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8585 */
8586IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8587 PCVMXVEXITINFO pExitInfo)
8588{
8589 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8590 {
8591 /* CPL. */
8592 if (pVCpu->iem.s.uCpl == 0)
8593 { /* likely */ }
8594 else
8595 {
8596 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8597 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8598 return iemRaiseGeneralProtectionFault0(pVCpu);
8599 }
8600
8601 /* A20M (A20 Masked) mode. */
8602 if (PGMPhysIsA20Enabled(pVCpu))
8603 { /* likely */ }
8604 else
8605 {
8606 Log(("vmxon: A20M mode -> #GP(0)\n"));
8607 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8608 return iemRaiseGeneralProtectionFault0(pVCpu);
8609 }
8610
8611 /* CR0. */
8612 {
8613 /* CR0 MB1 bits. */
8614 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8615 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8616 { /* likely */ }
8617 else
8618 {
8619 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8620 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8621 return iemRaiseGeneralProtectionFault0(pVCpu);
8622 }
8623
8624 /* CR0 MBZ bits. */
8625 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8626 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8627 { /* likely */ }
8628 else
8629 {
8630 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8631 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8632 return iemRaiseGeneralProtectionFault0(pVCpu);
8633 }
8634 }
8635
8636 /* CR4. */
8637 {
8638 /* CR4 MB1 bits. */
8639 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8640 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8641 { /* likely */ }
8642 else
8643 {
8644 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8645 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8646 return iemRaiseGeneralProtectionFault0(pVCpu);
8647 }
8648
8649 /* CR4 MBZ bits. */
8650 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8651 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8652 { /* likely */ }
8653 else
8654 {
8655 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8656 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8657 return iemRaiseGeneralProtectionFault0(pVCpu);
8658 }
8659 }
8660
8661 /* Feature control MSR's LOCK and VMXON bits. */
8662 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
8663 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8664 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8665 { /* likely */ }
8666 else
8667 {
8668 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8669 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8670 return iemRaiseGeneralProtectionFault0(pVCpu);
8671 }
8672
8673 /* Get the VMXON pointer from the location specified by the source memory operand. */
8674 RTGCPHYS GCPhysVmxon;
8675 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8676 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8677 { /* likely */ }
8678 else
8679 {
8680 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8681 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8682 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8683 return rcStrict;
8684 }
8685
8686 /* VMXON region pointer alignment. */
8687 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8688 { /* likely */ }
8689 else
8690 {
8691 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8692 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8693 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8694 iemVmxVmFailInvalid(pVCpu);
8695 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8696 return VINF_SUCCESS;
8697 }
8698
8699 /* VMXON physical-address width limits. */
8700 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8701 { /* likely */ }
8702 else
8703 {
8704 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8705 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8706 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8707 iemVmxVmFailInvalid(pVCpu);
8708 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8709 return VINF_SUCCESS;
8710 }
8711
8712 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8713 restriction imposed by our implementation. */
8714 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8715 { /* likely */ }
8716 else
8717 {
8718 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8719 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8720 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8721 iemVmxVmFailInvalid(pVCpu);
8722 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8723 return VINF_SUCCESS;
8724 }
8725
8726 /* Read the VMCS revision ID from the VMXON region. */
8727 VMXVMCSREVID VmcsRevId;
8728 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8729 if (RT_SUCCESS(rc))
8730 { /* likely */ }
8731 else
8732 {
8733 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8734 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8735 return rc;
8736 }
8737
8738 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8739 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8740 { /* likely */ }
8741 else
8742 {
8743 /* Revision ID mismatch. */
8744 if (!VmcsRevId.n.fIsShadowVmcs)
8745 {
8746 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8747 VmcsRevId.n.u31RevisionId));
8748 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8749 iemVmxVmFailInvalid(pVCpu);
8750 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8751 return VINF_SUCCESS;
8752 }
8753
8754 /* Shadow VMCS disallowed. */
8755 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8756 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8757 iemVmxVmFailInvalid(pVCpu);
8758 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8759 return VINF_SUCCESS;
8760 }
8761
8762 /*
8763 * Record that we're in VMX operation, block INIT, block and disable A20M.
8764 */
8765 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8766 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8767 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8768
8769 /* Clear address-range monitoring. */
8770 EMMonitorWaitClear(pVCpu);
8771 /** @todo NSTVMX: Intel PT. */
8772
8773 iemVmxVmSucceed(pVCpu);
8774 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8775 return VINF_SUCCESS;
8776 }
8777 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8778 {
8779 /* Nested-guest intercept. */
8780 if (pExitInfo)
8781 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8782 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8783 }
8784
8785 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8786
8787 /* CPL. */
8788 if (pVCpu->iem.s.uCpl > 0)
8789 {
8790 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8791 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8792 return iemRaiseGeneralProtectionFault0(pVCpu);
8793 }
8794
8795 /* VMXON when already in VMX root mode. */
8796 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8797 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8798 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8799 return VINF_SUCCESS;
8800}
8801
8802
8803/**
8804 * Implements 'VMXOFF'.
8805 *
8806 * @remarks Common VMX instruction checks are already expected to by the caller,
8807 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8808 */
8809IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8810{
8811 /* Nested-guest intercept. */
8812 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8813 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8814
8815 /* CPL. */
8816 if (pVCpu->iem.s.uCpl == 0)
8817 { /* likely */ }
8818 else
8819 {
8820 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8821 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8822 return iemRaiseGeneralProtectionFault0(pVCpu);
8823 }
8824
8825 /* Dual monitor treatment of SMIs and SMM. */
8826 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8827 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8828 { /* likely */ }
8829 else
8830 {
8831 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8832 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8833 return VINF_SUCCESS;
8834 }
8835
8836 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8837 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8838 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8839
8840 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8841 { /** @todo NSTVMX: Unblock SMI. */ }
8842
8843 EMMonitorWaitClear(pVCpu);
8844 /** @todo NSTVMX: Unblock and enable A20M. */
8845
8846 iemVmxVmSucceed(pVCpu);
8847 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8848 return VINF_SUCCESS;
8849}
8850
8851
8852/**
8853 * Implements 'VMXON'.
8854 */
8855IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8856{
8857 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8858}
8859
8860
8861/**
8862 * Implements 'VMLAUNCH'.
8863 */
8864IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8865{
8866 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8867}
8868
8869
8870/**
8871 * Implements 'VMRESUME'.
8872 */
8873IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8874{
8875 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8876}
8877
8878
8879/**
8880 * Implements 'VMPTRLD'.
8881 */
8882IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8883{
8884 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8885}
8886
8887
8888/**
8889 * Implements 'VMPTRST'.
8890 */
8891IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8892{
8893 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8894}
8895
8896
8897/**
8898 * Implements 'VMCLEAR'.
8899 */
8900IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8901{
8902 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8903}
8904
8905
8906/**
8907 * Implements 'VMWRITE' register.
8908 */
8909IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
8910{
8911 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
8912}
8913
8914
8915/**
8916 * Implements 'VMWRITE' memory.
8917 */
8918IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
8919{
8920 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
8921}
8922
8923
8924/**
8925 * Implements 'VMREAD' register (64-bit).
8926 */
8927IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
8928{
8929 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
8930}
8931
8932
8933/**
8934 * Implements 'VMREAD' register (32-bit).
8935 */
8936IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
8937{
8938 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
8939}
8940
8941
8942/**
8943 * Implements 'VMREAD' memory, 64-bit register.
8944 */
8945IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
8946{
8947 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
8948}
8949
8950
8951/**
8952 * Implements 'VMREAD' memory, 32-bit register.
8953 */
8954IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
8955{
8956 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
8957}
8958
8959
8960/**
8961 * Implements 'INVVPID'.
8962 */
8963IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
8964{
8965 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
8966}
8967
8968
8969/**
8970 * Implements VMX's implementation of PAUSE.
8971 */
8972IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8973{
8974 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8975 {
8976 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8977 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8978 return rcStrict;
8979 }
8980
8981 /*
8982 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8983 * a VM-exit, the instruction operates normally.
8984 */
8985 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8986 return VINF_SUCCESS;
8987}
8988
8989#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8990
8991
8992/**
8993 * Implements 'VMCALL'.
8994 */
8995IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8996{
8997#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8998 /* Nested-guest intercept. */
8999 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9000 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9001#endif
9002
9003 /* Join forces with vmmcall. */
9004 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9005}
9006
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