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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 93115

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1/* $Id: IEMAllCImplVmxInstr.cpp.h 93115 2022-01-01 11:31:46Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason and logs. */
156# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 } while (0)
163
164/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
165# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
166 do \
167 { \
168 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
169 return VERR_VMX_VMEXIT_FAILED; \
170 } while (0)
171
172
173/*********************************************************************************************************************************
174* Global Variables *
175*********************************************************************************************************************************/
176/** @todo NSTVMX: The following VM-exit intercepts are pending:
177 * VMX_EXIT_IO_SMI
178 * VMX_EXIT_SMI
179 * VMX_EXIT_GETSEC
180 * VMX_EXIT_RSM
181 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
182 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
183 * VMX_EXIT_INVEPT
184 * VMX_EXIT_RDRAND
185 * VMX_EXIT_VMFUNC
186 * VMX_EXIT_ENCLS
187 * VMX_EXIT_RDSEED
188 * VMX_EXIT_PML_FULL
189 * VMX_EXIT_XSAVES
190 * VMX_EXIT_XRSTORS
191 */
192/**
193 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
194 *
195 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
196 * second dimension is the Index, see VMXVMCSFIELD.
197 */
198uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
199{
200 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
201 {
202 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
203 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
204 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
205 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
206 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
207 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 27 */ UINT16_MAX,
209 },
210 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
211 {
212 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
213 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
214 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
215 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
216 },
217 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
218 {
219 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
220 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
221 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
222 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
223 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
224 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
225 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
226 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
227 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
228 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
229 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
230 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
231 /* 26-27 */ UINT16_MAX, UINT16_MAX
232 },
233 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
234 {
235 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
236 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
237 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
238 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
239 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
240 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
241 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
242 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
243 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
244 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
245 },
246 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
247 {
248 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
249 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
250 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
251 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
252 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
253 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
254 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
255 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
256 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
257 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
258 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
259 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
260 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
261 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
262 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
263 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
264 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
265 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
266 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
267 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
268 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
269 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
270 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
271 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
272 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
273 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
274 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
275 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
276 },
277 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
280 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
281 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
282 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
283 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
284 },
285 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
286 {
287 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
288 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
289 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
290 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
291 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
292 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
293 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
294 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
295 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
296 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
297 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
298 /* 11 */ UINT16_MAX,
299 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
300 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
301 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
302 },
303 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
304 {
305 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
306 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
307 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
308 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
309 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
310 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
311 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
312 },
313 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
314 {
315 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
316 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
317 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
318 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
319 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
320 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
321 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
322 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
323 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
324 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
325 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
326 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
327 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
328 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
329 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
330 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
331 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
332 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
333 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
334 /* 26-27 */ UINT16_MAX, UINT16_MAX
335 },
336 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
337 {
338 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
339 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
340 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
341 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
342 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
343 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
344 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
345 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
346 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
347 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
348 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
349 },
350 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
351 {
352 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
353 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
354 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
355 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
356 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
357 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
358 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
359 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
360 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
361 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
362 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
363 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
364 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
365 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
366 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
367 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
368 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
369 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
370 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
371 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
372 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
373 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
374 /* 22 */ UINT16_MAX,
375 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
376 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
377 },
378 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
379 {
380 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
381 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
382 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
383 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
385 },
386 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
387 {
388 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
389 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
390 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
391 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
392 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
393 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
394 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
395 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
396 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
398 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
399 },
400 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
401 {
402 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
403 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
404 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
405 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
406 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
407 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
408 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
409 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
410 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
411 },
412 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
413 {
414 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
415 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
416 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
417 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
418 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
419 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
420 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
421 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
422 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
423 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
424 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
425 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
426 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
427 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
428 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
429 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
430 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
431 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
432 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
433 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
434 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
435 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
436 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
437 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
438 },
439 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
440 {
441 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
442 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
443 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
444 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
445 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
446 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
447 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
448 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
449 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
450 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
451 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
452 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
453 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
454 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
455 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
456 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
457 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
458 }
459};
460
461
462/**
463 * Gets a host selector from the VMCS.
464 *
465 * @param pVmcs Pointer to the virtual VMCS.
466 * @param iSelReg The index of the segment register (X86_SREG_XXX).
467 */
468DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
469{
470 Assert(iSegReg < X86_SREG_COUNT);
471 RTSEL HostSel;
472 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
473 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
474 uint8_t const uWidthType = (uWidth << 2) | uType;
475 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
476 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
477 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
478 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
479 uint8_t const *pbField = pbVmcs + offField;
480 HostSel = *(uint16_t *)pbField;
481 return HostSel;
482}
483
484
485/**
486 * Sets a guest segment register in the VMCS.
487 *
488 * @param pVmcs Pointer to the virtual VMCS.
489 * @param iSegReg The index of the segment register (X86_SREG_XXX).
490 * @param pSelReg Pointer to the segment register.
491 */
492IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
493{
494 Assert(pSelReg);
495 Assert(iSegReg < X86_SREG_COUNT);
496
497 /* Selector. */
498 {
499 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
500 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
501 uint8_t const uWidthType = (uWidth << 2) | uType;
502 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
503 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
504 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
505 uint8_t *pbVmcs = (uint8_t *)pVmcs;
506 uint8_t *pbField = pbVmcs + offField;
507 *(uint16_t *)pbField = pSelReg->Sel;
508 }
509
510 /* Limit. */
511 {
512 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
513 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
514 uint8_t const uWidthType = (uWidth << 2) | uType;
515 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
516 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
517 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
518 uint8_t *pbVmcs = (uint8_t *)pVmcs;
519 uint8_t *pbField = pbVmcs + offField;
520 *(uint32_t *)pbField = pSelReg->u32Limit;
521 }
522
523 /* Base. */
524 {
525 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
526 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
527 uint8_t const uWidthType = (uWidth << 2) | uType;
528 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
529 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
530 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
531 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
532 uint8_t const *pbField = pbVmcs + offField;
533 *(uint64_t *)pbField = pSelReg->u64Base;
534 }
535
536 /* Attributes. */
537 {
538 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
539 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
540 | X86DESCATTR_UNUSABLE;
541 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
542 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
543 uint8_t const uWidthType = (uWidth << 2) | uType;
544 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
545 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
546 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
547 uint8_t *pbVmcs = (uint8_t *)pVmcs;
548 uint8_t *pbField = pbVmcs + offField;
549 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
550 }
551}
552
553
554/**
555 * Gets a guest segment register from the VMCS.
556 *
557 * @returns VBox status code.
558 * @param pVmcs Pointer to the virtual VMCS.
559 * @param iSegReg The index of the segment register (X86_SREG_XXX).
560 * @param pSelReg Where to store the segment register (only updated when
561 * VINF_SUCCESS is returned).
562 *
563 * @remarks Warning! This does not validate the contents of the retrieved segment
564 * register.
565 */
566IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
567{
568 Assert(pSelReg);
569 Assert(iSegReg < X86_SREG_COUNT);
570
571 /* Selector. */
572 uint16_t u16Sel;
573 {
574 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
575 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
576 uint8_t const uWidthType = (uWidth << 2) | uType;
577 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
578 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
579 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
580 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
581 uint8_t const *pbField = pbVmcs + offField;
582 u16Sel = *(uint16_t *)pbField;
583 }
584
585 /* Limit. */
586 uint32_t u32Limit;
587 {
588 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
589 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
590 uint8_t const uWidthType = (uWidth << 2) | uType;
591 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
592 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
593 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
594 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
595 uint8_t const *pbField = pbVmcs + offField;
596 u32Limit = *(uint32_t *)pbField;
597 }
598
599 /* Base. */
600 uint64_t u64Base;
601 {
602 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
603 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
604 uint8_t const uWidthType = (uWidth << 2) | uType;
605 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
606 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
607 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
608 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
609 uint8_t const *pbField = pbVmcs + offField;
610 u64Base = *(uint64_t *)pbField;
611 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
612 }
613
614 /* Attributes. */
615 uint32_t u32Attr;
616 {
617 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
618 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
619 uint8_t const uWidthType = (uWidth << 2) | uType;
620 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
621 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
622 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
623 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
624 uint8_t const *pbField = pbVmcs + offField;
625 u32Attr = *(uint32_t *)pbField;
626 }
627
628 pSelReg->Sel = u16Sel;
629 pSelReg->ValidSel = u16Sel;
630 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
631 pSelReg->u32Limit = u32Limit;
632 pSelReg->u64Base = u64Base;
633 pSelReg->Attr.u = u32Attr;
634 return VINF_SUCCESS;
635}
636
637
638/**
639 * Converts an IEM exception event type to a VMX event type.
640 *
641 * @returns The VMX event type.
642 * @param uVector The interrupt / exception vector.
643 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
644 */
645DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
646{
647 /* Paranoia (callers may use these interchangeably). */
648 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
649 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
650 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
651 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
652 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
653 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
654 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
655 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
656 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
657 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
658 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
659 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
660
661 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
662 {
663 if (uVector == X86_XCPT_NMI)
664 return VMX_EXIT_INT_INFO_TYPE_NMI;
665 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
666 }
667
668 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
669 {
670 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
671 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
672 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
673 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
674 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
675 }
676
677 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
678 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
679}
680
681
682/**
683 * Determines whether the guest is using PAE paging given the VMCS.
684 *
685 * @returns @c true if PAE paging mode is used, @c false otherwise.
686 * @param pVmcs Pointer to the virtual VMCS.
687 */
688DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
689{
690 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
691 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
692 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
693}
694
695
696/**
697 * Sets the Exit qualification VMCS field.
698 *
699 * @param pVCpu The cross context virtual CPU structure.
700 * @param u64ExitQual The Exit qualification.
701 */
702DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
703{
704 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
705}
706
707
708/**
709 * Sets the VM-exit interruption information field.
710 *
711 * @param pVCpu The cross context virtual CPU structure.
712 * @param uExitIntInfo The VM-exit interruption information.
713 */
714DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
715{
716 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
717}
718
719
720/**
721 * Sets the VM-exit interruption error code.
722 *
723 * @param pVCpu The cross context virtual CPU structure.
724 * @param uErrCode The error code.
725 */
726DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
727{
728 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
729}
730
731
732/**
733 * Sets the IDT-vectoring information field.
734 *
735 * @param pVCpu The cross context virtual CPU structure.
736 * @param uIdtVectorInfo The IDT-vectoring information.
737 */
738DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
739{
740 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
741}
742
743
744/**
745 * Sets the IDT-vectoring error code field.
746 *
747 * @param pVCpu The cross context virtual CPU structure.
748 * @param uErrCode The error code.
749 */
750DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
751{
752 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
753}
754
755
756/**
757 * Sets the VM-exit guest-linear address VMCS field.
758 *
759 * @param pVCpu The cross context virtual CPU structure.
760 * @param uGuestLinearAddr The VM-exit guest-linear address.
761 */
762DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
763{
764 /* Bits 63:32 of guest-linear address MBZ if the guest isn't in long mode prior to the VM-exit. */
765 Assert(CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)) || !(uGuestLinearAddr & UINT64_C(0xffffffff00000000)));
766 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
767}
768
769
770/**
771 * Sets the VM-exit guest-physical address VMCS field.
772 *
773 * @param pVCpu The cross context virtual CPU structure.
774 * @param uGuestPhysAddr The VM-exit guest-physical address.
775 */
776DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
777{
778 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
779}
780
781
782/**
783 * Sets the VM-exit instruction length VMCS field.
784 *
785 * @param pVCpu The cross context virtual CPU structure.
786 * @param cbInstr The VM-exit instruction length in bytes.
787 *
788 * @remarks Callers may clear this field to 0. Hence, this function does not check
789 * the validity of the instruction length.
790 */
791DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
792{
793 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
794}
795
796
797/**
798 * Sets the VM-exit instruction info. VMCS field.
799 *
800 * @param pVCpu The cross context virtual CPU structure.
801 * @param uExitInstrInfo The VM-exit instruction information.
802 */
803DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
804{
805 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
806}
807
808
809/**
810 * Sets the guest pending-debug exceptions field.
811 *
812 * @param pVCpu The cross context virtual CPU structure.
813 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
814 */
815DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
816{
817 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
818 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
819}
820
821
822/**
823 * Implements VMSucceed for VMX instruction success.
824 *
825 * @param pVCpu The cross context virtual CPU structure.
826 */
827DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
828{
829 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
830}
831
832
833/**
834 * Implements VMFailInvalid for VMX instruction failure.
835 *
836 * @param pVCpu The cross context virtual CPU structure.
837 */
838DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
839{
840 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
841}
842
843
844/**
845 * Implements VMFail for VMX instruction failure.
846 *
847 * @param pVCpu The cross context virtual CPU structure.
848 * @param enmInsErr The VM instruction error.
849 */
850DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
851{
852 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
853}
854
855
856/**
857 * Checks if the given auto-load/store MSR area count is valid for the
858 * implementation.
859 *
860 * @returns @c true if it's within the valid limit, @c false otherwise.
861 * @param pVCpu The cross context virtual CPU structure.
862 * @param uMsrCount The MSR area count to check.
863 */
864DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
865{
866 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
867 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
868 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
869 if (uMsrCount <= cMaxSupportedMsrs)
870 return true;
871 return false;
872}
873
874
875/**
876 * Flushes the current VMCS contents back to guest memory.
877 *
878 * @returns VBox status code.
879 * @param pVCpu The cross context virtual CPU structure.
880 */
881DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
882{
883 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
884 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
885 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
886 return rc;
887}
888
889
890/**
891 * Populates the current VMCS contents from guest memory.
892 *
893 * @returns VBox status code.
894 * @param pVCpu The cross context virtual CPU structure.
895 */
896DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
897{
898 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
899 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
900 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
901 return rc;
902}
903
904
905/**
906 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
907 *
908 * @param pVCpu The cross context virtual CPU structure.
909 */
910DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
911{
912 iemVmxVmSucceed(pVCpu);
913 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
914}
915
916
917/**
918 * Gets the instruction diagnostic for segment base checks during VM-entry of a
919 * nested-guest.
920 *
921 * @param iSegReg The segment index (X86_SREG_XXX).
922 */
923IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
924{
925 switch (iSegReg)
926 {
927 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
928 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
929 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
930 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
931 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
932 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
933 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
934 }
935}
936
937
938/**
939 * Gets the instruction diagnostic for segment base checks during VM-entry of a
940 * nested-guest that is in Virtual-8086 mode.
941 *
942 * @param iSegReg The segment index (X86_SREG_XXX).
943 */
944IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
945{
946 switch (iSegReg)
947 {
948 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
949 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
950 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
951 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
952 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
953 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
954 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
955 }
956}
957
958
959/**
960 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
961 * nested-guest that is in Virtual-8086 mode.
962 *
963 * @param iSegReg The segment index (X86_SREG_XXX).
964 */
965IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
966{
967 switch (iSegReg)
968 {
969 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
970 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
971 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
972 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
973 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
974 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
975 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
976 }
977}
978
979
980/**
981 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
982 * nested-guest that is in Virtual-8086 mode.
983 *
984 * @param iSegReg The segment index (X86_SREG_XXX).
985 */
986IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
987{
988 switch (iSegReg)
989 {
990 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
991 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
992 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
993 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
994 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
995 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
996 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
997 }
998}
999
1000
1001/**
1002 * Gets the instruction diagnostic for segment attributes reserved bits failure
1003 * during VM-entry of a nested-guest.
1004 *
1005 * @param iSegReg The segment index (X86_SREG_XXX).
1006 */
1007IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1008{
1009 switch (iSegReg)
1010 {
1011 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1012 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1013 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1014 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1015 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1016 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1017 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1018 }
1019}
1020
1021
1022/**
1023 * Gets the instruction diagnostic for segment attributes descriptor-type
1024 * (code/segment or system) failure during VM-entry of a nested-guest.
1025 *
1026 * @param iSegReg The segment index (X86_SREG_XXX).
1027 */
1028IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1029{
1030 switch (iSegReg)
1031 {
1032 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1033 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1034 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1035 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1036 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1037 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1038 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1039 }
1040}
1041
1042
1043/**
1044 * Gets the instruction diagnostic for segment attributes descriptor-type
1045 * (code/segment or system) failure during VM-entry of a nested-guest.
1046 *
1047 * @param iSegReg The segment index (X86_SREG_XXX).
1048 */
1049IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1050{
1051 switch (iSegReg)
1052 {
1053 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1054 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1055 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1056 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1057 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1058 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1059 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1060 }
1061}
1062
1063
1064/**
1065 * Gets the instruction diagnostic for segment attribute granularity failure during
1066 * VM-entry of a nested-guest.
1067 *
1068 * @param iSegReg The segment index (X86_SREG_XXX).
1069 */
1070IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1071{
1072 switch (iSegReg)
1073 {
1074 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1075 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1076 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1077 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1078 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1079 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1080 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1081 }
1082}
1083
1084/**
1085 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1086 * VM-entry of a nested-guest.
1087 *
1088 * @param iSegReg The segment index (X86_SREG_XXX).
1089 */
1090IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1091{
1092 switch (iSegReg)
1093 {
1094 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1095 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1096 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1097 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1098 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1099 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1100 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1101 }
1102}
1103
1104
1105/**
1106 * Gets the instruction diagnostic for segment attribute type accessed failure
1107 * during VM-entry of a nested-guest.
1108 *
1109 * @param iSegReg The segment index (X86_SREG_XXX).
1110 */
1111IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1112{
1113 switch (iSegReg)
1114 {
1115 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1116 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1117 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1118 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1119 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1120 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1121 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1122 }
1123}
1124
1125
1126/**
1127 * Saves the guest control registers, debug registers and some MSRs are part of
1128 * VM-exit.
1129 *
1130 * @param pVCpu The cross context virtual CPU structure.
1131 */
1132IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1133{
1134 /*
1135 * Saves the guest control registers, debug registers and some MSRs.
1136 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1137 */
1138 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1139
1140 /* Save control registers. */
1141 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1142 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1143 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1144
1145 /* Save SYSENTER CS, ESP, EIP. */
1146 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1147 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1148 {
1149 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1150 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1151 }
1152 else
1153 {
1154 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1155 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1156 }
1157
1158 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1159 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1160 {
1161 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1162 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1163 }
1164
1165 /* Save PAT MSR. */
1166 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1167 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1168
1169 /* Save EFER MSR. */
1170 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1171 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1172
1173 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1174 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1175
1176 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1177}
1178
1179
1180/**
1181 * Saves the guest force-flags in preparation of entering the nested-guest.
1182 *
1183 * @param pVCpu The cross context virtual CPU structure.
1184 */
1185IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1186{
1187 /* We shouldn't be called multiple times during VM-entry. */
1188 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1189
1190 /* MTF should not be set outside VMX non-root mode. */
1191 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1192
1193 /*
1194 * Preserve the required force-flags.
1195 *
1196 * We cache and clear force-flags that would affect the execution of the
1197 * nested-guest. Cached flags are then restored while returning to the guest
1198 * if necessary.
1199 *
1200 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1201 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1202 * instruction. Interrupt inhibition for any nested-guest instruction
1203 * is supplied by the guest-interruptibility state VMCS field and will
1204 * be set up as part of loading the guest state.
1205 *
1206 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1207 * successful VM-entry (due to invalid guest-state) need to continue
1208 * blocking NMIs if it was in effect before VM-entry.
1209 *
1210 * - MTF need not be preserved as it's used only in VMX non-root mode and
1211 * is supplied through the VM-execution controls.
1212 *
1213 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1214 * we will be able to generate interrupts that may cause VM-exits for
1215 * the nested-guest.
1216 */
1217 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1218}
1219
1220
1221/**
1222 * Restores the guest force-flags in preparation of exiting the nested-guest.
1223 *
1224 * @param pVCpu The cross context virtual CPU structure.
1225 */
1226IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1227{
1228 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1229 {
1230 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1231 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1232 }
1233}
1234
1235
1236/**
1237 * Performs the VMX transition to/from VMX non-root mode.
1238 *
1239 * @param pVCpu The cross context virtual CPU structure.
1240*/
1241IEM_STATIC int iemVmxTransition(PVMCPUCC pVCpu)
1242{
1243 /*
1244 * Inform PGM about paging mode changes.
1245 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1246 * see comment in iemMemPageTranslateAndCheckAccess().
1247 */
1248 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1249 true /* fForce */);
1250 AssertRCReturn(rc, rc);
1251
1252 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1253 IEMTlbInvalidateAll(pVCpu, false /*fVmm*/);
1254
1255 /* Inform CPUM (recompiler), can later be removed. */
1256 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1257
1258 /* Re-initialize IEM cache/state after the drastic mode switch. */
1259 iemReInitExec(pVCpu);
1260 return rc;
1261}
1262
1263
1264/**
1265 * Calculates the current VMX-preemption timer value.
1266 *
1267 * @returns The current VMX-preemption timer value.
1268 * @param pVCpu The cross context virtual CPU structure.
1269 */
1270IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1271{
1272 /*
1273 * Assume the following:
1274 * PreemptTimerShift = 5
1275 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1276 * EntryTick = 50000 (TSC at time of VM-entry)
1277 *
1278 * CurTick Delta PreemptTimerVal
1279 * ----------------------------------
1280 * 60000 10000 2
1281 * 80000 30000 1
1282 * 90000 40000 0 -> VM-exit.
1283 *
1284 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1285 * The saved VMX-preemption timer value is calculated as follows:
1286 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1287 * E.g.:
1288 * Delta = 10000
1289 * Tmp = 10000 / (2 * 10000) = 0.5
1290 * NewPt = 2 - 0.5 = 2
1291 * Delta = 30000
1292 * Tmp = 30000 / (2 * 10000) = 1.5
1293 * NewPt = 2 - 1.5 = 1
1294 * Delta = 40000
1295 * Tmp = 40000 / 20000 = 2
1296 * NewPt = 2 - 2 = 0
1297 */
1298 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1299 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1300 if (uVmcsPreemptVal > 0)
1301 {
1302 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1303 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1304 uint64_t const uDelta = uCurTick - uEntryTick;
1305 uint32_t const uPreemptTimer = uVmcsPreemptVal
1306 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1307 return uPreemptTimer;
1308 }
1309 return 0;
1310}
1311
1312
1313/**
1314 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1315 *
1316 * @param pVCpu The cross context virtual CPU structure.
1317 */
1318IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1319{
1320 /*
1321 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1322 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1323 */
1324 /* CS, SS, ES, DS, FS, GS. */
1325 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1326 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1327 {
1328 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1329 if (!pSelReg->Attr.n.u1Unusable)
1330 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1331 else
1332 {
1333 /*
1334 * For unusable segments the attributes are undefined except for CS and SS.
1335 * For the rest we don't bother preserving anything but the unusable bit.
1336 */
1337 switch (iSegReg)
1338 {
1339 case X86_SREG_CS:
1340 pVmcs->GuestCs = pSelReg->Sel;
1341 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1342 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1343 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1344 | X86DESCATTR_UNUSABLE);
1345 break;
1346
1347 case X86_SREG_SS:
1348 pVmcs->GuestSs = pSelReg->Sel;
1349 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1350 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1351 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1352 break;
1353
1354 case X86_SREG_DS:
1355 pVmcs->GuestDs = pSelReg->Sel;
1356 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1357 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1358 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1359 break;
1360
1361 case X86_SREG_ES:
1362 pVmcs->GuestEs = pSelReg->Sel;
1363 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1364 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1365 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1366 break;
1367
1368 case X86_SREG_FS:
1369 pVmcs->GuestFs = pSelReg->Sel;
1370 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1371 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1372 break;
1373
1374 case X86_SREG_GS:
1375 pVmcs->GuestGs = pSelReg->Sel;
1376 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1377 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1378 break;
1379 }
1380 }
1381 }
1382
1383 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1384 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1385 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1386 | X86DESCATTR_UNUSABLE;
1387 /* LDTR. */
1388 {
1389 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1390 pVmcs->GuestLdtr = pSelReg->Sel;
1391 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1392 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1393 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1394 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1395 }
1396
1397 /* TR. */
1398 {
1399 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1400 pVmcs->GuestTr = pSelReg->Sel;
1401 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1402 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1403 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1404 }
1405
1406 /* GDTR. */
1407 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1408 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1409
1410 /* IDTR. */
1411 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1412 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1413}
1414
1415
1416/**
1417 * Saves guest non-register state as part of VM-exit.
1418 *
1419 * @param pVCpu The cross context virtual CPU structure.
1420 * @param uExitReason The VM-exit reason.
1421 */
1422IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1423{
1424 /*
1425 * Save guest non-register state.
1426 * See Intel spec. 27.3.4 "Saving Non-Register State".
1427 */
1428 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1429
1430 /*
1431 * Activity state.
1432 * Most VM-exits will occur in the active state. However, if the first instruction
1433 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1434 * the VM-exit will be from the HLT activity state.
1435 *
1436 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1437 */
1438 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1439 * not? */
1440 EMSTATE const enmActivityState = EMGetState(pVCpu);
1441 switch (enmActivityState)
1442 {
1443 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1444 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1445 }
1446
1447 /*
1448 * Interruptibility-state.
1449 */
1450 /* NMI. */
1451 pVmcs->u32GuestIntrState = 0;
1452 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1453 {
1454 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1455 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1456 }
1457 else
1458 {
1459 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1460 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1461 }
1462
1463 /* Blocking-by-STI. */
1464 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1465 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1466 {
1467 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1468 * currently. */
1469 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1470 }
1471 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1472
1473 /*
1474 * Pending debug exceptions.
1475 *
1476 * For VM-exits where it is not applicable, we can safely zero out the field.
1477 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1478 */
1479 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1480 && uExitReason != VMX_EXIT_SMI
1481 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1482 && !VMXIsVmexitTrapLike(uExitReason))
1483 {
1484 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1485 * block-by-MovSS is in effect. */
1486 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1487 }
1488
1489 /*
1490 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1491 *
1492 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1493 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1494 */
1495 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1496 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1497 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1498
1499 /*
1500 * PAE PDPTEs.
1501 *
1502 * If EPT is enabled and PAE paging was used at the time of the VM-exit,
1503 * the PDPTEs are saved from the VMCS. Otherwise they're undefined but
1504 * we zero them for consistency.
1505 */
1506 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1507 {
1508 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
1509 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1510 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
1511 {
1512 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1513 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1514 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1515 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1516 }
1517 else
1518 {
1519 pVmcs->u64GuestPdpte0.u = 0;
1520 pVmcs->u64GuestPdpte1.u = 0;
1521 pVmcs->u64GuestPdpte2.u = 0;
1522 pVmcs->u64GuestPdpte3.u = 0;
1523 }
1524
1525 /* Clear PGM's copy of the EPT pointer for added safety. */
1526 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1527 }
1528 else
1529 {
1530 pVmcs->u64GuestPdpte0.u = 0;
1531 pVmcs->u64GuestPdpte1.u = 0;
1532 pVmcs->u64GuestPdpte2.u = 0;
1533 pVmcs->u64GuestPdpte3.u = 0;
1534 }
1535}
1536
1537
1538/**
1539 * Saves the guest-state as part of VM-exit.
1540 *
1541 * @returns VBox status code.
1542 * @param pVCpu The cross context virtual CPU structure.
1543 * @param uExitReason The VM-exit reason.
1544 */
1545IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1546{
1547 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1548 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1549
1550 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1551 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1552 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1553
1554 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1555}
1556
1557
1558/**
1559 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1560 *
1561 * @returns VBox status code.
1562 * @param pVCpu The cross context virtual CPU structure.
1563 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1564 */
1565IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1566{
1567 /*
1568 * Save guest MSRs.
1569 * See Intel spec. 27.4 "Saving MSRs".
1570 */
1571 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1572 const char * const pszFailure = "VMX-abort";
1573
1574 /*
1575 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1576 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1577 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1578 */
1579 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1580 if (!cMsrs)
1581 return VINF_SUCCESS;
1582
1583 /*
1584 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1585 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1586 * implementation causes a VMX-abort followed by a triple-fault.
1587 */
1588 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1589 if (fIsMsrCountValid)
1590 { /* likely */ }
1591 else
1592 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1593
1594 /*
1595 * Optimization if the nested hypervisor is using the same guest-physical page for both
1596 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1597 */
1598 PVMXAUTOMSR pMsrArea;
1599 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1600 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1601 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1602 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1603 else
1604 {
1605 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1606 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1607 if (RT_SUCCESS(rc))
1608 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1609 else
1610 {
1611 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1612 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1613 }
1614 }
1615
1616 /*
1617 * Update VM-exit MSR store area.
1618 */
1619 PVMXAUTOMSR pMsr = pMsrArea;
1620 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1621 {
1622 if ( !pMsr->u32Reserved
1623 && pMsr->u32Msr != MSR_IA32_SMBASE
1624 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1625 {
1626 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1627 if (rcStrict == VINF_SUCCESS)
1628 continue;
1629
1630 /*
1631 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1632 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1633 * recording the MSR index in the auxiliary info. field and indicated further by our
1634 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1635 * if possible, or come up with a better, generic solution.
1636 */
1637 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1638 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1639 ? kVmxVDiag_Vmexit_MsrStoreRing3
1640 : kVmxVDiag_Vmexit_MsrStore;
1641 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1642 }
1643 else
1644 {
1645 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1646 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1647 }
1648 }
1649
1650 /*
1651 * Commit the VM-exit MSR store are to guest memory.
1652 */
1653 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1654 if (RT_SUCCESS(rc))
1655 return VINF_SUCCESS;
1656
1657 NOREF(uExitReason);
1658 NOREF(pszFailure);
1659
1660 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1661 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1662}
1663
1664
1665/**
1666 * Performs a VMX abort (due to an fatal error during VM-exit).
1667 *
1668 * @returns Strict VBox status code.
1669 * @param pVCpu The cross context virtual CPU structure.
1670 * @param enmAbort The VMX abort reason.
1671 */
1672IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1673{
1674 /*
1675 * Perform the VMX abort.
1676 * See Intel spec. 27.7 "VMX Aborts".
1677 */
1678 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1679
1680 /* We don't support SMX yet. */
1681 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1682 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1683 {
1684 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1685 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1686 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1687 }
1688
1689 return VINF_EM_TRIPLE_FAULT;
1690}
1691
1692
1693/**
1694 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1695 *
1696 * @param pVCpu The cross context virtual CPU structure.
1697 */
1698IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1699{
1700 /*
1701 * Load host control registers, debug registers and MSRs.
1702 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1703 */
1704 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1705 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1706
1707 /* CR0. */
1708 {
1709 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1710 uint64_t const uCr0Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
1711 uint64_t const uCr0Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
1712 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1713 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1714 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1715 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1716
1717 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1718 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1719 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1720 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1721 }
1722
1723 /* CR4. */
1724 {
1725 /* CR4 fixed bits are not modified. */
1726 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1727 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1728 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1729 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1730 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1731 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1732 if (fHostInLongMode)
1733 uValidHostCr4 |= X86_CR4_PAE;
1734 else
1735 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1736
1737 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1738 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1739 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1740 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1741 }
1742
1743 /* CR3 (host value validated while checking host-state during VM-entry). */
1744 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1745
1746 /* DR7. */
1747 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1748
1749 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1750
1751 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1752 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1753 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1754 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1755
1756 /* FS, GS bases are loaded later while we load host segment registers. */
1757
1758 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1759 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1760 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1761 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1762 {
1763 if (fHostInLongMode)
1764 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1765 else
1766 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1767 }
1768
1769 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1770
1771 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1772 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1773 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1774
1775 /* We don't support IA32_BNDCFGS MSR yet. */
1776}
1777
1778
1779/**
1780 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1781 *
1782 * @param pVCpu The cross context virtual CPU structure.
1783 */
1784IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1785{
1786 /*
1787 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1788 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1789 *
1790 * Warning! Be careful to not touch fields that are reserved by VT-x,
1791 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1792 */
1793 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1794 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1795
1796 /* CS, SS, ES, DS, FS, GS. */
1797 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1798 {
1799 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1800 bool const fUnusable = RT_BOOL(HostSel == 0);
1801 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1802
1803 /* Selector. */
1804 pSelReg->Sel = HostSel;
1805 pSelReg->ValidSel = HostSel;
1806 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1807
1808 /* Limit. */
1809 pSelReg->u32Limit = 0xffffffff;
1810
1811 /* Base. */
1812 pSelReg->u64Base = 0;
1813
1814 /* Attributes. */
1815 if (iSegReg == X86_SREG_CS)
1816 {
1817 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1818 pSelReg->Attr.n.u1DescType = 1;
1819 pSelReg->Attr.n.u2Dpl = 0;
1820 pSelReg->Attr.n.u1Present = 1;
1821 pSelReg->Attr.n.u1Long = fHostInLongMode;
1822 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1823 pSelReg->Attr.n.u1Granularity = 1;
1824 Assert(!pSelReg->Attr.n.u1Unusable);
1825 Assert(!fUnusable);
1826 }
1827 else
1828 {
1829 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1830 pSelReg->Attr.n.u1DescType = 1;
1831 pSelReg->Attr.n.u2Dpl = 0;
1832 pSelReg->Attr.n.u1Present = 1;
1833 pSelReg->Attr.n.u1DefBig = 1;
1834 pSelReg->Attr.n.u1Granularity = 1;
1835 pSelReg->Attr.n.u1Unusable = fUnusable;
1836 }
1837 }
1838
1839 /* FS base. */
1840 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1841 || fHostInLongMode)
1842 {
1843 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1844 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1845 }
1846
1847 /* GS base. */
1848 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1849 || fHostInLongMode)
1850 {
1851 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1852 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1853 }
1854
1855 /* TR. */
1856 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1857 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1858 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1859 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1860 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1861 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1862 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1863 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1864 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1865 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1866 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1867 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1868 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1869
1870 /* LDTR (Warning! do not touch the base and limits here). */
1871 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1872 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1873 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1874 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1875
1876 /* GDTR. */
1877 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1878 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1879 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1880
1881 /* IDTR.*/
1882 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1883 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1884 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1885}
1886
1887
1888/**
1889 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1890 *
1891 * @returns VBox status code.
1892 * @param pVCpu The cross context virtual CPU structure.
1893 * @param uExitReason The VMX instruction name (for logging purposes).
1894 */
1895IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1896{
1897 /*
1898 * Load host MSRs.
1899 * See Intel spec. 27.6 "Loading MSRs".
1900 */
1901 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1902 const char * const pszFailure = "VMX-abort";
1903
1904 /*
1905 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1906 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1907 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1908 */
1909 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1910 if (!cMsrs)
1911 return VINF_SUCCESS;
1912
1913 /*
1914 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1915 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1916 * implementation causes a VMX-abort followed by a triple-fault.
1917 */
1918 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1919 if (fIsMsrCountValid)
1920 { /* likely */ }
1921 else
1922 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1923
1924 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1925 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1926 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1927 if (RT_SUCCESS(rc))
1928 {
1929 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1930 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1931 {
1932 if ( !pMsr->u32Reserved
1933 && pMsr->u32Msr != MSR_K8_FS_BASE
1934 && pMsr->u32Msr != MSR_K8_GS_BASE
1935 && pMsr->u32Msr != MSR_K6_EFER
1936 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1937 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1938 {
1939 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1940 if (rcStrict == VINF_SUCCESS)
1941 continue;
1942
1943 /*
1944 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1945 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1946 * recording the MSR index in the auxiliary info. field and indicated further by our
1947 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1948 * if possible, or come up with a better, generic solution.
1949 */
1950 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1951 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1952 ? kVmxVDiag_Vmexit_MsrLoadRing3
1953 : kVmxVDiag_Vmexit_MsrLoad;
1954 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1955 }
1956 else
1957 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1958 }
1959 }
1960 else
1961 {
1962 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1963 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1964 }
1965
1966 NOREF(uExitReason);
1967 NOREF(pszFailure);
1968 return VINF_SUCCESS;
1969}
1970
1971
1972/**
1973 * Loads the host state as part of VM-exit.
1974 *
1975 * @returns Strict VBox status code.
1976 * @param pVCpu The cross context virtual CPU structure.
1977 * @param uExitReason The VM-exit reason (for logging purposes).
1978 */
1979IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
1980{
1981 /*
1982 * Load host state.
1983 * See Intel spec. 27.5 "Loading Host State".
1984 */
1985 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1986 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1987
1988 /* We cannot return from a long-mode guest to a host that is not in long mode. */
1989 if ( CPUMIsGuestInLongMode(pVCpu)
1990 && !fHostInLongMode)
1991 {
1992 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
1993 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
1994 }
1995
1996 /*
1997 * Check host PAE PDPTEs prior to loading the host state.
1998 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1999 */
2000 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2001 && !fHostInLongMode
2002 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2003 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2004 {
2005 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2006 if (RT_SUCCESS(rc))
2007 { /* likely*/ }
2008 else
2009 {
2010 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2011 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2012 }
2013 }
2014
2015 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2016 iemVmxVmexitLoadHostSegRegs(pVCpu);
2017
2018 /*
2019 * Load host RIP, RSP and RFLAGS.
2020 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2021 */
2022 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2023 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2024 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2025
2026 /* Clear address range monitoring. */
2027 EMMonitorWaitClear(pVCpu);
2028
2029 /* Perform the VMX transition (PGM updates). */
2030 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2031 if (rcStrict == VINF_SUCCESS)
2032 { /* likely */ }
2033 else if (RT_SUCCESS(rcStrict))
2034 {
2035 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2036 uExitReason));
2037 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2038 }
2039 else
2040 {
2041 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2042 return VBOXSTRICTRC_VAL(rcStrict);
2043 }
2044
2045 Assert(rcStrict == VINF_SUCCESS);
2046
2047 /* Load MSRs from the VM-exit auto-load MSR area. */
2048 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2049 if (RT_FAILURE(rc))
2050 {
2051 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2052 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2053 }
2054 return VINF_SUCCESS;
2055}
2056
2057
2058/**
2059 * Gets VM-exit instruction information along with any displacement for an
2060 * instruction VM-exit.
2061 *
2062 * @returns The VM-exit instruction information.
2063 * @param pVCpu The cross context virtual CPU structure.
2064 * @param uExitReason The VM-exit reason.
2065 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2066 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2067 * NULL.
2068 */
2069IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2070{
2071 RTGCPTR GCPtrDisp;
2072 VMXEXITINSTRINFO ExitInstrInfo;
2073 ExitInstrInfo.u = 0;
2074
2075 /*
2076 * Get and parse the ModR/M byte from our decoded opcodes.
2077 */
2078 uint8_t bRm;
2079 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2080 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2081 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2082 {
2083 /*
2084 * ModR/M indicates register addressing.
2085 *
2086 * The primary/secondary register operands are reported in the iReg1 or iReg2
2087 * fields depending on whether it is a read/write form.
2088 */
2089 uint8_t idxReg1;
2090 uint8_t idxReg2;
2091 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2092 {
2093 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2094 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2095 }
2096 else
2097 {
2098 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2099 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2100 }
2101 ExitInstrInfo.All.u2Scaling = 0;
2102 ExitInstrInfo.All.iReg1 = idxReg1;
2103 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2104 ExitInstrInfo.All.fIsRegOperand = 1;
2105 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2106 ExitInstrInfo.All.iSegReg = 0;
2107 ExitInstrInfo.All.iIdxReg = 0;
2108 ExitInstrInfo.All.fIdxRegInvalid = 1;
2109 ExitInstrInfo.All.iBaseReg = 0;
2110 ExitInstrInfo.All.fBaseRegInvalid = 1;
2111 ExitInstrInfo.All.iReg2 = idxReg2;
2112
2113 /* Displacement not applicable for register addressing. */
2114 GCPtrDisp = 0;
2115 }
2116 else
2117 {
2118 /*
2119 * ModR/M indicates memory addressing.
2120 */
2121 uint8_t uScale = 0;
2122 bool fBaseRegValid = false;
2123 bool fIdxRegValid = false;
2124 uint8_t iBaseReg = 0;
2125 uint8_t iIdxReg = 0;
2126 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2127 {
2128 /*
2129 * Parse the ModR/M, displacement for 16-bit addressing mode.
2130 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2131 */
2132 uint16_t u16Disp = 0;
2133 uint8_t const offDisp = offModRm + sizeof(bRm);
2134 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2135 {
2136 /* Displacement without any registers. */
2137 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2138 }
2139 else
2140 {
2141 /* Register (index and base). */
2142 switch (bRm & X86_MODRM_RM_MASK)
2143 {
2144 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2145 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2146 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2147 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2148 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2149 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2150 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2151 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2152 }
2153
2154 /* Register + displacement. */
2155 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2156 {
2157 case 0: break;
2158 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2159 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2160 default:
2161 {
2162 /* Register addressing, handled at the beginning. */
2163 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2164 break;
2165 }
2166 }
2167 }
2168
2169 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2170 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2171 }
2172 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2173 {
2174 /*
2175 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2176 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2177 */
2178 uint32_t u32Disp = 0;
2179 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2180 {
2181 /* Displacement without any registers. */
2182 uint8_t const offDisp = offModRm + sizeof(bRm);
2183 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2184 }
2185 else
2186 {
2187 /* Register (and perhaps scale, index and base). */
2188 uint8_t offDisp = offModRm + sizeof(bRm);
2189 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2190 if (iBaseReg == 4)
2191 {
2192 /* An SIB byte follows the ModR/M byte, parse it. */
2193 uint8_t bSib;
2194 uint8_t const offSib = offModRm + sizeof(bRm);
2195 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2196
2197 /* A displacement may follow SIB, update its offset. */
2198 offDisp += sizeof(bSib);
2199
2200 /* Get the scale. */
2201 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2202
2203 /* Get the index register. */
2204 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2205 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2206
2207 /* Get the base register. */
2208 iBaseReg = bSib & X86_SIB_BASE_MASK;
2209 fBaseRegValid = true;
2210 if (iBaseReg == 5)
2211 {
2212 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2213 {
2214 /* Mod is 0 implies a 32-bit displacement with no base. */
2215 fBaseRegValid = false;
2216 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2217 }
2218 else
2219 {
2220 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2221 iBaseReg = X86_GREG_xBP;
2222 }
2223 }
2224 }
2225
2226 /* Register + displacement. */
2227 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2228 {
2229 case 0: /* Handled above */ break;
2230 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2231 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2232 default:
2233 {
2234 /* Register addressing, handled at the beginning. */
2235 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2236 break;
2237 }
2238 }
2239 }
2240
2241 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2242 }
2243 else
2244 {
2245 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2246
2247 /*
2248 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2249 * See Intel instruction spec. 2.2 "IA-32e Mode".
2250 */
2251 uint64_t u64Disp = 0;
2252 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2253 if (fRipRelativeAddr)
2254 {
2255 /*
2256 * RIP-relative addressing mode.
2257 *
2258 * The displacement is 32-bit signed implying an offset range of +/-2G.
2259 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2260 */
2261 uint8_t const offDisp = offModRm + sizeof(bRm);
2262 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2263 }
2264 else
2265 {
2266 uint8_t offDisp = offModRm + sizeof(bRm);
2267
2268 /*
2269 * Register (and perhaps scale, index and base).
2270 *
2271 * REX.B extends the most-significant bit of the base register. However, REX.B
2272 * is ignored while determining whether an SIB follows the opcode. Hence, we
2273 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2274 *
2275 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2276 */
2277 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2278 if (iBaseReg == 4)
2279 {
2280 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2281 uint8_t bSib;
2282 uint8_t const offSib = offModRm + sizeof(bRm);
2283 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2284
2285 /* Displacement may follow SIB, update its offset. */
2286 offDisp += sizeof(bSib);
2287
2288 /* Get the scale. */
2289 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2290
2291 /* Get the index. */
2292 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2293 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2294
2295 /* Get the base. */
2296 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2297 fBaseRegValid = true;
2298 if (iBaseReg == 5)
2299 {
2300 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2301 {
2302 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2303 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2304 }
2305 else
2306 {
2307 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2308 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2309 }
2310 }
2311 }
2312 iBaseReg |= pVCpu->iem.s.uRexB;
2313
2314 /* Register + displacement. */
2315 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2316 {
2317 case 0: /* Handled above */ break;
2318 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2319 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2320 default:
2321 {
2322 /* Register addressing, handled at the beginning. */
2323 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2324 break;
2325 }
2326 }
2327 }
2328
2329 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2330 }
2331
2332 /*
2333 * The primary or secondary register operand is reported in iReg2 depending
2334 * on whether the primary operand is in read/write form.
2335 */
2336 uint8_t idxReg2;
2337 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2338 {
2339 idxReg2 = bRm & X86_MODRM_RM_MASK;
2340 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2341 idxReg2 |= pVCpu->iem.s.uRexB;
2342 }
2343 else
2344 {
2345 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2346 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2347 idxReg2 |= pVCpu->iem.s.uRexReg;
2348 }
2349 ExitInstrInfo.All.u2Scaling = uScale;
2350 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2351 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2352 ExitInstrInfo.All.fIsRegOperand = 0;
2353 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2354 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2355 ExitInstrInfo.All.iIdxReg = iIdxReg;
2356 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2357 ExitInstrInfo.All.iBaseReg = iBaseReg;
2358 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2359 ExitInstrInfo.All.iReg2 = idxReg2;
2360 }
2361
2362 /*
2363 * Handle exceptions to the norm for certain instructions.
2364 * (e.g. some instructions convey an instruction identity in place of iReg2).
2365 */
2366 switch (uExitReason)
2367 {
2368 case VMX_EXIT_GDTR_IDTR_ACCESS:
2369 {
2370 Assert(VMXINSTRID_IS_VALID(uInstrId));
2371 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2372 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2373 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2374 break;
2375 }
2376
2377 case VMX_EXIT_LDTR_TR_ACCESS:
2378 {
2379 Assert(VMXINSTRID_IS_VALID(uInstrId));
2380 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2381 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2382 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2383 break;
2384 }
2385
2386 case VMX_EXIT_RDRAND:
2387 case VMX_EXIT_RDSEED:
2388 {
2389 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2390 break;
2391 }
2392 }
2393
2394 /* Update displacement and return the constructed VM-exit instruction information field. */
2395 if (pGCPtrDisp)
2396 *pGCPtrDisp = GCPtrDisp;
2397
2398 return ExitInstrInfo.u;
2399}
2400
2401
2402/**
2403 * VMX VM-exit handler.
2404 *
2405 * @returns Strict VBox status code.
2406 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2407 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2408 * triple-fault.
2409 *
2410 * @param pVCpu The cross context virtual CPU structure.
2411 * @param uExitReason The VM-exit reason.
2412 * @param u64ExitQual The Exit qualification.
2413 *
2414 * @remarks We need not necessarily have completed VM-entry before a VM-exit is
2415 * called. Failures during VM-entry can cause VM-exits as well, so we
2416 * -cannot- assert we're in VMX non-root mode here.
2417 */
2418IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2419{
2420# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2421 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2422 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2423 return VERR_IEM_IPE_7;
2424# else
2425 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2426
2427 /*
2428 * Import all the guest-CPU state.
2429 *
2430 * HM on returning to guest execution would have to reset up a whole lot of state
2431 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2432 * the state and flag reloading the entire state on re-entry. So import the entire
2433 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2434 */
2435 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2436
2437 /*
2438 * Ensure VM-entry interruption information valid bit is cleared.
2439 *
2440 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2441 * by invalid-guest state or machine-check exceptions) also clear this bit.
2442 *
2443 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2444 */
2445 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2446 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2447
2448 /*
2449 * Update the VM-exit reason and Exit qualification.
2450 * Other VMCS read-only data fields are expected to be updated by the caller already.
2451 */
2452 pVmcs->u32RoExitReason = uExitReason;
2453 pVmcs->u64RoExitQual.u = u64ExitQual;
2454
2455 Log3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2456 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2457 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2458
2459 /*
2460 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2461 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2462 */
2463 {
2464 uint8_t uVector;
2465 uint32_t fFlags;
2466 uint32_t uErrCode;
2467 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2468 if (fInEventDelivery)
2469 {
2470 /*
2471 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2472 * caused by a triple-fault or the original event results in a double-fault that
2473 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2474 * original event information into the IDT-vectoring information fields.
2475 *
2476 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2477 */
2478 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2479 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2480 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2481 {
2482 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2483 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2484 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2485 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2486 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2487 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2488 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2489 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2490 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2491 pVCpu->cpum.GstCtx.cr2));
2492 }
2493 }
2494 }
2495
2496 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2497 Assert(pVmcs->u64RoIoRcx.u == 0);
2498 Assert(pVmcs->u64RoIoRsi.u == 0);
2499 Assert(pVmcs->u64RoIoRdi.u == 0);
2500 Assert(pVmcs->u64RoIoRip.u == 0);
2501
2502 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2503 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2504 {
2505 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2506 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2507 }
2508
2509 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2510 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2511
2512 /*
2513 * Save the guest state back into the VMCS.
2514 * We only need to save the state when the VM-entry was successful.
2515 */
2516 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2517 if (!fVmentryFailed)
2518 {
2519 /*
2520 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2521 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2522 *
2523 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2524 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2525 * as guest-CPU state would not been modified. Hence for now, we do this only when
2526 * the VM-entry succeeded.
2527 */
2528 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2529 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2530 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2531 {
2532 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2533 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2534 else
2535 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2536 }
2537
2538 /*
2539 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2540 * occurs in enclave mode/SMM which we don't support yet.
2541 *
2542 * If we ever add support for it, we can pass just the lower bits to the functions
2543 * below, till then an assert should suffice.
2544 */
2545 Assert(!RT_HI_U16(uExitReason));
2546
2547 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2548 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2549 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2550 if (RT_SUCCESS(rc))
2551 { /* likely */ }
2552 else
2553 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2554
2555 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2556 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2557 }
2558 else
2559 {
2560 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2561 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2562 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2563 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2564 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2565 }
2566
2567 /*
2568 * Stop any running VMX-preemption timer if necessary.
2569 */
2570 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2571 CPUMStopGuestVmxPremptTimer(pVCpu);
2572
2573 /*
2574 * Clear any pending VMX nested-guest force-flags.
2575 * These force-flags have no effect on (outer) guest execution and will
2576 * be re-evaluated and setup on the next nested-guest VM-entry.
2577 */
2578 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2579
2580 /*
2581 * We're no longer in nested-guest execution mode.
2582 *
2583 * It is important to do this prior to loading the host state because
2584 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2585 * second-level address translation while switching to host CR3.
2586 */
2587 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2588
2589 /* Restore the host (outer guest) state. */
2590 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2591 if (RT_SUCCESS(rcStrict))
2592 {
2593 Assert(rcStrict == VINF_SUCCESS);
2594 rcStrict = VINF_VMX_VMEXIT;
2595 }
2596 else
2597 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2598
2599 /* Notify HM that the current VMCS fields have been modified. */
2600 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2601
2602 /* Notify HM that we've completed the VM-exit. */
2603 HMNotifyVmxNstGstVmexit(pVCpu);
2604
2605# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2606 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2607 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2608 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2609 if (rcSched != VINF_SUCCESS)
2610 iemSetPassUpStatus(pVCpu, rcSched);
2611# endif
2612 return rcStrict;
2613# endif
2614}
2615
2616
2617/**
2618 * VMX VM-exit handler for VM-exits due to instruction execution.
2619 *
2620 * This is intended for instructions where the caller provides all the relevant
2621 * VM-exit information.
2622 *
2623 * @returns Strict VBox status code.
2624 * @param pVCpu The cross context virtual CPU structure.
2625 * @param pExitInfo Pointer to the VM-exit information.
2626 */
2627IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2628{
2629 /*
2630 * For instructions where any of the following fields are not applicable:
2631 * - Exit qualification must be cleared.
2632 * - VM-exit instruction info. is undefined.
2633 * - Guest-linear address is undefined.
2634 * - Guest-physical address is undefined.
2635 *
2636 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2637 * instruction execution. For VM-exits that are not due to instruction execution this
2638 * field is undefined.
2639 *
2640 * In our implementation in IEM, all undefined fields are generally cleared. However,
2641 * if the caller supplies information (from say the physical CPU directly) it is
2642 * then possible that the undefined fields are not cleared.
2643 *
2644 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2645 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2646 */
2647 Assert(pExitInfo);
2648 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2649 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2650 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2651
2652 /* Update all the relevant fields from the VM-exit instruction information struct. */
2653 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2654 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2655 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2656 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2657
2658 /* Perform the VM-exit. */
2659 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2660}
2661
2662
2663/**
2664 * VMX VM-exit handler for VM-exits due to instruction execution.
2665 *
2666 * This is intended for instructions that only provide the VM-exit instruction
2667 * length.
2668 *
2669 * @param pVCpu The cross context virtual CPU structure.
2670 * @param uExitReason The VM-exit reason.
2671 * @param cbInstr The instruction length in bytes.
2672 */
2673IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2674{
2675 VMXVEXITINFO ExitInfo;
2676 RT_ZERO(ExitInfo);
2677 ExitInfo.uReason = uExitReason;
2678 ExitInfo.cbInstr = cbInstr;
2679
2680#ifdef VBOX_STRICT
2681 /*
2682 * To prevent us from shooting ourselves in the foot.
2683 * The follow instructions should convey more than just the instruction length.
2684 */
2685 switch (uExitReason)
2686 {
2687 case VMX_EXIT_INVEPT:
2688 case VMX_EXIT_INVPCID:
2689 case VMX_EXIT_INVVPID:
2690 case VMX_EXIT_LDTR_TR_ACCESS:
2691 case VMX_EXIT_GDTR_IDTR_ACCESS:
2692 case VMX_EXIT_VMCLEAR:
2693 case VMX_EXIT_VMPTRLD:
2694 case VMX_EXIT_VMPTRST:
2695 case VMX_EXIT_VMREAD:
2696 case VMX_EXIT_VMWRITE:
2697 case VMX_EXIT_VMXON:
2698 case VMX_EXIT_XRSTORS:
2699 case VMX_EXIT_XSAVES:
2700 case VMX_EXIT_RDRAND:
2701 case VMX_EXIT_RDSEED:
2702 case VMX_EXIT_IO_INSTR:
2703 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2704 break;
2705 }
2706#endif
2707
2708 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2709}
2710
2711
2712/**
2713 * VMX VM-exit handler for VM-exits due to instruction execution.
2714 *
2715 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2716 * instruction information and Exit qualification fields.
2717 *
2718 * @param pVCpu The cross context virtual CPU structure.
2719 * @param uExitReason The VM-exit reason.
2720 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2721 * @param cbInstr The instruction length in bytes.
2722 *
2723 * @remarks Do not use this for INS/OUTS instruction.
2724 */
2725IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2726{
2727 VMXVEXITINFO ExitInfo;
2728 RT_ZERO(ExitInfo);
2729 ExitInfo.uReason = uExitReason;
2730 ExitInfo.cbInstr = cbInstr;
2731
2732 /*
2733 * Update the Exit qualification field with displacement bytes.
2734 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2735 */
2736 switch (uExitReason)
2737 {
2738 case VMX_EXIT_INVEPT:
2739 case VMX_EXIT_INVPCID:
2740 case VMX_EXIT_INVVPID:
2741 case VMX_EXIT_LDTR_TR_ACCESS:
2742 case VMX_EXIT_GDTR_IDTR_ACCESS:
2743 case VMX_EXIT_VMCLEAR:
2744 case VMX_EXIT_VMPTRLD:
2745 case VMX_EXIT_VMPTRST:
2746 case VMX_EXIT_VMREAD:
2747 case VMX_EXIT_VMWRITE:
2748 case VMX_EXIT_VMXON:
2749 case VMX_EXIT_XRSTORS:
2750 case VMX_EXIT_XSAVES:
2751 case VMX_EXIT_RDRAND:
2752 case VMX_EXIT_RDSEED:
2753 {
2754 /* Construct the VM-exit instruction information. */
2755 RTGCPTR GCPtrDisp;
2756 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2757
2758 /* Update the VM-exit instruction information. */
2759 ExitInfo.InstrInfo.u = uInstrInfo;
2760
2761 /* Update the Exit qualification. */
2762 ExitInfo.u64Qual = GCPtrDisp;
2763 break;
2764 }
2765
2766 default:
2767 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2768 break;
2769 }
2770
2771 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2772}
2773
2774
2775/**
2776 * VMX VM-exit handler for VM-exits due to INVLPG.
2777 *
2778 * @returns Strict VBox status code.
2779 * @param pVCpu The cross context virtual CPU structure.
2780 * @param GCPtrPage The guest-linear address of the page being invalidated.
2781 * @param cbInstr The instruction length in bytes.
2782 */
2783IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2784{
2785 VMXVEXITINFO ExitInfo;
2786 RT_ZERO(ExitInfo);
2787 ExitInfo.uReason = VMX_EXIT_INVLPG;
2788 ExitInfo.cbInstr = cbInstr;
2789 ExitInfo.u64Qual = GCPtrPage;
2790 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2791
2792 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2793}
2794
2795
2796/**
2797 * VMX VM-exit handler for VM-exits due to LMSW.
2798 *
2799 * @returns Strict VBox status code.
2800 * @param pVCpu The cross context virtual CPU structure.
2801 * @param uGuestCr0 The current guest CR0.
2802 * @param pu16NewMsw The machine-status word specified in LMSW's source
2803 * operand. This will be updated depending on the VMX
2804 * guest/host CR0 mask if LMSW is not intercepted.
2805 * @param GCPtrEffDst The guest-linear address of the source operand in case
2806 * of a memory operand. For register operand, pass
2807 * NIL_RTGCPTR.
2808 * @param cbInstr The instruction length in bytes.
2809 */
2810IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2811 uint8_t cbInstr)
2812{
2813 Assert(pu16NewMsw);
2814
2815 uint16_t const uNewMsw = *pu16NewMsw;
2816 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2817 {
2818 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2819
2820 VMXVEXITINFO ExitInfo;
2821 RT_ZERO(ExitInfo);
2822 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2823 ExitInfo.cbInstr = cbInstr;
2824
2825 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2826 if (fMemOperand)
2827 {
2828 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2829 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2830 }
2831
2832 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2833 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2834 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2835 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2836
2837 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2838 }
2839
2840 /*
2841 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2842 * CR0 guest/host mask must be left unmodified.
2843 *
2844 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2845 */
2846 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2847 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2848 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2849
2850 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2851}
2852
2853
2854/**
2855 * VMX VM-exit handler for VM-exits due to CLTS.
2856 *
2857 * @returns Strict VBox status code.
2858 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2859 * VM-exit but must not modify the guest CR0.TS bit.
2860 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2861 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2862 * CR0 fixed bits in VMX operation).
2863 * @param pVCpu The cross context virtual CPU structure.
2864 * @param cbInstr The instruction length in bytes.
2865 */
2866IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2867{
2868 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2869 uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2870
2871 /*
2872 * If CR0.TS is owned by the host:
2873 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2874 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2875 * CLTS instruction completes without clearing CR0.TS.
2876 *
2877 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2878 */
2879 if (fGstHostMask & X86_CR0_TS)
2880 {
2881 if (fReadShadow & X86_CR0_TS)
2882 {
2883 Log2(("clts: Guest intercept -> VM-exit\n"));
2884
2885 VMXVEXITINFO ExitInfo;
2886 RT_ZERO(ExitInfo);
2887 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2888 ExitInfo.cbInstr = cbInstr;
2889 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2890 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2891 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2892 }
2893
2894 return VINF_VMX_MODIFIES_BEHAVIOR;
2895 }
2896
2897 /*
2898 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2899 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2900 */
2901 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2902}
2903
2904
2905/**
2906 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2907 * (CR0/CR4 write).
2908 *
2909 * @returns Strict VBox status code.
2910 * @param pVCpu The cross context virtual CPU structure.
2911 * @param iCrReg The control register (either CR0 or CR4).
2912 * @param uGuestCrX The current guest CR0/CR4.
2913 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2914 * VM-exit is caused.
2915 * @param iGReg The general register from which the CR0/CR4 value is being
2916 * loaded.
2917 * @param cbInstr The instruction length in bytes.
2918 */
2919IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2920 uint8_t cbInstr)
2921{
2922 Assert(puNewCrX);
2923 Assert(iCrReg == 0 || iCrReg == 4);
2924 Assert(iGReg < X86_GREG_COUNT);
2925
2926 uint64_t const uNewCrX = *puNewCrX;
2927 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2928 {
2929 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2930
2931 VMXVEXITINFO ExitInfo;
2932 RT_ZERO(ExitInfo);
2933 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2934 ExitInfo.cbInstr = cbInstr;
2935 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2936 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2937 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2938 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2939 }
2940
2941 /*
2942 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2943 * must not be modified the instruction.
2944 *
2945 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2946 */
2947 uint64_t uGuestCrX;
2948 uint64_t fGstHostMask;
2949 if (iCrReg == 0)
2950 {
2951 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2952 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2953 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2954 }
2955 else
2956 {
2957 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2958 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2959 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2960 }
2961
2962 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2963 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2964}
2965
2966
2967/**
2968 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2969 *
2970 * @returns VBox strict status code.
2971 * @param pVCpu The cross context virtual CPU structure.
2972 * @param iGReg The general register to which the CR3 value is being stored.
2973 * @param cbInstr The instruction length in bytes.
2974 */
2975IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
2976{
2977 Assert(iGReg < X86_GREG_COUNT);
2978 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
2979
2980 /*
2981 * If the CR3-store exiting control is set, we must cause a VM-exit.
2982 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2983 */
2984 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
2985 {
2986 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
2987
2988 VMXVEXITINFO ExitInfo;
2989 RT_ZERO(ExitInfo);
2990 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2991 ExitInfo.cbInstr = cbInstr;
2992 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
2993 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
2994 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2995 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2996 }
2997
2998 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2999}
3000
3001
3002/**
3003 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3004 *
3005 * @returns VBox strict status code.
3006 * @param pVCpu The cross context virtual CPU structure.
3007 * @param uNewCr3 The new CR3 value.
3008 * @param iGReg The general register from which the CR3 value is being
3009 * loaded.
3010 * @param cbInstr The instruction length in bytes.
3011 */
3012IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3013{
3014 Assert(iGReg < X86_GREG_COUNT);
3015
3016 /*
3017 * If the CR3-load exiting control is set and the new CR3 value does not
3018 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3019 *
3020 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3021 */
3022 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3023 {
3024 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3025
3026 VMXVEXITINFO ExitInfo;
3027 RT_ZERO(ExitInfo);
3028 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3029 ExitInfo.cbInstr = cbInstr;
3030 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3031 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3032 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3033 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3034 }
3035
3036 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3037}
3038
3039
3040/**
3041 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3042 *
3043 * @returns VBox strict status code.
3044 * @param pVCpu The cross context virtual CPU structure.
3045 * @param iGReg The general register to which the CR8 value is being stored.
3046 * @param cbInstr The instruction length in bytes.
3047 */
3048IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3049{
3050 Assert(iGReg < X86_GREG_COUNT);
3051
3052 /*
3053 * If the CR8-store exiting control is set, we must cause a VM-exit.
3054 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3055 */
3056 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3057 {
3058 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3059
3060 VMXVEXITINFO ExitInfo;
3061 RT_ZERO(ExitInfo);
3062 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3063 ExitInfo.cbInstr = cbInstr;
3064 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3065 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3066 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3067 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3068 }
3069
3070 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3071}
3072
3073
3074/**
3075 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3076 *
3077 * @returns VBox strict status code.
3078 * @param pVCpu The cross context virtual CPU structure.
3079 * @param iGReg The general register from which the CR8 value is being
3080 * loaded.
3081 * @param cbInstr The instruction length in bytes.
3082 */
3083IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3084{
3085 Assert(iGReg < X86_GREG_COUNT);
3086
3087 /*
3088 * If the CR8-load exiting control is set, we must cause a VM-exit.
3089 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3090 */
3091 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3092 {
3093 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3094
3095 VMXVEXITINFO ExitInfo;
3096 RT_ZERO(ExitInfo);
3097 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3098 ExitInfo.cbInstr = cbInstr;
3099 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3100 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3101 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3102 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3103 }
3104
3105 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3106}
3107
3108
3109/**
3110 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3111 * GReg,DRx' (DRx read).
3112 *
3113 * @returns VBox strict status code.
3114 * @param pVCpu The cross context virtual CPU structure.
3115 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3116 * VMXINSTRID_MOV_FROM_DRX).
3117 * @param iDrReg The debug register being accessed.
3118 * @param iGReg The general register to/from which the DRx value is being
3119 * store/loaded.
3120 * @param cbInstr The instruction length in bytes.
3121 */
3122IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3123 uint8_t cbInstr)
3124{
3125 Assert(iDrReg <= 7);
3126 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3127 Assert(iGReg < X86_GREG_COUNT);
3128
3129 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3130 {
3131 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3132 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3133 VMXVEXITINFO ExitInfo;
3134 RT_ZERO(ExitInfo);
3135 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3136 ExitInfo.cbInstr = cbInstr;
3137 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3138 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3139 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3140 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3141 }
3142
3143 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3144}
3145
3146
3147/**
3148 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3149 *
3150 * @returns VBox strict status code.
3151 * @param pVCpu The cross context virtual CPU structure.
3152 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3153 * VMXINSTRID_IO_OUT).
3154 * @param u16Port The I/O port being accessed.
3155 * @param fImm Whether the I/O port was encoded using an immediate operand
3156 * or the implicit DX register.
3157 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3158 * @param cbInstr The instruction length in bytes.
3159 */
3160IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3161 uint8_t cbInstr)
3162{
3163 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3164 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3165
3166 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3167 if (fIntercept)
3168 {
3169 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3170 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3171 VMXVEXITINFO ExitInfo;
3172 RT_ZERO(ExitInfo);
3173 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3174 ExitInfo.cbInstr = cbInstr;
3175 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3176 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3177 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3178 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3179 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3180 }
3181
3182 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3183}
3184
3185
3186/**
3187 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3188 *
3189 * @returns VBox strict status code.
3190 * @param pVCpu The cross context virtual CPU structure.
3191 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3192 * VMXINSTRID_IO_OUTS).
3193 * @param u16Port The I/O port being accessed.
3194 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3195 * @param fRep Whether the instruction has a REP prefix or not.
3196 * @param ExitInstrInfo The VM-exit instruction info. field.
3197 * @param cbInstr The instruction length in bytes.
3198 */
3199IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3200 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3201{
3202 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3203 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3204 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3205 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3206 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3207
3208 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3209 if (fIntercept)
3210 {
3211 /*
3212 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3213 */
3214 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3215 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3216 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3217 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3218 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3219
3220 uint32_t uDirection;
3221 uint64_t uGuestLinearAddr;
3222 if (uInstrId == VMXINSTRID_IO_INS)
3223 {
3224 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3225 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3226 }
3227 else
3228 {
3229 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3230 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3231 }
3232
3233 /*
3234 * If the segment is unusable, the guest-linear address in undefined.
3235 * We shall clear it for consistency.
3236 *
3237 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3238 */
3239 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3240 uGuestLinearAddr = 0;
3241
3242 VMXVEXITINFO ExitInfo;
3243 RT_ZERO(ExitInfo);
3244 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3245 ExitInfo.cbInstr = cbInstr;
3246 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3247 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3248 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3249 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3250 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3251 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3252 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3253 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3254 ExitInfo.InstrInfo = ExitInstrInfo;
3255 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3256 }
3257
3258 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3259}
3260
3261
3262/**
3263 * VMX VM-exit handler for VM-exits due to MWAIT.
3264 *
3265 * @returns VBox strict status code.
3266 * @param pVCpu The cross context virtual CPU structure.
3267 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3268 * @param cbInstr The instruction length in bytes.
3269 */
3270IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3271{
3272 VMXVEXITINFO ExitInfo;
3273 RT_ZERO(ExitInfo);
3274 ExitInfo.uReason = VMX_EXIT_MWAIT;
3275 ExitInfo.cbInstr = cbInstr;
3276 ExitInfo.u64Qual = fMonitorHwArmed;
3277 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3278}
3279
3280
3281/**
3282 * VMX VM-exit handler for VM-exits due to PAUSE.
3283 *
3284 * @returns VBox strict status code.
3285 * @param pVCpu The cross context virtual CPU structure.
3286 * @param cbInstr The instruction length in bytes.
3287 */
3288IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3289{
3290 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3291
3292 /*
3293 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3294 * "PAUSE-loop exiting" control.
3295 *
3296 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3297 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3298 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3299 * a VM-exit.
3300 *
3301 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3302 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3303 */
3304 bool fIntercept = false;
3305 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3306 fIntercept = true;
3307 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3308 && pVCpu->iem.s.uCpl == 0)
3309 {
3310 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3311
3312 /*
3313 * A previous-PAUSE-tick value of 0 is used to identify the first time
3314 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3315 * consider this to be the first execution of PAUSE in a loop according
3316 * to the Intel.
3317 *
3318 * All subsequent records for the previous-PAUSE-tick we ensure that it
3319 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3320 */
3321 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3322 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3323 uint64_t const uTick = TMCpuTickGet(pVCpu);
3324 uint32_t const uPleGap = pVmcs->u32PleGap;
3325 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3326 if ( *puPrevPauseTick == 0
3327 || uTick - *puPrevPauseTick > uPleGap)
3328 *puFirstPauseLoopTick = uTick;
3329 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3330 fIntercept = true;
3331
3332 *puPrevPauseTick = uTick | 1;
3333 }
3334
3335 if (fIntercept)
3336 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3337
3338 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3339}
3340
3341
3342/**
3343 * VMX VM-exit handler for VM-exits due to task switches.
3344 *
3345 * @returns VBox strict status code.
3346 * @param pVCpu The cross context virtual CPU structure.
3347 * @param enmTaskSwitch The cause of the task switch.
3348 * @param SelNewTss The selector of the new TSS.
3349 * @param cbInstr The instruction length in bytes.
3350 */
3351IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3352{
3353 /*
3354 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3355 *
3356 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3357 * instruction or delivery of the exception generated by one of these instructions
3358 * lead to a task switch through a task gate in the IDT, we need to provide the
3359 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3360 * leaves the VM-exit instruction length field undefined.
3361 *
3362 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3363 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3364 */
3365 Assert(cbInstr <= 15);
3366
3367 uint8_t uType;
3368 switch (enmTaskSwitch)
3369 {
3370 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3371 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3372 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3373 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3374 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3375 }
3376
3377 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3378 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3379 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3380 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3381}
3382
3383
3384/**
3385 * VMX VM-exit handler for trap-like VM-exits.
3386 *
3387 * @returns VBox strict status code.
3388 * @param pVCpu The cross context virtual CPU structure.
3389 * @param pExitInfo Pointer to the VM-exit information.
3390 * @param pExitEventInfo Pointer to the VM-exit event information.
3391 */
3392IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3393{
3394 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3395 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3396 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3397}
3398
3399
3400/**
3401 * VMX VM-exit handler for VM-exits due to task switches.
3402 *
3403 * This is intended for task switches where the caller provides all the relevant
3404 * VM-exit information.
3405 *
3406 * @returns VBox strict status code.
3407 * @param pVCpu The cross context virtual CPU structure.
3408 * @param pExitInfo Pointer to the VM-exit information.
3409 * @param pExitEventInfo Pointer to the VM-exit event information.
3410 */
3411IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3412 PCVMXVEXITEVENTINFO pExitEventInfo)
3413{
3414 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3415 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3416 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3417 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3418 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3419}
3420
3421
3422/**
3423 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3424 *
3425 * @returns VBox strict status code.
3426 * @param pVCpu The cross context virtual CPU structure.
3427 */
3428IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3429{
3430 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3431 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3432
3433 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3434 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3435
3436 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3437 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3438 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3439
3440 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3441 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3442}
3443
3444
3445/**
3446 * VMX VM-exit handler for VM-exits due to external interrupts.
3447 *
3448 * @returns VBox strict status code.
3449 * @param pVCpu The cross context virtual CPU structure.
3450 * @param uVector The external interrupt vector (pass 0 if the interrupt
3451 * is still pending since we typically won't know the
3452 * vector).
3453 * @param fIntPending Whether the external interrupt is pending or
3454 * acknowledged in the interrupt controller.
3455 */
3456IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3457{
3458 Assert(!fIntPending || uVector == 0);
3459
3460 /* The VM-exit is subject to "External interrupt exiting" being set. */
3461 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3462 {
3463 if (fIntPending)
3464 {
3465 /*
3466 * If the interrupt is pending and we don't need to acknowledge the
3467 * interrupt on VM-exit, cause the VM-exit immediately.
3468 *
3469 * See Intel spec 25.2 "Other Causes Of VM Exits".
3470 */
3471 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3472 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3473
3474 /*
3475 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3476 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3477 * acknowledged that the interrupt has been consumed. Callers would have to call
3478 * us again after getting the vector (and ofc, with fIntPending with false).
3479 */
3480 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3481 }
3482
3483 /*
3484 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3485 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3486 * all set, we need to record the vector of the external interrupt in the
3487 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3488 *
3489 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3490 */
3491 uint32_t uExitIntInfo;
3492 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3493 {
3494 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3495 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3496 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3497 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3498 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3499 }
3500 else
3501 uExitIntInfo = 0;
3502 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3503
3504 /*
3505 * Cause the VM-exit whether or not the vector has been stored
3506 * in the VM-exit interruption-information field.
3507 */
3508 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3509 }
3510
3511 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3512}
3513
3514
3515/**
3516 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3517 * an event.
3518 *
3519 * @returns VBox strict status code.
3520 * @param pVCpu The cross context virtual CPU structure.
3521 */
3522IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3523{
3524 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3525 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3526 {
3527 /*
3528 * The NMI-unblocking due to IRET field need not be set for double faults.
3529 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3530 */
3531 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3532 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3533 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3534 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3535 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3536 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3537 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3538 }
3539
3540 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3541}
3542
3543
3544/**
3545 * VMX VM-exit handler for VM-exit due to delivery of an events.
3546 *
3547 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3548 * all the relevant VM-exit information.
3549 *
3550 * @returns VBox strict status code.
3551 * @param pVCpu The cross context virtual CPU structure.
3552 * @param pExitInfo Pointer to the VM-exit information.
3553 * @param pExitEventInfo Pointer to the VM-exit event information.
3554 */
3555IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3556{
3557 Assert(pExitInfo);
3558 Assert(pExitEventInfo);
3559 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3560 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3561
3562 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3563 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3564 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3565 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3566 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3567 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3568}
3569
3570
3571/**
3572 * VMX VM-exit handler for VM-exits due to delivery of an event.
3573 *
3574 * @returns VBox strict status code.
3575 * @param pVCpu The cross context virtual CPU structure.
3576 * @param uVector The interrupt / exception vector.
3577 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3578 * @param uErrCode The error code associated with the event.
3579 * @param uCr2 The CR2 value in case of a \#PF exception.
3580 * @param cbInstr The instruction length in bytes.
3581 */
3582IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3583 uint8_t cbInstr)
3584{
3585 /*
3586 * If the event is being injected as part of VM-entry, it is -not- subject to event
3587 * intercepts in the nested-guest. However, secondary exceptions that occur during
3588 * injection of any event -are- subject to event interception.
3589 *
3590 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3591 */
3592 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3593 {
3594 /*
3595 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3596 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3597 *
3598 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3599 */
3600 if ( uVector == X86_XCPT_NMI
3601 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3602 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3603 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3604 else
3605 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3606
3607 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3608 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3609 }
3610
3611 /*
3612 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3613 * If not, the caller will continue delivery of the external interrupt as it would
3614 * normally. The interrupt is no longer pending in the interrupt controller at this
3615 * point.
3616 */
3617 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3618 {
3619 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3620 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3621 }
3622
3623 /*
3624 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3625 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3626 * interrupts.
3627 */
3628 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3629 bool fIntercept;
3630 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3631 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3632 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3633 else
3634 {
3635 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3636 fIntercept = false;
3637 }
3638
3639 /*
3640 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3641 * relevant VM-exit information and cause the VM-exit.
3642 */
3643 if (fIntercept)
3644 {
3645 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3646
3647 /* Construct the rest of the event related information fields and cause the VM-exit. */
3648 uint64_t u64ExitQual;
3649 if (uVector == X86_XCPT_PF)
3650 {
3651 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3652 u64ExitQual = uCr2;
3653 }
3654 else if (uVector == X86_XCPT_DB)
3655 {
3656 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3657 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3658 }
3659 else
3660 u64ExitQual = 0;
3661
3662 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3663 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3664 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3665 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3666 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3667 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3668 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3669 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3670 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3671 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3672
3673 /*
3674 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3675 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3676 * length.
3677 */
3678 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3679 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3680 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3681 else
3682 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3683
3684 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3685 }
3686
3687 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3688}
3689
3690
3691/**
3692 * VMX VM-exit handler for EPT misconfiguration.
3693 *
3694 * @param pVCpu The cross context virtual CPU structure.
3695 * @param GCPhysAddr The physical address causing the EPT misconfiguration. This
3696 * must be page aligned.
3697 */
3698IEM_STATIC VBOXSTRICTRC iemVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr)
3699{
3700 Assert(!(GCPhysAddr & PAGE_OFFSET_MASK));
3701 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3702 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3703}
3704
3705
3706/**
3707 * VMX VM-exit handler for EPT violation.
3708 *
3709 * @param pVCpu The cross context virtual CPU structure.
3710 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3711 * @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
3712 * @param fEptAccess The EPT paging structure bits.
3713 * @param GCPhysAddr The physical address causing the EPT violation. This
3714 * must be page aligned.
3715 * @param fIsLinearAddrValid Whether translation of a linear address caused this
3716 * EPT violation. If @c false, GCPtrAddr must be 0.
3717 * @param GCPtrAddr The linear address causing the EPT violation.
3718 * @param cbInstr The VM-exit instruction length.
3719 */
3720IEM_STATIC VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail, uint64_t fEptAccess,
3721 RTGCPHYS GCPhysAddr, bool fLinearAddrValid, uint64_t GCPtrAddr, uint8_t cbInstr)
3722{
3723 /*
3724 * If the linear address isn't valid (can happen when loading PDPTEs
3725 * as part of MOV CR execution) the linear address field is undefined.
3726 * While we can leave it this way, it's preferrable to zero it for consistency.
3727 */
3728 Assert(fLinearAddrValid || GCPtrAddr == 0);
3729 Assert(!(GCPhysAddr & PAGE_OFFSET_MASK));
3730
3731 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3732 uint8_t const fSupportsAccessDirty = fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY;
3733
3734 uint8_t const fDataRead = ((fAccess & IEM_ACCESS_DATA_R) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3735 uint8_t const fDataWrite = ((fAccess & IEM_ACCESS_DATA_RW) == IEM_ACCESS_DATA_RW) | fSupportsAccessDirty;
3736 uint8_t const fInstrFetch = (fAccess & IEM_ACCESS_INSTRUCTION) == IEM_ACCESS_INSTRUCTION;
3737 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3738 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3739 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3740 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3741 bool const fLinearToPhysAddr = fLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
3742
3743 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
3744 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
3745 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
3746 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
3747 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
3748 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
3749 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fLinearAddrValid)
3750 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fLinearToPhysAddr)
3751 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
3752
3753#ifdef VBOX_STRICT
3754 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
3755 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
3756 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
3757 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
3758 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3759 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
3760#endif
3761
3762 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3763 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
3764 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3765
3766 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
3767}
3768
3769
3770/**
3771 * VMX VM-exit handler for EPT-induced VM-exits.
3772 *
3773 * @param pVCpu The cross context virtual CPU structure.
3774 * @param pWalk The page walk info.
3775 * @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
3776 * @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
3777 * @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
3778 * applicable.
3779 */
3780IEM_STATIC VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail,
3781 uint8_t cbInstr)
3782{
3783 Assert(pWalk->fIsSlat);
3784 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
3785 Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
3786 Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
3787
3788 if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
3789 {
3790 uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
3791 return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
3792 pWalk->GCPtr, cbInstr);
3793 }
3794
3795 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
3796 return iemVmxVmexitEptMisconfig(pVCpu, pWalk->GCPhysNested);
3797}
3798
3799
3800/**
3801 * VMX VM-exit handler for APIC accesses.
3802 *
3803 * @param pVCpu The cross context virtual CPU structure.
3804 * @param offAccess The offset of the register being accessed.
3805 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3806 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3807 */
3808IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3809{
3810 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3811
3812 VMXAPICACCESS enmAccess;
3813 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3814 if (fInEventDelivery)
3815 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3816 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3817 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3818 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3819 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3820 else
3821 enmAccess = VMXAPICACCESS_LINEAR_READ;
3822
3823 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3824 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3825 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3826}
3827
3828
3829/**
3830 * VMX VM-exit handler for APIC accesses.
3831 *
3832 * This is intended for APIC accesses where the caller provides all the
3833 * relevant VM-exit information.
3834 *
3835 * @returns VBox strict status code.
3836 * @param pVCpu The cross context virtual CPU structure.
3837 * @param pExitInfo Pointer to the VM-exit information.
3838 * @param pExitEventInfo Pointer to the VM-exit event information.
3839 */
3840IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3841 PCVMXVEXITEVENTINFO pExitEventInfo)
3842{
3843 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3844 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3845 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3846 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3847 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3848 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3849 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3850 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3851 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3852}
3853
3854
3855/**
3856 * VMX VM-exit handler for APIC-write VM-exits.
3857 *
3858 * @param pVCpu The cross context virtual CPU structure.
3859 * @param offApic The write to the virtual-APIC page offset that caused this
3860 * VM-exit.
3861 */
3862IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3863{
3864 Assert(offApic < XAPIC_OFF_END + 4);
3865 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3866 offApic &= UINT16_C(0xfff);
3867 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3868}
3869
3870
3871/**
3872 * Sets virtual-APIC write emulation as pending.
3873 *
3874 * @param pVCpu The cross context virtual CPU structure.
3875 * @param offApic The offset in the virtual-APIC page that was written.
3876 */
3877DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3878{
3879 Assert(offApic < XAPIC_OFF_END + 4);
3880
3881 /*
3882 * Record the currently updated APIC offset, as we need this later for figuring
3883 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3884 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3885 */
3886 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3887
3888 /*
3889 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3890 * virtualization or APIC-write emulation).
3891 */
3892 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3893 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3894}
3895
3896
3897/**
3898 * Clears any pending virtual-APIC write emulation.
3899 *
3900 * @returns The virtual-APIC offset that was written before clearing it.
3901 * @param pVCpu The cross context virtual CPU structure.
3902 */
3903DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3904{
3905 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3906 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3907 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3908 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3909 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3910 return offVirtApicWrite;
3911}
3912
3913
3914/**
3915 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3916 *
3917 * @returns The register from the virtual-APIC page.
3918 * @param pVCpu The cross context virtual CPU structure.
3919 * @param offReg The offset of the register being read.
3920 */
3921IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3922{
3923 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3924
3925 uint32_t uReg = 0;
3926 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3927 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3928 AssertMsgStmt(RT_SUCCESS(rc),
3929 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3930 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3931 uReg = 0);
3932 return uReg;
3933}
3934
3935
3936/**
3937 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3938 *
3939 * @returns The register from the virtual-APIC page.
3940 * @param pVCpu The cross context virtual CPU structure.
3941 * @param offReg The offset of the register being read.
3942 */
3943IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3944{
3945 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3946
3947 uint64_t uReg = 0;
3948 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3949 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3950 AssertMsgStmt(RT_SUCCESS(rc),
3951 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3952 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3953 uReg = 0);
3954 return uReg;
3955}
3956
3957
3958/**
3959 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3960 *
3961 * @param pVCpu The cross context virtual CPU structure.
3962 * @param offReg The offset of the register being written.
3963 * @param uReg The register value to write.
3964 */
3965IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3966{
3967 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3968
3969 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3970 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3971 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3972 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3973}
3974
3975
3976/**
3977 * Writes a 64-bit register to the virtual-APIC page at the given offset.
3978 *
3979 * @param pVCpu The cross context virtual CPU structure.
3980 * @param offReg The offset of the register being written.
3981 * @param uReg The register value to write.
3982 */
3983IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
3984{
3985 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3986
3987 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3988 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3989 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3990 sizeof(uReg), offReg, GCPhysVirtApic, rc));
3991}
3992
3993
3994/**
3995 * Sets the vector in a virtual-APIC 256-bit sparse register.
3996 *
3997 * @param pVCpu The cross context virtual CPU structure.
3998 * @param offReg The offset of the 256-bit spare register.
3999 * @param uVector The vector to set.
4000 *
4001 * @remarks This is based on our APIC device code.
4002 */
4003IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
4004{
4005 /* Determine the vector offset within the chunk. */
4006 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4007
4008 /* Read the chunk at the offset. */
4009 uint32_t uReg;
4010 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4011 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4012 if (RT_SUCCESS(rc))
4013 {
4014 /* Modify the chunk. */
4015 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4016 uReg |= RT_BIT(idxVectorBit);
4017
4018 /* Write the chunk. */
4019 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4020 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4021 uVector, offReg, GCPhysVirtApic, rc));
4022 }
4023 else
4024 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4025 uVector, offReg, GCPhysVirtApic, rc));
4026}
4027
4028
4029/**
4030 * Clears the vector in a virtual-APIC 256-bit sparse register.
4031 *
4032 * @param pVCpu The cross context virtual CPU structure.
4033 * @param offReg The offset of the 256-bit spare register.
4034 * @param uVector The vector to clear.
4035 *
4036 * @remarks This is based on our APIC device code.
4037 */
4038IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
4039{
4040 /* Determine the vector offset within the chunk. */
4041 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4042
4043 /* Read the chunk at the offset. */
4044 uint32_t uReg;
4045 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4046 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4047 if (RT_SUCCESS(rc))
4048 {
4049 /* Modify the chunk. */
4050 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4051 uReg &= ~RT_BIT(idxVectorBit);
4052
4053 /* Write the chunk. */
4054 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4055 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4056 uVector, offReg, GCPhysVirtApic, rc));
4057 }
4058 else
4059 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4060 uVector, offReg, GCPhysVirtApic, rc));
4061}
4062
4063
4064/**
4065 * Checks if a memory access to the APIC-access page must causes an APIC-access
4066 * VM-exit.
4067 *
4068 * @param pVCpu The cross context virtual CPU structure.
4069 * @param offAccess The offset of the register being accessed.
4070 * @param cbAccess The size of the access in bytes.
4071 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4072 * IEM_ACCESS_TYPE_WRITE).
4073 *
4074 * @remarks This must not be used for MSR-based APIC-access page accesses!
4075 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4076 */
4077IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4078{
4079 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4080 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4081
4082 /*
4083 * We must cause a VM-exit if any of the following are true:
4084 * - TPR shadowing isn't active.
4085 * - The access size exceeds 32-bits.
4086 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4087 *
4088 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4089 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4090 */
4091 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4092 || cbAccess > sizeof(uint32_t)
4093 || ((offAccess + cbAccess - 1) & 0xc)
4094 || offAccess >= XAPIC_OFF_END + 4)
4095 return true;
4096
4097 /*
4098 * If the access is part of an operation where we have already
4099 * virtualized a virtual-APIC write, we must cause a VM-exit.
4100 */
4101 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4102 return true;
4103
4104 /*
4105 * Check write accesses to the APIC-access page that cause VM-exits.
4106 */
4107 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4108 {
4109 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4110 {
4111 /*
4112 * With APIC-register virtualization, a write access to any of the
4113 * following registers are virtualized. Accessing any other register
4114 * causes a VM-exit.
4115 */
4116 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4117 switch (offAlignedAccess)
4118 {
4119 case XAPIC_OFF_ID:
4120 case XAPIC_OFF_TPR:
4121 case XAPIC_OFF_EOI:
4122 case XAPIC_OFF_LDR:
4123 case XAPIC_OFF_DFR:
4124 case XAPIC_OFF_SVR:
4125 case XAPIC_OFF_ESR:
4126 case XAPIC_OFF_ICR_LO:
4127 case XAPIC_OFF_ICR_HI:
4128 case XAPIC_OFF_LVT_TIMER:
4129 case XAPIC_OFF_LVT_THERMAL:
4130 case XAPIC_OFF_LVT_PERF:
4131 case XAPIC_OFF_LVT_LINT0:
4132 case XAPIC_OFF_LVT_LINT1:
4133 case XAPIC_OFF_LVT_ERROR:
4134 case XAPIC_OFF_TIMER_ICR:
4135 case XAPIC_OFF_TIMER_DCR:
4136 break;
4137 default:
4138 return true;
4139 }
4140 }
4141 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4142 {
4143 /*
4144 * With virtual-interrupt delivery, a write access to any of the
4145 * following registers are virtualized. Accessing any other register
4146 * causes a VM-exit.
4147 *
4148 * Note! The specification does not allow writing to offsets in-between
4149 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4150 */
4151 switch (offAccess)
4152 {
4153 case XAPIC_OFF_TPR:
4154 case XAPIC_OFF_EOI:
4155 case XAPIC_OFF_ICR_LO:
4156 break;
4157 default:
4158 return true;
4159 }
4160 }
4161 else
4162 {
4163 /*
4164 * Without APIC-register virtualization or virtual-interrupt delivery,
4165 * only TPR accesses are virtualized.
4166 */
4167 if (offAccess == XAPIC_OFF_TPR)
4168 { /* likely */ }
4169 else
4170 return true;
4171 }
4172 }
4173 else
4174 {
4175 /*
4176 * Check read accesses to the APIC-access page that cause VM-exits.
4177 */
4178 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4179 {
4180 /*
4181 * With APIC-register virtualization, a read access to any of the
4182 * following registers are virtualized. Accessing any other register
4183 * causes a VM-exit.
4184 */
4185 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4186 switch (offAlignedAccess)
4187 {
4188 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4189 case XAPIC_OFF_ID:
4190 case XAPIC_OFF_VERSION:
4191 case XAPIC_OFF_TPR:
4192 case XAPIC_OFF_EOI:
4193 case XAPIC_OFF_LDR:
4194 case XAPIC_OFF_DFR:
4195 case XAPIC_OFF_SVR:
4196 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4197 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4198 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4199 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4200 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4201 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4202 case XAPIC_OFF_ESR:
4203 case XAPIC_OFF_ICR_LO:
4204 case XAPIC_OFF_ICR_HI:
4205 case XAPIC_OFF_LVT_TIMER:
4206 case XAPIC_OFF_LVT_THERMAL:
4207 case XAPIC_OFF_LVT_PERF:
4208 case XAPIC_OFF_LVT_LINT0:
4209 case XAPIC_OFF_LVT_LINT1:
4210 case XAPIC_OFF_LVT_ERROR:
4211 case XAPIC_OFF_TIMER_ICR:
4212 case XAPIC_OFF_TIMER_DCR:
4213 break;
4214 default:
4215 return true;
4216 }
4217 }
4218 else
4219 {
4220 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4221 if (offAccess == XAPIC_OFF_TPR)
4222 { /* likely */ }
4223 else
4224 return true;
4225 }
4226 }
4227
4228 /* The APIC access is virtualized, does not cause a VM-exit. */
4229 return false;
4230}
4231
4232
4233/**
4234 * Virtualizes a memory-based APIC access where the address is not used to access
4235 * memory.
4236 *
4237 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4238 * page-faults but do not use the address to access memory.
4239 *
4240 * @param pVCpu The cross context virtual CPU structure.
4241 * @param pGCPhysAccess Pointer to the guest-physical address used.
4242 */
4243IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4244{
4245 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4246 Assert(pGCPhysAccess);
4247
4248 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4249 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4250 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4251
4252 if (GCPhysAccess == GCPhysApic)
4253 {
4254 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4255 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4256 uint16_t const cbAccess = 1;
4257 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4258 if (fIntercept)
4259 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4260
4261 *pGCPhysAccess = GCPhysApic | offAccess;
4262 return VINF_VMX_MODIFIES_BEHAVIOR;
4263 }
4264
4265 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4266}
4267
4268
4269/**
4270 * Virtualizes a memory-based APIC access.
4271 *
4272 * @returns VBox strict status code.
4273 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4274 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4275 *
4276 * @param pVCpu The cross context virtual CPU structure.
4277 * @param offAccess The offset of the register being accessed (within the
4278 * APIC-access page).
4279 * @param cbAccess The size of the access in bytes.
4280 * @param pvData Pointer to the data being written or where to store the data
4281 * being read.
4282 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4283 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4284 */
4285IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4286 uint32_t fAccess)
4287{
4288 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4289 Assert(pvData);
4290 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4291 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4292 || (fAccess & IEM_ACCESS_INSTRUCTION));
4293
4294 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4295 if (fIntercept)
4296 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4297
4298 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4299 {
4300 /*
4301 * A write access to the APIC-access page that is virtualized (rather than
4302 * causing a VM-exit) writes data to the virtual-APIC page.
4303 */
4304 uint32_t const u32Data = *(uint32_t *)pvData;
4305 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4306
4307 /*
4308 * Record the currently updated APIC offset, as we need this later for figuring
4309 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4310 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4311 *
4312 * After completion of the current operation, we need to perform TPR virtualization,
4313 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4314 *
4315 * The current operation may be a REP-prefixed string instruction, execution of any
4316 * other instruction, or delivery of an event through the IDT.
4317 *
4318 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4319 * performed now but later after completion of the current operation.
4320 *
4321 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4322 */
4323 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4324 }
4325 else
4326 {
4327 /*
4328 * A read access from the APIC-access page that is virtualized (rather than
4329 * causing a VM-exit) returns data from the virtual-APIC page.
4330 *
4331 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4332 */
4333 Assert(cbAccess <= 4);
4334 Assert(offAccess < XAPIC_OFF_END + 4);
4335 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4336
4337 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4338 u32Data &= s_auAccessSizeMasks[cbAccess];
4339 *(uint32_t *)pvData = u32Data;
4340 }
4341
4342 return VINF_VMX_MODIFIES_BEHAVIOR;
4343}
4344
4345
4346/**
4347 * Virtualizes an MSR-based APIC read access.
4348 *
4349 * @returns VBox strict status code.
4350 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4351 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4352 * handled by the x2APIC device.
4353 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4354 * not within the range of valid MSRs, caller must raise \#GP(0).
4355 * @param pVCpu The cross context virtual CPU structure.
4356 * @param idMsr The x2APIC MSR being read.
4357 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4358 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4359 */
4360IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4361{
4362 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4363 Assert(pu64Value);
4364
4365 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4366 {
4367 if ( idMsr >= MSR_IA32_X2APIC_START
4368 && idMsr <= MSR_IA32_X2APIC_END)
4369 {
4370 uint16_t const offReg = (idMsr & 0xff) << 4;
4371 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4372 *pu64Value = u64Value;
4373 return VINF_VMX_MODIFIES_BEHAVIOR;
4374 }
4375 return VERR_OUT_OF_RANGE;
4376 }
4377
4378 if (idMsr == MSR_IA32_X2APIC_TPR)
4379 {
4380 uint16_t const offReg = (idMsr & 0xff) << 4;
4381 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4382 *pu64Value = u64Value;
4383 return VINF_VMX_MODIFIES_BEHAVIOR;
4384 }
4385
4386 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4387}
4388
4389
4390/**
4391 * Virtualizes an MSR-based APIC write access.
4392 *
4393 * @returns VBox strict status code.
4394 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4395 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4396 * not within the range of valid MSRs, caller must raise \#GP(0).
4397 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4398 *
4399 * @param pVCpu The cross context virtual CPU structure.
4400 * @param idMsr The x2APIC MSR being written.
4401 * @param u64Value The value of the x2APIC MSR being written.
4402 */
4403IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4404{
4405 /*
4406 * Check if the access is to be virtualized.
4407 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4408 */
4409 if ( idMsr == MSR_IA32_X2APIC_TPR
4410 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4411 && ( idMsr == MSR_IA32_X2APIC_EOI
4412 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4413 {
4414 /* Validate the MSR write depending on the register. */
4415 switch (idMsr)
4416 {
4417 case MSR_IA32_X2APIC_TPR:
4418 case MSR_IA32_X2APIC_SELF_IPI:
4419 {
4420 if (u64Value & UINT64_C(0xffffffffffffff00))
4421 return VERR_OUT_OF_RANGE;
4422 break;
4423 }
4424 case MSR_IA32_X2APIC_EOI:
4425 {
4426 if (u64Value != 0)
4427 return VERR_OUT_OF_RANGE;
4428 break;
4429 }
4430 }
4431
4432 /* Write the MSR to the virtual-APIC page. */
4433 uint16_t const offReg = (idMsr & 0xff) << 4;
4434 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4435
4436 /*
4437 * Record the currently updated APIC offset, as we need this later for figuring
4438 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4439 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4440 */
4441 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4442
4443 return VINF_VMX_MODIFIES_BEHAVIOR;
4444 }
4445
4446 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4447}
4448
4449
4450/**
4451 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4452 *
4453 * @returns VBox status code.
4454 * @retval VINF_SUCCESS when the highest set bit is found.
4455 * @retval VERR_NOT_FOUND when no bit is set.
4456 *
4457 * @param pVCpu The cross context virtual CPU structure.
4458 * @param offReg The offset of the APIC 256-bit sparse register.
4459 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4460 * set in the register. Only valid when VINF_SUCCESS is
4461 * returned.
4462 *
4463 * @remarks The format of the 256-bit sparse register here mirrors that found in
4464 * real APIC hardware.
4465 */
4466static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4467{
4468 Assert(offReg < XAPIC_OFF_END + 4);
4469 Assert(pidxHighestBit);
4470
4471 /*
4472 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4473 * However, in each fragment only the first 4 bytes are used.
4474 */
4475 uint8_t const cFrags = 8;
4476 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4477 {
4478 uint16_t const offFrag = iFrag * 16;
4479 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4480 if (!u32Frag)
4481 continue;
4482
4483 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4484 Assert(idxHighestBit > 0);
4485 --idxHighestBit;
4486 Assert(idxHighestBit <= UINT8_MAX);
4487 *pidxHighestBit = idxHighestBit;
4488 return VINF_SUCCESS;
4489 }
4490 return VERR_NOT_FOUND;
4491}
4492
4493
4494/**
4495 * Evaluates pending virtual interrupts.
4496 *
4497 * @param pVCpu The cross context virtual CPU structure.
4498 */
4499IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4500{
4501 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4502
4503 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4504 {
4505 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4506 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4507
4508 if ((uRvi >> 4) > (uPpr >> 4))
4509 {
4510 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4511 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4512 }
4513 else
4514 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4515 }
4516}
4517
4518
4519/**
4520 * Performs PPR virtualization.
4521 *
4522 * @returns VBox strict status code.
4523 * @param pVCpu The cross context virtual CPU structure.
4524 */
4525IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4526{
4527 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4528 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4529
4530 /*
4531 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4532 * or EOI-virtualization.
4533 *
4534 * See Intel spec. 29.1.3 "PPR Virtualization".
4535 */
4536 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4537 uint32_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4538
4539 uint32_t uPpr;
4540 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4541 uPpr = uTpr & 0xff;
4542 else
4543 uPpr = uSvi & 0xf0;
4544
4545 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4546 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4547}
4548
4549
4550/**
4551 * Performs VMX TPR virtualization.
4552 *
4553 * @returns VBox strict status code.
4554 * @param pVCpu The cross context virtual CPU structure.
4555 */
4556IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4557{
4558 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4559
4560 /*
4561 * We should have already performed the virtual-APIC write to the TPR offset
4562 * in the virtual-APIC page. We now perform TPR virtualization.
4563 *
4564 * See Intel spec. 29.1.2 "TPR Virtualization".
4565 */
4566 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4567 {
4568 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4569 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4570
4571 /*
4572 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4573 * See Intel spec. 29.1.2 "TPR Virtualization".
4574 */
4575 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4576 {
4577 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4578 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4579 }
4580 }
4581 else
4582 {
4583 iemVmxPprVirtualization(pVCpu);
4584 iemVmxEvalPendingVirtIntrs(pVCpu);
4585 }
4586
4587 return VINF_SUCCESS;
4588}
4589
4590
4591/**
4592 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4593 * not.
4594 *
4595 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4596 * @param pVCpu The cross context virtual CPU structure.
4597 * @param uVector The interrupt that was acknowledged using an EOI.
4598 */
4599IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4600{
4601 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4602 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4603
4604 if (uVector < 64)
4605 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4606 if (uVector < 128)
4607 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4608 if (uVector < 192)
4609 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4610 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4611}
4612
4613
4614/**
4615 * Performs EOI virtualization.
4616 *
4617 * @returns VBox strict status code.
4618 * @param pVCpu The cross context virtual CPU structure.
4619 */
4620IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4621{
4622 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4623 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4624
4625 /*
4626 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4627 * and get the next guest-interrupt that's in-service (if any).
4628 *
4629 * See Intel spec. 29.1.4 "EOI Virtualization".
4630 */
4631 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4632 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4633 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4634
4635 uint8_t uVector = uSvi;
4636 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4637
4638 uVector = 0;
4639 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4640
4641 if (uVector)
4642 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4643 else
4644 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4645
4646 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4647 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4648
4649 iemVmxPprVirtualization(pVCpu);
4650 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4651 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4652 iemVmxEvalPendingVirtIntrs(pVCpu);
4653 return VINF_SUCCESS;
4654}
4655
4656
4657/**
4658 * Performs self-IPI virtualization.
4659 *
4660 * @returns VBox strict status code.
4661 * @param pVCpu The cross context virtual CPU structure.
4662 */
4663IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4664{
4665 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4666 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4667
4668 /*
4669 * We should have already performed the virtual-APIC write to the self-IPI offset
4670 * in the virtual-APIC page. We now perform self-IPI virtualization.
4671 *
4672 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4673 */
4674 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4675 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4676 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4677 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4678 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4679 if (uVector > uRvi)
4680 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4681 iemVmxEvalPendingVirtIntrs(pVCpu);
4682 return VINF_SUCCESS;
4683}
4684
4685
4686/**
4687 * Performs VMX APIC-write emulation.
4688 *
4689 * @returns VBox strict status code.
4690 * @param pVCpu The cross context virtual CPU structure.
4691 */
4692IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4693{
4694 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4695
4696 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4697 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4698
4699 /*
4700 * Perform APIC-write emulation based on the virtual-APIC register written.
4701 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4702 */
4703 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4704 VBOXSTRICTRC rcStrict;
4705 switch (offApicWrite)
4706 {
4707 case XAPIC_OFF_TPR:
4708 {
4709 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4710 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4711 uTpr &= UINT32_C(0x000000ff);
4712 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4713 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4714 rcStrict = iemVmxTprVirtualization(pVCpu);
4715 break;
4716 }
4717
4718 case XAPIC_OFF_EOI:
4719 {
4720 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4721 {
4722 /* Clear VEOI and perform EOI virtualization. */
4723 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4724 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4725 rcStrict = iemVmxEoiVirtualization(pVCpu);
4726 }
4727 else
4728 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4729 break;
4730 }
4731
4732 case XAPIC_OFF_ICR_LO:
4733 {
4734 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4735 {
4736 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4737 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4738 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4739 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4740 if ( !(uIcrLo & fIcrLoMb0)
4741 && (uIcrLo & fIcrLoMb1))
4742 {
4743 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4744 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4745 }
4746 else
4747 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4748 }
4749 else
4750 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4751 break;
4752 }
4753
4754 case XAPIC_OFF_ICR_HI:
4755 {
4756 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4757 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4758 uIcrHi &= UINT32_C(0xff000000);
4759 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4760 rcStrict = VINF_SUCCESS;
4761 break;
4762 }
4763
4764 default:
4765 {
4766 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4767 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4768 break;
4769 }
4770 }
4771
4772 return rcStrict;
4773}
4774
4775
4776/**
4777 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4778 *
4779 * @param pVCpu The cross context virtual CPU structure.
4780 * @param pszInstr The VMX instruction name (for logging purposes).
4781 */
4782DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4783{
4784 /*
4785 * Guest Control Registers, Debug Registers, and MSRs.
4786 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4787 */
4788 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4789 const char * const pszFailure = "VM-exit";
4790 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4791
4792 /* CR0 reserved bits. */
4793 {
4794 /* CR0 MB1 bits. */
4795 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
4796 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
4797 if (fUnrestrictedGuest)
4798 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4799 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4800 { /* likely */ }
4801 else
4802 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4803
4804 /* CR0 MBZ bits. */
4805 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4806 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4807 { /* likely */ }
4808 else
4809 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4810
4811 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4812 if ( !fUnrestrictedGuest
4813 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4814 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4815 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4816 }
4817
4818 /* CR4 reserved bits. */
4819 {
4820 /* CR4 MB1 bits. */
4821 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4822 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4823 { /* likely */ }
4824 else
4825 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4826
4827 /* CR4 MBZ bits. */
4828 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4829 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4830 { /* likely */ }
4831 else
4832 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4833 }
4834
4835 /* DEBUGCTL MSR. */
4836 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4837 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4838 { /* likely */ }
4839 else
4840 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4841
4842 /* 64-bit CPU checks. */
4843 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4844 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4845 {
4846 if (fGstInLongMode)
4847 {
4848 /* PAE must be set. */
4849 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4850 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4851 { /* likely */ }
4852 else
4853 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4854 }
4855 else
4856 {
4857 /* PCIDE should not be set. */
4858 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4859 { /* likely */ }
4860 else
4861 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4862 }
4863
4864 /* CR3. */
4865 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4866 { /* likely */ }
4867 else
4868 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4869
4870 /* DR7. */
4871 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4872 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4873 { /* likely */ }
4874 else
4875 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4876
4877 /* SYSENTER ESP and SYSENTER EIP. */
4878 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4879 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4880 { /* likely */ }
4881 else
4882 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4883 }
4884
4885 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4886 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4887
4888 /* PAT MSR. */
4889 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4890 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4891 { /* likely */ }
4892 else
4893 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4894
4895 /* EFER MSR. */
4896 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4897 {
4898 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4899 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4900 { /* likely */ }
4901 else
4902 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4903
4904 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4905 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4906 if ( fGstLma == fGstInLongMode
4907 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4908 || fGstLma == fGstLme))
4909 { /* likely */ }
4910 else
4911 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4912 }
4913
4914 /* We don't support IA32_BNDCFGS MSR yet. */
4915 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4916
4917 NOREF(pszInstr);
4918 NOREF(pszFailure);
4919 return VINF_SUCCESS;
4920}
4921
4922
4923/**
4924 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4925 *
4926 * @param pVCpu The cross context virtual CPU structure.
4927 * @param pszInstr The VMX instruction name (for logging purposes).
4928 */
4929DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4930{
4931 /*
4932 * Segment registers.
4933 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4934 */
4935 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4936 const char * const pszFailure = "VM-exit";
4937 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4938 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4939 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4940
4941 /* Selectors. */
4942 if ( !fGstInV86Mode
4943 && !fUnrestrictedGuest
4944 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4945 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4946
4947 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4948 {
4949 CPUMSELREG SelReg;
4950 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4951 if (RT_LIKELY(rc == VINF_SUCCESS))
4952 { /* likely */ }
4953 else
4954 return rc;
4955
4956 /*
4957 * Virtual-8086 mode checks.
4958 */
4959 if (fGstInV86Mode)
4960 {
4961 /* Base address. */
4962 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4963 { /* likely */ }
4964 else
4965 {
4966 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4967 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4968 }
4969
4970 /* Limit. */
4971 if (SelReg.u32Limit == 0xffff)
4972 { /* likely */ }
4973 else
4974 {
4975 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
4976 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4977 }
4978
4979 /* Attribute. */
4980 if (SelReg.Attr.u == 0xf3)
4981 { /* likely */ }
4982 else
4983 {
4984 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
4985 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4986 }
4987
4988 /* We're done; move to checking the next segment. */
4989 continue;
4990 }
4991
4992 /* Checks done by 64-bit CPUs. */
4993 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4994 {
4995 /* Base address. */
4996 if ( iSegReg == X86_SREG_FS
4997 || iSegReg == X86_SREG_GS)
4998 {
4999 if (X86_IS_CANONICAL(SelReg.u64Base))
5000 { /* likely */ }
5001 else
5002 {
5003 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5004 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5005 }
5006 }
5007 else if (iSegReg == X86_SREG_CS)
5008 {
5009 if (!RT_HI_U32(SelReg.u64Base))
5010 { /* likely */ }
5011 else
5012 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5013 }
5014 else
5015 {
5016 if ( SelReg.Attr.n.u1Unusable
5017 || !RT_HI_U32(SelReg.u64Base))
5018 { /* likely */ }
5019 else
5020 {
5021 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5022 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5023 }
5024 }
5025 }
5026
5027 /*
5028 * Checks outside Virtual-8086 mode.
5029 */
5030 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5031 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5032 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5033 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5034 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5035 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5036 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5037 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5038
5039 /* Code or usable segment. */
5040 if ( iSegReg == X86_SREG_CS
5041 || fUsable)
5042 {
5043 /* Reserved bits (bits 31:17 and bits 11:8). */
5044 if (!(SelReg.Attr.u & 0xfffe0f00))
5045 { /* likely */ }
5046 else
5047 {
5048 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5049 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5050 }
5051
5052 /* Descriptor type. */
5053 if (fCodeDataSeg)
5054 { /* likely */ }
5055 else
5056 {
5057 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5058 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5059 }
5060
5061 /* Present. */
5062 if (fPresent)
5063 { /* likely */ }
5064 else
5065 {
5066 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5067 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5068 }
5069
5070 /* Granularity. */
5071 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5072 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5073 { /* likely */ }
5074 else
5075 {
5076 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5077 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5078 }
5079 }
5080
5081 if (iSegReg == X86_SREG_CS)
5082 {
5083 /* Segment Type and DPL. */
5084 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5085 && fUnrestrictedGuest)
5086 {
5087 if (uDpl == 0)
5088 { /* likely */ }
5089 else
5090 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5091 }
5092 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5093 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5094 {
5095 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5096 if (uDpl == AttrSs.n.u2Dpl)
5097 { /* likely */ }
5098 else
5099 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5100 }
5101 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5102 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5103 {
5104 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5105 if (uDpl <= AttrSs.n.u2Dpl)
5106 { /* likely */ }
5107 else
5108 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5109 }
5110 else
5111 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5112
5113 /* Def/Big. */
5114 if ( fGstInLongMode
5115 && fSegLong)
5116 {
5117 if (uDefBig == 0)
5118 { /* likely */ }
5119 else
5120 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5121 }
5122 }
5123 else if (iSegReg == X86_SREG_SS)
5124 {
5125 /* Segment Type. */
5126 if ( !fUsable
5127 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5128 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5129 { /* likely */ }
5130 else
5131 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5132
5133 /* DPL. */
5134 if (!fUnrestrictedGuest)
5135 {
5136 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5137 { /* likely */ }
5138 else
5139 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5140 }
5141 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5142 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5143 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5144 {
5145 if (uDpl == 0)
5146 { /* likely */ }
5147 else
5148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5149 }
5150 }
5151 else
5152 {
5153 /* DS, ES, FS, GS. */
5154 if (fUsable)
5155 {
5156 /* Segment type. */
5157 if (uSegType & X86_SEL_TYPE_ACCESSED)
5158 { /* likely */ }
5159 else
5160 {
5161 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5162 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5163 }
5164
5165 if ( !(uSegType & X86_SEL_TYPE_CODE)
5166 || (uSegType & X86_SEL_TYPE_READ))
5167 { /* likely */ }
5168 else
5169 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5170
5171 /* DPL. */
5172 if ( !fUnrestrictedGuest
5173 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5174 {
5175 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5176 { /* likely */ }
5177 else
5178 {
5179 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5180 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5181 }
5182 }
5183 }
5184 }
5185 }
5186
5187 /*
5188 * LDTR.
5189 */
5190 {
5191 CPUMSELREG Ldtr;
5192 Ldtr.Sel = pVmcs->GuestLdtr;
5193 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5194 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5195 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5196
5197 if (!Ldtr.Attr.n.u1Unusable)
5198 {
5199 /* Selector. */
5200 if (!(Ldtr.Sel & X86_SEL_LDT))
5201 { /* likely */ }
5202 else
5203 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5204
5205 /* Base. */
5206 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5207 {
5208 if (X86_IS_CANONICAL(Ldtr.u64Base))
5209 { /* likely */ }
5210 else
5211 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5212 }
5213
5214 /* Attributes. */
5215 /* Reserved bits (bits 31:17 and bits 11:8). */
5216 if (!(Ldtr.Attr.u & 0xfffe0f00))
5217 { /* likely */ }
5218 else
5219 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5220
5221 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5222 { /* likely */ }
5223 else
5224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5225
5226 if (!Ldtr.Attr.n.u1DescType)
5227 { /* likely */ }
5228 else
5229 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5230
5231 if (Ldtr.Attr.n.u1Present)
5232 { /* likely */ }
5233 else
5234 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5235
5236 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5237 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5238 { /* likely */ }
5239 else
5240 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5241 }
5242 }
5243
5244 /*
5245 * TR.
5246 */
5247 {
5248 CPUMSELREG Tr;
5249 Tr.Sel = pVmcs->GuestTr;
5250 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5251 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5252 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5253
5254 /* Selector. */
5255 if (!(Tr.Sel & X86_SEL_LDT))
5256 { /* likely */ }
5257 else
5258 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5259
5260 /* Base. */
5261 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5262 {
5263 if (X86_IS_CANONICAL(Tr.u64Base))
5264 { /* likely */ }
5265 else
5266 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5267 }
5268
5269 /* Attributes. */
5270 /* Reserved bits (bits 31:17 and bits 11:8). */
5271 if (!(Tr.Attr.u & 0xfffe0f00))
5272 { /* likely */ }
5273 else
5274 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5275
5276 if (!Tr.Attr.n.u1Unusable)
5277 { /* likely */ }
5278 else
5279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5280
5281 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5282 || ( !fGstInLongMode
5283 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5284 { /* likely */ }
5285 else
5286 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5287
5288 if (!Tr.Attr.n.u1DescType)
5289 { /* likely */ }
5290 else
5291 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5292
5293 if (Tr.Attr.n.u1Present)
5294 { /* likely */ }
5295 else
5296 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5297
5298 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5299 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5300 { /* likely */ }
5301 else
5302 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5303 }
5304
5305 NOREF(pszInstr);
5306 NOREF(pszFailure);
5307 return VINF_SUCCESS;
5308}
5309
5310
5311/**
5312 * Checks guest GDTR and IDTR as part of VM-entry.
5313 *
5314 * @param pVCpu The cross context virtual CPU structure.
5315 * @param pszInstr The VMX instruction name (for logging purposes).
5316 */
5317DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5318{
5319 /*
5320 * GDTR and IDTR.
5321 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5322 */
5323 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5324 const char *const pszFailure = "VM-exit";
5325
5326 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5327 {
5328 /* Base. */
5329 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5330 { /* likely */ }
5331 else
5332 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5333
5334 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5335 { /* likely */ }
5336 else
5337 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5338 }
5339
5340 /* Limit. */
5341 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5342 { /* likely */ }
5343 else
5344 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5345
5346 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5347 { /* likely */ }
5348 else
5349 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5350
5351 NOREF(pszInstr);
5352 NOREF(pszFailure);
5353 return VINF_SUCCESS;
5354}
5355
5356
5357/**
5358 * Checks guest RIP and RFLAGS as part of VM-entry.
5359 *
5360 * @param pVCpu The cross context virtual CPU structure.
5361 * @param pszInstr The VMX instruction name (for logging purposes).
5362 */
5363DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5364{
5365 /*
5366 * RIP and RFLAGS.
5367 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5368 */
5369 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5370 const char *const pszFailure = "VM-exit";
5371 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5372
5373 /* RIP. */
5374 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5375 {
5376 X86DESCATTR AttrCs;
5377 AttrCs.u = pVmcs->u32GuestCsAttr;
5378 if ( !fGstInLongMode
5379 || !AttrCs.n.u1Long)
5380 {
5381 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5382 { /* likely */ }
5383 else
5384 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5385 }
5386
5387 if ( fGstInLongMode
5388 && AttrCs.n.u1Long)
5389 {
5390 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5391 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5392 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5393 { /* likely */ }
5394 else
5395 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5396 }
5397 }
5398
5399 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5400 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5401 : pVmcs->u64GuestRFlags.s.Lo;
5402 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5403 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5404 { /* likely */ }
5405 else
5406 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5407
5408 if ( fGstInLongMode
5409 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5410 {
5411 if (!(uGuestRFlags & X86_EFL_VM))
5412 { /* likely */ }
5413 else
5414 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5415 }
5416
5417 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5418 {
5419 if (uGuestRFlags & X86_EFL_IF)
5420 { /* likely */ }
5421 else
5422 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5423 }
5424
5425 NOREF(pszInstr);
5426 NOREF(pszFailure);
5427 return VINF_SUCCESS;
5428}
5429
5430
5431/**
5432 * Checks guest non-register state as part of VM-entry.
5433 *
5434 * @param pVCpu The cross context virtual CPU structure.
5435 * @param pszInstr The VMX instruction name (for logging purposes).
5436 */
5437DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5438{
5439 /*
5440 * Guest non-register state.
5441 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5442 */
5443 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5444 const char *const pszFailure = "VM-exit";
5445
5446 /*
5447 * Activity state.
5448 */
5449 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5450 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5451 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5452 { /* likely */ }
5453 else
5454 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5455
5456 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5457 if ( !AttrSs.n.u2Dpl
5458 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5459 { /* likely */ }
5460 else
5461 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5462
5463 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5464 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5465 {
5466 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5467 { /* likely */ }
5468 else
5469 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5470 }
5471
5472 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5473 {
5474 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5475 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5476 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5477 switch (pVmcs->u32GuestActivityState)
5478 {
5479 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5480 {
5481 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5482 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5483 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5484 && ( uVector == X86_XCPT_DB
5485 || uVector == X86_XCPT_MC))
5486 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5487 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5488 { /* likely */ }
5489 else
5490 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5491 break;
5492 }
5493
5494 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5495 {
5496 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5497 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5498 && uVector == X86_XCPT_MC))
5499 { /* likely */ }
5500 else
5501 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5502 break;
5503 }
5504
5505 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5506 default:
5507 break;
5508 }
5509 }
5510
5511 /*
5512 * Interruptibility state.
5513 */
5514 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5515 { /* likely */ }
5516 else
5517 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5518
5519 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5520 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5521 { /* likely */ }
5522 else
5523 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5524
5525 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5526 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5527 { /* likely */ }
5528 else
5529 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5530
5531 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5532 {
5533 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5534 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5535 {
5536 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5537 { /* likely */ }
5538 else
5539 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5540 }
5541 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5542 {
5543 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5544 { /* likely */ }
5545 else
5546 {
5547 /*
5548 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5549 * We update the Exit qualification only when blocking-by-STI is set
5550 * without blocking-by-MovSS being set. Although in practise it does not
5551 * make much difference since the order of checks are implementation defined.
5552 */
5553 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5554 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5555 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5556 }
5557
5558 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5559 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5560 { /* likely */ }
5561 else
5562 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5563 }
5564 }
5565
5566 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5567 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5568 { /* likely */ }
5569 else
5570 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5571
5572 /* We don't support SGX yet. So enclave-interruption must not be set. */
5573 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5574 { /* likely */ }
5575 else
5576 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5577
5578 /*
5579 * Pending debug exceptions.
5580 */
5581 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5582 ? pVmcs->u64GuestPendingDbgXcpts.u
5583 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5584 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5585 { /* likely */ }
5586 else
5587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5588
5589 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5590 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5591 {
5592 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5593 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5594 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5595 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5596
5597 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5598 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5599 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5600 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5601 }
5602
5603 /* We don't support RTM (Real-time Transactional Memory) yet. */
5604 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5605 { /* likely */ }
5606 else
5607 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5608
5609 /*
5610 * VMCS link pointer.
5611 */
5612 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5613 {
5614 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5615 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5616 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5617 { /* likely */ }
5618 else
5619 {
5620 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5621 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5622 }
5623
5624 /* Validate the address. */
5625 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5626 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5627 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5628 { /* likely */ }
5629 else
5630 {
5631 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5632 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5633 }
5634 }
5635
5636 NOREF(pszInstr);
5637 NOREF(pszFailure);
5638 return VINF_SUCCESS;
5639}
5640
5641
5642#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5643/**
5644 * Checks guest PDPTEs as part of VM-entry.
5645 *
5646 * @param pVCpu The cross context virtual CPU structure.
5647 * @param pszInstr The VMX instruction name (for logging purposes).
5648 */
5649IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr)
5650{
5651 /*
5652 * Guest PDPTEs.
5653 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5654 */
5655 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5656 const char * const pszFailure = "VM-exit";
5657
5658 /*
5659 * When EPT is used, we only validate the PAE PDPTEs provided in the VMCS.
5660 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
5661 */
5662 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
5663 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
5664 {
5665 /* Get PDPTEs from the VMCS. */
5666 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
5667 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
5668 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
5669 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
5670 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
5671
5672 /* Check validity of the PDPTEs. */
5673 bool const fValid = PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]);
5674 if (fValid)
5675 { /* likely */ }
5676 else
5677 {
5678 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5679 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5680 }
5681 }
5682
5683 NOREF(pszFailure);
5684 NOREF(pszInstr);
5685 return VINF_SUCCESS;
5686}
5687#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
5688
5689
5690/**
5691 * Checks guest-state as part of VM-entry.
5692 *
5693 * @returns VBox status code.
5694 * @param pVCpu The cross context virtual CPU structure.
5695 * @param pszInstr The VMX instruction name (for logging purposes).
5696 */
5697IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr)
5698{
5699 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5700 if (RT_SUCCESS(rc))
5701 {
5702 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5703 if (RT_SUCCESS(rc))
5704 {
5705 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5706 if (RT_SUCCESS(rc))
5707 {
5708 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5709 if (RT_SUCCESS(rc))
5710 {
5711 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5712#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5713 if (RT_SUCCESS(rc))
5714 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5715#endif
5716 }
5717 }
5718 }
5719 }
5720 return rc;
5721}
5722
5723
5724/**
5725 * Checks host-state as part of VM-entry.
5726 *
5727 * @returns VBox status code.
5728 * @param pVCpu The cross context virtual CPU structure.
5729 * @param pszInstr The VMX instruction name (for logging purposes).
5730 */
5731IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5732{
5733 /*
5734 * Host Control Registers and MSRs.
5735 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5736 */
5737 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5738 const char * const pszFailure = "VMFail";
5739
5740 /* CR0 reserved bits. */
5741 {
5742 /* CR0 MB1 bits. */
5743 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5744 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5745 { /* likely */ }
5746 else
5747 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5748
5749 /* CR0 MBZ bits. */
5750 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5751 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5752 { /* likely */ }
5753 else
5754 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5755 }
5756
5757 /* CR4 reserved bits. */
5758 {
5759 /* CR4 MB1 bits. */
5760 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5761 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5762 { /* likely */ }
5763 else
5764 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5765
5766 /* CR4 MBZ bits. */
5767 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5768 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5769 { /* likely */ }
5770 else
5771 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5772 }
5773
5774 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5775 {
5776 /* CR3 reserved bits. */
5777 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5778 { /* likely */ }
5779 else
5780 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5781
5782 /* SYSENTER ESP and SYSENTER EIP. */
5783 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5784 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5785 { /* likely */ }
5786 else
5787 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5788 }
5789
5790 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5791 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5792
5793 /* PAT MSR. */
5794 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5795 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5796 { /* likely */ }
5797 else
5798 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5799
5800 /* EFER MSR. */
5801 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5802 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5803 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5804 { /* likely */ }
5805 else
5806 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5807
5808 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5809 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5810 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5811 if ( fHostInLongMode == fHostLma
5812 && fHostInLongMode == fHostLme)
5813 { /* likely */ }
5814 else
5815 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5816
5817 /*
5818 * Host Segment and Descriptor-Table Registers.
5819 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5820 */
5821 /* Selector RPL and TI. */
5822 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5823 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5824 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5825 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5826 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5827 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5828 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5829 { /* likely */ }
5830 else
5831 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5832
5833 /* CS and TR selectors cannot be 0. */
5834 if ( pVmcs->HostCs
5835 && pVmcs->HostTr)
5836 { /* likely */ }
5837 else
5838 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5839
5840 /* SS cannot be 0 if 32-bit host. */
5841 if ( fHostInLongMode
5842 || pVmcs->HostSs)
5843 { /* likely */ }
5844 else
5845 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5846
5847 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5848 {
5849 /* FS, GS, GDTR, IDTR, TR base address. */
5850 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5851 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5852 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5853 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5854 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5855 { /* likely */ }
5856 else
5857 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5858 }
5859
5860 /*
5861 * Host address-space size for 64-bit CPUs.
5862 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5863 */
5864 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5865 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5866 {
5867 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5868
5869 /* Logical processor in IA-32e mode. */
5870 if (fCpuInLongMode)
5871 {
5872 if (fHostInLongMode)
5873 {
5874 /* PAE must be set. */
5875 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5876 { /* likely */ }
5877 else
5878 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5879
5880 /* RIP must be canonical. */
5881 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5882 { /* likely */ }
5883 else
5884 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5885 }
5886 else
5887 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5888 }
5889 else
5890 {
5891 /* Logical processor is outside IA-32e mode. */
5892 if ( !fGstInLongMode
5893 && !fHostInLongMode)
5894 {
5895 /* PCIDE should not be set. */
5896 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5897 { /* likely */ }
5898 else
5899 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5900
5901 /* The high 32-bits of RIP MBZ. */
5902 if (!pVmcs->u64HostRip.s.Hi)
5903 { /* likely */ }
5904 else
5905 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5906 }
5907 else
5908 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5909 }
5910 }
5911 else
5912 {
5913 /* Host address-space size for 32-bit CPUs. */
5914 if ( !fGstInLongMode
5915 && !fHostInLongMode)
5916 { /* likely */ }
5917 else
5918 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5919 }
5920
5921 NOREF(pszInstr);
5922 NOREF(pszFailure);
5923 return VINF_SUCCESS;
5924}
5925
5926
5927#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5928/**
5929 * Checks the EPT pointer VMCS field as part of VM-entry.
5930 *
5931 * @returns VBox status code.
5932 * @param pVCpu The cross context virtual CPU structure.
5933 * @param uEptPtr The EPT pointer to check.
5934 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
5935 * updated on success). Optional, can be NULL.
5936 */
5937IEM_STATIC int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr, VMXVDIAG *penmVmxDiag)
5938{
5939 VMXVDIAG enmVmxDiag;
5940
5941 /* Reserved bits. */
5942 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
5943 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
5944 if (uEptPtr & fValidMask)
5945 {
5946 /* Memory Type. */
5947 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
5948 uint8_t const fMemType = RT_BF_GET(uEptPtr, VMX_BF_EPTP_MEMTYPE);
5949 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
5950 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
5951 || ( fMemType == VMX_EPTP_MEMTYPE_UC
5952 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
5953 {
5954 /*
5955 * Page walk length (PML4).
5956 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
5957 * of 5 but that seems to be removed from the latest specs. leaving only PML4
5958 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
5959 */
5960 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
5961 if (RT_BF_GET(uEptPtr, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
5962 {
5963 /* Access and dirty bits support in EPT structures. */
5964 if ( !RT_BF_GET(uEptPtr, VMX_BF_EPTP_ACCESS_DIRTY)
5965 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
5966 return VINF_SUCCESS;
5967
5968 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
5969 }
5970 else
5971 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
5972 }
5973 else
5974 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
5975 }
5976 else
5977 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
5978
5979 if (penmVmxDiag)
5980 *penmVmxDiag = enmVmxDiag;
5981 return VERR_VMX_VMENTRY_FAILED;
5982}
5983#endif
5984
5985
5986/**
5987 * Checks VMCS controls fields as part of VM-entry.
5988 *
5989 * @returns VBox status code.
5990 * @param pVCpu The cross context virtual CPU structure.
5991 * @param pszInstr The VMX instruction name (for logging purposes).
5992 *
5993 * @remarks This may update secondary-processor based VM-execution control fields
5994 * in the current VMCS if necessary.
5995 */
5996IEM_STATIC int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr)
5997{
5998 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5999 const char * const pszFailure = "VMFail";
6000
6001 /*
6002 * VM-execution controls.
6003 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6004 */
6005 {
6006 /* Pin-based VM-execution controls. */
6007 {
6008 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6009 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6010 { /* likely */ }
6011 else
6012 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6013
6014 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6015 { /* likely */ }
6016 else
6017 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6018 }
6019
6020 /* Processor-based VM-execution controls. */
6021 {
6022 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6023 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6024 { /* likely */ }
6025 else
6026 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6027
6028 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6029 { /* likely */ }
6030 else
6031 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6032 }
6033
6034 /* Secondary processor-based VM-execution controls. */
6035 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6036 {
6037 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6038 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6039 { /* likely */ }
6040 else
6041 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6042
6043 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6044 { /* likely */ }
6045 else
6046 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6047 }
6048 else
6049 Assert(!pVmcs->u32ProcCtls2);
6050
6051 /* CR3-target count. */
6052 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6053 { /* likely */ }
6054 else
6055 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6056
6057 /* I/O bitmaps physical addresses. */
6058 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6059 {
6060 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6061 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6062 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6063 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6064 { /* likely */ }
6065 else
6066 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6067
6068 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6069 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6070 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6071 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6072 { /* likely */ }
6073 else
6074 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6075 }
6076
6077 /* MSR bitmap physical address. */
6078 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6079 {
6080 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6081 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6082 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6083 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6084 { /* likely */ }
6085 else
6086 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6087 }
6088
6089 /* TPR shadow related controls. */
6090 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6091 {
6092 /* Virtual-APIC page physical address. */
6093 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6094 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6095 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6096 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6097 { /* likely */ }
6098 else
6099 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6100
6101 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6102 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6103 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6104 { /* likely */ }
6105 else
6106 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6107
6108 /* The rest done XXX document */
6109 }
6110 else
6111 {
6112 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6113 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6114 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6115 { /* likely */ }
6116 else
6117 {
6118 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6119 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6120 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6121 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6122 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6124 }
6125 }
6126
6127 /* NMI exiting and virtual-NMIs. */
6128 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6129 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6130 { /* likely */ }
6131 else
6132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6133
6134 /* Virtual-NMIs and NMI-window exiting. */
6135 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6136 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6137 { /* likely */ }
6138 else
6139 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6140
6141 /* Virtualize APIC accesses. */
6142 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6143 {
6144 /* APIC-access physical address. */
6145 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6146 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6147 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6148 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6149 { /* likely */ }
6150 else
6151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6152
6153 /*
6154 * Disallow APIC-access page and virtual-APIC page from being the same address.
6155 * Note! This is not an Intel requirement, but one imposed by our implementation.
6156 */
6157 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6158 * redirecting accesses between the APIC-access page and the virtual-APIC
6159 * page. If any nested hypervisor requires this, we can implement it later. */
6160 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6161 {
6162 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6163 if (GCPhysVirtApic != GCPhysApicAccess)
6164 { /* likely */ }
6165 else
6166 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6167 }
6168 }
6169
6170 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6171 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6172 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6173 { /* likely */ }
6174 else
6175 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6176
6177 /* Virtual-interrupt delivery requires external interrupt exiting. */
6178 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6179 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6180 { /* likely */ }
6181 else
6182 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6183
6184 /* VPID. */
6185 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6186 || pVmcs->u16Vpid != 0)
6187 { /* likely */ }
6188 else
6189 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6190
6191#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6192 /* Extended-Page-Table Pointer (EPTP). */
6193 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6194 {
6195 VMXVDIAG enmVmxDiag;
6196 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, pVmcs->u64EptPtr.u, &enmVmxDiag);
6197 if (RT_SUCCESS(rc))
6198 { /* likely */ }
6199 else
6200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6201 }
6202#else
6203 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6204#endif
6205
6206 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6207 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6208 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6209 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6210 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6211 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6212 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6213
6214 /* VMCS shadowing. */
6215 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6216 {
6217 /* VMREAD-bitmap physical address. */
6218 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6219 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6220 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6221 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6222 { /* likely */ }
6223 else
6224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6225
6226 /* VMWRITE-bitmap physical address. */
6227 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6228 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6229 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6230 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6231 { /* likely */ }
6232 else
6233 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6234 }
6235 }
6236
6237 /*
6238 * VM-exit controls.
6239 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6240 */
6241 {
6242 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6243 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6244 { /* likely */ }
6245 else
6246 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6247
6248 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6249 { /* likely */ }
6250 else
6251 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6252
6253 /* Save preemption timer without activating it. */
6254 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6255 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6256 { /* likely */ }
6257 else
6258 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6259
6260 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6261 if (pVmcs->u32ExitMsrStoreCount)
6262 {
6263 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6264 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6265 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6266 { /* likely */ }
6267 else
6268 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6269 }
6270
6271 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6272 if (pVmcs->u32ExitMsrLoadCount)
6273 {
6274 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6275 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6276 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6277 { /* likely */ }
6278 else
6279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6280 }
6281 }
6282
6283 /*
6284 * VM-entry controls.
6285 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6286 */
6287 {
6288 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6289 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6290 { /* likely */ }
6291 else
6292 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6293
6294 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6295 { /* likely */ }
6296 else
6297 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6298
6299 /* Event injection. */
6300 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6301 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6302 {
6303 /* Type and vector. */
6304 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6305 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6306 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6307 if ( !uRsvd
6308 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6309 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6310 { /* likely */ }
6311 else
6312 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6313
6314 /* Exception error code. */
6315 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6316 {
6317 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6318 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6319 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6320 { /* likely */ }
6321 else
6322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6323
6324 /* Exceptions that provide an error code. */
6325 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6326 && ( uVector == X86_XCPT_DF
6327 || uVector == X86_XCPT_TS
6328 || uVector == X86_XCPT_NP
6329 || uVector == X86_XCPT_SS
6330 || uVector == X86_XCPT_GP
6331 || uVector == X86_XCPT_PF
6332 || uVector == X86_XCPT_AC))
6333 { /* likely */ }
6334 else
6335 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6336
6337 /* Exception error-code reserved bits. */
6338 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6339 { /* likely */ }
6340 else
6341 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6342
6343 /* Injecting a software interrupt, software exception or privileged software exception. */
6344 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6345 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6346 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6347 {
6348 /* Instruction length must be in the range 0-15. */
6349 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6350 { /* likely */ }
6351 else
6352 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6353
6354 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6355 if ( pVmcs->u32EntryInstrLen != 0
6356 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6357 { /* likely */ }
6358 else
6359 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6360 }
6361 }
6362 }
6363
6364 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6365 if (pVmcs->u32EntryMsrLoadCount)
6366 {
6367 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6368 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6369 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6370 { /* likely */ }
6371 else
6372 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6373 }
6374
6375 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6376 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6377 }
6378
6379 NOREF(pszInstr);
6380 NOREF(pszFailure);
6381 return VINF_SUCCESS;
6382}
6383
6384
6385/**
6386 * Loads the guest control registers, debug register and some MSRs as part of
6387 * VM-entry.
6388 *
6389 * @param pVCpu The cross context virtual CPU structure.
6390 */
6391IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6392{
6393 /*
6394 * Load guest control registers, debug registers and MSRs.
6395 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6396 */
6397 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6398
6399 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6400 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6401 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6402 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6403 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6404 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6405
6406 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6407 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6408
6409 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6410 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6411 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6412
6413 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6414 {
6415 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6416
6417 /* EFER MSR. */
6418 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6419 {
6420 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6421 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6422 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6423 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6424 if (fGstInLongMode)
6425 {
6426 /* If the nested-guest is in long mode, LMA and LME are both set. */
6427 Assert(fGstPaging);
6428 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6429 }
6430 else
6431 {
6432 /*
6433 * If the nested-guest is outside long mode:
6434 * - With paging: LMA is cleared, LME is cleared.
6435 * - Without paging: LMA is cleared, LME is left unmodified.
6436 */
6437 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6438 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6439 }
6440 }
6441 /* else: see below. */
6442 }
6443
6444 /* PAT MSR. */
6445 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6446 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6447
6448 /* EFER MSR. */
6449 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6450 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6451
6452 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6453 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6454
6455 /* We don't support IA32_BNDCFGS MSR yet. */
6456 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6457
6458 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6459}
6460
6461
6462/**
6463 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6464 *
6465 * @param pVCpu The cross context virtual CPU structure.
6466 */
6467IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6468{
6469 /*
6470 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6471 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6472 */
6473 /* CS, SS, ES, DS, FS, GS. */
6474 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6475 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6476 {
6477 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6478 CPUMSELREG VmcsSelReg;
6479 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6480 AssertRC(rc); NOREF(rc);
6481 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6482 {
6483 pGstSelReg->Sel = VmcsSelReg.Sel;
6484 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6485 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6486 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6487 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6488 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6489 }
6490 else
6491 {
6492 pGstSelReg->Sel = VmcsSelReg.Sel;
6493 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6494 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6495 switch (iSegReg)
6496 {
6497 case X86_SREG_CS:
6498 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6499 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6500 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6501 break;
6502
6503 case X86_SREG_SS:
6504 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6505 pGstSelReg->u32Limit = 0;
6506 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6507 break;
6508
6509 case X86_SREG_ES:
6510 case X86_SREG_DS:
6511 pGstSelReg->u64Base = 0;
6512 pGstSelReg->u32Limit = 0;
6513 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6514 break;
6515
6516 case X86_SREG_FS:
6517 case X86_SREG_GS:
6518 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6519 pGstSelReg->u32Limit = 0;
6520 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6521 break;
6522 }
6523 Assert(pGstSelReg->Attr.n.u1Unusable);
6524 }
6525 }
6526
6527 /* LDTR. */
6528 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6529 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6530 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6531 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6532 {
6533 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6534 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6535 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6536 }
6537 else
6538 {
6539 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6540 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6541 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6542 }
6543
6544 /* TR. */
6545 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6546 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6547 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6548 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6549 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6550 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6551 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6552
6553 /* GDTR. */
6554 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6555 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6556
6557 /* IDTR. */
6558 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6559 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6560}
6561
6562
6563/**
6564 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6565 *
6566 * @returns VBox status code.
6567 * @param pVCpu The cross context virtual CPU structure.
6568 * @param pszInstr The VMX instruction name (for logging purposes).
6569 */
6570IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6571{
6572 /*
6573 * Load guest MSRs.
6574 * See Intel spec. 26.4 "Loading MSRs".
6575 */
6576 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6577 const char *const pszFailure = "VM-exit";
6578
6579 /*
6580 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6581 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6582 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6583 */
6584 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6585 if (!cMsrs)
6586 return VINF_SUCCESS;
6587
6588 /*
6589 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6590 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6591 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6592 */
6593 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6594 if (fIsMsrCountValid)
6595 { /* likely */ }
6596 else
6597 {
6598 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6599 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6600 }
6601
6602 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6603 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6604 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6605 if (RT_SUCCESS(rc))
6606 {
6607 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6608 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6609 {
6610 if ( !pMsr->u32Reserved
6611 && pMsr->u32Msr != MSR_K8_FS_BASE
6612 && pMsr->u32Msr != MSR_K8_GS_BASE
6613 && pMsr->u32Msr != MSR_K6_EFER
6614 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6615 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6616 {
6617 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6618 if (rcStrict == VINF_SUCCESS)
6619 continue;
6620
6621 /*
6622 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6623 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6624 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6625 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6626 * MSR in ring-0 if possible, or come up with a better, generic solution.
6627 */
6628 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6629 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6630 ? kVmxVDiag_Vmentry_MsrLoadRing3
6631 : kVmxVDiag_Vmentry_MsrLoad;
6632 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6633 }
6634 else
6635 {
6636 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6637 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6638 }
6639 }
6640 }
6641 else
6642 {
6643 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6644 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6645 }
6646
6647 NOREF(pszInstr);
6648 NOREF(pszFailure);
6649 return VINF_SUCCESS;
6650}
6651
6652
6653/**
6654 * Loads the guest-state non-register state as part of VM-entry.
6655 *
6656 * @returns VBox status code.
6657 * @param pVCpu The cross context virtual CPU structure.
6658 * @param pszInstr The VMX instruction name (for logging purposes).
6659 *
6660 * @remarks This must be called only after loading the nested-guest register state
6661 * (especially nested-guest RIP).
6662 */
6663IEM_STATIC int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
6664{
6665 /*
6666 * Load guest non-register state.
6667 * See Intel spec. 26.6 "Special Features of VM Entry"
6668 */
6669 const char *const pszFailure = "VM-exit";
6670 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6671
6672 /*
6673 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6674 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6675 *
6676 * See Intel spec. 26.6.1 "Interruptibility State".
6677 */
6678 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6679 if ( !fEntryVectoring
6680 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6681 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6682 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6683 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6684
6685 /* NMI blocking. */
6686 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6687 {
6688 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6689 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6690 else
6691 {
6692 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6693 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6694 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6695 }
6696 }
6697 else
6698 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6699
6700 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6701
6702 /*
6703 * Set PGM's copy of the EPT pointer.
6704 * The EPTP has already been validated while checking guest state.
6705 *
6706 * It is important to do this prior to mapping PAE PDPTEs (below).
6707 */
6708 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6709 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
6710
6711 /*
6712 * Load the guest's PAE PDPTEs.
6713 */
6714 if (iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
6715 {
6716 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6717 {
6718 /*
6719 * With EPT, we've already validated these while checking the guest state.
6720 * Just load them directly from the VMCS here.
6721 */
6722 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6723 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6724 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6725 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6726 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6727 AssertCompile(RT_ELEMENTS(aPaePdptes) == RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes));
6728 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes); i++)
6729 pVCpu->cpum.GstCtx.aPaePdpes[i].u = aPaePdptes[i].u;
6730 }
6731 else
6732 {
6733 /*
6734 * Without EPT, we must load the PAE PDPTEs referenced by CR3.
6735 * This involves loading (and mapping) CR3 and validating them now.
6736 */
6737 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
6738 if (RT_SUCCESS(rc))
6739 { /* likely */ }
6740 else
6741 {
6742 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6743 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6744 }
6745 }
6746 }
6747
6748 /* VPID is irrelevant. We don't support VPID yet. */
6749
6750 /* Clear address-range monitoring. */
6751 EMMonitorWaitClear(pVCpu);
6752
6753 return VINF_SUCCESS;
6754}
6755
6756
6757/**
6758 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
6759 *
6760 * @param pVCpu The cross context virtual CPU structure.
6761 * @param pszInstr The VMX instruction name (for logging purposes).
6762 *
6763 * @remarks This assumes various VMCS related data structure pointers have already
6764 * been verified prior to calling this function.
6765 */
6766IEM_STATIC int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr)
6767{
6768 const char *const pszFailure = "VM-exit";
6769 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6770
6771 /*
6772 * Virtualize APIC accesses.
6773 */
6774 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6775 {
6776 /* APIC-access physical address. */
6777 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6778
6779 /*
6780 * Register the handler for the APIC-access page.
6781 *
6782 * We don't deregister the APIC-access page handler during the VM-exit as a different
6783 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6784 *
6785 * We leave the page registered until the first access that happens outside VMX non-root
6786 * mode. Guest software is allowed to access structures such as the APIC-access page
6787 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6788 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6789 *
6790 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6791 */
6792 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6793 {
6794 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6795 PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
6796 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6797 pVCpu0->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6798 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6799 if (RT_SUCCESS(rc))
6800 { /* likely */ }
6801 else
6802 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6803 }
6804 }
6805
6806 /*
6807 * VMCS shadowing.
6808 */
6809 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6810 {
6811 /* Read the VMREAD-bitmap. */
6812 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6813 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
6814 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
6815 if (RT_SUCCESS(rc))
6816 { /* likely */ }
6817 else
6818 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6819
6820 /* Read the VMWRITE-bitmap. */
6821 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
6822 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
6823 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
6824 if (RT_SUCCESS(rc))
6825 { /* likely */ }
6826 else
6827 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6828 }
6829
6830 /*
6831 * I/O bitmaps.
6832 */
6833 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6834 {
6835 /* Read the IO bitmap A. */
6836 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6837 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
6838 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
6839 if (RT_SUCCESS(rc))
6840 { /* likely */ }
6841 else
6842 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
6843
6844 /* Read the IO bitmap B. */
6845 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6846 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
6847 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
6848 if (RT_SUCCESS(rc))
6849 { /* likely */ }
6850 else
6851 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
6852 }
6853
6854 /*
6855 * TPR shadow and Virtual-APIC page.
6856 */
6857 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6858 {
6859 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6860 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6861 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6862 {
6863 /* Read the VTPR from the virtual-APIC page. */
6864 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6865 uint8_t u8VTpr;
6866 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6867 if (RT_SUCCESS(rc))
6868 { /* likely */ }
6869 else
6870 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6871
6872 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6873 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6874 { /* likely */ }
6875 else
6876 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6877 }
6878 }
6879
6880 /*
6881 * VMCS link pointer.
6882 */
6883 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6884 {
6885 /* Read the VMCS-link pointer from guest memory. */
6886 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6887 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
6888 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
6889 if (RT_SUCCESS(rc))
6890 { /* likely */ }
6891 else
6892 {
6893 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6894 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6895 }
6896
6897 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6898 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6899 { /* likely */ }
6900 else
6901 {
6902 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6903 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6904 }
6905
6906 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6907 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6908 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
6909 { /* likely */ }
6910 else
6911 {
6912 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6913 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6914 }
6915
6916 /* Update our cache of the guest physical address of the shadow VMCS. */
6917 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6918 }
6919
6920 /*
6921 * MSR bitmap.
6922 */
6923 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6924 {
6925 /* Read the MSR bitmap. */
6926 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6927 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
6928 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
6929 if (RT_SUCCESS(rc))
6930 { /* likely */ }
6931 else
6932 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6933 }
6934
6935 NOREF(pszFailure);
6936 NOREF(pszInstr);
6937 return VINF_SUCCESS;
6938}
6939
6940
6941/**
6942 * Loads the guest-state as part of VM-entry.
6943 *
6944 * @returns VBox status code.
6945 * @param pVCpu The cross context virtual CPU structure.
6946 * @param pszInstr The VMX instruction name (for logging purposes).
6947 *
6948 * @remarks This must be done after all the necessary steps prior to loading of
6949 * guest-state (e.g. checking various VMCS state).
6950 */
6951IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6952{
6953 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
6954 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6955
6956 /* Load guest segment registers. */
6957 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6958
6959 /*
6960 * Load guest RIP, RSP and RFLAGS.
6961 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6962 */
6963 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6964 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6965 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6966 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6967
6968 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6969 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6970 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6971
6972 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
6973 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
6974 if (rc == VINF_SUCCESS)
6975 { /* likely */ }
6976 else
6977 return rc;
6978
6979 /* Load VMX related structures and state referenced by the VMCS. */
6980 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
6981 if (rc == VINF_SUCCESS)
6982 { /* likely */ }
6983 else
6984 return rc;
6985
6986 NOREF(pszInstr);
6987 return VINF_SUCCESS;
6988}
6989
6990
6991/**
6992 * Returns whether there are is a pending debug exception on VM-entry.
6993 *
6994 * @param pVCpu The cross context virtual CPU structure.
6995 * @param pszInstr The VMX instruction name (for logging purposes).
6996 */
6997IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
6998{
6999 /*
7000 * Pending debug exceptions.
7001 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7002 */
7003 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7004 Assert(pVmcs);
7005
7006 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7007 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7008 if (fPendingDbgXcpt)
7009 {
7010 uint8_t uEntryIntInfoType;
7011 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7012 if (fEntryVectoring)
7013 {
7014 switch (uEntryIntInfoType)
7015 {
7016 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7017 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7018 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7019 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7020 fPendingDbgXcpt = false;
7021 break;
7022
7023 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7024 {
7025 /*
7026 * Whether the pending debug exception for software exceptions other than
7027 * #BP and #OF is delivered after injecting the exception or is discard
7028 * is CPU implementation specific. We will discard them (easier).
7029 */
7030 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7031 if ( uVector != X86_XCPT_BP
7032 && uVector != X86_XCPT_OF)
7033 fPendingDbgXcpt = false;
7034 RT_FALL_THRU();
7035 }
7036 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7037 {
7038 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7039 fPendingDbgXcpt = false;
7040 break;
7041 }
7042 }
7043 }
7044 else
7045 {
7046 /*
7047 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7048 * pending debug exception is held pending or is discarded is CPU implementation
7049 * specific. We will discard them (easier).
7050 */
7051 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7052 fPendingDbgXcpt = false;
7053
7054 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7055 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7056 fPendingDbgXcpt = false;
7057 }
7058 }
7059
7060 NOREF(pszInstr);
7061 return fPendingDbgXcpt;
7062}
7063
7064
7065/**
7066 * Set up the monitor-trap flag (MTF).
7067 *
7068 * @param pVCpu The cross context virtual CPU structure.
7069 * @param pszInstr The VMX instruction name (for logging purposes).
7070 */
7071IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
7072{
7073 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7074 Assert(pVmcs);
7075 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7076 {
7077 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7078 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7079 }
7080 else
7081 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7082 NOREF(pszInstr);
7083}
7084
7085
7086/**
7087 * Sets up NMI-window exiting.
7088 *
7089 * @param pVCpu The cross context virtual CPU structure.
7090 * @param pszInstr The VMX instruction name (for logging purposes).
7091 */
7092IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
7093{
7094 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7095 Assert(pVmcs);
7096 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7097 {
7098 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7099 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7100 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7101 }
7102 else
7103 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7104 NOREF(pszInstr);
7105}
7106
7107
7108/**
7109 * Sets up interrupt-window exiting.
7110 *
7111 * @param pVCpu The cross context virtual CPU structure.
7112 * @param pszInstr The VMX instruction name (for logging purposes).
7113 */
7114IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
7115{
7116 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7117 Assert(pVmcs);
7118 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7119 {
7120 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7121 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7122 }
7123 else
7124 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7125 NOREF(pszInstr);
7126}
7127
7128
7129/**
7130 * Set up the VMX-preemption timer.
7131 *
7132 * @param pVCpu The cross context virtual CPU structure.
7133 * @param pszInstr The VMX instruction name (for logging purposes).
7134 */
7135IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
7136{
7137 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7138 Assert(pVmcs);
7139 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7140 {
7141 /*
7142 * If the timer is 0, we must cause a VM-exit before executing the first
7143 * nested-guest instruction. So we can flag as though the timer has already
7144 * expired and we will check and cause a VM-exit at the right priority elsewhere
7145 * in the code.
7146 */
7147 uint64_t uEntryTick;
7148 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7149 if (uPreemptTimer)
7150 {
7151 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7152 AssertRC(rc);
7153 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7154 }
7155 else
7156 {
7157 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7158 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7159 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7160 }
7161
7162 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7163 }
7164 else
7165 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7166
7167 NOREF(pszInstr);
7168}
7169
7170
7171/**
7172 * Injects an event using TRPM given a VM-entry interruption info. and related
7173 * fields.
7174 *
7175 * @param pVCpu The cross context virtual CPU structure.
7176 * @param pszInstr The VMX instruction name (for logging purposes).
7177 * @param uEntryIntInfo The VM-entry interruption info.
7178 * @param uErrCode The error code associated with the event if any.
7179 * @param cbInstr The VM-entry instruction length (for software
7180 * interrupts and software exceptions). Pass 0
7181 * otherwise.
7182 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7183 */
7184IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7185 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7186{
7187 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7188
7189 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7190 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7191 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7192
7193 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7194
7195 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7196 AssertRC(rc);
7197 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7198
7199 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7200 {
7201 TRPMSetErrorCode(pVCpu, uErrCode);
7202 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7203 }
7204
7205 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7206 {
7207 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7208 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7209 }
7210 else
7211 {
7212 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7213 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7214 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7215 {
7216 TRPMSetInstrLength(pVCpu, cbInstr);
7217 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7218 }
7219 }
7220
7221 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7222 {
7223 TRPMSetTrapDueToIcebp(pVCpu);
7224 Log(("%s: Injecting: icebp\n", pszInstr));
7225 }
7226
7227 NOREF(pszInstr);
7228}
7229
7230
7231/**
7232 * Performs event injection (if any) as part of VM-entry.
7233 *
7234 * @param pVCpu The cross context virtual CPU structure.
7235 * @param pszInstr The VMX instruction name (for logging purposes).
7236 */
7237IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7238{
7239 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7240
7241 /*
7242 * Inject events.
7243 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7244 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7245 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7246 * the actually delivery of this event.
7247 *
7248 * See Intel spec. 26.5 "Event Injection".
7249 */
7250 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7251 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7252
7253 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7254 if (fEntryIntInfoValid)
7255 {
7256 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7257 {
7258 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7259 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7260 }
7261 else
7262 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7263 pVCpu->cpum.GstCtx.cr2);
7264
7265 /*
7266 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7267 *
7268 * However, we do it here on VM-entry as well because while it isn't visible to guest
7269 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7270 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7271 *
7272 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7273 */
7274 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7275 }
7276 else
7277 {
7278 /*
7279 * Inject any pending guest debug exception.
7280 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7281 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7282 */
7283 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7284 if (fPendingDbgXcpt)
7285 {
7286 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7287 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7288 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7289 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7290 0 /* GCPtrFaultAddress */);
7291 }
7292 }
7293
7294 NOREF(pszInstr);
7295}
7296
7297
7298/**
7299 * Initializes all read-only VMCS fields as part of VM-entry.
7300 *
7301 * @param pVCpu The cross context virtual CPU structure.
7302 */
7303IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7304{
7305 /*
7306 * Any VMCS field which we do not establish on every VM-exit but may potentially
7307 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7308 * specified to be undefined, needs to be initialized here.
7309 *
7310 * Thus, it is especially important to clear the Exit qualification field
7311 * since it must be zero for VM-exits where it is not used. Similarly, the
7312 * VM-exit interruption information field's valid bit needs to be cleared for
7313 * the same reasons.
7314 */
7315 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7316 Assert(pVmcs);
7317
7318 /* 16-bit (none currently). */
7319 /* 32-bit. */
7320 pVmcs->u32RoVmInstrError = 0;
7321 pVmcs->u32RoExitReason = 0;
7322 pVmcs->u32RoExitIntInfo = 0;
7323 pVmcs->u32RoExitIntErrCode = 0;
7324 pVmcs->u32RoIdtVectoringInfo = 0;
7325 pVmcs->u32RoIdtVectoringErrCode = 0;
7326 pVmcs->u32RoExitInstrLen = 0;
7327 pVmcs->u32RoExitInstrInfo = 0;
7328
7329 /* 64-bit. */
7330 pVmcs->u64RoGuestPhysAddr.u = 0;
7331
7332 /* Natural-width. */
7333 pVmcs->u64RoExitQual.u = 0;
7334 pVmcs->u64RoIoRcx.u = 0;
7335 pVmcs->u64RoIoRsi.u = 0;
7336 pVmcs->u64RoIoRdi.u = 0;
7337 pVmcs->u64RoIoRip.u = 0;
7338 pVmcs->u64RoGuestLinearAddr.u = 0;
7339}
7340
7341
7342/**
7343 * VMLAUNCH/VMRESUME instruction execution worker.
7344 *
7345 * @returns Strict VBox status code.
7346 * @param pVCpu The cross context virtual CPU structure.
7347 * @param cbInstr The instruction length in bytes.
7348 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7349 * VMXINSTRID_VMRESUME).
7350 *
7351 * @remarks Common VMX instruction checks are already expected to by the caller,
7352 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7353 */
7354IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7355{
7356# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7357 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7358 return VINF_EM_RAW_EMULATE_INSTR;
7359# else
7360 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7361 || uInstrId == VMXINSTRID_VMRESUME);
7362 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7363
7364 /* Nested-guest intercept. */
7365 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7366 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7367
7368 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7369
7370 /*
7371 * Basic VM-entry checks.
7372 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7373 * The checks following that do not have to follow a specific order.
7374 *
7375 * See Intel spec. 26.1 "Basic VM-entry Checks".
7376 */
7377
7378 /* CPL. */
7379 if (pVCpu->iem.s.uCpl == 0)
7380 { /* likely */ }
7381 else
7382 {
7383 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7384 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7385 return iemRaiseGeneralProtectionFault0(pVCpu);
7386 }
7387
7388 /* Current VMCS valid. */
7389 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7390 { /* likely */ }
7391 else
7392 {
7393 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7394 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7395 iemVmxVmFailInvalid(pVCpu);
7396 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7397 return VINF_SUCCESS;
7398 }
7399
7400 /* Current VMCS is not a shadow VMCS. */
7401 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7402 { /* likely */ }
7403 else
7404 {
7405 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7406 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7407 iemVmxVmFailInvalid(pVCpu);
7408 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7409 return VINF_SUCCESS;
7410 }
7411
7412 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7413 * use block-by-STI here which is not quite correct. */
7414 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7415 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7416 { /* likely */ }
7417 else
7418 {
7419 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7420 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7421 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7422 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7423 return VINF_SUCCESS;
7424 }
7425
7426 if (uInstrId == VMXINSTRID_VMLAUNCH)
7427 {
7428 /* VMLAUNCH with non-clear VMCS. */
7429 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7430 { /* likely */ }
7431 else
7432 {
7433 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7434 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7435 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7436 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7437 return VINF_SUCCESS;
7438 }
7439 }
7440 else
7441 {
7442 /* VMRESUME with non-launched VMCS. */
7443 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7444 { /* likely */ }
7445 else
7446 {
7447 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7448 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7449 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7450 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7451 return VINF_SUCCESS;
7452 }
7453 }
7454
7455 /*
7456 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7457 * while entering VMX non-root mode. We do some of this while checking VM-execution
7458 * controls. The nested hypervisor should not make assumptions and cannot expect
7459 * predictable behavior if changes to these structures are made in guest memory while
7460 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7461 * modify them anyway as we cache them in host memory.
7462 *
7463 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7464 */
7465 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7466 Assert(pVmcs);
7467 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7468
7469 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7470 if (RT_SUCCESS(rc))
7471 {
7472 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7473 if (RT_SUCCESS(rc))
7474 {
7475 /*
7476 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7477 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7478 * ones that may occur during VM-entry below).
7479 */
7480 iemVmxVmentryInitReadOnlyFields(pVCpu);
7481
7482 /*
7483 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7484 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7485 * VM-exit when required.
7486 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7487 */
7488 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7489
7490 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7491 if (RT_SUCCESS(rc))
7492 {
7493 /*
7494 * We've now entered nested-guest execution.
7495 *
7496 * It is important do this prior to loading the guest state because
7497 * as part of loading the guest state, PGM (and perhaps other components
7498 * in the future) relies on detecting whether VMX non-root mode has been
7499 * entered.
7500 */
7501 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7502
7503 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7504 if (RT_SUCCESS(rc))
7505 {
7506 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7507 if (RT_SUCCESS(rc))
7508 {
7509 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7510
7511 /* VMLAUNCH instruction must update the VMCS launch state. */
7512 if (uInstrId == VMXINSTRID_VMLAUNCH)
7513 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7514
7515 /* Perform the VMX transition (PGM updates). */
7516 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7517 if (rcStrict == VINF_SUCCESS)
7518 { /* likely */ }
7519 else if (RT_SUCCESS(rcStrict))
7520 {
7521 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7522 VBOXSTRICTRC_VAL(rcStrict)));
7523 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7524 }
7525 else
7526 {
7527 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7528 return rcStrict;
7529 }
7530
7531 /* Paranoia. */
7532 Assert(rcStrict == VINF_SUCCESS);
7533
7534 /*
7535 * The priority of potential VM-exits during VM-entry is important.
7536 * The priorities of VM-exits and events are listed from highest
7537 * to lowest as follows:
7538 *
7539 * 1. Event injection.
7540 * 2. Trap on task-switch (T flag set in TSS).
7541 * 3. TPR below threshold / APIC-write.
7542 * 4. SMI, INIT.
7543 * 5. MTF exit.
7544 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7545 * 7. VMX-preemption timer.
7546 * 9. NMI-window exit.
7547 * 10. NMI injection.
7548 * 11. Interrupt-window exit.
7549 * 12. Virtual-interrupt injection.
7550 * 13. Interrupt injection.
7551 * 14. Process next instruction (fetch, decode, execute).
7552 */
7553
7554 /* Setup VMX-preemption timer. */
7555 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7556
7557 /* Setup monitor-trap flag. */
7558 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7559
7560 /* Setup NMI-window exiting. */
7561 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7562
7563 /* Setup interrupt-window exiting. */
7564 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7565
7566 /*
7567 * Inject any event that the nested hypervisor wants to inject.
7568 * Note! We cannot immediately perform the event injection here as we may have
7569 * pending PGM operations to perform due to switching page tables and/or
7570 * mode.
7571 */
7572 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7573
7574# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7575 /* Reschedule to IEM-only execution of the nested-guest. */
7576 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7577 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7578 if (rcSched != VINF_SUCCESS)
7579 iemSetPassUpStatus(pVCpu, rcSched);
7580# endif
7581
7582 /* Finally, done. */
7583 Log3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",
7584 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7585 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7586 pVCpu->cpum.GstCtx.msrEFER));
7587 return VINF_SUCCESS;
7588 }
7589 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7590 }
7591 }
7592 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7593 }
7594
7595 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7596 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7597 return VINF_SUCCESS;
7598 }
7599
7600 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7601 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7602 return VINF_SUCCESS;
7603# endif
7604}
7605
7606
7607/**
7608 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7609 * (causes a VM-exit) or not.
7610 *
7611 * @returns @c true if the instruction is intercepted, @c false otherwise.
7612 * @param pVCpu The cross context virtual CPU structure.
7613 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7614 * VMX_EXIT_WRMSR).
7615 * @param idMsr The MSR.
7616 */
7617IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7618{
7619 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7620 Assert( uExitReason == VMX_EXIT_RDMSR
7621 || uExitReason == VMX_EXIT_WRMSR);
7622
7623 /* Consult the MSR bitmap if the feature is supported. */
7624 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7625 Assert(pVmcs);
7626 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7627 {
7628 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7629 if (uExitReason == VMX_EXIT_RDMSR)
7630 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7631 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7632 }
7633
7634 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7635 return true;
7636}
7637
7638
7639/**
7640 * VMREAD instruction execution worker that does not perform any validation checks.
7641 *
7642 * Callers are expected to have performed the necessary checks and to ensure the
7643 * VMREAD will succeed.
7644 *
7645 * @param pVmcs Pointer to the virtual VMCS.
7646 * @param pu64Dst Where to write the VMCS value.
7647 * @param u64VmcsField The VMCS field.
7648 *
7649 * @remarks May be called with interrupts disabled.
7650 */
7651IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7652{
7653 VMXVMCSFIELD VmcsField;
7654 VmcsField.u = u64VmcsField;
7655 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7656 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7657 uint8_t const uWidthType = (uWidth << 2) | uType;
7658 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7659 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7660 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7661 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
7662 uWidth, uType, uIndex, uIndex));
7663 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7664
7665 /*
7666 * Read the VMCS component based on the field's effective width.
7667 *
7668 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7669 * indicates high bits (little endian).
7670 *
7671 * Note! The caller is responsible to trim the result and update registers
7672 * or memory locations are required. Here we just zero-extend to the largest
7673 * type (i.e. 64-bits).
7674 */
7675 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7676 uint8_t const *pbField = pbVmcs + offField;
7677 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7678 switch (uEffWidth)
7679 {
7680 case VMX_VMCSFIELD_WIDTH_64BIT:
7681 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7682 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7683 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7684 }
7685}
7686
7687
7688/**
7689 * VMREAD common (memory/register) instruction execution worker.
7690 *
7691 * @returns Strict VBox status code.
7692 * @param pVCpu The cross context virtual CPU structure.
7693 * @param cbInstr The instruction length in bytes.
7694 * @param pu64Dst Where to write the VMCS value (only updated when
7695 * VINF_SUCCESS is returned).
7696 * @param u64VmcsField The VMCS field.
7697 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7698 * NULL.
7699 */
7700IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7701 PCVMXVEXITINFO pExitInfo)
7702{
7703 /* Nested-guest intercept. */
7704 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7705 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7706 {
7707 if (pExitInfo)
7708 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7709 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7710 }
7711
7712 /* CPL. */
7713 if (pVCpu->iem.s.uCpl == 0)
7714 { /* likely */ }
7715 else
7716 {
7717 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7718 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7719 return iemRaiseGeneralProtectionFault0(pVCpu);
7720 }
7721
7722 /* VMCS pointer in root mode. */
7723 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7724 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7725 { /* likely */ }
7726 else
7727 {
7728 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7729 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7730 iemVmxVmFailInvalid(pVCpu);
7731 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7732 return VINF_SUCCESS;
7733 }
7734
7735 /* VMCS-link pointer in non-root mode. */
7736 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7737 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7738 { /* likely */ }
7739 else
7740 {
7741 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7742 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7743 iemVmxVmFailInvalid(pVCpu);
7744 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7745 return VINF_SUCCESS;
7746 }
7747
7748 /* Supported VMCS field. */
7749 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7750 { /* likely */ }
7751 else
7752 {
7753 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7754 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7755 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7756 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7757 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7758 return VINF_SUCCESS;
7759 }
7760
7761 /*
7762 * Reading from the current or shadow VMCS.
7763 */
7764 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7765 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7766 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7767 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7768 return VINF_SUCCESS;
7769}
7770
7771
7772/**
7773 * VMREAD (64-bit register) instruction execution worker.
7774 *
7775 * @returns Strict VBox status code.
7776 * @param pVCpu The cross context virtual CPU structure.
7777 * @param cbInstr The instruction length in bytes.
7778 * @param pu64Dst Where to store the VMCS field's value.
7779 * @param u64VmcsField The VMCS field.
7780 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7781 * NULL.
7782 */
7783IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7784 PCVMXVEXITINFO pExitInfo)
7785{
7786 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7787 if (rcStrict == VINF_SUCCESS)
7788 {
7789 iemVmxVmreadSuccess(pVCpu, cbInstr);
7790 return VINF_SUCCESS;
7791 }
7792
7793 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7794 return rcStrict;
7795}
7796
7797
7798/**
7799 * VMREAD (32-bit register) instruction execution worker.
7800 *
7801 * @returns Strict VBox status code.
7802 * @param pVCpu The cross context virtual CPU structure.
7803 * @param cbInstr The instruction length in bytes.
7804 * @param pu32Dst Where to store the VMCS field's value.
7805 * @param u32VmcsField The VMCS field.
7806 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7807 * NULL.
7808 */
7809IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7810 PCVMXVEXITINFO pExitInfo)
7811{
7812 uint64_t u64Dst;
7813 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7814 if (rcStrict == VINF_SUCCESS)
7815 {
7816 *pu32Dst = u64Dst;
7817 iemVmxVmreadSuccess(pVCpu, cbInstr);
7818 return VINF_SUCCESS;
7819 }
7820
7821 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7822 return rcStrict;
7823}
7824
7825
7826/**
7827 * VMREAD (memory) instruction execution worker.
7828 *
7829 * @returns Strict VBox status code.
7830 * @param pVCpu The cross context virtual CPU structure.
7831 * @param cbInstr The instruction length in bytes.
7832 * @param iEffSeg The effective segment register to use with @a u64Val.
7833 * Pass UINT8_MAX if it is a register access.
7834 * @param GCPtrDst The guest linear address to store the VMCS field's
7835 * value.
7836 * @param u64VmcsField The VMCS field.
7837 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7838 * NULL.
7839 */
7840IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7841 PCVMXVEXITINFO pExitInfo)
7842{
7843 uint64_t u64Dst;
7844 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7845 if (rcStrict == VINF_SUCCESS)
7846 {
7847 /*
7848 * Write the VMCS field's value to the location specified in guest-memory.
7849 */
7850 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7851 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7852 else
7853 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7854 if (rcStrict == VINF_SUCCESS)
7855 {
7856 iemVmxVmreadSuccess(pVCpu, cbInstr);
7857 return VINF_SUCCESS;
7858 }
7859
7860 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7861 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7862 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7863 return rcStrict;
7864 }
7865
7866 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7867 return rcStrict;
7868}
7869
7870
7871/**
7872 * VMWRITE instruction execution worker that does not perform any validation
7873 * checks.
7874 *
7875 * Callers are expected to have performed the necessary checks and to ensure the
7876 * VMWRITE will succeed.
7877 *
7878 * @param pVmcs Pointer to the virtual VMCS.
7879 * @param u64Val The value to write.
7880 * @param u64VmcsField The VMCS field.
7881 *
7882 * @remarks May be called with interrupts disabled.
7883 */
7884IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7885{
7886 VMXVMCSFIELD VmcsField;
7887 VmcsField.u = u64VmcsField;
7888 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7889 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7890 uint8_t const uWidthType = (uWidth << 2) | uType;
7891 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7892 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7893 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7894 Assert(offField < VMX_V_VMCS_SIZE);
7895 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7896
7897 /*
7898 * Write the VMCS component based on the field's effective width.
7899 *
7900 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7901 * indicates high bits (little endian).
7902 */
7903 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7904 uint8_t *pbField = pbVmcs + offField;
7905 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7906 switch (uEffWidth)
7907 {
7908 case VMX_VMCSFIELD_WIDTH_64BIT:
7909 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7910 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7911 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7912 }
7913}
7914
7915
7916/**
7917 * VMWRITE instruction execution worker.
7918 *
7919 * @returns Strict VBox status code.
7920 * @param pVCpu The cross context virtual CPU structure.
7921 * @param cbInstr The instruction length in bytes.
7922 * @param iEffSeg The effective segment register to use with @a u64Val.
7923 * Pass UINT8_MAX if it is a register access.
7924 * @param u64Val The value to write (or guest linear address to the
7925 * value), @a iEffSeg will indicate if it's a memory
7926 * operand.
7927 * @param u64VmcsField The VMCS field.
7928 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7929 * NULL.
7930 */
7931IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7932 PCVMXVEXITINFO pExitInfo)
7933{
7934 /* Nested-guest intercept. */
7935 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7936 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7937 {
7938 if (pExitInfo)
7939 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7940 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7941 }
7942
7943 /* CPL. */
7944 if (pVCpu->iem.s.uCpl == 0)
7945 { /* likely */ }
7946 else
7947 {
7948 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7949 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7950 return iemRaiseGeneralProtectionFault0(pVCpu);
7951 }
7952
7953 /* VMCS pointer in root mode. */
7954 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7955 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7956 { /* likely */ }
7957 else
7958 {
7959 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7960 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7961 iemVmxVmFailInvalid(pVCpu);
7962 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7963 return VINF_SUCCESS;
7964 }
7965
7966 /* VMCS-link pointer in non-root mode. */
7967 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7968 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7969 { /* likely */ }
7970 else
7971 {
7972 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7973 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
7974 iemVmxVmFailInvalid(pVCpu);
7975 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7976 return VINF_SUCCESS;
7977 }
7978
7979 /* If the VMWRITE instruction references memory, access the specified memory operand. */
7980 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
7981 if (!fIsRegOperand)
7982 {
7983 /* Read the value from the specified guest memory location. */
7984 VBOXSTRICTRC rcStrict;
7985 RTGCPTR const GCPtrVal = u64Val;
7986 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7987 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7988 else
7989 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
7990 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
7991 {
7992 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
7993 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
7994 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
7995 return rcStrict;
7996 }
7997 }
7998 else
7999 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8000
8001 /* Supported VMCS field. */
8002 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8003 { /* likely */ }
8004 else
8005 {
8006 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8007 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8008 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8009 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8010 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8011 return VINF_SUCCESS;
8012 }
8013
8014 /* Read-only VMCS field. */
8015 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8016 if ( !fIsFieldReadOnly
8017 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8018 { /* likely */ }
8019 else
8020 {
8021 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8022 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8023 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8024 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8025 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8026 return VINF_SUCCESS;
8027 }
8028
8029 /*
8030 * Write to the current or shadow VMCS.
8031 */
8032 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8033 PVMXVVMCS pVmcs = !fInVmxNonRootMode
8034 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8035 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8036 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8037
8038 /* Notify HM that the VMCS content might have changed. */
8039 if (!fInVmxNonRootMode)
8040 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8041
8042 iemVmxVmSucceed(pVCpu);
8043 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8044 return VINF_SUCCESS;
8045}
8046
8047
8048/**
8049 * VMCLEAR instruction execution worker.
8050 *
8051 * @returns Strict VBox status code.
8052 * @param pVCpu The cross context virtual CPU structure.
8053 * @param cbInstr The instruction length in bytes.
8054 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8055 * @param GCPtrVmcs The linear address of the VMCS pointer.
8056 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8057 *
8058 * @remarks Common VMX instruction checks are already expected to by the caller,
8059 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8060 */
8061IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8062 PCVMXVEXITINFO pExitInfo)
8063{
8064 /* Nested-guest intercept. */
8065 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8066 {
8067 if (pExitInfo)
8068 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8069 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8070 }
8071
8072 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8073
8074 /* CPL. */
8075 if (pVCpu->iem.s.uCpl == 0)
8076 { /* likely */ }
8077 else
8078 {
8079 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8080 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8081 return iemRaiseGeneralProtectionFault0(pVCpu);
8082 }
8083
8084 /* Get the VMCS pointer from the location specified by the source memory operand. */
8085 RTGCPHYS GCPhysVmcs;
8086 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8087 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8088 { /* likely */ }
8089 else
8090 {
8091 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8092 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8093 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8094 return rcStrict;
8095 }
8096
8097 /* VMCS pointer alignment. */
8098 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8099 { /* likely */ }
8100 else
8101 {
8102 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8103 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8104 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8105 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8106 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8107 return VINF_SUCCESS;
8108 }
8109
8110 /* VMCS physical-address width limits. */
8111 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8112 { /* likely */ }
8113 else
8114 {
8115 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8116 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8117 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8118 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8119 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8120 return VINF_SUCCESS;
8121 }
8122
8123 /* VMCS is not the VMXON region. */
8124 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8125 { /* likely */ }
8126 else
8127 {
8128 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8129 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8130 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8131 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8132 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8133 return VINF_SUCCESS;
8134 }
8135
8136 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8137 restriction imposed by our implementation. */
8138 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8139 { /* likely */ }
8140 else
8141 {
8142 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8143 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8144 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8145 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8146 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8147 return VINF_SUCCESS;
8148 }
8149
8150 /*
8151 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8152 *
8153 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8154 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8155 * to 'clear'.
8156 */
8157 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8158 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8159 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8160 {
8161 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8162 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8163 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8164 }
8165 else
8166 {
8167 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8168 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8169 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8170 if (RT_FAILURE(rcStrict))
8171 return rcStrict;
8172 }
8173
8174 iemVmxVmSucceed(pVCpu);
8175 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8176 return VINF_SUCCESS;
8177}
8178
8179
8180/**
8181 * VMPTRST instruction execution worker.
8182 *
8183 * @returns Strict VBox status code.
8184 * @param pVCpu The cross context virtual CPU structure.
8185 * @param cbInstr The instruction length in bytes.
8186 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8187 * @param GCPtrVmcs The linear address of where to store the current VMCS
8188 * pointer.
8189 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8190 *
8191 * @remarks Common VMX instruction checks are already expected to by the caller,
8192 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8193 */
8194IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8195 PCVMXVEXITINFO pExitInfo)
8196{
8197 /* Nested-guest intercept. */
8198 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8199 {
8200 if (pExitInfo)
8201 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8202 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8203 }
8204
8205 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8206
8207 /* CPL. */
8208 if (pVCpu->iem.s.uCpl == 0)
8209 { /* likely */ }
8210 else
8211 {
8212 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8213 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8214 return iemRaiseGeneralProtectionFault0(pVCpu);
8215 }
8216
8217 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8218 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8219 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8220 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8221 {
8222 iemVmxVmSucceed(pVCpu);
8223 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8224 return rcStrict;
8225 }
8226
8227 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8228 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8229 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8230 return rcStrict;
8231}
8232
8233
8234/**
8235 * VMPTRLD instruction execution worker.
8236 *
8237 * @returns Strict VBox status code.
8238 * @param pVCpu The cross context virtual CPU structure.
8239 * @param cbInstr The instruction length in bytes.
8240 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8241 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8242 *
8243 * @remarks Common VMX instruction checks are already expected to by the caller,
8244 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8245 */
8246IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8247 PCVMXVEXITINFO pExitInfo)
8248{
8249 /* Nested-guest intercept. */
8250 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8251 {
8252 if (pExitInfo)
8253 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8254 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8255 }
8256
8257 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8258
8259 /* CPL. */
8260 if (pVCpu->iem.s.uCpl == 0)
8261 { /* likely */ }
8262 else
8263 {
8264 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8265 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8266 return iemRaiseGeneralProtectionFault0(pVCpu);
8267 }
8268
8269 /* Get the VMCS pointer from the location specified by the source memory operand. */
8270 RTGCPHYS GCPhysVmcs;
8271 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8272 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8273 { /* likely */ }
8274 else
8275 {
8276 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8277 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8278 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8279 return rcStrict;
8280 }
8281
8282 /* VMCS pointer alignment. */
8283 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8284 { /* likely */ }
8285 else
8286 {
8287 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8288 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8289 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8290 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8291 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8292 return VINF_SUCCESS;
8293 }
8294
8295 /* VMCS physical-address width limits. */
8296 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8297 { /* likely */ }
8298 else
8299 {
8300 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8301 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8302 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8303 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8304 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8305 return VINF_SUCCESS;
8306 }
8307
8308 /* VMCS is not the VMXON region. */
8309 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8310 { /* likely */ }
8311 else
8312 {
8313 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8314 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8315 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8316 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8317 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8318 return VINF_SUCCESS;
8319 }
8320
8321 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8322 restriction imposed by our implementation. */
8323 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8324 { /* likely */ }
8325 else
8326 {
8327 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8328 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8329 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8330 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8331 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8332 return VINF_SUCCESS;
8333 }
8334
8335 /* Read just the VMCS revision from the VMCS. */
8336 VMXVMCSREVID VmcsRevId;
8337 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8338 if (RT_SUCCESS(rc))
8339 { /* likely */ }
8340 else
8341 {
8342 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8343 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8344 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8345 return rc;
8346 }
8347
8348 /*
8349 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8350 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8351 */
8352 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8353 && ( !VmcsRevId.n.fIsShadowVmcs
8354 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8355 { /* likely */ }
8356 else
8357 {
8358 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8359 {
8360 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8361 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8362 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8363 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8364 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8365 return VINF_SUCCESS;
8366 }
8367
8368 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8369 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8370 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8371 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8372 return VINF_SUCCESS;
8373 }
8374
8375 /*
8376 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8377 * the cache of an existing, current VMCS back to guest memory before loading a new,
8378 * different current VMCS.
8379 */
8380 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8381 {
8382 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8383 {
8384 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8385 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8386 }
8387
8388 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8389 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8390 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8391 if (RT_SUCCESS(rc))
8392 {
8393 /* Notify HM that a new, current VMCS is loaded. */
8394 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8395 }
8396 else
8397 {
8398 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8399 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8400 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8401 return rc;
8402 }
8403 }
8404
8405 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8406 iemVmxVmSucceed(pVCpu);
8407 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8408 return VINF_SUCCESS;
8409}
8410
8411
8412/**
8413 * INVVPID instruction execution worker.
8414 *
8415 * @returns Strict VBox status code.
8416 * @param pVCpu The cross context virtual CPU structure.
8417 * @param cbInstr The instruction length in bytes.
8418 * @param iEffSeg The segment of the invvpid descriptor.
8419 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8420 * @param u64InvvpidType The invalidation type.
8421 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8422 * NULL.
8423 *
8424 * @remarks Common VMX instruction checks are already expected to by the caller,
8425 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8426 */
8427IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8428 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8429{
8430 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8431 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8432 return iemRaiseUndefinedOpcode(pVCpu);
8433
8434 /* Nested-guest intercept. */
8435 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8436 {
8437 if (pExitInfo)
8438 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8439 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8440 }
8441
8442 /* CPL. */
8443 if (pVCpu->iem.s.uCpl != 0)
8444 {
8445 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8446 return iemRaiseGeneralProtectionFault0(pVCpu);
8447 }
8448
8449 /*
8450 * Validate INVVPID invalidation type.
8451 *
8452 * The instruction specifies exactly ONE of the supported invalidation types.
8453 *
8454 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8455 * supported. In theory, it's possible for a CPU to not support flushing individual
8456 * addresses but all the other types or any other combination. We do not take any
8457 * shortcuts here by assuming the types we currently expose to the guest.
8458 */
8459 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8460 bool const fInvvpidSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID);
8461 bool const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8462 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8463 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8464 bool const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8465
8466 bool afSupportedTypes[4];
8467 afSupportedTypes[0] = fTypeIndivAddr;
8468 afSupportedTypes[1] = fTypeSingleCtx;
8469 afSupportedTypes[2] = fTypeAllCtx;
8470 afSupportedTypes[3] = fTypeSingleCtxRetainGlobals;
8471
8472 if ( fInvvpidSupported
8473 && !(u64InvvpidType & ~(uint64_t)VMX_INVVPID_VALID_MASK)
8474 && afSupportedTypes[u64InvvpidType & 3])
8475 { /* likely */ }
8476 else
8477 {
8478 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8479 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8480 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8481 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8482 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8483 return VINF_SUCCESS;
8484 }
8485
8486 /*
8487 * Fetch the invvpid descriptor from guest memory.
8488 */
8489 RTUINT128U uDesc;
8490 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8491 if (rcStrict == VINF_SUCCESS)
8492 {
8493 /*
8494 * Validate the descriptor.
8495 */
8496 if (uDesc.s.Lo > 0xfff)
8497 {
8498 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8499 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8500 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8501 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8502 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8503 return VINF_SUCCESS;
8504 }
8505
8506 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8507 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8508 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8509 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8510 switch (u64InvvpidType)
8511 {
8512 case VMXTLBFLUSHVPID_INDIV_ADDR:
8513 {
8514 if (uVpid != 0)
8515 {
8516 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8517 {
8518 /* Invalidate mappings for the linear address tagged with VPID. */
8519 /** @todo PGM support for VPID? Currently just flush everything. */
8520 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8521 iemVmxVmSucceed(pVCpu);
8522 }
8523 else
8524 {
8525 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8526 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8527 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8528 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8529 }
8530 }
8531 else
8532 {
8533 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8534 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8535 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8536 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8537 }
8538 break;
8539 }
8540
8541 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8542 {
8543 if (uVpid != 0)
8544 {
8545 /* Invalidate all mappings with VPID. */
8546 /** @todo PGM support for VPID? Currently just flush everything. */
8547 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8548 iemVmxVmSucceed(pVCpu);
8549 }
8550 else
8551 {
8552 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8553 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8554 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8555 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8556 }
8557 break;
8558 }
8559
8560 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8561 {
8562 /* Invalidate all mappings with non-zero VPIDs. */
8563 /** @todo PGM support for VPID? Currently just flush everything. */
8564 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8565 iemVmxVmSucceed(pVCpu);
8566 break;
8567 }
8568
8569 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8570 {
8571 if (uVpid != 0)
8572 {
8573 /* Invalidate all mappings with VPID except global translations. */
8574 /** @todo PGM support for VPID? Currently just flush everything. */
8575 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8576 iemVmxVmSucceed(pVCpu);
8577 }
8578 else
8579 {
8580 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8581 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8582 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8583 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8584 }
8585 break;
8586 }
8587 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8588 }
8589 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8590 }
8591 return rcStrict;
8592}
8593
8594
8595#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
8596/**
8597 * INVEPT instruction execution worker.
8598 *
8599 * @returns Strict VBox status code.
8600 * @param pVCpu The cross context virtual CPU structure.
8601 * @param cbInstr The instruction length in bytes.
8602 * @param iEffSeg The segment of the invept descriptor.
8603 * @param GCPtrInveptDesc The address of invept descriptor.
8604 * @param u64InveptType The invalidation type.
8605 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8606 * NULL.
8607 *
8608 * @remarks Common VMX instruction checks are already expected to by the caller,
8609 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8610 */
8611IEM_STATIC VBOXSTRICTRC iemVmxInvept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInveptDesc,
8612 uint64_t u64InveptType, PCVMXVEXITINFO pExitInfo)
8613{
8614 /* Check if EPT is supported, otherwise raise #UD. */
8615 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEpt)
8616 return iemRaiseUndefinedOpcode(pVCpu);
8617
8618 /* Nested-guest intercept. */
8619 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8620 {
8621 if (pExitInfo)
8622 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8623 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVEPT, VMXINSTRID_NONE, cbInstr);
8624 }
8625
8626 /* CPL. */
8627 if (pVCpu->iem.s.uCpl != 0)
8628 {
8629 Log(("invept: CPL != 0 -> #GP(0)\n"));
8630 return iemRaiseGeneralProtectionFault0(pVCpu);
8631 }
8632
8633 /*
8634 * Validate INVEPT invalidation type.
8635 *
8636 * The instruction specifies exactly ONE of the supported invalidation types.
8637 *
8638 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8639 * supported. In theory, it's possible for a CPU to not support flushing individual
8640 * addresses but all the other types or any other combination. We do not take any
8641 * shortcuts here by assuming the types we currently expose to the guest.
8642 */
8643 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8644 bool const fInveptSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT);
8645 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
8646 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
8647
8648 bool afSupportedTypes[4];
8649 afSupportedTypes[0] = false;
8650 afSupportedTypes[1] = fTypeSingleCtx;
8651 afSupportedTypes[2] = fTypeAllCtx;
8652 afSupportedTypes[3] = false;
8653
8654 if ( fInveptSupported
8655 && !(u64InveptType & ~(uint64_t)VMX_INVEPT_VALID_MASK)
8656 && afSupportedTypes[u64InveptType & 3])
8657 { /* likely */ }
8658 else
8659 {
8660 Log(("invept: invalid/unsupported invvpid type %#x -> VMFail\n", u64InveptType));
8661 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_TypeInvalid;
8662 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType;
8663 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8664 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8665 return VINF_SUCCESS;
8666 }
8667
8668 /*
8669 * Fetch the invept descriptor from guest memory.
8670 */
8671 RTUINT128U uDesc;
8672 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInveptDesc);
8673 if (rcStrict == VINF_SUCCESS)
8674 {
8675 /*
8676 * Validate the descriptor.
8677 *
8678 * The Intel spec. does not explicit say the INVEPT instruction fails when reserved
8679 * bits in the descriptor are set, but it -does- for INVVPID. Until we test on real
8680 * hardware, it's assumed INVEPT behaves the same as INVVPID in this regard. It's
8681 * better to be strict in our emulation until proven otherwise.
8682 */
8683 if (uDesc.s.Hi)
8684 {
8685 Log(("invept: reserved bits set in invept descriptor %#RX64 -> VMFail\n", uDesc.s.Hi));
8686 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_DescRsvd;
8687 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi;
8688 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8689 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8690 return VINF_SUCCESS;
8691 }
8692
8693 /*
8694 * Flush TLB mappings based on the EPT type.
8695 */
8696 if (u64InveptType == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
8697 {
8698 uint64_t const GCPhysEptPtr = uDesc.s.Lo;
8699 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, GCPhysEptPtr, NULL /* enmDiag */);
8700 if (RT_SUCCESS(rc))
8701 { /* likely */ }
8702 else
8703 {
8704 Log(("invept: EPTP invalid %#RX64 -> VMFail\n", GCPhysEptPtr));
8705 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_EptpInvalid;
8706 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr;
8707 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8708 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8709 return VINF_SUCCESS;
8710 }
8711 }
8712
8713 /** @todo PGM support for EPT tags? Currently just flush everything. */
8714 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8715 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8716 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8717 }
8718
8719 return rcStrict;
8720}
8721#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
8722
8723
8724/**
8725 * VMXON instruction execution worker.
8726 *
8727 * @returns Strict VBox status code.
8728 * @param pVCpu The cross context virtual CPU structure.
8729 * @param cbInstr The instruction length in bytes.
8730 * @param iEffSeg The effective segment register to use with @a
8731 * GCPtrVmxon.
8732 * @param GCPtrVmxon The linear address of the VMXON pointer.
8733 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8734 *
8735 * @remarks Common VMX instruction checks are already expected to by the caller,
8736 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8737 */
8738IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8739 PCVMXVEXITINFO pExitInfo)
8740{
8741 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8742 {
8743 /* CPL. */
8744 if (pVCpu->iem.s.uCpl == 0)
8745 { /* likely */ }
8746 else
8747 {
8748 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8749 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8750 return iemRaiseGeneralProtectionFault0(pVCpu);
8751 }
8752
8753 /* A20M (A20 Masked) mode. */
8754 if (PGMPhysIsA20Enabled(pVCpu))
8755 { /* likely */ }
8756 else
8757 {
8758 Log(("vmxon: A20M mode -> #GP(0)\n"));
8759 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8760 return iemRaiseGeneralProtectionFault0(pVCpu);
8761 }
8762
8763 /* CR0. */
8764 {
8765 /* CR0 MB1 bits. */
8766 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8767 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8768 { /* likely */ }
8769 else
8770 {
8771 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8772 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8773 return iemRaiseGeneralProtectionFault0(pVCpu);
8774 }
8775
8776 /* CR0 MBZ bits. */
8777 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8778 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8779 { /* likely */ }
8780 else
8781 {
8782 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8783 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8784 return iemRaiseGeneralProtectionFault0(pVCpu);
8785 }
8786 }
8787
8788 /* CR4. */
8789 {
8790 /* CR4 MB1 bits. */
8791 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8792 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8793 { /* likely */ }
8794 else
8795 {
8796 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8797 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8798 return iemRaiseGeneralProtectionFault0(pVCpu);
8799 }
8800
8801 /* CR4 MBZ bits. */
8802 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8803 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8804 { /* likely */ }
8805 else
8806 {
8807 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8808 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8809 return iemRaiseGeneralProtectionFault0(pVCpu);
8810 }
8811 }
8812
8813 /* Feature control MSR's LOCK and VMXON bits. */
8814 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
8815 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8816 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8817 { /* likely */ }
8818 else
8819 {
8820 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8821 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8822 return iemRaiseGeneralProtectionFault0(pVCpu);
8823 }
8824
8825 /* Get the VMXON pointer from the location specified by the source memory operand. */
8826 RTGCPHYS GCPhysVmxon;
8827 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8828 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8829 { /* likely */ }
8830 else
8831 {
8832 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8833 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8834 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8835 return rcStrict;
8836 }
8837
8838 /* VMXON region pointer alignment. */
8839 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8840 { /* likely */ }
8841 else
8842 {
8843 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8844 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8845 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8846 iemVmxVmFailInvalid(pVCpu);
8847 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8848 return VINF_SUCCESS;
8849 }
8850
8851 /* VMXON physical-address width limits. */
8852 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8853 { /* likely */ }
8854 else
8855 {
8856 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8857 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8858 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8859 iemVmxVmFailInvalid(pVCpu);
8860 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8861 return VINF_SUCCESS;
8862 }
8863
8864 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8865 restriction imposed by our implementation. */
8866 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8867 { /* likely */ }
8868 else
8869 {
8870 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8871 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8872 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8873 iemVmxVmFailInvalid(pVCpu);
8874 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8875 return VINF_SUCCESS;
8876 }
8877
8878 /* Read the VMCS revision ID from the VMXON region. */
8879 VMXVMCSREVID VmcsRevId;
8880 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8881 if (RT_SUCCESS(rc))
8882 { /* likely */ }
8883 else
8884 {
8885 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8886 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8887 return rc;
8888 }
8889
8890 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8891 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8892 { /* likely */ }
8893 else
8894 {
8895 /* Revision ID mismatch. */
8896 if (!VmcsRevId.n.fIsShadowVmcs)
8897 {
8898 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8899 VmcsRevId.n.u31RevisionId));
8900 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8901 iemVmxVmFailInvalid(pVCpu);
8902 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8903 return VINF_SUCCESS;
8904 }
8905
8906 /* Shadow VMCS disallowed. */
8907 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8908 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8909 iemVmxVmFailInvalid(pVCpu);
8910 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8911 return VINF_SUCCESS;
8912 }
8913
8914 /*
8915 * Record that we're in VMX operation, block INIT, block and disable A20M.
8916 */
8917 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8918 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8919 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8920
8921 /* Clear address-range monitoring. */
8922 EMMonitorWaitClear(pVCpu);
8923 /** @todo NSTVMX: Intel PT. */
8924
8925 iemVmxVmSucceed(pVCpu);
8926 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8927 return VINF_SUCCESS;
8928 }
8929 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8930 {
8931 /* Nested-guest intercept. */
8932 if (pExitInfo)
8933 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8934 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8935 }
8936
8937 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8938
8939 /* CPL. */
8940 if (pVCpu->iem.s.uCpl > 0)
8941 {
8942 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8943 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8944 return iemRaiseGeneralProtectionFault0(pVCpu);
8945 }
8946
8947 /* VMXON when already in VMX root mode. */
8948 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8949 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8950 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8951 return VINF_SUCCESS;
8952}
8953
8954
8955/**
8956 * Implements 'VMXOFF'.
8957 *
8958 * @remarks Common VMX instruction checks are already expected to by the caller,
8959 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8960 */
8961IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8962{
8963 /* Nested-guest intercept. */
8964 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8965 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8966
8967 /* CPL. */
8968 if (pVCpu->iem.s.uCpl == 0)
8969 { /* likely */ }
8970 else
8971 {
8972 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8973 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8974 return iemRaiseGeneralProtectionFault0(pVCpu);
8975 }
8976
8977 /* Dual monitor treatment of SMIs and SMM. */
8978 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8979 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8980 { /* likely */ }
8981 else
8982 {
8983 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8984 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8985 return VINF_SUCCESS;
8986 }
8987
8988 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8989 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8990 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8991
8992 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8993 { /** @todo NSTVMX: Unblock SMI. */ }
8994
8995 EMMonitorWaitClear(pVCpu);
8996 /** @todo NSTVMX: Unblock and enable A20M. */
8997
8998 iemVmxVmSucceed(pVCpu);
8999 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9000 return VINF_SUCCESS;
9001}
9002
9003
9004/**
9005 * Implements 'VMXON'.
9006 */
9007IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9008{
9009 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9010}
9011
9012
9013/**
9014 * Implements 'VMLAUNCH'.
9015 */
9016IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9017{
9018 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9019}
9020
9021
9022/**
9023 * Implements 'VMRESUME'.
9024 */
9025IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9026{
9027 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9028}
9029
9030
9031/**
9032 * Implements 'VMPTRLD'.
9033 */
9034IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9035{
9036 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9037}
9038
9039
9040/**
9041 * Implements 'VMPTRST'.
9042 */
9043IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9044{
9045 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9046}
9047
9048
9049/**
9050 * Implements 'VMCLEAR'.
9051 */
9052IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9053{
9054 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9055}
9056
9057
9058/**
9059 * Implements 'VMWRITE' register.
9060 */
9061IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9062{
9063 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9064}
9065
9066
9067/**
9068 * Implements 'VMWRITE' memory.
9069 */
9070IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9071{
9072 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9073}
9074
9075
9076/**
9077 * Implements 'VMREAD' register (64-bit).
9078 */
9079IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9080{
9081 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9082}
9083
9084
9085/**
9086 * Implements 'VMREAD' register (32-bit).
9087 */
9088IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
9089{
9090 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
9091}
9092
9093
9094/**
9095 * Implements 'VMREAD' memory, 64-bit register.
9096 */
9097IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9098{
9099 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9100}
9101
9102
9103/**
9104 * Implements 'VMREAD' memory, 32-bit register.
9105 */
9106IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9107{
9108 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9109}
9110
9111
9112/**
9113 * Implements 'INVVPID'.
9114 */
9115IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9116{
9117 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9118}
9119
9120
9121#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9122/**
9123 * Implements 'INVEPT'.
9124 */
9125IEM_CIMPL_DEF_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType)
9126{
9127 return iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType, NULL /* pExitInfo */);
9128}
9129#endif
9130
9131
9132/**
9133 * Implements VMX's implementation of PAUSE.
9134 */
9135IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9136{
9137 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9138 {
9139 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9140 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9141 return rcStrict;
9142 }
9143
9144 /*
9145 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9146 * a VM-exit, the instruction operates normally.
9147 */
9148 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9149 return VINF_SUCCESS;
9150}
9151
9152#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9153
9154
9155/**
9156 * Implements 'VMCALL'.
9157 */
9158IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9159{
9160#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9161 /* Nested-guest intercept. */
9162 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9163 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9164#endif
9165
9166 /* Join forces with vmmcall. */
9167 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9168}
9169
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