VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 93338

Last change on this file since 93338 was 93338, checked in by vboxsync, 3 years ago

VMM/IEM: Nested VMX: bugref:10092 Fixed CR0-fixed bits validation when unrestricted-guest mode is available/used.
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 93338 2022-01-19 05:46:52Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason and logs. */
156# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 } while (0)
163
164/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
165# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
166 do \
167 { \
168 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
169 return VERR_VMX_VMEXIT_FAILED; \
170 } while (0)
171
172
173/*********************************************************************************************************************************
174* Global Variables *
175*********************************************************************************************************************************/
176/** @todo NSTVMX: The following VM-exit intercepts are pending:
177 * VMX_EXIT_IO_SMI
178 * VMX_EXIT_SMI
179 * VMX_EXIT_GETSEC
180 * VMX_EXIT_RSM
181 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
182 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
183 * VMX_EXIT_INVEPT
184 * VMX_EXIT_RDRAND
185 * VMX_EXIT_VMFUNC
186 * VMX_EXIT_ENCLS
187 * VMX_EXIT_RDSEED
188 * VMX_EXIT_PML_FULL
189 * VMX_EXIT_XSAVES
190 * VMX_EXIT_XRSTORS
191 */
192/**
193 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
194 *
195 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
196 * second dimension is the Index, see VMXVMCSFIELD.
197 */
198uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
199{
200 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
201 {
202 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
203 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
204 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
205 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
206 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
207 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
208 /* 27 */ UINT16_MAX,
209 },
210 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
211 {
212 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
213 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
214 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
215 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
216 },
217 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
218 {
219 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
220 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
221 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
222 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
223 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
224 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
225 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
226 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
227 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
228 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
229 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
230 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
231 /* 26-27 */ UINT16_MAX, UINT16_MAX
232 },
233 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
234 {
235 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
236 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
237 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
238 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
239 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
240 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
241 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
242 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
243 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
244 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
245 },
246 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
247 {
248 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
249 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
250 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
251 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
252 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
253 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
254 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
255 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
256 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
257 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
258 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
259 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
260 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
261 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
262 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
263 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
264 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
265 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
266 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
267 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
268 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
269 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
270 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
271 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
272 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
273 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
274 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
275 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
276 },
277 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
278 {
279 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
280 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
281 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
282 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
283 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
284 },
285 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
286 {
287 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
288 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
289 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
290 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
291 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
292 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
293 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
294 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
295 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
296 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
297 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
298 /* 11 */ UINT16_MAX,
299 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
300 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
301 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
302 },
303 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
304 {
305 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
306 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
307 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
308 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
309 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
310 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
311 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
312 },
313 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
314 {
315 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
316 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
317 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
318 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
319 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
320 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
321 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
322 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
323 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
324 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
325 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
326 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
327 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
328 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
329 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
330 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
331 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
332 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
333 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
334 /* 26-27 */ UINT16_MAX, UINT16_MAX
335 },
336 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
337 {
338 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
339 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
340 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
341 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
342 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
343 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
344 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
345 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
346 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
347 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
348 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
349 },
350 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
351 {
352 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
353 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
354 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
355 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
356 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
357 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
358 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
359 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
360 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
361 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
362 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
363 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
364 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
365 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
366 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
367 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
368 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
369 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
370 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
371 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
372 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
373 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
374 /* 22 */ UINT16_MAX,
375 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
376 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
377 },
378 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
379 {
380 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
381 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
382 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
383 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
385 },
386 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
387 {
388 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
389 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
390 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
391 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
392 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
393 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
394 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
395 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
396 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
397 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
398 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
399 },
400 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
401 {
402 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
403 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
404 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
405 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
406 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
407 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
408 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
409 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
410 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
411 },
412 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
413 {
414 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
415 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
416 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
417 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
418 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
419 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
420 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
421 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
422 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
423 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
424 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
425 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
426 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
427 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
428 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
429 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
430 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
431 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
432 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
433 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
434 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
435 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
436 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
437 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
438 },
439 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
440 {
441 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
442 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
443 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
444 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
445 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
446 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
447 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
448 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
449 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
450 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
451 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
452 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
453 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
454 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
455 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
456 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
457 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
458 }
459};
460
461
462/**
463 * Gets CR0 fixed-0 bits in VMX non-root mode.
464 *
465 * We do this rather than fetching what we report to the guest (in
466 * IA32_VMX_CR0_FIXED0 MSR) because real hardware (and so do we) report the same
467 * values regardless of whether unrestricted-guest feature is available on the CPU.
468 *
469 * @returns CR0 fixed-0 bits.
470 * @param pVCpu The cross context virtual CPU structure.
471 */
472DECLINLINE(uint64_t) iemVmxGetCr0Fixed0(PCVMCPUCC pVCpu)
473{
474 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
475 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
476
477 static uint64_t const s_auCr0Fixed0[2] = { VMX_V_CR0_FIXED0, VMX_V_CR0_FIXED0_UX };
478 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
479 uint8_t const fUnrestrictedGuest = !!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
480 uint64_t const uCr0Fixed0 = s_auCr0Fixed0[fUnrestrictedGuest];
481 Assert(!(uCr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
482 return uCr0Fixed0;
483}
484
485
486/**
487 * Gets a host selector from the VMCS.
488 *
489 * @param pVmcs Pointer to the virtual VMCS.
490 * @param iSelReg The index of the segment register (X86_SREG_XXX).
491 */
492DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
493{
494 Assert(iSegReg < X86_SREG_COUNT);
495 RTSEL HostSel;
496 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
497 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
498 uint8_t const uWidthType = (uWidth << 2) | uType;
499 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
500 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
501 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
502 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
503 uint8_t const *pbField = pbVmcs + offField;
504 HostSel = *(uint16_t *)pbField;
505 return HostSel;
506}
507
508
509/**
510 * Sets a guest segment register in the VMCS.
511 *
512 * @param pVmcs Pointer to the virtual VMCS.
513 * @param iSegReg The index of the segment register (X86_SREG_XXX).
514 * @param pSelReg Pointer to the segment register.
515 */
516IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
517{
518 Assert(pSelReg);
519 Assert(iSegReg < X86_SREG_COUNT);
520
521 /* Selector. */
522 {
523 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
524 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
525 uint8_t const uWidthType = (uWidth << 2) | uType;
526 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
527 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
528 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
529 uint8_t *pbVmcs = (uint8_t *)pVmcs;
530 uint8_t *pbField = pbVmcs + offField;
531 *(uint16_t *)pbField = pSelReg->Sel;
532 }
533
534 /* Limit. */
535 {
536 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
537 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
538 uint8_t const uWidthType = (uWidth << 2) | uType;
539 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
540 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
541 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
542 uint8_t *pbVmcs = (uint8_t *)pVmcs;
543 uint8_t *pbField = pbVmcs + offField;
544 *(uint32_t *)pbField = pSelReg->u32Limit;
545 }
546
547 /* Base. */
548 {
549 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
550 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
551 uint8_t const uWidthType = (uWidth << 2) | uType;
552 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
553 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
554 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
555 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
556 uint8_t const *pbField = pbVmcs + offField;
557 *(uint64_t *)pbField = pSelReg->u64Base;
558 }
559
560 /* Attributes. */
561 {
562 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
563 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
564 | X86DESCATTR_UNUSABLE;
565 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
566 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
567 uint8_t const uWidthType = (uWidth << 2) | uType;
568 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
569 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
570 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
571 uint8_t *pbVmcs = (uint8_t *)pVmcs;
572 uint8_t *pbField = pbVmcs + offField;
573 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
574 }
575}
576
577
578/**
579 * Gets a guest segment register from the VMCS.
580 *
581 * @returns VBox status code.
582 * @param pVmcs Pointer to the virtual VMCS.
583 * @param iSegReg The index of the segment register (X86_SREG_XXX).
584 * @param pSelReg Where to store the segment register (only updated when
585 * VINF_SUCCESS is returned).
586 *
587 * @remarks Warning! This does not validate the contents of the retrieved segment
588 * register.
589 */
590IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
591{
592 Assert(pSelReg);
593 Assert(iSegReg < X86_SREG_COUNT);
594
595 /* Selector. */
596 uint16_t u16Sel;
597 {
598 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
599 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
600 uint8_t const uWidthType = (uWidth << 2) | uType;
601 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
602 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
603 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
604 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
605 uint8_t const *pbField = pbVmcs + offField;
606 u16Sel = *(uint16_t *)pbField;
607 }
608
609 /* Limit. */
610 uint32_t u32Limit;
611 {
612 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
613 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
614 uint8_t const uWidthType = (uWidth << 2) | uType;
615 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
616 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
617 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
618 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
619 uint8_t const *pbField = pbVmcs + offField;
620 u32Limit = *(uint32_t *)pbField;
621 }
622
623 /* Base. */
624 uint64_t u64Base;
625 {
626 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
627 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
628 uint8_t const uWidthType = (uWidth << 2) | uType;
629 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
630 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
631 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
632 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
633 uint8_t const *pbField = pbVmcs + offField;
634 u64Base = *(uint64_t *)pbField;
635 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
636 }
637
638 /* Attributes. */
639 uint32_t u32Attr;
640 {
641 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
642 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
643 uint8_t const uWidthType = (uWidth << 2) | uType;
644 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
645 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
646 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
647 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
648 uint8_t const *pbField = pbVmcs + offField;
649 u32Attr = *(uint32_t *)pbField;
650 }
651
652 pSelReg->Sel = u16Sel;
653 pSelReg->ValidSel = u16Sel;
654 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
655 pSelReg->u32Limit = u32Limit;
656 pSelReg->u64Base = u64Base;
657 pSelReg->Attr.u = u32Attr;
658 return VINF_SUCCESS;
659}
660
661
662/**
663 * Converts an IEM exception event type to a VMX event type.
664 *
665 * @returns The VMX event type.
666 * @param uVector The interrupt / exception vector.
667 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
668 */
669DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
670{
671 /* Paranoia (callers may use these interchangeably). */
672 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
673 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
674 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
675 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
676 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
677 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
678 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
679 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
680 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
681 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
682 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
683 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
684
685 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
686 {
687 if (uVector == X86_XCPT_NMI)
688 return VMX_EXIT_INT_INFO_TYPE_NMI;
689 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
690 }
691
692 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
693 {
694 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
695 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
696 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
697 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
698 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
699 }
700
701 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
702 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
703}
704
705
706/**
707 * Determines whether the guest is using PAE paging given the VMCS.
708 *
709 * @returns @c true if PAE paging mode is used, @c false otherwise.
710 * @param pVmcs Pointer to the virtual VMCS.
711 */
712DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
713{
714 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
715 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
716 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
717}
718
719
720/**
721 * Sets the Exit qualification VMCS field.
722 *
723 * @param pVCpu The cross context virtual CPU structure.
724 * @param u64ExitQual The Exit qualification.
725 */
726DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
727{
728 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
729}
730
731
732/**
733 * Sets the VM-exit interruption information field.
734 *
735 * @param pVCpu The cross context virtual CPU structure.
736 * @param uExitIntInfo The VM-exit interruption information.
737 */
738DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
739{
740 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
741}
742
743
744/**
745 * Sets the VM-exit interruption error code.
746 *
747 * @param pVCpu The cross context virtual CPU structure.
748 * @param uErrCode The error code.
749 */
750DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
751{
752 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
753}
754
755
756/**
757 * Sets the IDT-vectoring information field.
758 *
759 * @param pVCpu The cross context virtual CPU structure.
760 * @param uIdtVectorInfo The IDT-vectoring information.
761 */
762DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
763{
764 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
765}
766
767
768/**
769 * Sets the IDT-vectoring error code field.
770 *
771 * @param pVCpu The cross context virtual CPU structure.
772 * @param uErrCode The error code.
773 */
774DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
775{
776 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
777}
778
779
780/**
781 * Sets the VM-exit guest-linear address VMCS field.
782 *
783 * @param pVCpu The cross context virtual CPU structure.
784 * @param uGuestLinearAddr The VM-exit guest-linear address.
785 */
786DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
787{
788 /* Bits 63:32 of guest-linear address MBZ if the guest isn't in long mode prior to the VM-exit. */
789 Assert(CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)) || !(uGuestLinearAddr & UINT64_C(0xffffffff00000000)));
790 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
791}
792
793
794/**
795 * Sets the VM-exit guest-physical address VMCS field.
796 *
797 * @param pVCpu The cross context virtual CPU structure.
798 * @param uGuestPhysAddr The VM-exit guest-physical address.
799 */
800DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
801{
802 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
803}
804
805
806/**
807 * Sets the VM-exit instruction length VMCS field.
808 *
809 * @param pVCpu The cross context virtual CPU structure.
810 * @param cbInstr The VM-exit instruction length in bytes.
811 *
812 * @remarks Callers may clear this field to 0. Hence, this function does not check
813 * the validity of the instruction length.
814 */
815DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
816{
817 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
818}
819
820
821/**
822 * Sets the VM-exit instruction info. VMCS field.
823 *
824 * @param pVCpu The cross context virtual CPU structure.
825 * @param uExitInstrInfo The VM-exit instruction information.
826 */
827DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
828{
829 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
830}
831
832
833/**
834 * Sets the guest pending-debug exceptions field.
835 *
836 * @param pVCpu The cross context virtual CPU structure.
837 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
838 */
839DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
840{
841 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
842 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
843}
844
845
846/**
847 * Implements VMSucceed for VMX instruction success.
848 *
849 * @param pVCpu The cross context virtual CPU structure.
850 */
851DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
852{
853 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
854}
855
856
857/**
858 * Implements VMFailInvalid for VMX instruction failure.
859 *
860 * @param pVCpu The cross context virtual CPU structure.
861 */
862DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
863{
864 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
865}
866
867
868/**
869 * Implements VMFail for VMX instruction failure.
870 *
871 * @param pVCpu The cross context virtual CPU structure.
872 * @param enmInsErr The VM instruction error.
873 */
874DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
875{
876 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
877}
878
879
880/**
881 * Checks if the given auto-load/store MSR area count is valid for the
882 * implementation.
883 *
884 * @returns @c true if it's within the valid limit, @c false otherwise.
885 * @param pVCpu The cross context virtual CPU structure.
886 * @param uMsrCount The MSR area count to check.
887 */
888DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
889{
890 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
891 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
892 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
893 if (uMsrCount <= cMaxSupportedMsrs)
894 return true;
895 return false;
896}
897
898
899/**
900 * Flushes the current VMCS contents back to guest memory.
901 *
902 * @returns VBox status code.
903 * @param pVCpu The cross context virtual CPU structure.
904 */
905DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
906{
907 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
908 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
909 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
910 return rc;
911}
912
913
914/**
915 * Populates the current VMCS contents from guest memory.
916 *
917 * @returns VBox status code.
918 * @param pVCpu The cross context virtual CPU structure.
919 */
920DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
921{
922 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
923 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
924 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
925 return rc;
926}
927
928
929/**
930 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
931 *
932 * @param pVCpu The cross context virtual CPU structure.
933 */
934DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPUCC pVCpu, uint8_t cbInstr)
935{
936 iemVmxVmSucceed(pVCpu);
937 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
938}
939
940
941/**
942 * Gets the instruction diagnostic for segment base checks during VM-entry of a
943 * nested-guest.
944 *
945 * @param iSegReg The segment index (X86_SREG_XXX).
946 */
947IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
948{
949 switch (iSegReg)
950 {
951 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
952 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
953 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
954 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
955 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
956 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
957 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
958 }
959}
960
961
962/**
963 * Gets the instruction diagnostic for segment base checks during VM-entry of a
964 * nested-guest that is in Virtual-8086 mode.
965 *
966 * @param iSegReg The segment index (X86_SREG_XXX).
967 */
968IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
969{
970 switch (iSegReg)
971 {
972 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
973 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
974 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
975 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
976 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
977 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
978 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
979 }
980}
981
982
983/**
984 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
985 * nested-guest that is in Virtual-8086 mode.
986 *
987 * @param iSegReg The segment index (X86_SREG_XXX).
988 */
989IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
990{
991 switch (iSegReg)
992 {
993 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
994 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
995 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
996 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
997 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
998 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
999 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1000 }
1001}
1002
1003
1004/**
1005 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1006 * nested-guest that is in Virtual-8086 mode.
1007 *
1008 * @param iSegReg The segment index (X86_SREG_XXX).
1009 */
1010IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1011{
1012 switch (iSegReg)
1013 {
1014 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1015 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1016 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1017 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1018 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1019 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1020 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1021 }
1022}
1023
1024
1025/**
1026 * Gets the instruction diagnostic for segment attributes reserved bits failure
1027 * during VM-entry of a nested-guest.
1028 *
1029 * @param iSegReg The segment index (X86_SREG_XXX).
1030 */
1031IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1032{
1033 switch (iSegReg)
1034 {
1035 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1036 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1037 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1038 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1039 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1040 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1041 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1042 }
1043}
1044
1045
1046/**
1047 * Gets the instruction diagnostic for segment attributes descriptor-type
1048 * (code/segment or system) failure during VM-entry of a nested-guest.
1049 *
1050 * @param iSegReg The segment index (X86_SREG_XXX).
1051 */
1052IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1053{
1054 switch (iSegReg)
1055 {
1056 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1057 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1058 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1059 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1060 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1061 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1062 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1063 }
1064}
1065
1066
1067/**
1068 * Gets the instruction diagnostic for segment attributes descriptor-type
1069 * (code/segment or system) failure during VM-entry of a nested-guest.
1070 *
1071 * @param iSegReg The segment index (X86_SREG_XXX).
1072 */
1073IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1074{
1075 switch (iSegReg)
1076 {
1077 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1078 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1079 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1080 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1081 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1082 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1083 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1084 }
1085}
1086
1087
1088/**
1089 * Gets the instruction diagnostic for segment attribute granularity failure during
1090 * VM-entry of a nested-guest.
1091 *
1092 * @param iSegReg The segment index (X86_SREG_XXX).
1093 */
1094IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1095{
1096 switch (iSegReg)
1097 {
1098 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1099 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1100 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1101 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1102 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1103 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1104 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1105 }
1106}
1107
1108/**
1109 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1110 * VM-entry of a nested-guest.
1111 *
1112 * @param iSegReg The segment index (X86_SREG_XXX).
1113 */
1114IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1115{
1116 switch (iSegReg)
1117 {
1118 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1119 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1120 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1121 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1122 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1123 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1124 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1125 }
1126}
1127
1128
1129/**
1130 * Gets the instruction diagnostic for segment attribute type accessed failure
1131 * during VM-entry of a nested-guest.
1132 *
1133 * @param iSegReg The segment index (X86_SREG_XXX).
1134 */
1135IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1136{
1137 switch (iSegReg)
1138 {
1139 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1140 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1141 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1142 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1143 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1144 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1145 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1146 }
1147}
1148
1149
1150/**
1151 * Saves the guest control registers, debug registers and some MSRs are part of
1152 * VM-exit.
1153 *
1154 * @param pVCpu The cross context virtual CPU structure.
1155 */
1156IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu)
1157{
1158 /*
1159 * Saves the guest control registers, debug registers and some MSRs.
1160 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1161 */
1162 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1163
1164 /* Save control registers. */
1165 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1166 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1167 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1168
1169 /* Save SYSENTER CS, ESP, EIP. */
1170 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1171 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1172 {
1173 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1174 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1175 }
1176 else
1177 {
1178 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1179 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1180 }
1181
1182 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1183 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1184 {
1185 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1186 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1187 }
1188
1189 /* Save PAT MSR. */
1190 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1191 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1192
1193 /* Save EFER MSR. */
1194 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1195 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1196
1197 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1198 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1199
1200 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1201}
1202
1203
1204/**
1205 * Saves the guest force-flags in preparation of entering the nested-guest.
1206 *
1207 * @param pVCpu The cross context virtual CPU structure.
1208 */
1209IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu)
1210{
1211 /* We shouldn't be called multiple times during VM-entry. */
1212 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1213
1214 /* MTF should not be set outside VMX non-root mode. */
1215 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1216
1217 /*
1218 * Preserve the required force-flags.
1219 *
1220 * We cache and clear force-flags that would affect the execution of the
1221 * nested-guest. Cached flags are then restored while returning to the guest
1222 * if necessary.
1223 *
1224 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1225 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1226 * instruction. Interrupt inhibition for any nested-guest instruction
1227 * is supplied by the guest-interruptibility state VMCS field and will
1228 * be set up as part of loading the guest state.
1229 *
1230 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1231 * successful VM-entry (due to invalid guest-state) need to continue
1232 * blocking NMIs if it was in effect before VM-entry.
1233 *
1234 * - MTF need not be preserved as it's used only in VMX non-root mode and
1235 * is supplied through the VM-execution controls.
1236 *
1237 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1238 * we will be able to generate interrupts that may cause VM-exits for
1239 * the nested-guest.
1240 */
1241 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1242}
1243
1244
1245/**
1246 * Restores the guest force-flags in preparation of exiting the nested-guest.
1247 *
1248 * @param pVCpu The cross context virtual CPU structure.
1249 */
1250IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu)
1251{
1252 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1253 {
1254 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1255 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1256 }
1257}
1258
1259
1260/**
1261 * Performs the VMX transition to/from VMX non-root mode.
1262 *
1263 * @param pVCpu The cross context virtual CPU structure.
1264*/
1265IEM_STATIC int iemVmxTransition(PVMCPUCC pVCpu)
1266{
1267 /*
1268 * Inform PGM about paging mode changes.
1269 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1270 * see comment in iemMemPageTranslateAndCheckAccess().
1271 */
1272 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1273 true /* fForce */);
1274 AssertRCReturn(rc, rc);
1275
1276 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1277 IEMTlbInvalidateAll(pVCpu, false /*fVmm*/);
1278
1279 /* Inform CPUM (recompiler), can later be removed. */
1280 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1281
1282 /* Re-initialize IEM cache/state after the drastic mode switch. */
1283 iemReInitExec(pVCpu);
1284 return rc;
1285}
1286
1287
1288/**
1289 * Calculates the current VMX-preemption timer value.
1290 *
1291 * @returns The current VMX-preemption timer value.
1292 * @param pVCpu The cross context virtual CPU structure.
1293 */
1294IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu)
1295{
1296 /*
1297 * Assume the following:
1298 * PreemptTimerShift = 5
1299 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1300 * EntryTick = 50000 (TSC at time of VM-entry)
1301 *
1302 * CurTick Delta PreemptTimerVal
1303 * ----------------------------------
1304 * 60000 10000 2
1305 * 80000 30000 1
1306 * 90000 40000 0 -> VM-exit.
1307 *
1308 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1309 * The saved VMX-preemption timer value is calculated as follows:
1310 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1311 * E.g.:
1312 * Delta = 10000
1313 * Tmp = 10000 / (2 * 10000) = 0.5
1314 * NewPt = 2 - 0.5 = 2
1315 * Delta = 30000
1316 * Tmp = 30000 / (2 * 10000) = 1.5
1317 * NewPt = 2 - 1.5 = 1
1318 * Delta = 40000
1319 * Tmp = 40000 / 20000 = 2
1320 * NewPt = 2 - 2 = 0
1321 */
1322 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1323 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1324 if (uVmcsPreemptVal > 0)
1325 {
1326 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1327 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1328 uint64_t const uDelta = uCurTick - uEntryTick;
1329 uint32_t const uPreemptTimer = uVmcsPreemptVal
1330 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1331 return uPreemptTimer;
1332 }
1333 return 0;
1334}
1335
1336
1337/**
1338 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1339 *
1340 * @param pVCpu The cross context virtual CPU structure.
1341 */
1342IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu)
1343{
1344 /*
1345 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1346 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1347 */
1348 /* CS, SS, ES, DS, FS, GS. */
1349 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1350 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1351 {
1352 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1353 if (!pSelReg->Attr.n.u1Unusable)
1354 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1355 else
1356 {
1357 /*
1358 * For unusable segments the attributes are undefined except for CS and SS.
1359 * For the rest we don't bother preserving anything but the unusable bit.
1360 */
1361 switch (iSegReg)
1362 {
1363 case X86_SREG_CS:
1364 pVmcs->GuestCs = pSelReg->Sel;
1365 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1366 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1367 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1368 | X86DESCATTR_UNUSABLE);
1369 break;
1370
1371 case X86_SREG_SS:
1372 pVmcs->GuestSs = pSelReg->Sel;
1373 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1374 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1375 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1376 break;
1377
1378 case X86_SREG_DS:
1379 pVmcs->GuestDs = pSelReg->Sel;
1380 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1381 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1382 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1383 break;
1384
1385 case X86_SREG_ES:
1386 pVmcs->GuestEs = pSelReg->Sel;
1387 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1388 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1389 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1390 break;
1391
1392 case X86_SREG_FS:
1393 pVmcs->GuestFs = pSelReg->Sel;
1394 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1395 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1396 break;
1397
1398 case X86_SREG_GS:
1399 pVmcs->GuestGs = pSelReg->Sel;
1400 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1401 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1402 break;
1403 }
1404 }
1405 }
1406
1407 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1408 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1409 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1410 | X86DESCATTR_UNUSABLE;
1411 /* LDTR. */
1412 {
1413 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1414 pVmcs->GuestLdtr = pSelReg->Sel;
1415 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1416 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1417 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1418 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1419 }
1420
1421 /* TR. */
1422 {
1423 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1424 pVmcs->GuestTr = pSelReg->Sel;
1425 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1426 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1427 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1428 }
1429
1430 /* GDTR. */
1431 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1432 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1433
1434 /* IDTR. */
1435 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1436 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1437}
1438
1439
1440/**
1441 * Saves guest non-register state as part of VM-exit.
1442 *
1443 * @param pVCpu The cross context virtual CPU structure.
1444 * @param uExitReason The VM-exit reason.
1445 */
1446IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason)
1447{
1448 /*
1449 * Save guest non-register state.
1450 * See Intel spec. 27.3.4 "Saving Non-Register State".
1451 */
1452 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1453
1454 /*
1455 * Activity state.
1456 * Most VM-exits will occur in the active state. However, if the first instruction
1457 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1458 * the VM-exit will be from the HLT activity state.
1459 *
1460 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1461 */
1462 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1463 * not? */
1464 EMSTATE const enmActivityState = EMGetState(pVCpu);
1465 switch (enmActivityState)
1466 {
1467 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1468 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1469 }
1470
1471 /*
1472 * Interruptibility-state.
1473 */
1474 /* NMI. */
1475 pVmcs->u32GuestIntrState = 0;
1476 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1477 {
1478 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1479 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1480 }
1481 else
1482 {
1483 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1484 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1485 }
1486
1487 /* Blocking-by-STI. */
1488 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1489 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1490 {
1491 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1492 * currently. */
1493 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1494 }
1495 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1496
1497 /*
1498 * Pending debug exceptions.
1499 *
1500 * For VM-exits where it is not applicable, we can safely zero out the field.
1501 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1502 */
1503 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1504 && uExitReason != VMX_EXIT_SMI
1505 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1506 && !VMXIsVmexitTrapLike(uExitReason))
1507 {
1508 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1509 * block-by-MovSS is in effect. */
1510 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1511 }
1512
1513 /*
1514 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1515 *
1516 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1517 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1518 */
1519 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1520 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1521 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1522
1523 /*
1524 * PAE PDPTEs.
1525 *
1526 * If EPT is enabled and PAE paging was used at the time of the VM-exit,
1527 * the PDPTEs are saved from the VMCS. Otherwise they're undefined but
1528 * we zero them for consistency.
1529 */
1530 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1531 {
1532 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
1533 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1534 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
1535 {
1536 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1537 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1538 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1539 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1540 }
1541 else
1542 {
1543 pVmcs->u64GuestPdpte0.u = 0;
1544 pVmcs->u64GuestPdpte1.u = 0;
1545 pVmcs->u64GuestPdpte2.u = 0;
1546 pVmcs->u64GuestPdpte3.u = 0;
1547 }
1548
1549 /* Clear PGM's copy of the EPT pointer for added safety. */
1550 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1551 }
1552 else
1553 {
1554 pVmcs->u64GuestPdpte0.u = 0;
1555 pVmcs->u64GuestPdpte1.u = 0;
1556 pVmcs->u64GuestPdpte2.u = 0;
1557 pVmcs->u64GuestPdpte3.u = 0;
1558 }
1559}
1560
1561
1562/**
1563 * Saves the guest-state as part of VM-exit.
1564 *
1565 * @returns VBox status code.
1566 * @param pVCpu The cross context virtual CPU structure.
1567 * @param uExitReason The VM-exit reason.
1568 */
1569IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason)
1570{
1571 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1572 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1573
1574 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1575 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1576 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1577
1578 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1579}
1580
1581
1582/**
1583 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1584 *
1585 * @returns VBox status code.
1586 * @param pVCpu The cross context virtual CPU structure.
1587 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1588 */
1589IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1590{
1591 /*
1592 * Save guest MSRs.
1593 * See Intel spec. 27.4 "Saving MSRs".
1594 */
1595 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1596 const char * const pszFailure = "VMX-abort";
1597
1598 /*
1599 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1600 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1601 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1602 */
1603 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1604 if (!cMsrs)
1605 return VINF_SUCCESS;
1606
1607 /*
1608 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1609 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1610 * implementation causes a VMX-abort followed by a triple-fault.
1611 */
1612 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1613 if (fIsMsrCountValid)
1614 { /* likely */ }
1615 else
1616 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1617
1618 /*
1619 * Optimization if the nested hypervisor is using the same guest-physical page for both
1620 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1621 */
1622 PVMXAUTOMSR pMsrArea;
1623 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1624 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1625 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1626 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1627 else
1628 {
1629 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1630 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1631 if (RT_SUCCESS(rc))
1632 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1633 else
1634 {
1635 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1636 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1637 }
1638 }
1639
1640 /*
1641 * Update VM-exit MSR store area.
1642 */
1643 PVMXAUTOMSR pMsr = pMsrArea;
1644 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1645 {
1646 if ( !pMsr->u32Reserved
1647 && pMsr->u32Msr != MSR_IA32_SMBASE
1648 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1649 {
1650 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1651 if (rcStrict == VINF_SUCCESS)
1652 continue;
1653
1654 /*
1655 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1656 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1657 * recording the MSR index in the auxiliary info. field and indicated further by our
1658 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1659 * if possible, or come up with a better, generic solution.
1660 */
1661 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1662 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1663 ? kVmxVDiag_Vmexit_MsrStoreRing3
1664 : kVmxVDiag_Vmexit_MsrStore;
1665 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1666 }
1667 else
1668 {
1669 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1670 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1671 }
1672 }
1673
1674 /*
1675 * Commit the VM-exit MSR store are to guest memory.
1676 */
1677 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1678 if (RT_SUCCESS(rc))
1679 return VINF_SUCCESS;
1680
1681 NOREF(uExitReason);
1682 NOREF(pszFailure);
1683
1684 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1685 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1686}
1687
1688
1689/**
1690 * Performs a VMX abort (due to an fatal error during VM-exit).
1691 *
1692 * @returns Strict VBox status code.
1693 * @param pVCpu The cross context virtual CPU structure.
1694 * @param enmAbort The VMX abort reason.
1695 */
1696IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort)
1697{
1698 /*
1699 * Perform the VMX abort.
1700 * See Intel spec. 27.7 "VMX Aborts".
1701 */
1702 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1703
1704 /* We don't support SMX yet. */
1705 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1706 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1707 {
1708 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1709 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1710 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1711 }
1712
1713 return VINF_EM_TRIPLE_FAULT;
1714}
1715
1716
1717/**
1718 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1719 *
1720 * @param pVCpu The cross context virtual CPU structure.
1721 */
1722IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu)
1723{
1724 /*
1725 * Load host control registers, debug registers and MSRs.
1726 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1727 */
1728 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1729 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1730
1731 /* CR0. */
1732 {
1733 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1734 uint64_t const uCr0Mb1 = iemVmxGetCr0Fixed0(pVCpu);
1735 uint64_t const uCr0Mb0 = VMX_V_CR0_FIXED1;
1736 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1737 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1738 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1739 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1740
1741 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1742 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1743 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1744 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1745 }
1746
1747 /* CR4. */
1748 {
1749 /* CR4 fixed bits are not modified. */
1750 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1751 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1752 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1753 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1754 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1755 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1756 if (fHostInLongMode)
1757 uValidHostCr4 |= X86_CR4_PAE;
1758 else
1759 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1760
1761 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1762 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1763 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1764 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1765 }
1766
1767 /* CR3 (host value validated while checking host-state during VM-entry). */
1768 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1769
1770 /* DR7. */
1771 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1772
1773 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1774
1775 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1776 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1777 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1778 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1779
1780 /* FS, GS bases are loaded later while we load host segment registers. */
1781
1782 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1783 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1784 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1785 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1786 {
1787 if (fHostInLongMode)
1788 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1789 else
1790 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1791 }
1792
1793 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1794
1795 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1796 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1797 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1798
1799 /* We don't support IA32_BNDCFGS MSR yet. */
1800}
1801
1802
1803/**
1804 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1805 *
1806 * @param pVCpu The cross context virtual CPU structure.
1807 */
1808IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu)
1809{
1810 /*
1811 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1812 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1813 *
1814 * Warning! Be careful to not touch fields that are reserved by VT-x,
1815 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1816 */
1817 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1818 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1819
1820 /* CS, SS, ES, DS, FS, GS. */
1821 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1822 {
1823 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1824 bool const fUnusable = RT_BOOL(HostSel == 0);
1825 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1826
1827 /* Selector. */
1828 pSelReg->Sel = HostSel;
1829 pSelReg->ValidSel = HostSel;
1830 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1831
1832 /* Limit. */
1833 pSelReg->u32Limit = 0xffffffff;
1834
1835 /* Base. */
1836 pSelReg->u64Base = 0;
1837
1838 /* Attributes. */
1839 if (iSegReg == X86_SREG_CS)
1840 {
1841 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1842 pSelReg->Attr.n.u1DescType = 1;
1843 pSelReg->Attr.n.u2Dpl = 0;
1844 pSelReg->Attr.n.u1Present = 1;
1845 pSelReg->Attr.n.u1Long = fHostInLongMode;
1846 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1847 pSelReg->Attr.n.u1Granularity = 1;
1848 Assert(!pSelReg->Attr.n.u1Unusable);
1849 Assert(!fUnusable);
1850 }
1851 else
1852 {
1853 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1854 pSelReg->Attr.n.u1DescType = 1;
1855 pSelReg->Attr.n.u2Dpl = 0;
1856 pSelReg->Attr.n.u1Present = 1;
1857 pSelReg->Attr.n.u1DefBig = 1;
1858 pSelReg->Attr.n.u1Granularity = 1;
1859 pSelReg->Attr.n.u1Unusable = fUnusable;
1860 }
1861 }
1862
1863 /* FS base. */
1864 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1865 || fHostInLongMode)
1866 {
1867 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1868 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1869 }
1870
1871 /* GS base. */
1872 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1873 || fHostInLongMode)
1874 {
1875 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1876 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1877 }
1878
1879 /* TR. */
1880 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1881 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1882 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1883 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1884 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1885 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1886 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1887 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1888 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1889 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1890 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1891 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1892 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1893
1894 /* LDTR (Warning! do not touch the base and limits here). */
1895 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1896 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1897 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1898 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1899
1900 /* GDTR. */
1901 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1902 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1903 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1904
1905 /* IDTR.*/
1906 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1907 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1908 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1909}
1910
1911
1912/**
1913 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1914 *
1915 * @returns VBox status code.
1916 * @param pVCpu The cross context virtual CPU structure.
1917 * @param uExitReason The VMX instruction name (for logging purposes).
1918 */
1919IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason)
1920{
1921 /*
1922 * Load host MSRs.
1923 * See Intel spec. 27.6 "Loading MSRs".
1924 */
1925 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1926 const char * const pszFailure = "VMX-abort";
1927
1928 /*
1929 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1930 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1931 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1932 */
1933 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1934 if (!cMsrs)
1935 return VINF_SUCCESS;
1936
1937 /*
1938 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1939 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1940 * implementation causes a VMX-abort followed by a triple-fault.
1941 */
1942 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1943 if (fIsMsrCountValid)
1944 { /* likely */ }
1945 else
1946 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1947
1948 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1949 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1950 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1951 if (RT_SUCCESS(rc))
1952 {
1953 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1954 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1955 {
1956 if ( !pMsr->u32Reserved
1957 && pMsr->u32Msr != MSR_K8_FS_BASE
1958 && pMsr->u32Msr != MSR_K8_GS_BASE
1959 && pMsr->u32Msr != MSR_K6_EFER
1960 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1961 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1962 {
1963 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1964 if (rcStrict == VINF_SUCCESS)
1965 continue;
1966
1967 /*
1968 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1969 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1970 * recording the MSR index in the auxiliary info. field and indicated further by our
1971 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1972 * if possible, or come up with a better, generic solution.
1973 */
1974 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1975 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1976 ? kVmxVDiag_Vmexit_MsrLoadRing3
1977 : kVmxVDiag_Vmexit_MsrLoad;
1978 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1979 }
1980 else
1981 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1982 }
1983 }
1984 else
1985 {
1986 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1987 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1988 }
1989
1990 NOREF(uExitReason);
1991 NOREF(pszFailure);
1992 return VINF_SUCCESS;
1993}
1994
1995
1996/**
1997 * Loads the host state as part of VM-exit.
1998 *
1999 * @returns Strict VBox status code.
2000 * @param pVCpu The cross context virtual CPU structure.
2001 * @param uExitReason The VM-exit reason (for logging purposes).
2002 */
2003IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason)
2004{
2005 /*
2006 * Load host state.
2007 * See Intel spec. 27.5 "Loading Host State".
2008 */
2009 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2010 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2011
2012 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2013 if ( CPUMIsGuestInLongMode(pVCpu)
2014 && !fHostInLongMode)
2015 {
2016 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2017 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2018 }
2019
2020 /*
2021 * Check host PAE PDPTEs prior to loading the host state.
2022 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2023 */
2024 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2025 && !fHostInLongMode
2026 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2027 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2028 {
2029 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2030 if (RT_SUCCESS(rc))
2031 { /* likely*/ }
2032 else
2033 {
2034 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2035 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2036 }
2037 }
2038
2039 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2040 iemVmxVmexitLoadHostSegRegs(pVCpu);
2041
2042 /*
2043 * Load host RIP, RSP and RFLAGS.
2044 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2045 */
2046 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2047 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2048 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2049
2050 /* Clear address range monitoring. */
2051 EMMonitorWaitClear(pVCpu);
2052
2053 /* Perform the VMX transition (PGM updates). */
2054 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2055 if (rcStrict == VINF_SUCCESS)
2056 { /* likely */ }
2057 else if (RT_SUCCESS(rcStrict))
2058 {
2059 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2060 uExitReason));
2061 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2062 }
2063 else
2064 {
2065 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2066 return VBOXSTRICTRC_VAL(rcStrict);
2067 }
2068
2069 Assert(rcStrict == VINF_SUCCESS);
2070
2071 /* Load MSRs from the VM-exit auto-load MSR area. */
2072 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2073 if (RT_FAILURE(rc))
2074 {
2075 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2076 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2077 }
2078 return VINF_SUCCESS;
2079}
2080
2081
2082/**
2083 * Gets VM-exit instruction information along with any displacement for an
2084 * instruction VM-exit.
2085 *
2086 * @returns The VM-exit instruction information.
2087 * @param pVCpu The cross context virtual CPU structure.
2088 * @param uExitReason The VM-exit reason.
2089 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2090 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2091 * NULL.
2092 */
2093IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2094{
2095 RTGCPTR GCPtrDisp;
2096 VMXEXITINSTRINFO ExitInstrInfo;
2097 ExitInstrInfo.u = 0;
2098
2099 /*
2100 * Get and parse the ModR/M byte from our decoded opcodes.
2101 */
2102 uint8_t bRm;
2103 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2104 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2105 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2106 {
2107 /*
2108 * ModR/M indicates register addressing.
2109 *
2110 * The primary/secondary register operands are reported in the iReg1 or iReg2
2111 * fields depending on whether it is a read/write form.
2112 */
2113 uint8_t idxReg1;
2114 uint8_t idxReg2;
2115 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2116 {
2117 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2118 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2119 }
2120 else
2121 {
2122 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2123 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2124 }
2125 ExitInstrInfo.All.u2Scaling = 0;
2126 ExitInstrInfo.All.iReg1 = idxReg1;
2127 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2128 ExitInstrInfo.All.fIsRegOperand = 1;
2129 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2130 ExitInstrInfo.All.iSegReg = 0;
2131 ExitInstrInfo.All.iIdxReg = 0;
2132 ExitInstrInfo.All.fIdxRegInvalid = 1;
2133 ExitInstrInfo.All.iBaseReg = 0;
2134 ExitInstrInfo.All.fBaseRegInvalid = 1;
2135 ExitInstrInfo.All.iReg2 = idxReg2;
2136
2137 /* Displacement not applicable for register addressing. */
2138 GCPtrDisp = 0;
2139 }
2140 else
2141 {
2142 /*
2143 * ModR/M indicates memory addressing.
2144 */
2145 uint8_t uScale = 0;
2146 bool fBaseRegValid = false;
2147 bool fIdxRegValid = false;
2148 uint8_t iBaseReg = 0;
2149 uint8_t iIdxReg = 0;
2150 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2151 {
2152 /*
2153 * Parse the ModR/M, displacement for 16-bit addressing mode.
2154 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2155 */
2156 uint16_t u16Disp = 0;
2157 uint8_t const offDisp = offModRm + sizeof(bRm);
2158 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2159 {
2160 /* Displacement without any registers. */
2161 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2162 }
2163 else
2164 {
2165 /* Register (index and base). */
2166 switch (bRm & X86_MODRM_RM_MASK)
2167 {
2168 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2169 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2170 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2171 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2172 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2173 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2174 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2175 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2176 }
2177
2178 /* Register + displacement. */
2179 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2180 {
2181 case 0: break;
2182 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2183 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2184 default:
2185 {
2186 /* Register addressing, handled at the beginning. */
2187 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2188 break;
2189 }
2190 }
2191 }
2192
2193 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2194 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2195 }
2196 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2197 {
2198 /*
2199 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2200 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2201 */
2202 uint32_t u32Disp = 0;
2203 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2204 {
2205 /* Displacement without any registers. */
2206 uint8_t const offDisp = offModRm + sizeof(bRm);
2207 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2208 }
2209 else
2210 {
2211 /* Register (and perhaps scale, index and base). */
2212 uint8_t offDisp = offModRm + sizeof(bRm);
2213 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2214 if (iBaseReg == 4)
2215 {
2216 /* An SIB byte follows the ModR/M byte, parse it. */
2217 uint8_t bSib;
2218 uint8_t const offSib = offModRm + sizeof(bRm);
2219 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2220
2221 /* A displacement may follow SIB, update its offset. */
2222 offDisp += sizeof(bSib);
2223
2224 /* Get the scale. */
2225 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2226
2227 /* Get the index register. */
2228 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2229 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2230
2231 /* Get the base register. */
2232 iBaseReg = bSib & X86_SIB_BASE_MASK;
2233 fBaseRegValid = true;
2234 if (iBaseReg == 5)
2235 {
2236 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2237 {
2238 /* Mod is 0 implies a 32-bit displacement with no base. */
2239 fBaseRegValid = false;
2240 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2241 }
2242 else
2243 {
2244 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2245 iBaseReg = X86_GREG_xBP;
2246 }
2247 }
2248 }
2249
2250 /* Register + displacement. */
2251 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2252 {
2253 case 0: /* Handled above */ break;
2254 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2255 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2256 default:
2257 {
2258 /* Register addressing, handled at the beginning. */
2259 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2260 break;
2261 }
2262 }
2263 }
2264
2265 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2266 }
2267 else
2268 {
2269 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2270
2271 /*
2272 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2273 * See Intel instruction spec. 2.2 "IA-32e Mode".
2274 */
2275 uint64_t u64Disp = 0;
2276 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2277 if (fRipRelativeAddr)
2278 {
2279 /*
2280 * RIP-relative addressing mode.
2281 *
2282 * The displacement is 32-bit signed implying an offset range of +/-2G.
2283 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2284 */
2285 uint8_t const offDisp = offModRm + sizeof(bRm);
2286 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2287 }
2288 else
2289 {
2290 uint8_t offDisp = offModRm + sizeof(bRm);
2291
2292 /*
2293 * Register (and perhaps scale, index and base).
2294 *
2295 * REX.B extends the most-significant bit of the base register. However, REX.B
2296 * is ignored while determining whether an SIB follows the opcode. Hence, we
2297 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2298 *
2299 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2300 */
2301 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2302 if (iBaseReg == 4)
2303 {
2304 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2305 uint8_t bSib;
2306 uint8_t const offSib = offModRm + sizeof(bRm);
2307 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2308
2309 /* Displacement may follow SIB, update its offset. */
2310 offDisp += sizeof(bSib);
2311
2312 /* Get the scale. */
2313 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2314
2315 /* Get the index. */
2316 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2317 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2318
2319 /* Get the base. */
2320 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2321 fBaseRegValid = true;
2322 if (iBaseReg == 5)
2323 {
2324 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2325 {
2326 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2327 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2328 }
2329 else
2330 {
2331 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2332 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2333 }
2334 }
2335 }
2336 iBaseReg |= pVCpu->iem.s.uRexB;
2337
2338 /* Register + displacement. */
2339 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2340 {
2341 case 0: /* Handled above */ break;
2342 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2343 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2344 default:
2345 {
2346 /* Register addressing, handled at the beginning. */
2347 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2348 break;
2349 }
2350 }
2351 }
2352
2353 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2354 }
2355
2356 /*
2357 * The primary or secondary register operand is reported in iReg2 depending
2358 * on whether the primary operand is in read/write form.
2359 */
2360 uint8_t idxReg2;
2361 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2362 {
2363 idxReg2 = bRm & X86_MODRM_RM_MASK;
2364 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2365 idxReg2 |= pVCpu->iem.s.uRexB;
2366 }
2367 else
2368 {
2369 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2370 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2371 idxReg2 |= pVCpu->iem.s.uRexReg;
2372 }
2373 ExitInstrInfo.All.u2Scaling = uScale;
2374 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2375 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2376 ExitInstrInfo.All.fIsRegOperand = 0;
2377 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2378 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2379 ExitInstrInfo.All.iIdxReg = iIdxReg;
2380 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2381 ExitInstrInfo.All.iBaseReg = iBaseReg;
2382 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2383 ExitInstrInfo.All.iReg2 = idxReg2;
2384 }
2385
2386 /*
2387 * Handle exceptions to the norm for certain instructions.
2388 * (e.g. some instructions convey an instruction identity in place of iReg2).
2389 */
2390 switch (uExitReason)
2391 {
2392 case VMX_EXIT_GDTR_IDTR_ACCESS:
2393 {
2394 Assert(VMXINSTRID_IS_VALID(uInstrId));
2395 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2396 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2397 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2398 break;
2399 }
2400
2401 case VMX_EXIT_LDTR_TR_ACCESS:
2402 {
2403 Assert(VMXINSTRID_IS_VALID(uInstrId));
2404 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2405 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2406 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2407 break;
2408 }
2409
2410 case VMX_EXIT_RDRAND:
2411 case VMX_EXIT_RDSEED:
2412 {
2413 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2414 break;
2415 }
2416 }
2417
2418 /* Update displacement and return the constructed VM-exit instruction information field. */
2419 if (pGCPtrDisp)
2420 *pGCPtrDisp = GCPtrDisp;
2421
2422 return ExitInstrInfo.u;
2423}
2424
2425
2426/**
2427 * VMX VM-exit handler.
2428 *
2429 * @returns Strict VBox status code.
2430 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2431 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2432 * triple-fault.
2433 *
2434 * @param pVCpu The cross context virtual CPU structure.
2435 * @param uExitReason The VM-exit reason.
2436 * @param u64ExitQual The Exit qualification.
2437 *
2438 * @remarks We need not necessarily have completed VM-entry before a VM-exit is
2439 * called. Failures during VM-entry can cause VM-exits as well, so we
2440 * -cannot- assert we're in VMX non-root mode here.
2441 */
2442IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2443{
2444# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2445 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2446 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2447 return VERR_IEM_IPE_7;
2448# else
2449 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2450
2451 /*
2452 * Import all the guest-CPU state.
2453 *
2454 * HM on returning to guest execution would have to reset up a whole lot of state
2455 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2456 * the state and flag reloading the entire state on re-entry. So import the entire
2457 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2458 */
2459 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2460
2461 /*
2462 * Ensure VM-entry interruption information valid bit is cleared.
2463 *
2464 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2465 * by invalid-guest state or machine-check exceptions) also clear this bit.
2466 *
2467 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2468 */
2469 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2470 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2471
2472 /*
2473 * Update the VM-exit reason and Exit qualification.
2474 * Other VMCS read-only data fields are expected to be updated by the caller already.
2475 */
2476 pVmcs->u32RoExitReason = uExitReason;
2477 pVmcs->u64RoExitQual.u = u64ExitQual;
2478
2479 Log3(("vmexit: reason=%#RX32 qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2480 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2481 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2482
2483 /*
2484 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2485 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2486 */
2487 {
2488 uint8_t uVector;
2489 uint32_t fFlags;
2490 uint32_t uErrCode;
2491 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2492 if (fInEventDelivery)
2493 {
2494 /*
2495 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2496 * caused by a triple-fault or the original event results in a double-fault that
2497 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2498 * original event information into the IDT-vectoring information fields.
2499 *
2500 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2501 */
2502 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2503 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2504 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2505 {
2506 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2507 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2508 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2509 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2510 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2511 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2512 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2513 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2514 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2515 pVCpu->cpum.GstCtx.cr2));
2516 }
2517 }
2518 }
2519
2520 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2521 Assert(pVmcs->u64RoIoRcx.u == 0);
2522 Assert(pVmcs->u64RoIoRsi.u == 0);
2523 Assert(pVmcs->u64RoIoRdi.u == 0);
2524 Assert(pVmcs->u64RoIoRip.u == 0);
2525
2526 /*
2527 * Save the guest state back into the VMCS.
2528 * We only need to save the state when the VM-entry was successful.
2529 */
2530 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2531 if (!fVmentryFailed)
2532 {
2533 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2534 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2535 {
2536 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2537 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2538 }
2539
2540 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2541 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2542
2543 /*
2544 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2545 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2546 *
2547 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2548 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2549 * as guest-CPU state would not been modified. Hence for now, we do this only when
2550 * the VM-entry succeeded.
2551 */
2552 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2553 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2554 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2555 {
2556 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2557 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2558 else
2559 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2560 }
2561
2562 /*
2563 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2564 * occurs in enclave mode/SMM which we don't support yet.
2565 *
2566 * If we ever add support for it, we can pass just the lower bits to the functions
2567 * below, till then an assert should suffice.
2568 */
2569 Assert(!RT_HI_U16(uExitReason));
2570
2571 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2572 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2573 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2574 if (RT_SUCCESS(rc))
2575 { /* likely */ }
2576 else
2577 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2578
2579 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2580 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2581 }
2582 else
2583 {
2584 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2585 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2586 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2587 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2588 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2589 }
2590
2591 /*
2592 * Stop any running VMX-preemption timer if necessary.
2593 */
2594 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2595 CPUMStopGuestVmxPremptTimer(pVCpu);
2596
2597 /*
2598 * Clear any pending VMX nested-guest force-flags.
2599 * These force-flags have no effect on (outer) guest execution and will
2600 * be re-evaluated and setup on the next nested-guest VM-entry.
2601 */
2602 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2603
2604 /*
2605 * We're no longer in nested-guest execution mode.
2606 *
2607 * It is important to do this prior to loading the host state because
2608 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2609 * second-level address translation while switching to host CR3.
2610 */
2611 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2612
2613 /* Restore the host (outer guest) state. */
2614 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2615 if (RT_SUCCESS(rcStrict))
2616 {
2617 Assert(rcStrict == VINF_SUCCESS);
2618 rcStrict = VINF_VMX_VMEXIT;
2619 }
2620 else
2621 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2622
2623 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
2624 {
2625 /* Notify HM that the current VMCS fields have been modified. */
2626 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2627
2628 /* Notify HM that we've completed the VM-exit. */
2629 HMNotifyVmxNstGstVmexit(pVCpu);
2630 }
2631
2632# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2633 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2634 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2635 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2636 if (rcSched != VINF_SUCCESS)
2637 iemSetPassUpStatus(pVCpu, rcSched);
2638# endif
2639 return rcStrict;
2640# endif
2641}
2642
2643
2644/**
2645 * VMX VM-exit handler for VM-exits due to instruction execution.
2646 *
2647 * This is intended for instructions where the caller provides all the relevant
2648 * VM-exit information.
2649 *
2650 * @returns Strict VBox status code.
2651 * @param pVCpu The cross context virtual CPU structure.
2652 * @param pExitInfo Pointer to the VM-exit information.
2653 */
2654IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2655{
2656 /*
2657 * For instructions where any of the following fields are not applicable:
2658 * - Exit qualification must be cleared.
2659 * - VM-exit instruction info. is undefined.
2660 * - Guest-linear address is undefined.
2661 * - Guest-physical address is undefined.
2662 *
2663 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2664 * instruction execution. For VM-exits that are not due to instruction execution this
2665 * field is undefined.
2666 *
2667 * In our implementation in IEM, all undefined fields are generally cleared. However,
2668 * if the caller supplies information (from say the physical CPU directly) it is
2669 * then possible that the undefined fields are not cleared.
2670 *
2671 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2672 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2673 */
2674 Assert(pExitInfo);
2675 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2676 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2677 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2678
2679 /* Update all the relevant fields from the VM-exit instruction information struct. */
2680 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2681 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2682 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2683 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2684
2685 /* Perform the VM-exit. */
2686 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2687}
2688
2689
2690/**
2691 * VMX VM-exit handler for VM-exits due to instruction execution.
2692 *
2693 * This is intended for instructions that only provide the VM-exit instruction
2694 * length.
2695 *
2696 * @param pVCpu The cross context virtual CPU structure.
2697 * @param uExitReason The VM-exit reason.
2698 * @param cbInstr The instruction length in bytes.
2699 */
2700IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2701{
2702 VMXVEXITINFO ExitInfo;
2703 RT_ZERO(ExitInfo);
2704 ExitInfo.uReason = uExitReason;
2705 ExitInfo.cbInstr = cbInstr;
2706
2707#ifdef VBOX_STRICT
2708 /*
2709 * To prevent us from shooting ourselves in the foot.
2710 * The follow instructions should convey more than just the instruction length.
2711 */
2712 switch (uExitReason)
2713 {
2714 case VMX_EXIT_INVEPT:
2715 case VMX_EXIT_INVPCID:
2716 case VMX_EXIT_INVVPID:
2717 case VMX_EXIT_LDTR_TR_ACCESS:
2718 case VMX_EXIT_GDTR_IDTR_ACCESS:
2719 case VMX_EXIT_VMCLEAR:
2720 case VMX_EXIT_VMPTRLD:
2721 case VMX_EXIT_VMPTRST:
2722 case VMX_EXIT_VMREAD:
2723 case VMX_EXIT_VMWRITE:
2724 case VMX_EXIT_VMXON:
2725 case VMX_EXIT_XRSTORS:
2726 case VMX_EXIT_XSAVES:
2727 case VMX_EXIT_RDRAND:
2728 case VMX_EXIT_RDSEED:
2729 case VMX_EXIT_IO_INSTR:
2730 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2731 break;
2732 }
2733#endif
2734
2735 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2736}
2737
2738
2739/**
2740 * VMX VM-exit handler for VM-exits due to instruction execution.
2741 *
2742 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2743 * instruction information and Exit qualification fields.
2744 *
2745 * @param pVCpu The cross context virtual CPU structure.
2746 * @param uExitReason The VM-exit reason.
2747 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2748 * @param cbInstr The instruction length in bytes.
2749 *
2750 * @remarks Do not use this for INS/OUTS instruction.
2751 */
2752IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2753{
2754 VMXVEXITINFO ExitInfo;
2755 RT_ZERO(ExitInfo);
2756 ExitInfo.uReason = uExitReason;
2757 ExitInfo.cbInstr = cbInstr;
2758
2759 /*
2760 * Update the Exit qualification field with displacement bytes.
2761 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2762 */
2763 switch (uExitReason)
2764 {
2765 case VMX_EXIT_INVEPT:
2766 case VMX_EXIT_INVPCID:
2767 case VMX_EXIT_INVVPID:
2768 case VMX_EXIT_LDTR_TR_ACCESS:
2769 case VMX_EXIT_GDTR_IDTR_ACCESS:
2770 case VMX_EXIT_VMCLEAR:
2771 case VMX_EXIT_VMPTRLD:
2772 case VMX_EXIT_VMPTRST:
2773 case VMX_EXIT_VMREAD:
2774 case VMX_EXIT_VMWRITE:
2775 case VMX_EXIT_VMXON:
2776 case VMX_EXIT_XRSTORS:
2777 case VMX_EXIT_XSAVES:
2778 case VMX_EXIT_RDRAND:
2779 case VMX_EXIT_RDSEED:
2780 {
2781 /* Construct the VM-exit instruction information. */
2782 RTGCPTR GCPtrDisp;
2783 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2784
2785 /* Update the VM-exit instruction information. */
2786 ExitInfo.InstrInfo.u = uInstrInfo;
2787
2788 /* Update the Exit qualification. */
2789 ExitInfo.u64Qual = GCPtrDisp;
2790 break;
2791 }
2792
2793 default:
2794 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2795 break;
2796 }
2797
2798 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2799}
2800
2801
2802/**
2803 * VMX VM-exit handler for VM-exits due to INVLPG.
2804 *
2805 * @returns Strict VBox status code.
2806 * @param pVCpu The cross context virtual CPU structure.
2807 * @param GCPtrPage The guest-linear address of the page being invalidated.
2808 * @param cbInstr The instruction length in bytes.
2809 */
2810IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
2811{
2812 VMXVEXITINFO ExitInfo;
2813 RT_ZERO(ExitInfo);
2814 ExitInfo.uReason = VMX_EXIT_INVLPG;
2815 ExitInfo.cbInstr = cbInstr;
2816 ExitInfo.u64Qual = GCPtrPage;
2817 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2818
2819 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2820}
2821
2822
2823/**
2824 * VMX VM-exit handler for VM-exits due to LMSW.
2825 *
2826 * @returns Strict VBox status code.
2827 * @param pVCpu The cross context virtual CPU structure.
2828 * @param uGuestCr0 The current guest CR0.
2829 * @param pu16NewMsw The machine-status word specified in LMSW's source
2830 * operand. This will be updated depending on the VMX
2831 * guest/host CR0 mask if LMSW is not intercepted.
2832 * @param GCPtrEffDst The guest-linear address of the source operand in case
2833 * of a memory operand. For register operand, pass
2834 * NIL_RTGCPTR.
2835 * @param cbInstr The instruction length in bytes.
2836 */
2837IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
2838 uint8_t cbInstr)
2839{
2840 Assert(pu16NewMsw);
2841
2842 uint16_t const uNewMsw = *pu16NewMsw;
2843 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2844 {
2845 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2846
2847 VMXVEXITINFO ExitInfo;
2848 RT_ZERO(ExitInfo);
2849 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2850 ExitInfo.cbInstr = cbInstr;
2851
2852 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2853 if (fMemOperand)
2854 {
2855 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2856 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2857 }
2858
2859 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2860 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2861 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2862 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2863
2864 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2865 }
2866
2867 /*
2868 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2869 * CR0 guest/host mask must be left unmodified.
2870 *
2871 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2872 */
2873 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2874 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2875 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2876
2877 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2878}
2879
2880
2881/**
2882 * VMX VM-exit handler for VM-exits due to CLTS.
2883 *
2884 * @returns Strict VBox status code.
2885 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2886 * VM-exit but must not modify the guest CR0.TS bit.
2887 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2888 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2889 * CR0 fixed bits in VMX operation).
2890 * @param pVCpu The cross context virtual CPU structure.
2891 * @param cbInstr The instruction length in bytes.
2892 */
2893IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr)
2894{
2895 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2896 uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2897
2898 /*
2899 * If CR0.TS is owned by the host:
2900 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2901 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2902 * CLTS instruction completes without clearing CR0.TS.
2903 *
2904 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2905 */
2906 if (fGstHostMask & X86_CR0_TS)
2907 {
2908 if (fReadShadow & X86_CR0_TS)
2909 {
2910 Log2(("clts: Guest intercept -> VM-exit\n"));
2911
2912 VMXVEXITINFO ExitInfo;
2913 RT_ZERO(ExitInfo);
2914 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2915 ExitInfo.cbInstr = cbInstr;
2916 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2917 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2918 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2919 }
2920
2921 return VINF_VMX_MODIFIES_BEHAVIOR;
2922 }
2923
2924 /*
2925 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2926 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2927 */
2928 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2929}
2930
2931
2932/**
2933 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2934 * (CR0/CR4 write).
2935 *
2936 * @returns Strict VBox status code.
2937 * @param pVCpu The cross context virtual CPU structure.
2938 * @param iCrReg The control register (either CR0 or CR4).
2939 * @param uGuestCrX The current guest CR0/CR4.
2940 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
2941 * VM-exit is caused.
2942 * @param iGReg The general register from which the CR0/CR4 value is being
2943 * loaded.
2944 * @param cbInstr The instruction length in bytes.
2945 */
2946IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
2947 uint8_t cbInstr)
2948{
2949 Assert(puNewCrX);
2950 Assert(iCrReg == 0 || iCrReg == 4);
2951 Assert(iGReg < X86_GREG_COUNT);
2952
2953 uint64_t const uNewCrX = *puNewCrX;
2954 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
2955 {
2956 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
2957
2958 VMXVEXITINFO ExitInfo;
2959 RT_ZERO(ExitInfo);
2960 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2961 ExitInfo.cbInstr = cbInstr;
2962 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
2963 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
2964 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
2965 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2966 }
2967
2968 /*
2969 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
2970 * must not be modified the instruction.
2971 *
2972 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2973 */
2974 uint64_t uGuestCrX;
2975 uint64_t fGstHostMask;
2976 if (iCrReg == 0)
2977 {
2978 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
2979 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
2980 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2981 }
2982 else
2983 {
2984 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
2985 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
2986 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2987 }
2988
2989 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
2990 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2991}
2992
2993
2994/**
2995 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
2996 *
2997 * @returns VBox strict status code.
2998 * @param pVCpu The cross context virtual CPU structure.
2999 * @param iGReg The general register to which the CR3 value is being stored.
3000 * @param cbInstr The instruction length in bytes.
3001 */
3002IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3003{
3004 Assert(iGReg < X86_GREG_COUNT);
3005 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3006
3007 /*
3008 * If the CR3-store exiting control is set, we must cause a VM-exit.
3009 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3010 */
3011 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3012 {
3013 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3014
3015 VMXVEXITINFO ExitInfo;
3016 RT_ZERO(ExitInfo);
3017 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3018 ExitInfo.cbInstr = cbInstr;
3019 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3020 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3021 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3022 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3023 }
3024
3025 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3026}
3027
3028
3029/**
3030 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3031 *
3032 * @returns VBox strict status code.
3033 * @param pVCpu The cross context virtual CPU structure.
3034 * @param uNewCr3 The new CR3 value.
3035 * @param iGReg The general register from which the CR3 value is being
3036 * loaded.
3037 * @param cbInstr The instruction length in bytes.
3038 */
3039IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3040{
3041 Assert(iGReg < X86_GREG_COUNT);
3042
3043 /*
3044 * If the CR3-load exiting control is set and the new CR3 value does not
3045 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3046 *
3047 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3048 */
3049 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3050 {
3051 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3052
3053 VMXVEXITINFO ExitInfo;
3054 RT_ZERO(ExitInfo);
3055 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3056 ExitInfo.cbInstr = cbInstr;
3057 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3058 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3059 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3060 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3061 }
3062
3063 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3064}
3065
3066
3067/**
3068 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3069 *
3070 * @returns VBox strict status code.
3071 * @param pVCpu The cross context virtual CPU structure.
3072 * @param iGReg The general register to which the CR8 value is being stored.
3073 * @param cbInstr The instruction length in bytes.
3074 */
3075IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3076{
3077 Assert(iGReg < X86_GREG_COUNT);
3078
3079 /*
3080 * If the CR8-store exiting control is set, we must cause a VM-exit.
3081 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3082 */
3083 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3084 {
3085 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3086
3087 VMXVEXITINFO ExitInfo;
3088 RT_ZERO(ExitInfo);
3089 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3090 ExitInfo.cbInstr = cbInstr;
3091 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3092 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3093 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3094 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3095 }
3096
3097 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3098}
3099
3100
3101/**
3102 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3103 *
3104 * @returns VBox strict status code.
3105 * @param pVCpu The cross context virtual CPU structure.
3106 * @param iGReg The general register from which the CR8 value is being
3107 * loaded.
3108 * @param cbInstr The instruction length in bytes.
3109 */
3110IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr)
3111{
3112 Assert(iGReg < X86_GREG_COUNT);
3113
3114 /*
3115 * If the CR8-load exiting control is set, we must cause a VM-exit.
3116 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3117 */
3118 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3119 {
3120 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3121
3122 VMXVEXITINFO ExitInfo;
3123 RT_ZERO(ExitInfo);
3124 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3125 ExitInfo.cbInstr = cbInstr;
3126 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3127 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3128 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3129 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3130 }
3131
3132 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3133}
3134
3135
3136/**
3137 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3138 * GReg,DRx' (DRx read).
3139 *
3140 * @returns VBox strict status code.
3141 * @param pVCpu The cross context virtual CPU structure.
3142 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3143 * VMXINSTRID_MOV_FROM_DRX).
3144 * @param iDrReg The debug register being accessed.
3145 * @param iGReg The general register to/from which the DRx value is being
3146 * store/loaded.
3147 * @param cbInstr The instruction length in bytes.
3148 */
3149IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3150 uint8_t cbInstr)
3151{
3152 Assert(iDrReg <= 7);
3153 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3154 Assert(iGReg < X86_GREG_COUNT);
3155
3156 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3157 {
3158 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3159 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3160 VMXVEXITINFO ExitInfo;
3161 RT_ZERO(ExitInfo);
3162 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3163 ExitInfo.cbInstr = cbInstr;
3164 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3165 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3166 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3167 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3168 }
3169
3170 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3171}
3172
3173
3174/**
3175 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3176 *
3177 * @returns VBox strict status code.
3178 * @param pVCpu The cross context virtual CPU structure.
3179 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3180 * VMXINSTRID_IO_OUT).
3181 * @param u16Port The I/O port being accessed.
3182 * @param fImm Whether the I/O port was encoded using an immediate operand
3183 * or the implicit DX register.
3184 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3185 * @param cbInstr The instruction length in bytes.
3186 */
3187IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3188 uint8_t cbInstr)
3189{
3190 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3191 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3192
3193 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3194 if (fIntercept)
3195 {
3196 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3197 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3198 VMXVEXITINFO ExitInfo;
3199 RT_ZERO(ExitInfo);
3200 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3201 ExitInfo.cbInstr = cbInstr;
3202 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3203 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3204 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3205 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3206 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3207 }
3208
3209 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3210}
3211
3212
3213/**
3214 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3215 *
3216 * @returns VBox strict status code.
3217 * @param pVCpu The cross context virtual CPU structure.
3218 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3219 * VMXINSTRID_IO_OUTS).
3220 * @param u16Port The I/O port being accessed.
3221 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3222 * @param fRep Whether the instruction has a REP prefix or not.
3223 * @param ExitInstrInfo The VM-exit instruction info. field.
3224 * @param cbInstr The instruction length in bytes.
3225 */
3226IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3227 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3228{
3229 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3230 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3231 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3232 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3233 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3234
3235 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3236 if (fIntercept)
3237 {
3238 /*
3239 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3240 */
3241 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3242 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3243 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3244 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3245 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3246
3247 uint32_t uDirection;
3248 uint64_t uGuestLinearAddr;
3249 if (uInstrId == VMXINSTRID_IO_INS)
3250 {
3251 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3252 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3253 }
3254 else
3255 {
3256 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3257 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3258 }
3259
3260 /*
3261 * If the segment is unusable, the guest-linear address in undefined.
3262 * We shall clear it for consistency.
3263 *
3264 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3265 */
3266 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3267 uGuestLinearAddr = 0;
3268
3269 VMXVEXITINFO ExitInfo;
3270 RT_ZERO(ExitInfo);
3271 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3272 ExitInfo.cbInstr = cbInstr;
3273 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3274 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3275 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3276 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3277 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3278 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3279 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3280 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3281 ExitInfo.InstrInfo = ExitInstrInfo;
3282 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3283 }
3284
3285 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3286}
3287
3288
3289/**
3290 * VMX VM-exit handler for VM-exits due to MWAIT.
3291 *
3292 * @returns VBox strict status code.
3293 * @param pVCpu The cross context virtual CPU structure.
3294 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3295 * @param cbInstr The instruction length in bytes.
3296 */
3297IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3298{
3299 VMXVEXITINFO ExitInfo;
3300 RT_ZERO(ExitInfo);
3301 ExitInfo.uReason = VMX_EXIT_MWAIT;
3302 ExitInfo.cbInstr = cbInstr;
3303 ExitInfo.u64Qual = fMonitorHwArmed;
3304 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3305}
3306
3307
3308/**
3309 * VMX VM-exit handler for VM-exits due to PAUSE.
3310 *
3311 * @returns VBox strict status code.
3312 * @param pVCpu The cross context virtual CPU structure.
3313 * @param cbInstr The instruction length in bytes.
3314 */
3315IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr)
3316{
3317 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3318
3319 /*
3320 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3321 * "PAUSE-loop exiting" control.
3322 *
3323 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3324 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3325 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3326 * a VM-exit.
3327 *
3328 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3329 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3330 */
3331 bool fIntercept = false;
3332 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3333 fIntercept = true;
3334 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3335 && pVCpu->iem.s.uCpl == 0)
3336 {
3337 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3338
3339 /*
3340 * A previous-PAUSE-tick value of 0 is used to identify the first time
3341 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3342 * consider this to be the first execution of PAUSE in a loop according
3343 * to the Intel.
3344 *
3345 * All subsequent records for the previous-PAUSE-tick we ensure that it
3346 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3347 */
3348 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3349 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3350 uint64_t const uTick = TMCpuTickGet(pVCpu);
3351 uint32_t const uPleGap = pVmcs->u32PleGap;
3352 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3353 if ( *puPrevPauseTick == 0
3354 || uTick - *puPrevPauseTick > uPleGap)
3355 *puFirstPauseLoopTick = uTick;
3356 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3357 fIntercept = true;
3358
3359 *puPrevPauseTick = uTick | 1;
3360 }
3361
3362 if (fIntercept)
3363 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3364
3365 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3366}
3367
3368
3369/**
3370 * VMX VM-exit handler for VM-exits due to task switches.
3371 *
3372 * @returns VBox strict status code.
3373 * @param pVCpu The cross context virtual CPU structure.
3374 * @param enmTaskSwitch The cause of the task switch.
3375 * @param SelNewTss The selector of the new TSS.
3376 * @param cbInstr The instruction length in bytes.
3377 */
3378IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3379{
3380 /*
3381 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3382 *
3383 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3384 * instruction or delivery of the exception generated by one of these instructions
3385 * lead to a task switch through a task gate in the IDT, we need to provide the
3386 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3387 * leaves the VM-exit instruction length field undefined.
3388 *
3389 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3390 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3391 */
3392 Assert(cbInstr <= 15);
3393
3394 uint8_t uType;
3395 switch (enmTaskSwitch)
3396 {
3397 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3398 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3399 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3400 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3401 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3402 }
3403
3404 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3405 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3406 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3407 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3408}
3409
3410
3411/**
3412 * VMX VM-exit handler for trap-like VM-exits.
3413 *
3414 * @returns VBox strict status code.
3415 * @param pVCpu The cross context virtual CPU structure.
3416 * @param pExitInfo Pointer to the VM-exit information.
3417 * @param pExitEventInfo Pointer to the VM-exit event information.
3418 */
3419IEM_STATIC VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3420{
3421 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3422 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3423 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3424}
3425
3426
3427/**
3428 * VMX VM-exit handler for VM-exits due to task switches.
3429 *
3430 * This is intended for task switches where the caller provides all the relevant
3431 * VM-exit information.
3432 *
3433 * @returns VBox strict status code.
3434 * @param pVCpu The cross context virtual CPU structure.
3435 * @param pExitInfo Pointer to the VM-exit information.
3436 * @param pExitEventInfo Pointer to the VM-exit event information.
3437 */
3438IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3439 PCVMXVEXITEVENTINFO pExitEventInfo)
3440{
3441 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3442 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3443 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3444 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3445 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3446}
3447
3448
3449/**
3450 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3451 *
3452 * @returns VBox strict status code.
3453 * @param pVCpu The cross context virtual CPU structure.
3454 */
3455IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3456{
3457 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3458 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3459
3460 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3461 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3462
3463 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3464 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3465 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3466
3467 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3468 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3469}
3470
3471
3472/**
3473 * VMX VM-exit handler for VM-exits due to external interrupts.
3474 *
3475 * @returns VBox strict status code.
3476 * @param pVCpu The cross context virtual CPU structure.
3477 * @param uVector The external interrupt vector (pass 0 if the interrupt
3478 * is still pending since we typically won't know the
3479 * vector).
3480 * @param fIntPending Whether the external interrupt is pending or
3481 * acknowledged in the interrupt controller.
3482 */
3483IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3484{
3485 Assert(!fIntPending || uVector == 0);
3486
3487 /* The VM-exit is subject to "External interrupt exiting" being set. */
3488 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3489 {
3490 if (fIntPending)
3491 {
3492 /*
3493 * If the interrupt is pending and we don't need to acknowledge the
3494 * interrupt on VM-exit, cause the VM-exit immediately.
3495 *
3496 * See Intel spec 25.2 "Other Causes Of VM Exits".
3497 */
3498 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3499 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3500
3501 /*
3502 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3503 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3504 * acknowledged that the interrupt has been consumed. Callers would have to call
3505 * us again after getting the vector (and ofc, with fIntPending with false).
3506 */
3507 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3508 }
3509
3510 /*
3511 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3512 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3513 * all set, we need to record the vector of the external interrupt in the
3514 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3515 *
3516 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3517 */
3518 uint32_t uExitIntInfo;
3519 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3520 {
3521 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3522 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3523 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3524 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3525 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3526 }
3527 else
3528 uExitIntInfo = 0;
3529 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3530
3531 /*
3532 * Cause the VM-exit whether or not the vector has been stored
3533 * in the VM-exit interruption-information field.
3534 */
3535 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3536 }
3537
3538 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3539}
3540
3541
3542/**
3543 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3544 * an event.
3545 *
3546 * @returns VBox strict status code.
3547 * @param pVCpu The cross context virtual CPU structure.
3548 */
3549IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu)
3550{
3551 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3552 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3553 {
3554 /*
3555 * The NMI-unblocking due to IRET field need not be set for double faults.
3556 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3557 */
3558 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3559 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3560 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3561 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3562 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3563 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3564 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3565 }
3566
3567 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3568}
3569
3570
3571/**
3572 * VMX VM-exit handler for VM-exit due to delivery of an events.
3573 *
3574 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3575 * all the relevant VM-exit information.
3576 *
3577 * @returns VBox strict status code.
3578 * @param pVCpu The cross context virtual CPU structure.
3579 * @param pExitInfo Pointer to the VM-exit information.
3580 * @param pExitEventInfo Pointer to the VM-exit event information.
3581 */
3582IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3583{
3584 Assert(pExitInfo);
3585 Assert(pExitEventInfo);
3586 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3587 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3588
3589 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3590 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3591 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3592 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3593 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3594 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3595}
3596
3597
3598/**
3599 * VMX VM-exit handler for VM-exits due to delivery of an event.
3600 *
3601 * @returns VBox strict status code.
3602 * @param pVCpu The cross context virtual CPU structure.
3603 * @param uVector The interrupt / exception vector.
3604 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3605 * @param uErrCode The error code associated with the event.
3606 * @param uCr2 The CR2 value in case of a \#PF exception.
3607 * @param cbInstr The instruction length in bytes.
3608 */
3609IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3610 uint8_t cbInstr)
3611{
3612 /*
3613 * If the event is being injected as part of VM-entry, it is -not- subject to event
3614 * intercepts in the nested-guest. However, secondary exceptions that occur during
3615 * injection of any event -are- subject to event interception.
3616 *
3617 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3618 */
3619 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3620 {
3621 /*
3622 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3623 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3624 *
3625 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3626 */
3627 if ( uVector == X86_XCPT_NMI
3628 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3629 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3630 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3631 else
3632 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3633
3634 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3635 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3636 }
3637
3638 /*
3639 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3640 * If not, the caller will continue delivery of the external interrupt as it would
3641 * normally. The interrupt is no longer pending in the interrupt controller at this
3642 * point.
3643 */
3644 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3645 {
3646 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3647 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3648 }
3649
3650 /*
3651 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3652 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3653 * interrupts.
3654 */
3655 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3656 bool fIntercept;
3657 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3658 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3659 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3660 else
3661 {
3662 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3663 fIntercept = false;
3664 }
3665
3666 /*
3667 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3668 * relevant VM-exit information and cause the VM-exit.
3669 */
3670 if (fIntercept)
3671 {
3672 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3673
3674 /* Construct the rest of the event related information fields and cause the VM-exit. */
3675 uint64_t u64ExitQual;
3676 if (uVector == X86_XCPT_PF)
3677 {
3678 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3679 u64ExitQual = uCr2;
3680 }
3681 else if (uVector == X86_XCPT_DB)
3682 {
3683 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3684 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3685 }
3686 else
3687 u64ExitQual = 0;
3688
3689 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3690 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3691 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3692 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3693 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3694 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3695 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3696 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3697 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3698 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3699
3700 /*
3701 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3702 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3703 * length.
3704 */
3705 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3706 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3707 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3708 else
3709 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3710
3711 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3712 }
3713
3714 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3715}
3716
3717
3718/**
3719 * VMX VM-exit handler for EPT misconfiguration.
3720 *
3721 * @param pVCpu The cross context virtual CPU structure.
3722 * @param GCPhysAddr The physical address causing the EPT misconfiguration. This
3723 * must be page aligned.
3724 */
3725IEM_STATIC VBOXSTRICTRC iemVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr)
3726{
3727 Assert(!(GCPhysAddr & PAGE_OFFSET_MASK));
3728 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3729 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3730}
3731
3732
3733/**
3734 * VMX VM-exit handler for EPT violation.
3735 *
3736 * @param pVCpu The cross context virtual CPU structure.
3737 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3738 * @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
3739 * @param fEptAccess The EPT paging structure bits.
3740 * @param GCPhysAddr The physical address causing the EPT violation. This
3741 * must be page aligned.
3742 * @param fIsLinearAddrValid Whether translation of a linear address caused this
3743 * EPT violation. If @c false, GCPtrAddr must be 0.
3744 * @param GCPtrAddr The linear address causing the EPT violation.
3745 * @param cbInstr The VM-exit instruction length.
3746 */
3747IEM_STATIC VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail, uint64_t fEptAccess,
3748 RTGCPHYS GCPhysAddr, bool fLinearAddrValid, uint64_t GCPtrAddr, uint8_t cbInstr)
3749{
3750 /*
3751 * If the linear address isn't valid (can happen when loading PDPTEs
3752 * as part of MOV CR execution) the linear address field is undefined.
3753 * While we can leave it this way, it's preferrable to zero it for consistency.
3754 */
3755 Assert(fLinearAddrValid || GCPtrAddr == 0);
3756 Assert(!(GCPhysAddr & PAGE_OFFSET_MASK));
3757
3758 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3759 uint8_t const fSupportsAccessDirty = fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY;
3760
3761 uint8_t const fDataRead = ((fAccess & IEM_ACCESS_DATA_R) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3762 uint8_t const fDataWrite = ((fAccess & IEM_ACCESS_DATA_RW) == IEM_ACCESS_DATA_RW) | fSupportsAccessDirty;
3763 uint8_t const fInstrFetch = (fAccess & IEM_ACCESS_INSTRUCTION) == IEM_ACCESS_INSTRUCTION;
3764 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3765 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3766 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3767 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3768 bool const fLinearToPhysAddr = fLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
3769
3770 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
3771 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
3772 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
3773 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
3774 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
3775 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
3776 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fLinearAddrValid)
3777 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fLinearToPhysAddr)
3778 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
3779
3780#ifdef VBOX_STRICT
3781 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
3782 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
3783 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
3784 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
3785 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
3786 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
3787#endif
3788
3789 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3790 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
3791 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3792
3793 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
3794}
3795
3796
3797/**
3798 * VMX VM-exit handler for EPT-induced VM-exits.
3799 *
3800 * @param pVCpu The cross context virtual CPU structure.
3801 * @param pWalk The page walk info.
3802 * @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
3803 * @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
3804 * @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
3805 * applicable.
3806 */
3807IEM_STATIC VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail,
3808 uint8_t cbInstr)
3809{
3810 Assert(pWalk->fIsSlat);
3811 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
3812 Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
3813 Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
3814
3815 if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
3816 {
3817 uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
3818 return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
3819 pWalk->GCPtr, cbInstr);
3820 }
3821
3822 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
3823 return iemVmxVmexitEptMisconfig(pVCpu, pWalk->GCPhysNested);
3824}
3825
3826
3827/**
3828 * VMX VM-exit handler for APIC accesses.
3829 *
3830 * @param pVCpu The cross context virtual CPU structure.
3831 * @param offAccess The offset of the register being accessed.
3832 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
3833 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
3834 */
3835IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess)
3836{
3837 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
3838
3839 VMXAPICACCESS enmAccess;
3840 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
3841 if (fInEventDelivery)
3842 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
3843 else if (fAccess & IEM_ACCESS_INSTRUCTION)
3844 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
3845 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
3846 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
3847 else
3848 enmAccess = VMXAPICACCESS_LINEAR_READ;
3849
3850 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
3851 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
3852 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
3853}
3854
3855
3856/**
3857 * VMX VM-exit handler for APIC accesses.
3858 *
3859 * This is intended for APIC accesses where the caller provides all the
3860 * relevant VM-exit information.
3861 *
3862 * @returns VBox strict status code.
3863 * @param pVCpu The cross context virtual CPU structure.
3864 * @param pExitInfo Pointer to the VM-exit information.
3865 * @param pExitEventInfo Pointer to the VM-exit event information.
3866 */
3867IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3868 PCVMXVEXITEVENTINFO pExitEventInfo)
3869{
3870 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
3871 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3872 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
3873 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
3874 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3875 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3876 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3877 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3878 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
3879}
3880
3881
3882/**
3883 * VMX VM-exit handler for APIC-write VM-exits.
3884 *
3885 * @param pVCpu The cross context virtual CPU structure.
3886 * @param offApic The write to the virtual-APIC page offset that caused this
3887 * VM-exit.
3888 */
3889IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic)
3890{
3891 Assert(offApic < XAPIC_OFF_END + 4);
3892 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
3893 offApic &= UINT16_C(0xfff);
3894 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
3895}
3896
3897
3898/**
3899 * Sets virtual-APIC write emulation as pending.
3900 *
3901 * @param pVCpu The cross context virtual CPU structure.
3902 * @param offApic The offset in the virtual-APIC page that was written.
3903 */
3904DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic)
3905{
3906 Assert(offApic < XAPIC_OFF_END + 4);
3907
3908 /*
3909 * Record the currently updated APIC offset, as we need this later for figuring
3910 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3911 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3912 */
3913 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3914
3915 /*
3916 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3917 * virtualization or APIC-write emulation).
3918 */
3919 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3920 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3921}
3922
3923
3924/**
3925 * Clears any pending virtual-APIC write emulation.
3926 *
3927 * @returns The virtual-APIC offset that was written before clearing it.
3928 * @param pVCpu The cross context virtual CPU structure.
3929 */
3930DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
3931{
3932 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3933 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
3934 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
3935 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
3936 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3937 return offVirtApicWrite;
3938}
3939
3940
3941/**
3942 * Reads a 32-bit register from the virtual-APIC page at the given offset.
3943 *
3944 * @returns The register from the virtual-APIC page.
3945 * @param pVCpu The cross context virtual CPU structure.
3946 * @param offReg The offset of the register being read.
3947 */
3948IEM_STATIC uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg)
3949{
3950 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3951
3952 uint32_t uReg = 0;
3953 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3954 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3955 AssertMsgStmt(RT_SUCCESS(rc),
3956 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3957 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3958 uReg = 0);
3959 return uReg;
3960}
3961
3962
3963/**
3964 * Reads a 64-bit register from the virtual-APIC page at the given offset.
3965 *
3966 * @returns The register from the virtual-APIC page.
3967 * @param pVCpu The cross context virtual CPU structure.
3968 * @param offReg The offset of the register being read.
3969 */
3970IEM_STATIC uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg)
3971{
3972 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
3973
3974 uint64_t uReg = 0;
3975 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3976 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
3977 AssertMsgStmt(RT_SUCCESS(rc),
3978 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3979 sizeof(uReg), offReg, GCPhysVirtApic, rc),
3980 uReg = 0);
3981 return uReg;
3982}
3983
3984
3985/**
3986 * Writes a 32-bit register to the virtual-APIC page at the given offset.
3987 *
3988 * @param pVCpu The cross context virtual CPU structure.
3989 * @param offReg The offset of the register being written.
3990 * @param uReg The register value to write.
3991 */
3992IEM_STATIC void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg)
3993{
3994 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
3995
3996 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
3997 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
3998 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
3999 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4000}
4001
4002
4003/**
4004 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4005 *
4006 * @param pVCpu The cross context virtual CPU structure.
4007 * @param offReg The offset of the register being written.
4008 * @param uReg The register value to write.
4009 */
4010IEM_STATIC void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg)
4011{
4012 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4013
4014 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4015 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4016 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4017 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4018}
4019
4020
4021/**
4022 * Sets the vector in a virtual-APIC 256-bit sparse register.
4023 *
4024 * @param pVCpu The cross context virtual CPU structure.
4025 * @param offReg The offset of the 256-bit spare register.
4026 * @param uVector The vector to set.
4027 *
4028 * @remarks This is based on our APIC device code.
4029 */
4030IEM_STATIC void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
4031{
4032 /* Determine the vector offset within the chunk. */
4033 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4034
4035 /* Read the chunk at the offset. */
4036 uint32_t uReg;
4037 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4038 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4039 if (RT_SUCCESS(rc))
4040 {
4041 /* Modify the chunk. */
4042 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4043 uReg |= RT_BIT(idxVectorBit);
4044
4045 /* Write the chunk. */
4046 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4047 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4048 uVector, offReg, GCPhysVirtApic, rc));
4049 }
4050 else
4051 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4052 uVector, offReg, GCPhysVirtApic, rc));
4053}
4054
4055
4056/**
4057 * Clears the vector in a virtual-APIC 256-bit sparse register.
4058 *
4059 * @param pVCpu The cross context virtual CPU structure.
4060 * @param offReg The offset of the 256-bit spare register.
4061 * @param uVector The vector to clear.
4062 *
4063 * @remarks This is based on our APIC device code.
4064 */
4065IEM_STATIC void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector)
4066{
4067 /* Determine the vector offset within the chunk. */
4068 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4069
4070 /* Read the chunk at the offset. */
4071 uint32_t uReg;
4072 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4073 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4074 if (RT_SUCCESS(rc))
4075 {
4076 /* Modify the chunk. */
4077 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4078 uReg &= ~RT_BIT(idxVectorBit);
4079
4080 /* Write the chunk. */
4081 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4082 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4083 uVector, offReg, GCPhysVirtApic, rc));
4084 }
4085 else
4086 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4087 uVector, offReg, GCPhysVirtApic, rc));
4088}
4089
4090
4091/**
4092 * Checks if a memory access to the APIC-access page must causes an APIC-access
4093 * VM-exit.
4094 *
4095 * @param pVCpu The cross context virtual CPU structure.
4096 * @param offAccess The offset of the register being accessed.
4097 * @param cbAccess The size of the access in bytes.
4098 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4099 * IEM_ACCESS_TYPE_WRITE).
4100 *
4101 * @remarks This must not be used for MSR-based APIC-access page accesses!
4102 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4103 */
4104IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4105{
4106 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4107 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4108
4109 /*
4110 * We must cause a VM-exit if any of the following are true:
4111 * - TPR shadowing isn't active.
4112 * - The access size exceeds 32-bits.
4113 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4114 *
4115 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4116 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4117 */
4118 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4119 || cbAccess > sizeof(uint32_t)
4120 || ((offAccess + cbAccess - 1) & 0xc)
4121 || offAccess >= XAPIC_OFF_END + 4)
4122 return true;
4123
4124 /*
4125 * If the access is part of an operation where we have already
4126 * virtualized a virtual-APIC write, we must cause a VM-exit.
4127 */
4128 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4129 return true;
4130
4131 /*
4132 * Check write accesses to the APIC-access page that cause VM-exits.
4133 */
4134 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4135 {
4136 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4137 {
4138 /*
4139 * With APIC-register virtualization, a write access to any of the
4140 * following registers are virtualized. Accessing any other register
4141 * causes a VM-exit.
4142 */
4143 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4144 switch (offAlignedAccess)
4145 {
4146 case XAPIC_OFF_ID:
4147 case XAPIC_OFF_TPR:
4148 case XAPIC_OFF_EOI:
4149 case XAPIC_OFF_LDR:
4150 case XAPIC_OFF_DFR:
4151 case XAPIC_OFF_SVR:
4152 case XAPIC_OFF_ESR:
4153 case XAPIC_OFF_ICR_LO:
4154 case XAPIC_OFF_ICR_HI:
4155 case XAPIC_OFF_LVT_TIMER:
4156 case XAPIC_OFF_LVT_THERMAL:
4157 case XAPIC_OFF_LVT_PERF:
4158 case XAPIC_OFF_LVT_LINT0:
4159 case XAPIC_OFF_LVT_LINT1:
4160 case XAPIC_OFF_LVT_ERROR:
4161 case XAPIC_OFF_TIMER_ICR:
4162 case XAPIC_OFF_TIMER_DCR:
4163 break;
4164 default:
4165 return true;
4166 }
4167 }
4168 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4169 {
4170 /*
4171 * With virtual-interrupt delivery, a write access to any of the
4172 * following registers are virtualized. Accessing any other register
4173 * causes a VM-exit.
4174 *
4175 * Note! The specification does not allow writing to offsets in-between
4176 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4177 */
4178 switch (offAccess)
4179 {
4180 case XAPIC_OFF_TPR:
4181 case XAPIC_OFF_EOI:
4182 case XAPIC_OFF_ICR_LO:
4183 break;
4184 default:
4185 return true;
4186 }
4187 }
4188 else
4189 {
4190 /*
4191 * Without APIC-register virtualization or virtual-interrupt delivery,
4192 * only TPR accesses are virtualized.
4193 */
4194 if (offAccess == XAPIC_OFF_TPR)
4195 { /* likely */ }
4196 else
4197 return true;
4198 }
4199 }
4200 else
4201 {
4202 /*
4203 * Check read accesses to the APIC-access page that cause VM-exits.
4204 */
4205 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4206 {
4207 /*
4208 * With APIC-register virtualization, a read access to any of the
4209 * following registers are virtualized. Accessing any other register
4210 * causes a VM-exit.
4211 */
4212 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4213 switch (offAlignedAccess)
4214 {
4215 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4216 case XAPIC_OFF_ID:
4217 case XAPIC_OFF_VERSION:
4218 case XAPIC_OFF_TPR:
4219 case XAPIC_OFF_EOI:
4220 case XAPIC_OFF_LDR:
4221 case XAPIC_OFF_DFR:
4222 case XAPIC_OFF_SVR:
4223 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4224 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4225 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4226 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4227 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4228 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4229 case XAPIC_OFF_ESR:
4230 case XAPIC_OFF_ICR_LO:
4231 case XAPIC_OFF_ICR_HI:
4232 case XAPIC_OFF_LVT_TIMER:
4233 case XAPIC_OFF_LVT_THERMAL:
4234 case XAPIC_OFF_LVT_PERF:
4235 case XAPIC_OFF_LVT_LINT0:
4236 case XAPIC_OFF_LVT_LINT1:
4237 case XAPIC_OFF_LVT_ERROR:
4238 case XAPIC_OFF_TIMER_ICR:
4239 case XAPIC_OFF_TIMER_DCR:
4240 break;
4241 default:
4242 return true;
4243 }
4244 }
4245 else
4246 {
4247 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4248 if (offAccess == XAPIC_OFF_TPR)
4249 { /* likely */ }
4250 else
4251 return true;
4252 }
4253 }
4254
4255 /* The APIC access is virtualized, does not cause a VM-exit. */
4256 return false;
4257}
4258
4259
4260/**
4261 * Virtualizes a memory-based APIC access where the address is not used to access
4262 * memory.
4263 *
4264 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4265 * page-faults but do not use the address to access memory.
4266 *
4267 * @param pVCpu The cross context virtual CPU structure.
4268 * @param pGCPhysAccess Pointer to the guest-physical address used.
4269 */
4270IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess)
4271{
4272 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4273 Assert(pGCPhysAccess);
4274
4275 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4276 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4277 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4278
4279 if (GCPhysAccess == GCPhysApic)
4280 {
4281 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4282 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4283 uint16_t const cbAccess = 1;
4284 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4285 if (fIntercept)
4286 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4287
4288 *pGCPhysAccess = GCPhysApic | offAccess;
4289 return VINF_VMX_MODIFIES_BEHAVIOR;
4290 }
4291
4292 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4293}
4294
4295
4296/**
4297 * Virtualizes a memory-based APIC access.
4298 *
4299 * @returns VBox strict status code.
4300 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4301 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4302 *
4303 * @param pVCpu The cross context virtual CPU structure.
4304 * @param offAccess The offset of the register being accessed (within the
4305 * APIC-access page).
4306 * @param cbAccess The size of the access in bytes.
4307 * @param pvData Pointer to the data being written or where to store the data
4308 * being read.
4309 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4310 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4311 */
4312IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4313 uint32_t fAccess)
4314{
4315 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4316 Assert(pvData);
4317 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4318 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4319 || (fAccess & IEM_ACCESS_INSTRUCTION));
4320
4321 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4322 if (fIntercept)
4323 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4324
4325 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4326 {
4327 /*
4328 * A write access to the APIC-access page that is virtualized (rather than
4329 * causing a VM-exit) writes data to the virtual-APIC page.
4330 */
4331 uint32_t const u32Data = *(uint32_t *)pvData;
4332 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4333
4334 /*
4335 * Record the currently updated APIC offset, as we need this later for figuring
4336 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4337 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4338 *
4339 * After completion of the current operation, we need to perform TPR virtualization,
4340 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4341 *
4342 * The current operation may be a REP-prefixed string instruction, execution of any
4343 * other instruction, or delivery of an event through the IDT.
4344 *
4345 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4346 * performed now but later after completion of the current operation.
4347 *
4348 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4349 */
4350 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4351 }
4352 else
4353 {
4354 /*
4355 * A read access from the APIC-access page that is virtualized (rather than
4356 * causing a VM-exit) returns data from the virtual-APIC page.
4357 *
4358 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4359 */
4360 Assert(cbAccess <= 4);
4361 Assert(offAccess < XAPIC_OFF_END + 4);
4362 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4363
4364 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4365 u32Data &= s_auAccessSizeMasks[cbAccess];
4366 *(uint32_t *)pvData = u32Data;
4367 }
4368
4369 return VINF_VMX_MODIFIES_BEHAVIOR;
4370}
4371
4372
4373/**
4374 * Virtualizes an MSR-based APIC read access.
4375 *
4376 * @returns VBox strict status code.
4377 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4378 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4379 * handled by the x2APIC device.
4380 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4381 * not within the range of valid MSRs, caller must raise \#GP(0).
4382 * @param pVCpu The cross context virtual CPU structure.
4383 * @param idMsr The x2APIC MSR being read.
4384 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4385 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4386 */
4387IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4388{
4389 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4390 Assert(pu64Value);
4391
4392 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4393 {
4394 if ( idMsr >= MSR_IA32_X2APIC_START
4395 && idMsr <= MSR_IA32_X2APIC_END)
4396 {
4397 uint16_t const offReg = (idMsr & 0xff) << 4;
4398 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4399 *pu64Value = u64Value;
4400 return VINF_VMX_MODIFIES_BEHAVIOR;
4401 }
4402 return VERR_OUT_OF_RANGE;
4403 }
4404
4405 if (idMsr == MSR_IA32_X2APIC_TPR)
4406 {
4407 uint16_t const offReg = (idMsr & 0xff) << 4;
4408 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4409 *pu64Value = u64Value;
4410 return VINF_VMX_MODIFIES_BEHAVIOR;
4411 }
4412
4413 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4414}
4415
4416
4417/**
4418 * Virtualizes an MSR-based APIC write access.
4419 *
4420 * @returns VBox strict status code.
4421 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4422 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4423 * not within the range of valid MSRs, caller must raise \#GP(0).
4424 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4425 *
4426 * @param pVCpu The cross context virtual CPU structure.
4427 * @param idMsr The x2APIC MSR being written.
4428 * @param u64Value The value of the x2APIC MSR being written.
4429 */
4430IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value)
4431{
4432 /*
4433 * Check if the access is to be virtualized.
4434 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4435 */
4436 if ( idMsr == MSR_IA32_X2APIC_TPR
4437 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4438 && ( idMsr == MSR_IA32_X2APIC_EOI
4439 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4440 {
4441 /* Validate the MSR write depending on the register. */
4442 switch (idMsr)
4443 {
4444 case MSR_IA32_X2APIC_TPR:
4445 case MSR_IA32_X2APIC_SELF_IPI:
4446 {
4447 if (u64Value & UINT64_C(0xffffffffffffff00))
4448 return VERR_OUT_OF_RANGE;
4449 break;
4450 }
4451 case MSR_IA32_X2APIC_EOI:
4452 {
4453 if (u64Value != 0)
4454 return VERR_OUT_OF_RANGE;
4455 break;
4456 }
4457 }
4458
4459 /* Write the MSR to the virtual-APIC page. */
4460 uint16_t const offReg = (idMsr & 0xff) << 4;
4461 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4462
4463 /*
4464 * Record the currently updated APIC offset, as we need this later for figuring
4465 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4466 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4467 */
4468 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4469
4470 return VINF_VMX_MODIFIES_BEHAVIOR;
4471 }
4472
4473 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4474}
4475
4476
4477/**
4478 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4479 *
4480 * @returns VBox status code.
4481 * @retval VINF_SUCCESS when the highest set bit is found.
4482 * @retval VERR_NOT_FOUND when no bit is set.
4483 *
4484 * @param pVCpu The cross context virtual CPU structure.
4485 * @param offReg The offset of the APIC 256-bit sparse register.
4486 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4487 * set in the register. Only valid when VINF_SUCCESS is
4488 * returned.
4489 *
4490 * @remarks The format of the 256-bit sparse register here mirrors that found in
4491 * real APIC hardware.
4492 */
4493static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4494{
4495 Assert(offReg < XAPIC_OFF_END + 4);
4496 Assert(pidxHighestBit);
4497
4498 /*
4499 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4500 * However, in each fragment only the first 4 bytes are used.
4501 */
4502 uint8_t const cFrags = 8;
4503 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4504 {
4505 uint16_t const offFrag = iFrag * 16;
4506 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4507 if (!u32Frag)
4508 continue;
4509
4510 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4511 Assert(idxHighestBit > 0);
4512 --idxHighestBit;
4513 Assert(idxHighestBit <= UINT8_MAX);
4514 *pidxHighestBit = idxHighestBit;
4515 return VINF_SUCCESS;
4516 }
4517 return VERR_NOT_FOUND;
4518}
4519
4520
4521/**
4522 * Evaluates pending virtual interrupts.
4523 *
4524 * @param pVCpu The cross context virtual CPU structure.
4525 */
4526IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu)
4527{
4528 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4529
4530 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4531 {
4532 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4533 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4534
4535 if ((uRvi >> 4) > (uPpr >> 4))
4536 {
4537 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4538 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4539 }
4540 else
4541 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4542 }
4543}
4544
4545
4546/**
4547 * Performs PPR virtualization.
4548 *
4549 * @returns VBox strict status code.
4550 * @param pVCpu The cross context virtual CPU structure.
4551 */
4552IEM_STATIC void iemVmxPprVirtualization(PVMCPUCC pVCpu)
4553{
4554 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4555 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4556
4557 /*
4558 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4559 * or EOI-virtualization.
4560 *
4561 * See Intel spec. 29.1.3 "PPR Virtualization".
4562 */
4563 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4564 uint32_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4565
4566 uint32_t uPpr;
4567 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4568 uPpr = uTpr & 0xff;
4569 else
4570 uPpr = uSvi & 0xf0;
4571
4572 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4573 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4574}
4575
4576
4577/**
4578 * Performs VMX TPR virtualization.
4579 *
4580 * @returns VBox strict status code.
4581 * @param pVCpu The cross context virtual CPU structure.
4582 */
4583IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu)
4584{
4585 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4586
4587 /*
4588 * We should have already performed the virtual-APIC write to the TPR offset
4589 * in the virtual-APIC page. We now perform TPR virtualization.
4590 *
4591 * See Intel spec. 29.1.2 "TPR Virtualization".
4592 */
4593 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4594 {
4595 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4596 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4597
4598 /*
4599 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4600 * See Intel spec. 29.1.2 "TPR Virtualization".
4601 */
4602 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4603 {
4604 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4605 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4606 }
4607 }
4608 else
4609 {
4610 iemVmxPprVirtualization(pVCpu);
4611 iemVmxEvalPendingVirtIntrs(pVCpu);
4612 }
4613
4614 return VINF_SUCCESS;
4615}
4616
4617
4618/**
4619 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4620 * not.
4621 *
4622 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4623 * @param pVCpu The cross context virtual CPU structure.
4624 * @param uVector The interrupt that was acknowledged using an EOI.
4625 */
4626IEM_STATIC bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector)
4627{
4628 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4629 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4630
4631 if (uVector < 64)
4632 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4633 if (uVector < 128)
4634 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4635 if (uVector < 192)
4636 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4637 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4638}
4639
4640
4641/**
4642 * Performs EOI virtualization.
4643 *
4644 * @returns VBox strict status code.
4645 * @param pVCpu The cross context virtual CPU structure.
4646 */
4647IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu)
4648{
4649 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4650 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4651
4652 /*
4653 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4654 * and get the next guest-interrupt that's in-service (if any).
4655 *
4656 * See Intel spec. 29.1.4 "EOI Virtualization".
4657 */
4658 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4659 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4660 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4661
4662 uint8_t uVector = uSvi;
4663 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4664
4665 uVector = 0;
4666 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4667
4668 if (uVector)
4669 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4670 else
4671 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4672
4673 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4674 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4675
4676 iemVmxPprVirtualization(pVCpu);
4677 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4678 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4679 iemVmxEvalPendingVirtIntrs(pVCpu);
4680 return VINF_SUCCESS;
4681}
4682
4683
4684/**
4685 * Performs self-IPI virtualization.
4686 *
4687 * @returns VBox strict status code.
4688 * @param pVCpu The cross context virtual CPU structure.
4689 */
4690IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu)
4691{
4692 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4693 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4694
4695 /*
4696 * We should have already performed the virtual-APIC write to the self-IPI offset
4697 * in the virtual-APIC page. We now perform self-IPI virtualization.
4698 *
4699 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4700 */
4701 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4702 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4703 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
4704 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4705 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4706 if (uVector > uRvi)
4707 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
4708 iemVmxEvalPendingVirtIntrs(pVCpu);
4709 return VINF_SUCCESS;
4710}
4711
4712
4713/**
4714 * Performs VMX APIC-write emulation.
4715 *
4716 * @returns VBox strict status code.
4717 * @param pVCpu The cross context virtual CPU structure.
4718 */
4719IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu)
4720{
4721 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4722
4723 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
4724 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4725
4726 /*
4727 * Perform APIC-write emulation based on the virtual-APIC register written.
4728 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4729 */
4730 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
4731 VBOXSTRICTRC rcStrict;
4732 switch (offApicWrite)
4733 {
4734 case XAPIC_OFF_TPR:
4735 {
4736 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
4737 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4738 uTpr &= UINT32_C(0x000000ff);
4739 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
4740 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
4741 rcStrict = iemVmxTprVirtualization(pVCpu);
4742 break;
4743 }
4744
4745 case XAPIC_OFF_EOI:
4746 {
4747 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4748 {
4749 /* Clear VEOI and perform EOI virtualization. */
4750 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
4751 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
4752 rcStrict = iemVmxEoiVirtualization(pVCpu);
4753 }
4754 else
4755 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4756 break;
4757 }
4758
4759 case XAPIC_OFF_ICR_LO:
4760 {
4761 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4762 {
4763 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
4764 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4765 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
4766 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
4767 if ( !(uIcrLo & fIcrLoMb0)
4768 && (uIcrLo & fIcrLoMb1))
4769 {
4770 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
4771 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
4772 }
4773 else
4774 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4775 }
4776 else
4777 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4778 break;
4779 }
4780
4781 case XAPIC_OFF_ICR_HI:
4782 {
4783 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
4784 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
4785 uIcrHi &= UINT32_C(0xff000000);
4786 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
4787 rcStrict = VINF_SUCCESS;
4788 break;
4789 }
4790
4791 default:
4792 {
4793 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
4794 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
4795 break;
4796 }
4797 }
4798
4799 return rcStrict;
4800}
4801
4802
4803/**
4804 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
4805 *
4806 * @param pVCpu The cross context virtual CPU structure.
4807 * @param pszInstr The VMX instruction name (for logging purposes).
4808 */
4809DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
4810{
4811 /*
4812 * Guest Control Registers, Debug Registers, and MSRs.
4813 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
4814 */
4815 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4816 const char * const pszFailure = "VM-exit";
4817 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4818
4819 /* CR0 reserved bits. */
4820 {
4821 /* CR0 MB1 bits. */
4822 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu);
4823 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
4824 { /* likely */ }
4825 else
4826 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
4827
4828 /* CR0 MBZ bits. */
4829 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
4830 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
4831 { /* likely */ }
4832 else
4833 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
4834
4835 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
4836 if ( !fUnrestrictedGuest
4837 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4838 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
4839 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
4840 }
4841
4842 /* CR4 reserved bits. */
4843 {
4844 /* CR4 MB1 bits. */
4845 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
4846 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
4847 { /* likely */ }
4848 else
4849 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
4850
4851 /* CR4 MBZ bits. */
4852 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
4853 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
4854 { /* likely */ }
4855 else
4856 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
4857 }
4858
4859 /* DEBUGCTL MSR. */
4860 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4861 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
4862 { /* likely */ }
4863 else
4864 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
4865
4866 /* 64-bit CPU checks. */
4867 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4868 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
4869 {
4870 if (fGstInLongMode)
4871 {
4872 /* PAE must be set. */
4873 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
4874 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
4875 { /* likely */ }
4876 else
4877 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
4878 }
4879 else
4880 {
4881 /* PCIDE should not be set. */
4882 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
4883 { /* likely */ }
4884 else
4885 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
4886 }
4887
4888 /* CR3. */
4889 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
4890 { /* likely */ }
4891 else
4892 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
4893
4894 /* DR7. */
4895 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4896 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
4897 { /* likely */ }
4898 else
4899 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
4900
4901 /* SYSENTER ESP and SYSENTER EIP. */
4902 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
4903 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
4904 { /* likely */ }
4905 else
4906 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
4907 }
4908
4909 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
4910 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
4911
4912 /* PAT MSR. */
4913 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
4914 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
4915 { /* likely */ }
4916 else
4917 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
4918
4919 /* EFER MSR. */
4920 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4921 {
4922 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
4923 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
4924 { /* likely */ }
4925 else
4926 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
4927
4928 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
4929 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
4930 if ( fGstLma == fGstInLongMode
4931 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
4932 || fGstLma == fGstLme))
4933 { /* likely */ }
4934 else
4935 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
4936 }
4937
4938 /* We don't support IA32_BNDCFGS MSR yet. */
4939 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
4940
4941 NOREF(pszInstr);
4942 NOREF(pszFailure);
4943 return VINF_SUCCESS;
4944}
4945
4946
4947/**
4948 * Checks guest segment registers, LDTR and TR as part of VM-entry.
4949 *
4950 * @param pVCpu The cross context virtual CPU structure.
4951 * @param pszInstr The VMX instruction name (for logging purposes).
4952 */
4953DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
4954{
4955 /*
4956 * Segment registers.
4957 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4958 */
4959 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4960 const char * const pszFailure = "VM-exit";
4961 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
4962 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
4963 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
4964
4965 /* Selectors. */
4966 if ( !fGstInV86Mode
4967 && !fUnrestrictedGuest
4968 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
4969 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
4970
4971 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
4972 {
4973 CPUMSELREG SelReg;
4974 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
4975 if (RT_LIKELY(rc == VINF_SUCCESS))
4976 { /* likely */ }
4977 else
4978 return rc;
4979
4980 /*
4981 * Virtual-8086 mode checks.
4982 */
4983 if (fGstInV86Mode)
4984 {
4985 /* Base address. */
4986 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
4987 { /* likely */ }
4988 else
4989 {
4990 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
4991 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
4992 }
4993
4994 /* Limit. */
4995 if (SelReg.u32Limit == 0xffff)
4996 { /* likely */ }
4997 else
4998 {
4999 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5000 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5001 }
5002
5003 /* Attribute. */
5004 if (SelReg.Attr.u == 0xf3)
5005 { /* likely */ }
5006 else
5007 {
5008 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5009 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5010 }
5011
5012 /* We're done; move to checking the next segment. */
5013 continue;
5014 }
5015
5016 /* Checks done by 64-bit CPUs. */
5017 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5018 {
5019 /* Base address. */
5020 if ( iSegReg == X86_SREG_FS
5021 || iSegReg == X86_SREG_GS)
5022 {
5023 if (X86_IS_CANONICAL(SelReg.u64Base))
5024 { /* likely */ }
5025 else
5026 {
5027 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5028 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5029 }
5030 }
5031 else if (iSegReg == X86_SREG_CS)
5032 {
5033 if (!RT_HI_U32(SelReg.u64Base))
5034 { /* likely */ }
5035 else
5036 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5037 }
5038 else
5039 {
5040 if ( SelReg.Attr.n.u1Unusable
5041 || !RT_HI_U32(SelReg.u64Base))
5042 { /* likely */ }
5043 else
5044 {
5045 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5046 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5047 }
5048 }
5049 }
5050
5051 /*
5052 * Checks outside Virtual-8086 mode.
5053 */
5054 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5055 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5056 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5057 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5058 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5059 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5060 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5061 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5062
5063 /* Code or usable segment. */
5064 if ( iSegReg == X86_SREG_CS
5065 || fUsable)
5066 {
5067 /* Reserved bits (bits 31:17 and bits 11:8). */
5068 if (!(SelReg.Attr.u & 0xfffe0f00))
5069 { /* likely */ }
5070 else
5071 {
5072 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5073 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5074 }
5075
5076 /* Descriptor type. */
5077 if (fCodeDataSeg)
5078 { /* likely */ }
5079 else
5080 {
5081 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5082 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5083 }
5084
5085 /* Present. */
5086 if (fPresent)
5087 { /* likely */ }
5088 else
5089 {
5090 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5091 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5092 }
5093
5094 /* Granularity. */
5095 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5096 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5097 { /* likely */ }
5098 else
5099 {
5100 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5101 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5102 }
5103 }
5104
5105 if (iSegReg == X86_SREG_CS)
5106 {
5107 /* Segment Type and DPL. */
5108 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5109 && fUnrestrictedGuest)
5110 {
5111 if (uDpl == 0)
5112 { /* likely */ }
5113 else
5114 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5115 }
5116 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5117 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5118 {
5119 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5120 if (uDpl == AttrSs.n.u2Dpl)
5121 { /* likely */ }
5122 else
5123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5124 }
5125 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5126 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5127 {
5128 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5129 if (uDpl <= AttrSs.n.u2Dpl)
5130 { /* likely */ }
5131 else
5132 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5133 }
5134 else
5135 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5136
5137 /* Def/Big. */
5138 if ( fGstInLongMode
5139 && fSegLong)
5140 {
5141 if (uDefBig == 0)
5142 { /* likely */ }
5143 else
5144 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5145 }
5146 }
5147 else if (iSegReg == X86_SREG_SS)
5148 {
5149 /* Segment Type. */
5150 if ( !fUsable
5151 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5152 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5153 { /* likely */ }
5154 else
5155 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5156
5157 /* DPL. */
5158 if (!fUnrestrictedGuest)
5159 {
5160 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5161 { /* likely */ }
5162 else
5163 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5164 }
5165 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5166 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5167 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5168 {
5169 if (uDpl == 0)
5170 { /* likely */ }
5171 else
5172 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5173 }
5174 }
5175 else
5176 {
5177 /* DS, ES, FS, GS. */
5178 if (fUsable)
5179 {
5180 /* Segment type. */
5181 if (uSegType & X86_SEL_TYPE_ACCESSED)
5182 { /* likely */ }
5183 else
5184 {
5185 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5186 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5187 }
5188
5189 if ( !(uSegType & X86_SEL_TYPE_CODE)
5190 || (uSegType & X86_SEL_TYPE_READ))
5191 { /* likely */ }
5192 else
5193 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5194
5195 /* DPL. */
5196 if ( !fUnrestrictedGuest
5197 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5198 {
5199 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5200 { /* likely */ }
5201 else
5202 {
5203 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5204 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5205 }
5206 }
5207 }
5208 }
5209 }
5210
5211 /*
5212 * LDTR.
5213 */
5214 {
5215 CPUMSELREG Ldtr;
5216 Ldtr.Sel = pVmcs->GuestLdtr;
5217 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5218 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5219 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5220
5221 if (!Ldtr.Attr.n.u1Unusable)
5222 {
5223 /* Selector. */
5224 if (!(Ldtr.Sel & X86_SEL_LDT))
5225 { /* likely */ }
5226 else
5227 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5228
5229 /* Base. */
5230 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5231 {
5232 if (X86_IS_CANONICAL(Ldtr.u64Base))
5233 { /* likely */ }
5234 else
5235 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5236 }
5237
5238 /* Attributes. */
5239 /* Reserved bits (bits 31:17 and bits 11:8). */
5240 if (!(Ldtr.Attr.u & 0xfffe0f00))
5241 { /* likely */ }
5242 else
5243 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5244
5245 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5246 { /* likely */ }
5247 else
5248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5249
5250 if (!Ldtr.Attr.n.u1DescType)
5251 { /* likely */ }
5252 else
5253 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5254
5255 if (Ldtr.Attr.n.u1Present)
5256 { /* likely */ }
5257 else
5258 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5259
5260 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5261 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5262 { /* likely */ }
5263 else
5264 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5265 }
5266 }
5267
5268 /*
5269 * TR.
5270 */
5271 {
5272 CPUMSELREG Tr;
5273 Tr.Sel = pVmcs->GuestTr;
5274 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5275 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5276 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5277
5278 /* Selector. */
5279 if (!(Tr.Sel & X86_SEL_LDT))
5280 { /* likely */ }
5281 else
5282 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5283
5284 /* Base. */
5285 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5286 {
5287 if (X86_IS_CANONICAL(Tr.u64Base))
5288 { /* likely */ }
5289 else
5290 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5291 }
5292
5293 /* Attributes. */
5294 /* Reserved bits (bits 31:17 and bits 11:8). */
5295 if (!(Tr.Attr.u & 0xfffe0f00))
5296 { /* likely */ }
5297 else
5298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5299
5300 if (!Tr.Attr.n.u1Unusable)
5301 { /* likely */ }
5302 else
5303 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5304
5305 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5306 || ( !fGstInLongMode
5307 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5308 { /* likely */ }
5309 else
5310 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5311
5312 if (!Tr.Attr.n.u1DescType)
5313 { /* likely */ }
5314 else
5315 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5316
5317 if (Tr.Attr.n.u1Present)
5318 { /* likely */ }
5319 else
5320 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5321
5322 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5323 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5324 { /* likely */ }
5325 else
5326 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5327 }
5328
5329 NOREF(pszInstr);
5330 NOREF(pszFailure);
5331 return VINF_SUCCESS;
5332}
5333
5334
5335/**
5336 * Checks guest GDTR and IDTR as part of VM-entry.
5337 *
5338 * @param pVCpu The cross context virtual CPU structure.
5339 * @param pszInstr The VMX instruction name (for logging purposes).
5340 */
5341DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5342{
5343 /*
5344 * GDTR and IDTR.
5345 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5346 */
5347 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5348 const char *const pszFailure = "VM-exit";
5349
5350 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5351 {
5352 /* Base. */
5353 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5354 { /* likely */ }
5355 else
5356 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5357
5358 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5359 { /* likely */ }
5360 else
5361 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5362 }
5363
5364 /* Limit. */
5365 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5366 { /* likely */ }
5367 else
5368 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5369
5370 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5371 { /* likely */ }
5372 else
5373 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5374
5375 NOREF(pszInstr);
5376 NOREF(pszFailure);
5377 return VINF_SUCCESS;
5378}
5379
5380
5381/**
5382 * Checks guest RIP and RFLAGS as part of VM-entry.
5383 *
5384 * @param pVCpu The cross context virtual CPU structure.
5385 * @param pszInstr The VMX instruction name (for logging purposes).
5386 */
5387DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5388{
5389 /*
5390 * RIP and RFLAGS.
5391 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5392 */
5393 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5394 const char *const pszFailure = "VM-exit";
5395 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5396
5397 /* RIP. */
5398 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5399 {
5400 X86DESCATTR AttrCs;
5401 AttrCs.u = pVmcs->u32GuestCsAttr;
5402 if ( !fGstInLongMode
5403 || !AttrCs.n.u1Long)
5404 {
5405 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5406 { /* likely */ }
5407 else
5408 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5409 }
5410
5411 if ( fGstInLongMode
5412 && AttrCs.n.u1Long)
5413 {
5414 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5415 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5416 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5417 { /* likely */ }
5418 else
5419 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5420 }
5421 }
5422
5423 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5424 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5425 : pVmcs->u64GuestRFlags.s.Lo;
5426 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5427 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5428 { /* likely */ }
5429 else
5430 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5431
5432 if (!(uGuestRFlags & X86_EFL_VM))
5433 { /* likely */ }
5434 else
5435 {
5436 if ( fGstInLongMode
5437 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5438 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5439 }
5440
5441 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5442 {
5443 if (uGuestRFlags & X86_EFL_IF)
5444 { /* likely */ }
5445 else
5446 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5447 }
5448
5449 NOREF(pszInstr);
5450 NOREF(pszFailure);
5451 return VINF_SUCCESS;
5452}
5453
5454
5455/**
5456 * Checks guest non-register state as part of VM-entry.
5457 *
5458 * @param pVCpu The cross context virtual CPU structure.
5459 * @param pszInstr The VMX instruction name (for logging purposes).
5460 */
5461DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5462{
5463 /*
5464 * Guest non-register state.
5465 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5466 */
5467 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5468 const char *const pszFailure = "VM-exit";
5469
5470 /*
5471 * Activity state.
5472 */
5473 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5474 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5475 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5476 { /* likely */ }
5477 else
5478 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5479
5480 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5481 if ( !AttrSs.n.u2Dpl
5482 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5483 { /* likely */ }
5484 else
5485 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5486
5487 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5488 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5489 {
5490 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5491 { /* likely */ }
5492 else
5493 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5494 }
5495
5496 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5497 {
5498 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5499 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5500 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5501 switch (pVmcs->u32GuestActivityState)
5502 {
5503 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5504 {
5505 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5506 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5507 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5508 && ( uVector == X86_XCPT_DB
5509 || uVector == X86_XCPT_MC))
5510 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5511 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5512 { /* likely */ }
5513 else
5514 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5515 break;
5516 }
5517
5518 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5519 {
5520 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5521 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5522 && uVector == X86_XCPT_MC))
5523 { /* likely */ }
5524 else
5525 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5526 break;
5527 }
5528
5529 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5530 default:
5531 break;
5532 }
5533 }
5534
5535 /*
5536 * Interruptibility state.
5537 */
5538 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5539 { /* likely */ }
5540 else
5541 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5542
5543 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5544 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5545 { /* likely */ }
5546 else
5547 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5548
5549 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5550 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5551 { /* likely */ }
5552 else
5553 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5554
5555 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5556 {
5557 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5558 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5559 {
5560 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5561 { /* likely */ }
5562 else
5563 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5564 }
5565 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5566 {
5567 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5568 { /* likely */ }
5569 else
5570 {
5571 /*
5572 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5573 * We update the Exit qualification only when blocking-by-STI is set
5574 * without blocking-by-MovSS being set. Although in practise it does not
5575 * make much difference since the order of checks are implementation defined.
5576 */
5577 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5578 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5579 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5580 }
5581
5582 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5583 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5584 { /* likely */ }
5585 else
5586 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5587 }
5588 }
5589
5590 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5591 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5592 { /* likely */ }
5593 else
5594 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5595
5596 /* We don't support SGX yet. So enclave-interruption must not be set. */
5597 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5598 { /* likely */ }
5599 else
5600 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5601
5602 /*
5603 * Pending debug exceptions.
5604 */
5605 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5606 ? pVmcs->u64GuestPendingDbgXcpts.u
5607 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5608 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5609 { /* likely */ }
5610 else
5611 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5612
5613 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5614 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5615 {
5616 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5617 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5618 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5619 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5620
5621 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5622 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5623 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5624 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5625 }
5626
5627 /* We don't support RTM (Real-time Transactional Memory) yet. */
5628 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5629 { /* likely */ }
5630 else
5631 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5632
5633 /*
5634 * VMCS link pointer.
5635 */
5636 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5637 {
5638 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5639 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5640 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5641 { /* likely */ }
5642 else
5643 {
5644 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5645 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5646 }
5647
5648 /* Validate the address. */
5649 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5650 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5651 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5652 { /* likely */ }
5653 else
5654 {
5655 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5656 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5657 }
5658 }
5659
5660 NOREF(pszInstr);
5661 NOREF(pszFailure);
5662 return VINF_SUCCESS;
5663}
5664
5665
5666#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5667/**
5668 * Checks guest PDPTEs as part of VM-entry.
5669 *
5670 * @param pVCpu The cross context virtual CPU structure.
5671 * @param pszInstr The VMX instruction name (for logging purposes).
5672 */
5673IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr)
5674{
5675 /*
5676 * Guest PDPTEs.
5677 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5678 */
5679 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5680 const char * const pszFailure = "VM-exit";
5681
5682 /*
5683 * When EPT is used, we only validate the PAE PDPTEs provided in the VMCS.
5684 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
5685 */
5686 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
5687 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
5688 {
5689 /* Get PDPTEs from the VMCS. */
5690 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
5691 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
5692 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
5693 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
5694 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
5695
5696 /* Check validity of the PDPTEs. */
5697 bool const fValid = PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]);
5698 if (fValid)
5699 { /* likely */ }
5700 else
5701 {
5702 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
5703 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
5704 }
5705 }
5706
5707 NOREF(pszFailure);
5708 NOREF(pszInstr);
5709 return VINF_SUCCESS;
5710}
5711#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
5712
5713
5714/**
5715 * Checks guest-state as part of VM-entry.
5716 *
5717 * @returns VBox status code.
5718 * @param pVCpu The cross context virtual CPU structure.
5719 * @param pszInstr The VMX instruction name (for logging purposes).
5720 */
5721IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr)
5722{
5723 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
5724 if (RT_SUCCESS(rc))
5725 {
5726 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
5727 if (RT_SUCCESS(rc))
5728 {
5729 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
5730 if (RT_SUCCESS(rc))
5731 {
5732 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
5733 if (RT_SUCCESS(rc))
5734 {
5735 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
5736#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5737 if (RT_SUCCESS(rc))
5738 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
5739#endif
5740 }
5741 }
5742 }
5743 }
5744 return rc;
5745}
5746
5747
5748/**
5749 * Checks host-state as part of VM-entry.
5750 *
5751 * @returns VBox status code.
5752 * @param pVCpu The cross context virtual CPU structure.
5753 * @param pszInstr The VMX instruction name (for logging purposes).
5754 */
5755IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr)
5756{
5757 /*
5758 * Host Control Registers and MSRs.
5759 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
5760 */
5761 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5762 const char * const pszFailure = "VMFail";
5763
5764 /* CR0 reserved bits. */
5765 {
5766 /* CR0 MB1 bits. */
5767 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu);
5768 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5769 { /* likely */ }
5770 else
5771 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
5772
5773 /* CR0 MBZ bits. */
5774 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5775 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
5776 { /* likely */ }
5777 else
5778 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
5779 }
5780
5781 /* CR4 reserved bits. */
5782 {
5783 /* CR4 MB1 bits. */
5784 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5785 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5786 { /* likely */ }
5787 else
5788 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
5789
5790 /* CR4 MBZ bits. */
5791 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5792 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
5793 { /* likely */ }
5794 else
5795 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
5796 }
5797
5798 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5799 {
5800 /* CR3 reserved bits. */
5801 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5802 { /* likely */ }
5803 else
5804 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
5805
5806 /* SYSENTER ESP and SYSENTER EIP. */
5807 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
5808 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
5809 { /* likely */ }
5810 else
5811 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
5812 }
5813
5814 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5815 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
5816
5817 /* PAT MSR. */
5818 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
5819 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
5820 { /* likely */ }
5821 else
5822 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
5823
5824 /* EFER MSR. */
5825 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5826 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
5827 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
5828 { /* likely */ }
5829 else
5830 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
5831
5832 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
5833 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
5834 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
5835 if ( fHostInLongMode == fHostLma
5836 && fHostInLongMode == fHostLme)
5837 { /* likely */ }
5838 else
5839 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
5840
5841 /*
5842 * Host Segment and Descriptor-Table Registers.
5843 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
5844 */
5845 /* Selector RPL and TI. */
5846 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
5847 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
5848 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
5849 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
5850 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
5851 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
5852 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
5853 { /* likely */ }
5854 else
5855 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
5856
5857 /* CS and TR selectors cannot be 0. */
5858 if ( pVmcs->HostCs
5859 && pVmcs->HostTr)
5860 { /* likely */ }
5861 else
5862 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
5863
5864 /* SS cannot be 0 if 32-bit host. */
5865 if ( fHostInLongMode
5866 || pVmcs->HostSs)
5867 { /* likely */ }
5868 else
5869 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
5870
5871 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5872 {
5873 /* FS, GS, GDTR, IDTR, TR base address. */
5874 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5875 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
5876 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
5877 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
5878 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
5879 { /* likely */ }
5880 else
5881 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
5882 }
5883
5884 /*
5885 * Host address-space size for 64-bit CPUs.
5886 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
5887 */
5888 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5889 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5890 {
5891 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
5892
5893 /* Logical processor in IA-32e mode. */
5894 if (fCpuInLongMode)
5895 {
5896 if (fHostInLongMode)
5897 {
5898 /* PAE must be set. */
5899 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
5900 { /* likely */ }
5901 else
5902 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
5903
5904 /* RIP must be canonical. */
5905 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
5906 { /* likely */ }
5907 else
5908 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
5909 }
5910 else
5911 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
5912 }
5913 else
5914 {
5915 /* Logical processor is outside IA-32e mode. */
5916 if ( !fGstInLongMode
5917 && !fHostInLongMode)
5918 {
5919 /* PCIDE should not be set. */
5920 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
5921 { /* likely */ }
5922 else
5923 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
5924
5925 /* The high 32-bits of RIP MBZ. */
5926 if (!pVmcs->u64HostRip.s.Hi)
5927 { /* likely */ }
5928 else
5929 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
5930 }
5931 else
5932 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
5933 }
5934 }
5935 else
5936 {
5937 /* Host address-space size for 32-bit CPUs. */
5938 if ( !fGstInLongMode
5939 && !fHostInLongMode)
5940 { /* likely */ }
5941 else
5942 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
5943 }
5944
5945 NOREF(pszInstr);
5946 NOREF(pszFailure);
5947 return VINF_SUCCESS;
5948}
5949
5950
5951#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5952/**
5953 * Checks the EPT pointer VMCS field as part of VM-entry.
5954 *
5955 * @returns VBox status code.
5956 * @param pVCpu The cross context virtual CPU structure.
5957 * @param uEptPtr The EPT pointer to check.
5958 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
5959 * updated on success). Optional, can be NULL.
5960 */
5961IEM_STATIC int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr, VMXVDIAG *penmVmxDiag)
5962{
5963 VMXVDIAG enmVmxDiag;
5964
5965 /* Reserved bits. */
5966 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
5967 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
5968 if (uEptPtr & fValidMask)
5969 {
5970 /* Memory Type. */
5971 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
5972 uint8_t const fMemType = RT_BF_GET(uEptPtr, VMX_BF_EPTP_MEMTYPE);
5973 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
5974 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
5975 || ( fMemType == VMX_EPTP_MEMTYPE_UC
5976 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
5977 {
5978 /*
5979 * Page walk length (PML4).
5980 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
5981 * of 5 but that seems to be removed from the latest specs. leaving only PML4
5982 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
5983 */
5984 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
5985 if (RT_BF_GET(uEptPtr, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
5986 {
5987 /* Access and dirty bits support in EPT structures. */
5988 if ( !RT_BF_GET(uEptPtr, VMX_BF_EPTP_ACCESS_DIRTY)
5989 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
5990 return VINF_SUCCESS;
5991
5992 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
5993 }
5994 else
5995 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
5996 }
5997 else
5998 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
5999 }
6000 else
6001 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
6002
6003 if (penmVmxDiag)
6004 *penmVmxDiag = enmVmxDiag;
6005 return VERR_VMX_VMENTRY_FAILED;
6006}
6007#endif
6008
6009
6010/**
6011 * Checks VMCS controls fields as part of VM-entry.
6012 *
6013 * @returns VBox status code.
6014 * @param pVCpu The cross context virtual CPU structure.
6015 * @param pszInstr The VMX instruction name (for logging purposes).
6016 *
6017 * @remarks This may update secondary-processor based VM-execution control fields
6018 * in the current VMCS if necessary.
6019 */
6020IEM_STATIC int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr)
6021{
6022 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6023 const char * const pszFailure = "VMFail";
6024 bool const fVmxTrueMsrs = RT_BOOL(pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
6025
6026 /*
6027 * VM-execution controls.
6028 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6029 */
6030 {
6031 /* Pin-based VM-execution controls. */
6032 {
6033 VMXCTLSMSR const PinCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TruePinCtls
6034 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6035 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6036 { /* likely */ }
6037 else
6038 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6039
6040 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6041 { /* likely */ }
6042 else
6043 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6044 }
6045
6046 /* Processor-based VM-execution controls. */
6047 {
6048 VMXCTLSMSR const ProcCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueProcCtls
6049 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6050 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6051 { /* likely */ }
6052 else
6053 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6054
6055 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6056 { /* likely */ }
6057 else
6058 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6059 }
6060
6061 /* Secondary processor-based VM-execution controls. */
6062 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6063 {
6064 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6065 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6066 { /* likely */ }
6067 else
6068 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6069
6070 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6071 { /* likely */ }
6072 else
6073 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6074 }
6075 else
6076 Assert(!pVmcs->u32ProcCtls2);
6077
6078 /* CR3-target count. */
6079 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6080 { /* likely */ }
6081 else
6082 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6083
6084 /* I/O bitmaps physical addresses. */
6085 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6086 {
6087 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6088 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6089 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6090 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6091 { /* likely */ }
6092 else
6093 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6094
6095 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6096 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6097 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6098 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6099 { /* likely */ }
6100 else
6101 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6102 }
6103
6104 /* MSR bitmap physical address. */
6105 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6106 {
6107 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6108 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6109 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6110 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6111 { /* likely */ }
6112 else
6113 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6114 }
6115
6116 /* TPR shadow related controls. */
6117 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6118 {
6119 /* Virtual-APIC page physical address. */
6120 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6121 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6122 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6123 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6124 { /* likely */ }
6125 else
6126 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6127
6128 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6129 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6130 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6131 { /* likely */ }
6132 else
6133 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6134
6135 /* The rest done XXX document */
6136 }
6137 else
6138 {
6139 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6140 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6141 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6142 { /* likely */ }
6143 else
6144 {
6145 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6146 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6147 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6149 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6150 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6151 }
6152 }
6153
6154 /* NMI exiting and virtual-NMIs. */
6155 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6156 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6157 { /* likely */ }
6158 else
6159 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6160
6161 /* Virtual-NMIs and NMI-window exiting. */
6162 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6163 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6164 { /* likely */ }
6165 else
6166 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6167
6168 /* Virtualize APIC accesses. */
6169 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6170 {
6171 /* APIC-access physical address. */
6172 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6173 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6174 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6175 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6176 { /* likely */ }
6177 else
6178 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6179
6180 /*
6181 * Disallow APIC-access page and virtual-APIC page from being the same address.
6182 * Note! This is not an Intel requirement, but one imposed by our implementation.
6183 */
6184 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6185 * redirecting accesses between the APIC-access page and the virtual-APIC
6186 * page. If any nested hypervisor requires this, we can implement it later. */
6187 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6188 {
6189 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6190 if (GCPhysVirtApic != GCPhysApicAccess)
6191 { /* likely */ }
6192 else
6193 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6194 }
6195 }
6196
6197 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6198 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6199 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6200 { /* likely */ }
6201 else
6202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6203
6204 /* Virtual-interrupt delivery requires external interrupt exiting. */
6205 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6206 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6207 { /* likely */ }
6208 else
6209 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6210
6211 /* VPID. */
6212 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6213 || pVmcs->u16Vpid != 0)
6214 { /* likely */ }
6215 else
6216 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6217
6218#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6219 /* Extended-Page-Table Pointer (EPTP). */
6220 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6221 {
6222 VMXVDIAG enmVmxDiag;
6223 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, pVmcs->u64EptPtr.u, &enmVmxDiag);
6224 if (RT_SUCCESS(rc))
6225 { /* likely */ }
6226 else
6227 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6228 }
6229#else
6230 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6231 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST));
6232#endif
6233 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6234 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6235 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6236 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6237 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6238 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6239
6240 /* VMCS shadowing. */
6241 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6242 {
6243 /* VMREAD-bitmap physical address. */
6244 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6245 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6246 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6247 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6248 { /* likely */ }
6249 else
6250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6251
6252 /* VMWRITE-bitmap physical address. */
6253 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6254 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6255 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6256 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6257 { /* likely */ }
6258 else
6259 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6260 }
6261 }
6262
6263 /*
6264 * VM-exit controls.
6265 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6266 */
6267 {
6268 VMXCTLSMSR const ExitCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueExitCtls
6269 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6270 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6271 { /* likely */ }
6272 else
6273 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6274
6275 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6276 { /* likely */ }
6277 else
6278 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6279
6280 /* Save preemption timer without activating it. */
6281 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6282 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6283 { /* likely */ }
6284 else
6285 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6286
6287 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6288 if (pVmcs->u32ExitMsrStoreCount)
6289 {
6290 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6291 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6292 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6293 { /* likely */ }
6294 else
6295 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6296 }
6297
6298 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6299 if (pVmcs->u32ExitMsrLoadCount)
6300 {
6301 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6302 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6303 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6304 { /* likely */ }
6305 else
6306 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6307 }
6308 }
6309
6310 /*
6311 * VM-entry controls.
6312 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6313 */
6314 {
6315 VMXCTLSMSR const EntryCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueEntryCtls
6316 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6317 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6318 { /* likely */ }
6319 else
6320 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6321
6322 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6323 { /* likely */ }
6324 else
6325 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6326
6327 /* Event injection. */
6328 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6329 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6330 {
6331 /* Type and vector. */
6332 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6333 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6334 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6335 if ( !uRsvd
6336 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6337 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6338 { /* likely */ }
6339 else
6340 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6341
6342 /* Exception error code. */
6343 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6344 {
6345 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6346 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6347 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6348 { /* likely */ }
6349 else
6350 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6351
6352 /* Exceptions that provide an error code. */
6353 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6354 && ( uVector == X86_XCPT_DF
6355 || uVector == X86_XCPT_TS
6356 || uVector == X86_XCPT_NP
6357 || uVector == X86_XCPT_SS
6358 || uVector == X86_XCPT_GP
6359 || uVector == X86_XCPT_PF
6360 || uVector == X86_XCPT_AC))
6361 { /* likely */ }
6362 else
6363 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6364
6365 /* Exception error-code reserved bits. */
6366 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6367 { /* likely */ }
6368 else
6369 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6370
6371 /* Injecting a software interrupt, software exception or privileged software exception. */
6372 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6373 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6374 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6375 {
6376 /* Instruction length must be in the range 0-15. */
6377 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6378 { /* likely */ }
6379 else
6380 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6381
6382 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6383 if ( pVmcs->u32EntryInstrLen != 0
6384 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6385 { /* likely */ }
6386 else
6387 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6388 }
6389 }
6390 }
6391
6392 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6393 if (pVmcs->u32EntryMsrLoadCount)
6394 {
6395 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6396 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6397 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6398 { /* likely */ }
6399 else
6400 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6401 }
6402
6403 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6404 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6405 }
6406
6407 NOREF(pszInstr);
6408 NOREF(pszFailure);
6409 return VINF_SUCCESS;
6410}
6411
6412
6413/**
6414 * Loads the guest control registers, debug register and some MSRs as part of
6415 * VM-entry.
6416 *
6417 * @param pVCpu The cross context virtual CPU structure.
6418 */
6419IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu)
6420{
6421 /*
6422 * Load guest control registers, debug registers and MSRs.
6423 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6424 */
6425 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6426
6427 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6428 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6429 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6430 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6431 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6432 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6433
6434 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6435 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6436
6437 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6438 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6439 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6440
6441 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6442 {
6443 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6444
6445 /* EFER MSR. */
6446 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6447 {
6448 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6449 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6450 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6451 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6452 if (fGstInLongMode)
6453 {
6454 /* If the nested-guest is in long mode, LMA and LME are both set. */
6455 Assert(fGstPaging);
6456 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6457 }
6458 else
6459 {
6460 /*
6461 * If the nested-guest is outside long mode:
6462 * - With paging: LMA is cleared, LME is cleared.
6463 * - Without paging: LMA is cleared, LME is left unmodified.
6464 */
6465 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6466 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6467 }
6468 }
6469 /* else: see below. */
6470 }
6471
6472 /* PAT MSR. */
6473 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6474 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6475
6476 /* EFER MSR. */
6477 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6478 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6479
6480 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6481 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6482
6483 /* We don't support IA32_BNDCFGS MSR yet. */
6484 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6485
6486 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6487}
6488
6489
6490/**
6491 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6492 *
6493 * @param pVCpu The cross context virtual CPU structure.
6494 */
6495IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu)
6496{
6497 /*
6498 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6499 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6500 */
6501 /* CS, SS, ES, DS, FS, GS. */
6502 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6503 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6504 {
6505 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6506 CPUMSELREG VmcsSelReg;
6507 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6508 AssertRC(rc); NOREF(rc);
6509 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6510 {
6511 pGstSelReg->Sel = VmcsSelReg.Sel;
6512 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6513 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6514 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6515 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6516 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6517 }
6518 else
6519 {
6520 pGstSelReg->Sel = VmcsSelReg.Sel;
6521 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6522 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6523 switch (iSegReg)
6524 {
6525 case X86_SREG_CS:
6526 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6527 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6528 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6529 break;
6530
6531 case X86_SREG_SS:
6532 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6533 pGstSelReg->u32Limit = 0;
6534 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6535 break;
6536
6537 case X86_SREG_ES:
6538 case X86_SREG_DS:
6539 pGstSelReg->u64Base = 0;
6540 pGstSelReg->u32Limit = 0;
6541 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6542 break;
6543
6544 case X86_SREG_FS:
6545 case X86_SREG_GS:
6546 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6547 pGstSelReg->u32Limit = 0;
6548 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6549 break;
6550 }
6551 Assert(pGstSelReg->Attr.n.u1Unusable);
6552 }
6553 }
6554
6555 /* LDTR. */
6556 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6557 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6558 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6559 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6560 {
6561 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6562 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6563 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6564 }
6565 else
6566 {
6567 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6568 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6569 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6570 }
6571
6572 /* TR. */
6573 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6574 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6575 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6576 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6577 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6578 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6579 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6580
6581 /* GDTR. */
6582 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6583 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6584
6585 /* IDTR. */
6586 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6587 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6588}
6589
6590
6591/**
6592 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6593 *
6594 * @returns VBox status code.
6595 * @param pVCpu The cross context virtual CPU structure.
6596 * @param pszInstr The VMX instruction name (for logging purposes).
6597 */
6598IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr)
6599{
6600 /*
6601 * Load guest MSRs.
6602 * See Intel spec. 26.4 "Loading MSRs".
6603 */
6604 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6605 const char *const pszFailure = "VM-exit";
6606
6607 /*
6608 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6609 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6610 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6611 */
6612 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6613 if (!cMsrs)
6614 return VINF_SUCCESS;
6615
6616 /*
6617 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6618 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6619 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6620 */
6621 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6622 if (fIsMsrCountValid)
6623 { /* likely */ }
6624 else
6625 {
6626 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6627 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6628 }
6629
6630 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6631 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6632 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6633 if (RT_SUCCESS(rc))
6634 {
6635 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6636 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6637 {
6638 if ( !pMsr->u32Reserved
6639 && pMsr->u32Msr != MSR_K8_FS_BASE
6640 && pMsr->u32Msr != MSR_K8_GS_BASE
6641 && pMsr->u32Msr != MSR_K6_EFER
6642 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6643 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6644 {
6645 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6646 if (rcStrict == VINF_SUCCESS)
6647 continue;
6648
6649 /*
6650 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6651 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6652 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6653 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6654 * MSR in ring-0 if possible, or come up with a better, generic solution.
6655 */
6656 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6657 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6658 ? kVmxVDiag_Vmentry_MsrLoadRing3
6659 : kVmxVDiag_Vmentry_MsrLoad;
6660 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6661 }
6662 else
6663 {
6664 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6665 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6666 }
6667 }
6668 }
6669 else
6670 {
6671 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6672 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6673 }
6674
6675 NOREF(pszInstr);
6676 NOREF(pszFailure);
6677 return VINF_SUCCESS;
6678}
6679
6680
6681/**
6682 * Loads the guest-state non-register state as part of VM-entry.
6683 *
6684 * @returns VBox status code.
6685 * @param pVCpu The cross context virtual CPU structure.
6686 * @param pszInstr The VMX instruction name (for logging purposes).
6687 *
6688 * @remarks This must be called only after loading the nested-guest register state
6689 * (especially nested-guest RIP).
6690 */
6691IEM_STATIC int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
6692{
6693 /*
6694 * Load guest non-register state.
6695 * See Intel spec. 26.6 "Special Features of VM Entry"
6696 */
6697 const char *const pszFailure = "VM-exit";
6698 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6699
6700 /*
6701 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
6702 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
6703 *
6704 * See Intel spec. 26.6.1 "Interruptibility State".
6705 */
6706 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
6707 if ( !fEntryVectoring
6708 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
6709 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
6710 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6711 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6712
6713 /* NMI blocking. */
6714 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6715 {
6716 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6717 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
6718 else
6719 {
6720 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6721 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6722 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6723 }
6724 }
6725 else
6726 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
6727
6728 /* SMI blocking is irrelevant. We don't support SMIs yet. */
6729
6730 /*
6731 * Set PGM's copy of the EPT pointer.
6732 * The EPTP has already been validated while checking guest state.
6733 *
6734 * It is important to do this prior to mapping PAE PDPTEs (below).
6735 */
6736 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6737 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
6738
6739 /*
6740 * Load the guest's PAE PDPTEs.
6741 */
6742 if (iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
6743 {
6744 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6745 {
6746 /*
6747 * With EPT, we've already validated these while checking the guest state.
6748 * Just load them directly from the VMCS here.
6749 */
6750 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6751 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6752 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6753 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6754 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6755 AssertCompile(RT_ELEMENTS(aPaePdptes) == RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes));
6756 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes); i++)
6757 pVCpu->cpum.GstCtx.aPaePdpes[i].u = aPaePdptes[i].u;
6758 }
6759 else
6760 {
6761 /*
6762 * Without EPT, we must load the PAE PDPTEs referenced by CR3.
6763 * This involves loading (and mapping) CR3 and validating them now.
6764 */
6765 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
6766 if (RT_SUCCESS(rc))
6767 { /* likely */ }
6768 else
6769 {
6770 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6771 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6772 }
6773 }
6774 }
6775
6776 /* VPID is irrelevant. We don't support VPID yet. */
6777
6778 /* Clear address-range monitoring. */
6779 EMMonitorWaitClear(pVCpu);
6780
6781 return VINF_SUCCESS;
6782}
6783
6784
6785/**
6786 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
6787 *
6788 * @param pVCpu The cross context virtual CPU structure.
6789 * @param pszInstr The VMX instruction name (for logging purposes).
6790 *
6791 * @remarks This assumes various VMCS related data structure pointers have already
6792 * been verified prior to calling this function.
6793 */
6794IEM_STATIC int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr)
6795{
6796 const char *const pszFailure = "VM-exit";
6797 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6798
6799 /*
6800 * Virtualize APIC accesses.
6801 */
6802 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6803 {
6804 /* APIC-access physical address. */
6805 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6806
6807 /*
6808 * Register the handler for the APIC-access page.
6809 *
6810 * We don't deregister the APIC-access page handler during the VM-exit as a different
6811 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6812 *
6813 * We leave the page registered until the first access that happens outside VMX non-root
6814 * mode. Guest software is allowed to access structures such as the APIC-access page
6815 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6816 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6817 *
6818 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6819 */
6820 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6821 {
6822 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6823 PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
6824 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess + X86_PAGE_4K_SIZE - 1,
6825 pVCpu0->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6826 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6827 if (RT_SUCCESS(rc))
6828 { /* likely */ }
6829 else
6830 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6831 }
6832 }
6833
6834 /*
6835 * VMCS shadowing.
6836 */
6837 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6838 {
6839 /* Read the VMREAD-bitmap. */
6840 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6841 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
6842 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
6843 if (RT_SUCCESS(rc))
6844 { /* likely */ }
6845 else
6846 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6847
6848 /* Read the VMWRITE-bitmap. */
6849 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
6850 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
6851 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
6852 if (RT_SUCCESS(rc))
6853 { /* likely */ }
6854 else
6855 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6856 }
6857
6858 /*
6859 * I/O bitmaps.
6860 */
6861 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6862 {
6863 /* Read the IO bitmap A. */
6864 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6865 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
6866 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
6867 if (RT_SUCCESS(rc))
6868 { /* likely */ }
6869 else
6870 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
6871
6872 /* Read the IO bitmap B. */
6873 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6874 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
6875 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
6876 if (RT_SUCCESS(rc))
6877 { /* likely */ }
6878 else
6879 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
6880 }
6881
6882 /*
6883 * TPR shadow and Virtual-APIC page.
6884 */
6885 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6886 {
6887 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
6888 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6889 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6890 {
6891 /* Read the VTPR from the virtual-APIC page. */
6892 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6893 uint8_t u8VTpr;
6894 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
6895 if (RT_SUCCESS(rc))
6896 { /* likely */ }
6897 else
6898 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6899
6900 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
6901 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
6902 { /* likely */ }
6903 else
6904 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6905 }
6906 }
6907
6908 /*
6909 * VMCS link pointer.
6910 */
6911 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6912 {
6913 /* Read the VMCS-link pointer from guest memory. */
6914 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6915 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
6916 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
6917 if (RT_SUCCESS(rc))
6918 { /* likely */ }
6919 else
6920 {
6921 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6922 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
6923 }
6924
6925 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
6926 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
6927 { /* likely */ }
6928 else
6929 {
6930 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6931 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
6932 }
6933
6934 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
6935 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6936 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
6937 { /* likely */ }
6938 else
6939 {
6940 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6941 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
6942 }
6943
6944 /* Update our cache of the guest physical address of the shadow VMCS. */
6945 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
6946 }
6947
6948 /*
6949 * MSR bitmap.
6950 */
6951 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6952 {
6953 /* Read the MSR bitmap. */
6954 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6955 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
6956 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
6957 if (RT_SUCCESS(rc))
6958 { /* likely */ }
6959 else
6960 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6961 }
6962
6963 NOREF(pszFailure);
6964 NOREF(pszInstr);
6965 return VINF_SUCCESS;
6966}
6967
6968
6969/**
6970 * Loads the guest-state as part of VM-entry.
6971 *
6972 * @returns VBox status code.
6973 * @param pVCpu The cross context virtual CPU structure.
6974 * @param pszInstr The VMX instruction name (for logging purposes).
6975 *
6976 * @remarks This must be done after all the necessary steps prior to loading of
6977 * guest-state (e.g. checking various VMCS state).
6978 */
6979IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr)
6980{
6981 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
6982 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
6983
6984 /* Load guest segment registers. */
6985 iemVmxVmentryLoadGuestSegRegs(pVCpu);
6986
6987 /*
6988 * Load guest RIP, RSP and RFLAGS.
6989 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
6990 */
6991 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6992 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
6993 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
6994 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
6995
6996 /* Initialize the PAUSE-loop controls as part of VM-entry. */
6997 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
6998 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
6999
7000 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
7001 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
7002 if (rc == VINF_SUCCESS)
7003 { /* likely */ }
7004 else
7005 return rc;
7006
7007 /* Load VMX related structures and state referenced by the VMCS. */
7008 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
7009 if (rc == VINF_SUCCESS)
7010 { /* likely */ }
7011 else
7012 return rc;
7013
7014 NOREF(pszInstr);
7015 return VINF_SUCCESS;
7016}
7017
7018
7019/**
7020 * Returns whether there are is a pending debug exception on VM-entry.
7021 *
7022 * @param pVCpu The cross context virtual CPU structure.
7023 * @param pszInstr The VMX instruction name (for logging purposes).
7024 */
7025IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr)
7026{
7027 /*
7028 * Pending debug exceptions.
7029 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7030 */
7031 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7032 Assert(pVmcs);
7033
7034 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7035 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7036 if (fPendingDbgXcpt)
7037 {
7038 uint8_t uEntryIntInfoType;
7039 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7040 if (fEntryVectoring)
7041 {
7042 switch (uEntryIntInfoType)
7043 {
7044 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7045 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7046 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7047 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7048 fPendingDbgXcpt = false;
7049 break;
7050
7051 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7052 {
7053 /*
7054 * Whether the pending debug exception for software exceptions other than
7055 * #BP and #OF is delivered after injecting the exception or is discard
7056 * is CPU implementation specific. We will discard them (easier).
7057 */
7058 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7059 if ( uVector != X86_XCPT_BP
7060 && uVector != X86_XCPT_OF)
7061 fPendingDbgXcpt = false;
7062 RT_FALL_THRU();
7063 }
7064 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7065 {
7066 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7067 fPendingDbgXcpt = false;
7068 break;
7069 }
7070 }
7071 }
7072 else
7073 {
7074 /*
7075 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7076 * pending debug exception is held pending or is discarded is CPU implementation
7077 * specific. We will discard them (easier).
7078 */
7079 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7080 fPendingDbgXcpt = false;
7081
7082 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7083 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7084 fPendingDbgXcpt = false;
7085 }
7086 }
7087
7088 NOREF(pszInstr);
7089 return fPendingDbgXcpt;
7090}
7091
7092
7093/**
7094 * Set up the monitor-trap flag (MTF).
7095 *
7096 * @param pVCpu The cross context virtual CPU structure.
7097 * @param pszInstr The VMX instruction name (for logging purposes).
7098 */
7099IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr)
7100{
7101 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7102 Assert(pVmcs);
7103 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7104 {
7105 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7106 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7107 }
7108 else
7109 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7110 NOREF(pszInstr);
7111}
7112
7113
7114/**
7115 * Sets up NMI-window exiting.
7116 *
7117 * @param pVCpu The cross context virtual CPU structure.
7118 * @param pszInstr The VMX instruction name (for logging purposes).
7119 */
7120IEM_STATIC void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr)
7121{
7122 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7123 Assert(pVmcs);
7124 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7125 {
7126 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7127 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7128 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7129 }
7130 else
7131 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7132 NOREF(pszInstr);
7133}
7134
7135
7136/**
7137 * Sets up interrupt-window exiting.
7138 *
7139 * @param pVCpu The cross context virtual CPU structure.
7140 * @param pszInstr The VMX instruction name (for logging purposes).
7141 */
7142IEM_STATIC void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr)
7143{
7144 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7145 Assert(pVmcs);
7146 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7147 {
7148 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7149 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7150 }
7151 else
7152 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7153 NOREF(pszInstr);
7154}
7155
7156
7157/**
7158 * Set up the VMX-preemption timer.
7159 *
7160 * @param pVCpu The cross context virtual CPU structure.
7161 * @param pszInstr The VMX instruction name (for logging purposes).
7162 */
7163IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr)
7164{
7165 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7166 Assert(pVmcs);
7167 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7168 {
7169 /*
7170 * If the timer is 0, we must cause a VM-exit before executing the first
7171 * nested-guest instruction. So we can flag as though the timer has already
7172 * expired and we will check and cause a VM-exit at the right priority elsewhere
7173 * in the code.
7174 */
7175 uint64_t uEntryTick;
7176 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7177 if (uPreemptTimer)
7178 {
7179 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7180 AssertRC(rc);
7181 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7182 }
7183 else
7184 {
7185 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7186 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7187 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7188 }
7189
7190 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7191 }
7192 else
7193 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7194
7195 NOREF(pszInstr);
7196}
7197
7198
7199/**
7200 * Injects an event using TRPM given a VM-entry interruption info. and related
7201 * fields.
7202 *
7203 * @param pVCpu The cross context virtual CPU structure.
7204 * @param pszInstr The VMX instruction name (for logging purposes).
7205 * @param uEntryIntInfo The VM-entry interruption info.
7206 * @param uErrCode The error code associated with the event if any.
7207 * @param cbInstr The VM-entry instruction length (for software
7208 * interrupts and software exceptions). Pass 0
7209 * otherwise.
7210 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7211 */
7212IEM_STATIC void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7213 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress)
7214{
7215 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7216
7217 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7218 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7219 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7220
7221 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7222
7223 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7224 AssertRC(rc);
7225 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7226
7227 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7228 {
7229 TRPMSetErrorCode(pVCpu, uErrCode);
7230 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7231 }
7232
7233 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7234 {
7235 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7236 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7237 }
7238 else
7239 {
7240 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7241 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7242 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7243 {
7244 TRPMSetInstrLength(pVCpu, cbInstr);
7245 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7246 }
7247 }
7248
7249 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7250 {
7251 TRPMSetTrapDueToIcebp(pVCpu);
7252 Log(("%s: Injecting: icebp\n", pszInstr));
7253 }
7254
7255 NOREF(pszInstr);
7256}
7257
7258
7259/**
7260 * Performs event injection (if any) as part of VM-entry.
7261 *
7262 * @param pVCpu The cross context virtual CPU structure.
7263 * @param pszInstr The VMX instruction name (for logging purposes).
7264 */
7265IEM_STATIC void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr)
7266{
7267 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7268
7269 /*
7270 * Inject events.
7271 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7272 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7273 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7274 * the actually delivery of this event.
7275 *
7276 * See Intel spec. 26.5 "Event Injection".
7277 */
7278 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7279 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7280
7281 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7282 if (fEntryIntInfoValid)
7283 {
7284 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7285 {
7286 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7287 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7288 }
7289 else
7290 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7291 pVCpu->cpum.GstCtx.cr2);
7292
7293 /*
7294 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7295 *
7296 * However, we do it here on VM-entry as well because while it isn't visible to guest
7297 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7298 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7299 *
7300 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7301 */
7302 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7303 }
7304 else
7305 {
7306 /*
7307 * Inject any pending guest debug exception.
7308 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7309 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7310 */
7311 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7312 if (fPendingDbgXcpt)
7313 {
7314 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7315 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7316 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7317 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7318 0 /* GCPtrFaultAddress */);
7319 }
7320 }
7321
7322 NOREF(pszInstr);
7323}
7324
7325
7326/**
7327 * Initializes all read-only VMCS fields as part of VM-entry.
7328 *
7329 * @param pVCpu The cross context virtual CPU structure.
7330 */
7331IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu)
7332{
7333 /*
7334 * Any VMCS field which we do not establish on every VM-exit but may potentially
7335 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7336 * specified to be undefined, needs to be initialized here.
7337 *
7338 * Thus, it is especially important to clear the Exit qualification field
7339 * since it must be zero for VM-exits where it is not used. Similarly, the
7340 * VM-exit interruption information field's valid bit needs to be cleared for
7341 * the same reasons.
7342 */
7343 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7344 Assert(pVmcs);
7345
7346 /* 16-bit (none currently). */
7347 /* 32-bit. */
7348 pVmcs->u32RoVmInstrError = 0;
7349 pVmcs->u32RoExitReason = 0;
7350 pVmcs->u32RoExitIntInfo = 0;
7351 pVmcs->u32RoExitIntErrCode = 0;
7352 pVmcs->u32RoIdtVectoringInfo = 0;
7353 pVmcs->u32RoIdtVectoringErrCode = 0;
7354 pVmcs->u32RoExitInstrLen = 0;
7355 pVmcs->u32RoExitInstrInfo = 0;
7356
7357 /* 64-bit. */
7358 pVmcs->u64RoGuestPhysAddr.u = 0;
7359
7360 /* Natural-width. */
7361 pVmcs->u64RoExitQual.u = 0;
7362 pVmcs->u64RoIoRcx.u = 0;
7363 pVmcs->u64RoIoRsi.u = 0;
7364 pVmcs->u64RoIoRdi.u = 0;
7365 pVmcs->u64RoIoRip.u = 0;
7366 pVmcs->u64RoGuestLinearAddr.u = 0;
7367}
7368
7369
7370/**
7371 * VMLAUNCH/VMRESUME instruction execution worker.
7372 *
7373 * @returns Strict VBox status code.
7374 * @param pVCpu The cross context virtual CPU structure.
7375 * @param cbInstr The instruction length in bytes.
7376 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7377 * VMXINSTRID_VMRESUME).
7378 *
7379 * @remarks Common VMX instruction checks are already expected to by the caller,
7380 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7381 */
7382IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7383{
7384# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7385 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7386 return VINF_EM_RAW_EMULATE_INSTR;
7387# else
7388 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7389 || uInstrId == VMXINSTRID_VMRESUME);
7390 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7391
7392 /* Nested-guest intercept. */
7393 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7394 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7395
7396 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7397
7398 /*
7399 * Basic VM-entry checks.
7400 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7401 * The checks following that do not have to follow a specific order.
7402 *
7403 * See Intel spec. 26.1 "Basic VM-entry Checks".
7404 */
7405
7406 /* CPL. */
7407 if (pVCpu->iem.s.uCpl == 0)
7408 { /* likely */ }
7409 else
7410 {
7411 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7412 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7413 return iemRaiseGeneralProtectionFault0(pVCpu);
7414 }
7415
7416 /* Current VMCS valid. */
7417 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7418 { /* likely */ }
7419 else
7420 {
7421 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7422 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7423 iemVmxVmFailInvalid(pVCpu);
7424 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7425 return VINF_SUCCESS;
7426 }
7427
7428 /* Current VMCS is not a shadow VMCS. */
7429 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7430 { /* likely */ }
7431 else
7432 {
7433 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7434 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7435 iemVmxVmFailInvalid(pVCpu);
7436 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7437 return VINF_SUCCESS;
7438 }
7439
7440 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7441 * use block-by-STI here which is not quite correct. */
7442 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7443 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7444 { /* likely */ }
7445 else
7446 {
7447 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7448 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7449 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7450 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7451 return VINF_SUCCESS;
7452 }
7453
7454 if (uInstrId == VMXINSTRID_VMLAUNCH)
7455 {
7456 /* VMLAUNCH with non-clear VMCS. */
7457 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7458 { /* likely */ }
7459 else
7460 {
7461 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7462 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7463 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7464 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7465 return VINF_SUCCESS;
7466 }
7467 }
7468 else
7469 {
7470 /* VMRESUME with non-launched VMCS. */
7471 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7472 { /* likely */ }
7473 else
7474 {
7475 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7476 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7477 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7478 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7479 return VINF_SUCCESS;
7480 }
7481 }
7482
7483 /*
7484 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7485 * while entering VMX non-root mode. We do some of this while checking VM-execution
7486 * controls. The nested hypervisor should not make assumptions and cannot expect
7487 * predictable behavior if changes to these structures are made in guest memory while
7488 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7489 * modify them anyway as we cache them in host memory.
7490 *
7491 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7492 */
7493 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7494 Assert(pVmcs);
7495 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7496
7497 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7498 if (RT_SUCCESS(rc))
7499 {
7500 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7501 if (RT_SUCCESS(rc))
7502 {
7503 /*
7504 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7505 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7506 * ones that may occur during VM-entry below).
7507 */
7508 iemVmxVmentryInitReadOnlyFields(pVCpu);
7509
7510 /*
7511 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7512 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7513 * VM-exit when required.
7514 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7515 */
7516 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7517
7518 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7519 if (RT_SUCCESS(rc))
7520 {
7521 /*
7522 * We've now entered nested-guest execution.
7523 *
7524 * It is important do this prior to loading the guest state because
7525 * as part of loading the guest state, PGM (and perhaps other components
7526 * in the future) relies on detecting whether VMX non-root mode has been
7527 * entered.
7528 */
7529 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7530
7531 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7532 if (RT_SUCCESS(rc))
7533 {
7534 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7535 if (RT_SUCCESS(rc))
7536 {
7537 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7538
7539 /* VMLAUNCH instruction must update the VMCS launch state. */
7540 if (uInstrId == VMXINSTRID_VMLAUNCH)
7541 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7542
7543 /* Perform the VMX transition (PGM updates). */
7544 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7545 if (rcStrict == VINF_SUCCESS)
7546 { /* likely */ }
7547 else if (RT_SUCCESS(rcStrict))
7548 {
7549 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7550 VBOXSTRICTRC_VAL(rcStrict)));
7551 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7552 }
7553 else
7554 {
7555 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7556 return rcStrict;
7557 }
7558
7559 /* Paranoia. */
7560 Assert(rcStrict == VINF_SUCCESS);
7561
7562 /*
7563 * The priority of potential VM-exits during VM-entry is important.
7564 * The priorities of VM-exits and events are listed from highest
7565 * to lowest as follows:
7566 *
7567 * 1. Event injection.
7568 * 2. Trap on task-switch (T flag set in TSS).
7569 * 3. TPR below threshold / APIC-write.
7570 * 4. SMI, INIT.
7571 * 5. MTF exit.
7572 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7573 * 7. VMX-preemption timer.
7574 * 9. NMI-window exit.
7575 * 10. NMI injection.
7576 * 11. Interrupt-window exit.
7577 * 12. Virtual-interrupt injection.
7578 * 13. Interrupt injection.
7579 * 14. Process next instruction (fetch, decode, execute).
7580 */
7581
7582 /* Setup VMX-preemption timer. */
7583 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7584
7585 /* Setup monitor-trap flag. */
7586 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7587
7588 /* Setup NMI-window exiting. */
7589 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7590
7591 /* Setup interrupt-window exiting. */
7592 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7593
7594 /*
7595 * Inject any event that the nested hypervisor wants to inject.
7596 * Note! We cannot immediately perform the event injection here as we may have
7597 * pending PGM operations to perform due to switching page tables and/or
7598 * mode.
7599 */
7600 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7601
7602# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7603 /* Reschedule to IEM-only execution of the nested-guest. */
7604 Log(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7605 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7606 if (rcSched != VINF_SUCCESS)
7607 iemSetPassUpStatus(pVCpu, rcSched);
7608# endif
7609
7610 /* Finally, done. */
7611 Log3(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64\n",
7612 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7613 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7614 pVCpu->cpum.GstCtx.msrEFER));
7615 return VINF_SUCCESS;
7616 }
7617 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7618 }
7619 }
7620 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7621 }
7622
7623 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7624 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7625 return VINF_SUCCESS;
7626 }
7627
7628 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7629 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7630 return VINF_SUCCESS;
7631# endif
7632}
7633
7634
7635/**
7636 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7637 * (causes a VM-exit) or not.
7638 *
7639 * @returns @c true if the instruction is intercepted, @c false otherwise.
7640 * @param pVCpu The cross context virtual CPU structure.
7641 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7642 * VMX_EXIT_WRMSR).
7643 * @param idMsr The MSR.
7644 */
7645IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7646{
7647 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7648 Assert( uExitReason == VMX_EXIT_RDMSR
7649 || uExitReason == VMX_EXIT_WRMSR);
7650
7651 /* Consult the MSR bitmap if the feature is supported. */
7652 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7653 Assert(pVmcs);
7654 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7655 {
7656 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7657 if (uExitReason == VMX_EXIT_RDMSR)
7658 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
7659 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
7660 }
7661
7662 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7663 return true;
7664}
7665
7666
7667/**
7668 * VMREAD instruction execution worker that does not perform any validation checks.
7669 *
7670 * Callers are expected to have performed the necessary checks and to ensure the
7671 * VMREAD will succeed.
7672 *
7673 * @param pVmcs Pointer to the virtual VMCS.
7674 * @param pu64Dst Where to write the VMCS value.
7675 * @param u64VmcsField The VMCS field.
7676 *
7677 * @remarks May be called with interrupts disabled.
7678 */
7679IEM_STATIC void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField)
7680{
7681 VMXVMCSFIELD VmcsField;
7682 VmcsField.u = u64VmcsField;
7683 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7684 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7685 uint8_t const uWidthType = (uWidth << 2) | uType;
7686 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7687 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7688 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7689 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
7690 uWidth, uType, uIndex, uIndex));
7691 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7692
7693 /*
7694 * Read the VMCS component based on the field's effective width.
7695 *
7696 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7697 * indicates high bits (little endian).
7698 *
7699 * Note! The caller is responsible to trim the result and update registers
7700 * or memory locations are required. Here we just zero-extend to the largest
7701 * type (i.e. 64-bits).
7702 */
7703 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
7704 uint8_t const *pbField = pbVmcs + offField;
7705 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7706 switch (uEffWidth)
7707 {
7708 case VMX_VMCSFIELD_WIDTH_64BIT:
7709 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
7710 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
7711 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
7712 }
7713}
7714
7715
7716/**
7717 * VMREAD common (memory/register) instruction execution worker.
7718 *
7719 * @returns Strict VBox status code.
7720 * @param pVCpu The cross context virtual CPU structure.
7721 * @param cbInstr The instruction length in bytes.
7722 * @param pu64Dst Where to write the VMCS value (only updated when
7723 * VINF_SUCCESS is returned).
7724 * @param u64VmcsField The VMCS field.
7725 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7726 * NULL.
7727 */
7728IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7729 PCVMXVEXITINFO pExitInfo)
7730{
7731 /* Nested-guest intercept. */
7732 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7733 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
7734 {
7735 if (pExitInfo)
7736 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7737 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7738 }
7739
7740 /* CPL. */
7741 if (pVCpu->iem.s.uCpl == 0)
7742 { /* likely */ }
7743 else
7744 {
7745 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7746 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7747 return iemRaiseGeneralProtectionFault0(pVCpu);
7748 }
7749
7750 /* VMCS pointer in root mode. */
7751 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7752 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7753 { /* likely */ }
7754 else
7755 {
7756 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7757 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7758 iemVmxVmFailInvalid(pVCpu);
7759 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7760 return VINF_SUCCESS;
7761 }
7762
7763 /* VMCS-link pointer in non-root mode. */
7764 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7765 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7766 { /* likely */ }
7767 else
7768 {
7769 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7770 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7771 iemVmxVmFailInvalid(pVCpu);
7772 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7773 return VINF_SUCCESS;
7774 }
7775
7776 /* Supported VMCS field. */
7777 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
7778 { /* likely */ }
7779 else
7780 {
7781 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
7782 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7783 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
7784 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7785 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7786 return VINF_SUCCESS;
7787 }
7788
7789 /*
7790 * Reading from the current or shadow VMCS.
7791 */
7792 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7793 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
7794 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
7795 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
7796 return VINF_SUCCESS;
7797}
7798
7799
7800/**
7801 * VMREAD (64-bit register) instruction execution worker.
7802 *
7803 * @returns Strict VBox status code.
7804 * @param pVCpu The cross context virtual CPU structure.
7805 * @param cbInstr The instruction length in bytes.
7806 * @param pu64Dst Where to store the VMCS field's value.
7807 * @param u64VmcsField The VMCS field.
7808 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7809 * NULL.
7810 */
7811IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64VmcsField,
7812 PCVMXVEXITINFO pExitInfo)
7813{
7814 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
7815 if (rcStrict == VINF_SUCCESS)
7816 {
7817 iemVmxVmreadSuccess(pVCpu, cbInstr);
7818 return VINF_SUCCESS;
7819 }
7820
7821 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7822 return rcStrict;
7823}
7824
7825
7826/**
7827 * VMREAD (32-bit register) instruction execution worker.
7828 *
7829 * @returns Strict VBox status code.
7830 * @param pVCpu The cross context virtual CPU structure.
7831 * @param cbInstr The instruction length in bytes.
7832 * @param pu32Dst Where to store the VMCS field's value.
7833 * @param u32VmcsField The VMCS field.
7834 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7835 * NULL.
7836 */
7837IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32VmcsField,
7838 PCVMXVEXITINFO pExitInfo)
7839{
7840 uint64_t u64Dst;
7841 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
7842 if (rcStrict == VINF_SUCCESS)
7843 {
7844 *pu32Dst = u64Dst;
7845 iemVmxVmreadSuccess(pVCpu, cbInstr);
7846 return VINF_SUCCESS;
7847 }
7848
7849 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7850 return rcStrict;
7851}
7852
7853
7854/**
7855 * VMREAD (memory) instruction execution worker.
7856 *
7857 * @returns Strict VBox status code.
7858 * @param pVCpu The cross context virtual CPU structure.
7859 * @param cbInstr The instruction length in bytes.
7860 * @param iEffSeg The effective segment register to use with @a u64Val.
7861 * Pass UINT8_MAX if it is a register access.
7862 * @param GCPtrDst The guest linear address to store the VMCS field's
7863 * value.
7864 * @param u64VmcsField The VMCS field.
7865 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7866 * NULL.
7867 */
7868IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst, uint64_t u64VmcsField,
7869 PCVMXVEXITINFO pExitInfo)
7870{
7871 uint64_t u64Dst;
7872 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
7873 if (rcStrict == VINF_SUCCESS)
7874 {
7875 /*
7876 * Write the VMCS field's value to the location specified in guest-memory.
7877 */
7878 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7879 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7880 else
7881 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7882 if (rcStrict == VINF_SUCCESS)
7883 {
7884 iemVmxVmreadSuccess(pVCpu, cbInstr);
7885 return VINF_SUCCESS;
7886 }
7887
7888 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7889 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7890 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
7891 return rcStrict;
7892 }
7893
7894 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7895 return rcStrict;
7896}
7897
7898
7899/**
7900 * VMWRITE instruction execution worker that does not perform any validation
7901 * checks.
7902 *
7903 * Callers are expected to have performed the necessary checks and to ensure the
7904 * VMWRITE will succeed.
7905 *
7906 * @param pVmcs Pointer to the virtual VMCS.
7907 * @param u64Val The value to write.
7908 * @param u64VmcsField The VMCS field.
7909 *
7910 * @remarks May be called with interrupts disabled.
7911 */
7912IEM_STATIC void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField)
7913{
7914 VMXVMCSFIELD VmcsField;
7915 VmcsField.u = u64VmcsField;
7916 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
7917 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
7918 uint8_t const uWidthType = (uWidth << 2) | uType;
7919 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
7920 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
7921 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7922 Assert(offField < VMX_V_VMCS_SIZE);
7923 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
7924
7925 /*
7926 * Write the VMCS component based on the field's effective width.
7927 *
7928 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7929 * indicates high bits (little endian).
7930 */
7931 uint8_t *pbVmcs = (uint8_t *)pVmcs;
7932 uint8_t *pbField = pbVmcs + offField;
7933 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
7934 switch (uEffWidth)
7935 {
7936 case VMX_VMCSFIELD_WIDTH_64BIT:
7937 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
7938 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
7939 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
7940 }
7941}
7942
7943
7944/**
7945 * VMWRITE instruction execution worker.
7946 *
7947 * @returns Strict VBox status code.
7948 * @param pVCpu The cross context virtual CPU structure.
7949 * @param cbInstr The instruction length in bytes.
7950 * @param iEffSeg The effective segment register to use with @a u64Val.
7951 * Pass UINT8_MAX if it is a register access.
7952 * @param u64Val The value to write (or guest linear address to the
7953 * value), @a iEffSeg will indicate if it's a memory
7954 * operand.
7955 * @param u64VmcsField The VMCS field.
7956 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
7957 * NULL.
7958 */
7959IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val, uint64_t u64VmcsField,
7960 PCVMXVEXITINFO pExitInfo)
7961{
7962 /* Nested-guest intercept. */
7963 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7964 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
7965 {
7966 if (pExitInfo)
7967 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7968 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7969 }
7970
7971 /* CPL. */
7972 if (pVCpu->iem.s.uCpl == 0)
7973 { /* likely */ }
7974 else
7975 {
7976 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7977 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
7978 return iemRaiseGeneralProtectionFault0(pVCpu);
7979 }
7980
7981 /* VMCS pointer in root mode. */
7982 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7983 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7984 { /* likely */ }
7985 else
7986 {
7987 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7988 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
7989 iemVmxVmFailInvalid(pVCpu);
7990 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7991 return VINF_SUCCESS;
7992 }
7993
7994 /* VMCS-link pointer in non-root mode. */
7995 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7996 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7997 { /* likely */ }
7998 else
7999 {
8000 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8001 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8002 iemVmxVmFailInvalid(pVCpu);
8003 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8004 return VINF_SUCCESS;
8005 }
8006
8007 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8008 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8009 if (!fIsRegOperand)
8010 {
8011 /* Read the value from the specified guest memory location. */
8012 VBOXSTRICTRC rcStrict;
8013 RTGCPTR const GCPtrVal = u64Val;
8014 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8015 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8016 else
8017 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8018 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8019 {
8020 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8021 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8022 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
8023 return rcStrict;
8024 }
8025 }
8026 else
8027 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8028
8029 /* Supported VMCS field. */
8030 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8031 { /* likely */ }
8032 else
8033 {
8034 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8035 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8036 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8037 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8038 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8039 return VINF_SUCCESS;
8040 }
8041
8042 /* Read-only VMCS field. */
8043 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8044 if ( !fIsFieldReadOnly
8045 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8046 { /* likely */ }
8047 else
8048 {
8049 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8050 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8051 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8052 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8053 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8054 return VINF_SUCCESS;
8055 }
8056
8057 /*
8058 * Write to the current or shadow VMCS.
8059 */
8060 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8061 PVMXVVMCS pVmcs = !fInVmxNonRootMode
8062 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8063 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8064 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8065
8066 if ( VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM))
8067 && !fInVmxNonRootMode)
8068 {
8069 /* Notify HM that the VMCS content might have changed. */
8070 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8071 }
8072
8073 iemVmxVmSucceed(pVCpu);
8074 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8075 return VINF_SUCCESS;
8076}
8077
8078
8079/**
8080 * VMCLEAR instruction execution worker.
8081 *
8082 * @returns Strict VBox status code.
8083 * @param pVCpu The cross context virtual CPU structure.
8084 * @param cbInstr The instruction length in bytes.
8085 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8086 * @param GCPtrVmcs The linear address of the VMCS pointer.
8087 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8088 *
8089 * @remarks Common VMX instruction checks are already expected to by the caller,
8090 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8091 */
8092IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8093 PCVMXVEXITINFO pExitInfo)
8094{
8095 /* Nested-guest intercept. */
8096 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8097 {
8098 if (pExitInfo)
8099 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8100 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8101 }
8102
8103 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8104
8105 /* CPL. */
8106 if (pVCpu->iem.s.uCpl == 0)
8107 { /* likely */ }
8108 else
8109 {
8110 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8111 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8112 return iemRaiseGeneralProtectionFault0(pVCpu);
8113 }
8114
8115 /* Get the VMCS pointer from the location specified by the source memory operand. */
8116 RTGCPHYS GCPhysVmcs;
8117 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8118 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8119 { /* likely */ }
8120 else
8121 {
8122 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8123 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8124 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8125 return rcStrict;
8126 }
8127
8128 /* VMCS pointer alignment. */
8129 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8130 { /* likely */ }
8131 else
8132 {
8133 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8134 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8135 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8136 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8137 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8138 return VINF_SUCCESS;
8139 }
8140
8141 /* VMCS physical-address width limits. */
8142 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8143 { /* likely */ }
8144 else
8145 {
8146 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8147 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8148 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8149 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8150 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8151 return VINF_SUCCESS;
8152 }
8153
8154 /* VMCS is not the VMXON region. */
8155 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8156 { /* likely */ }
8157 else
8158 {
8159 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8160 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8161 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8162 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8163 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8164 return VINF_SUCCESS;
8165 }
8166
8167 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8168 restriction imposed by our implementation. */
8169 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8170 { /* likely */ }
8171 else
8172 {
8173 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8174 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8175 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8176 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8177 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8178 return VINF_SUCCESS;
8179 }
8180
8181 /*
8182 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8183 *
8184 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8185 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8186 * to 'clear'.
8187 */
8188 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8189 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8190 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8191 {
8192 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8193 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8194 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8195 }
8196 else
8197 {
8198 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8199 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8200 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8201 if (RT_FAILURE(rcStrict))
8202 return rcStrict;
8203 }
8204
8205 iemVmxVmSucceed(pVCpu);
8206 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8207 return VINF_SUCCESS;
8208}
8209
8210
8211/**
8212 * VMPTRST instruction execution worker.
8213 *
8214 * @returns Strict VBox status code.
8215 * @param pVCpu The cross context virtual CPU structure.
8216 * @param cbInstr The instruction length in bytes.
8217 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8218 * @param GCPtrVmcs The linear address of where to store the current VMCS
8219 * pointer.
8220 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8221 *
8222 * @remarks Common VMX instruction checks are already expected to by the caller,
8223 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8224 */
8225IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8226 PCVMXVEXITINFO pExitInfo)
8227{
8228 /* Nested-guest intercept. */
8229 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8230 {
8231 if (pExitInfo)
8232 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8233 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8234 }
8235
8236 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8237
8238 /* CPL. */
8239 if (pVCpu->iem.s.uCpl == 0)
8240 { /* likely */ }
8241 else
8242 {
8243 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8244 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8245 return iemRaiseGeneralProtectionFault0(pVCpu);
8246 }
8247
8248 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8249 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8250 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8251 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8252 {
8253 iemVmxVmSucceed(pVCpu);
8254 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8255 return rcStrict;
8256 }
8257
8258 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8259 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8260 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8261 return rcStrict;
8262}
8263
8264
8265/**
8266 * VMPTRLD instruction execution worker.
8267 *
8268 * @returns Strict VBox status code.
8269 * @param pVCpu The cross context virtual CPU structure.
8270 * @param cbInstr The instruction length in bytes.
8271 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8272 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8273 *
8274 * @remarks Common VMX instruction checks are already expected to by the caller,
8275 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8276 */
8277IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8278 PCVMXVEXITINFO pExitInfo)
8279{
8280 /* Nested-guest intercept. */
8281 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8282 {
8283 if (pExitInfo)
8284 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8285 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8286 }
8287
8288 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8289
8290 /* CPL. */
8291 if (pVCpu->iem.s.uCpl == 0)
8292 { /* likely */ }
8293 else
8294 {
8295 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8296 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8297 return iemRaiseGeneralProtectionFault0(pVCpu);
8298 }
8299
8300 /* Get the VMCS pointer from the location specified by the source memory operand. */
8301 RTGCPHYS GCPhysVmcs;
8302 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8303 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8304 { /* likely */ }
8305 else
8306 {
8307 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8308 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8309 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8310 return rcStrict;
8311 }
8312
8313 /* VMCS pointer alignment. */
8314 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8315 { /* likely */ }
8316 else
8317 {
8318 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8319 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8320 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8321 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8322 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8323 return VINF_SUCCESS;
8324 }
8325
8326 /* VMCS physical-address width limits. */
8327 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8328 { /* likely */ }
8329 else
8330 {
8331 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8332 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8333 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8334 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8335 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8336 return VINF_SUCCESS;
8337 }
8338
8339 /* VMCS is not the VMXON region. */
8340 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8341 { /* likely */ }
8342 else
8343 {
8344 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8345 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8346 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8347 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8348 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8349 return VINF_SUCCESS;
8350 }
8351
8352 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8353 restriction imposed by our implementation. */
8354 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8355 { /* likely */ }
8356 else
8357 {
8358 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8359 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8360 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8361 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8362 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8363 return VINF_SUCCESS;
8364 }
8365
8366 /* Read just the VMCS revision from the VMCS. */
8367 VMXVMCSREVID VmcsRevId;
8368 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8369 if (RT_SUCCESS(rc))
8370 { /* likely */ }
8371 else
8372 {
8373 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8374 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8375 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8376 return rc;
8377 }
8378
8379 /*
8380 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8381 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8382 */
8383 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8384 && ( !VmcsRevId.n.fIsShadowVmcs
8385 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8386 { /* likely */ }
8387 else
8388 {
8389 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8390 {
8391 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8392 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8393 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8394 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8395 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8396 return VINF_SUCCESS;
8397 }
8398
8399 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8400 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8401 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8402 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8403 return VINF_SUCCESS;
8404 }
8405
8406 /*
8407 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8408 * the cache of an existing, current VMCS back to guest memory before loading a new,
8409 * different current VMCS.
8410 */
8411 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8412 {
8413 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8414 {
8415 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8416 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8417 }
8418
8419 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8420 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8421 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8422 if (RT_SUCCESS(rc))
8423 {
8424 /* Notify HM that a new, current VMCS is loaded. */
8425 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8426 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8427 }
8428 else
8429 {
8430 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8431 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8432 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8433 return rc;
8434 }
8435 }
8436
8437 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8438 iemVmxVmSucceed(pVCpu);
8439 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8440 return VINF_SUCCESS;
8441}
8442
8443
8444/**
8445 * INVVPID instruction execution worker.
8446 *
8447 * @returns Strict VBox status code.
8448 * @param pVCpu The cross context virtual CPU structure.
8449 * @param cbInstr The instruction length in bytes.
8450 * @param iEffSeg The segment of the invvpid descriptor.
8451 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8452 * @param u64InvvpidType The invalidation type.
8453 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8454 * NULL.
8455 *
8456 * @remarks Common VMX instruction checks are already expected to by the caller,
8457 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8458 */
8459IEM_STATIC VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8460 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo)
8461{
8462 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8463 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8464 return iemRaiseUndefinedOpcode(pVCpu);
8465
8466 /* Nested-guest intercept. */
8467 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8468 {
8469 if (pExitInfo)
8470 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8471 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8472 }
8473
8474 /* CPL. */
8475 if (pVCpu->iem.s.uCpl != 0)
8476 {
8477 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
8478 return iemRaiseGeneralProtectionFault0(pVCpu);
8479 }
8480
8481 /*
8482 * Validate INVVPID invalidation type.
8483 *
8484 * The instruction specifies exactly ONE of the supported invalidation types.
8485 *
8486 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8487 * supported. In theory, it's possible for a CPU to not support flushing individual
8488 * addresses but all the other types or any other combination. We do not take any
8489 * shortcuts here by assuming the types we currently expose to the guest.
8490 */
8491 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8492 bool const fInvvpidSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID);
8493 bool const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
8494 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
8495 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
8496 bool const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
8497
8498 bool afSupportedTypes[4];
8499 afSupportedTypes[0] = fTypeIndivAddr;
8500 afSupportedTypes[1] = fTypeSingleCtx;
8501 afSupportedTypes[2] = fTypeAllCtx;
8502 afSupportedTypes[3] = fTypeSingleCtxRetainGlobals;
8503
8504 if ( fInvvpidSupported
8505 && !(u64InvvpidType & ~(uint64_t)VMX_INVVPID_VALID_MASK)
8506 && afSupportedTypes[u64InvvpidType & 3])
8507 { /* likely */ }
8508 else
8509 {
8510 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
8511 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
8512 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8513 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8514 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8515 return VINF_SUCCESS;
8516 }
8517
8518 /*
8519 * Fetch the invvpid descriptor from guest memory.
8520 */
8521 RTUINT128U uDesc;
8522 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
8523 if (rcStrict == VINF_SUCCESS)
8524 {
8525 /*
8526 * Validate the descriptor.
8527 */
8528 if (uDesc.s.Lo > 0xfff)
8529 {
8530 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
8531 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
8532 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
8533 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8534 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8535 return VINF_SUCCESS;
8536 }
8537
8538 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8539 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
8540 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
8541 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8542 switch (u64InvvpidType)
8543 {
8544 case VMXTLBFLUSHVPID_INDIV_ADDR:
8545 {
8546 if (uVpid != 0)
8547 {
8548 if (IEM_IS_CANONICAL(GCPtrInvAddr))
8549 {
8550 /* Invalidate mappings for the linear address tagged with VPID. */
8551 /** @todo PGM support for VPID? Currently just flush everything. */
8552 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8553 iemVmxVmSucceed(pVCpu);
8554 }
8555 else
8556 {
8557 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
8558 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
8559 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
8560 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8561 }
8562 }
8563 else
8564 {
8565 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8566 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
8567 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8568 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8569 }
8570 break;
8571 }
8572
8573 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
8574 {
8575 if (uVpid != 0)
8576 {
8577 /* Invalidate all mappings with VPID. */
8578 /** @todo PGM support for VPID? Currently just flush everything. */
8579 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8580 iemVmxVmSucceed(pVCpu);
8581 }
8582 else
8583 {
8584 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8585 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
8586 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
8587 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8588 }
8589 break;
8590 }
8591
8592 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
8593 {
8594 /* Invalidate all mappings with non-zero VPIDs. */
8595 /** @todo PGM support for VPID? Currently just flush everything. */
8596 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8597 iemVmxVmSucceed(pVCpu);
8598 break;
8599 }
8600
8601 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
8602 {
8603 if (uVpid != 0)
8604 {
8605 /* Invalidate all mappings with VPID except global translations. */
8606 /** @todo PGM support for VPID? Currently just flush everything. */
8607 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8608 iemVmxVmSucceed(pVCpu);
8609 }
8610 else
8611 {
8612 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
8613 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
8614 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
8615 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8616 }
8617 break;
8618 }
8619 IEM_NOT_REACHED_DEFAULT_CASE_RET();
8620 }
8621 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8622 }
8623 return rcStrict;
8624}
8625
8626
8627#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
8628/**
8629 * INVEPT instruction execution worker.
8630 *
8631 * @returns Strict VBox status code.
8632 * @param pVCpu The cross context virtual CPU structure.
8633 * @param cbInstr The instruction length in bytes.
8634 * @param iEffSeg The segment of the invept descriptor.
8635 * @param GCPtrInveptDesc The address of invept descriptor.
8636 * @param u64InveptType The invalidation type.
8637 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8638 * NULL.
8639 *
8640 * @remarks Common VMX instruction checks are already expected to by the caller,
8641 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8642 */
8643IEM_STATIC VBOXSTRICTRC iemVmxInvept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInveptDesc,
8644 uint64_t u64InveptType, PCVMXVEXITINFO pExitInfo)
8645{
8646 /* Check if EPT is supported, otherwise raise #UD. */
8647 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEpt)
8648 return iemRaiseUndefinedOpcode(pVCpu);
8649
8650 /* Nested-guest intercept. */
8651 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8652 {
8653 if (pExitInfo)
8654 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8655 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVEPT, VMXINSTRID_NONE, cbInstr);
8656 }
8657
8658 /* CPL. */
8659 if (pVCpu->iem.s.uCpl != 0)
8660 {
8661 Log(("invept: CPL != 0 -> #GP(0)\n"));
8662 return iemRaiseGeneralProtectionFault0(pVCpu);
8663 }
8664
8665 /*
8666 * Validate INVEPT invalidation type.
8667 *
8668 * The instruction specifies exactly ONE of the supported invalidation types.
8669 *
8670 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
8671 * supported. In theory, it's possible for a CPU to not support flushing individual
8672 * addresses but all the other types or any other combination. We do not take any
8673 * shortcuts here by assuming the types we currently expose to the guest.
8674 */
8675 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
8676 bool const fInveptSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT);
8677 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
8678 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
8679
8680 bool afSupportedTypes[4];
8681 afSupportedTypes[0] = false;
8682 afSupportedTypes[1] = fTypeSingleCtx;
8683 afSupportedTypes[2] = fTypeAllCtx;
8684 afSupportedTypes[3] = false;
8685
8686 if ( fInveptSupported
8687 && !(u64InveptType & ~(uint64_t)VMX_INVEPT_VALID_MASK)
8688 && afSupportedTypes[u64InveptType & 3])
8689 { /* likely */ }
8690 else
8691 {
8692 Log(("invept: invalid/unsupported invvpid type %#x -> VMFail\n", u64InveptType));
8693 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_TypeInvalid;
8694 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType;
8695 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8696 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8697 return VINF_SUCCESS;
8698 }
8699
8700 /*
8701 * Fetch the invept descriptor from guest memory.
8702 */
8703 RTUINT128U uDesc;
8704 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInveptDesc);
8705 if (rcStrict == VINF_SUCCESS)
8706 {
8707 /*
8708 * Validate the descriptor.
8709 *
8710 * The Intel spec. does not explicit say the INVEPT instruction fails when reserved
8711 * bits in the descriptor are set, but it -does- for INVVPID. Until we test on real
8712 * hardware, it's assumed INVEPT behaves the same as INVVPID in this regard. It's
8713 * better to be strict in our emulation until proven otherwise.
8714 */
8715 if (uDesc.s.Hi)
8716 {
8717 Log(("invept: reserved bits set in invept descriptor %#RX64 -> VMFail\n", uDesc.s.Hi));
8718 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_DescRsvd;
8719 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi;
8720 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8721 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8722 return VINF_SUCCESS;
8723 }
8724
8725 /*
8726 * Flush TLB mappings based on the EPT type.
8727 */
8728 if (u64InveptType == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
8729 {
8730 uint64_t const GCPhysEptPtr = uDesc.s.Lo;
8731 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, GCPhysEptPtr, NULL /* enmDiag */);
8732 if (RT_SUCCESS(rc))
8733 { /* likely */ }
8734 else
8735 {
8736 Log(("invept: EPTP invalid %#RX64 -> VMFail\n", GCPhysEptPtr));
8737 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_EptpInvalid;
8738 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr;
8739 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
8740 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8741 return VINF_SUCCESS;
8742 }
8743 }
8744
8745 /** @todo PGM support for EPT tags? Currently just flush everything. */
8746 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
8747 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
8748 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
8749
8750 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8751 }
8752
8753 return rcStrict;
8754}
8755#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
8756
8757
8758/**
8759 * VMXON instruction execution worker.
8760 *
8761 * @returns Strict VBox status code.
8762 * @param pVCpu The cross context virtual CPU structure.
8763 * @param cbInstr The instruction length in bytes.
8764 * @param iEffSeg The effective segment register to use with @a
8765 * GCPtrVmxon.
8766 * @param GCPtrVmxon The linear address of the VMXON pointer.
8767 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8768 *
8769 * @remarks Common VMX instruction checks are already expected to by the caller,
8770 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8771 */
8772IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8773 PCVMXVEXITINFO pExitInfo)
8774{
8775 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8776 {
8777 /* CPL. */
8778 if (pVCpu->iem.s.uCpl == 0)
8779 { /* likely */ }
8780 else
8781 {
8782 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8783 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8784 return iemRaiseGeneralProtectionFault0(pVCpu);
8785 }
8786
8787 /* A20M (A20 Masked) mode. */
8788 if (PGMPhysIsA20Enabled(pVCpu))
8789 { /* likely */ }
8790 else
8791 {
8792 Log(("vmxon: A20M mode -> #GP(0)\n"));
8793 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8794 return iemRaiseGeneralProtectionFault0(pVCpu);
8795 }
8796
8797 /* CR0. */
8798 {
8799 /*
8800 * CR0 MB1 bits.
8801 *
8802 * We use VMX_V_CR0_FIXED0 below to ensure CR0.PE and CR0.PG are always set
8803 * while executing VMXON. CR0.PE and CR0.PG are only allowed to be clear
8804 * when the guest running in VMX non-root mode with unrestricted-guest control
8805 * enabled in the VMCS.
8806 */
8807 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
8808 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8809 { /* likely */ }
8810 else
8811 {
8812 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8813 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8814 return iemRaiseGeneralProtectionFault0(pVCpu);
8815 }
8816
8817 /* CR0 MBZ bits. */
8818 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8819 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8820 { /* likely */ }
8821 else
8822 {
8823 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8824 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8825 return iemRaiseGeneralProtectionFault0(pVCpu);
8826 }
8827 }
8828
8829 /* CR4. */
8830 {
8831 /* CR4 MB1 bits. */
8832 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8833 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8834 { /* likely */ }
8835 else
8836 {
8837 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8838 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8839 return iemRaiseGeneralProtectionFault0(pVCpu);
8840 }
8841
8842 /* CR4 MBZ bits. */
8843 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8844 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8845 { /* likely */ }
8846 else
8847 {
8848 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8849 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8850 return iemRaiseGeneralProtectionFault0(pVCpu);
8851 }
8852 }
8853
8854 /* Feature control MSR's LOCK and VMXON bits. */
8855 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
8856 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8857 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8858 { /* likely */ }
8859 else
8860 {
8861 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8862 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8863 return iemRaiseGeneralProtectionFault0(pVCpu);
8864 }
8865
8866 /* Get the VMXON pointer from the location specified by the source memory operand. */
8867 RTGCPHYS GCPhysVmxon;
8868 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8869 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8870 { /* likely */ }
8871 else
8872 {
8873 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8874 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8875 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
8876 return rcStrict;
8877 }
8878
8879 /* VMXON region pointer alignment. */
8880 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8881 { /* likely */ }
8882 else
8883 {
8884 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8885 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8886 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8887 iemVmxVmFailInvalid(pVCpu);
8888 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8889 return VINF_SUCCESS;
8890 }
8891
8892 /* VMXON physical-address width limits. */
8893 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8894 { /* likely */ }
8895 else
8896 {
8897 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8898 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8899 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8900 iemVmxVmFailInvalid(pVCpu);
8901 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8902 return VINF_SUCCESS;
8903 }
8904
8905 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8906 restriction imposed by our implementation. */
8907 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8908 { /* likely */ }
8909 else
8910 {
8911 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8912 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8913 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
8914 iemVmxVmFailInvalid(pVCpu);
8915 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8916 return VINF_SUCCESS;
8917 }
8918
8919 /* Read the VMCS revision ID from the VMXON region. */
8920 VMXVMCSREVID VmcsRevId;
8921 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8922 if (RT_SUCCESS(rc))
8923 { /* likely */ }
8924 else
8925 {
8926 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8927 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8928 return rc;
8929 }
8930
8931 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8932 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8933 { /* likely */ }
8934 else
8935 {
8936 /* Revision ID mismatch. */
8937 if (!VmcsRevId.n.fIsShadowVmcs)
8938 {
8939 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8940 VmcsRevId.n.u31RevisionId));
8941 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8942 iemVmxVmFailInvalid(pVCpu);
8943 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8944 return VINF_SUCCESS;
8945 }
8946
8947 /* Shadow VMCS disallowed. */
8948 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8949 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8950 iemVmxVmFailInvalid(pVCpu);
8951 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8952 return VINF_SUCCESS;
8953 }
8954
8955 /*
8956 * Record that we're in VMX operation, block INIT, block and disable A20M.
8957 */
8958 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8959 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8960 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8961
8962 /* Clear address-range monitoring. */
8963 EMMonitorWaitClear(pVCpu);
8964 /** @todo NSTVMX: Intel PT. */
8965
8966 iemVmxVmSucceed(pVCpu);
8967 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8968 return VINF_SUCCESS;
8969 }
8970 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8971 {
8972 /* Nested-guest intercept. */
8973 if (pExitInfo)
8974 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8975 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8976 }
8977
8978 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8979
8980 /* CPL. */
8981 if (pVCpu->iem.s.uCpl > 0)
8982 {
8983 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8984 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8985 return iemRaiseGeneralProtectionFault0(pVCpu);
8986 }
8987
8988 /* VMXON when already in VMX root mode. */
8989 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8990 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8991 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8992 return VINF_SUCCESS;
8993}
8994
8995
8996/**
8997 * Implements 'VMXOFF'.
8998 *
8999 * @remarks Common VMX instruction checks are already expected to by the caller,
9000 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9001 */
9002IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
9003{
9004 /* Nested-guest intercept. */
9005 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9006 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9007
9008 /* CPL. */
9009 if (pVCpu->iem.s.uCpl == 0)
9010 { /* likely */ }
9011 else
9012 {
9013 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9014 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9015 return iemRaiseGeneralProtectionFault0(pVCpu);
9016 }
9017
9018 /* Dual monitor treatment of SMIs and SMM. */
9019 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9020 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9021 { /* likely */ }
9022 else
9023 {
9024 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9025 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9026 return VINF_SUCCESS;
9027 }
9028
9029 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9030 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9031 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9032
9033 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9034 { /** @todo NSTVMX: Unblock SMI. */ }
9035
9036 EMMonitorWaitClear(pVCpu);
9037 /** @todo NSTVMX: Unblock and enable A20M. */
9038
9039 iemVmxVmSucceed(pVCpu);
9040 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9041 return VINF_SUCCESS;
9042}
9043
9044
9045/**
9046 * Implements 'VMXON'.
9047 */
9048IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9049{
9050 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9051}
9052
9053
9054/**
9055 * Implements 'VMLAUNCH'.
9056 */
9057IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9058{
9059 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9060}
9061
9062
9063/**
9064 * Implements 'VMRESUME'.
9065 */
9066IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9067{
9068 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9069}
9070
9071
9072/**
9073 * Implements 'VMPTRLD'.
9074 */
9075IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9076{
9077 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9078}
9079
9080
9081/**
9082 * Implements 'VMPTRST'.
9083 */
9084IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9085{
9086 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9087}
9088
9089
9090/**
9091 * Implements 'VMCLEAR'.
9092 */
9093IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9094{
9095 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9096}
9097
9098
9099/**
9100 * Implements 'VMWRITE' register.
9101 */
9102IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9103{
9104 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9105}
9106
9107
9108/**
9109 * Implements 'VMWRITE' memory.
9110 */
9111IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9112{
9113 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9114}
9115
9116
9117/**
9118 * Implements 'VMREAD' register (64-bit).
9119 */
9120IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9121{
9122 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9123}
9124
9125
9126/**
9127 * Implements 'VMREAD' register (32-bit).
9128 */
9129IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
9130{
9131 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
9132}
9133
9134
9135/**
9136 * Implements 'VMREAD' memory, 64-bit register.
9137 */
9138IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9139{
9140 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9141}
9142
9143
9144/**
9145 * Implements 'VMREAD' memory, 32-bit register.
9146 */
9147IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9148{
9149 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9150}
9151
9152
9153/**
9154 * Implements 'INVVPID'.
9155 */
9156IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9157{
9158 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9159}
9160
9161
9162#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9163/**
9164 * Implements 'INVEPT'.
9165 */
9166IEM_CIMPL_DEF_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType)
9167{
9168 return iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType, NULL /* pExitInfo */);
9169}
9170#endif
9171
9172
9173/**
9174 * Implements VMX's implementation of PAUSE.
9175 */
9176IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9177{
9178 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9179 {
9180 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9181 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9182 return rcStrict;
9183 }
9184
9185 /*
9186 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9187 * a VM-exit, the instruction operates normally.
9188 */
9189 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9190 return VINF_SUCCESS;
9191}
9192
9193#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9194
9195
9196/**
9197 * Implements 'VMCALL'.
9198 */
9199IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9200{
9201#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9202 /* Nested-guest intercept. */
9203 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9204 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9205#endif
9206
9207 /* Join forces with vmmcall. */
9208 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9209}
9210
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