VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp@ 99051

Last change on this file since 99051 was 98797, checked in by vboxsync, 21 months ago

VMM/IEM: Corrected bug in 32-bit vmread to register emulation where the clearing of the high register dword was made in unreachable code. Found after re-enabling warning. bugref:10368
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1/* $Id: IEMAllCImplVmxInstr.cpp 98797 2023-03-01 00:23:26Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_IEM_VMX
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/iem.h>
35#include <VBox/vmm/apic.h>
36#include <VBox/vmm/cpum.h>
37#include <VBox/vmm/dbgf.h>
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/gim.h>
40#include <VBox/vmm/hm.h>
41#include <VBox/vmm/pgm.h>
42#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
43# include <VBox/vmm/hmvmxinline.h>
44#endif
45#include <VBox/vmm/tm.h>
46#include "IEMInternal.h"
47#include <VBox/vmm/vmcc.h>
48#include <VBox/log.h>
49#include <VBox/err.h>
50#include <VBox/param.h>
51#include <VBox/disopcode.h>
52#include <iprt/asm-math.h>
53#include <iprt/assert.h>
54#include <iprt/string.h>
55#include <iprt/x86.h>
56
57#include "IEMInline.h"
58
59
60/*********************************************************************************************************************************
61* Defined Constants And Macros *
62*********************************************************************************************************************************/
63#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
64/**
65 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
66 * relative offsets.
67 */
68# ifdef IEM_WITH_CODE_TLB /** @todo IEM TLB */
69# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { a_bModRm = 0; RT_NOREF(a_offModRm); } while (0)
70# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { a_bSib = 0; RT_NOREF(a_offSib); } while (0)
71# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
72# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
73# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
75# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
76# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
77# if 0
78# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
79# endif
80# else /* !IEM_WITH_CODE_TLB */
81# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
82 do \
83 { \
84 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
86 } while (0)
87
88# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
89
90# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
91 do \
92 { \
93 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
94 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
95 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
96 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
97 } while (0)
98
99# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
100 do \
101 { \
102 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
103 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
104 } while (0)
105
106# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
107 do \
108 { \
109 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
110 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
111 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
112 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
113 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
114 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
115 } while (0)
116
117# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
118 do \
119 { \
120 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
121 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
122 } while (0)
123
124# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
125 do \
126 { \
127 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
128 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
129 } while (0)
130
131# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
132 do \
133 { \
134 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
135 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
136 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
137 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
138 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
139 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
140 } while (0)
141# endif /* !IEM_WITH_CODE_TLB */
142
143/** Check for VMX instructions requiring to be in VMX operation.
144 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
145# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
146 do \
147 { \
148 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
149 { /* likely */ } \
150 else \
151 { \
152 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
153 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
154 return iemRaiseUndefinedOpcode(a_pVCpu); \
155 } \
156 } while (0)
157
158/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
159# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
160 do \
161 { \
162 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
163 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
164 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
165 return VERR_VMX_VMENTRY_FAILED; \
166 } while (0)
167
168/** Marks a VM-exit failure with a diagnostic reason and logs. */
169# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
170 do \
171 { \
172 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
173 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
174 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
175 } while (0)
176
177/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
178# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
179 do \
180 { \
181 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
182 return VERR_VMX_VMEXIT_FAILED; \
183 } while (0)
184
185
186/*********************************************************************************************************************************
187* Global Variables *
188*********************************************************************************************************************************/
189/** @todo NSTVMX: The following VM-exit intercepts are pending:
190 * VMX_EXIT_IO_SMI
191 * VMX_EXIT_SMI
192 * VMX_EXIT_GETSEC
193 * VMX_EXIT_RSM
194 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
195 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
196 * VMX_EXIT_RDRAND
197 * VMX_EXIT_VMFUNC
198 * VMX_EXIT_ENCLS
199 * VMX_EXIT_RDSEED
200 * VMX_EXIT_PML_FULL
201 * VMX_EXIT_XSAVES
202 * VMX_EXIT_XRSTORS
203 */
204/**
205 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
206 *
207 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
208 * second dimension is the Index, see VMXVMCSFIELD.
209 */
210uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
211{
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u16HlatPrefixSize),
218 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
219 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
220 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
221 /* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
222 },
223 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
224 {
225 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
227 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
228 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
229 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
230 },
231 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
232 {
233 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
234 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
235 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
236 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
237 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
238 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
239 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
240 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
241 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
242 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
243 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
244 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
245 /* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
246 /* 34 */ UINT16_MAX
247 },
248 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
249 {
250 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
251 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
252 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
253 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
254 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
255 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
256 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
257 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
258 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
259 /* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
260 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
261 },
262 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
263 {
264 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
265 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
266 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
267 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
268 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
269 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
270 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
271 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
272 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
273 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
274 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
275 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
276 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
277 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
278 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
279 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
280 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
281 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
282 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
283 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
284 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
285 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
286 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
287 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
288 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
289 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
290 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
291 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap),
292 /* 28 */ UINT16_MAX,
293 /* 29 */ UINT16_MAX,
294 /* 30 */ UINT16_MAX,
295 /* 31 */ RT_UOFFSETOF(VMXVVMCS, u64PconfigExitBitmap),
296 /* 32 */ RT_UOFFSETOF(VMXVVMCS, u64HlatPtr),
297 /* 33 */ UINT16_MAX,
298 /* 34 */ RT_UOFFSETOF(VMXVVMCS, u64ExitCtls2)
299 },
300 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
301 {
302 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
303 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
304 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
307 /* 33-34*/ UINT16_MAX, UINT16_MAX
308 },
309 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
310 {
311 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
312 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
313 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
314 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
315 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
316 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
317 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
318 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
319 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
320 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
321 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
322 /* 11 */ UINT16_MAX,
323 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
324 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
325 /* 21-28 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
326 /* 29-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
327 },
328 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
329 {
330 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
331 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
332 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
333 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
334 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
337 /* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
338 },
339 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
340 {
341 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
342 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
343 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
344 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
345 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
346 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
347 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
348 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
349 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
350 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
351 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
352 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
353 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
354 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
355 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
356 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
357 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
358 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
359 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
360 /* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
361 /* 34 */ UINT16_MAX
362 },
363 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
364 {
365 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
366 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
367 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
368 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
369 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
370 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
371 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
372 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
373 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
374 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
375 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
376 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
377 },
378 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
379 {
380 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
381 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
382 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
383 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
384 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
385 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
386 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
387 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
388 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
389 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
390 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
391 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
392 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
393 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
394 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
395 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
396 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
397 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
398 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
399 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
400 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
401 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
402 /* 22 */ UINT16_MAX,
403 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
404 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
405 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
406 },
407 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
408 {
409 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
410 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
411 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
412 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
413 /* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
414 /* 33-34 */ UINT16_MAX, UINT16_MAX
415 },
416 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
417 {
418 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
419 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
420 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
421 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
422 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
423 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
424 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
425 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
426 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
427 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
428 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
429 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
430 },
431 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
432 {
433 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
434 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
435 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
436 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
437 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
438 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
439 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
440 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
441 /* 22-29 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
442 /* 30-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
443 },
444 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
445 {
446 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
447 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
448 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
449 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
450 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
451 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
452 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
453 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
454 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
455 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
456 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
457 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
458 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
459 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
460 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
461 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
462 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
463 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
464 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
465 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
466 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
467 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
468 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
469 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
470 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
471 },
472 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
473 {
474 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
475 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
476 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
477 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
478 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
479 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
480 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
481 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
482 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
483 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
484 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
485 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
486 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
487 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
488 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
489 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
490 /* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
491 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
492 }
493};
494
495
496/**
497 * Gets a host selector from the VMCS.
498 *
499 * @param pVmcs Pointer to the virtual VMCS.
500 * @param iSelReg The index of the segment register (X86_SREG_XXX).
501 */
502DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
503{
504 Assert(iSegReg < X86_SREG_COUNT);
505 RTSEL HostSel;
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 HostSel = *(uint16_t *)pbField;
515 return HostSel;
516}
517
518
519/**
520 * Sets a guest segment register in the VMCS.
521 *
522 * @param pVmcs Pointer to the virtual VMCS.
523 * @param iSegReg The index of the segment register (X86_SREG_XXX).
524 * @param pSelReg Pointer to the segment register.
525 */
526static void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg) RT_NOEXCEPT
527{
528 Assert(pSelReg);
529 Assert(iSegReg < X86_SREG_COUNT);
530
531 /* Selector. */
532 {
533 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
534 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
535 uint8_t const uWidthType = (uWidth << 2) | uType;
536 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
537 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
538 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
539 uint8_t *pbVmcs = (uint8_t *)pVmcs;
540 uint8_t *pbField = pbVmcs + offField;
541 *(uint16_t *)pbField = pSelReg->Sel;
542 }
543
544 /* Limit. */
545 {
546 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
547 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
548 uint8_t const uWidthType = (uWidth << 2) | uType;
549 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
550 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
551 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
552 uint8_t *pbVmcs = (uint8_t *)pVmcs;
553 uint8_t *pbField = pbVmcs + offField;
554 *(uint32_t *)pbField = pSelReg->u32Limit;
555 }
556
557 /* Base. */
558 {
559 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
560 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
561 uint8_t const uWidthType = (uWidth << 2) | uType;
562 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
563 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
564 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
565 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
566 uint8_t const *pbField = pbVmcs + offField;
567 *(uint64_t *)pbField = pSelReg->u64Base;
568 }
569
570 /* Attributes. */
571 {
572 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
573 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
574 | X86DESCATTR_UNUSABLE;
575 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
576 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
577 uint8_t const uWidthType = (uWidth << 2) | uType;
578 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
579 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
580 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
581 uint8_t *pbVmcs = (uint8_t *)pVmcs;
582 uint8_t *pbField = pbVmcs + offField;
583 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
584 }
585}
586
587
588/**
589 * Gets a guest segment register from the VMCS.
590 *
591 * @returns VBox status code.
592 * @param pVmcs Pointer to the virtual VMCS.
593 * @param iSegReg The index of the segment register (X86_SREG_XXX).
594 * @param pSelReg Where to store the segment register (only updated when
595 * VINF_SUCCESS is returned).
596 *
597 * @remarks Warning! This does not validate the contents of the retrieved segment
598 * register.
599 */
600static int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg) RT_NOEXCEPT
601{
602 Assert(pSelReg);
603 Assert(iSegReg < X86_SREG_COUNT);
604
605 /* Selector. */
606 uint16_t u16Sel;
607 {
608 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
609 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
610 uint8_t const uWidthType = (uWidth << 2) | uType;
611 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
612 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
613 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
614 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
615 uint8_t const *pbField = pbVmcs + offField;
616 u16Sel = *(uint16_t *)pbField;
617 }
618
619 /* Limit. */
620 uint32_t u32Limit;
621 {
622 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
623 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
624 uint8_t const uWidthType = (uWidth << 2) | uType;
625 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
626 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
627 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
628 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
629 uint8_t const *pbField = pbVmcs + offField;
630 u32Limit = *(uint32_t *)pbField;
631 }
632
633 /* Base. */
634 uint64_t u64Base;
635 {
636 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
637 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
638 uint8_t const uWidthType = (uWidth << 2) | uType;
639 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
640 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
641 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
642 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
643 uint8_t const *pbField = pbVmcs + offField;
644 u64Base = *(uint64_t *)pbField;
645 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
646 }
647
648 /* Attributes. */
649 uint32_t u32Attr;
650 {
651 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
652 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
653 uint8_t const uWidthType = (uWidth << 2) | uType;
654 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
655 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
656 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
657 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
658 uint8_t const *pbField = pbVmcs + offField;
659 u32Attr = *(uint32_t *)pbField;
660 }
661
662 pSelReg->Sel = u16Sel;
663 pSelReg->ValidSel = u16Sel;
664 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
665 pSelReg->u32Limit = u32Limit;
666 pSelReg->u64Base = u64Base;
667 pSelReg->Attr.u = u32Attr;
668 return VINF_SUCCESS;
669}
670
671
672/**
673 * Converts an IEM exception event type to a VMX event type.
674 *
675 * @returns The VMX event type.
676 * @param uVector The interrupt / exception vector.
677 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
678 */
679DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
680{
681 /* Paranoia (callers may use these interchangeably). */
682 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
683 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
684 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
685 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
686 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
687 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
688 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
689 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
690 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
691 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
692 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
693 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
694
695 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
696 {
697 if (uVector == X86_XCPT_NMI)
698 return VMX_EXIT_INT_INFO_TYPE_NMI;
699 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
700 }
701
702 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
703 {
704 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
705 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
706 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
707 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
708 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
709 }
710
711 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
712 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
713}
714
715
716/**
717 * Determines whether the guest is using PAE paging given the VMCS.
718 *
719 * @returns @c true if PAE paging mode is used, @c false otherwise.
720 * @param pVmcs Pointer to the virtual VMCS.
721 *
722 * @warning Only use this prior to switching the guest-CPU state with the
723 * nested-guest CPU state!
724 */
725DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
726{
727 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
728 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
729 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
730}
731
732
733/**
734 * Sets the Exit qualification VMCS field.
735 *
736 * @param pVCpu The cross context virtual CPU structure.
737 * @param u64ExitQual The Exit qualification.
738 */
739DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
740{
741 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
742}
743
744
745/**
746 * Sets the VM-exit interruption information field.
747 *
748 * @param pVCpu The cross context virtual CPU structure.
749 * @param uExitIntInfo The VM-exit interruption information.
750 */
751DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
752{
753 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
754}
755
756
757/**
758 * Sets the VM-exit interruption error code.
759 *
760 * @param pVCpu The cross context virtual CPU structure.
761 * @param uErrCode The error code.
762 */
763DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
764{
765 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
766}
767
768
769/**
770 * Sets the IDT-vectoring information field.
771 *
772 * @param pVCpu The cross context virtual CPU structure.
773 * @param uIdtVectorInfo The IDT-vectoring information.
774 */
775DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
776{
777 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
778}
779
780
781/**
782 * Sets the IDT-vectoring error code field.
783 *
784 * @param pVCpu The cross context virtual CPU structure.
785 * @param uErrCode The error code.
786 */
787DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
788{
789 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
790}
791
792
793/**
794 * Sets the VM-exit guest-linear address VMCS field.
795 *
796 * @param pVCpu The cross context virtual CPU structure.
797 * @param uGuestLinearAddr The VM-exit guest-linear address.
798 */
799DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
800{
801 /* Bits 63:32 of guest-linear address MBZ if the guest isn't in long mode prior to the VM-exit. */
802 Assert(CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)) || !(uGuestLinearAddr & UINT64_C(0xffffffff00000000)));
803 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
804}
805
806
807/**
808 * Sets the VM-exit guest-physical address VMCS field.
809 *
810 * @param pVCpu The cross context virtual CPU structure.
811 * @param uGuestPhysAddr The VM-exit guest-physical address.
812 */
813DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
814{
815 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
816}
817
818
819/**
820 * Sets the VM-exit instruction length VMCS field.
821 *
822 * @param pVCpu The cross context virtual CPU structure.
823 * @param cbInstr The VM-exit instruction length in bytes.
824 *
825 * @remarks Callers may clear this field to 0. Hence, this function does not check
826 * the validity of the instruction length.
827 */
828DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
829{
830 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
831}
832
833
834/**
835 * Sets the VM-exit instruction info. VMCS field.
836 *
837 * @param pVCpu The cross context virtual CPU structure.
838 * @param uExitInstrInfo The VM-exit instruction information.
839 */
840DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
841{
842 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
843}
844
845
846/**
847 * Sets the guest pending-debug exceptions field.
848 *
849 * @param pVCpu The cross context virtual CPU structure.
850 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
851 */
852DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
853{
854 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
855 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
856}
857
858
859/**
860 * Implements VMSucceed for VMX instruction success.
861 *
862 * @param pVCpu The cross context virtual CPU structure.
863 */
864DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
865{
866 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
867}
868
869
870/**
871 * Implements VMFailInvalid for VMX instruction failure.
872 *
873 * @param pVCpu The cross context virtual CPU structure.
874 */
875DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
876{
877 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
878}
879
880
881/**
882 * Implements VMFail for VMX instruction failure.
883 *
884 * @param pVCpu The cross context virtual CPU structure.
885 * @param enmInsErr The VM instruction error.
886 */
887DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
888{
889 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
890}
891
892
893/**
894 * Checks if the given auto-load/store MSR area count is valid for the
895 * implementation.
896 *
897 * @returns @c true if it's within the valid limit, @c false otherwise.
898 * @param pVCpu The cross context virtual CPU structure.
899 * @param uMsrCount The MSR area count to check.
900 */
901DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
902{
903 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
904 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
905 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
906 if (uMsrCount <= cMaxSupportedMsrs)
907 return true;
908 return false;
909}
910
911
912/**
913 * Flushes the current VMCS contents back to guest memory.
914 *
915 * @returns VBox status code.
916 * @param pVCpu The cross context virtual CPU structure.
917 */
918DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
919{
920 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
921 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
922 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
923 return rc;
924}
925
926
927/**
928 * Populates the current VMCS contents from guest memory.
929 *
930 * @returns VBox status code.
931 * @param pVCpu The cross context virtual CPU structure.
932 */
933DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
934{
935 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
936 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
937 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
938 return rc;
939}
940
941
942/**
943 * Gets the instruction diagnostic for segment base checks during VM-entry of a
944 * nested-guest.
945 *
946 * @param iSegReg The segment index (X86_SREG_XXX).
947 */
948static VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg) RT_NOEXCEPT
949{
950 switch (iSegReg)
951 {
952 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
953 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
954 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
955 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
956 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
957 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
958 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
959 }
960}
961
962
963/**
964 * Gets the instruction diagnostic for segment base checks during VM-entry of a
965 * nested-guest that is in Virtual-8086 mode.
966 *
967 * @param iSegReg The segment index (X86_SREG_XXX).
968 */
969static VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg) RT_NOEXCEPT
970{
971 switch (iSegReg)
972 {
973 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
974 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
975 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
976 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
977 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
978 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
979 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
980 }
981}
982
983
984/**
985 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
986 * nested-guest that is in Virtual-8086 mode.
987 *
988 * @param iSegReg The segment index (X86_SREG_XXX).
989 */
990static VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg) RT_NOEXCEPT
991{
992 switch (iSegReg)
993 {
994 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
995 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
996 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
997 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
998 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
999 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1000 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1001 }
1002}
1003
1004
1005/**
1006 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1007 * nested-guest that is in Virtual-8086 mode.
1008 *
1009 * @param iSegReg The segment index (X86_SREG_XXX).
1010 */
1011static VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg) RT_NOEXCEPT
1012{
1013 switch (iSegReg)
1014 {
1015 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1016 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1017 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1018 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1019 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1020 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1021 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1022 }
1023}
1024
1025
1026/**
1027 * Gets the instruction diagnostic for segment attributes reserved bits failure
1028 * during VM-entry of a nested-guest.
1029 *
1030 * @param iSegReg The segment index (X86_SREG_XXX).
1031 */
1032static VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg) RT_NOEXCEPT
1033{
1034 switch (iSegReg)
1035 {
1036 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1037 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1038 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1039 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1040 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1041 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1042 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1043 }
1044}
1045
1046
1047/**
1048 * Gets the instruction diagnostic for segment attributes descriptor-type
1049 * (code/segment or system) failure during VM-entry of a nested-guest.
1050 *
1051 * @param iSegReg The segment index (X86_SREG_XXX).
1052 */
1053static VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg) RT_NOEXCEPT
1054{
1055 switch (iSegReg)
1056 {
1057 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1058 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1059 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1060 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1061 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1062 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1063 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1064 }
1065}
1066
1067
1068/**
1069 * Gets the instruction diagnostic for segment attributes descriptor-type
1070 * (code/segment or system) failure during VM-entry of a nested-guest.
1071 *
1072 * @param iSegReg The segment index (X86_SREG_XXX).
1073 */
1074static VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg) RT_NOEXCEPT
1075{
1076 switch (iSegReg)
1077 {
1078 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1079 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1080 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1081 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1082 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1083 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1084 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1085 }
1086}
1087
1088
1089/**
1090 * Gets the instruction diagnostic for segment attribute granularity failure during
1091 * VM-entry of a nested-guest.
1092 *
1093 * @param iSegReg The segment index (X86_SREG_XXX).
1094 */
1095static VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg) RT_NOEXCEPT
1096{
1097 switch (iSegReg)
1098 {
1099 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1100 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1101 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1102 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1103 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1104 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1105 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1106 }
1107}
1108
1109/**
1110 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1111 * VM-entry of a nested-guest.
1112 *
1113 * @param iSegReg The segment index (X86_SREG_XXX).
1114 */
1115static VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg) RT_NOEXCEPT
1116{
1117 switch (iSegReg)
1118 {
1119 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1120 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1121 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1122 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1123 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1124 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1125 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1126 }
1127}
1128
1129
1130/**
1131 * Gets the instruction diagnostic for segment attribute type accessed failure
1132 * during VM-entry of a nested-guest.
1133 *
1134 * @param iSegReg The segment index (X86_SREG_XXX).
1135 */
1136static VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg) RT_NOEXCEPT
1137{
1138 switch (iSegReg)
1139 {
1140 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1141 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1142 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1143 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1144 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1145 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1146 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1147 }
1148}
1149
1150
1151/**
1152 * Saves the guest control registers, debug registers and some MSRs are part of
1153 * VM-exit.
1154 *
1155 * @param pVCpu The cross context virtual CPU structure.
1156 */
1157static void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1158{
1159 /*
1160 * Saves the guest control registers, debug registers and some MSRs.
1161 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1162 */
1163 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1164
1165 /* Save control registers. */
1166 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1167 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1168 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1169
1170 /* Save SYSENTER CS, ESP, EIP. */
1171 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1172 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1173 {
1174 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1175 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1176 }
1177 else
1178 {
1179 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1180 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1181 }
1182
1183 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1184 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1185 {
1186 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1187 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1188 }
1189
1190 /* Save PAT MSR. */
1191 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1192 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1193
1194 /* Save EFER MSR. */
1195 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1196 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1197
1198 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1199 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1200
1201 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1202}
1203
1204
1205/**
1206 * Saves the guest force-flags in preparation of entering the nested-guest.
1207 *
1208 * @param pVCpu The cross context virtual CPU structure.
1209 */
1210static void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1211{
1212 /* We shouldn't be called multiple times during VM-entry. */
1213 Assert(pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit == 0);
1214
1215 /* MTF should not be set outside VMX non-root mode. */
1216 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1217
1218 /*
1219 * Preserve the required force-flags.
1220 *
1221 * We cache and clear force-flags that would affect the execution of the
1222 * nested-guest. Cached flags are then restored while returning to the guest
1223 * if necessary.
1224 *
1225 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1226 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1227 * instruction. Interrupt inhibition for any nested-guest instruction
1228 * is supplied by the guest-interruptibility state VMCS field and will
1229 * be set up as part of loading the guest state. Technically
1230 * blocking-by-STI is possible with VMLAUNCH/VMRESUME but we currently
1231 * disallow it since we can't distinguish it from blocking-by-MovSS
1232 * and no nested-hypervisor we care about uses STI immediately
1233 * followed by VMLAUNCH/VMRESUME.
1234 *
1235 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1236 * successful VM-entry (due to invalid guest-state) need to continue
1237 * blocking NMIs if it was in effect before VM-entry.
1238 *
1239 * - MTF need not be preserved as it's used only in VMX non-root mode and
1240 * is supplied through the VM-execution controls.
1241 *
1242 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1243 * we will be able to generate interrupts that may cause VM-exits for
1244 * the nested-guest.
1245 */
1246 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_INHIBIT_NMI;
1247}
1248
1249
1250/**
1251 * Restores the guest force-flags in preparation of exiting the nested-guest.
1252 *
1253 * @param pVCpu The cross context virtual CPU structure.
1254 */
1255static void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1256{
1257 /** @todo r=bird: why aren't we clearing the nested guest flags first here?
1258 * If there is some other code doing that already, it would be great
1259 * to point to it here... */
1260 pVCpu->cpum.GstCtx.eflags.uBoth |= pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit;
1261 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = 0;
1262}
1263
1264
1265/**
1266 * Performs the VMX transition to/from VMX non-root mode.
1267 *
1268 * @param pVCpu The cross context virtual CPU structure.
1269*/
1270static int iemVmxTransition(PVMCPUCC pVCpu) RT_NOEXCEPT
1271{
1272 /*
1273 * Inform PGM about paging mode changes.
1274 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1275 * see comment in iemMemPageTranslateAndCheckAccess().
1276 */
1277 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1278 true /* fForce */);
1279 if (RT_SUCCESS(rc))
1280 { /* likely */ }
1281 else
1282 return rc;
1283
1284 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1285 IEMTlbInvalidateAll(pVCpu);
1286
1287 /* Inform CPUM (recompiler), can later be removed. */
1288 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1289
1290 /* Re-initialize IEM cache/state after the drastic mode switch. */
1291 iemReInitExec(pVCpu);
1292 return rc;
1293}
1294
1295
1296/**
1297 * Calculates the current VMX-preemption timer value.
1298 *
1299 * @returns The current VMX-preemption timer value.
1300 * @param pVCpu The cross context virtual CPU structure.
1301 */
1302static uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
1303{
1304 /*
1305 * Assume the following:
1306 * PreemptTimerShift = 5
1307 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1308 * EntryTick = 50000 (TSC at time of VM-entry)
1309 *
1310 * CurTick Delta PreemptTimerVal
1311 * ----------------------------------
1312 * 60000 10000 2
1313 * 80000 30000 1
1314 * 90000 40000 0 -> VM-exit.
1315 *
1316 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1317 * The saved VMX-preemption timer value is calculated as follows:
1318 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1319 * E.g.:
1320 * Delta = 10000
1321 * Tmp = 10000 / (2 * 10000) = 0.5
1322 * NewPt = 2 - 0.5 = 2
1323 * Delta = 30000
1324 * Tmp = 30000 / (2 * 10000) = 1.5
1325 * NewPt = 2 - 1.5 = 1
1326 * Delta = 40000
1327 * Tmp = 40000 / 20000 = 2
1328 * NewPt = 2 - 2 = 0
1329 */
1330 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1331 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1332 if (uVmcsPreemptVal > 0)
1333 {
1334 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1335 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1336 uint64_t const uDelta = uCurTick - uEntryTick;
1337 uint32_t const uPreemptTimer = uVmcsPreemptVal
1338 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1339 return uPreemptTimer;
1340 }
1341 return 0;
1342}
1343
1344
1345/**
1346 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1347 *
1348 * @param pVCpu The cross context virtual CPU structure.
1349 */
1350static void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1351{
1352 /*
1353 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1354 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1355 */
1356 /* CS, SS, ES, DS, FS, GS. */
1357 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1358 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1359 {
1360 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1361 if (!pSelReg->Attr.n.u1Unusable)
1362 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1363 else
1364 {
1365 /*
1366 * For unusable segments the attributes are undefined except for CS and SS.
1367 * For the rest we don't bother preserving anything but the unusable bit.
1368 */
1369 switch (iSegReg)
1370 {
1371 case X86_SREG_CS:
1372 pVmcs->GuestCs = pSelReg->Sel;
1373 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1374 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1375 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1376 | X86DESCATTR_UNUSABLE);
1377 break;
1378
1379 case X86_SREG_SS:
1380 pVmcs->GuestSs = pSelReg->Sel;
1381 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1382 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1383 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1384 break;
1385
1386 case X86_SREG_DS:
1387 pVmcs->GuestDs = pSelReg->Sel;
1388 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1389 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1390 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1391 break;
1392
1393 case X86_SREG_ES:
1394 pVmcs->GuestEs = pSelReg->Sel;
1395 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1396 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1397 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1398 break;
1399
1400 case X86_SREG_FS:
1401 pVmcs->GuestFs = pSelReg->Sel;
1402 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1403 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1404 break;
1405
1406 case X86_SREG_GS:
1407 pVmcs->GuestGs = pSelReg->Sel;
1408 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1409 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1410 break;
1411 }
1412 }
1413 }
1414
1415 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1416 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1417 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1418 | X86DESCATTR_UNUSABLE;
1419 /* LDTR. */
1420 {
1421 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1422 pVmcs->GuestLdtr = pSelReg->Sel;
1423 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1424 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1425 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1426 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1427 }
1428
1429 /* TR. */
1430 {
1431 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1432 pVmcs->GuestTr = pSelReg->Sel;
1433 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1434 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1435 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1436 }
1437
1438 /* GDTR. */
1439 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1440 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1441
1442 /* IDTR. */
1443 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1444 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1445}
1446
1447
1448/**
1449 * Saves guest non-register state as part of VM-exit.
1450 *
1451 * @param pVCpu The cross context virtual CPU structure.
1452 * @param uExitReason The VM-exit reason.
1453 */
1454static void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1455{
1456 /*
1457 * Save guest non-register state.
1458 * See Intel spec. 27.3.4 "Saving Non-Register State".
1459 */
1460 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1461
1462 /*
1463 * Activity state.
1464 * Most VM-exits will occur in the active state. However, if the first instruction
1465 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1466 * the VM-exit will be from the HLT activity state.
1467 *
1468 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1469 */
1470 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1471 * not? */
1472 EMSTATE const enmActivityState = EMGetState(pVCpu);
1473 switch (enmActivityState)
1474 {
1475 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1476 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1477 }
1478
1479 /*
1480 * Interruptibility-state.
1481 */
1482 /* NMI. */
1483 pVmcs->u32GuestIntrState = 0;
1484 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1485 {
1486 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1487 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1488 }
1489 else
1490 {
1491 if (CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx))
1492 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1493 }
1494
1495 /* Blocking-by-STI. */
1496 if (!CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx))
1497 { /* probable */}
1498 else
1499 {
1500 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1501 * currently. */
1502 if (pVCpu->cpum.GstCtx.rip == pVCpu->cpum.GstCtx.uRipInhibitInt)
1503 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI; /** @todo r=bird: Why the STI one? MOVSS seems to block more and the one to use. */
1504
1505 /* Clear inhibition unconditionally since we've ensured it isn't set prior to executing VMLAUNCH/VMRESUME. */
1506 CPUMClearInterruptShadow(&pVCpu->cpum.GstCtx);
1507 }
1508 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1509
1510 /*
1511 * Pending debug exceptions.
1512 *
1513 * For VM-exits where it is not applicable, we can safely zero out the field.
1514 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1515 */
1516 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1517 && uExitReason != VMX_EXIT_SMI
1518 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1519 && !VMXIsVmexitTrapLike(uExitReason))
1520 {
1521 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1522 * block-by-MovSS is in effect. */
1523 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1524 }
1525
1526 /*
1527 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1528 *
1529 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1530 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1531 */
1532 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1533 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1534 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1535
1536 /*
1537 * Save the guest PAE PDPTEs.
1538 */
1539 if ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
1540 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
1541 {
1542 /*
1543 * Without EPT or when the nested-guest is not using PAE paging, the values saved
1544 * in the VMCS during VM-exit are undefined. We zero them here for consistency.
1545 */
1546 pVmcs->u64GuestPdpte0.u = 0;
1547 pVmcs->u64GuestPdpte1.u = 0;
1548 pVmcs->u64GuestPdpte2.u = 0;
1549 pVmcs->u64GuestPdpte3.u = 0;
1550 }
1551 else
1552 {
1553 /*
1554 * With EPT and when the nested-guest is using PAE paging, we update the PDPTEs from
1555 * the nested-guest CPU context. Both IEM (Mov CRx) and hardware-assisted execution
1556 * of the nested-guest is expected to have updated them.
1557 */
1558 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1559 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1560 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1561 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1562 }
1563
1564 /* Clear PGM's copy of the EPT pointer for added safety. */
1565 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1566 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1567}
1568
1569
1570/**
1571 * Saves the guest-state as part of VM-exit.
1572 *
1573 * @returns VBox status code.
1574 * @param pVCpu The cross context virtual CPU structure.
1575 * @param uExitReason The VM-exit reason.
1576 */
1577static void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1578{
1579 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1580 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1581
1582 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1583 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1584 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1585
1586 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1587}
1588
1589
1590/**
1591 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1592 *
1593 * @returns VBox status code.
1594 * @param pVCpu The cross context virtual CPU structure.
1595 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1596 */
1597static int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1598{
1599 /*
1600 * Save guest MSRs.
1601 * See Intel spec. 27.4 "Saving MSRs".
1602 */
1603 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1604 const char * const pszFailure = "VMX-abort";
1605
1606 /*
1607 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1608 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1609 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1610 */
1611 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1612 if (!cMsrs)
1613 return VINF_SUCCESS;
1614
1615 /*
1616 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1617 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1618 * implementation causes a VMX-abort followed by a triple-fault.
1619 */
1620 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1621 if (fIsMsrCountValid)
1622 { /* likely */ }
1623 else
1624 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1625
1626 /*
1627 * Optimization if the nested hypervisor is using the same guest-physical page for both
1628 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1629 */
1630 PVMXAUTOMSR pMsrArea;
1631 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1632 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1633 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1634 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1635 else
1636 {
1637 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1638 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1639 if (RT_SUCCESS(rc))
1640 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1641 else
1642 {
1643 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1644 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1645 }
1646 }
1647
1648 /*
1649 * Update VM-exit MSR store area.
1650 */
1651 PVMXAUTOMSR pMsr = pMsrArea;
1652 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1653 {
1654 if ( !pMsr->u32Reserved
1655 && pMsr->u32Msr != MSR_IA32_SMBASE
1656 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1657 {
1658 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1659 if (rcStrict == VINF_SUCCESS)
1660 continue;
1661
1662 /*
1663 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1664 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1665 * recording the MSR index in the auxiliary info. field and indicated further by our
1666 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1667 * if possible, or come up with a better, generic solution.
1668 */
1669 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1670 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1671 ? kVmxVDiag_Vmexit_MsrStoreRing3
1672 : kVmxVDiag_Vmexit_MsrStore;
1673 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1674 }
1675 else
1676 {
1677 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1678 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1679 }
1680 }
1681
1682 /*
1683 * Commit the VM-exit MSR store are to guest memory.
1684 */
1685 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1686 if (RT_SUCCESS(rc))
1687 return VINF_SUCCESS;
1688
1689 NOREF(uExitReason);
1690 NOREF(pszFailure);
1691
1692 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1693 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1694}
1695
1696
1697/**
1698 * Performs a VMX abort (due to an fatal error during VM-exit).
1699 *
1700 * @returns Strict VBox status code.
1701 * @param pVCpu The cross context virtual CPU structure.
1702 * @param enmAbort The VMX abort reason.
1703 */
1704static VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort) RT_NOEXCEPT
1705{
1706 /*
1707 * Perform the VMX abort.
1708 * See Intel spec. 27.7 "VMX Aborts".
1709 */
1710 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1711
1712 /* We don't support SMX yet. */
1713 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1714 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1715 {
1716 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1717 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1718 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1719 }
1720
1721 return VINF_EM_TRIPLE_FAULT;
1722}
1723
1724
1725/**
1726 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1727 *
1728 * @param pVCpu The cross context virtual CPU structure.
1729 */
1730static void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1731{
1732 /*
1733 * Load host control registers, debug registers and MSRs.
1734 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1735 */
1736 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1737 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1738
1739 /* CR0. */
1740 {
1741 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1742 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK;
1743 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1744 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1745 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1746
1747 /* Verify we have not modified CR0 fixed bits in VMX operation. */
1748#ifdef VBOX_STRICT
1749 uint64_t const uCr0Mb1 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
1750 bool const fUx = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1751 AssertMsg( (uValidHostCr0 & uCr0Mb1) == uCr0Mb1
1752 && (uValidHostCr0 & ~VMX_V_CR0_FIXED1) == 0,
1753 ("host=%#RX64 guest=%#RX64 mb1=%#RX64 valid_host_cr0=%#RX64 fUx=%RTbool\n",
1754 uHostCr0, uGuestCr0, uCr0Mb1, uValidHostCr0, fUx));
1755#endif
1756 Assert(!(uValidHostCr0 >> 32));
1757 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1758 }
1759
1760 /* CR4. */
1761 {
1762 /* CR4 fixed bits are not modified. */
1763 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1764 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1765 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1766 uint64_t uValidHostCr4 = (uHostCr4 & uCr4Mb0) | uCr4Mb1;
1767 if (fHostInLongMode)
1768 uValidHostCr4 |= X86_CR4_PAE;
1769 else
1770 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1771
1772 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1773 AssertMsg( (uValidHostCr4 & uCr4Mb1) == uCr4Mb1
1774 && (uValidHostCr4 & ~uCr4Mb0) == 0,
1775 ("host=%#RX64 guest=%#RX64, uCr4Mb1=%#RX64 uCr4Mb0=%#RX64 valid_host_cr4=%#RX64\n",
1776 uHostCr4, pVCpu->cpum.GstCtx.cr4, uCr4Mb1, uCr4Mb0, uValidHostCr4));
1777 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1778 }
1779
1780 /* CR3 (host value validated while checking host-state during VM-entry). */
1781 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1782
1783 /* DR7. */
1784 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1785
1786 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1787
1788 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1789 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1790 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1791 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1792
1793 /* FS, GS bases are loaded later while we load host segment registers. */
1794
1795 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1796 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1797 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1798 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1799 {
1800 if (fHostInLongMode)
1801 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1802 else
1803 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1804 }
1805
1806 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1807
1808 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1809 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1810 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1811
1812 /* We don't support IA32_BNDCFGS MSR yet. */
1813}
1814
1815
1816/**
1817 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1818 *
1819 * @param pVCpu The cross context virtual CPU structure.
1820 */
1821static void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1822{
1823 /*
1824 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1825 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1826 *
1827 * Warning! Be careful to not touch fields that are reserved by VT-x,
1828 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1829 */
1830 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1831 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1832
1833 /* CS, SS, ES, DS, FS, GS. */
1834 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1835 {
1836 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1837 bool const fUnusable = RT_BOOL(HostSel == 0);
1838 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1839
1840 /* Selector. */
1841 pSelReg->Sel = HostSel;
1842 pSelReg->ValidSel = HostSel;
1843 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1844
1845 /* Limit. */
1846 pSelReg->u32Limit = 0xffffffff;
1847
1848 /* Base. */
1849 pSelReg->u64Base = 0;
1850
1851 /* Attributes. */
1852 if (iSegReg == X86_SREG_CS)
1853 {
1854 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1855 pSelReg->Attr.n.u1DescType = 1;
1856 pSelReg->Attr.n.u2Dpl = 0;
1857 pSelReg->Attr.n.u1Present = 1;
1858 pSelReg->Attr.n.u1Long = fHostInLongMode;
1859 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1860 pSelReg->Attr.n.u1Granularity = 1;
1861 Assert(!pSelReg->Attr.n.u1Unusable);
1862 Assert(!fUnusable);
1863 }
1864 else
1865 {
1866 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1867 pSelReg->Attr.n.u1DescType = 1;
1868 pSelReg->Attr.n.u2Dpl = 0;
1869 pSelReg->Attr.n.u1Present = 1;
1870 pSelReg->Attr.n.u1DefBig = 1;
1871 pSelReg->Attr.n.u1Granularity = 1;
1872 pSelReg->Attr.n.u1Unusable = fUnusable;
1873 }
1874 }
1875
1876 /* FS base. */
1877 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1878 || fHostInLongMode)
1879 {
1880 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1881 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1882 }
1883
1884 /* GS base. */
1885 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1886 || fHostInLongMode)
1887 {
1888 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1889 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1890 }
1891
1892 /* TR. */
1893 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1894 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1895 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1896 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1897 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1898 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1899 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1900 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1901 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1902 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1903 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1904 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1905 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1906
1907 /* LDTR (Warning! do not touch the base and limits here). */
1908 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1909 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1910 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1911 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1912
1913 /* GDTR. */
1914 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1915 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1916 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1917
1918 /* IDTR.*/
1919 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1920 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1921 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1922}
1923
1924
1925/**
1926 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1927 *
1928 * @returns VBox status code.
1929 * @param pVCpu The cross context virtual CPU structure.
1930 * @param uExitReason The VMX instruction name (for logging purposes).
1931 */
1932static int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1933{
1934 /*
1935 * Load host MSRs.
1936 * See Intel spec. 27.6 "Loading MSRs".
1937 */
1938 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1939 const char * const pszFailure = "VMX-abort";
1940
1941 /*
1942 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1943 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1944 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1945 */
1946 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1947 if (!cMsrs)
1948 return VINF_SUCCESS;
1949
1950 /*
1951 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1952 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1953 * implementation causes a VMX-abort followed by a triple-fault.
1954 */
1955 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1956 if (fIsMsrCountValid)
1957 { /* likely */ }
1958 else
1959 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1960
1961 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1962 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1963 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1964 if (RT_SUCCESS(rc))
1965 {
1966 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1967 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1968 {
1969 if ( !pMsr->u32Reserved
1970 && pMsr->u32Msr != MSR_K8_FS_BASE
1971 && pMsr->u32Msr != MSR_K8_GS_BASE
1972 && pMsr->u32Msr != MSR_K6_EFER
1973 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1974 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1975 {
1976 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1977 if (rcStrict == VINF_SUCCESS)
1978 continue;
1979
1980 /*
1981 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1982 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1983 * recording the MSR index in the auxiliary info. field and indicated further by our
1984 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1985 * if possible, or come up with a better, generic solution.
1986 */
1987 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1988 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1989 ? kVmxVDiag_Vmexit_MsrLoadRing3
1990 : kVmxVDiag_Vmexit_MsrLoad;
1991 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1992 }
1993 else
1994 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1995 }
1996 }
1997 else
1998 {
1999 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2000 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2001 }
2002
2003 NOREF(uExitReason);
2004 NOREF(pszFailure);
2005 return VINF_SUCCESS;
2006}
2007
2008
2009/**
2010 * Loads the host state as part of VM-exit.
2011 *
2012 * @returns Strict VBox status code.
2013 * @param pVCpu The cross context virtual CPU structure.
2014 * @param uExitReason The VM-exit reason (for logging purposes).
2015 */
2016static VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
2017{
2018 /*
2019 * Load host state.
2020 * See Intel spec. 27.5 "Loading Host State".
2021 */
2022 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2023 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2024
2025 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2026 if ( CPUMIsGuestInLongMode(pVCpu)
2027 && !fHostInLongMode)
2028 {
2029 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2030 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2031 }
2032
2033 /*
2034 * Check host PAE PDPTEs prior to loading the host state.
2035 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2036 */
2037 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2038 && !fHostInLongMode
2039 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2040 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2041 {
2042 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2043 if (RT_SUCCESS(rc))
2044 { /* likely*/ }
2045 else
2046 {
2047 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2048 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2049 }
2050 }
2051
2052 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2053 iemVmxVmexitLoadHostSegRegs(pVCpu);
2054
2055 /*
2056 * Load host RIP, RSP and RFLAGS.
2057 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2058 */
2059 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2060 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2061 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2062
2063 /* Clear address range monitoring. */
2064 EMMonitorWaitClear(pVCpu);
2065
2066 /* Perform the VMX transition (PGM updates). */
2067 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2068 if (rcStrict == VINF_SUCCESS)
2069 { /* likely */ }
2070 else if (RT_SUCCESS(rcStrict))
2071 {
2072 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2073 uExitReason));
2074 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2075 }
2076 else
2077 {
2078 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2079 return VBOXSTRICTRC_VAL(rcStrict);
2080 }
2081
2082 Assert(rcStrict == VINF_SUCCESS);
2083
2084 /* Load MSRs from the VM-exit auto-load MSR area. */
2085 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2086 if (RT_FAILURE(rc))
2087 {
2088 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2089 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2090 }
2091 return VINF_SUCCESS;
2092}
2093
2094
2095/**
2096 * Gets VM-exit instruction information along with any displacement for an
2097 * instruction VM-exit.
2098 *
2099 * @returns The VM-exit instruction information.
2100 * @param pVCpu The cross context virtual CPU structure.
2101 * @param uExitReason The VM-exit reason.
2102 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2103 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2104 * NULL.
2105 */
2106static uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp) RT_NOEXCEPT
2107{
2108 RTGCPTR GCPtrDisp;
2109 VMXEXITINSTRINFO ExitInstrInfo;
2110 ExitInstrInfo.u = 0;
2111
2112 /*
2113 * Get and parse the ModR/M byte from our decoded opcodes.
2114 */
2115 uint8_t bRm;
2116 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2117 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2118 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2119 {
2120 /*
2121 * ModR/M indicates register addressing.
2122 *
2123 * The primary/secondary register operands are reported in the iReg1 or iReg2
2124 * fields depending on whether it is a read/write form.
2125 */
2126 uint8_t idxReg1;
2127 uint8_t idxReg2;
2128 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2129 {
2130 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2131 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2132 }
2133 else
2134 {
2135 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2136 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2137 }
2138 ExitInstrInfo.All.u2Scaling = 0;
2139 ExitInstrInfo.All.iReg1 = idxReg1;
2140 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2141 ExitInstrInfo.All.fIsRegOperand = 1;
2142 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2143 ExitInstrInfo.All.iSegReg = 0;
2144 ExitInstrInfo.All.iIdxReg = 0;
2145 ExitInstrInfo.All.fIdxRegInvalid = 1;
2146 ExitInstrInfo.All.iBaseReg = 0;
2147 ExitInstrInfo.All.fBaseRegInvalid = 1;
2148 ExitInstrInfo.All.iReg2 = idxReg2;
2149
2150 /* Displacement not applicable for register addressing. */
2151 GCPtrDisp = 0;
2152 }
2153 else
2154 {
2155 /*
2156 * ModR/M indicates memory addressing.
2157 */
2158 uint8_t uScale = 0;
2159 bool fBaseRegValid = false;
2160 bool fIdxRegValid = false;
2161 uint8_t iBaseReg = 0;
2162 uint8_t iIdxReg = 0;
2163 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2164 {
2165 /*
2166 * Parse the ModR/M, displacement for 16-bit addressing mode.
2167 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2168 */
2169 uint16_t u16Disp = 0;
2170 uint8_t const offDisp = offModRm + sizeof(bRm);
2171 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2172 {
2173 /* Displacement without any registers. */
2174 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2175 }
2176 else
2177 {
2178 /* Register (index and base). */
2179 switch (bRm & X86_MODRM_RM_MASK)
2180 {
2181 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2182 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2183 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2184 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2185 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2186 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2187 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2188 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2189 }
2190
2191 /* Register + displacement. */
2192 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2193 {
2194 case 0: break;
2195 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2196 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2197 default:
2198 {
2199 /* Register addressing, handled at the beginning. */
2200 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2201 break;
2202 }
2203 }
2204 }
2205
2206 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2207 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2208 }
2209 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2210 {
2211 /*
2212 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2213 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2214 */
2215 uint32_t u32Disp = 0;
2216 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2217 {
2218 /* Displacement without any registers. */
2219 uint8_t const offDisp = offModRm + sizeof(bRm);
2220 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2221 }
2222 else
2223 {
2224 /* Register (and perhaps scale, index and base). */
2225 uint8_t offDisp = offModRm + sizeof(bRm);
2226 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2227 if (iBaseReg == 4)
2228 {
2229 /* An SIB byte follows the ModR/M byte, parse it. */
2230 uint8_t bSib;
2231 uint8_t const offSib = offModRm + sizeof(bRm);
2232 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2233
2234 /* A displacement may follow SIB, update its offset. */
2235 offDisp += sizeof(bSib);
2236
2237 /* Get the scale. */
2238 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2239
2240 /* Get the index register. */
2241 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2242 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2243
2244 /* Get the base register. */
2245 iBaseReg = bSib & X86_SIB_BASE_MASK;
2246 fBaseRegValid = true;
2247 if (iBaseReg == 5)
2248 {
2249 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2250 {
2251 /* Mod is 0 implies a 32-bit displacement with no base. */
2252 fBaseRegValid = false;
2253 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2254 }
2255 else
2256 {
2257 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2258 iBaseReg = X86_GREG_xBP;
2259 }
2260 }
2261 }
2262
2263 /* Register + displacement. */
2264 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2265 {
2266 case 0: /* Handled above */ break;
2267 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2268 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2269 default:
2270 {
2271 /* Register addressing, handled at the beginning. */
2272 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2273 break;
2274 }
2275 }
2276 }
2277
2278 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2279 }
2280 else
2281 {
2282 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2283
2284 /*
2285 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2286 * See Intel instruction spec. 2.2 "IA-32e Mode".
2287 */
2288 uint64_t u64Disp = 0;
2289 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2290 if (fRipRelativeAddr)
2291 {
2292 /*
2293 * RIP-relative addressing mode.
2294 *
2295 * The displacement is 32-bit signed implying an offset range of +/-2G.
2296 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2297 */
2298 uint8_t const offDisp = offModRm + sizeof(bRm);
2299 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2300 }
2301 else
2302 {
2303 uint8_t offDisp = offModRm + sizeof(bRm);
2304
2305 /*
2306 * Register (and perhaps scale, index and base).
2307 *
2308 * REX.B extends the most-significant bit of the base register. However, REX.B
2309 * is ignored while determining whether an SIB follows the opcode. Hence, we
2310 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2311 *
2312 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2313 */
2314 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2315 if (iBaseReg == 4)
2316 {
2317 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2318 uint8_t bSib;
2319 uint8_t const offSib = offModRm + sizeof(bRm);
2320 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2321
2322 /* Displacement may follow SIB, update its offset. */
2323 offDisp += sizeof(bSib);
2324
2325 /* Get the scale. */
2326 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2327
2328 /* Get the index. */
2329 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2330 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2331
2332 /* Get the base. */
2333 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2334 fBaseRegValid = true;
2335 if (iBaseReg == 5)
2336 {
2337 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2338 {
2339 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2340 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2341 }
2342 else
2343 {
2344 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2345 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2346 }
2347 }
2348 }
2349 iBaseReg |= pVCpu->iem.s.uRexB;
2350
2351 /* Register + displacement. */
2352 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2353 {
2354 case 0: /* Handled above */ break;
2355 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2356 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2357 default:
2358 {
2359 /* Register addressing, handled at the beginning. */
2360 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2361 break;
2362 }
2363 }
2364 }
2365
2366 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2367 }
2368
2369 /*
2370 * The primary or secondary register operand is reported in iReg2 depending
2371 * on whether the primary operand is in read/write form.
2372 */
2373 uint8_t idxReg2;
2374 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2375 {
2376 idxReg2 = bRm & X86_MODRM_RM_MASK;
2377 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2378 idxReg2 |= pVCpu->iem.s.uRexB;
2379 }
2380 else
2381 {
2382 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2383 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2384 idxReg2 |= pVCpu->iem.s.uRexReg;
2385 }
2386 ExitInstrInfo.All.u2Scaling = uScale;
2387 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2388 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2389 ExitInstrInfo.All.fIsRegOperand = 0;
2390 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2391 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2392 ExitInstrInfo.All.iIdxReg = iIdxReg;
2393 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2394 ExitInstrInfo.All.iBaseReg = iBaseReg;
2395 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2396 ExitInstrInfo.All.iReg2 = idxReg2;
2397 }
2398
2399 /*
2400 * Handle exceptions to the norm for certain instructions.
2401 * (e.g. some instructions convey an instruction identity in place of iReg2).
2402 */
2403 switch (uExitReason)
2404 {
2405 case VMX_EXIT_GDTR_IDTR_ACCESS:
2406 {
2407 Assert(VMXINSTRID_IS_VALID(uInstrId));
2408 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2409 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2410 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2411 break;
2412 }
2413
2414 case VMX_EXIT_LDTR_TR_ACCESS:
2415 {
2416 Assert(VMXINSTRID_IS_VALID(uInstrId));
2417 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2418 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2419 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2420 break;
2421 }
2422
2423 case VMX_EXIT_RDRAND:
2424 case VMX_EXIT_RDSEED:
2425 {
2426 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2427 break;
2428 }
2429 }
2430
2431 /* Update displacement and return the constructed VM-exit instruction information field. */
2432 if (pGCPtrDisp)
2433 *pGCPtrDisp = GCPtrDisp;
2434
2435 return ExitInstrInfo.u;
2436}
2437
2438
2439/**
2440 * VMX VM-exit handler.
2441 *
2442 * @returns Strict VBox status code.
2443 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2444 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2445 * triple-fault.
2446 *
2447 * @param pVCpu The cross context virtual CPU structure.
2448 * @param uExitReason The VM-exit reason.
2449 * @param u64ExitQual The Exit qualification.
2450 *
2451 * @remarks We need not necessarily have completed VM-entry before a VM-exit is
2452 * called. Failures during VM-entry can cause VM-exits as well, so we
2453 * -cannot- assert we're in VMX non-root mode here.
2454 */
2455VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT
2456{
2457# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2458 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2459 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2460 return VERR_IEM_IPE_7;
2461# else
2462 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2463
2464 /* Just count this as an exit and be done with that. */
2465 pVCpu->iem.s.cPotentialExits++;
2466
2467 /*
2468 * Import all the guest-CPU state.
2469 *
2470 * HM on returning to guest execution would have to reset up a whole lot of state
2471 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2472 * the state and flag reloading the entire state on re-entry. So import the entire
2473 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2474 */
2475 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2476
2477 /*
2478 * Ensure VM-entry interruption information valid bit is cleared.
2479 *
2480 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2481 * by invalid-guest state or machine-check exceptions) also clear this bit.
2482 *
2483 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2484 */
2485 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2486 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2487
2488 /*
2489 * Update the VM-exit reason and Exit qualification.
2490 * Other VMCS read-only data fields are expected to be updated by the caller already.
2491 */
2492 pVmcs->u32RoExitReason = uExitReason;
2493 pVmcs->u64RoExitQual.u = u64ExitQual;
2494
2495 Log2(("vmexit: reason=%u qual=%#RX64 cs:rip=%04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 eflags=%#RX32\n", uExitReason,
2496 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2497 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.eflags.u));
2498
2499 /*
2500 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2501 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2502 */
2503 {
2504 uint8_t uVector;
2505 uint32_t fFlags;
2506 uint32_t uErrCode;
2507 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2508 if (fInEventDelivery)
2509 {
2510 /*
2511 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2512 * caused by a triple-fault or the original event results in a double-fault that
2513 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2514 * original event information into the IDT-vectoring information fields.
2515 *
2516 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2517 */
2518 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2519 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2520 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2521 {
2522 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2523 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2524 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2525 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2526 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2527 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2528 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2529 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2530 Log2(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2531 pVCpu->cpum.GstCtx.cr2));
2532 }
2533 }
2534 }
2535
2536 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2537 Assert(pVmcs->u64RoIoRcx.u == 0);
2538 Assert(pVmcs->u64RoIoRsi.u == 0);
2539 Assert(pVmcs->u64RoIoRdi.u == 0);
2540 Assert(pVmcs->u64RoIoRip.u == 0);
2541
2542 /*
2543 * Save the guest state back into the VMCS.
2544 * We only need to save the state when the VM-entry was successful.
2545 */
2546 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2547 if (!fVmentryFailed)
2548 {
2549 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2550 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2551 {
2552 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2553 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2554 }
2555
2556 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2557 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2558
2559 /*
2560 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2561 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2562 *
2563 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2564 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2565 * as guest-CPU state would not been modified. Hence for now, we do this only when
2566 * the VM-entry succeeded.
2567 */
2568 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2569 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2570 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2571 {
2572 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2573 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2574 else
2575 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2576 }
2577
2578 /*
2579 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2580 * occurs in enclave mode/SMM which we don't support yet.
2581 *
2582 * If we ever add support for it, we can pass just the lower bits to the functions
2583 * below, till then an assert should suffice.
2584 */
2585 Assert(!RT_HI_U16(uExitReason));
2586
2587 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2588 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2589 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2590 if (RT_SUCCESS(rc))
2591 { /* likely */ }
2592 else
2593 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2594
2595 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2596 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit &= ~CPUMCTX_INHIBIT_NMI;
2597 }
2598 else
2599 {
2600 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2601 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2602 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2603 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2604 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2605 }
2606
2607 /*
2608 * Stop any running VMX-preemption timer if necessary.
2609 */
2610 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2611 CPUMStopGuestVmxPremptTimer(pVCpu);
2612
2613 /*
2614 * Clear any pending VMX nested-guest force-flags.
2615 * These force-flags have no effect on (outer) guest execution and will
2616 * be re-evaluated and setup on the next nested-guest VM-entry.
2617 */
2618 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2619
2620 /*
2621 * We're no longer in nested-guest execution mode.
2622 *
2623 * It is important to do this prior to loading the host state because
2624 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2625 * second-level address translation while switching to host CR3.
2626 */
2627 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2628
2629 /* Restore the host (outer guest) state. */
2630 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2631 if (RT_SUCCESS(rcStrict))
2632 {
2633 Assert(rcStrict == VINF_SUCCESS);
2634 rcStrict = VINF_VMX_VMEXIT;
2635 }
2636 else
2637 Log(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2638
2639 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
2640 {
2641 /* Notify HM that the current VMCS fields have been modified. */
2642 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2643
2644 /* Notify HM that we've completed the VM-exit. */
2645 HMNotifyVmxNstGstVmexit(pVCpu);
2646 }
2647
2648# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2649 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2650 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2651 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2652 if (rcSched != VINF_SUCCESS)
2653 iemSetPassUpStatus(pVCpu, rcSched);
2654# endif
2655 return rcStrict;
2656# endif
2657}
2658
2659
2660/**
2661 * VMX VM-exit handler for VM-exits due to instruction execution.
2662 *
2663 * This is intended for instructions where the caller provides all the relevant
2664 * VM-exit information.
2665 *
2666 * @returns Strict VBox status code.
2667 * @param pVCpu The cross context virtual CPU structure.
2668 * @param pExitInfo Pointer to the VM-exit information.
2669 */
2670static VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
2671{
2672 /*
2673 * For instructions where any of the following fields are not applicable:
2674 * - Exit qualification must be cleared.
2675 * - VM-exit instruction info. is undefined.
2676 * - Guest-linear address is undefined.
2677 * - Guest-physical address is undefined.
2678 *
2679 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2680 * instruction execution. For VM-exits that are not due to instruction execution this
2681 * field is undefined.
2682 *
2683 * In our implementation in IEM, all undefined fields are generally cleared. However,
2684 * if the caller supplies information (from say the physical CPU directly) it is
2685 * then possible that the undefined fields are not cleared.
2686 *
2687 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2688 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2689 */
2690 Assert(pExitInfo);
2691 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2692 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2693 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2694
2695 /* Update all the relevant fields from the VM-exit instruction information struct. */
2696 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2697 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2698 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2699 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2700
2701 /* Perform the VM-exit. */
2702 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2703}
2704
2705
2706/**
2707 * VMX VM-exit handler for VM-exits due to instruction execution.
2708 *
2709 * This is intended for instructions that only provide the VM-exit instruction
2710 * length.
2711 *
2712 * @param pVCpu The cross context virtual CPU structure.
2713 * @param uExitReason The VM-exit reason.
2714 * @param cbInstr The instruction length in bytes.
2715 */
2716VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT
2717{
2718#ifdef VBOX_STRICT
2719 /*
2720 * To prevent us from shooting ourselves in the foot.
2721 * The follow instructions should convey more than just the instruction length.
2722 */
2723 switch (uExitReason)
2724 {
2725 case VMX_EXIT_INVEPT:
2726 case VMX_EXIT_INVPCID:
2727 case VMX_EXIT_INVVPID:
2728 case VMX_EXIT_LDTR_TR_ACCESS:
2729 case VMX_EXIT_GDTR_IDTR_ACCESS:
2730 case VMX_EXIT_VMCLEAR:
2731 case VMX_EXIT_VMPTRLD:
2732 case VMX_EXIT_VMPTRST:
2733 case VMX_EXIT_VMREAD:
2734 case VMX_EXIT_VMWRITE:
2735 case VMX_EXIT_VMXON:
2736 case VMX_EXIT_XRSTORS:
2737 case VMX_EXIT_XSAVES:
2738 case VMX_EXIT_RDRAND:
2739 case VMX_EXIT_RDSEED:
2740 case VMX_EXIT_IO_INSTR:
2741 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2742 break;
2743 }
2744#endif
2745
2746 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_INSTR_LEN(uExitReason, cbInstr);
2747 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2748}
2749
2750
2751/**
2752 * Interface for HM and EM to emulate VM-exit due to a triple-fault.
2753 *
2754 * @returns Strict VBox status code.
2755 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2756 * @thread EMT(pVCpu)
2757 */
2758VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu)
2759{
2760 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
2761 Assert(!pVCpu->iem.s.cActiveMappings);
2762 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2763}
2764
2765
2766/**
2767 * Interface for HM and EM to emulate VM-exit due to startup-IPI (SIPI).
2768 *
2769 * @returns Strict VBox status code.
2770 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2771 * @param uVector The SIPI vector.
2772 * @thread EMT(pVCpu)
2773 */
2774VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector)
2775{
2776 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_SIPI, uVector);
2777 Assert(!pVCpu->iem.s.cActiveMappings);
2778 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2779}
2780
2781
2782/**
2783 * Interface for HM and EM to emulate a VM-exit.
2784 *
2785 * If a specialized version of a VM-exit handler exists, that must be used instead.
2786 *
2787 * @returns Strict VBox status code.
2788 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2789 * @param uExitReason The VM-exit reason.
2790 * @param u64ExitQual The Exit qualification.
2791 * @thread EMT(pVCpu)
2792 */
2793VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2794{
2795 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, uExitReason, u64ExitQual);
2796 Assert(!pVCpu->iem.s.cActiveMappings);
2797 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2798}
2799
2800
2801/**
2802 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2803 *
2804 * This is meant to be used for those instructions that VMX provides additional
2805 * decoding information beyond just the instruction length!
2806 *
2807 * @returns Strict VBox status code.
2808 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2809 * @param pExitInfo Pointer to the VM-exit information.
2810 * @thread EMT(pVCpu)
2811 */
2812VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2813{
2814 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
2815 Assert(!pVCpu->iem.s.cActiveMappings);
2816 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2817}
2818
2819
2820/**
2821 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2822 *
2823 * This is meant to be used for those instructions that VMX provides only the
2824 * instruction length.
2825 *
2826 * @returns Strict VBox status code.
2827 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2828 * @param pExitInfo Pointer to the VM-exit information.
2829 * @param cbInstr The instruction length in bytes.
2830 * @thread EMT(pVCpu)
2831 */
2832VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2833{
2834 VBOXSTRICTRC rcStrict = iemVmxVmexitInstr(pVCpu, uExitReason, cbInstr);
2835 Assert(!pVCpu->iem.s.cActiveMappings);
2836 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2837}
2838
2839
2840/**
2841 * VMX VM-exit handler for VM-exits due to instruction execution.
2842 *
2843 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2844 * instruction information and Exit qualification fields.
2845 *
2846 * @param pVCpu The cross context virtual CPU structure.
2847 * @param uExitReason The VM-exit reason.
2848 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2849 * @param cbInstr The instruction length in bytes.
2850 *
2851 * @remarks Do not use this for INS/OUTS instruction.
2852 */
2853VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT
2854{
2855#ifdef VBOX_STRICT
2856 /*
2857 * To prevent us from shooting ourselves in the foot.
2858 * The follow instructions convey specific info that require using their respective handlers.
2859 */
2860 switch (uExitReason)
2861 {
2862 case VMX_EXIT_INVEPT:
2863 case VMX_EXIT_INVPCID:
2864 case VMX_EXIT_INVVPID:
2865 case VMX_EXIT_LDTR_TR_ACCESS:
2866 case VMX_EXIT_GDTR_IDTR_ACCESS:
2867 case VMX_EXIT_VMCLEAR:
2868 case VMX_EXIT_VMPTRLD:
2869 case VMX_EXIT_VMPTRST:
2870 case VMX_EXIT_VMREAD:
2871 case VMX_EXIT_VMWRITE:
2872 case VMX_EXIT_VMXON:
2873 case VMX_EXIT_XRSTORS:
2874 case VMX_EXIT_XSAVES:
2875 case VMX_EXIT_RDRAND:
2876 case VMX_EXIT_RDSEED:
2877 break;
2878 default:
2879 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2880 break;
2881 }
2882#endif
2883
2884 /*
2885 * Update the Exit qualification field with displacement bytes.
2886 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2887 */
2888 /* Construct the VM-exit instruction information. */
2889 RTGCPTR GCPtrDisp;
2890 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2891
2892 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO(uExitReason, GCPtrDisp, uInstrInfo, cbInstr);
2893 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2894}
2895
2896
2897/**
2898 * VMX VM-exit handler for VM-exits due to INVLPG.
2899 *
2900 * @returns Strict VBox status code.
2901 * @param pVCpu The cross context virtual CPU structure.
2902 * @param GCPtrPage The guest-linear address of the page being invalidated.
2903 * @param cbInstr The instruction length in bytes.
2904 */
2905VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT
2906{
2907 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_INVLPG, GCPtrPage, cbInstr);
2908 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2909 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2910}
2911
2912
2913/**
2914 * VMX VM-exit handler for VM-exits due to LMSW.
2915 *
2916 * @returns Strict VBox status code.
2917 * @param pVCpu The cross context virtual CPU structure.
2918 * @param uGuestCr0 The current guest CR0.
2919 * @param pu16NewMsw The machine-status word specified in LMSW's source
2920 * operand. This will be updated depending on the VMX
2921 * guest/host CR0 mask if LMSW is not intercepted.
2922 * @param GCPtrEffDst The guest-linear address of the source operand in case
2923 * of a memory operand. For register operand, pass
2924 * NIL_RTGCPTR.
2925 * @param cbInstr The instruction length in bytes.
2926 */
2927VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
2928 RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT
2929{
2930 Assert(pu16NewMsw);
2931
2932 uint16_t const uNewMsw = *pu16NewMsw;
2933 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2934 {
2935 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2936 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2937 VMXVEXITINFO ExitInfo
2938 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
2939 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2940 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2941 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw)
2942 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW),
2943 cbInstr);
2944 if (fMemOperand)
2945 {
2946 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2947 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2948 }
2949 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2950 }
2951
2952 /*
2953 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2954 * CR0 guest/host mask must be left unmodified.
2955 *
2956 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2957 */
2958 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2959 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2960 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2961
2962 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2963}
2964
2965
2966/**
2967 * VMX VM-exit handler for VM-exits due to CLTS.
2968 *
2969 * @returns Strict VBox status code.
2970 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2971 * VM-exit but must not modify the guest CR0.TS bit.
2972 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2973 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2974 * CR0 fixed bits in VMX operation).
2975 * @param pVCpu The cross context virtual CPU structure.
2976 * @param cbInstr The instruction length in bytes.
2977 */
2978VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
2979{
2980 /*
2981 * If CR0.TS is owned by the host:
2982 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2983 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2984 * CLTS instruction completes without clearing CR0.TS.
2985 *
2986 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2987 */
2988 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2989 if (fGstHostMask & X86_CR0_TS)
2990 {
2991 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u & X86_CR0_TS)
2992 {
2993 Log2(("clts: Guest intercept -> VM-exit\n"));
2994 VMXVEXITINFO const ExitInfo
2995 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
2996 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2997 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
2998 VMX_EXIT_QUAL_CRX_ACCESS_CLTS),
2999 cbInstr);
3000 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3001 }
3002 return VINF_VMX_MODIFIES_BEHAVIOR;
3003 }
3004
3005 /*
3006 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3007 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3008 */
3009 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3010}
3011
3012
3013/**
3014 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3015 * (CR0/CR4 write).
3016 *
3017 * @returns Strict VBox status code.
3018 * @param pVCpu The cross context virtual CPU structure.
3019 * @param iCrReg The control register (either CR0 or CR4).
3020 * @param uGuestCrX The current guest CR0/CR4.
3021 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
3022 * VM-exit is caused.
3023 * @param iGReg The general register from which the CR0/CR4 value is being
3024 * loaded.
3025 * @param cbInstr The instruction length in bytes.
3026 */
3027VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX,
3028 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3029{
3030 Assert(puNewCrX);
3031 Assert(iCrReg == 0 || iCrReg == 4);
3032 Assert(iGReg < X86_GREG_COUNT);
3033
3034 uint64_t const uNewCrX = *puNewCrX;
3035 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3036 {
3037 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3038 VMXVEXITINFO const ExitInfo
3039 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3040 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3041 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3042 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3043 cbInstr);
3044 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3045 }
3046
3047 /*
3048 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3049 * must not be modified the instruction.
3050 *
3051 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3052 */
3053 uint64_t uGuestCrX;
3054 uint64_t fGstHostMask;
3055 if (iCrReg == 0)
3056 {
3057 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3058 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3059 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3060 }
3061 else
3062 {
3063 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3064 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3065 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
3066 }
3067
3068 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3069 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3070}
3071
3072
3073/**
3074 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3075 *
3076 * @returns VBox strict status code.
3077 * @param pVCpu The cross context virtual CPU structure.
3078 * @param iGReg The general register to which the CR3 value is being stored.
3079 * @param cbInstr The instruction length in bytes.
3080 */
3081VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3082{
3083 Assert(iGReg < X86_GREG_COUNT);
3084 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3085
3086 /*
3087 * If the CR3-store exiting control is set, we must cause a VM-exit.
3088 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3089 */
3090 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3091 {
3092 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3093 VMXVEXITINFO const ExitInfo
3094 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3095 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3096 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3097 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3098 cbInstr);
3099 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3100 }
3101 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3102}
3103
3104
3105/**
3106 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3107 *
3108 * @returns VBox strict status code.
3109 * @param pVCpu The cross context virtual CPU structure.
3110 * @param uNewCr3 The new CR3 value.
3111 * @param iGReg The general register from which the CR3 value is being
3112 * loaded.
3113 * @param cbInstr The instruction length in bytes.
3114 */
3115VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3116{
3117 Assert(iGReg < X86_GREG_COUNT);
3118
3119 /*
3120 * If the CR3-load exiting control is set and the new CR3 value does not
3121 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3122 *
3123 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3124 */
3125 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3126 {
3127 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3128 VMXVEXITINFO const ExitInfo
3129 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3130 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3131 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3132 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
3133 VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3134 cbInstr);
3135 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3136 }
3137 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3138}
3139
3140
3141/**
3142 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3143 *
3144 * @returns VBox strict status code.
3145 * @param pVCpu The cross context virtual CPU structure.
3146 * @param iGReg The general register to which the CR8 value is being stored.
3147 * @param cbInstr The instruction length in bytes.
3148 */
3149VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3150{
3151 Assert(iGReg < X86_GREG_COUNT);
3152
3153 /*
3154 * If the CR8-store exiting control is set, we must cause a VM-exit.
3155 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3156 */
3157 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3158 {
3159 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3160 VMXVEXITINFO const ExitInfo
3161 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3162 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3163 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3164 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3165 cbInstr);
3166 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3167 }
3168 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3169}
3170
3171
3172/**
3173 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3174 *
3175 * @returns VBox strict status code.
3176 * @param pVCpu The cross context virtual CPU structure.
3177 * @param iGReg The general register from which the CR8 value is being
3178 * loaded.
3179 * @param cbInstr The instruction length in bytes.
3180 */
3181VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3182{
3183 Assert(iGReg < X86_GREG_COUNT);
3184
3185 /*
3186 * If the CR8-load exiting control is set, we must cause a VM-exit.
3187 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3188 */
3189 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3190 {
3191 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3192 VMXVEXITINFO const ExitInfo
3193 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3194 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3195 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3196 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3197 cbInstr);
3198 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3199 }
3200 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3201}
3202
3203
3204/**
3205 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3206 * GReg,DRx' (DRx read).
3207 *
3208 * @returns VBox strict status code.
3209 * @param pVCpu The cross context virtual CPU structure.
3210 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3211 * VMXINSTRID_MOV_FROM_DRX).
3212 * @param iDrReg The debug register being accessed.
3213 * @param iGReg The general register to/from which the DRx value is being
3214 * store/loaded.
3215 * @param cbInstr The instruction length in bytes.
3216 */
3217VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg,
3218 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3219{
3220 Assert(iDrReg <= 7);
3221 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3222 Assert(iGReg < X86_GREG_COUNT);
3223
3224 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3225 {
3226 VMXVEXITINFO const ExitInfo
3227 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_DRX,
3228 RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3229 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg)
3230 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION,
3231 uInstrId == VMXINSTRID_MOV_TO_DRX
3232 ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3233 : VMX_EXIT_QUAL_DRX_DIRECTION_READ),
3234 cbInstr);
3235 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3236 }
3237
3238 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3239}
3240
3241
3242/**
3243 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3244 *
3245 * @returns VBox strict status code.
3246 * @param pVCpu The cross context virtual CPU structure.
3247 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3248 * VMXINSTRID_IO_OUT).
3249 * @param u16Port The I/O port being accessed.
3250 * @param fImm Whether the I/O port was encoded using an immediate operand
3251 * or the implicit DX register.
3252 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3253 * @param cbInstr The instruction length in bytes.
3254 */
3255VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3256 bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT
3257{
3258 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3259 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3260
3261 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3262 {
3263 VMXVEXITINFO const ExitInfo
3264 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_IO_INSTR,
3265 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3266 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3267 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port)
3268 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION,
3269 uInstrId == VMXINSTRID_IO_IN
3270 ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3271 : VMX_EXIT_QUAL_IO_DIRECTION_OUT),
3272 cbInstr);
3273 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3274 }
3275 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3276}
3277
3278
3279/**
3280 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3281 *
3282 * @returns VBox strict status code.
3283 * @param pVCpu The cross context virtual CPU structure.
3284 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3285 * VMXINSTRID_IO_OUTS).
3286 * @param u16Port The I/O port being accessed.
3287 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3288 * @param fRep Whether the instruction has a REP prefix or not.
3289 * @param ExitInstrInfo The VM-exit instruction info. field.
3290 * @param cbInstr The instruction length in bytes.
3291 */
3292VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3293 bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT
3294{
3295 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3296 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3297 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3298 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3299 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3300
3301 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3302 {
3303 /*
3304 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3305 */
3306 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3307 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3308 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3309 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3310 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3311
3312 uint32_t uDirection;
3313 uint64_t uGuestLinearAddr;
3314 if (uInstrId == VMXINSTRID_IO_INS)
3315 {
3316 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3317 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3318 }
3319 else
3320 {
3321 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3322 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3323 }
3324
3325 /*
3326 * If the segment is unusable, the guest-linear address in undefined.
3327 * We shall clear it for consistency.
3328 *
3329 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3330 */
3331 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3332 uGuestLinearAddr = 0;
3333
3334 VMXVEXITINFO const ExitInfo
3335 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO_AND_LIN_ADDR(VMX_EXIT_IO_INSTR,
3336 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3337 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3338 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3339 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3340 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING,
3341 VMX_EXIT_QUAL_IO_ENCODING_DX)
3342 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port),
3343 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo
3344 ? ExitInstrInfo.u : 0,
3345 cbInstr,
3346 uGuestLinearAddr);
3347 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3348 }
3349
3350 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3351}
3352
3353
3354/**
3355 * VMX VM-exit handler for VM-exits due to MWAIT.
3356 *
3357 * @returns VBox strict status code.
3358 * @param pVCpu The cross context virtual CPU structure.
3359 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3360 * @param cbInstr The instruction length in bytes.
3361 */
3362VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT
3363{
3364 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MWAIT, fMonitorHwArmed, cbInstr);
3365 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3366}
3367
3368
3369/**
3370 * VMX VM-exit handler for VM-exits due to PAUSE.
3371 *
3372 * @returns VBox strict status code.
3373 * @param pVCpu The cross context virtual CPU structure.
3374 * @param cbInstr The instruction length in bytes.
3375 */
3376static VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3377{
3378 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3379
3380 /*
3381 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3382 * "PAUSE-loop exiting" control.
3383 *
3384 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3385 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3386 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3387 * a VM-exit.
3388 *
3389 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3390 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3391 */
3392 bool fIntercept = false;
3393 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3394 fIntercept = true;
3395 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3396 && pVCpu->iem.s.uCpl == 0)
3397 {
3398 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3399
3400 /*
3401 * A previous-PAUSE-tick value of 0 is used to identify the first time
3402 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3403 * consider this to be the first execution of PAUSE in a loop according
3404 * to the Intel.
3405 *
3406 * All subsequent records for the previous-PAUSE-tick we ensure that it
3407 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3408 */
3409 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3410 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3411 uint64_t const uTick = TMCpuTickGet(pVCpu);
3412 uint32_t const uPleGap = pVmcs->u32PleGap;
3413 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3414 if ( *puPrevPauseTick == 0
3415 || uTick - *puPrevPauseTick > uPleGap)
3416 *puFirstPauseLoopTick = uTick;
3417 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3418 fIntercept = true;
3419
3420 *puPrevPauseTick = uTick | 1;
3421 }
3422
3423 if (fIntercept)
3424 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3425
3426 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3427}
3428
3429
3430/**
3431 * VMX VM-exit handler for VM-exits due to task switches.
3432 *
3433 * @returns VBox strict status code.
3434 * @param pVCpu The cross context virtual CPU structure.
3435 * @param enmTaskSwitch The cause of the task switch.
3436 * @param SelNewTss The selector of the new TSS.
3437 * @param cbInstr The instruction length in bytes.
3438 */
3439VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT
3440{
3441 /*
3442 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3443 *
3444 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3445 * instruction or delivery of the exception generated by one of these instructions
3446 * lead to a task switch through a task gate in the IDT, we need to provide the
3447 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3448 * leaves the VM-exit instruction length field undefined.
3449 *
3450 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3451 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3452 */
3453 Assert(cbInstr <= 15);
3454
3455 uint8_t uType;
3456 switch (enmTaskSwitch)
3457 {
3458 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3459 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3460 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3461 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3462 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3463 }
3464
3465 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3466 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3467 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3468 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3469}
3470
3471
3472/**
3473 * VMX VM-exit handler for trap-like VM-exits.
3474 *
3475 * @returns VBox strict status code.
3476 * @param pVCpu The cross context virtual CPU structure.
3477 * @param pExitInfo Pointer to the VM-exit information.
3478 * @param pExitEventInfo Pointer to the VM-exit event information.
3479 */
3480static VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
3481{
3482 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3483 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3484 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3485}
3486
3487
3488/**
3489 * Interface for HM and EM to emulate a trap-like VM-exit (MTF, APIC-write,
3490 * Virtualized-EOI, TPR-below threshold).
3491 *
3492 * @returns Strict VBox status code.
3493 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3494 * @param pExitInfo Pointer to the VM-exit information.
3495 * @thread EMT(pVCpu)
3496 */
3497VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3498{
3499 Assert(pExitInfo);
3500 VBOXSTRICTRC rcStrict = iemVmxVmexitTrapLikeWithInfo(pVCpu, pExitInfo);
3501 Assert(!pVCpu->iem.s.cActiveMappings);
3502 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3503}
3504
3505
3506/**
3507 * VMX VM-exit handler for VM-exits due to task switches.
3508 *
3509 * This is intended for task switches where the caller provides all the relevant
3510 * VM-exit information.
3511 *
3512 * @returns VBox strict status code.
3513 * @param pVCpu The cross context virtual CPU structure.
3514 * @param pExitInfo Pointer to the VM-exit information.
3515 * @param pExitEventInfo Pointer to the VM-exit event information.
3516 */
3517static VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3518 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3519{
3520 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3521 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3522 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3523 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3524 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3525}
3526
3527
3528/**
3529 * Interface for HM and EM to emulate a VM-exit due to a task switch.
3530 *
3531 * @returns Strict VBox status code.
3532 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3533 * @param pExitInfo Pointer to the VM-exit information.
3534 * @param pExitEventInfo Pointer to the VM-exit event information.
3535 * @thread EMT(pVCpu)
3536 */
3537VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3538{
3539 Assert(pExitInfo);
3540 Assert(pExitEventInfo);
3541 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3542 VBOXSTRICTRC rcStrict = iemVmxVmexitTaskSwitchWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3543 Assert(!pVCpu->iem.s.cActiveMappings);
3544 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3545}
3546
3547
3548/**
3549 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3550 *
3551 * @returns VBox strict status code.
3552 * @param pVCpu The cross context virtual CPU structure.
3553 */
3554VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
3555{
3556 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3557 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3558
3559 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3560 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3561
3562 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3563 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3564 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3565
3566 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3567 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3568}
3569
3570
3571/**
3572 * Interface for HM and EM to emulate VM-exit due to expiry of the preemption timer.
3573 *
3574 * @returns Strict VBox status code.
3575 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3576 * @thread EMT(pVCpu)
3577 */
3578VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3579{
3580 VBOXSTRICTRC rcStrict = iemVmxVmexitPreemptTimer(pVCpu);
3581 Assert(!pVCpu->iem.s.cActiveMappings);
3582 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3583}
3584
3585
3586/**
3587 * VMX VM-exit handler for VM-exits due to external interrupts.
3588 *
3589 * @returns VBox strict status code.
3590 * @param pVCpu The cross context virtual CPU structure.
3591 * @param uVector The external interrupt vector (pass 0 if the interrupt
3592 * is still pending since we typically won't know the
3593 * vector).
3594 * @param fIntPending Whether the external interrupt is pending or
3595 * acknowledged in the interrupt controller.
3596 */
3597static VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending) RT_NOEXCEPT
3598{
3599 Assert(!fIntPending || uVector == 0);
3600
3601 /* The VM-exit is subject to "External interrupt exiting" being set. */
3602 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3603 {
3604 if (fIntPending)
3605 {
3606 /*
3607 * If the interrupt is pending and we don't need to acknowledge the
3608 * interrupt on VM-exit, cause the VM-exit immediately.
3609 *
3610 * See Intel spec 25.2 "Other Causes Of VM Exits".
3611 */
3612 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3613 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3614
3615 /*
3616 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3617 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3618 * acknowledged that the interrupt has been consumed. Callers would have to call
3619 * us again after getting the vector (and ofc, with fIntPending with false).
3620 */
3621 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3622 }
3623
3624 /*
3625 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3626 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3627 * all set, we need to record the vector of the external interrupt in the
3628 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3629 *
3630 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3631 */
3632 uint32_t uExitIntInfo;
3633 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3634 {
3635 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3636 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3637 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3638 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3639 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3640 }
3641 else
3642 uExitIntInfo = 0;
3643 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3644
3645 /*
3646 * Cause the VM-exit whether or not the vector has been stored
3647 * in the VM-exit interruption-information field.
3648 */
3649 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3650 }
3651
3652 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3653}
3654
3655
3656/**
3657 * Interface for HM and EM to emulate VM-exit due to external interrupts.
3658 *
3659 * @returns Strict VBox status code.
3660 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3661 * @param uVector The external interrupt vector (pass 0 if the external
3662 * interrupt is still pending).
3663 * @param fIntPending Whether the external interrupt is pending or
3664 * acknowdledged in the interrupt controller.
3665 * @thread EMT(pVCpu)
3666 */
3667VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3668{
3669 VBOXSTRICTRC rcStrict = iemVmxVmexitExtInt(pVCpu, uVector, fIntPending);
3670 Assert(!pVCpu->iem.s.cActiveMappings);
3671 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3672}
3673
3674
3675/**
3676 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3677 * an event.
3678 *
3679 * @returns VBox strict status code.
3680 * @param pVCpu The cross context virtual CPU structure.
3681 */
3682VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT
3683{
3684 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3685 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3686 {
3687 /*
3688 * The NMI-unblocking due to IRET field need not be set for double faults.
3689 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3690 */
3691 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3692 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3693 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3694 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3695 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3696 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3697 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3698 }
3699
3700 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3701}
3702
3703
3704/**
3705 * VMX VM-exit handler for VM-exit due to delivery of an events.
3706 *
3707 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3708 * all the relevant VM-exit information.
3709 *
3710 * @returns VBox strict status code.
3711 * @param pVCpu The cross context virtual CPU structure.
3712 * @param pExitInfo Pointer to the VM-exit information.
3713 * @param pExitEventInfo Pointer to the VM-exit event information.
3714 */
3715static VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3716{
3717 Assert(pExitInfo);
3718 Assert(pExitEventInfo);
3719 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3720 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3721
3722 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3723 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3724 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3725 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3726 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3727 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3728}
3729
3730
3731/**
3732 * Interface for HM and EM to emulate VM-exit due to NMIs.
3733 *
3734 * @returns Strict VBox status code.
3735 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3736 * @thread EMT(pVCpu)
3737 */
3738VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu)
3739{
3740 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_ONLY_REASON(VMX_EXIT_XCPT_OR_NMI);
3741 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_INT( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1)
3742 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE,
3743 VMX_EXIT_INT_INFO_TYPE_NMI)
3744 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR,
3745 X86_XCPT_NMI),
3746 0);
3747 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
3748 Assert(!pVCpu->iem.s.cActiveMappings);
3749 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3750}
3751
3752
3753/**
3754 * Interface for HM and EM to emulate VM-exit due to exceptions.
3755 *
3756 * Exception includes NMIs, software exceptions (those generated by INT3 or
3757 * INTO) and privileged software exceptions (those generated by INT1/ICEBP).
3758 *
3759 * @returns Strict VBox status code.
3760 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3761 * @param pExitInfo Pointer to the VM-exit information.
3762 * @param pExitEventInfo Pointer to the VM-exit event information.
3763 * @thread EMT(pVCpu)
3764 */
3765VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3766{
3767 Assert(pExitInfo);
3768 Assert(pExitEventInfo);
3769 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3770 Assert(!pVCpu->iem.s.cActiveMappings);
3771 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3772}
3773
3774
3775/**
3776 * VMX VM-exit handler for VM-exits due to delivery of an event.
3777 *
3778 * @returns VBox strict status code.
3779 * @param pVCpu The cross context virtual CPU structure.
3780 * @param uVector The interrupt / exception vector.
3781 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3782 * @param uErrCode The error code associated with the event.
3783 * @param uCr2 The CR2 value in case of a \#PF exception.
3784 * @param cbInstr The instruction length in bytes.
3785 */
3786VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode,
3787 uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT
3788{
3789 /*
3790 * If the event is being injected as part of VM-entry, it is -not- subject to event
3791 * intercepts in the nested-guest. However, secondary exceptions that occur during
3792 * injection of any event -are- subject to event interception.
3793 *
3794 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3795 */
3796 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3797 {
3798 /*
3799 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3800 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3801 *
3802 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3803 */
3804 if ( uVector == X86_XCPT_NMI
3805 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3806 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3807 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3808 else
3809 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3810
3811 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3812 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3813 }
3814
3815 /*
3816 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3817 * If not, the caller will continue delivery of the external interrupt as it would
3818 * normally. The interrupt is no longer pending in the interrupt controller at this
3819 * point.
3820 */
3821 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3822 {
3823 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3824 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3825 }
3826
3827 /*
3828 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3829 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3830 * interrupts.
3831 */
3832 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3833 bool fIntercept;
3834 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3835 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3836 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3837 else
3838 {
3839 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3840 fIntercept = false;
3841 }
3842
3843 /*
3844 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3845 * relevant VM-exit information and cause the VM-exit.
3846 */
3847 if (fIntercept)
3848 {
3849 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3850
3851 /* Construct the rest of the event related information fields and cause the VM-exit. */
3852 uint64_t u64ExitQual;
3853 if (uVector == X86_XCPT_PF)
3854 {
3855 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3856 u64ExitQual = uCr2;
3857 }
3858 else if (uVector == X86_XCPT_DB)
3859 {
3860 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3861 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3862 }
3863 else
3864 u64ExitQual = 0;
3865
3866 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3867 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3868 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3869 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3870 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3871 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3872 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3873 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3874 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3875 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3876
3877 /*
3878 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3879 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3880 * length.
3881 */
3882 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3883 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3884 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3885 else
3886 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3887
3888 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3889 }
3890
3891 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3892}
3893
3894
3895/**
3896 * VMX VM-exit handler for EPT misconfiguration.
3897 *
3898 * @param pVCpu The cross context virtual CPU structure.
3899 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3900 * This need not be page aligned (e.g. nested-guest in real
3901 * mode).
3902 */
3903static VBOXSTRICTRC iemVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr) RT_NOEXCEPT
3904{
3905 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3906 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3907}
3908
3909
3910/**
3911 * VMX VM-exit handler for EPT misconfiguration.
3912 *
3913 * This is intended for EPT misconfigurations where the caller provides all the
3914 * relevant VM-exit information.
3915 *
3916 * @param pVCpu The cross context virtual CPU structure.
3917 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3918 * This need not be page aligned (e.g. nested-guest in real
3919 * mode).
3920 * @param pExitEventInfo Pointer to the VM-exit event information.
3921 */
3922static VBOXSTRICTRC iemVmxVmexitEptMisconfigWithInfo(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3923{
3924 Assert(pExitEventInfo);
3925 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3926 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3927 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3928 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3929 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3930}
3931
3932
3933/**
3934 * Interface for HM and EM to emulate a VM-exit due to an EPT misconfiguration.
3935 *
3936 * @returns Strict VBox status code.
3937 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3938 * @param GCPhysAddr The nested-guest physical address causing the EPT
3939 * misconfiguration.
3940 * @param pExitEventInfo Pointer to the VM-exit event information.
3941 * @thread EMT(pVCpu)
3942 */
3943VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo)
3944{
3945 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
3946
3947 iemInitExec(pVCpu, false /*fBypassHandlers*/);
3948 VBOXSTRICTRC rcStrict = iemVmxVmexitEptMisconfigWithInfo(pVCpu, GCPhysAddr, pExitEventInfo);
3949 Assert(!pVCpu->iem.s.cActiveMappings);
3950 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
3951}
3952
3953
3954/**
3955 * VMX VM-exit handler for EPT violation.
3956 *
3957 * @param pVCpu The cross context virtual CPU structure.
3958 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3959 * @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
3960 * @param fEptAccess The EPT paging structure bits.
3961 * @param GCPhysAddr The physical address causing the EPT violation. This
3962 * need not be page aligned (e.g. nested-guest in real
3963 * mode).
3964 * @param fIsLinearAddrValid Whether translation of a linear address caused this
3965 * EPT violation. If @c false, GCPtrAddr must be 0.
3966 * @param GCPtrAddr The linear address causing the EPT violation.
3967 * @param cbInstr The VM-exit instruction length.
3968 */
3969static VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail,
3970 uint64_t fEptAccess, RTGCPHYS GCPhysAddr, bool fIsLinearAddrValid,
3971 uint64_t GCPtrAddr, uint8_t cbInstr) RT_NOEXCEPT
3972{
3973 /*
3974 * If the linear address isn't valid (can happen when loading PDPTEs
3975 * as part of MOV CR execution) the linear address field is undefined.
3976 * While we can leave it this way, it's preferrable to zero it for consistency.
3977 */
3978 Assert(fIsLinearAddrValid || GCPtrAddr == 0);
3979
3980 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3981 bool const fSupportsAccessDirty = RT_BOOL(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
3982
3983 uint32_t const fDataRdMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_READ;
3984 uint32_t const fDataWrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_WRITE;
3985 uint32_t const fInstrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_EXEC;
3986 bool const fDataRead = ((fAccess & fDataRdMask) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3987 bool const fDataWrite = ((fAccess & fDataWrMask) == IEM_ACCESS_DATA_W) | fSupportsAccessDirty;
3988 bool const fInstrFetch = ((fAccess & fInstrMask) == IEM_ACCESS_INSTRUCTION);
3989 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3990 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3991 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3992 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3993 bool const fIsLinearToPhysAddr = fIsLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
3994
3995 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
3996 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
3997 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
3998 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
3999 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
4000 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
4001 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fIsLinearAddrValid)
4002 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fIsLinearToPhysAddr)
4003 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
4004
4005#ifdef VBOX_STRICT
4006 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
4007 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
4008 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
4009 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
4010 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
4011 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
4012#endif
4013
4014 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
4015 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
4016 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4017
4018 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
4019}
4020
4021
4022/**
4023 * VMX VM-exit handler for EPT violation.
4024 *
4025 * This is intended for EPT violations where the caller provides all the
4026 * relevant VM-exit information.
4027 *
4028 * @returns VBox strict status code.
4029 * @param pVCpu The cross context virtual CPU structure.
4030 * @param pExitInfo Pointer to the VM-exit information.
4031 * @param pExitEventInfo Pointer to the VM-exit event information.
4032 */
4033static VBOXSTRICTRC iemVmxVmexitEptViolationWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4034 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4035{
4036 Assert(pExitInfo);
4037 Assert(pExitEventInfo);
4038 Assert(pExitInfo->uReason == VMX_EXIT_EPT_VIOLATION);
4039 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4040
4041 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4042 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4043
4044 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
4045 if (pExitInfo->u64Qual & VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK)
4046 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
4047 else
4048 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, 0);
4049 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4050 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, pExitInfo->u64Qual);
4051}
4052
4053
4054/**
4055 * Interface for HM and EM to emulate a VM-exit due to an EPT violation.
4056 *
4057 * @returns Strict VBox status code.
4058 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4059 * @param pExitInfo Pointer to the VM-exit information.
4060 * @param pExitEventInfo Pointer to the VM-exit event information.
4061 * @thread EMT(pVCpu)
4062 */
4063VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4064 PCVMXVEXITEVENTINFO pExitEventInfo)
4065{
4066 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
4067
4068 iemInitExec(pVCpu, false /*fBypassHandlers*/);
4069 VBOXSTRICTRC rcStrict = iemVmxVmexitEptViolationWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4070 Assert(!pVCpu->iem.s.cActiveMappings);
4071 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
4072}
4073
4074
4075/**
4076 * VMX VM-exit handler for EPT-induced VM-exits.
4077 *
4078 * @param pVCpu The cross context virtual CPU structure.
4079 * @param pWalk The page walk info.
4080 * @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
4081 * @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
4082 * @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
4083 * applicable.
4084 */
4085VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT
4086{
4087 Assert(pWalk->fIsSlat);
4088 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
4089 Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
4090 Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
4091
4092 if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
4093 {
4094 LogFlow(("EptViolation: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4095 uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
4096 return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
4097 pWalk->GCPtr, cbInstr);
4098 }
4099
4100 LogFlow(("EptMisconfig: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4101 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
4102 return iemVmxVmexitEptMisconfig(pVCpu, pWalk->GCPhysNested);
4103}
4104
4105
4106/**
4107 * VMX VM-exit handler for APIC accesses.
4108 *
4109 * @param pVCpu The cross context virtual CPU structure.
4110 * @param offAccess The offset of the register being accessed.
4111 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4112 */
4113static VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess) RT_NOEXCEPT
4114{
4115 VMXAPICACCESS enmAccess;
4116 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4117 if (fInEventDelivery)
4118 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4119 else if ((fAccess & (IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_MASK)) == IEM_ACCESS_INSTRUCTION)
4120 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4121 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4122 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4123 else
4124 enmAccess = VMXAPICACCESS_LINEAR_READ;
4125
4126 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4127 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4128 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4129}
4130
4131
4132/**
4133 * VMX VM-exit handler for APIC accesses.
4134 *
4135 * This is intended for APIC accesses where the caller provides all the
4136 * relevant VM-exit information.
4137 *
4138 * @returns VBox strict status code.
4139 * @param pVCpu The cross context virtual CPU structure.
4140 * @param pExitInfo Pointer to the VM-exit information.
4141 * @param pExitEventInfo Pointer to the VM-exit event information.
4142 */
4143static VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4144 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4145{
4146 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4147 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4148 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
4149 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4150 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4151 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4152 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4153 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4154 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4155}
4156
4157
4158/**
4159 * Interface for HM and EM to virtualize memory-mapped APIC accesses.
4160 *
4161 * @returns Strict VBox status code.
4162 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the memory access was virtualized.
4163 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4164 *
4165 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4166 * @param pExitInfo Pointer to the VM-exit information.
4167 * @param pExitEventInfo Pointer to the VM-exit event information.
4168 * @thread EMT(pVCpu)
4169 */
4170VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
4171{
4172 Assert(pExitInfo);
4173 Assert(pExitEventInfo);
4174 VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4175 Assert(!pVCpu->iem.s.cActiveMappings);
4176 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4177}
4178
4179
4180/**
4181 * VMX VM-exit handler for APIC-write VM-exits.
4182 *
4183 * @param pVCpu The cross context virtual CPU structure.
4184 * @param offApic The write to the virtual-APIC page offset that caused this
4185 * VM-exit.
4186 */
4187static VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic) RT_NOEXCEPT
4188{
4189 Assert(offApic < XAPIC_OFF_END + 4);
4190 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4191 offApic &= UINT16_C(0xfff);
4192 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4193}
4194
4195
4196/**
4197 * Clears any pending virtual-APIC write emulation.
4198 *
4199 * @returns The virtual-APIC offset that was written before clearing it.
4200 * @param pVCpu The cross context virtual CPU structure.
4201 */
4202DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
4203{
4204 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4205 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4206 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4207 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4208 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4209 return offVirtApicWrite;
4210}
4211
4212
4213/**
4214 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4215 *
4216 * @returns The register from the virtual-APIC page.
4217 * @param pVCpu The cross context virtual CPU structure.
4218 * @param offReg The offset of the register being read.
4219 */
4220uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4221{
4222 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4223
4224 uint32_t uReg = 0;
4225 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4226 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4227 AssertMsgStmt(RT_SUCCESS(rc),
4228 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4229 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4230 uReg = 0);
4231 return uReg;
4232}
4233
4234
4235/**
4236 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4237 *
4238 * @returns The register from the virtual-APIC page.
4239 * @param pVCpu The cross context virtual CPU structure.
4240 * @param offReg The offset of the register being read.
4241 */
4242static uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4243{
4244 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4245
4246 uint64_t uReg = 0;
4247 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4248 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4249 AssertMsgStmt(RT_SUCCESS(rc),
4250 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4251 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4252 uReg = 0);
4253 return uReg;
4254}
4255
4256
4257/**
4258 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4259 *
4260 * @param pVCpu The cross context virtual CPU structure.
4261 * @param offReg The offset of the register being written.
4262 * @param uReg The register value to write.
4263 */
4264void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT
4265{
4266 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4267
4268 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4269 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4270 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4271 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4272}
4273
4274
4275/**
4276 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4277 *
4278 * @param pVCpu The cross context virtual CPU structure.
4279 * @param offReg The offset of the register being written.
4280 * @param uReg The register value to write.
4281 */
4282static void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg) RT_NOEXCEPT
4283{
4284 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4285
4286 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4287 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4288 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4289 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4290}
4291
4292
4293/**
4294 * Sets the vector in a virtual-APIC 256-bit sparse register.
4295 *
4296 * @param pVCpu The cross context virtual CPU structure.
4297 * @param offReg The offset of the 256-bit spare register.
4298 * @param uVector The vector to set.
4299 *
4300 * @remarks This is based on our APIC device code.
4301 */
4302static void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4303{
4304 /* Determine the vector offset within the chunk. */
4305 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4306
4307 /* Read the chunk at the offset. */
4308 uint32_t uReg;
4309 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4310 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4311 if (RT_SUCCESS(rc))
4312 {
4313 /* Modify the chunk. */
4314 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4315 uReg |= RT_BIT(idxVectorBit);
4316
4317 /* Write the chunk. */
4318 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4319 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4320 uVector, offReg, GCPhysVirtApic, rc));
4321 }
4322 else
4323 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4324 uVector, offReg, GCPhysVirtApic, rc));
4325}
4326
4327
4328/**
4329 * Clears the vector in a virtual-APIC 256-bit sparse register.
4330 *
4331 * @param pVCpu The cross context virtual CPU structure.
4332 * @param offReg The offset of the 256-bit spare register.
4333 * @param uVector The vector to clear.
4334 *
4335 * @remarks This is based on our APIC device code.
4336 */
4337static void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4338{
4339 /* Determine the vector offset within the chunk. */
4340 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4341
4342 /* Read the chunk at the offset. */
4343 uint32_t uReg;
4344 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4345 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4346 if (RT_SUCCESS(rc))
4347 {
4348 /* Modify the chunk. */
4349 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4350 uReg &= ~RT_BIT(idxVectorBit);
4351
4352 /* Write the chunk. */
4353 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4354 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4355 uVector, offReg, GCPhysVirtApic, rc));
4356 }
4357 else
4358 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4359 uVector, offReg, GCPhysVirtApic, rc));
4360}
4361
4362
4363/**
4364 * Checks if a memory access to the APIC-access page must causes an APIC-access
4365 * VM-exit.
4366 *
4367 * @param pVCpu The cross context virtual CPU structure.
4368 * @param offAccess The offset of the register being accessed.
4369 * @param cbAccess The size of the access in bytes.
4370 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4371 *
4372 * @remarks This must not be used for MSR-based APIC-access page accesses!
4373 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4374 */
4375static bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4376{
4377 Assert(cbAccess > 0);
4378 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4379
4380 /*
4381 * We must cause a VM-exit if any of the following are true:
4382 * - TPR shadowing isn't active.
4383 * - The access size exceeds 32-bits.
4384 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4385 *
4386 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4387 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4388 */
4389 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4390 || cbAccess > sizeof(uint32_t)
4391 || ((offAccess + cbAccess - 1) & 0xc)
4392 || offAccess >= XAPIC_OFF_END + 4)
4393 return true;
4394
4395 /*
4396 * If the access is part of an operation where we have already
4397 * virtualized a virtual-APIC write, we must cause a VM-exit.
4398 */
4399 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4400 return true;
4401
4402 /*
4403 * Check write accesses to the APIC-access page that cause VM-exits.
4404 */
4405 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4406 {
4407 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4408 {
4409 /*
4410 * With APIC-register virtualization, a write access to any of the
4411 * following registers are virtualized. Accessing any other register
4412 * causes a VM-exit.
4413 */
4414 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4415 switch (offAlignedAccess)
4416 {
4417 case XAPIC_OFF_ID:
4418 case XAPIC_OFF_TPR:
4419 case XAPIC_OFF_EOI:
4420 case XAPIC_OFF_LDR:
4421 case XAPIC_OFF_DFR:
4422 case XAPIC_OFF_SVR:
4423 case XAPIC_OFF_ESR:
4424 case XAPIC_OFF_ICR_LO:
4425 case XAPIC_OFF_ICR_HI:
4426 case XAPIC_OFF_LVT_TIMER:
4427 case XAPIC_OFF_LVT_THERMAL:
4428 case XAPIC_OFF_LVT_PERF:
4429 case XAPIC_OFF_LVT_LINT0:
4430 case XAPIC_OFF_LVT_LINT1:
4431 case XAPIC_OFF_LVT_ERROR:
4432 case XAPIC_OFF_TIMER_ICR:
4433 case XAPIC_OFF_TIMER_DCR:
4434 break;
4435 default:
4436 return true;
4437 }
4438 }
4439 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4440 {
4441 /*
4442 * With virtual-interrupt delivery, a write access to any of the
4443 * following registers are virtualized. Accessing any other register
4444 * causes a VM-exit.
4445 *
4446 * Note! The specification does not allow writing to offsets in-between
4447 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4448 */
4449 switch (offAccess)
4450 {
4451 case XAPIC_OFF_TPR:
4452 case XAPIC_OFF_EOI:
4453 case XAPIC_OFF_ICR_LO:
4454 break;
4455 default:
4456 return true;
4457 }
4458 }
4459 else
4460 {
4461 /*
4462 * Without APIC-register virtualization or virtual-interrupt delivery,
4463 * only TPR accesses are virtualized.
4464 */
4465 if (offAccess == XAPIC_OFF_TPR)
4466 { /* likely */ }
4467 else
4468 return true;
4469 }
4470 }
4471 else
4472 {
4473 /*
4474 * Check read accesses to the APIC-access page that cause VM-exits.
4475 */
4476 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4477 {
4478 /*
4479 * With APIC-register virtualization, a read access to any of the
4480 * following registers are virtualized. Accessing any other register
4481 * causes a VM-exit.
4482 */
4483 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4484 switch (offAlignedAccess)
4485 {
4486 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4487 case XAPIC_OFF_ID:
4488 case XAPIC_OFF_VERSION:
4489 case XAPIC_OFF_TPR:
4490 case XAPIC_OFF_EOI:
4491 case XAPIC_OFF_LDR:
4492 case XAPIC_OFF_DFR:
4493 case XAPIC_OFF_SVR:
4494 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4495 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4496 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4497 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4498 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4499 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4500 case XAPIC_OFF_ESR:
4501 case XAPIC_OFF_ICR_LO:
4502 case XAPIC_OFF_ICR_HI:
4503 case XAPIC_OFF_LVT_TIMER:
4504 case XAPIC_OFF_LVT_THERMAL:
4505 case XAPIC_OFF_LVT_PERF:
4506 case XAPIC_OFF_LVT_LINT0:
4507 case XAPIC_OFF_LVT_LINT1:
4508 case XAPIC_OFF_LVT_ERROR:
4509 case XAPIC_OFF_TIMER_ICR:
4510 case XAPIC_OFF_TIMER_DCR:
4511 break;
4512 default:
4513 return true;
4514 }
4515 }
4516 else
4517 {
4518 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4519 if (offAccess == XAPIC_OFF_TPR)
4520 { /* likely */ }
4521 else
4522 return true;
4523 }
4524 }
4525
4526 /* The APIC access is virtualized, does not cause a VM-exit. */
4527 return false;
4528}
4529
4530
4531/**
4532 * Virtualizes a memory-based APIC access by certain instructions even though they
4533 * do not use the address to access memory.
4534 *
4535 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4536 * page-faults but do not use the address to access memory.
4537 *
4538 * @param pVCpu The cross context virtual CPU structure.
4539 * @param pGCPhysAccess Pointer to the guest-physical address accessed.
4540 * @param cbAccess The size of the access in bytes.
4541 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4542 */
4543VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4544{
4545 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4546 Assert(pGCPhysAccess);
4547
4548 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
4549 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4550 Assert(!(GCPhysApic & GUEST_PAGE_OFFSET_MASK));
4551
4552 if (GCPhysAccess == GCPhysApic)
4553 {
4554 uint16_t const offAccess = *pGCPhysAccess & GUEST_PAGE_OFFSET_MASK;
4555 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4556 if (fIntercept)
4557 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4558
4559 *pGCPhysAccess = GCPhysApic | offAccess;
4560 return VINF_VMX_MODIFIES_BEHAVIOR;
4561 }
4562
4563 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4564}
4565
4566
4567/**
4568 * Virtualizes a memory-based APIC access.
4569 *
4570 * @returns VBox strict status code.
4571 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4572 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4573 *
4574 * @param pVCpu The cross context virtual CPU structure.
4575 * @param offAccess The offset of the register being accessed (within the
4576 * APIC-access page).
4577 * @param cbAccess The size of the access in bytes.
4578 * @param pvData Pointer to the data being written or where to store the data
4579 * being read.
4580 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4581 */
4582static VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess,
4583 void *pvData, uint32_t fAccess) RT_NOEXCEPT
4584{
4585 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4586 Assert(pvData);
4587
4588 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4589 if (fIntercept)
4590 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4591
4592 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4593 {
4594 /*
4595 * A write access to the APIC-access page that is virtualized (rather than
4596 * causing a VM-exit) writes data to the virtual-APIC page.
4597 */
4598 uint32_t const u32Data = *(uint32_t *)pvData;
4599 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4600
4601 /*
4602 * Record the currently updated APIC offset, as we need this later for figuring
4603 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4604 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4605 *
4606 * After completion of the current operation, we need to perform TPR virtualization,
4607 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4608 *
4609 * The current operation may be a REP-prefixed string instruction, execution of any
4610 * other instruction, or delivery of an event through the IDT.
4611 *
4612 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4613 * performed now but later after completion of the current operation.
4614 *
4615 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4616 */
4617 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4618
4619 LogFlowFunc(("Write access at offset %#x not intercepted -> Wrote %#RX32\n", offAccess, u32Data));
4620 }
4621 else
4622 {
4623 /*
4624 * A read access from the APIC-access page that is virtualized (rather than
4625 * causing a VM-exit) returns data from the virtual-APIC page.
4626 *
4627 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4628 */
4629 Assert(fAccess & IEM_ACCESS_TYPE_READ);
4630
4631 Assert(cbAccess <= 4);
4632 Assert(offAccess < XAPIC_OFF_END + 4);
4633 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4634
4635 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4636 u32Data &= s_auAccessSizeMasks[cbAccess];
4637 *(uint32_t *)pvData = u32Data;
4638
4639 LogFlowFunc(("Read access at offset %#x not intercepted -> Read %#RX32\n", offAccess, u32Data));
4640 }
4641
4642 return VINF_VMX_MODIFIES_BEHAVIOR;
4643}
4644
4645
4646/**
4647 * Virtualizes an MSR-based APIC read access.
4648 *
4649 * @returns VBox strict status code.
4650 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4651 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4652 * handled by the x2APIC device.
4653 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4654 * not within the range of valid MSRs, caller must raise \#GP(0).
4655 * @param pVCpu The cross context virtual CPU structure.
4656 * @param idMsr The x2APIC MSR being read.
4657 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4658 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4659 */
4660static VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value) RT_NOEXCEPT
4661{
4662 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4663 Assert(pu64Value);
4664
4665 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4666 {
4667 if ( idMsr >= MSR_IA32_X2APIC_START
4668 && idMsr <= MSR_IA32_X2APIC_END)
4669 {
4670 uint16_t const offReg = (idMsr & 0xff) << 4;
4671 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4672 *pu64Value = u64Value;
4673 return VINF_VMX_MODIFIES_BEHAVIOR;
4674 }
4675 return VERR_OUT_OF_RANGE;
4676 }
4677
4678 if (idMsr == MSR_IA32_X2APIC_TPR)
4679 {
4680 uint16_t const offReg = (idMsr & 0xff) << 4;
4681 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4682 *pu64Value = u64Value;
4683 return VINF_VMX_MODIFIES_BEHAVIOR;
4684 }
4685
4686 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4687}
4688
4689
4690/**
4691 * Virtualizes an MSR-based APIC write access.
4692 *
4693 * @returns VBox strict status code.
4694 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4695 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4696 * not within the range of valid MSRs, caller must raise \#GP(0).
4697 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4698 *
4699 * @param pVCpu The cross context virtual CPU structure.
4700 * @param idMsr The x2APIC MSR being written.
4701 * @param u64Value The value of the x2APIC MSR being written.
4702 */
4703static VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value) RT_NOEXCEPT
4704{
4705 /*
4706 * Check if the access is to be virtualized.
4707 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4708 */
4709 if ( idMsr == MSR_IA32_X2APIC_TPR
4710 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4711 && ( idMsr == MSR_IA32_X2APIC_EOI
4712 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4713 {
4714 /* Validate the MSR write depending on the register. */
4715 switch (idMsr)
4716 {
4717 case MSR_IA32_X2APIC_TPR:
4718 case MSR_IA32_X2APIC_SELF_IPI:
4719 {
4720 if (u64Value & UINT64_C(0xffffffffffffff00))
4721 return VERR_OUT_OF_RANGE;
4722 break;
4723 }
4724 case MSR_IA32_X2APIC_EOI:
4725 {
4726 if (u64Value != 0)
4727 return VERR_OUT_OF_RANGE;
4728 break;
4729 }
4730 }
4731
4732 /* Write the MSR to the virtual-APIC page. */
4733 uint16_t const offReg = (idMsr & 0xff) << 4;
4734 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4735
4736 /*
4737 * Record the currently updated APIC offset, as we need this later for figuring
4738 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4739 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4740 */
4741 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4742
4743 return VINF_VMX_MODIFIES_BEHAVIOR;
4744 }
4745
4746 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4747}
4748
4749
4750/**
4751 * Interface for HM and EM to virtualize x2APIC MSR accesses.
4752 *
4753 * @returns Strict VBox status code.
4754 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR access was virtualized.
4755 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR access must be handled by
4756 * the x2APIC device.
4757 * @retval VERR_OUT_RANGE if the caller must raise \#GP(0).
4758 *
4759 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4760 * @param idMsr The MSR being read.
4761 * @param pu64Value Pointer to the value being written or where to store the
4762 * value being read.
4763 * @param fWrite Whether this is an MSR write or read access.
4764 * @thread EMT(pVCpu)
4765 */
4766VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value, bool fWrite)
4767{
4768 Assert(pu64Value);
4769
4770 VBOXSTRICTRC rcStrict;
4771 if (fWrite)
4772 rcStrict = iemVmxVirtApicAccessMsrWrite(pVCpu, idMsr, *pu64Value);
4773 else
4774 rcStrict = iemVmxVirtApicAccessMsrRead(pVCpu, idMsr, pu64Value);
4775 Assert(!pVCpu->iem.s.cActiveMappings);
4776 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4777
4778}
4779
4780
4781/**
4782 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4783 *
4784 * @returns VBox status code.
4785 * @retval VINF_SUCCESS when the highest set bit is found.
4786 * @retval VERR_NOT_FOUND when no bit is set.
4787 *
4788 * @param pVCpu The cross context virtual CPU structure.
4789 * @param offReg The offset of the APIC 256-bit sparse register.
4790 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4791 * set in the register. Only valid when VINF_SUCCESS is
4792 * returned.
4793 *
4794 * @remarks The format of the 256-bit sparse register here mirrors that found in
4795 * real APIC hardware.
4796 */
4797static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4798{
4799 Assert(offReg < XAPIC_OFF_END + 4);
4800 Assert(pidxHighestBit);
4801
4802 /*
4803 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4804 * However, in each fragment only the first 4 bytes are used.
4805 */
4806 uint8_t const cFrags = 8;
4807 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4808 {
4809 uint16_t const offFrag = iFrag * 16;
4810 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4811 if (!u32Frag)
4812 continue;
4813
4814 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4815 Assert(idxHighestBit > 0);
4816 --idxHighestBit;
4817 Assert(idxHighestBit <= UINT8_MAX);
4818 *pidxHighestBit = idxHighestBit;
4819 return VINF_SUCCESS;
4820 }
4821 return VERR_NOT_FOUND;
4822}
4823
4824
4825/**
4826 * Evaluates pending virtual interrupts.
4827 *
4828 * @param pVCpu The cross context virtual CPU structure.
4829 */
4830static void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu) RT_NOEXCEPT
4831{
4832 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4833
4834 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4835 {
4836 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4837 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4838
4839 if ((uRvi >> 4) > (uPpr >> 4))
4840 {
4841 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4842 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4843 }
4844 else
4845 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4846 }
4847}
4848
4849
4850/**
4851 * Performs PPR virtualization.
4852 *
4853 * @returns VBox strict status code.
4854 * @param pVCpu The cross context virtual CPU structure.
4855 */
4856static void iemVmxPprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4857{
4858 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4859 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4860
4861 /*
4862 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4863 * or EOI-virtualization.
4864 *
4865 * See Intel spec. 29.1.3 "PPR Virtualization".
4866 */
4867 uint8_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4868 uint8_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus) & 0xf0;
4869
4870 uint32_t uPpr;
4871 if ((uTpr & 0xf0) >= uSvi)
4872 uPpr = uTpr;
4873 else
4874 uPpr = uSvi;
4875
4876 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4877 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4878}
4879
4880
4881/**
4882 * Performs VMX TPR virtualization.
4883 *
4884 * @returns VBox strict status code.
4885 * @param pVCpu The cross context virtual CPU structure.
4886 */
4887static VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4888{
4889 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4890
4891 /*
4892 * We should have already performed the virtual-APIC write to the TPR offset
4893 * in the virtual-APIC page. We now perform TPR virtualization.
4894 *
4895 * See Intel spec. 29.1.2 "TPR Virtualization".
4896 */
4897 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4898 {
4899 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4900 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4901
4902 /*
4903 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4904 * See Intel spec. 29.1.2 "TPR Virtualization".
4905 */
4906 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4907 {
4908 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4909 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4910 }
4911 }
4912 else
4913 {
4914 iemVmxPprVirtualization(pVCpu);
4915 iemVmxEvalPendingVirtIntrs(pVCpu);
4916 }
4917
4918 return VINF_SUCCESS;
4919}
4920
4921
4922/**
4923 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4924 * not.
4925 *
4926 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4927 * @param pVCpu The cross context virtual CPU structure.
4928 * @param uVector The interrupt that was acknowledged using an EOI.
4929 */
4930static bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector) RT_NOEXCEPT
4931{
4932 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4933 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4934
4935 if (uVector < 64)
4936 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4937 if (uVector < 128)
4938 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4939 if (uVector < 192)
4940 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4941 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4942}
4943
4944
4945/**
4946 * Performs EOI virtualization.
4947 *
4948 * @returns VBox strict status code.
4949 * @param pVCpu The cross context virtual CPU structure.
4950 */
4951static VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4952{
4953 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4954 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4955
4956 /*
4957 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4958 * and get the next guest-interrupt that's in-service (if any).
4959 *
4960 * See Intel spec. 29.1.4 "EOI Virtualization".
4961 */
4962 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4963 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4964 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4965
4966 uint8_t uVector = uSvi;
4967 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4968
4969 uVector = 0;
4970 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4971
4972 if (uVector)
4973 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4974 else
4975 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4976
4977 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4978 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4979
4980 iemVmxPprVirtualization(pVCpu);
4981 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4982 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4983 iemVmxEvalPendingVirtIntrs(pVCpu);
4984 return VINF_SUCCESS;
4985}
4986
4987
4988/**
4989 * Performs self-IPI virtualization.
4990 *
4991 * @returns VBox strict status code.
4992 * @param pVCpu The cross context virtual CPU structure.
4993 */
4994static VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4995{
4996 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4997 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4998
4999 /*
5000 * We should have already performed the virtual-APIC write to the self-IPI offset
5001 * in the virtual-APIC page. We now perform self-IPI virtualization.
5002 *
5003 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5004 */
5005 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5006 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5007 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5008 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5009 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5010 if (uVector > uRvi)
5011 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5012 iemVmxEvalPendingVirtIntrs(pVCpu);
5013 return VINF_SUCCESS;
5014}
5015
5016
5017/**
5018 * Performs VMX APIC-write emulation.
5019 *
5020 * @returns VBox strict status code.
5021 * @param pVCpu The cross context virtual CPU structure.
5022 */
5023VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT
5024{
5025 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5026
5027 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5028 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5029
5030 /*
5031 * Perform APIC-write emulation based on the virtual-APIC register written.
5032 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5033 */
5034 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5035 VBOXSTRICTRC rcStrict;
5036 switch (offApicWrite)
5037 {
5038 case XAPIC_OFF_TPR:
5039 {
5040 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5041 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5042 uTpr &= UINT32_C(0x000000ff);
5043 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5044 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5045 rcStrict = iemVmxTprVirtualization(pVCpu);
5046 break;
5047 }
5048
5049 case XAPIC_OFF_EOI:
5050 {
5051 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5052 {
5053 /* Clear VEOI and perform EOI virtualization. */
5054 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5055 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5056 rcStrict = iemVmxEoiVirtualization(pVCpu);
5057 }
5058 else
5059 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5060 break;
5061 }
5062
5063 case XAPIC_OFF_ICR_LO:
5064 {
5065 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5066 {
5067 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5068 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5069 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5070 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5071 if ( !(uIcrLo & fIcrLoMb0)
5072 && (uIcrLo & fIcrLoMb1))
5073 {
5074 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5075 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5076 }
5077 else
5078 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5079 }
5080 else
5081 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5082 break;
5083 }
5084
5085 case XAPIC_OFF_ICR_HI:
5086 {
5087 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5088 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5089 uIcrHi &= UINT32_C(0xff000000);
5090 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5091 rcStrict = VINF_SUCCESS;
5092 break;
5093 }
5094
5095 default:
5096 {
5097 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5098 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5099 break;
5100 }
5101 }
5102
5103 return rcStrict;
5104}
5105
5106
5107/**
5108 * Interface for HM and EM to perform an APIC-write emulation which may cause a
5109 * VM-exit.
5110 *
5111 * @returns Strict VBox status code.
5112 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
5113 * @thread EMT(pVCpu)
5114 */
5115VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu)
5116{
5117 VBOXSTRICTRC rcStrict = iemVmxApicWriteEmulation(pVCpu);
5118 Assert(!pVCpu->iem.s.cActiveMappings);
5119 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
5120}
5121
5122
5123/**
5124 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5125 *
5126 * @param pVCpu The cross context virtual CPU structure.
5127 * @param pszInstr The VMX instruction name (for logging purposes).
5128 */
5129DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
5130{
5131 /*
5132 * Guest Control Registers, Debug Registers, and MSRs.
5133 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5134 */
5135 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5136 const char * const pszFailure = "VM-exit";
5137 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5138
5139 /* CR0 reserved bits. */
5140 {
5141 /* CR0 MB1 bits. */
5142 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
5143 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5144 { /* likely */ }
5145 else
5146 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5147
5148 /* CR0 MBZ bits. */
5149 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5150 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5151 { /* likely */ }
5152 else
5153 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5154
5155 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5156 if ( !fUnrestrictedGuest
5157 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5158 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5159 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5160 }
5161
5162 /* CR4 reserved bits. */
5163 {
5164 /* CR4 MB1 bits. */
5165 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5166 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5167 { /* likely */ }
5168 else
5169 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5170
5171 /* CR4 MBZ bits. */
5172 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5173 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5174 { /* likely */ }
5175 else
5176 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5177 }
5178
5179 /* DEBUGCTL MSR. */
5180 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5181 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5182 { /* likely */ }
5183 else
5184 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5185
5186 /* 64-bit CPU checks. */
5187 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5188 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5189 {
5190 if (fGstInLongMode)
5191 {
5192 /* PAE must be set. */
5193 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5194 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5195 { /* likely */ }
5196 else
5197 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5198 }
5199 else
5200 {
5201 /* PCIDE should not be set. */
5202 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5203 { /* likely */ }
5204 else
5205 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5206 }
5207
5208 /* CR3. */
5209 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5210 { /* likely */ }
5211 else
5212 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5213
5214 /* DR7. */
5215 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5216 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5217 { /* likely */ }
5218 else
5219 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5220
5221 /* SYSENTER ESP and SYSENTER EIP. */
5222 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5223 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5224 { /* likely */ }
5225 else
5226 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5227 }
5228
5229 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5230 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5231
5232 /* PAT MSR. */
5233 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5234 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5235 { /* likely */ }
5236 else
5237 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5238
5239 /* EFER MSR. */
5240 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5241 {
5242 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5243 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5244 { /* likely */ }
5245 else
5246 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5247
5248 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5249 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5250 if ( fGstLma == fGstInLongMode
5251 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5252 || fGstLma == fGstLme))
5253 { /* likely */ }
5254 else
5255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5256 }
5257
5258 /* We don't support IA32_BNDCFGS MSR yet. */
5259 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5260
5261 NOREF(pszInstr);
5262 NOREF(pszFailure);
5263 return VINF_SUCCESS;
5264}
5265
5266
5267/**
5268 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5269 *
5270 * @param pVCpu The cross context virtual CPU structure.
5271 * @param pszInstr The VMX instruction name (for logging purposes).
5272 */
5273DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
5274{
5275 /*
5276 * Segment registers.
5277 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5278 */
5279 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5280 const char * const pszFailure = "VM-exit";
5281 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5282 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5283 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5284
5285 /* Selectors. */
5286 if ( !fGstInV86Mode
5287 && !fUnrestrictedGuest
5288 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5289 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5290
5291 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5292 {
5293 CPUMSELREG SelReg;
5294 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5295 if (RT_LIKELY(rc == VINF_SUCCESS))
5296 { /* likely */ }
5297 else
5298 return rc;
5299
5300 /*
5301 * Virtual-8086 mode checks.
5302 */
5303 if (fGstInV86Mode)
5304 {
5305 /* Base address. */
5306 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5307 { /* likely */ }
5308 else
5309 {
5310 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5311 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5312 }
5313
5314 /* Limit. */
5315 if (SelReg.u32Limit == 0xffff)
5316 { /* likely */ }
5317 else
5318 {
5319 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5320 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5321 }
5322
5323 /* Attribute. */
5324 if (SelReg.Attr.u == 0xf3)
5325 { /* likely */ }
5326 else
5327 {
5328 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5329 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5330 }
5331
5332 /* We're done; move to checking the next segment. */
5333 continue;
5334 }
5335
5336 /* Checks done by 64-bit CPUs. */
5337 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5338 {
5339 /* Base address. */
5340 if ( iSegReg == X86_SREG_FS
5341 || iSegReg == X86_SREG_GS)
5342 {
5343 if (X86_IS_CANONICAL(SelReg.u64Base))
5344 { /* likely */ }
5345 else
5346 {
5347 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5348 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5349 }
5350 }
5351 else if (iSegReg == X86_SREG_CS)
5352 {
5353 if (!RT_HI_U32(SelReg.u64Base))
5354 { /* likely */ }
5355 else
5356 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5357 }
5358 else
5359 {
5360 if ( SelReg.Attr.n.u1Unusable
5361 || !RT_HI_U32(SelReg.u64Base))
5362 { /* likely */ }
5363 else
5364 {
5365 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5366 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5367 }
5368 }
5369 }
5370
5371 /*
5372 * Checks outside Virtual-8086 mode.
5373 */
5374 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5375 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5376 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5377 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5378 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5379 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5380 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5381 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5382
5383 /* Code or usable segment. */
5384 if ( iSegReg == X86_SREG_CS
5385 || fUsable)
5386 {
5387 /* Reserved bits (bits 31:17 and bits 11:8). */
5388 if (!(SelReg.Attr.u & 0xfffe0f00))
5389 { /* likely */ }
5390 else
5391 {
5392 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5393 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5394 }
5395
5396 /* Descriptor type. */
5397 if (fCodeDataSeg)
5398 { /* likely */ }
5399 else
5400 {
5401 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5402 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5403 }
5404
5405 /* Present. */
5406 if (fPresent)
5407 { /* likely */ }
5408 else
5409 {
5410 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5411 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5412 }
5413
5414 /* Granularity. */
5415 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5416 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5417 { /* likely */ }
5418 else
5419 {
5420 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5421 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5422 }
5423 }
5424
5425 if (iSegReg == X86_SREG_CS)
5426 {
5427 /* Segment Type and DPL. */
5428 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5429 && fUnrestrictedGuest)
5430 {
5431 if (uDpl == 0)
5432 { /* likely */ }
5433 else
5434 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5435 }
5436 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5437 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5438 {
5439 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5440 if (uDpl == AttrSs.n.u2Dpl)
5441 { /* likely */ }
5442 else
5443 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5444 }
5445 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5446 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5447 {
5448 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5449 if (uDpl <= AttrSs.n.u2Dpl)
5450 { /* likely */ }
5451 else
5452 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5453 }
5454 else
5455 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5456
5457 /* Def/Big. */
5458 if ( fGstInLongMode
5459 && fSegLong)
5460 {
5461 if (uDefBig == 0)
5462 { /* likely */ }
5463 else
5464 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5465 }
5466 }
5467 else if (iSegReg == X86_SREG_SS)
5468 {
5469 /* Segment Type. */
5470 if ( !fUsable
5471 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5472 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5473 { /* likely */ }
5474 else
5475 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5476
5477 /* DPL. */
5478 if (!fUnrestrictedGuest)
5479 {
5480 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5481 { /* likely */ }
5482 else
5483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5484 }
5485 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5486 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5487 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5488 {
5489 if (uDpl == 0)
5490 { /* likely */ }
5491 else
5492 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5493 }
5494 }
5495 else
5496 {
5497 /* DS, ES, FS, GS. */
5498 if (fUsable)
5499 {
5500 /* Segment type. */
5501 if (uSegType & X86_SEL_TYPE_ACCESSED)
5502 { /* likely */ }
5503 else
5504 {
5505 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5506 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5507 }
5508
5509 if ( !(uSegType & X86_SEL_TYPE_CODE)
5510 || (uSegType & X86_SEL_TYPE_READ))
5511 { /* likely */ }
5512 else
5513 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5514
5515 /* DPL. */
5516 if ( !fUnrestrictedGuest
5517 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5518 {
5519 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5520 { /* likely */ }
5521 else
5522 {
5523 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5524 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5525 }
5526 }
5527 }
5528 }
5529 }
5530
5531 /*
5532 * LDTR.
5533 */
5534 {
5535 CPUMSELREG Ldtr;
5536 Ldtr.Sel = pVmcs->GuestLdtr;
5537 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5538 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5539 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5540
5541 if (!Ldtr.Attr.n.u1Unusable)
5542 {
5543 /* Selector. */
5544 if (!(Ldtr.Sel & X86_SEL_LDT))
5545 { /* likely */ }
5546 else
5547 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5548
5549 /* Base. */
5550 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5551 {
5552 if (X86_IS_CANONICAL(Ldtr.u64Base))
5553 { /* likely */ }
5554 else
5555 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5556 }
5557
5558 /* Attributes. */
5559 /* Reserved bits (bits 31:17 and bits 11:8). */
5560 if (!(Ldtr.Attr.u & 0xfffe0f00))
5561 { /* likely */ }
5562 else
5563 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5564
5565 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5566 { /* likely */ }
5567 else
5568 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5569
5570 if (!Ldtr.Attr.n.u1DescType)
5571 { /* likely */ }
5572 else
5573 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5574
5575 if (Ldtr.Attr.n.u1Present)
5576 { /* likely */ }
5577 else
5578 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5579
5580 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5581 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5582 { /* likely */ }
5583 else
5584 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5585 }
5586 }
5587
5588 /*
5589 * TR.
5590 */
5591 {
5592 CPUMSELREG Tr;
5593 Tr.Sel = pVmcs->GuestTr;
5594 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5595 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5596 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5597
5598 /* Selector. */
5599 if (!(Tr.Sel & X86_SEL_LDT))
5600 { /* likely */ }
5601 else
5602 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5603
5604 /* Base. */
5605 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5606 {
5607 if (X86_IS_CANONICAL(Tr.u64Base))
5608 { /* likely */ }
5609 else
5610 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5611 }
5612
5613 /* Attributes. */
5614 /* Reserved bits (bits 31:17 and bits 11:8). */
5615 if (!(Tr.Attr.u & 0xfffe0f00))
5616 { /* likely */ }
5617 else
5618 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5619
5620 if (!Tr.Attr.n.u1Unusable)
5621 { /* likely */ }
5622 else
5623 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5624
5625 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5626 || ( !fGstInLongMode
5627 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5628 { /* likely */ }
5629 else
5630 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5631
5632 if (!Tr.Attr.n.u1DescType)
5633 { /* likely */ }
5634 else
5635 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5636
5637 if (Tr.Attr.n.u1Present)
5638 { /* likely */ }
5639 else
5640 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5641
5642 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5643 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5644 { /* likely */ }
5645 else
5646 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5647 }
5648
5649 NOREF(pszInstr);
5650 NOREF(pszFailure);
5651 return VINF_SUCCESS;
5652}
5653
5654
5655/**
5656 * Checks guest GDTR and IDTR as part of VM-entry.
5657 *
5658 * @param pVCpu The cross context virtual CPU structure.
5659 * @param pszInstr The VMX instruction name (for logging purposes).
5660 */
5661DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5662{
5663 /*
5664 * GDTR and IDTR.
5665 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5666 */
5667 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5668 const char *const pszFailure = "VM-exit";
5669
5670 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5671 {
5672 /* Base. */
5673 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5674 { /* likely */ }
5675 else
5676 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5677
5678 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5679 { /* likely */ }
5680 else
5681 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5682 }
5683
5684 /* Limit. */
5685 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5686 { /* likely */ }
5687 else
5688 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5689
5690 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5691 { /* likely */ }
5692 else
5693 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5694
5695 NOREF(pszInstr);
5696 NOREF(pszFailure);
5697 return VINF_SUCCESS;
5698}
5699
5700
5701/**
5702 * Checks guest RIP and RFLAGS as part of VM-entry.
5703 *
5704 * @param pVCpu The cross context virtual CPU structure.
5705 * @param pszInstr The VMX instruction name (for logging purposes).
5706 */
5707DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5708{
5709 /*
5710 * RIP and RFLAGS.
5711 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5712 */
5713 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5714 const char *const pszFailure = "VM-exit";
5715 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5716
5717 /* RIP. */
5718 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5719 {
5720 X86DESCATTR AttrCs;
5721 AttrCs.u = pVmcs->u32GuestCsAttr;
5722 if ( !fGstInLongMode
5723 || !AttrCs.n.u1Long)
5724 {
5725 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5726 { /* likely */ }
5727 else
5728 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5729 }
5730
5731 if ( fGstInLongMode
5732 && AttrCs.n.u1Long)
5733 {
5734 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5735 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5736 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5737 { /* likely */ }
5738 else
5739 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5740 }
5741 }
5742
5743 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5744 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5745 : pVmcs->u64GuestRFlags.s.Lo;
5746 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5747 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5748 { /* likely */ }
5749 else
5750 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5751
5752 if (!(uGuestRFlags & X86_EFL_VM))
5753 { /* likely */ }
5754 else
5755 {
5756 if ( fGstInLongMode
5757 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5758 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5759 }
5760
5761 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5762 {
5763 if (uGuestRFlags & X86_EFL_IF)
5764 { /* likely */ }
5765 else
5766 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5767 }
5768
5769 NOREF(pszInstr);
5770 NOREF(pszFailure);
5771 return VINF_SUCCESS;
5772}
5773
5774
5775/**
5776 * Checks guest non-register state as part of VM-entry.
5777 *
5778 * @param pVCpu The cross context virtual CPU structure.
5779 * @param pszInstr The VMX instruction name (for logging purposes).
5780 */
5781DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5782{
5783 /*
5784 * Guest non-register state.
5785 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5786 */
5787 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5788 const char *const pszFailure = "VM-exit";
5789
5790 /*
5791 * Activity state.
5792 */
5793 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5794 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5795 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5796 { /* likely */ }
5797 else
5798 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5799
5800 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5801 if ( !AttrSs.n.u2Dpl
5802 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5803 { /* likely */ }
5804 else
5805 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5806
5807 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5808 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5809 {
5810 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5811 { /* likely */ }
5812 else
5813 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5814 }
5815
5816 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5817 {
5818 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5819 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5820 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5821 switch (pVmcs->u32GuestActivityState)
5822 {
5823 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5824 {
5825 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5826 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5827 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5828 && ( uVector == X86_XCPT_DB
5829 || uVector == X86_XCPT_MC))
5830 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5831 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5832 { /* likely */ }
5833 else
5834 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5835 break;
5836 }
5837
5838 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5839 {
5840 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5841 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5842 && uVector == X86_XCPT_MC))
5843 { /* likely */ }
5844 else
5845 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5846 break;
5847 }
5848
5849 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5850 default:
5851 break;
5852 }
5853 }
5854
5855 /*
5856 * Interruptibility state.
5857 */
5858 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5859 { /* likely */ }
5860 else
5861 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5862
5863 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5864 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5865 { /* likely */ }
5866 else
5867 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5868
5869 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5870 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5871 { /* likely */ }
5872 else
5873 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5874
5875 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5876 {
5877 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5878 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5879 {
5880 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5881 { /* likely */ }
5882 else
5883 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5884 }
5885 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5886 {
5887 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5888 { /* likely */ }
5889 else
5890 {
5891 /*
5892 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5893 * We update the Exit qualification only when blocking-by-STI is set
5894 * without blocking-by-MovSS being set. Although in practise it does not
5895 * make much difference since the order of checks are implementation defined.
5896 */
5897 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5898 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5899 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5900 }
5901
5902 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5903 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5904 { /* likely */ }
5905 else
5906 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5907 }
5908 }
5909
5910 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5911 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5912 { /* likely */ }
5913 else
5914 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5915
5916 /* We don't support SGX yet. So enclave-interruption must not be set. */
5917 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5918 { /* likely */ }
5919 else
5920 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5921
5922 /*
5923 * Pending debug exceptions.
5924 */
5925 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5926 ? pVmcs->u64GuestPendingDbgXcpts.u
5927 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5928 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5929 { /* likely */ }
5930 else
5931 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5932
5933 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5934 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5935 {
5936 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5937 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5938 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5939 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5940
5941 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5942 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5943 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5944 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5945 }
5946
5947 /* We don't support RTM (Real-time Transactional Memory) yet. */
5948 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5949 { /* likely */ }
5950 else
5951 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5952
5953 /*
5954 * VMCS link pointer.
5955 */
5956 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5957 {
5958 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5959 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5960 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5961 { /* likely */ }
5962 else
5963 {
5964 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5965 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5966 }
5967
5968 /* Validate the address. */
5969 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5970 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5971 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5972 { /* likely */ }
5973 else
5974 {
5975 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5976 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5977 }
5978 }
5979
5980 NOREF(pszInstr);
5981 NOREF(pszFailure);
5982 return VINF_SUCCESS;
5983}
5984
5985
5986#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5987/**
5988 * Checks guest PDPTEs as part of VM-entry.
5989 *
5990 * @param pVCpu The cross context virtual CPU structure.
5991 * @param pszInstr The VMX instruction name (for logging purposes).
5992 */
5993static int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
5994{
5995 /*
5996 * Guest PDPTEs.
5997 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
5998 */
5999 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6000 const char * const pszFailure = "VM-exit";
6001
6002 /*
6003 * When EPT is used, we need to validate the PAE PDPTEs provided in the VMCS.
6004 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
6005 */
6006 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
6007 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
6008 {
6009 /* Get PDPTEs from the VMCS. */
6010 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6011 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6012 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6013 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6014 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6015
6016 /* Check validity of the PDPTEs. */
6017 if (PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]))
6018 { /* likely */ }
6019 else
6020 {
6021 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6022 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6023 }
6024 }
6025
6026 NOREF(pszFailure);
6027 NOREF(pszInstr);
6028 return VINF_SUCCESS;
6029}
6030#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
6031
6032
6033/**
6034 * Checks guest-state as part of VM-entry.
6035 *
6036 * @returns VBox status code.
6037 * @param pVCpu The cross context virtual CPU structure.
6038 * @param pszInstr The VMX instruction name (for logging purposes).
6039 */
6040static int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6041{
6042 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6043 if (RT_SUCCESS(rc))
6044 {
6045 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6046 if (RT_SUCCESS(rc))
6047 {
6048 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6049 if (RT_SUCCESS(rc))
6050 {
6051 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6052 if (RT_SUCCESS(rc))
6053 {
6054 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6055#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6056 if (RT_SUCCESS(rc))
6057 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6058#endif
6059 }
6060 }
6061 }
6062 }
6063 return rc;
6064}
6065
6066
6067/**
6068 * Checks host-state as part of VM-entry.
6069 *
6070 * @returns VBox status code.
6071 * @param pVCpu The cross context virtual CPU structure.
6072 * @param pszInstr The VMX instruction name (for logging purposes).
6073 */
6074static int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6075{
6076 /*
6077 * Host Control Registers and MSRs.
6078 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6079 */
6080 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6081 const char * const pszFailure = "VMFail";
6082
6083 /* CR0 reserved bits. */
6084 {
6085 /* CR0 MB1 bits. */
6086 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
6087 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6088 { /* likely */ }
6089 else
6090 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6091
6092 /* CR0 MBZ bits. */
6093 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6094 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6095 { /* likely */ }
6096 else
6097 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6098 }
6099
6100 /* CR4 reserved bits. */
6101 {
6102 /* CR4 MB1 bits. */
6103 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6104 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6105 { /* likely */ }
6106 else
6107 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6108
6109 /* CR4 MBZ bits. */
6110 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6111 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6112 { /* likely */ }
6113 else
6114 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6115 }
6116
6117 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6118 {
6119 /* CR3 reserved bits. */
6120 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6121 { /* likely */ }
6122 else
6123 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6124
6125 /* SYSENTER ESP and SYSENTER EIP. */
6126 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6127 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6128 { /* likely */ }
6129 else
6130 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6131 }
6132
6133 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6134 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6135
6136 /* PAT MSR. */
6137 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6138 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6139 { /* likely */ }
6140 else
6141 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6142
6143 /* EFER MSR. */
6144 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6145 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6146 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6147 {
6148 if (!(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6149 { /* likely */ }
6150 else
6151 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6152
6153 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6154 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6155 if ( fHostInLongMode == fHostLma
6156 && fHostInLongMode == fHostLme)
6157 { /* likely */ }
6158 else
6159 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6160 }
6161
6162 /*
6163 * Host Segment and Descriptor-Table Registers.
6164 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6165 */
6166 /* Selector RPL and TI. */
6167 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6168 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6169 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6170 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6171 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6172 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6173 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6174 { /* likely */ }
6175 else
6176 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6177
6178 /* CS and TR selectors cannot be 0. */
6179 if ( pVmcs->HostCs
6180 && pVmcs->HostTr)
6181 { /* likely */ }
6182 else
6183 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6184
6185 /* SS cannot be 0 if 32-bit host. */
6186 if ( fHostInLongMode
6187 || pVmcs->HostSs)
6188 { /* likely */ }
6189 else
6190 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6191
6192 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6193 {
6194 /* FS, GS, GDTR, IDTR, TR base address. */
6195 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6196 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6197 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6198 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6199 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6200 { /* likely */ }
6201 else
6202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6203 }
6204
6205 /*
6206 * Host address-space size for 64-bit CPUs.
6207 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6208 */
6209 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6210 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6211 {
6212 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6213
6214 /* Logical processor in IA-32e mode. */
6215 if (fCpuInLongMode)
6216 {
6217 if (fHostInLongMode)
6218 {
6219 /* PAE must be set. */
6220 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6221 { /* likely */ }
6222 else
6223 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6224
6225 /* RIP must be canonical. */
6226 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6227 { /* likely */ }
6228 else
6229 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6230 }
6231 else
6232 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6233 }
6234 else
6235 {
6236 /* Logical processor is outside IA-32e mode. */
6237 if ( !fGstInLongMode
6238 && !fHostInLongMode)
6239 {
6240 /* PCIDE should not be set. */
6241 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6242 { /* likely */ }
6243 else
6244 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6245
6246 /* The high 32-bits of RIP MBZ. */
6247 if (!pVmcs->u64HostRip.s.Hi)
6248 { /* likely */ }
6249 else
6250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6251 }
6252 else
6253 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6254 }
6255 }
6256 else
6257 {
6258 /* Host address-space size for 32-bit CPUs. */
6259 if ( !fGstInLongMode
6260 && !fHostInLongMode)
6261 { /* likely */ }
6262 else
6263 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6264 }
6265
6266 NOREF(pszInstr);
6267 NOREF(pszFailure);
6268 return VINF_SUCCESS;
6269}
6270
6271
6272#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6273/**
6274 * Checks the EPT pointer VMCS field as part of VM-entry.
6275 *
6276 * @returns VBox status code.
6277 * @param pVCpu The cross context virtual CPU structure.
6278 * @param uEptPtr The EPT pointer to check.
6279 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
6280 * updated on success). Optional, can be NULL.
6281 */
6282static int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr, VMXVDIAG *penmVmxDiag) RT_NOEXCEPT
6283{
6284 VMXVDIAG enmVmxDiag;
6285
6286 /* Reserved bits. */
6287 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
6288 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
6289 if (uEptPtr & fValidMask)
6290 {
6291 /* Memory Type. */
6292 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
6293 uint8_t const fMemType = RT_BF_GET(uEptPtr, VMX_BF_EPTP_MEMTYPE);
6294 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
6295 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
6296 || ( fMemType == VMX_EPTP_MEMTYPE_UC
6297 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
6298 {
6299 /*
6300 * Page walk length (PML4).
6301 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
6302 * of 5 but that seems to be removed from the latest specs. leaving only PML4
6303 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
6304 */
6305 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
6306 if (RT_BF_GET(uEptPtr, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
6307 {
6308 /* Access and dirty bits support in EPT structures. */
6309 if ( !RT_BF_GET(uEptPtr, VMX_BF_EPTP_ACCESS_DIRTY)
6310 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
6311 return VINF_SUCCESS;
6312
6313 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
6314 }
6315 else
6316 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
6317 }
6318 else
6319 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
6320 }
6321 else
6322 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
6323
6324 if (penmVmxDiag)
6325 *penmVmxDiag = enmVmxDiag;
6326 return VERR_VMX_VMENTRY_FAILED;
6327}
6328#endif
6329
6330
6331/**
6332 * Checks VMCS controls fields as part of VM-entry.
6333 *
6334 * @returns VBox status code.
6335 * @param pVCpu The cross context virtual CPU structure.
6336 * @param pszInstr The VMX instruction name (for logging purposes).
6337 *
6338 * @remarks This may update secondary-processor based VM-execution control fields
6339 * in the current VMCS if necessary.
6340 */
6341static int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6342{
6343 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6344 const char * const pszFailure = "VMFail";
6345 bool const fVmxTrueMsrs = RT_BOOL(pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
6346
6347 /*
6348 * VM-execution controls.
6349 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6350 */
6351 {
6352 /* Pin-based VM-execution controls. */
6353 {
6354 VMXCTLSMSR const PinCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TruePinCtls
6355 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6356 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6357 { /* likely */ }
6358 else
6359 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6360
6361 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6362 { /* likely */ }
6363 else
6364 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6365 }
6366
6367 /* Processor-based VM-execution controls. */
6368 {
6369 VMXCTLSMSR const ProcCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueProcCtls
6370 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6371 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6372 { /* likely */ }
6373 else
6374 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6375
6376 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6377 { /* likely */ }
6378 else
6379 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6380 }
6381
6382 /* Secondary processor-based VM-execution controls. */
6383 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6384 {
6385 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6386 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6387 { /* likely */ }
6388 else
6389 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6390
6391 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6392 { /* likely */ }
6393 else
6394 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6395 }
6396 else
6397 {
6398 /*
6399 * If the "activate secondary controls" is clear, then the secondary processor-based VM-execution controls
6400 * is treated as 0. We must not fail/assert here. Microsoft Hyper-V relies on this behavior.
6401 *
6402 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6403 */
6404 pVmcs->u32ProcCtls2 = 0;
6405 }
6406
6407 /* CR3-target count. */
6408 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6409 { /* likely */ }
6410 else
6411 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6412
6413 /* I/O bitmaps physical addresses. */
6414 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6415 {
6416 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6417 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6418 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6419 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6420 { /* likely */ }
6421 else
6422 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6423
6424 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6425 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6426 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6427 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6428 { /* likely */ }
6429 else
6430 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6431 }
6432
6433 /* MSR bitmap physical address. */
6434 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6435 {
6436 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6437 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6438 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6439 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6440 { /* likely */ }
6441 else
6442 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6443 }
6444
6445 /* TPR shadow related controls. */
6446 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6447 {
6448 /* Virtual-APIC page physical address. */
6449 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6450 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6451 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6452 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6453 { /* likely */ }
6454 else
6455 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6456
6457 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6458 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6459 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6460 { /* likely */ }
6461 else
6462 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6463
6464 /* The rest done XXX document */
6465 }
6466 else
6467 {
6468 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6469 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6470 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6471 { /* likely */ }
6472 else
6473 {
6474 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6475 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6476 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6477 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6478 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6479 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6480 }
6481 }
6482
6483 /* NMI exiting and virtual-NMIs. */
6484 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6485 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6486 { /* likely */ }
6487 else
6488 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6489
6490 /* Virtual-NMIs and NMI-window exiting. */
6491 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6492 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6493 { /* likely */ }
6494 else
6495 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6496
6497 /* Virtualize APIC accesses. */
6498 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6499 {
6500 /* APIC-access physical address. */
6501 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6502 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6503 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6504 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6505 { /* likely */ }
6506 else
6507 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6508
6509 /*
6510 * Disallow APIC-access page and virtual-APIC page from being the same address.
6511 * Note! This is not an Intel requirement, but one imposed by our implementation.
6512 */
6513 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6514 * redirecting accesses between the APIC-access page and the virtual-APIC
6515 * page. If any nested hypervisor requires this, we can implement it later. */
6516 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6517 {
6518 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6519 if (GCPhysVirtApic != GCPhysApicAccess)
6520 { /* likely */ }
6521 else
6522 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6523 }
6524 }
6525
6526 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6527 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6528 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6529 { /* likely */ }
6530 else
6531 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6532
6533 /* Virtual-interrupt delivery requires external interrupt exiting. */
6534 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6535 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6536 { /* likely */ }
6537 else
6538 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6539
6540 /* VPID. */
6541 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6542 || pVmcs->u16Vpid != 0)
6543 { /* likely */ }
6544 else
6545 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6546
6547#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6548 /* Extended-Page-Table Pointer (EPTP). */
6549 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6550 {
6551 VMXVDIAG enmVmxDiag;
6552 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, pVmcs->u64EptPtr.u, &enmVmxDiag);
6553 if (RT_SUCCESS(rc))
6554 { /* likely */ }
6555 else
6556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6557 }
6558#else
6559 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6560 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST));
6561#endif
6562 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6563 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6564 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6565 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6566 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6567
6568 /* VMCS shadowing. */
6569 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6570 {
6571 /* VMREAD-bitmap physical address. */
6572 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6573 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6574 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6575 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6576 { /* likely */ }
6577 else
6578 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6579
6580 /* VMWRITE-bitmap physical address. */
6581 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6582 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6583 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6584 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6585 { /* likely */ }
6586 else
6587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6588 }
6589 }
6590
6591 /*
6592 * VM-exit controls.
6593 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6594 */
6595 {
6596 VMXCTLSMSR const ExitCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueExitCtls
6597 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6598 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6599 { /* likely */ }
6600 else
6601 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6602
6603 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6604 { /* likely */ }
6605 else
6606 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6607
6608 /* Save preemption timer without activating it. */
6609 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6610 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6611 { /* likely */ }
6612 else
6613 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6614
6615 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6616 if (pVmcs->u32ExitMsrStoreCount)
6617 {
6618 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6619 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6620 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6621 { /* likely */ }
6622 else
6623 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6624 }
6625
6626 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6627 if (pVmcs->u32ExitMsrLoadCount)
6628 {
6629 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6630 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6631 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6632 { /* likely */ }
6633 else
6634 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6635 }
6636 }
6637
6638 /*
6639 * VM-entry controls.
6640 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6641 */
6642 {
6643 VMXCTLSMSR const EntryCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueEntryCtls
6644 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6645 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6646 { /* likely */ }
6647 else
6648 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6649
6650 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6651 { /* likely */ }
6652 else
6653 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6654
6655 /* Event injection. */
6656 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6657 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6658 {
6659 /* Type and vector. */
6660 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6661 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6662 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6663 if ( !uRsvd
6664 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6665 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6666 { /* likely */ }
6667 else
6668 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6669
6670 /* Exception error code. */
6671 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6672 {
6673 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6674 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6675 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6676 { /* likely */ }
6677 else
6678 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6679
6680 /* Exceptions that provide an error code. */
6681 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6682 && ( uVector == X86_XCPT_DF
6683 || uVector == X86_XCPT_TS
6684 || uVector == X86_XCPT_NP
6685 || uVector == X86_XCPT_SS
6686 || uVector == X86_XCPT_GP
6687 || uVector == X86_XCPT_PF
6688 || uVector == X86_XCPT_AC))
6689 { /* likely */ }
6690 else
6691 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6692
6693 /* Exception error-code reserved bits. */
6694 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6695 { /* likely */ }
6696 else
6697 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6698
6699 /* Injecting a software interrupt, software exception or privileged software exception. */
6700 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6701 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6702 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6703 {
6704 /* Instruction length must be in the range 0-15. */
6705 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6706 { /* likely */ }
6707 else
6708 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6709
6710 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6711 if ( pVmcs->u32EntryInstrLen != 0
6712 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6713 { /* likely */ }
6714 else
6715 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6716 }
6717 }
6718 }
6719
6720 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6721 if (pVmcs->u32EntryMsrLoadCount)
6722 {
6723 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6724 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6725 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6726 { /* likely */ }
6727 else
6728 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6729 }
6730
6731 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6732 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6733 }
6734
6735 NOREF(pszInstr);
6736 NOREF(pszFailure);
6737 return VINF_SUCCESS;
6738}
6739
6740
6741/**
6742 * Loads the guest control registers, debug register and some MSRs as part of
6743 * VM-entry.
6744 *
6745 * @param pVCpu The cross context virtual CPU structure.
6746 */
6747static void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
6748{
6749 /*
6750 * Load guest control registers, debug registers and MSRs.
6751 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6752 */
6753 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6754
6755 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6756 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6757 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6758 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6759 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6760 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6761
6762 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6763 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6764
6765 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6766 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6767 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6768
6769 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6770 {
6771 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6772
6773 /* EFER MSR. */
6774 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6775 {
6776 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6777 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6778 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6779 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6780 if (fGstInLongMode)
6781 {
6782 /* If the nested-guest is in long mode, LMA and LME are both set. */
6783 Assert(fGstPaging);
6784 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6785 }
6786 else
6787 {
6788 /*
6789 * If the nested-guest is outside long mode:
6790 * - With paging: LMA is cleared, LME is cleared.
6791 * - Without paging: LMA is cleared, LME is left unmodified.
6792 */
6793 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6794 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6795 }
6796 }
6797 /* else: see below. */
6798 }
6799
6800 /* PAT MSR. */
6801 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6802 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6803
6804 /* EFER MSR. */
6805 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6806 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6807
6808 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6809 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6810
6811 /* We don't support IA32_BNDCFGS MSR yet. */
6812 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6813
6814 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6815}
6816
6817
6818/**
6819 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6820 *
6821 * @param pVCpu The cross context virtual CPU structure.
6822 */
6823static void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
6824{
6825 /*
6826 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6827 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6828 */
6829 /* CS, SS, ES, DS, FS, GS. */
6830 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6831 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6832 {
6833 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6834 CPUMSELREG VmcsSelReg;
6835 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6836 AssertRC(rc); NOREF(rc);
6837 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6838 {
6839 pGstSelReg->Sel = VmcsSelReg.Sel;
6840 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6841 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6842 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6843 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6844 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6845 }
6846 else
6847 {
6848 pGstSelReg->Sel = VmcsSelReg.Sel;
6849 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6850 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6851 switch (iSegReg)
6852 {
6853 case X86_SREG_CS:
6854 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6855 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6856 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6857 break;
6858
6859 case X86_SREG_SS:
6860 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6861 pGstSelReg->u32Limit = 0;
6862 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6863 break;
6864
6865 case X86_SREG_ES:
6866 case X86_SREG_DS:
6867 pGstSelReg->u64Base = 0;
6868 pGstSelReg->u32Limit = 0;
6869 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6870 break;
6871
6872 case X86_SREG_FS:
6873 case X86_SREG_GS:
6874 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6875 pGstSelReg->u32Limit = 0;
6876 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6877 break;
6878 }
6879 Assert(pGstSelReg->Attr.n.u1Unusable);
6880 }
6881 }
6882
6883 /* LDTR. */
6884 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6885 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6886 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6887 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6888 {
6889 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6890 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6891 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6892 }
6893 else
6894 {
6895 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6896 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6897 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6898 }
6899
6900 /* TR. */
6901 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6902 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6903 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6904 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6905 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6906 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6907 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6908
6909 /* GDTR. */
6910 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6911 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6912
6913 /* IDTR. */
6914 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6915 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6916}
6917
6918
6919/**
6920 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6921 *
6922 * @returns VBox status code.
6923 * @param pVCpu The cross context virtual CPU structure.
6924 * @param pszInstr The VMX instruction name (for logging purposes).
6925 */
6926static int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6927{
6928 /*
6929 * Load guest MSRs.
6930 * See Intel spec. 26.4 "Loading MSRs".
6931 */
6932 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6933 const char *const pszFailure = "VM-exit";
6934
6935 /*
6936 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6937 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6938 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6939 */
6940 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6941 if (!cMsrs)
6942 return VINF_SUCCESS;
6943
6944 /*
6945 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6946 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6947 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6948 */
6949 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6950 if (fIsMsrCountValid)
6951 { /* likely */ }
6952 else
6953 {
6954 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6955 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6956 }
6957
6958 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6959 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6960 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6961 if (RT_SUCCESS(rc))
6962 {
6963 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6964 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6965 {
6966 if ( !pMsr->u32Reserved
6967 && pMsr->u32Msr != MSR_K8_FS_BASE
6968 && pMsr->u32Msr != MSR_K8_GS_BASE
6969 && pMsr->u32Msr != MSR_K6_EFER
6970 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6971 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6972 {
6973 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6974 if (rcStrict == VINF_SUCCESS)
6975 continue;
6976
6977 /*
6978 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6979 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6980 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6981 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6982 * MSR in ring-0 if possible, or come up with a better, generic solution.
6983 */
6984 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6985 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6986 ? kVmxVDiag_Vmentry_MsrLoadRing3
6987 : kVmxVDiag_Vmentry_MsrLoad;
6988 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6989 }
6990 else
6991 {
6992 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6993 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6994 }
6995 }
6996 }
6997 else
6998 {
6999 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7000 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7001 }
7002
7003 NOREF(pszInstr);
7004 NOREF(pszFailure);
7005 return VINF_SUCCESS;
7006}
7007
7008
7009/**
7010 * Loads the guest-state non-register state as part of VM-entry.
7011 *
7012 * @returns VBox status code.
7013 * @param pVCpu The cross context virtual CPU structure.
7014 * @param pszInstr The VMX instruction name (for logging purposes).
7015 *
7016 * @remarks This must be called only after loading the nested-guest register state
7017 * (especially nested-guest RIP).
7018 */
7019static int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7020{
7021 /*
7022 * Load guest non-register state.
7023 * See Intel spec. 26.6 "Special Features of VM Entry"
7024 */
7025 const char *const pszFailure = "VM-exit";
7026 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7027
7028 /*
7029 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7030 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7031 *
7032 * See Intel spec. 26.6.1 "Interruptibility State".
7033 */
7034 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7035 if ( !fEntryVectoring
7036 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7037 CPUMSetInInterruptShadowEx(&pVCpu->cpum.GstCtx, pVmcs->u64GuestRip.u);
7038 else
7039 Assert(!CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx));
7040
7041 /* NMI blocking. */
7042 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7043 {
7044 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7045 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7046 else
7047 {
7048 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7049 CPUMSetInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx);
7050 }
7051 }
7052 else
7053 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7054
7055 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7056
7057 /*
7058 * Set PGM's copy of the EPT pointer.
7059 * The EPTP has already been validated while checking guest state.
7060 *
7061 * It is important to do this prior to mapping PAE PDPTEs (below).
7062 */
7063 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7064 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
7065
7066 /*
7067 * Load the guest's PAE PDPTEs.
7068 */
7069 if (!iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
7070 {
7071 /*
7072 * When PAE paging is not used we clear the PAE PDPTEs for safety
7073 * in case we might be switching from a PAE host to a non-PAE guest.
7074 */
7075 pVCpu->cpum.GstCtx.aPaePdpes[0].u = 0;
7076 pVCpu->cpum.GstCtx.aPaePdpes[1].u = 0;
7077 pVCpu->cpum.GstCtx.aPaePdpes[2].u = 0;
7078 pVCpu->cpum.GstCtx.aPaePdpes[3].u = 0;
7079 }
7080 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7081 {
7082 /*
7083 * With EPT and the nested-guest using PAE paging, we've already validated the PAE PDPTEs
7084 * while checking the guest state. We can load them into the nested-guest CPU state now.
7085 * They'll later be used while mapping CR3 and the PAE PDPTEs.
7086 */
7087 pVCpu->cpum.GstCtx.aPaePdpes[0].u = pVmcs->u64GuestPdpte0.u;
7088 pVCpu->cpum.GstCtx.aPaePdpes[1].u = pVmcs->u64GuestPdpte1.u;
7089 pVCpu->cpum.GstCtx.aPaePdpes[2].u = pVmcs->u64GuestPdpte2.u;
7090 pVCpu->cpum.GstCtx.aPaePdpes[3].u = pVmcs->u64GuestPdpte3.u;
7091 }
7092 else
7093 {
7094 /*
7095 * Without EPT and the nested-guest using PAE paging, we must load the PAE PDPTEs
7096 * referenced by CR3. This involves loading (and mapping) CR3 and validating them now.
7097 */
7098 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
7099 if (RT_SUCCESS(rc))
7100 { /* likely */ }
7101 else
7102 {
7103 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
7104 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
7105 }
7106 }
7107
7108 /* VPID is irrelevant. We don't support VPID yet. */
7109
7110 /* Clear address-range monitoring. */
7111 EMMonitorWaitClear(pVCpu);
7112
7113 return VINF_SUCCESS;
7114}
7115
7116
7117/**
7118 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
7119 *
7120 * @param pVCpu The cross context virtual CPU structure.
7121 * @param pszInstr The VMX instruction name (for logging purposes).
7122 *
7123 * @remarks This assumes various VMCS related data structure pointers have already
7124 * been verified prior to calling this function.
7125 */
7126static int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7127{
7128 const char *const pszFailure = "VM-exit";
7129 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7130
7131 /*
7132 * Virtualize APIC accesses.
7133 */
7134 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7135 {
7136 /* APIC-access physical address. */
7137 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
7138
7139 /*
7140 * Register the handler for the APIC-access page.
7141 *
7142 * We don't deregister the APIC-access page handler during the VM-exit as a different
7143 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
7144 *
7145 * We leave the page registered until the first access that happens outside VMX non-root
7146 * mode. Guest software is allowed to access structures such as the APIC-access page
7147 * only when no logical processor with a current VMCS references it in VMX non-root mode,
7148 * otherwise it can lead to unpredictable behavior including guest triple-faults.
7149 *
7150 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7151 */
7152 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
7153 {
7154 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7155 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess | X86_PAGE_4K_OFFSET_MASK,
7156 pVM->iem.s.hVmxApicAccessPage, 0 /*uUser*/, NULL /*pszDesc*/);
7157 if (RT_SUCCESS(rc))
7158 { /* likely */ }
7159 else
7160 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
7161 }
7162 }
7163
7164 /*
7165 * VMCS shadowing.
7166 */
7167 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7168 {
7169 /* Read the VMREAD-bitmap. */
7170 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
7171 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
7172 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
7173 if (RT_SUCCESS(rc))
7174 { /* likely */ }
7175 else
7176 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
7177
7178 /* Read the VMWRITE-bitmap. */
7179 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
7180 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
7181 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
7182 if (RT_SUCCESS(rc))
7183 { /* likely */ }
7184 else
7185 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
7186 }
7187
7188 /*
7189 * I/O bitmaps.
7190 */
7191 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
7192 {
7193 /* Read the IO bitmap A. */
7194 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
7195 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
7196 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
7197 if (RT_SUCCESS(rc))
7198 { /* likely */ }
7199 else
7200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
7201
7202 /* Read the IO bitmap B. */
7203 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
7204 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
7205 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
7206 if (RT_SUCCESS(rc))
7207 { /* likely */ }
7208 else
7209 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
7210 }
7211
7212 /*
7213 * TPR shadow and Virtual-APIC page.
7214 */
7215 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7216 {
7217 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
7218 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7219 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
7220 {
7221 /* Read the VTPR from the virtual-APIC page. */
7222 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
7223 uint8_t u8VTpr;
7224 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
7225 if (RT_SUCCESS(rc))
7226 { /* likely */ }
7227 else
7228 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
7229
7230 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
7231 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
7232 { /* likely */ }
7233 else
7234 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
7235 }
7236 }
7237
7238 /*
7239 * VMCS link pointer.
7240 */
7241 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
7242 {
7243 /* Read the VMCS-link pointer from guest memory. */
7244 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
7245 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
7246 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
7247 if (RT_SUCCESS(rc))
7248 { /* likely */ }
7249 else
7250 {
7251 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7252 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
7253 }
7254
7255 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7256 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
7257 { /* likely */ }
7258 else
7259 {
7260 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
7262 }
7263
7264 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
7265 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7266 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
7267 { /* likely */ }
7268 else
7269 {
7270 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7271 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
7272 }
7273
7274 /* Update our cache of the guest physical address of the shadow VMCS. */
7275 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
7276 }
7277
7278 /*
7279 * MSR bitmap.
7280 */
7281 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7282 {
7283 /* Read the MSR bitmap. */
7284 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
7285 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
7286 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
7287 if (RT_SUCCESS(rc))
7288 { /* likely */ }
7289 else
7290 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
7291 }
7292
7293 NOREF(pszFailure);
7294 NOREF(pszInstr);
7295 return VINF_SUCCESS;
7296}
7297
7298
7299/**
7300 * Loads the guest-state as part of VM-entry.
7301 *
7302 * @returns VBox status code.
7303 * @param pVCpu The cross context virtual CPU structure.
7304 * @param pszInstr The VMX instruction name (for logging purposes).
7305 *
7306 * @remarks This must be done after all the necessary steps prior to loading of
7307 * guest-state (e.g. checking various VMCS state).
7308 */
7309static int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7310{
7311 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
7312 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7313
7314 /* Load guest segment registers. */
7315 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7316
7317 /*
7318 * Load guest RIP, RSP and RFLAGS.
7319 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7320 */
7321 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7322 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7323 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7324 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7325
7326 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7327 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7328 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7329
7330 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
7331 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
7332 if (rc == VINF_SUCCESS)
7333 { /* likely */ }
7334 else
7335 return rc;
7336
7337 /* Load VMX related structures and state referenced by the VMCS. */
7338 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
7339 if (rc == VINF_SUCCESS)
7340 { /* likely */ }
7341 else
7342 return rc;
7343
7344 NOREF(pszInstr);
7345 return VINF_SUCCESS;
7346}
7347
7348
7349/**
7350 * Returns whether there are is a pending debug exception on VM-entry.
7351 *
7352 * @param pVCpu The cross context virtual CPU structure.
7353 * @param pszInstr The VMX instruction name (for logging purposes).
7354 */
7355static bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7356{
7357 /*
7358 * Pending debug exceptions.
7359 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7360 */
7361 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7362 Assert(pVmcs);
7363
7364 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7365 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7366 if (fPendingDbgXcpt)
7367 {
7368 uint8_t uEntryIntInfoType;
7369 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7370 if (fEntryVectoring)
7371 {
7372 switch (uEntryIntInfoType)
7373 {
7374 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7375 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7376 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7377 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7378 fPendingDbgXcpt = false;
7379 break;
7380
7381 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7382 {
7383 /*
7384 * Whether the pending debug exception for software exceptions other than
7385 * #BP and #OF is delivered after injecting the exception or is discard
7386 * is CPU implementation specific. We will discard them (easier).
7387 */
7388 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7389 if ( uVector != X86_XCPT_BP
7390 && uVector != X86_XCPT_OF)
7391 fPendingDbgXcpt = false;
7392 RT_FALL_THRU();
7393 }
7394 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7395 {
7396 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7397 fPendingDbgXcpt = false;
7398 break;
7399 }
7400 }
7401 }
7402 else
7403 {
7404 /*
7405 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7406 * pending debug exception is held pending or is discarded is CPU implementation
7407 * specific. We will discard them (easier).
7408 */
7409 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7410 fPendingDbgXcpt = false;
7411
7412 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7413 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7414 fPendingDbgXcpt = false;
7415 }
7416 }
7417
7418 NOREF(pszInstr);
7419 return fPendingDbgXcpt;
7420}
7421
7422
7423/**
7424 * Set up the monitor-trap flag (MTF).
7425 *
7426 * @param pVCpu The cross context virtual CPU structure.
7427 * @param pszInstr The VMX instruction name (for logging purposes).
7428 */
7429static void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7430{
7431 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7432 Assert(pVmcs);
7433 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7434 {
7435 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7436 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7437 }
7438 else
7439 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7440 NOREF(pszInstr);
7441}
7442
7443
7444/**
7445 * Sets up NMI-window exiting.
7446 *
7447 * @param pVCpu The cross context virtual CPU structure.
7448 * @param pszInstr The VMX instruction name (for logging purposes).
7449 */
7450static void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7451{
7452 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7453 Assert(pVmcs);
7454 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7455 {
7456 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7457 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7458 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7459 }
7460 else
7461 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7462 NOREF(pszInstr);
7463}
7464
7465
7466/**
7467 * Sets up interrupt-window exiting.
7468 *
7469 * @param pVCpu The cross context virtual CPU structure.
7470 * @param pszInstr The VMX instruction name (for logging purposes).
7471 */
7472static void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7473{
7474 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7475 Assert(pVmcs);
7476 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7477 {
7478 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7479 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7480 }
7481 else
7482 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7483 NOREF(pszInstr);
7484}
7485
7486
7487/**
7488 * Set up the VMX-preemption timer.
7489 *
7490 * @param pVCpu The cross context virtual CPU structure.
7491 * @param pszInstr The VMX instruction name (for logging purposes).
7492 */
7493static void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7494{
7495 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7496 Assert(pVmcs);
7497 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7498 {
7499 /*
7500 * If the timer is 0, we must cause a VM-exit before executing the first
7501 * nested-guest instruction. So we can flag as though the timer has already
7502 * expired and we will check and cause a VM-exit at the right priority elsewhere
7503 * in the code.
7504 */
7505 uint64_t uEntryTick;
7506 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7507 if (uPreemptTimer)
7508 {
7509 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7510 AssertRC(rc);
7511 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7512 }
7513 else
7514 {
7515 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7516 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7517 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7518 }
7519
7520 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7521 }
7522 else
7523 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7524
7525 NOREF(pszInstr);
7526}
7527
7528
7529/**
7530 * Injects an event using TRPM given a VM-entry interruption info and related
7531 * fields.
7532 *
7533 * @param pVCpu The cross context virtual CPU structure.
7534 * @param pszInstr The VMX instruction name (for logging purposes).
7535 * @param uEntryIntInfo The VM-entry interruption info.
7536 * @param uErrCode The error code associated with the event if any.
7537 * @param cbInstr The VM-entry instruction length (for software
7538 * interrupts and software exceptions). Pass 0
7539 * otherwise.
7540 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7541 */
7542static void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7543 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress) RT_NOEXCEPT
7544{
7545 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7546
7547 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7548 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7549 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7550
7551 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7552
7553 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7554 AssertRC(rc);
7555 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7556
7557 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7558 {
7559 TRPMSetErrorCode(pVCpu, uErrCode);
7560 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7561 }
7562
7563 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7564 {
7565 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7566 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7567 }
7568 else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7569 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7570 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7571 {
7572 TRPMSetInstrLength(pVCpu, cbInstr);
7573 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7574 }
7575
7576 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7577 {
7578 TRPMSetTrapDueToIcebp(pVCpu);
7579 Log(("%s: Injecting: icebp\n", pszInstr));
7580 }
7581
7582 NOREF(pszInstr);
7583}
7584
7585
7586/**
7587 * Performs event injection (if any) as part of VM-entry.
7588 *
7589 * @param pVCpu The cross context virtual CPU structure.
7590 * @param pszInstr The VMX instruction name (for logging purposes).
7591 */
7592static void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7593{
7594 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7595
7596 /*
7597 * Inject events.
7598 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7599 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7600 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7601 * the actually delivery of this event.
7602 *
7603 * See Intel spec. 26.5 "Event Injection".
7604 */
7605 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7606 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7607
7608 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7609 if (fEntryIntInfoValid)
7610 {
7611 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7612 {
7613 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7614 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7615 }
7616 else
7617 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7618 pVCpu->cpum.GstCtx.cr2);
7619
7620 /*
7621 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7622 *
7623 * However, we do it here on VM-entry as well because while it isn't visible to guest
7624 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7625 * execution using hardware-assisted VMX, it will not try to inject the event again.
7626 *
7627 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7628 */
7629 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7630 }
7631 else
7632 {
7633 /*
7634 * Inject any pending guest debug exception.
7635 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7636 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7637 */
7638 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7639 if (fPendingDbgXcpt)
7640 {
7641 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7642 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7643 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7644 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7645 0 /* GCPtrFaultAddress */);
7646 }
7647 }
7648
7649 NOREF(pszInstr);
7650}
7651
7652
7653/**
7654 * Initializes all read-only VMCS fields as part of VM-entry.
7655 *
7656 * @param pVCpu The cross context virtual CPU structure.
7657 */
7658static void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu) RT_NOEXCEPT
7659{
7660 /*
7661 * Any VMCS field which we do not establish on every VM-exit but may potentially
7662 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7663 * specified to be undefined, needs to be initialized here.
7664 *
7665 * Thus, it is especially important to clear the Exit qualification field
7666 * since it must be zero for VM-exits where it is not used. Similarly, the
7667 * VM-exit interruption information field's valid bit needs to be cleared for
7668 * the same reasons.
7669 */
7670 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7671 Assert(pVmcs);
7672
7673 /* 16-bit (none currently). */
7674 /* 32-bit. */
7675 pVmcs->u32RoVmInstrError = 0;
7676 pVmcs->u32RoExitReason = 0;
7677 pVmcs->u32RoExitIntInfo = 0;
7678 pVmcs->u32RoExitIntErrCode = 0;
7679 pVmcs->u32RoIdtVectoringInfo = 0;
7680 pVmcs->u32RoIdtVectoringErrCode = 0;
7681 pVmcs->u32RoExitInstrLen = 0;
7682 pVmcs->u32RoExitInstrInfo = 0;
7683
7684 /* 64-bit. */
7685 pVmcs->u64RoGuestPhysAddr.u = 0;
7686
7687 /* Natural-width. */
7688 pVmcs->u64RoExitQual.u = 0;
7689 pVmcs->u64RoIoRcx.u = 0;
7690 pVmcs->u64RoIoRsi.u = 0;
7691 pVmcs->u64RoIoRdi.u = 0;
7692 pVmcs->u64RoIoRip.u = 0;
7693 pVmcs->u64RoGuestLinearAddr.u = 0;
7694}
7695
7696
7697/**
7698 * VMLAUNCH/VMRESUME instruction execution worker.
7699 *
7700 * @returns Strict VBox status code.
7701 * @param pVCpu The cross context virtual CPU structure.
7702 * @param cbInstr The instruction length in bytes.
7703 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7704 * VMXINSTRID_VMRESUME).
7705 *
7706 * @remarks Common VMX instruction checks are already expected to by the caller,
7707 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7708 */
7709static VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId) RT_NOEXCEPT
7710{
7711# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7712 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7713 return VINF_EM_RAW_EMULATE_INSTR;
7714# else
7715 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7716 || uInstrId == VMXINSTRID_VMRESUME);
7717 const char * const pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7718
7719 /* Nested-guest intercept. */
7720 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7721 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7722
7723 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7724
7725 /*
7726 * Basic VM-entry checks.
7727 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7728 * The checks following that do not have to follow a specific order.
7729 *
7730 * See Intel spec. 26.1 "Basic VM-entry Checks".
7731 */
7732
7733 /* CPL. */
7734 if (pVCpu->iem.s.uCpl == 0)
7735 { /* likely */ }
7736 else
7737 {
7738 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7739 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7740 return iemRaiseGeneralProtectionFault0(pVCpu);
7741 }
7742
7743 /* Current VMCS valid. */
7744 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7745 { /* likely */ }
7746 else
7747 {
7748 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7749 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7750 iemVmxVmFailInvalid(pVCpu);
7751 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7752 }
7753
7754 /* Current VMCS is not a shadow VMCS. */
7755 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7756 { /* likely */ }
7757 else
7758 {
7759 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7760 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7761 iemVmxVmFailInvalid(pVCpu);
7762 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7763 }
7764
7765 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7766 * use block-by-STI here which is not quite correct. */
7767 if (!CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx))
7768 { /* likely */ }
7769 else
7770 {
7771 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7772 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7773 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7774 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7775 }
7776
7777 if (uInstrId == VMXINSTRID_VMLAUNCH)
7778 {
7779 /* VMLAUNCH with non-clear VMCS. */
7780 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7781 { /* likely */ }
7782 else
7783 {
7784 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7785 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7786 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7787 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7788 }
7789 }
7790 else
7791 {
7792 /* VMRESUME with non-launched VMCS. */
7793 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7794 { /* likely */ }
7795 else
7796 {
7797 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7798 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7799 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7800 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7801 }
7802 }
7803
7804 /*
7805 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7806 * while entering VMX non-root mode. We do some of this while checking VM-execution
7807 * controls. The nested hypervisor should not make assumptions and cannot expect
7808 * predictable behavior if changes to these structures are made in guest memory while
7809 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7810 * modify them anyway as we cache them in host memory.
7811 *
7812 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7813 */
7814 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7815 Assert(pVmcs);
7816 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7817
7818 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7819 if (RT_SUCCESS(rc))
7820 {
7821 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7822 if (RT_SUCCESS(rc))
7823 {
7824 /*
7825 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7826 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7827 * ones that may occur during VM-entry below).
7828 */
7829 iemVmxVmentryInitReadOnlyFields(pVCpu);
7830
7831 /*
7832 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7833 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7834 * VM-exit when required.
7835 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7836 */
7837 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7838
7839 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7840 if (RT_SUCCESS(rc))
7841 {
7842 /*
7843 * We've now entered nested-guest execution.
7844 *
7845 * It is important do this prior to loading the guest state because
7846 * as part of loading the guest state, PGM (and perhaps other components
7847 * in the future) relies on detecting whether VMX non-root mode has been
7848 * entered.
7849 */
7850 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7851
7852 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7853 if (RT_SUCCESS(rc))
7854 {
7855 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7856 if (RT_SUCCESS(rc))
7857 {
7858 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7859
7860 /* VMLAUNCH instruction must update the VMCS launch state. */
7861 if (uInstrId == VMXINSTRID_VMLAUNCH)
7862 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7863
7864 /* Perform the VMX transition (PGM updates). */
7865 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7866 if (rcStrict == VINF_SUCCESS)
7867 { /* likely */ }
7868 else if (RT_SUCCESS(rcStrict))
7869 {
7870 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7871 VBOXSTRICTRC_VAL(rcStrict)));
7872 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7873 }
7874 else
7875 {
7876 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7877 return rcStrict;
7878 }
7879
7880 /* Paranoia. */
7881 Assert(rcStrict == VINF_SUCCESS);
7882
7883 /*
7884 * The priority of potential VM-exits during VM-entry is important.
7885 * The priorities of VM-exits and events are listed from highest
7886 * to lowest as follows:
7887 *
7888 * 1. Event injection.
7889 * 2. Trap on task-switch (T flag set in TSS).
7890 * 3. TPR below threshold / APIC-write.
7891 * 4. SMI, INIT.
7892 * 5. MTF exit.
7893 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7894 * 7. VMX-preemption timer.
7895 * 9. NMI-window exit.
7896 * 10. NMI injection.
7897 * 11. Interrupt-window exit.
7898 * 12. Virtual-interrupt injection.
7899 * 13. Interrupt injection.
7900 * 14. Process next instruction (fetch, decode, execute).
7901 */
7902
7903 /* Setup VMX-preemption timer. */
7904 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7905
7906 /* Setup monitor-trap flag. */
7907 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7908
7909 /* Setup NMI-window exiting. */
7910 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7911
7912 /* Setup interrupt-window exiting. */
7913 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7914
7915 /*
7916 * Inject any event that the nested hypervisor wants to inject.
7917 * Note! We cannot immediately perform the event injection here as we may have
7918 * pending PGM operations to perform due to switching page tables and/or
7919 * mode.
7920 */
7921 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7922
7923# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7924 /* Reschedule to IEM-only execution of the nested-guest. */
7925 LogFlow(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7926 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7927 if (rcSched != VINF_SUCCESS)
7928 iemSetPassUpStatus(pVCpu, rcSched);
7929# endif
7930
7931 /* Finally, done. */
7932 Log2(("vmentry: %s: cs:rip=%04x:%08RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64 (%#RX64)\n",
7933 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7934 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7935 pVCpu->cpum.GstCtx.msrEFER, pVmcs->u64GuestEferMsr.u));
7936 return VINF_SUCCESS;
7937 }
7938 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7939 }
7940 }
7941 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7942 }
7943
7944 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7945 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7946 }
7947
7948 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7949 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7950# endif
7951}
7952
7953
7954/**
7955 * Interface for HM and EM to emulate the VMLAUNCH/VMRESUME instruction.
7956 *
7957 * @returns Strict VBox status code.
7958 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
7959 * @param cbInstr The instruction length in bytes.
7960 * @param uInstrId The instruction ID (VMXINSTRID_VMLAUNCH or
7961 * VMXINSTRID_VMRESUME).
7962 * @thread EMT(pVCpu)
7963 */
7964VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7965{
7966 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
7967 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
7968
7969 iemInitExec(pVCpu, false /*fBypassHandlers*/);
7970 VBOXSTRICTRC rcStrict = iemVmxVmlaunchVmresume(pVCpu, cbInstr, uInstrId);
7971 Assert(!pVCpu->iem.s.cActiveMappings);
7972 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
7973}
7974
7975
7976/**
7977 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7978 * (causes a VM-exit) or not.
7979 *
7980 * @returns @c true if the instruction is intercepted, @c false otherwise.
7981 * @param pVCpu The cross context virtual CPU structure.
7982 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7983 * VMX_EXIT_WRMSR).
7984 * @param idMsr The MSR.
7985 */
7986bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT
7987{
7988 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7989 Assert( uExitReason == VMX_EXIT_RDMSR
7990 || uExitReason == VMX_EXIT_WRMSR);
7991
7992 /* Consult the MSR bitmap if the feature is supported. */
7993 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7994 Assert(pVmcs);
7995 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7996 {
7997 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
7998 if (uExitReason == VMX_EXIT_RDMSR)
7999 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
8000 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
8001 }
8002
8003 /* Without MSR bitmaps, all MSR accesses are intercepted. */
8004 return true;
8005}
8006
8007
8008/**
8009 * VMREAD instruction execution worker that does not perform any validation checks.
8010 *
8011 * Callers are expected to have performed the necessary checks and to ensure the
8012 * VMREAD will succeed.
8013 *
8014 * @param pVmcs Pointer to the virtual VMCS.
8015 * @param pu64Dst Where to write the VMCS value.
8016 * @param u64VmcsField The VMCS field.
8017 *
8018 * @remarks May be called with interrupts disabled.
8019 */
8020static void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField) RT_NOEXCEPT
8021{
8022 VMXVMCSFIELD VmcsField;
8023 VmcsField.u = u64VmcsField;
8024 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8025 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8026 uint8_t const uWidthType = (uWidth << 2) | uType;
8027 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8028 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8029 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8030 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
8031 uWidth, uType, uIndex, uIndex));
8032 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8033
8034 /*
8035 * Read the VMCS component based on the field's effective width.
8036 *
8037 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8038 * indicates high bits (little endian).
8039 *
8040 * Note! The caller is responsible to trim the result and update registers
8041 * or memory locations are required. Here we just zero-extend to the largest
8042 * type (i.e. 64-bits).
8043 */
8044 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
8045 uint8_t const *pbField = pbVmcs + offField;
8046 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8047 switch (uEffWidth)
8048 {
8049 case VMX_VMCSFIELD_WIDTH_64BIT:
8050 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
8051 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
8052 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
8053 }
8054}
8055
8056
8057/**
8058 * Interface for HM and EM to read a VMCS field from the nested-guest VMCS.
8059 *
8060 * It is ASSUMED the caller knows what they're doing. No VMREAD instruction checks
8061 * are performed. Bounds checks are strict builds only.
8062 *
8063 * @param pVmcs Pointer to the virtual VMCS.
8064 * @param u64VmcsField The VMCS field.
8065 * @param pu64Dst Where to store the VMCS value.
8066 *
8067 * @remarks May be called with interrupts disabled.
8068 * @todo This should probably be moved to CPUM someday.
8069 */
8070VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst)
8071{
8072 AssertPtr(pVmcs);
8073 AssertPtr(pu64Dst);
8074 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8075}
8076
8077
8078/**
8079 * VMREAD common (memory/register) instruction execution worker.
8080 *
8081 * @returns Strict VBox status code.
8082 * @param pVCpu The cross context virtual CPU structure.
8083 * @param cbInstr The instruction length in bytes.
8084 * @param pu64Dst Where to write the VMCS value (only updated when
8085 * VINF_SUCCESS is returned).
8086 * @param u64VmcsField The VMCS field.
8087 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8088 * NULL.
8089 */
8090static VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8091 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8092{
8093 /* Nested-guest intercept. */
8094 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8095 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
8096 {
8097 if (pExitInfo)
8098 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8099 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
8100 }
8101
8102 /* CPL. */
8103 if (pVCpu->iem.s.uCpl == 0)
8104 { /* likely */ }
8105 else
8106 {
8107 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8108 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
8109 return iemRaiseGeneralProtectionFault0(pVCpu);
8110 }
8111
8112 pVCpu->iem.s.cPotentialExits++;
8113
8114 /* VMCS pointer in root mode. */
8115 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8116 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8117 { /* likely */ }
8118 else
8119 {
8120 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8121 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
8122 iemVmxVmFailInvalid(pVCpu);
8123 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8124 }
8125
8126 /* VMCS-link pointer in non-root mode. */
8127 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8128 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8129 { /* likely */ }
8130 else
8131 {
8132 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8133 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
8134 iemVmxVmFailInvalid(pVCpu);
8135 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8136 }
8137
8138 /* Supported VMCS field. */
8139 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8140 { /* likely */ }
8141 else
8142 {
8143 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8144 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
8145 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8146 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
8147 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8148 }
8149
8150 /*
8151 * Reading from the current or shadow VMCS.
8152 */
8153 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8154 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8155 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8156 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8157 Log4(("vmread %#RX64 => %#RX64\n", u64VmcsField, *pu64Dst));
8158 return VINF_SUCCESS;
8159}
8160
8161
8162/**
8163 * VMREAD (64-bit register) instruction execution worker.
8164 *
8165 * @returns Strict VBox status code.
8166 * @param pVCpu The cross context virtual CPU structure.
8167 * @param cbInstr The instruction length in bytes.
8168 * @param pu64Dst Where to store the VMCS field's value.
8169 * @param u64VmcsField The VMCS field.
8170 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8171 * NULL.
8172 */
8173static VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8174 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8175{
8176 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
8177 if (rcStrict == VINF_SUCCESS)
8178 {
8179 iemVmxVmSucceed(pVCpu);
8180 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8181 }
8182
8183 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8184 return rcStrict;
8185}
8186
8187
8188/**
8189 * VMREAD (32-bit register) instruction execution worker.
8190 *
8191 * @returns Strict VBox status code.
8192 * @param pVCpu The cross context virtual CPU structure.
8193 * @param cbInstr The instruction length in bytes.
8194 * @param pu32Dst Where to store the VMCS field's value.
8195 * @param u32VmcsField The VMCS field.
8196 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8197 * NULL.
8198 */
8199static VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst,
8200 uint64_t u32VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8201{
8202 uint64_t u64Dst;
8203 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
8204 if (rcStrict == VINF_SUCCESS)
8205 {
8206 *pu32Dst = u64Dst;
8207 iemVmxVmSucceed(pVCpu);
8208 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8209 }
8210
8211 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8212 return rcStrict;
8213}
8214
8215
8216/**
8217 * VMREAD (memory) instruction execution worker.
8218 *
8219 * @returns Strict VBox status code.
8220 * @param pVCpu The cross context virtual CPU structure.
8221 * @param cbInstr The instruction length in bytes.
8222 * @param iEffSeg The effective segment register to use with @a u64Val.
8223 * Pass UINT8_MAX if it is a register access.
8224 * @param GCPtrDst The guest linear address to store the VMCS field's
8225 * value.
8226 * @param u64VmcsField The VMCS field.
8227 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8228 * NULL.
8229 */
8230static VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst,
8231 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8232{
8233 uint64_t u64Dst;
8234 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
8235 if (rcStrict == VINF_SUCCESS)
8236 {
8237 /*
8238 * Write the VMCS field's value to the location specified in guest-memory.
8239 */
8240 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8241 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8242 else
8243 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8244 if (rcStrict == VINF_SUCCESS)
8245 {
8246 iemVmxVmSucceed(pVCpu);
8247 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8248 }
8249
8250 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8251 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8252 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
8253 return rcStrict;
8254 }
8255
8256 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8257 return rcStrict;
8258}
8259
8260
8261/**
8262 * Interface for HM and EM to emulate the VMREAD instruction.
8263 *
8264 * @returns Strict VBox status code.
8265 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8266 * @param pExitInfo Pointer to the VM-exit information.
8267 * @thread EMT(pVCpu)
8268 */
8269VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8270{
8271 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8272 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8273 Assert(pExitInfo);
8274
8275 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8276
8277 VBOXSTRICTRC rcStrict;
8278 uint8_t const cbInstr = pExitInfo->cbInstr;
8279 bool const fIs64BitMode = RT_BOOL(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
8280 uint64_t const u64FieldEnc = fIs64BitMode
8281 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8282 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8283 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8284 {
8285 if (fIs64BitMode)
8286 {
8287 uint64_t *pu64Dst = iemGRegRefU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8288 rcStrict = iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
8289 }
8290 else
8291 {
8292 uint32_t *pu32Dst = iemGRegRefU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8293 rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u64FieldEnc, pExitInfo);
8294 }
8295 }
8296 else
8297 {
8298 RTGCPTR const GCPtrDst = pExitInfo->GCPtrEffAddr;
8299 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8300 rcStrict = iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, pExitInfo);
8301 }
8302 Assert(!pVCpu->iem.s.cActiveMappings);
8303 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8304}
8305
8306
8307/**
8308 * VMWRITE instruction execution worker that does not perform any validation
8309 * checks.
8310 *
8311 * Callers are expected to have performed the necessary checks and to ensure the
8312 * VMWRITE will succeed.
8313 *
8314 * @param pVmcs Pointer to the virtual VMCS.
8315 * @param u64Val The value to write.
8316 * @param u64VmcsField The VMCS field.
8317 *
8318 * @remarks May be called with interrupts disabled.
8319 */
8320static void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField) RT_NOEXCEPT
8321{
8322 VMXVMCSFIELD VmcsField;
8323 VmcsField.u = u64VmcsField;
8324 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8325 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8326 uint8_t const uWidthType = (uWidth << 2) | uType;
8327 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8328 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8329 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8330 Assert(offField < VMX_V_VMCS_SIZE);
8331 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8332
8333 /*
8334 * Write the VMCS component based on the field's effective width.
8335 *
8336 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8337 * indicates high bits (little endian).
8338 */
8339 uint8_t *pbVmcs = (uint8_t *)pVmcs;
8340 uint8_t *pbField = pbVmcs + offField;
8341 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8342 switch (uEffWidth)
8343 {
8344 case VMX_VMCSFIELD_WIDTH_64BIT:
8345 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8346 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8347 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8348 }
8349}
8350
8351
8352/**
8353 * Interface for HM and EM to write a VMCS field in the nested-guest VMCS.
8354 *
8355 * It is ASSUMED the caller knows what they're doing. No VMWRITE instruction checks
8356 * are performed. Bounds checks are strict builds only.
8357 *
8358 * @param pVmcs Pointer to the virtual VMCS.
8359 * @param u64VmcsField The VMCS field.
8360 * @param u64Val The value to write.
8361 *
8362 * @remarks May be called with interrupts disabled.
8363 * @todo This should probably be moved to CPUM someday.
8364 */
8365VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val)
8366{
8367 AssertPtr(pVmcs);
8368 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8369}
8370
8371
8372/**
8373 * VMWRITE instruction execution worker.
8374 *
8375 * @returns Strict VBox status code.
8376 * @param pVCpu The cross context virtual CPU structure.
8377 * @param cbInstr The instruction length in bytes.
8378 * @param iEffSeg The effective segment register to use with @a u64Val.
8379 * Pass UINT8_MAX if it is a register access.
8380 * @param u64Val The value to write (or guest linear address to the
8381 * value), @a iEffSeg will indicate if it's a memory
8382 * operand.
8383 * @param u64VmcsField The VMCS field.
8384 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8385 * NULL.
8386 */
8387static VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val,
8388 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8389{
8390 /* Nested-guest intercept. */
8391 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8392 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8393 {
8394 if (pExitInfo)
8395 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8396 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8397 }
8398
8399 /* CPL. */
8400 if (pVCpu->iem.s.uCpl == 0)
8401 { /* likely */ }
8402 else
8403 {
8404 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8405 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8406 return iemRaiseGeneralProtectionFault0(pVCpu);
8407 }
8408
8409 pVCpu->iem.s.cPotentialExits++;
8410
8411 /* VMCS pointer in root mode. */
8412 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8413 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8414 { /* likely */ }
8415 else
8416 {
8417 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8418 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8419 iemVmxVmFailInvalid(pVCpu);
8420 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8421 }
8422
8423 /* VMCS-link pointer in non-root mode. */
8424 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8425 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8426 { /* likely */ }
8427 else
8428 {
8429 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8430 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8431 iemVmxVmFailInvalid(pVCpu);
8432 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8433 }
8434
8435 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8436 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8437 if (!fIsRegOperand)
8438 {
8439 /* Read the value from the specified guest memory location. */
8440 VBOXSTRICTRC rcStrict;
8441 RTGCPTR const GCPtrVal = u64Val;
8442 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8443 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8444 else
8445 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8446 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8447 {
8448 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8449 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8450 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
8451 return rcStrict;
8452 }
8453 }
8454 else
8455 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8456
8457 /* Supported VMCS field. */
8458 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8459 { /* likely */ }
8460 else
8461 {
8462 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8463 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8464 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8465 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8466 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8467 }
8468
8469 /* Read-only VMCS field. */
8470 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8471 if ( !fIsFieldReadOnly
8472 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8473 { /* likely */ }
8474 else
8475 {
8476 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8477 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8478 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8479 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8480 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8481 }
8482
8483 /*
8484 * Write to the current or shadow VMCS.
8485 */
8486 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8487 PVMXVVMCS pVmcs = !fInVmxNonRootMode
8488 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8489 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8490 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8491 Log4(("vmwrite %#RX64 <= %#RX64\n", u64VmcsField, u64Val));
8492
8493 if ( !fInVmxNonRootMode
8494 && VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8495 {
8496 /* Notify HM that the VMCS content might have changed. */
8497 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8498 }
8499
8500 iemVmxVmSucceed(pVCpu);
8501 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8502}
8503
8504
8505/**
8506 * Interface for HM and EM to emulate the VMWRITE instruction.
8507 *
8508 * @returns Strict VBox status code.
8509 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8510 * @param pExitInfo Pointer to the VM-exit information.
8511 * @thread EMT(pVCpu)
8512 */
8513VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8514{
8515 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8516 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8517 Assert(pExitInfo);
8518
8519 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8520
8521 uint64_t u64Val;
8522 uint8_t iEffSeg;
8523 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8524 {
8525 u64Val = iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8526 iEffSeg = UINT8_MAX;
8527 }
8528 else
8529 {
8530 u64Val = pExitInfo->GCPtrEffAddr;
8531 iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8532 }
8533 uint8_t const cbInstr = pExitInfo->cbInstr;
8534 uint64_t const u64FieldEnc = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
8535 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8536 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8537 VBOXSTRICTRC rcStrict = iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, u64Val, u64FieldEnc, pExitInfo);
8538 Assert(!pVCpu->iem.s.cActiveMappings);
8539 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8540}
8541
8542
8543/**
8544 * VMCLEAR instruction execution worker.
8545 *
8546 * @returns Strict VBox status code.
8547 * @param pVCpu The cross context virtual CPU structure.
8548 * @param cbInstr The instruction length in bytes.
8549 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8550 * @param GCPtrVmcs The linear address of the VMCS pointer.
8551 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8552 *
8553 * @remarks Common VMX instruction checks are already expected to by the caller,
8554 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8555 */
8556static VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8557 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8558{
8559 /* Nested-guest intercept. */
8560 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8561 {
8562 if (pExitInfo)
8563 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8564 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8565 }
8566
8567 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8568
8569 /* CPL. */
8570 if (pVCpu->iem.s.uCpl == 0)
8571 { /* likely */ }
8572 else
8573 {
8574 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8575 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8576 return iemRaiseGeneralProtectionFault0(pVCpu);
8577 }
8578
8579 /* Get the VMCS pointer from the location specified by the source memory operand. */
8580 RTGCPHYS GCPhysVmcs;
8581 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8582 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8583 { /* likely */ }
8584 else
8585 {
8586 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8587 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8588 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8589 return rcStrict;
8590 }
8591
8592 /* VMCS pointer alignment. */
8593 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8594 { /* likely */ }
8595 else
8596 {
8597 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8598 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8599 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8600 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8601 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8602 }
8603
8604 /* VMCS physical-address width limits. */
8605 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8606 { /* likely */ }
8607 else
8608 {
8609 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8610 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8611 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8612 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8613 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8614 }
8615
8616 /* VMCS is not the VMXON region. */
8617 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8618 { /* likely */ }
8619 else
8620 {
8621 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8622 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8623 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8624 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8625 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8626 }
8627
8628 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8629 restriction imposed by our implementation. */
8630 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8631 { /* likely */ }
8632 else
8633 {
8634 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8635 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8636 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8637 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8638 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8639 }
8640
8641 /*
8642 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8643 *
8644 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8645 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8646 * to 'clear'.
8647 */
8648 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8649 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8650 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8651 {
8652 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8653 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8654 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8655 }
8656 else
8657 {
8658 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8659 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8660 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8661 if (RT_FAILURE(rcStrict))
8662 return rcStrict;
8663 }
8664
8665 iemVmxVmSucceed(pVCpu);
8666 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8667}
8668
8669
8670/**
8671 * Interface for HM and EM to emulate the VMCLEAR instruction.
8672 *
8673 * @returns Strict VBox status code.
8674 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8675 * @param pExitInfo Pointer to the VM-exit information.
8676 * @thread EMT(pVCpu)
8677 */
8678VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8679{
8680 Assert(pExitInfo);
8681 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8682 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8683
8684 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8685
8686 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8687 uint8_t const cbInstr = pExitInfo->cbInstr;
8688 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8689 VBOXSTRICTRC rcStrict = iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8690 Assert(!pVCpu->iem.s.cActiveMappings);
8691 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8692}
8693
8694
8695/**
8696 * VMPTRST instruction execution worker.
8697 *
8698 * @returns Strict VBox status code.
8699 * @param pVCpu The cross context virtual CPU structure.
8700 * @param cbInstr The instruction length in bytes.
8701 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8702 * @param GCPtrVmcs The linear address of where to store the current VMCS
8703 * pointer.
8704 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8705 *
8706 * @remarks Common VMX instruction checks are already expected to by the caller,
8707 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8708 */
8709static VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8710 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8711{
8712 /* Nested-guest intercept. */
8713 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8714 {
8715 if (pExitInfo)
8716 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8717 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8718 }
8719
8720 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8721
8722 /* CPL. */
8723 if (pVCpu->iem.s.uCpl == 0)
8724 { /* likely */ }
8725 else
8726 {
8727 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8728 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8729 return iemRaiseGeneralProtectionFault0(pVCpu);
8730 }
8731
8732 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8733 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8734 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8735 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8736 {
8737 iemVmxVmSucceed(pVCpu);
8738 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8739 }
8740
8741 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8742 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8743 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8744 return rcStrict;
8745}
8746
8747
8748/**
8749 * Interface for HM and EM to emulate the VMPTRST instruction.
8750 *
8751 * @returns Strict VBox status code.
8752 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8753 * @param pExitInfo Pointer to the VM-exit information.
8754 * @thread EMT(pVCpu)
8755 */
8756VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8757{
8758 Assert(pExitInfo);
8759 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8760 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8761
8762 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8763
8764 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8765 uint8_t const cbInstr = pExitInfo->cbInstr;
8766 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8767 VBOXSTRICTRC rcStrict = iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8768 Assert(!pVCpu->iem.s.cActiveMappings);
8769 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8770}
8771
8772
8773/**
8774 * VMPTRLD instruction execution worker.
8775 *
8776 * @returns Strict VBox status code.
8777 * @param pVCpu The cross context virtual CPU structure.
8778 * @param cbInstr The instruction length in bytes.
8779 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8780 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8781 *
8782 * @remarks Common VMX instruction checks are already expected to by the caller,
8783 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8784 */
8785static VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8786 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8787{
8788 /* Nested-guest intercept. */
8789 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8790 {
8791 if (pExitInfo)
8792 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8793 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8794 }
8795
8796 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8797
8798 /* CPL. */
8799 if (pVCpu->iem.s.uCpl == 0)
8800 { /* likely */ }
8801 else
8802 {
8803 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8804 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8805 return iemRaiseGeneralProtectionFault0(pVCpu);
8806 }
8807
8808 /* Get the VMCS pointer from the location specified by the source memory operand. */
8809 RTGCPHYS GCPhysVmcs;
8810 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8811 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8812 { /* likely */ }
8813 else
8814 {
8815 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8816 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8817 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8818 return rcStrict;
8819 }
8820
8821 /* VMCS pointer alignment. */
8822 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8823 { /* likely */ }
8824 else
8825 {
8826 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8827 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8828 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8829 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8830 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8831 }
8832
8833 /* VMCS physical-address width limits. */
8834 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8835 { /* likely */ }
8836 else
8837 {
8838 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8839 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8840 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8841 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8842 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8843 }
8844
8845 /* VMCS is not the VMXON region. */
8846 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8847 { /* likely */ }
8848 else
8849 {
8850 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8851 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8852 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8853 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8854 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8855 }
8856
8857 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8858 restriction imposed by our implementation. */
8859 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8860 { /* likely */ }
8861 else
8862 {
8863 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8864 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8865 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8866 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8867 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8868 }
8869
8870 /* Read just the VMCS revision from the VMCS. */
8871 VMXVMCSREVID VmcsRevId;
8872 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8873 if (RT_SUCCESS(rc))
8874 { /* likely */ }
8875 else
8876 {
8877 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8878 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8879 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8880 return rc;
8881 }
8882
8883 /*
8884 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8885 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8886 */
8887 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8888 && ( !VmcsRevId.n.fIsShadowVmcs
8889 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8890 { /* likely */ }
8891 else
8892 {
8893 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8894 {
8895 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8896 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8897 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8898 }
8899 else
8900 {
8901 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8902 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8903 }
8904 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8905 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8906 }
8907
8908 /*
8909 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8910 * the cache of an existing, current VMCS back to guest memory before loading a new,
8911 * different current VMCS.
8912 */
8913 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8914 {
8915 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8916 {
8917 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8918 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8919 }
8920
8921 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8922 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8923 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8924 if (RT_SUCCESS(rc))
8925 {
8926 /* Notify HM that a new, current VMCS is loaded. */
8927 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8928 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8929 }
8930 else
8931 {
8932 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8933 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8934 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8935 return rc;
8936 }
8937 }
8938
8939 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8940 iemVmxVmSucceed(pVCpu);
8941 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8942}
8943
8944
8945/**
8946 * Interface for HM and EM to emulate the VMPTRLD instruction.
8947 *
8948 * @returns Strict VBox status code.
8949 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8950 * @param pExitInfo Pointer to the VM-exit information.
8951 * @thread EMT(pVCpu)
8952 */
8953VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8954{
8955 Assert(pExitInfo);
8956 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8957 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8958
8959 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8960
8961 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8962 uint8_t const cbInstr = pExitInfo->cbInstr;
8963 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8964 VBOXSTRICTRC rcStrict = iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8965 Assert(!pVCpu->iem.s.cActiveMappings);
8966 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8967}
8968
8969
8970/**
8971 * INVVPID instruction execution worker.
8972 *
8973 * @returns Strict VBox status code.
8974 * @param pVCpu The cross context virtual CPU structure.
8975 * @param cbInstr The instruction length in bytes.
8976 * @param iEffSeg The segment of the invvpid descriptor.
8977 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
8978 * @param u64InvvpidType The invalidation type.
8979 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8980 * NULL.
8981 *
8982 * @remarks Common VMX instruction checks are already expected to by the caller,
8983 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8984 */
8985VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
8986 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8987{
8988 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
8989 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
8990 return iemRaiseUndefinedOpcode(pVCpu);
8991
8992 /* Nested-guest intercept. */
8993 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8994 {
8995 if (pExitInfo)
8996 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8997 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
8998 }
8999
9000 /* CPL. */
9001 if (pVCpu->iem.s.uCpl != 0)
9002 {
9003 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
9004 return iemRaiseGeneralProtectionFault0(pVCpu);
9005 }
9006
9007 /*
9008 * Validate INVVPID invalidation type.
9009 *
9010 * The instruction specifies exactly ONE of the supported invalidation types.
9011 *
9012 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9013 * supported. In theory, it's possible for a CPU to not support flushing individual
9014 * addresses but all the other types or any other combination. We do not take any
9015 * shortcuts here by assuming the types we currently expose to the guest.
9016 */
9017 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9018 bool const fInvvpidSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID);
9019 bool const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
9020 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
9021 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
9022 bool const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
9023
9024 bool afSupportedTypes[4];
9025 afSupportedTypes[0] = fTypeIndivAddr;
9026 afSupportedTypes[1] = fTypeSingleCtx;
9027 afSupportedTypes[2] = fTypeAllCtx;
9028 afSupportedTypes[3] = fTypeSingleCtxRetainGlobals;
9029
9030 if ( fInvvpidSupported
9031 && !(u64InvvpidType & ~(uint64_t)VMX_INVVPID_VALID_MASK)
9032 && afSupportedTypes[u64InvvpidType & 3])
9033 { /* likely */ }
9034 else
9035 {
9036 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
9037 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
9038 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9039 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9040 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9041 }
9042
9043 /*
9044 * Fetch the invvpid descriptor from guest memory.
9045 */
9046 RTUINT128U uDesc;
9047 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
9048 if (rcStrict == VINF_SUCCESS)
9049 {
9050 /*
9051 * Validate the descriptor.
9052 */
9053 if (uDesc.s.Lo <= 0xffff)
9054 { /* likely */ }
9055 else
9056 {
9057 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
9058 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
9059 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
9060 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9061 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9062 }
9063
9064 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9065 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
9066 uint16_t const uVpid = uDesc.Words.w0;
9067 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9068 switch (u64InvvpidType)
9069 {
9070 case VMXTLBFLUSHVPID_INDIV_ADDR:
9071 {
9072 if (uVpid != 0)
9073 {
9074 if (IEM_IS_CANONICAL(GCPtrInvAddr))
9075 {
9076 /* Invalidate mappings for the linear address tagged with VPID. */
9077 /** @todo PGM support for VPID? Currently just flush everything. */
9078 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9079 iemVmxVmSucceed(pVCpu);
9080 }
9081 else
9082 {
9083 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
9084 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
9085 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
9086 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9087 }
9088 }
9089 else
9090 {
9091 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9092 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
9093 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9094 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9095 }
9096 break;
9097 }
9098
9099 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
9100 {
9101 if (uVpid != 0)
9102 {
9103 /* Invalidate all mappings with VPID. */
9104 /** @todo PGM support for VPID? Currently just flush everything. */
9105 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9106 iemVmxVmSucceed(pVCpu);
9107 }
9108 else
9109 {
9110 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9111 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
9112 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9113 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9114 }
9115 break;
9116 }
9117
9118 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
9119 {
9120 /* Invalidate all mappings with non-zero VPIDs. */
9121 /** @todo PGM support for VPID? Currently just flush everything. */
9122 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9123 iemVmxVmSucceed(pVCpu);
9124 break;
9125 }
9126
9127 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
9128 {
9129 if (uVpid != 0)
9130 {
9131 /* Invalidate all mappings with VPID except global translations. */
9132 /** @todo PGM support for VPID? Currently just flush everything. */
9133 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9134 iemVmxVmSucceed(pVCpu);
9135 }
9136 else
9137 {
9138 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9139 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
9140 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
9141 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9142 }
9143 break;
9144 }
9145 IEM_NOT_REACHED_DEFAULT_CASE_RET();
9146 }
9147 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9148 }
9149 return rcStrict;
9150}
9151
9152
9153/**
9154 * Interface for HM and EM to emulate the INVVPID instruction.
9155 *
9156 * @returns Strict VBox status code.
9157 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9158 * @param pExitInfo Pointer to the VM-exit information.
9159 * @thread EMT(pVCpu)
9160 */
9161VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9162{
9163 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9164 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9165 Assert(pExitInfo);
9166
9167 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9168
9169 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9170 uint8_t const cbInstr = pExitInfo->cbInstr;
9171 RTGCPTR const GCPtrInvvpidDesc = pExitInfo->GCPtrEffAddr;
9172 uint64_t const u64InvvpidType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9173 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9174 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9175 VBOXSTRICTRC rcStrict = iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, u64InvvpidType, pExitInfo);
9176 Assert(!pVCpu->iem.s.cActiveMappings);
9177 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9178}
9179
9180#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9181
9182/**
9183 * INVEPT instruction execution worker.
9184 *
9185 * @returns Strict VBox status code.
9186 * @param pVCpu The cross context virtual CPU structure.
9187 * @param cbInstr The instruction length in bytes.
9188 * @param iEffSeg The segment of the invept descriptor.
9189 * @param GCPtrInveptDesc The address of invept descriptor.
9190 * @param u64InveptType The invalidation type.
9191 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9192 * NULL.
9193 *
9194 * @remarks Common VMX instruction checks are already expected to by the caller,
9195 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9196 */
9197static VBOXSTRICTRC iemVmxInvept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInveptDesc,
9198 uint64_t u64InveptType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9199{
9200 /* Check if EPT is supported, otherwise raise #UD. */
9201 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEpt)
9202 return iemRaiseUndefinedOpcode(pVCpu);
9203
9204 /* Nested-guest intercept. */
9205 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9206 {
9207 if (pExitInfo)
9208 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9209 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVEPT, VMXINSTRID_NONE, cbInstr);
9210 }
9211
9212 /* CPL. */
9213 if (pVCpu->iem.s.uCpl != 0)
9214 {
9215 Log(("invept: CPL != 0 -> #GP(0)\n"));
9216 return iemRaiseGeneralProtectionFault0(pVCpu);
9217 }
9218
9219 /*
9220 * Validate INVEPT invalidation type.
9221 *
9222 * The instruction specifies exactly ONE of the supported invalidation types.
9223 *
9224 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9225 * supported. In theory, it's possible for a CPU to not support flushing individual
9226 * addresses but all the other types or any other combination. We do not take any
9227 * shortcuts here by assuming the types we currently expose to the guest.
9228 */
9229 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9230 bool const fInveptSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT);
9231 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
9232 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
9233
9234 bool afSupportedTypes[4];
9235 afSupportedTypes[0] = false;
9236 afSupportedTypes[1] = fTypeSingleCtx;
9237 afSupportedTypes[2] = fTypeAllCtx;
9238 afSupportedTypes[3] = false;
9239
9240 if ( fInveptSupported
9241 && !(u64InveptType & ~(uint64_t)VMX_INVEPT_VALID_MASK)
9242 && afSupportedTypes[u64InveptType & 3])
9243 { /* likely */ }
9244 else
9245 {
9246 Log(("invept: invalid/unsupported invvpid type %#x -> VMFail\n", u64InveptType));
9247 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_TypeInvalid;
9248 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType;
9249 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9250 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9251 }
9252
9253 /*
9254 * Fetch the invept descriptor from guest memory.
9255 */
9256 RTUINT128U uDesc;
9257 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInveptDesc);
9258 if (rcStrict == VINF_SUCCESS)
9259 {
9260 /*
9261 * Validate the descriptor.
9262 *
9263 * The Intel spec. does not explicit say the INVEPT instruction fails when reserved
9264 * bits in the descriptor are set, but it -does- for INVVPID. Until we test on real
9265 * hardware, it's assumed INVEPT behaves the same as INVVPID in this regard. It's
9266 * better to be strict in our emulation until proven otherwise.
9267 */
9268 if (uDesc.s.Hi)
9269 {
9270 Log(("invept: reserved bits set in invept descriptor %#RX64 -> VMFail\n", uDesc.s.Hi));
9271 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_DescRsvd;
9272 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi;
9273 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9274 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9275 }
9276
9277 /*
9278 * Flush TLB mappings based on the EPT type.
9279 */
9280 if (u64InveptType == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
9281 {
9282 uint64_t const GCPhysEptPtr = uDesc.s.Lo;
9283 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, GCPhysEptPtr, NULL /* enmDiag */);
9284 if (RT_SUCCESS(rc))
9285 { /* likely */ }
9286 else
9287 {
9288 Log(("invept: EPTP invalid %#RX64 -> VMFail\n", GCPhysEptPtr));
9289 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_EptpInvalid;
9290 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr;
9291 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9292 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9293 }
9294 }
9295
9296 /** @todo PGM support for EPT tags? Currently just flush everything. */
9297 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9298 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9299 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9300
9301 iemVmxVmSucceed(pVCpu);
9302 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9303 }
9304
9305 return rcStrict;
9306}
9307
9308
9309/**
9310 * Interface for HM and EM to emulate the INVEPT instruction.
9311 *
9312 * @returns Strict VBox status code.
9313 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9314 * @param pExitInfo Pointer to the VM-exit information.
9315 * @thread EMT(pVCpu)
9316 */
9317VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9318{
9319 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9320 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9321 Assert(pExitInfo);
9322
9323 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9324
9325 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9326 uint8_t const cbInstr = pExitInfo->cbInstr;
9327 RTGCPTR const GCPtrInveptDesc = pExitInfo->GCPtrEffAddr;
9328 uint64_t const u64InveptType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9329 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9330 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9331 VBOXSTRICTRC rcStrict = iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, u64InveptType, pExitInfo);
9332 Assert(!pVCpu->iem.s.cActiveMappings);
9333 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9334}
9335
9336#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
9337
9338/**
9339 * VMXON instruction execution worker.
9340 *
9341 * @returns Strict VBox status code.
9342 * @param pVCpu The cross context virtual CPU structure.
9343 * @param cbInstr The instruction length in bytes.
9344 * @param iEffSeg The effective segment register to use with @a
9345 * GCPtrVmxon.
9346 * @param GCPtrVmxon The linear address of the VMXON pointer.
9347 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
9348 *
9349 * @remarks Common VMX instruction checks are already expected to by the caller,
9350 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9351 */
9352static VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
9353 RTGCPHYS GCPtrVmxon, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9354{
9355 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
9356 {
9357 /* CPL. */
9358 if (pVCpu->iem.s.uCpl == 0)
9359 { /* likely */ }
9360 else
9361 {
9362 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9363 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
9364 return iemRaiseGeneralProtectionFault0(pVCpu);
9365 }
9366
9367 /* A20M (A20 Masked) mode. */
9368 if (PGMPhysIsA20Enabled(pVCpu))
9369 { /* likely */ }
9370 else
9371 {
9372 Log(("vmxon: A20M mode -> #GP(0)\n"));
9373 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
9374 return iemRaiseGeneralProtectionFault0(pVCpu);
9375 }
9376
9377 /* CR0. */
9378 {
9379 /*
9380 * CR0 MB1 bits.
9381 *
9382 * We use VMX_V_CR0_FIXED0 below to ensure CR0.PE and CR0.PG are always set
9383 * while executing VMXON. CR0.PE and CR0.PG are only allowed to be clear
9384 * when the guest running in VMX non-root mode with unrestricted-guest control
9385 * enabled in the VMCS.
9386 */
9387 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
9388 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
9389 { /* likely */ }
9390 else
9391 {
9392 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
9393 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
9394 return iemRaiseGeneralProtectionFault0(pVCpu);
9395 }
9396
9397 /* CR0 MBZ bits. */
9398 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
9399 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
9400 { /* likely */ }
9401 else
9402 {
9403 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
9404 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
9405 return iemRaiseGeneralProtectionFault0(pVCpu);
9406 }
9407 }
9408
9409 /* CR4. */
9410 {
9411 /* CR4 MB1 bits. */
9412 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
9413 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
9414 { /* likely */ }
9415 else
9416 {
9417 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
9418 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
9419 return iemRaiseGeneralProtectionFault0(pVCpu);
9420 }
9421
9422 /* CR4 MBZ bits. */
9423 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
9424 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
9425 { /* likely */ }
9426 else
9427 {
9428 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
9429 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
9430 return iemRaiseGeneralProtectionFault0(pVCpu);
9431 }
9432 }
9433
9434 /* Feature control MSR's LOCK and VMXON bits. */
9435 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
9436 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9437 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9438 { /* likely */ }
9439 else
9440 {
9441 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
9442 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
9443 return iemRaiseGeneralProtectionFault0(pVCpu);
9444 }
9445
9446 /* Get the VMXON pointer from the location specified by the source memory operand. */
9447 RTGCPHYS GCPhysVmxon;
9448 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
9449 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
9450 { /* likely */ }
9451 else
9452 {
9453 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
9454 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
9455 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
9456 return rcStrict;
9457 }
9458
9459 /* VMXON region pointer alignment. */
9460 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
9461 { /* likely */ }
9462 else
9463 {
9464 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
9465 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
9466 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9467 iemVmxVmFailInvalid(pVCpu);
9468 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9469 }
9470
9471 /* VMXON physical-address width limits. */
9472 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
9473 { /* likely */ }
9474 else
9475 {
9476 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
9477 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
9478 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9479 iemVmxVmFailInvalid(pVCpu);
9480 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9481 }
9482
9483 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
9484 restriction imposed by our implementation. */
9485 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
9486 { /* likely */ }
9487 else
9488 {
9489 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
9490 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
9491 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9492 iemVmxVmFailInvalid(pVCpu);
9493 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9494 }
9495
9496 /* Read the VMCS revision ID from the VMXON region. */
9497 VMXVMCSREVID VmcsRevId;
9498 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
9499 if (RT_SUCCESS(rc))
9500 { /* likely */ }
9501 else
9502 {
9503 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
9504 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
9505 return rc;
9506 }
9507
9508 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
9509 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
9510 { /* likely */ }
9511 else
9512 {
9513 /* Revision ID mismatch. */
9514 if (!VmcsRevId.n.fIsShadowVmcs)
9515 {
9516 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
9517 VmcsRevId.n.u31RevisionId));
9518 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
9519 iemVmxVmFailInvalid(pVCpu);
9520 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9521 }
9522
9523 /* Shadow VMCS disallowed. */
9524 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
9525 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
9526 iemVmxVmFailInvalid(pVCpu);
9527 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9528 }
9529
9530 /*
9531 * Record that we're in VMX operation, block INIT, block and disable A20M.
9532 */
9533 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
9534 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
9535 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
9536
9537 /* Clear address-range monitoring. */
9538 EMMonitorWaitClear(pVCpu);
9539 /** @todo NSTVMX: Intel PT. */
9540
9541 iemVmxVmSucceed(pVCpu);
9542 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9543 }
9544 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9545 {
9546 /* Nested-guest intercept. */
9547 if (pExitInfo)
9548 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9549 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
9550 }
9551
9552 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
9553
9554 /* CPL. */
9555 if (pVCpu->iem.s.uCpl > 0)
9556 {
9557 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9558 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
9559 return iemRaiseGeneralProtectionFault0(pVCpu);
9560 }
9561
9562 /* VMXON when already in VMX root mode. */
9563 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
9564 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
9565 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9566}
9567
9568
9569/**
9570 * Interface for HM and EM to emulate the VMXON instruction.
9571 *
9572 * @returns Strict VBox status code.
9573 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9574 * @param pExitInfo Pointer to the VM-exit information.
9575 * @thread EMT(pVCpu)
9576 */
9577VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9578{
9579 Assert(pExitInfo);
9580 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
9581 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9582
9583 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9584
9585 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
9586 uint8_t const cbInstr = pExitInfo->cbInstr;
9587 RTGCPTR const GCPtrVmxon = pExitInfo->GCPtrEffAddr;
9588 VBOXSTRICTRC rcStrict = iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
9589 Assert(!pVCpu->iem.s.cActiveMappings);
9590 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9591}
9592
9593
9594/**
9595 * Implements 'VMXOFF'.
9596 *
9597 * @remarks Common VMX instruction checks are already expected to by the caller,
9598 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9599 */
9600IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
9601{
9602 /* Nested-guest intercept. */
9603 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9604 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9605
9606 /* CPL. */
9607 if (pVCpu->iem.s.uCpl == 0)
9608 { /* likely */ }
9609 else
9610 {
9611 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9612 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9613 return iemRaiseGeneralProtectionFault0(pVCpu);
9614 }
9615
9616 /* Dual monitor treatment of SMIs and SMM. */
9617 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9618 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9619 { /* likely */ }
9620 else
9621 {
9622 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9623 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9624 }
9625
9626 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9627 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9628 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9629
9630 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9631 { /** @todo NSTVMX: Unblock SMI. */ }
9632
9633 EMMonitorWaitClear(pVCpu);
9634 /** @todo NSTVMX: Unblock and enable A20M. */
9635
9636 iemVmxVmSucceed(pVCpu);
9637 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9638}
9639
9640
9641/**
9642 * Interface for HM and EM to emulate the VMXOFF instruction.
9643 *
9644 * @returns Strict VBox status code.
9645 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9646 * @param cbInstr The instruction length in bytes.
9647 * @thread EMT(pVCpu)
9648 */
9649VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr)
9650{
9651 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
9652 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9653
9654 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9655 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmxoff);
9656 Assert(!pVCpu->iem.s.cActiveMappings);
9657 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9658}
9659
9660
9661/**
9662 * Implements 'VMXON'.
9663 */
9664IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9665{
9666 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9667}
9668
9669
9670/**
9671 * Implements 'VMLAUNCH'.
9672 */
9673IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9674{
9675 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9676}
9677
9678
9679/**
9680 * Implements 'VMRESUME'.
9681 */
9682IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9683{
9684 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9685}
9686
9687
9688/**
9689 * Implements 'VMPTRLD'.
9690 */
9691IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9692{
9693 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9694}
9695
9696
9697/**
9698 * Implements 'VMPTRST'.
9699 */
9700IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9701{
9702 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9703}
9704
9705
9706/**
9707 * Implements 'VMCLEAR'.
9708 */
9709IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9710{
9711 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9712}
9713
9714
9715/**
9716 * Implements 'VMWRITE' register.
9717 */
9718IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9719{
9720 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9721}
9722
9723
9724/**
9725 * Implements 'VMWRITE' memory.
9726 */
9727IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9728{
9729 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9730}
9731
9732
9733/**
9734 * Implements 'VMREAD' register (64-bit).
9735 */
9736IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9737{
9738 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9739}
9740
9741
9742/**
9743 * Implements 'VMREAD' register (32-bit).
9744 */
9745IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint64_t *, pu64Dst, uint32_t, u32VmcsField)
9746{
9747 VBOXSTRICTRC const rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, (uint32_t *)pu64Dst, u32VmcsField, NULL /* pExitInfo */);
9748 /* Zero the high part of the register on success. */
9749 if (rcStrict == VINF_SUCCESS)
9750 *pu64Dst = (uint32_t)*pu64Dst;
9751 return rcStrict;
9752}
9753
9754
9755/**
9756 * Implements 'VMREAD' memory, 64-bit register.
9757 */
9758IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9759{
9760 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9761}
9762
9763
9764/**
9765 * Implements 'VMREAD' memory, 32-bit register.
9766 */
9767IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9768{
9769 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9770}
9771
9772
9773/**
9774 * Implements 'INVVPID'.
9775 */
9776IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9777{
9778 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9779}
9780
9781
9782#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9783/**
9784 * Implements 'INVEPT'.
9785 */
9786IEM_CIMPL_DEF_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType)
9787{
9788 return iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType, NULL /* pExitInfo */);
9789}
9790#endif
9791
9792
9793/**
9794 * Implements VMX's implementation of PAUSE.
9795 */
9796IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9797{
9798 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9799 {
9800 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9801 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9802 return rcStrict;
9803 }
9804
9805 /*
9806 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9807 * a VM-exit, the instruction operates normally.
9808 */
9809 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9810}
9811
9812#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9813
9814
9815/**
9816 * Implements 'VMCALL'.
9817 */
9818IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9819{
9820 pVCpu->iem.s.cPotentialExits++;
9821
9822#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9823 /* Nested-guest intercept. */
9824 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9825 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9826#endif
9827
9828 /* Join forces with vmmcall. */
9829 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9830}
9831
9832
9833#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9834
9835/**
9836 * @callback_method_impl{FNPGMPHYSHANDLER, VMX APIC-access page accesses}
9837 *
9838 * @remarks The @a uUser argument is currently unused.
9839 */
9840DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPageHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, void *pvPhys,
9841 void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
9842 PGMACCESSORIGIN enmOrigin, uint64_t uUser)
9843{
9844 RT_NOREF3(pvPhys, enmOrigin, uUser);
9845
9846 RTGCPHYS const GCPhysAccessBase = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9847 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9848 {
9849 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9850 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysAccessBase);
9851
9852 uint32_t const fAccess = enmAccessType == PGMACCESSTYPE_WRITE ? IEM_ACCESS_DATA_W : IEM_ACCESS_DATA_R;
9853 uint16_t const offAccess = GCPhysFault & GUEST_PAGE_OFFSET_MASK;
9854
9855 LogFlowFunc(("Fault at %#RGp (cbBuf=%u fAccess=%#x)\n", GCPhysFault, cbBuf, fAccess));
9856 VBOXSTRICTRC rcStrict = iemVmxVirtApicAccessMem(pVCpu, offAccess, cbBuf, pvBuf, fAccess);
9857 if (RT_FAILURE(rcStrict))
9858 return rcStrict;
9859
9860 /* Any access on this APIC-access page has been handled, caller should not carry out the access. */
9861 return VINF_SUCCESS;
9862 }
9863
9864 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysAccessBase));
9865 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhysAccessBase);
9866 if (RT_FAILURE(rc))
9867 return rc;
9868
9869 /* Instruct the caller of this handler to perform the read/write as normal memory. */
9870 return VINF_PGM_HANDLER_DO_DEFAULT;
9871}
9872
9873
9874# ifndef IN_RING3
9875/**
9876 * @callback_method_impl{FNPGMRZPHYSPFHANDLER,
9877 * \#PF access handler callback for guest VMX APIC-access page.}
9878 */
9879DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
9880 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
9881
9882{
9883 RT_NOREF3(pVM, pCtx, uUser);
9884
9885 /*
9886 * Handle the VMX APIC-access page only when the guest is in VMX non-root mode.
9887 * Otherwise we must deregister the page and allow regular RAM access.
9888 * Failing to do so lands us with endless EPT VM-exits.
9889 */
9890 RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9891 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9892 {
9893 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9894 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysPage);
9895
9896 /*
9897 * Check if the access causes an APIC-access VM-exit.
9898 */
9899 uint32_t fAccess;
9900 if (uErr & X86_TRAP_PF_ID)
9901 fAccess = IEM_ACCESS_INSTRUCTION;
9902 else if (uErr & X86_TRAP_PF_RW)
9903 fAccess = IEM_ACCESS_DATA_W;
9904 else
9905 fAccess = IEM_ACCESS_DATA_R;
9906
9907 RTGCPHYS const GCPhysNestedFault = (RTGCPHYS)pvFault;
9908 uint16_t const offAccess = GCPhysNestedFault & GUEST_PAGE_OFFSET_MASK;
9909 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, 1 /* cbAccess */, fAccess);
9910 LogFlowFunc(("#PF at %#RGp (GCPhysNestedFault=%#RGp offAccess=%#x)\n", GCPhysFault, GCPhysNestedFault, offAccess));
9911 if (fIntercept)
9912 {
9913 /*
9914 * Query the source VM-exit (from the execution engine) that caused this access
9915 * within the APIC-access page. Currently only HM is supported.
9916 */
9917 AssertMsg(VM_IS_HM_ENABLED(pVM),
9918 ("VM-exit auxiliary info. fetching not supported for execution engine %d\n", pVM->bMainExecutionEngine));
9919
9920 HMEXITAUX HmExitAux;
9921 RT_ZERO(HmExitAux);
9922 int const rc = HMR0GetExitAuxInfo(pVCpu, &HmExitAux, HMVMX_READ_EXIT_INSTR_LEN
9923 | HMVMX_READ_EXIT_QUALIFICATION
9924 | HMVMX_READ_IDT_VECTORING_INFO
9925 | HMVMX_READ_IDT_VECTORING_ERROR_CODE);
9926 AssertRC(rc);
9927
9928 /*
9929 * Verify the VM-exit reason must be an EPT violation.
9930 * Other accesses should go through the other handler (iemVmxApicAccessPageHandler).
9931 * Refer to @bugref{10092#c33s} for a more detailed explanation.
9932 */
9933 AssertMsgReturn(HmExitAux.Vmx.uReason == VMX_EXIT_EPT_VIOLATION,
9934 ("Unexpected call to APIC-access page #PF handler for %#RGp offAcesss=%u uErr=%#RGx uReason=%u\n",
9935 GCPhysPage, offAccess, uErr, HmExitAux.Vmx.uReason), VERR_IEM_IPE_7);
9936
9937 /*
9938 * Construct the virtual APIC-access VM-exit.
9939 */
9940 VMXAPICACCESS enmAccess;
9941 if (HmExitAux.Vmx.u64Qual & VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID)
9942 {
9943 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9944 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
9945 else if (fAccess == IEM_ACCESS_INSTRUCTION)
9946 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
9947 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
9948 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
9949 else
9950 enmAccess = VMXAPICACCESS_LINEAR_READ;
9951
9952 /* For linear-address accesss the instruction length must be valid. */
9953 AssertMsg(HmExitAux.Vmx.cbInstr > 0,
9954 ("Invalid APIC-access VM-exit instruction length. cbInstr=%u\n", HmExitAux.Vmx.cbInstr));
9955 }
9956 else
9957 {
9958 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9959 enmAccess = VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY;
9960 else
9961 {
9962 /** @todo How to distinguish between monitoring/trace vs other instructions
9963 * here? */
9964 enmAccess = VMXAPICACCESS_PHYSICAL_INSTR;
9965 }
9966
9967 /* For physical accesses the instruction length is undefined, we zero it for safety and consistency. */
9968 HmExitAux.Vmx.cbInstr = 0;
9969 }
9970
9971 /*
9972 * Raise the APIC-access VM-exit.
9973 */
9974 LogFlowFunc(("Raising APIC-access VM-exit from #PF handler at offset %#x\n", offAccess));
9975 VMXVEXITINFO const ExitInfo
9976 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_APIC_ACCESS,
9977 RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
9978 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess),
9979 HmExitAux.Vmx.cbInstr);
9980 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_IDT(HmExitAux.Vmx.uIdtVectoringInfo,
9981 HmExitAux.Vmx.uIdtVectoringErrCode);
9982 VBOXSTRICTRC const rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
9983 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
9984 }
9985
9986 /*
9987 * The access isn't intercepted, which means it needs to be virtualized.
9988 *
9989 * This requires emulating the instruction because we need the bytes being
9990 * read/written by the instruction not just the offset being accessed within
9991 * the APIC-access page (which we derive from the faulting address).
9992 */
9993 LogFlowFunc(("Access at offset %#x not intercepted -> VINF_EM_RAW_EMULATE_INSTR\n", offAccess));
9994 return VINF_EM_RAW_EMULATE_INSTR;
9995 }
9996
9997 /** @todo This isn't ideal but works for now as nested-hypervisors generally play
9998 * nice because the spec states that this page should be modified only when
9999 * no CPU refers to it VMX non-root mode. Nonetheless, we could use an atomic
10000 * reference counter to ensure the aforementioned condition before
10001 * de-registering the page. */
10002 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysPage));
10003 int const rc = PGMHandlerPhysicalDeregister(pVM, GCPhysPage);
10004 if (RT_FAILURE(rc))
10005 return rc;
10006
10007 return VINF_SUCCESS;
10008}
10009# endif /* !IN_RING3 */
10010
10011#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
10012
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