IEMAllCImplVmxInstr.cpp@ 102020

Last change on this file since 102020 was 102020, checked in by vboxsync, 13 months ago
VMM: Nested VMX: bugref:10318 Discard unused VMCS launch-state bits and update 'VMCLEAR' VMCS launch-state bit to be 0.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 412.7 KB

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1	/* $Id: IEMAllCImplVmxInstr.cpp 102020 2023-11-09 11:27:42Z vboxsync $ */
2	/** @file
3	* IEM - VT-x instruction implementation.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_IEM_VMX
33	#define VMCPU_INCL_CPUM_GST_CTX
34	#include <VBox/vmm/iem.h>
35	#include <VBox/vmm/apic.h>
36	#include <VBox/vmm/cpum.h>
37	#include <VBox/vmm/dbgf.h>
38	#include <VBox/vmm/em.h>
39	#include <VBox/vmm/gim.h>
40	#include <VBox/vmm/hm.h>
41	#include <VBox/vmm/pgm.h>
42	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
43	# include <VBox/vmm/hmvmxinline.h>
44	#endif
45	#include <VBox/vmm/tm.h>
46	#include "IEMInternal.h"
47	#include <VBox/vmm/vmcc.h>
48	#include <VBox/log.h>
49	#include <VBox/err.h>
50	#include <VBox/param.h>
51	#include <VBox/disopcode-x86-amd64.h>
52	#include <iprt/asm-math.h>
53	#include <iprt/assert.h>
54	#include <iprt/string.h>
55	#include <iprt/x86.h>
56
57	#include "IEMInline.h"
58
59
60	/*********************************************************************************************************************************
61	* Defined Constants And Macros *
62	*********************************************************************************************************************************/
63	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
64	/**
65	* Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
66	* relative offsets.
67	*/
68	# ifdef IEM_WITH_CODE_TLB /** @todo IEM TLB */
69	# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { a_bModRm = 0; RT_NOREF(a_offModRm); } while (0)
70	# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { a_bSib = 0; RT_NOREF(a_offSib); } while (0)
71	# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
72	# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
73	# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
74	# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
75	# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
76	# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
77	# if 0
78	# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
79	# endif
80	# else /* !IEM_WITH_CODE_TLB */
81	# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
82	do \
83	{ \
84	Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
85	(a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
86	} while (0)
87
88	# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
89
90	# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
91	do \
92	{ \
93	Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
94	uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
95	uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
96	(a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
97	} while (0)
98
99	# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
100	do \
101	{ \
102	Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
103	(a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
104	} while (0)
105
106	# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
107	do \
108	{ \
109	Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
110	uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
111	uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
112	uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
113	uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
114	(a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
115	} while (0)
116
117	# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
118	do \
119	{ \
120	Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
121	(a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
122	} while (0)
123
124	# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
125	do \
126	{ \
127	Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
128	(a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
129	} while (0)
130
131	# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
132	do \
133	{ \
134	Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
135	uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
136	uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
137	uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
138	uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
139	(a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
140	} while (0)
141	# endif /* !IEM_WITH_CODE_TLB */
142
143	/** Check for VMX instructions requiring to be in VMX operation.
144	* @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
145	# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
146	do \
147	{ \
148	if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
149	{ /* likely */ } \
150	else \
151	{ \
152	Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
153	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
154	return iemRaiseUndefinedOpcode(a_pVCpu); \
155	} \
156	} while (0)
157
158	/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
159	# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
160	do \
161	{ \
162	LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
163	HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
164	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
165	return VERR_VMX_VMENTRY_FAILED; \
166	} while (0)
167
168	/** Marks a VM-entry failure with an return code, diagnostic reason, logs and
169	* returns. */
170	# define IEM_VMX_VMENTRY_FAILED_RET_2(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag, a_rc) \
171	do \
172	{ \
173	LogRel(("%s: VM-entry failed! rc=%Rrc enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_rc), (a_VmxDiag), \
174	HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
175	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
176	return VERR_VMX_VMENTRY_FAILED; \
177	} while (0)
178
179	/** Marks a VM-exit failure with a diagnostic reason and logs. */
180	# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
181	do \
182	{ \
183	LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
184	HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
185	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
186	} while (0)
187
188	/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
189	# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
190	do \
191	{ \
192	IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
193	return VERR_VMX_VMEXIT_FAILED; \
194	} while (0)
195
196
197	/*********************************************************************************************************************************
198	* Global Variables *
199	*********************************************************************************************************************************/
200	/** @todo NSTVMX: The following VM-exit intercepts are pending:
201	* VMX_EXIT_IO_SMI
202	* VMX_EXIT_SMI
203	* VMX_EXIT_GETSEC
204	* VMX_EXIT_RSM
205	* VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
206	* VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
207	* VMX_EXIT_VMFUNC
208	* VMX_EXIT_ENCLS
209	* VMX_EXIT_PML_FULL
210	* VMX_EXIT_XSAVES
211	* VMX_EXIT_XRSTORS
212	*/
213	/**
214	* Map of VMCS field encodings to their virtual-VMCS structure offsets.
215	*
216	* The first array dimension is VMCS field encoding of Width OR'ed with Type and the
217	* second dimension is the Index, see VMXVMCSFIELD.
218	*/
219	uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
220	{
221	/* VMX_VMCSFIELD_WIDTH_16BIT \| VMX_VMCSFIELD_TYPE_CONTROL: */
222	{
223	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
224	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
225	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
226	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u16HlatPrefixSize),
227	/* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
228	/* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
229	/* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
230	/* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
231	},
232	/* VMX_VMCSFIELD_WIDTH_16BIT \| VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
233	{
234	/* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
235	/* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
236	/* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
237	/* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
238	/* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
239	},
240	/* VMX_VMCSFIELD_WIDTH_16BIT \| VMX_VMCSFIELD_TYPE_GUEST_STATE: */
241	{
242	/* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
243	/* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
244	/* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
245	/* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
246	/* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
247	/* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
248	/* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
249	/* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
250	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
251	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
252	/* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
253	/* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
254	/* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
255	/* 34 */ UINT16_MAX
256	},
257	/* VMX_VMCSFIELD_WIDTH_16BIT \| VMX_VMCSFIELD_TYPE_HOST_STATE: */
258	{
259	/* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
260	/* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
261	/* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
262	/* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
263	/* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
264	/* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
265	/* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
266	/* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
267	/* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
268	/* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
269	/* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
270	},
271	/* VMX_VMCSFIELD_WIDTH_64BIT \| VMX_VMCSFIELD_TYPE_CONTROL: */
272	{
273	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
274	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
275	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
276	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
277	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
278	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
279	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
280	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
281	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
282	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
283	/* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
284	/* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
285	/* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
286	/* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
287	/* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
288	/* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
289	/* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
290	/* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
291	/* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
292	/* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
293	/* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
294	/* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
295	/* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
296	/* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
297	/* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
298	/* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
299	/* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
300	/* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap),
301	/* 28 */ UINT16_MAX,
302	/* 29 */ UINT16_MAX,
303	/* 30 */ UINT16_MAX,
304	/* 31 */ RT_UOFFSETOF(VMXVVMCS, u64PconfigExitBitmap),
305	/* 32 */ RT_UOFFSETOF(VMXVVMCS, u64HlatPtr),
306	/* 33 */ UINT16_MAX,
307	/* 34 */ RT_UOFFSETOF(VMXVVMCS, u64ExitCtls2)
308	},
309	/* VMX_VMCSFIELD_WIDTH_64BIT \| VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
310	{
311	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
312	/* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
313	/* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
314	/* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
315	/* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
316	/* 33-34*/ UINT16_MAX, UINT16_MAX
317	},
318	/* VMX_VMCSFIELD_WIDTH_64BIT \| VMX_VMCSFIELD_TYPE_GUEST_STATE: */
319	{
320	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
321	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
322	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
323	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
324	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
325	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
326	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
327	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
328	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
329	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
330	/* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
331	/* 11 */ UINT16_MAX,
332	/* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
333	/* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
334	/* 21-28 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335	/* 29-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
336	},
337	/* VMX_VMCSFIELD_WIDTH_64BIT \| VMX_VMCSFIELD_TYPE_HOST_STATE: */
338	{
339	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
340	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
341	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
342	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
343	/* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
344	/* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
345	/* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
346	/* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
347	},
348	/* VMX_VMCSFIELD_WIDTH_32BIT \| VMX_VMCSFIELD_TYPE_CONTROL: */
349	{
350	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
351	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
352	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
353	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
354	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
355	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
356	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
357	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
358	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
359	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
360	/* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
361	/* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
362	/* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
363	/* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
364	/* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
365	/* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
366	/* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
367	/* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
368	/* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
369	/* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
370	/* 34 */ UINT16_MAX
371	},
372	/* VMX_VMCSFIELD_WIDTH_32BIT \| VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
373	{
374	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
375	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
376	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
377	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
378	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
379	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
380	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
381	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
382	/* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
383	/* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
384	/* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
385	/* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
386	},
387	/* VMX_VMCSFIELD_WIDTH_32BIT \| VMX_VMCSFIELD_TYPE_GUEST_STATE: */
388	{
389	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
390	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
391	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
392	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
393	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
394	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
395	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
396	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
397	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
398	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
399	/* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
400	/* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
401	/* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
402	/* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
403	/* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
404	/* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
405	/* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
406	/* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
407	/* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
408	/* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
409	/* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
410	/* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
411	/* 22 */ UINT16_MAX,
412	/* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
413	/* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
414	/* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
415	},
416	/* VMX_VMCSFIELD_WIDTH_32BIT \| VMX_VMCSFIELD_TYPE_HOST_STATE: */
417	{
418	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
419	/* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
420	/* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
421	/* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
422	/* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
423	/* 33-34 */ UINT16_MAX, UINT16_MAX
424	},
425	/* VMX_VMCSFIELD_WIDTH_NATURAL \| VMX_VMCSFIELD_TYPE_CONTROL: */
426	{
427	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
428	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
429	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
430	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
431	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
432	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
433	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
434	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
435	/* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
436	/* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
437	/* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
438	/* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
439	},
440	/* VMX_VMCSFIELD_WIDTH_NATURAL \| VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
441	{
442	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
443	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
444	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
445	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
446	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
447	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
448	/* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
449	/* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
450	/* 22-29 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
451	/* 30-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
452	},
453	/* VMX_VMCSFIELD_WIDTH_NATURAL \| VMX_VMCSFIELD_TYPE_GUEST_STATE: */
454	{
455	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
456	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
457	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
458	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
459	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
460	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
461	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
462	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
463	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
464	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
465	/* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
466	/* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
467	/* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
468	/* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
469	/* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
470	/* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
471	/* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
472	/* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
473	/* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
474	/* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
475	/* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
476	/* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
477	/* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
478	/* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
479	/* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
480	},
481	/* VMX_VMCSFIELD_WIDTH_NATURAL \| VMX_VMCSFIELD_TYPE_HOST_STATE: */
482	{
483	/* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
484	/* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
485	/* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
486	/* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
487	/* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
488	/* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
489	/* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
490	/* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
491	/* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
492	/* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
493	/* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
494	/* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
495	/* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
496	/* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
497	/* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
498	/* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
499	/* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
500	/* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
501	}
502	};
503
504
505	/**
506	* Gets a host selector from the VMCS.
507	*
508	* @param pVmcs Pointer to the virtual VMCS.
509	* @param iSelReg The index of the segment register (X86_SREG_XXX).
510	*/
511	DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
512	{
513	Assert(iSegReg < X86_SREG_COUNT);
514	RTSEL HostSel;
515	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
516	uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
517	uint8_t const uWidthType = (uWidth << 2) \| uType;
518	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
519	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
520	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
521	uint8_t const pbVmcs = (uint8_t )pVmcs;
522	uint8_t const *pbField = pbVmcs + offField;
523	HostSel = (uint16_t )pbField;
524	return HostSel;
525	}
526
527
528	/**
529	* Sets a guest segment register in the VMCS.
530	*
531	* @param pVmcs Pointer to the virtual VMCS.
532	* @param iSegReg The index of the segment register (X86_SREG_XXX).
533	* @param pSelReg Pointer to the segment register.
534	*/
535	static void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg) RT_NOEXCEPT
536	{
537	Assert(pSelReg);
538	Assert(iSegReg < X86_SREG_COUNT);
539
540	/* Selector. */
541	{
542	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
543	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
544	uint8_t const uWidthType = (uWidth << 2) \| uType;
545	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
546	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
547	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
548	uint8_t pbVmcs = (uint8_t )pVmcs;
549	uint8_t *pbField = pbVmcs + offField;
550	(uint16_t )pbField = pSelReg->Sel;
551	}
552
553	/* Limit. */
554	{
555	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
556	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
557	uint8_t const uWidthType = (uWidth << 2) \| uType;
558	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
559	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
560	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
561	uint8_t pbVmcs = (uint8_t )pVmcs;
562	uint8_t *pbField = pbVmcs + offField;
563	(uint32_t )pbField = pSelReg->u32Limit;
564	}
565
566	/* Base. */
567	{
568	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
569	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
570	uint8_t const uWidthType = (uWidth << 2) \| uType;
571	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
572	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
573	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
574	uint8_t const pbVmcs = (uint8_t )pVmcs;
575	uint8_t const *pbField = pbVmcs + offField;
576	(uint64_t )pbField = pSelReg->u64Base;
577	}
578
579	/* Attributes. */
580	{
581	uint32_t const fValidAttrMask = X86DESCATTR_TYPE \| X86DESCATTR_DT \| X86DESCATTR_DPL \| X86DESCATTR_P
582	\| X86DESCATTR_AVL \| X86DESCATTR_L \| X86DESCATTR_D \| X86DESCATTR_G
583	\| X86DESCATTR_UNUSABLE;
584	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
585	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
586	uint8_t const uWidthType = (uWidth << 2) \| uType;
587	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
588	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
589	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
590	uint8_t pbVmcs = (uint8_t )pVmcs;
591	uint8_t *pbField = pbVmcs + offField;
592	(uint32_t )pbField = pSelReg->Attr.u & fValidAttrMask;
593	}
594	}
595
596
597	/**
598	* Gets a guest segment register from the VMCS.
599	*
600	* @returns VBox status code.
601	* @param pVmcs Pointer to the virtual VMCS.
602	* @param iSegReg The index of the segment register (X86_SREG_XXX).
603	* @param pSelReg Where to store the segment register (only updated when
604	* VINF_SUCCESS is returned).
605	*
606	* @remarks Warning! This does not validate the contents of the retrieved segment
607	* register.
608	*/
609	static int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg) RT_NOEXCEPT
610	{
611	Assert(pSelReg);
612	Assert(iSegReg < X86_SREG_COUNT);
613
614	/* Selector. */
615	uint16_t u16Sel;
616	{
617	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
618	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
619	uint8_t const uWidthType = (uWidth << 2) \| uType;
620	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
621	AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
622	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
623	uint8_t const pbVmcs = (uint8_t )pVmcs;
624	uint8_t const *pbField = pbVmcs + offField;
625	u16Sel = (uint16_t )pbField;
626	}
627
628	/* Limit. */
629	uint32_t u32Limit;
630	{
631	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
632	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
633	uint8_t const uWidthType = (uWidth << 2) \| uType;
634	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
635	AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
636	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
637	uint8_t const pbVmcs = (uint8_t )pVmcs;
638	uint8_t const *pbField = pbVmcs + offField;
639	u32Limit = (uint32_t )pbField;
640	}
641
642	/* Base. */
643	uint64_t u64Base;
644	{
645	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
646	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
647	uint8_t const uWidthType = (uWidth << 2) \| uType;
648	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
649	AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
650	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
651	uint8_t const pbVmcs = (uint8_t )pVmcs;
652	uint8_t const *pbField = pbVmcs + offField;
653	u64Base = (uint64_t )pbField;
654	/** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
655	}
656
657	/* Attributes. */
658	uint32_t u32Attr;
659	{
660	uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
661	uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
662	uint8_t const uWidthType = (uWidth << 2) \| uType;
663	uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
664	AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
665	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
666	uint8_t const pbVmcs = (uint8_t )pVmcs;
667	uint8_t const *pbField = pbVmcs + offField;
668	u32Attr = (uint32_t )pbField;
669	}
670
671	pSelReg->Sel = u16Sel;
672	pSelReg->ValidSel = u16Sel;
673	pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
674	pSelReg->u32Limit = u32Limit;
675	pSelReg->u64Base = u64Base;
676	pSelReg->Attr.u = u32Attr;
677	return VINF_SUCCESS;
678	}
679
680
681	/**
682	* Converts an IEM exception event type to a VMX event type.
683	*
684	* @returns The VMX event type.
685	* @param uVector The interrupt / exception vector.
686	* @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
687	*/
688	DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
689	{
690	/* Paranoia (callers may use these interchangeably). */
691	AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
692	AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
693	AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
694	AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
695	AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
696	AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
697	AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
698	AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
699	AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
700	AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
701	AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
702	AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
703
704	if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
705	{
706	if (uVector == X86_XCPT_NMI)
707	return VMX_EXIT_INT_INFO_TYPE_NMI;
708	return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
709	}
710
711	if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
712	{
713	if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR \| IEM_XCPT_FLAGS_OF_INSTR))
714	return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
715	if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
716	return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
717	return VMX_EXIT_INT_INFO_TYPE_SW_INT;
718	}
719
720	Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
721	return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
722	}
723
724
725	/**
726	* Determines whether the guest is using PAE paging given the VMCS.
727	*
728	* @returns @c true if PAE paging mode is used, @c false otherwise.
729	* @param pVmcs Pointer to the virtual VMCS.
730	*
731	* @warning Only use this prior to switching the guest-CPU state with the
732	* nested-guest CPU state!
733	*/
734	DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
735	{
736	return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
737	&& (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
738	&& (pVmcs->u64GuestCr0.u & X86_CR0_PG));
739	}
740
741
742	/**
743	* Sets the Exit qualification VMCS field.
744	*
745	* @param pVCpu The cross context virtual CPU structure.
746	* @param u64ExitQual The Exit qualification.
747	*/
748	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
749	{
750	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
751	}
752
753
754	/**
755	* Sets the VM-exit interruption information field.
756	*
757	* @param pVCpu The cross context virtual CPU structure.
758	* @param uExitIntInfo The VM-exit interruption information.
759	*/
760	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
761	{
762	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
763	}
764
765
766	/**
767	* Sets the VM-exit interruption error code.
768	*
769	* @param pVCpu The cross context virtual CPU structure.
770	* @param uErrCode The error code.
771	*/
772	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
773	{
774	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
775	}
776
777
778	/**
779	* Sets the IDT-vectoring information field.
780	*
781	* @param pVCpu The cross context virtual CPU structure.
782	* @param uIdtVectorInfo The IDT-vectoring information.
783	*/
784	DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
785	{
786	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
787	}
788
789
790	/**
791	* Sets the IDT-vectoring error code field.
792	*
793	* @param pVCpu The cross context virtual CPU structure.
794	* @param uErrCode The error code.
795	*/
796	DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
797	{
798	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
799	}
800
801
802	/**
803	* Sets the VM-exit guest-linear address VMCS field.
804	*
805	* @param pVCpu The cross context virtual CPU structure.
806	* @param uGuestLinearAddr The VM-exit guest-linear address.
807	*/
808	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
809	{
810	/* Bits 63:32 of guest-linear address MBZ if the guest isn't in long mode prior to the VM-exit. */
811	Assert(CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)) \|\| !(uGuestLinearAddr & UINT64_C(0xffffffff00000000)));
812	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
813	}
814
815
816	/**
817	* Sets the VM-exit guest-physical address VMCS field.
818	*
819	* @param pVCpu The cross context virtual CPU structure.
820	* @param uGuestPhysAddr The VM-exit guest-physical address.
821	*/
822	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
823	{
824	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
825	}
826
827
828	/**
829	* Sets the VM-exit instruction length VMCS field.
830	*
831	* @param pVCpu The cross context virtual CPU structure.
832	* @param cbInstr The VM-exit instruction length in bytes.
833	*
834	* @remarks Callers may clear this field to 0. Hence, this function does not check
835	* the validity of the instruction length.
836	*/
837	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
838	{
839	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
840	}
841
842
843	/**
844	* Sets the VM-exit instruction info. VMCS field.
845	*
846	* @param pVCpu The cross context virtual CPU structure.
847	* @param uExitInstrInfo The VM-exit instruction information.
848	*/
849	DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
850	{
851	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
852	}
853
854
855	/**
856	* Sets the guest pending-debug exceptions field.
857	*
858	* @param pVCpu The cross context virtual CPU structure.
859	* @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
860	*/
861	DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
862	{
863	Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
864	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
865	}
866
867
868	/**
869	* Implements VMSucceed for VMX instruction success.
870	*
871	* @param pVCpu The cross context virtual CPU structure.
872	*/
873	DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
874	{
875	return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
876	}
877
878
879	/**
880	* Implements VMFailInvalid for VMX instruction failure.
881	*
882	* @param pVCpu The cross context virtual CPU structure.
883	*/
884	DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
885	{
886	return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
887	}
888
889
890	/**
891	* Implements VMFail for VMX instruction failure.
892	*
893	* @param pVCpu The cross context virtual CPU structure.
894	* @param enmInsErr The VM instruction error.
895	*/
896	DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
897	{
898	return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
899	}
900
901
902	/**
903	* Checks if the given auto-load/store MSR area count is valid for the
904	* implementation.
905	*
906	* @returns @c true if it's within the valid limit, @c false otherwise.
907	* @param pVCpu The cross context virtual CPU structure.
908	* @param uMsrCount The MSR area count to check.
909	*/
910	DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
911	{
912	uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
913	uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
914	Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
915	if (uMsrCount <= cMaxSupportedMsrs)
916	return true;
917	return false;
918	}
919
920
921	/**
922	* Flushes the current VMCS contents back to guest memory.
923	*
924	* @returns VBox status code.
925	* @param pVCpu The cross context virtual CPU structure.
926	*/
927	DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
928	{
929	Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
930	int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
931	&pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
932	return rc;
933	}
934
935
936	/**
937	* Populates the current VMCS contents from guest memory.
938	*
939	* @returns VBox status code.
940	* @param pVCpu The cross context virtual CPU structure.
941	*/
942	DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
943	{
944	Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
945	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
946	IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
947	return rc;
948	}
949
950
951	/**
952	* Gets the instruction diagnostic for segment base checks during VM-entry of a
953	* nested-guest.
954	*
955	* @param iSegReg The segment index (X86_SREG_XXX).
956	*/
957	static VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg) RT_NOEXCEPT
958	{
959	switch (iSegReg)
960	{
961	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
962	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
963	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
964	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
965	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
966	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
967	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
968	}
969	}
970
971
972	/**
973	* Gets the instruction diagnostic for segment base checks during VM-entry of a
974	* nested-guest that is in Virtual-8086 mode.
975	*
976	* @param iSegReg The segment index (X86_SREG_XXX).
977	*/
978	static VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg) RT_NOEXCEPT
979	{
980	switch (iSegReg)
981	{
982	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
983	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
984	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
985	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
986	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
987	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
988	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
989	}
990	}
991
992
993	/**
994	* Gets the instruction diagnostic for segment limit checks during VM-entry of a
995	* nested-guest that is in Virtual-8086 mode.
996	*
997	* @param iSegReg The segment index (X86_SREG_XXX).
998	*/
999	static VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg) RT_NOEXCEPT
1000	{
1001	switch (iSegReg)
1002	{
1003	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1004	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1005	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1006	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1007	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1008	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1009	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1010	}
1011	}
1012
1013
1014	/**
1015	* Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1016	* nested-guest that is in Virtual-8086 mode.
1017	*
1018	* @param iSegReg The segment index (X86_SREG_XXX).
1019	*/
1020	static VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg) RT_NOEXCEPT
1021	{
1022	switch (iSegReg)
1023	{
1024	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1025	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1026	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1027	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1028	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1029	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1030	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1031	}
1032	}
1033
1034
1035	/**
1036	* Gets the instruction diagnostic for segment attributes reserved bits failure
1037	* during VM-entry of a nested-guest.
1038	*
1039	* @param iSegReg The segment index (X86_SREG_XXX).
1040	*/
1041	static VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg) RT_NOEXCEPT
1042	{
1043	switch (iSegReg)
1044	{
1045	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1046	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1047	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1048	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1049	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1050	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1051	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1052	}
1053	}
1054
1055
1056	/**
1057	* Gets the instruction diagnostic for segment attributes descriptor-type
1058	* (code/segment or system) failure during VM-entry of a nested-guest.
1059	*
1060	* @param iSegReg The segment index (X86_SREG_XXX).
1061	*/
1062	static VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg) RT_NOEXCEPT
1063	{
1064	switch (iSegReg)
1065	{
1066	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1067	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1068	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1069	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1070	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1071	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1072	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1073	}
1074	}
1075
1076
1077	/**
1078	* Gets the instruction diagnostic for segment attributes descriptor-type
1079	* (code/segment or system) failure during VM-entry of a nested-guest.
1080	*
1081	* @param iSegReg The segment index (X86_SREG_XXX).
1082	*/
1083	static VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg) RT_NOEXCEPT
1084	{
1085	switch (iSegReg)
1086	{
1087	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1088	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1089	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1090	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1091	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1092	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1093	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1094	}
1095	}
1096
1097
1098	/**
1099	* Gets the instruction diagnostic for segment attribute granularity failure during
1100	* VM-entry of a nested-guest.
1101	*
1102	* @param iSegReg The segment index (X86_SREG_XXX).
1103	*/
1104	static VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg) RT_NOEXCEPT
1105	{
1106	switch (iSegReg)
1107	{
1108	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1109	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1110	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1111	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1112	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1113	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1114	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1115	}
1116	}
1117
1118	/**
1119	* Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1120	* VM-entry of a nested-guest.
1121	*
1122	* @param iSegReg The segment index (X86_SREG_XXX).
1123	*/
1124	static VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg) RT_NOEXCEPT
1125	{
1126	switch (iSegReg)
1127	{
1128	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1129	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1130	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1131	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1132	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1133	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1134	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1135	}
1136	}
1137
1138
1139	/**
1140	* Gets the instruction diagnostic for segment attribute type accessed failure
1141	* during VM-entry of a nested-guest.
1142	*
1143	* @param iSegReg The segment index (X86_SREG_XXX).
1144	*/
1145	static VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg) RT_NOEXCEPT
1146	{
1147	switch (iSegReg)
1148	{
1149	case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1150	case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1151	case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1152	case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1153	case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1154	case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1155	IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1156	}
1157	}
1158
1159
1160	/**
1161	* Saves the guest control registers, debug registers and some MSRs are part of
1162	* VM-exit.
1163	*
1164	* @param pVCpu The cross context virtual CPU structure.
1165	*/
1166	static void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1167	{
1168	/*
1169	* Saves the guest control registers, debug registers and some MSRs.
1170	* See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1171	*/
1172	PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1173
1174	/* Save control registers. */
1175	pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1176	pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1177	pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1178
1179	/* Save SYSENTER CS, ESP, EIP. */
1180	pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1181	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1182	{
1183	pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1184	pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1185	}
1186	else
1187	{
1188	pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1189	pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1190	}
1191
1192	/* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1193	if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1194	{
1195	pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1196	/** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1197	}
1198
1199	/* Save PAT MSR. */
1200	if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1201	pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1202
1203	/* Save EFER MSR. */
1204	if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1205	pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1206
1207	/* We don't support clearing IA32_BNDCFGS MSR yet. */
1208	Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1209
1210	/* Nothing to do for SMBASE register - We don't support SMM yet. */
1211	}
1212
1213
1214	/**
1215	* Saves the guest force-flags in preparation of entering the nested-guest.
1216	*
1217	* @param pVCpu The cross context virtual CPU structure.
1218	*/
1219	static void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1220	{
1221	/* We shouldn't be called multiple times during VM-entry. */
1222	Assert(pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit == 0);
1223
1224	/* MTF should not be set outside VMX non-root mode. */
1225	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1226
1227	/*
1228	* Preserve the required force-flags.
1229	*
1230	* We cache and clear force-flags that would affect the execution of the
1231	* nested-guest. Cached flags are then restored while returning to the guest
1232	* if necessary.
1233	*
1234	* - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1235	* interrupts until the completion of the current VMLAUNCH/VMRESUME
1236	* instruction. Interrupt inhibition for any nested-guest instruction
1237	* is supplied by the guest-interruptibility state VMCS field and will
1238	* be set up as part of loading the guest state. Technically
1239	* blocking-by-STI is possible with VMLAUNCH/VMRESUME but we currently
1240	* disallow it since we can't distinguish it from blocking-by-MovSS
1241	* and no nested-hypervisor we care about uses STI immediately
1242	* followed by VMLAUNCH/VMRESUME.
1243	*
1244	* - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1245	* successful VM-entry (due to invalid guest-state) need to continue
1246	* blocking NMIs if it was in effect before VM-entry.
1247	*
1248	* - MTF need not be preserved as it's used only in VMX non-root mode and
1249	* is supplied through the VM-execution controls.
1250	*
1251	* The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1252	* we will be able to generate interrupts that may cause VM-exits for
1253	* the nested-guest.
1254	*/
1255	pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_INHIBIT_NMI;
1256	}
1257
1258
1259	/**
1260	* Restores the guest force-flags in preparation of exiting the nested-guest.
1261	*
1262	* @param pVCpu The cross context virtual CPU structure.
1263	*/
1264	static void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1265	{
1266	/** @todo r=bird: why aren't we clearing the nested guest flags first here?
1267	* If there is some other code doing that already, it would be great
1268	* to point to it here... */
1269	pVCpu->cpum.GstCtx.eflags.uBoth \|= pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit;
1270	pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = 0;
1271	}
1272
1273
1274	/**
1275	* Performs the VMX transition to/from VMX non-root mode.
1276	*
1277	* @param pVCpu The cross context virtual CPU structure.
1278	* @param cbInstr The length of the current instruction.
1279	*/
1280	static int iemVmxTransition(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
1281	{
1282	/*
1283	* Inform PGM about paging mode changes.
1284	* We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1285	* see comment in iemMemPageTranslateAndCheckAccess().
1286	*/
1287	int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 \| X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1288	true /* fForce */);
1289	if (RT_SUCCESS(rc))
1290	{ /* likely */ }
1291	else
1292	return rc;
1293
1294	/* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1295	IEMTlbInvalidateAll(pVCpu);
1296
1297	/* Inform CPUM (recompiler), can later be removed. */
1298	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1299
1300	/* Re-initialize IEM cache/state after the drastic mode switch. */
1301	iemReInitExec(pVCpu, cbInstr);
1302	return rc;
1303	}
1304
1305
1306	/**
1307	* Calculates the current VMX-preemption timer value.
1308	*
1309	* @returns The current VMX-preemption timer value.
1310	* @param pVCpu The cross context virtual CPU structure.
1311	*/
1312	static uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
1313	{
1314	/*
1315	* Assume the following:
1316	* PreemptTimerShift = 5
1317	* VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1318	* EntryTick = 50000 (TSC at time of VM-entry)
1319	*
1320	* CurTick Delta PreemptTimerVal
1321	* ----------------------------------
1322	* 60000 10000 2
1323	* 80000 30000 1
1324	* 90000 40000 0 -> VM-exit.
1325	*
1326	* If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1327	* The saved VMX-preemption timer value is calculated as follows:
1328	* PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1329	* E.g.:
1330	* Delta = 10000
1331	* Tmp = 10000 / (2 * 10000) = 0.5
1332	* NewPt = 2 - 0.5 = 2
1333	* Delta = 30000
1334	* Tmp = 30000 / (2 * 10000) = 1.5
1335	* NewPt = 2 - 1.5 = 1
1336	* Delta = 40000
1337	* Tmp = 40000 / 20000 = 2
1338	* NewPt = 2 - 2 = 0
1339	*/
1340	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1341	uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1342	if (uVmcsPreemptVal > 0)
1343	{
1344	uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1345	uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1346	uint64_t const uDelta = uCurTick - uEntryTick;
1347	uint32_t const uPreemptTimer = uVmcsPreemptVal
1348	- ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1349	return uPreemptTimer;
1350	}
1351	return 0;
1352	}
1353
1354
1355	/**
1356	* Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1357	*
1358	* @param pVCpu The cross context virtual CPU structure.
1359	*/
1360	static void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1361	{
1362	/*
1363	* Save guest segment registers, GDTR, IDTR, LDTR, TR.
1364	* See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1365	*/
1366	/* CS, SS, ES, DS, FS, GS. */
1367	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1368	for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1369	{
1370	PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1371	if (!pSelReg->Attr.n.u1Unusable)
1372	iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1373	else
1374	{
1375	/*
1376	* For unusable segments the attributes are undefined except for CS and SS.
1377	* For the rest we don't bother preserving anything but the unusable bit.
1378	*/
1379	switch (iSegReg)
1380	{
1381	case X86_SREG_CS:
1382	pVmcs->GuestCs = pSelReg->Sel;
1383	pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1384	pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1385	pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L \| X86DESCATTR_D \| X86DESCATTR_G
1386	\| X86DESCATTR_UNUSABLE);
1387	break;
1388
1389	case X86_SREG_SS:
1390	pVmcs->GuestSs = pSelReg->Sel;
1391	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1392	pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1393	pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL \| X86DESCATTR_UNUSABLE);
1394	break;
1395
1396	case X86_SREG_DS:
1397	pVmcs->GuestDs = pSelReg->Sel;
1398	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1399	pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1400	pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1401	break;
1402
1403	case X86_SREG_ES:
1404	pVmcs->GuestEs = pSelReg->Sel;
1405	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1406	pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1407	pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1408	break;
1409
1410	case X86_SREG_FS:
1411	pVmcs->GuestFs = pSelReg->Sel;
1412	pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1413	pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1414	break;
1415
1416	case X86_SREG_GS:
1417	pVmcs->GuestGs = pSelReg->Sel;
1418	pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1419	pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1420	break;
1421	}
1422	}
1423	}
1424
1425	/* Segment attribute bits 31:17 and 11:8 MBZ. */
1426	uint32_t const fValidAttrMask = X86DESCATTR_TYPE \| X86DESCATTR_DT \| X86DESCATTR_DPL \| X86DESCATTR_P
1427	\| X86DESCATTR_AVL \| X86DESCATTR_L \| X86DESCATTR_D \| X86DESCATTR_G
1428	\| X86DESCATTR_UNUSABLE;
1429	/* LDTR. */
1430	{
1431	PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1432	pVmcs->GuestLdtr = pSelReg->Sel;
1433	pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1434	Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1435	pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1436	pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1437	}
1438
1439	/* TR. */
1440	{
1441	PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1442	pVmcs->GuestTr = pSelReg->Sel;
1443	pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1444	pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1445	pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1446	}
1447
1448	/* GDTR. */
1449	pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1450	pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1451
1452	/* IDTR. */
1453	pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1454	pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1455	}
1456
1457
1458	/**
1459	* Saves guest non-register state as part of VM-exit.
1460	*
1461	* @param pVCpu The cross context virtual CPU structure.
1462	* @param uExitReason The VM-exit reason.
1463	*/
1464	static void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1465	{
1466	/*
1467	* Save guest non-register state.
1468	* See Intel spec. 27.3.4 "Saving Non-Register State".
1469	*/
1470	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1471
1472	/*
1473	* Activity state.
1474	* Most VM-exits will occur in the active state. However, if the first instruction
1475	* following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1476	* the VM-exit will be from the HLT activity state.
1477	*
1478	* See Intel spec. 25.5.2 "Monitor Trap Flag".
1479	*/
1480	/** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1481	* not? */
1482	EMSTATE const enmActivityState = EMGetState(pVCpu);
1483	switch (enmActivityState)
1484	{
1485	case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1486	default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1487	}
1488
1489	/*
1490	* Interruptibility-state.
1491	*/
1492	/* NMI. */
1493	pVmcs->u32GuestIntrState = 0;
1494	if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1495	{
1496	if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1497	pVmcs->u32GuestIntrState \|= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1498	}
1499	else
1500	{
1501	if (CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx))
1502	pVmcs->u32GuestIntrState \|= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1503	}
1504
1505	/* Blocking-by-STI or blocking-by-MovSS. */
1506	uint32_t fInhibitShw;
1507	if (!CPUMIsInInterruptShadowWithUpdateEx(&pVCpu->cpum.GstCtx, &fInhibitShw))
1508	{ /* probable */}
1509	else
1510	{
1511	if (pVCpu->cpum.GstCtx.rip == pVCpu->cpum.GstCtx.uRipInhibitInt)
1512	{
1513	/*
1514	* We must ensure only one of these bits is set.
1515	* Our emulation can have both set (perhaps because AMD doesn't distinguish
1516	* between the two?). Hence, the 'else' with blocking-by-MovSS taking priority
1517	* since it blocks more. Nested Ubuntu 22.04.2 running inside a Hyper-V enabled
1518	* Windows Server 2008 R2 guest runs into this issue.
1519	*
1520	* See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
1521	*/
1522	if (fInhibitShw & CPUMCTX_INHIBIT_SHADOW_SS)
1523	pVmcs->u32GuestIntrState \|= VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS;
1524	else
1525	{
1526	Assert(fInhibitShw & CPUMCTX_INHIBIT_SHADOW_STI);
1527	pVmcs->u32GuestIntrState \|= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1528	}
1529	}
1530	}
1531	/* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1532
1533	/*
1534	* Pending debug exceptions.
1535	*
1536	* For VM-exits where it is not applicable, we can safely zero out the field.
1537	* For VM-exits where it is applicable, it's expected to be updated by the caller already.
1538	*/
1539	if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1540	&& uExitReason != VMX_EXIT_SMI
1541	&& uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1542	&& !VMXIsVmexitTrapLike(uExitReason))
1543	{
1544	/** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1545	* block-by-MovSS is in effect. */
1546	pVmcs->u64GuestPendingDbgXcpts.u = 0;
1547	}
1548
1549	/*
1550	* Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1551	*
1552	* For VMX-preemption timer VM-exits, we should have already written back 0 if the
1553	* feature is supported back into the VMCS, and thus there is nothing further to do here.
1554	*/
1555	if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1556	&& (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1557	pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1558
1559	/*
1560	* Save the guest PAE PDPTEs.
1561	*/
1562	if ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
1563	\|\| !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
1564	{
1565	/*
1566	* Without EPT or when the nested-guest is not using PAE paging, the values saved
1567	* in the VMCS during VM-exit are undefined. We zero them here for consistency.
1568	*/
1569	pVmcs->u64GuestPdpte0.u = 0;
1570	pVmcs->u64GuestPdpte1.u = 0;
1571	pVmcs->u64GuestPdpte2.u = 0;
1572	pVmcs->u64GuestPdpte3.u = 0;
1573	}
1574	else
1575	{
1576	/*
1577	* With EPT and when the nested-guest is using PAE paging, we update the PDPTEs from
1578	* the nested-guest CPU context. Both IEM (Mov CRx) and hardware-assisted execution
1579	* of the nested-guest is expected to have updated them.
1580	*/
1581	pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1582	pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1583	pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1584	pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1585	}
1586
1587	/* Clear PGM's copy of the EPT pointer for added safety. */
1588	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1589	PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1590	}
1591
1592
1593	/**
1594	* Saves the guest-state as part of VM-exit.
1595	*
1596	* @returns VBox status code.
1597	* @param pVCpu The cross context virtual CPU structure.
1598	* @param uExitReason The VM-exit reason.
1599	*/
1600	static void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1601	{
1602	iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1603	iemVmxVmexitSaveGuestSegRegs(pVCpu);
1604
1605	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1606	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1607	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1608
1609	iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1610	}
1611
1612
1613	/**
1614	* Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1615	*
1616	* @returns VBox status code.
1617	* @param pVCpu The cross context virtual CPU structure.
1618	* @param uExitReason The VM-exit reason (for diagnostic purposes).
1619	*/
1620	static int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1621	{
1622	/*
1623	* Save guest MSRs.
1624	* See Intel spec. 27.4 "Saving MSRs".
1625	*/
1626	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1627	const char * const pszFailure = "VMX-abort";
1628
1629	/*
1630	* The VM-exit MSR-store area address need not be a valid guest-physical address if the
1631	* VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1632	* See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1633	*/
1634	uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1635	if (!cMsrs)
1636	return VINF_SUCCESS;
1637
1638	/*
1639	* Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1640	* is exceeded including possibly raising #MC exceptions during VMX transition. Our
1641	* implementation causes a VMX-abort followed by a triple-fault.
1642	*/
1643	bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1644	if (fIsMsrCountValid)
1645	{ /* likely */ }
1646	else
1647	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1648
1649	/*
1650	* Optimization if the nested hypervisor is using the same guest-physical page for both
1651	* the VM-entry MSR-load area as well as the VM-exit MSR store area.
1652	*/
1653	PVMXAUTOMSR pMsrArea;
1654	RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1655	RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1656	if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1657	pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1658	else
1659	{
1660	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1661	GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1662	if (RT_SUCCESS(rc))
1663	pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1664	else
1665	{
1666	AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1667	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1668	}
1669	}
1670
1671	/*
1672	* Update VM-exit MSR store area.
1673	*/
1674	PVMXAUTOMSR pMsr = pMsrArea;
1675	for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1676	{
1677	if ( !pMsr->u32Reserved
1678	&& pMsr->u32Msr != MSR_IA32_SMBASE
1679	&& pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1680	{
1681	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1682	if (rcStrict == VINF_SUCCESS)
1683	continue;
1684
1685	/*
1686	* If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1687	* If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1688	* recording the MSR index in the auxiliary info. field and indicated further by our
1689	* own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1690	* if possible, or come up with a better, generic solution.
1691	*/
1692	pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1693	VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1694	? kVmxVDiag_Vmexit_MsrStoreRing3
1695	: kVmxVDiag_Vmexit_MsrStore;
1696	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1697	}
1698	else
1699	{
1700	pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1701	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1702	}
1703	}
1704
1705	/*
1706	* Commit the VM-exit MSR store are to guest memory.
1707	*/
1708	int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1709	if (RT_SUCCESS(rc))
1710	return VINF_SUCCESS;
1711
1712	NOREF(uExitReason);
1713	NOREF(pszFailure);
1714
1715	AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1716	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1717	}
1718
1719
1720	/**
1721	* Performs a VMX abort (due to an fatal error during VM-exit).
1722	*
1723	* @returns Strict VBox status code.
1724	* @param pVCpu The cross context virtual CPU structure.
1725	* @param enmAbort The VMX abort reason.
1726	*/
1727	static VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort) RT_NOEXCEPT
1728	{
1729	/*
1730	* Perform the VMX abort.
1731	* See Intel spec. 27.7 "VMX Aborts".
1732	*/
1733	LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1734
1735	/* We don't support SMX yet. */
1736	pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1737	if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1738	{
1739	RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1740	uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1741	PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1742	}
1743
1744	return VINF_EM_TRIPLE_FAULT;
1745	}
1746
1747
1748	/**
1749	* Loads host control registers, debug registers and MSRs as part of VM-exit.
1750	*
1751	* @param pVCpu The cross context virtual CPU structure.
1752	*/
1753	static void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1754	{
1755	/*
1756	* Load host control registers, debug registers and MSRs.
1757	* See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1758	*/
1759	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1760	bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1761
1762	/* CR0. */
1763	{
1764	/* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1765	uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK;
1766	uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1767	uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1768	uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) \| (uGuestCr0 & fCr0IgnMask);
1769
1770	/* Verify we have not modified CR0 fixed bits in VMX operation. */
1771	#ifdef VBOX_STRICT
1772	uint64_t const uCr0Mb1 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
1773	bool const fUx = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1774	AssertMsg( (uValidHostCr0 & uCr0Mb1) == uCr0Mb1
1775	&& (uValidHostCr0 & ~VMX_V_CR0_FIXED1) == 0,
1776	("host=%#RX64 guest=%#RX64 mb1=%#RX64 valid_host_cr0=%#RX64 fUx=%RTbool\n",
1777	uHostCr0, uGuestCr0, uCr0Mb1, uValidHostCr0, fUx));
1778	#endif
1779	Assert(!(uValidHostCr0 >> 32));
1780	CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1781	}
1782
1783	/* CR4. */
1784	{
1785	/* CR4 fixed bits are not modified. */
1786	uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1787	uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1788	uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1789	uint64_t uValidHostCr4 = (uHostCr4 & uCr4Mb0) \| uCr4Mb1;
1790	if (fHostInLongMode)
1791	uValidHostCr4 \|= X86_CR4_PAE;
1792	else
1793	uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1794
1795	/* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1796	AssertMsg( (uValidHostCr4 & uCr4Mb1) == uCr4Mb1
1797	&& (uValidHostCr4 & ~uCr4Mb0) == 0,
1798	("host=%#RX64 guest=%#RX64, uCr4Mb1=%#RX64 uCr4Mb0=%#RX64 valid_host_cr4=%#RX64\n",
1799	uHostCr4, pVCpu->cpum.GstCtx.cr4, uCr4Mb1, uCr4Mb0, uValidHostCr4));
1800	CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1801	}
1802
1803	/* CR3 (host value validated while checking host-state during VM-entry). */
1804	pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1805
1806	/* DR7. */
1807	pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1808
1809	/** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1810
1811	/* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1812	pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1813	pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1814	pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1815
1816	/* FS, GS bases are loaded later while we load host segment registers. */
1817
1818	/* EFER MSR (host value validated while checking host-state during VM-entry). */
1819	if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1820	pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1821	else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1822	{
1823	if (fHostInLongMode)
1824	pVCpu->cpum.GstCtx.msrEFER \|= (MSR_K6_EFER_LMA \| MSR_K6_EFER_LME);
1825	else
1826	pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA \| MSR_K6_EFER_LME);
1827	}
1828
1829	/* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1830
1831	/* PAT MSR (host value is validated while checking host-state during VM-entry). */
1832	if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1833	pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1834
1835	/* We don't support IA32_BNDCFGS MSR yet. */
1836	}
1837
1838
1839	/**
1840	* Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1841	*
1842	* @param pVCpu The cross context virtual CPU structure.
1843	*/
1844	static void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1845	{
1846	/*
1847	* Load host segment registers, GDTR, IDTR, LDTR and TR.
1848	* See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1849	*
1850	* Warning! Be careful to not touch fields that are reserved by VT-x,
1851	* e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1852	*/
1853	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1854	bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1855
1856	/* CS, SS, ES, DS, FS, GS. */
1857	for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1858	{
1859	RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1860	bool const fUnusable = RT_BOOL(HostSel == 0);
1861	PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1862
1863	/* Selector. */
1864	pSelReg->Sel = HostSel;
1865	pSelReg->ValidSel = HostSel;
1866	pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1867
1868	/* Limit. */
1869	pSelReg->u32Limit = 0xffffffff;
1870
1871	/* Base. */
1872	pSelReg->u64Base = 0;
1873
1874	/* Attributes. */
1875	if (iSegReg == X86_SREG_CS)
1876	{
1877	pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE \| X86_SEL_TYPE_READ \| X86_SEL_TYPE_ACCESSED;
1878	pSelReg->Attr.n.u1DescType = 1;
1879	pSelReg->Attr.n.u2Dpl = 0;
1880	pSelReg->Attr.n.u1Present = 1;
1881	pSelReg->Attr.n.u1Long = fHostInLongMode;
1882	pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1883	pSelReg->Attr.n.u1Granularity = 1;
1884	Assert(!pSelReg->Attr.n.u1Unusable);
1885	Assert(!fUnusable);
1886	}
1887	else
1888	{
1889	pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW \| X86_SEL_TYPE_ACCESSED;
1890	pSelReg->Attr.n.u1DescType = 1;
1891	pSelReg->Attr.n.u2Dpl = 0;
1892	pSelReg->Attr.n.u1Present = 1;
1893	pSelReg->Attr.n.u1DefBig = 1;
1894	pSelReg->Attr.n.u1Granularity = 1;
1895	pSelReg->Attr.n.u1Unusable = fUnusable;
1896	}
1897	}
1898
1899	/* FS base. */
1900	if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1901	\|\| fHostInLongMode)
1902	{
1903	Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1904	pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1905	}
1906
1907	/* GS base. */
1908	if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1909	\|\| fHostInLongMode)
1910	{
1911	Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1912	pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1913	}
1914
1915	/* TR. */
1916	Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1917	Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1918	pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1919	pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1920	pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1921	pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1922	pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1923	pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1924	pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1925	pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1926	pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1927	pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1928	pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1929
1930	/* LDTR (Warning! do not touch the base and limits here). */
1931	pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1932	pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1933	pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1934	pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1935
1936	/* GDTR. */
1937	Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1938	pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1939	pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1940
1941	/* IDTR.*/
1942	Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1943	pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1944	pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1945	}
1946
1947
1948	/**
1949	* Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1950	*
1951	* @returns VBox status code.
1952	* @param pVCpu The cross context virtual CPU structure.
1953	* @param uExitReason The VMX instruction name (for logging purposes).
1954	*/
1955	static int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1956	{
1957	/*
1958	* Load host MSRs.
1959	* See Intel spec. 27.6 "Loading MSRs".
1960	*/
1961	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1962	const char * const pszFailure = "VMX-abort";
1963
1964	/*
1965	* The VM-exit MSR-load area address need not be a valid guest-physical address if the
1966	* VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1967	* See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1968	*/
1969	uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1970	if (!cMsrs)
1971	return VINF_SUCCESS;
1972
1973	/*
1974	* Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1975	* is exceeded including possibly raising #MC exceptions during VMX transition. Our
1976	* implementation causes a VMX-abort followed by a triple-fault.
1977	*/
1978	bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1979	if (fIsMsrCountValid)
1980	{ /* likely */ }
1981	else
1982	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1983
1984	RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1985	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1986	GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1987	if (RT_SUCCESS(rc))
1988	{
1989	PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1990	for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1991	{
1992	if ( !pMsr->u32Reserved
1993	&& pMsr->u32Msr != MSR_K8_FS_BASE
1994	&& pMsr->u32Msr != MSR_K8_GS_BASE
1995	&& pMsr->u32Msr != MSR_K6_EFER
1996	&& pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1997	&& pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1998	{
1999	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2000	if (rcStrict == VINF_SUCCESS)
2001	continue;
2002
2003	/*
2004	* If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2005	* If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2006	* recording the MSR index in the auxiliary info. field and indicated further by our
2007	* own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2008	* if possible, or come up with a better, generic solution.
2009	*/
2010	pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2011	VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2012	? kVmxVDiag_Vmexit_MsrLoadRing3
2013	: kVmxVDiag_Vmexit_MsrLoad;
2014	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2015	}
2016	else
2017	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2018	}
2019	}
2020	else
2021	{
2022	AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2023	IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2024	}
2025
2026	NOREF(uExitReason);
2027	NOREF(pszFailure);
2028	return VINF_SUCCESS;
2029	}
2030
2031
2032	/**
2033	* Loads the host state as part of VM-exit.
2034	*
2035	* @returns Strict VBox status code.
2036	* @param pVCpu The cross context virtual CPU structure.
2037	* @param uExitReason The VM-exit reason (for logging purposes).
2038	*/
2039	static VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
2040	{
2041	/*
2042	* Load host state.
2043	* See Intel spec. 27.5 "Loading Host State".
2044	*/
2045	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2046	bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2047
2048	/* We cannot return from a long-mode guest to a host that is not in long mode. */
2049	if ( CPUMIsGuestInLongMode(pVCpu)
2050	&& !fHostInLongMode)
2051	{
2052	Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2053	return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2054	}
2055
2056	/*
2057	* Check host PAE PDPTEs prior to loading the host state.
2058	* See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2059	*/
2060	if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2061	&& !fHostInLongMode
2062	&& ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2063	\|\| pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2064	{
2065	int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2066	if (RT_SUCCESS(rc))
2067	{ /* likely*/ }
2068	else
2069	{
2070	IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2071	return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2072	}
2073	}
2074
2075	iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2076	iemVmxVmexitLoadHostSegRegs(pVCpu);
2077
2078	/*
2079	* Load host RIP, RSP and RFLAGS.
2080	* See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2081	*/
2082	pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2083	pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2084	pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2085
2086	/* Clear address range monitoring. */
2087	EMMonitorWaitClear(pVCpu);
2088
2089	/* Perform the VMX transition (PGM updates). */
2090	VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu, 0 /cbInstr - whatever/);
2091	if (rcStrict == VINF_SUCCESS)
2092	{ /* likely */ }
2093	else if (RT_SUCCESS(rcStrict))
2094	{
2095	Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2096	uExitReason));
2097	rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2098	}
2099	else
2100	{
2101	Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2102	return VBOXSTRICTRC_VAL(rcStrict);
2103	}
2104
2105	Assert(rcStrict == VINF_SUCCESS);
2106
2107	/* Load MSRs from the VM-exit auto-load MSR area. */
2108	int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2109	if (RT_FAILURE(rc))
2110	{
2111	Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2112	return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2113	}
2114	return VINF_SUCCESS;
2115	}
2116
2117
2118	/**
2119	* Gets VM-exit instruction information along with any displacement for an
2120	* instruction VM-exit.
2121	*
2122	* @returns The VM-exit instruction information.
2123	* @param pVCpu The cross context virtual CPU structure.
2124	* @param uExitReason The VM-exit reason.
2125	* @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2126	* @param pGCPtrDisp Where to store the displacement field. Optional, can be
2127	* NULL.
2128	*/
2129	static uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp) RT_NOEXCEPT
2130	{
2131	RTGCPTR GCPtrDisp;
2132	VMXEXITINSTRINFO ExitInstrInfo;
2133	ExitInstrInfo.u = 0;
2134
2135	/*
2136	* Get and parse the ModR/M byte from our decoded opcodes.
2137	*/
2138	uint8_t bRm;
2139	uint8_t const offModRm = pVCpu->iem.s.offModRm;
2140	IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2141	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2142	{
2143	/*
2144	* ModR/M indicates register addressing.
2145	*
2146	* The primary/secondary register operands are reported in the iReg1 or iReg2
2147	* fields depending on whether it is a read/write form.
2148	*/
2149	uint8_t idxReg1;
2150	uint8_t idxReg2;
2151	if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2152	{
2153	idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg;
2154	idxReg2 = (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB;
2155	}
2156	else
2157	{
2158	idxReg1 = (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB;
2159	idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg;
2160	}
2161	ExitInstrInfo.All.u2Scaling = 0;
2162	ExitInstrInfo.All.iReg1 = idxReg1;
2163	ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2164	ExitInstrInfo.All.fIsRegOperand = 1;
2165	ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2166	ExitInstrInfo.All.iSegReg = 0;
2167	ExitInstrInfo.All.iIdxReg = 0;
2168	ExitInstrInfo.All.fIdxRegInvalid = 1;
2169	ExitInstrInfo.All.iBaseReg = 0;
2170	ExitInstrInfo.All.fBaseRegInvalid = 1;
2171	ExitInstrInfo.All.iReg2 = idxReg2;
2172
2173	/* Displacement not applicable for register addressing. */
2174	GCPtrDisp = 0;
2175	}
2176	else
2177	{
2178	/*
2179	* ModR/M indicates memory addressing.
2180	*/
2181	uint8_t uScale = 0;
2182	bool fBaseRegValid = false;
2183	bool fIdxRegValid = false;
2184	uint8_t iBaseReg = 0;
2185	uint8_t iIdxReg = 0;
2186	if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2187	{
2188	/*
2189	* Parse the ModR/M, displacement for 16-bit addressing mode.
2190	* See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2191	*/
2192	uint16_t u16Disp = 0;
2193	uint8_t const offDisp = offModRm + sizeof(bRm);
2194	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 6)
2195	{
2196	/* Displacement without any registers. */
2197	IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2198	}
2199	else
2200	{
2201	/* Register (index and base). */
2202	switch (bRm & X86_MODRM_RM_MASK)
2203	{
2204	case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2205	case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2206	case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2207	case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2208	case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2209	case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2210	case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2211	case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2212	}
2213
2214	/* Register + displacement. */
2215	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2216	{
2217	case 0: break;
2218	case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2219	case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2220	default:
2221	{
2222	/* Register addressing, handled at the beginning. */
2223	AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2224	break;
2225	}
2226	}
2227	}
2228
2229	Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2230	GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2231	}
2232	else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2233	{
2234	/*
2235	* Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2236	* See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2237	*/
2238	uint32_t u32Disp = 0;
2239	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
2240	{
2241	/* Displacement without any registers. */
2242	uint8_t const offDisp = offModRm + sizeof(bRm);
2243	IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2244	}
2245	else
2246	{
2247	/* Register (and perhaps scale, index and base). */
2248	uint8_t offDisp = offModRm + sizeof(bRm);
2249	iBaseReg = (bRm & X86_MODRM_RM_MASK);
2250	if (iBaseReg == 4)
2251	{
2252	/* An SIB byte follows the ModR/M byte, parse it. */
2253	uint8_t bSib;
2254	uint8_t const offSib = offModRm + sizeof(bRm);
2255	IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2256
2257	/* A displacement may follow SIB, update its offset. */
2258	offDisp += sizeof(bSib);
2259
2260	/* Get the scale. */
2261	uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2262
2263	/* Get the index register. */
2264	iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2265	fIdxRegValid = RT_BOOL(iIdxReg != 4);
2266
2267	/* Get the base register. */
2268	iBaseReg = bSib & X86_SIB_BASE_MASK;
2269	fBaseRegValid = true;
2270	if (iBaseReg == 5)
2271	{
2272	if ((bRm & X86_MODRM_MOD_MASK) == 0)
2273	{
2274	/* Mod is 0 implies a 32-bit displacement with no base. */
2275	fBaseRegValid = false;
2276	IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2277	}
2278	else
2279	{
2280	/* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2281	iBaseReg = X86_GREG_xBP;
2282	}
2283	}
2284	}
2285
2286	/* Register + displacement. */
2287	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2288	{
2289	case 0: /* Handled above */ break;
2290	case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2291	case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2292	default:
2293	{
2294	/* Register addressing, handled at the beginning. */
2295	AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2296	break;
2297	}
2298	}
2299	}
2300
2301	GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2302	}
2303	else
2304	{
2305	Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2306
2307	/*
2308	* Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2309	* See Intel instruction spec. 2.2 "IA-32e Mode".
2310	*/
2311	uint64_t u64Disp = 0;
2312	bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5);
2313	if (fRipRelativeAddr)
2314	{
2315	/*
2316	* RIP-relative addressing mode.
2317	*
2318	* The displacement is 32-bit signed implying an offset range of +/-2G.
2319	* See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2320	*/
2321	uint8_t const offDisp = offModRm + sizeof(bRm);
2322	IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2323	}
2324	else
2325	{
2326	uint8_t offDisp = offModRm + sizeof(bRm);
2327
2328	/*
2329	* Register (and perhaps scale, index and base).
2330	*
2331	* REX.B extends the most-significant bit of the base register. However, REX.B
2332	* is ignored while determining whether an SIB follows the opcode. Hence, we
2333	* shall OR any REX.B bit -after- inspecting for an SIB byte below.
2334	*
2335	* See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2336	*/
2337	iBaseReg = (bRm & X86_MODRM_RM_MASK);
2338	if (iBaseReg == 4)
2339	{
2340	/* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2341	uint8_t bSib;
2342	uint8_t const offSib = offModRm + sizeof(bRm);
2343	IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2344
2345	/* Displacement may follow SIB, update its offset. */
2346	offDisp += sizeof(bSib);
2347
2348	/* Get the scale. */
2349	uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2350
2351	/* Get the index. */
2352	iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) \| pVCpu->iem.s.uRexIndex;
2353	fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2354
2355	/* Get the base. */
2356	iBaseReg = (bSib & X86_SIB_BASE_MASK);
2357	fBaseRegValid = true;
2358	if (iBaseReg == 5)
2359	{
2360	if ((bRm & X86_MODRM_MOD_MASK) == 0)
2361	{
2362	/* Mod is 0 implies a signed 32-bit displacement with no base. */
2363	IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2364	}
2365	else
2366	{
2367	/* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2368	iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2369	}
2370	}
2371	}
2372	iBaseReg \|= pVCpu->iem.s.uRexB;
2373
2374	/* Register + displacement. */
2375	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2376	{
2377	case 0: /* Handled above */ break;
2378	case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2379	case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2380	default:
2381	{
2382	/* Register addressing, handled at the beginning. */
2383	AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2384	break;
2385	}
2386	}
2387	}
2388
2389	GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2390	}
2391
2392	/*
2393	* The primary or secondary register operand is reported in iReg2 depending
2394	* on whether the primary operand is in read/write form.
2395	*/
2396	uint8_t idxReg2;
2397	if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2398	{
2399	idxReg2 = bRm & X86_MODRM_RM_MASK;
2400	if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2401	idxReg2 \|= pVCpu->iem.s.uRexB;
2402	}
2403	else
2404	{
2405	idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2406	if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2407	idxReg2 \|= pVCpu->iem.s.uRexReg;
2408	}
2409	ExitInstrInfo.All.u2Scaling = uScale;
2410	ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2411	ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2412	ExitInstrInfo.All.fIsRegOperand = 0;
2413	ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2414	ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2415	ExitInstrInfo.All.iIdxReg = iIdxReg;
2416	ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2417	ExitInstrInfo.All.iBaseReg = iBaseReg;
2418	ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2419	ExitInstrInfo.All.iReg2 = idxReg2;
2420	}
2421
2422	/*
2423	* Handle exceptions to the norm for certain instructions.
2424	* (e.g. some instructions convey an instruction identity in place of iReg2).
2425	*/
2426	switch (uExitReason)
2427	{
2428	case VMX_EXIT_GDTR_IDTR_ACCESS:
2429	{
2430	Assert(VMXINSTRID_IS_VALID(uInstrId));
2431	Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2432	ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2433	ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2434	break;
2435	}
2436
2437	case VMX_EXIT_LDTR_TR_ACCESS:
2438	{
2439	Assert(VMXINSTRID_IS_VALID(uInstrId));
2440	Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2441	ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2442	ExitInstrInfo.LdtTr.u2Undef0 = 0;
2443	break;
2444	}
2445
2446	case VMX_EXIT_RDRAND:
2447	case VMX_EXIT_RDSEED:
2448	{
2449	Assert(VMXINSTRID_IS_VALID(uInstrId));
2450	Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2451	Assert(GCPtrDisp == 0);
2452	Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2453	ExitInstrInfo.RdrandRdseed.u3Undef0 = 0;
2454	ExitInstrInfo.RdrandRdseed.u4Undef0 = 0;
2455	ExitInstrInfo.RdrandRdseed.u19Undef0 = 0;
2456	break;
2457	}
2458	}
2459
2460	/* Update displacement and return the constructed VM-exit instruction information field. */
2461	if (pGCPtrDisp)
2462	*pGCPtrDisp = GCPtrDisp;
2463
2464	return ExitInstrInfo.u;
2465	}
2466
2467
2468	/**
2469	* VMX VM-exit handler.
2470	*
2471	* @returns Strict VBox status code.
2472	* @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2473	* @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2474	* triple-fault.
2475	*
2476	* @param pVCpu The cross context virtual CPU structure.
2477	* @param uExitReason The VM-exit reason.
2478	* @param u64ExitQual The Exit qualification.
2479	*
2480	* @remarks We need not necessarily have completed VM-entry before a VM-exit is
2481	* called. Failures during VM-entry can cause VM-exits as well, so we
2482	* -cannot- assert we're in VMX non-root mode here.
2483	*/
2484	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT
2485	{
2486	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2487	RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2488	AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2489	return VERR_IEM_IPE_7;
2490	# else
2491	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2492
2493	/* Just count this as an exit and be done with that. */
2494	pVCpu->iem.s.cPotentialExits++;
2495
2496	/*
2497	* Import all the guest-CPU state.
2498	*
2499	* HM on returning to guest execution would have to reset up a whole lot of state
2500	* anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2501	* the state and flag reloading the entire state on re-entry. So import the entire
2502	* state here, see HMNotifyVmxNstGstVmexit() for more comments.
2503	*/
2504	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2505
2506	/*
2507	* Ensure VM-entry interruption information valid bit is cleared.
2508	*
2509	* We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2510	* by invalid-guest state or machine-check exceptions) also clear this bit.
2511	*
2512	* See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2513	*/
2514	if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2515	pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2516
2517	/*
2518	* Update the VM-exit reason and Exit qualification.
2519	* Other VMCS read-only data fields are expected to be updated by the caller already.
2520	*/
2521	pVmcs->u32RoExitReason = uExitReason;
2522	pVmcs->u64RoExitQual.u = u64ExitQual;
2523
2524	Log2(("vmexit: reason=%u qual=%#RX64 cs:rip=%04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 eflags=%#RX32\n", uExitReason,
2525	pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2526	pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.eflags.u));
2527
2528	/*
2529	* Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2530	* See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2531	*/
2532	{
2533	uint8_t uVector;
2534	uint32_t fFlags;
2535	uint32_t uErrCode;
2536	bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2537	if (fInEventDelivery)
2538	{
2539	/*
2540	* A VM-exit is not considered to occur during event delivery when the VM-exit is
2541	* caused by a triple-fault or the original event results in a double-fault that
2542	* causes the VM exit directly (exception bitmap). Therefore, we must not set the
2543	* original event information into the IDT-vectoring information fields.
2544	*
2545	* See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2546	*/
2547	if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2548	&& ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2549	\|\| !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2550	{
2551	uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2552	uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2553	uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2554	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2555	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2556	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2557	iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2558	iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2559	Log2(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2560	pVCpu->cpum.GstCtx.cr2));
2561	}
2562	}
2563	}
2564
2565	/* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2566	Assert(pVmcs->u64RoIoRcx.u == 0);
2567	Assert(pVmcs->u64RoIoRsi.u == 0);
2568	Assert(pVmcs->u64RoIoRdi.u == 0);
2569	Assert(pVmcs->u64RoIoRip.u == 0);
2570
2571	/*
2572	* Save the guest state back into the VMCS.
2573	* We only need to save the state when the VM-entry was successful.
2574	*/
2575	bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2576	if (!fVmentryFailed)
2577	{
2578	/* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2579	if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2580	{
2581	Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2582	Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2583	}
2584
2585	/* For exception or NMI VM-exits, the VM-exit interruption info. field must be valid. */
2586	Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI \|\| VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2587
2588	/* For external interrupts that occur while "acknowledge interrupt on exit" VM-exit is set,
2589	the VM-exit interruption info. field must be valid. */
2590	Assert( uExitReason != VMX_EXIT_EXT_INT
2591	\|\| !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
2592	\|\| VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2593
2594	/*
2595	* If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2596	* See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2597	*
2598	* It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2599	* If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2600	* as guest-CPU state would not been modified. Hence for now, we do this only when
2601	* the VM-entry succeeded.
2602	*/
2603	/** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2604	* hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2605	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2606	{
2607	if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2608	pVmcs->u32EntryCtls \|= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2609	else
2610	pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2611	}
2612
2613	/*
2614	* The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2615	* occurs in enclave mode/SMM which we don't support yet.
2616	*
2617	* If we ever add support for it, we can pass just the lower bits to the functions
2618	* below, till then an assert should suffice.
2619	*/
2620	Assert(!RT_HI_U16(uExitReason));
2621
2622	/* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2623	iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2624	int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2625	if (RT_SUCCESS(rc))
2626	{ /* likely */ }
2627	else
2628	return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2629
2630	/* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2631	pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit &= ~CPUMCTX_INHIBIT_NMI;
2632	}
2633	else
2634	{
2635	/* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2636	uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2637	if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2638	\|\| uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2639	iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2640	}
2641
2642	/*
2643	* Stop any running VMX-preemption timer if necessary.
2644	*/
2645	if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2646	CPUMStopGuestVmxPremptTimer(pVCpu);
2647
2648	/*
2649	* Clear the state of "NMI unblocked due to IRET" as otherwise we risk
2650	* reporting a stale state on a subsequent VM-exit. This state will be
2651	* re-established while emulating IRET in VMX non-root mode.
2652	*/
2653	pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret = false;
2654
2655	/*
2656	* Clear any pending VMX nested-guest force-flags.
2657	* These force-flags have no effect on (outer) guest execution and will
2658	* be re-evaluated and setup on the next nested-guest VM-entry.
2659	*/
2660	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2661
2662	/*
2663	* We're no longer in nested-guest execution mode.
2664	*
2665	* It is important to do this prior to loading the host state because
2666	* PGM looks at fInVmxNonRootMode to determine if it needs to perform
2667	* second-level address translation while switching to host CR3.
2668	*/
2669	pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2670
2671	/* Restore the host (outer guest) state. */
2672	VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2673	if (RT_SUCCESS(rcStrict))
2674	{
2675	Assert(rcStrict == VINF_SUCCESS);
2676	rcStrict = VINF_VMX_VMEXIT;
2677	}
2678	else
2679	Log(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2680
2681	/*
2682	* Restore non-zero Secondary-processor based VM-execution controls
2683	* when the "activate secondary controls" bit was not set.
2684	*/
2685	if (pVmcs->u32RestoreProcCtls2)
2686	{
2687	Assert(!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS));
2688	pVmcs->u32ProcCtls2 = pVmcs->u32RestoreProcCtls2;
2689	pVmcs->u32RestoreProcCtls2 = 0;
2690	}
2691
2692	if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
2693	{
2694	/* Notify HM that the current VMCS fields have been modified. */
2695	HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2696
2697	/* Notify HM that we've completed the VM-exit. */
2698	HMNotifyVmxNstGstVmexit(pVCpu);
2699	}
2700
2701	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2702	/* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2703	Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2704	int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2705	if (rcSched != VINF_SUCCESS)
2706	iemSetPassUpStatus(pVCpu, rcSched);
2707	# endif
2708	return rcStrict;
2709	# endif
2710	}
2711
2712
2713	/**
2714	* VMX VM-exit handler for VM-exits due to instruction execution.
2715	*
2716	* This is intended for instructions where the caller provides all the relevant
2717	* VM-exit information.
2718	*
2719	* @returns Strict VBox status code.
2720	* @param pVCpu The cross context virtual CPU structure.
2721	* @param pExitInfo Pointer to the VM-exit information.
2722	*/
2723	static VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
2724	{
2725	/*
2726	* For instructions where any of the following fields are not applicable:
2727	* - Exit qualification must be cleared.
2728	* - VM-exit instruction info. is undefined.
2729	* - Guest-linear address is undefined.
2730	* - Guest-physical address is undefined.
2731	*
2732	* The VM-exit instruction length is mandatory for all VM-exits that are caused by
2733	* instruction execution. For VM-exits that are not due to instruction execution this
2734	* field is undefined.
2735	*
2736	* In our implementation in IEM, all undefined fields are generally cleared. However,
2737	* if the caller supplies information (from say the physical CPU directly) it is
2738	* then possible that the undefined fields are not cleared.
2739	*
2740	* See Intel spec. 27.2.1 "Basic VM-Exit Information".
2741	* See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2742	*/
2743	Assert(pExitInfo);
2744	AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2745	AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2746	("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2747
2748	/* Update all the relevant fields from the VM-exit instruction information struct. */
2749	iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2750	iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2751	iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2752	iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2753
2754	/* Perform the VM-exit. */
2755	return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2756	}
2757
2758
2759	/**
2760	* VMX VM-exit handler for VM-exits due to instruction execution.
2761	*
2762	* This is intended for instructions that only provide the VM-exit instruction
2763	* length.
2764	*
2765	* @param pVCpu The cross context virtual CPU structure.
2766	* @param uExitReason The VM-exit reason.
2767	* @param cbInstr The instruction length in bytes.
2768	*/
2769	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT
2770	{
2771	#ifdef VBOX_STRICT
2772	/*
2773	* To prevent us from shooting ourselves in the foot.
2774	* The follow instructions should convey more than just the instruction length.
2775	*/
2776	switch (uExitReason)
2777	{
2778	case VMX_EXIT_INVEPT:
2779	case VMX_EXIT_INVPCID:
2780	case VMX_EXIT_INVVPID:
2781	case VMX_EXIT_LDTR_TR_ACCESS:
2782	case VMX_EXIT_GDTR_IDTR_ACCESS:
2783	case VMX_EXIT_VMCLEAR:
2784	case VMX_EXIT_VMPTRLD:
2785	case VMX_EXIT_VMPTRST:
2786	case VMX_EXIT_VMREAD:
2787	case VMX_EXIT_VMWRITE:
2788	case VMX_EXIT_VMXON:
2789	case VMX_EXIT_XRSTORS:
2790	case VMX_EXIT_XSAVES:
2791	case VMX_EXIT_RDRAND:
2792	case VMX_EXIT_RDSEED:
2793	case VMX_EXIT_IO_INSTR:
2794	AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2795	break;
2796	}
2797	#endif
2798
2799	VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_INSTR_LEN(uExitReason, cbInstr);
2800	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2801	}
2802
2803
2804	/**
2805	* Interface for HM and EM to emulate VM-exit due to a triple-fault.
2806	*
2807	* @returns Strict VBox status code.
2808	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2809	* @thread EMT(pVCpu)
2810	*/
2811	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu)
2812	{
2813	VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
2814	Assert(!pVCpu->iem.s.cActiveMappings);
2815	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2816	}
2817
2818
2819	/**
2820	* Interface for HM and EM to emulate VM-exit due to startup-IPI (SIPI).
2821	*
2822	* @returns Strict VBox status code.
2823	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2824	* @param uVector The SIPI vector.
2825	* @thread EMT(pVCpu)
2826	*/
2827	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector)
2828	{
2829	VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_SIPI, uVector);
2830	Assert(!pVCpu->iem.s.cActiveMappings);
2831	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2832	}
2833
2834
2835	/**
2836	* Interface for HM and EM to emulate a VM-exit.
2837	*
2838	* If a specialized version of a VM-exit handler exists, that must be used instead.
2839	*
2840	* @returns Strict VBox status code.
2841	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2842	* @param uExitReason The VM-exit reason.
2843	* @param u64ExitQual The Exit qualification.
2844	* @thread EMT(pVCpu)
2845	*/
2846	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2847	{
2848	VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, uExitReason, u64ExitQual);
2849	Assert(!pVCpu->iem.s.cActiveMappings);
2850	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2851	}
2852
2853
2854	/**
2855	* Interface for HM and EM to emulate a VM-exit due to an instruction.
2856	*
2857	* This is meant to be used for those instructions that VMX provides additional
2858	* decoding information beyond just the instruction length!
2859	*
2860	* @returns Strict VBox status code.
2861	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2862	* @param pExitInfo Pointer to the VM-exit information.
2863	* @thread EMT(pVCpu)
2864	*/
2865	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2866	{
2867	VBOXSTRICTRC rcStrict = iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
2868	Assert(!pVCpu->iem.s.cActiveMappings);
2869	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2870	}
2871
2872
2873	/**
2874	* Interface for HM and EM to emulate a VM-exit due to an instruction.
2875	*
2876	* This is meant to be used for those instructions that VMX provides only the
2877	* instruction length.
2878	*
2879	* @returns Strict VBox status code.
2880	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2881	* @param pExitInfo Pointer to the VM-exit information.
2882	* @param cbInstr The instruction length in bytes.
2883	* @thread EMT(pVCpu)
2884	*/
2885	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2886	{
2887	VBOXSTRICTRC rcStrict = iemVmxVmexitInstr(pVCpu, uExitReason, cbInstr);
2888	Assert(!pVCpu->iem.s.cActiveMappings);
2889	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2890	}
2891
2892
2893	/**
2894	* VMX VM-exit handler for VM-exits due to instruction execution.
2895	*
2896	* This is intended for instructions that have a ModR/M byte and update the VM-exit
2897	* instruction information and Exit qualification fields.
2898	*
2899	* @param pVCpu The cross context virtual CPU structure.
2900	* @param uExitReason The VM-exit reason.
2901	* @param uInstrid The instruction identity (VMXINSTRID_XXX).
2902	* @param cbInstr The instruction length in bytes.
2903	*
2904	* @remarks Do not use this for INS/OUTS instruction.
2905	*/
2906	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT
2907	{
2908	#ifdef VBOX_STRICT
2909	/*
2910	* To prevent us from shooting ourselves in the foot.
2911	* The follow instructions convey specific info that require using their respective handlers.
2912	*/
2913	switch (uExitReason)
2914	{
2915	case VMX_EXIT_INVEPT:
2916	case VMX_EXIT_INVPCID:
2917	case VMX_EXIT_INVVPID:
2918	case VMX_EXIT_LDTR_TR_ACCESS:
2919	case VMX_EXIT_GDTR_IDTR_ACCESS:
2920	case VMX_EXIT_VMCLEAR:
2921	case VMX_EXIT_VMPTRLD:
2922	case VMX_EXIT_VMPTRST:
2923	case VMX_EXIT_VMREAD:
2924	case VMX_EXIT_VMWRITE:
2925	case VMX_EXIT_VMXON:
2926	case VMX_EXIT_XRSTORS:
2927	case VMX_EXIT_XSAVES:
2928	case VMX_EXIT_RDRAND:
2929	case VMX_EXIT_RDSEED:
2930	break;
2931	default:
2932	AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2933	break;
2934	}
2935	#endif
2936
2937	/*
2938	* Update the Exit qualification field with displacement bytes.
2939	* See Intel spec. 27.2.1 "Basic VM-Exit Information".
2940	*/
2941	/* Construct the VM-exit instruction information. */
2942	RTGCPTR GCPtrDisp;
2943	uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2944
2945	VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO(uExitReason, GCPtrDisp, uInstrInfo, cbInstr);
2946	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2947	}
2948
2949
2950	/**
2951	* VMX VM-exit handler for VM-exits due to INVLPG.
2952	*
2953	* @returns Strict VBox status code.
2954	* @param pVCpu The cross context virtual CPU structure.
2955	* @param GCPtrPage The guest-linear address of the page being invalidated.
2956	* @param cbInstr The instruction length in bytes.
2957	*/
2958	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT
2959	{
2960	VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_INVLPG, GCPtrPage, cbInstr);
2961	Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode \|\| !RT_HI_U32(ExitInfo.u64Qual));
2962	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2963	}
2964
2965
2966	/**
2967	* VMX VM-exit handler for VM-exits due to LMSW.
2968	*
2969	* @returns Strict VBox status code.
2970	* @param pVCpu The cross context virtual CPU structure.
2971	* @param uGuestCr0 The current guest CR0.
2972	* @param pu16NewMsw The machine-status word specified in LMSW's source
2973	* operand. This will be updated depending on the VMX
2974	* guest/host CR0 mask if LMSW is not intercepted.
2975	* @param GCPtrEffDst The guest-linear address of the source operand in case
2976	* of a memory operand. For register operand, pass
2977	* NIL_RTGCPTR.
2978	* @param cbInstr The instruction length in bytes.
2979	*/
2980	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
2981	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT
2982	{
2983	Assert(pu16NewMsw);
2984
2985	uint16_t const uNewMsw = *pu16NewMsw;
2986	if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2987	{
2988	Log2(("lmsw: Guest intercept -> VM-exit\n"));
2989	bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2990	VMXVEXITINFO ExitInfo
2991	= VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
2992	RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2993	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2994	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw)
2995	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW),
2996	cbInstr);
2997	if (fMemOperand)
2998	{
2999	Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode \|\| !RT_HI_U32(GCPtrEffDst));
3000	ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3001	}
3002	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3003	}
3004
3005	/*
3006	* If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3007	* CR0 guest/host mask must be left unmodified.
3008	*
3009	* See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3010	*/
3011	uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3012	uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS);
3013	*pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) \| (uNewMsw & ~fGstHostLmswMask);
3014
3015	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3016	}
3017
3018
3019	/**
3020	* VMX VM-exit handler for VM-exits due to CLTS.
3021	*
3022	* @returns Strict VBox status code.
3023	* @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3024	* VM-exit but must not modify the guest CR0.TS bit.
3025	* @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3026	* VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3027	* CR0 fixed bits in VMX operation).
3028	* @param pVCpu The cross context virtual CPU structure.
3029	* @param cbInstr The instruction length in bytes.
3030	*/
3031	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3032	{
3033	/*
3034	* If CR0.TS is owned by the host:
3035	* - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3036	* - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3037	* CLTS instruction completes without clearing CR0.TS.
3038	*
3039	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3040	*/
3041	uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3042	if (fGstHostMask & X86_CR0_TS)
3043	{
3044	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u & X86_CR0_TS)
3045	{
3046	Log2(("clts: Guest intercept -> VM-exit\n"));
3047	VMXVEXITINFO const ExitInfo
3048	= VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3049	RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3050	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
3051	VMX_EXIT_QUAL_CRX_ACCESS_CLTS),
3052	cbInstr);
3053	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3054	}
3055	return VINF_VMX_MODIFIES_BEHAVIOR;
3056	}
3057
3058	/*
3059	* If CR0.TS is not owned by the host, the CLTS instructions operates normally
3060	* and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3061	*/
3062	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3063	}
3064
3065
3066	/**
3067	* VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3068	* (CR0/CR4 write).
3069	*
3070	* @returns Strict VBox status code.
3071	* @param pVCpu The cross context virtual CPU structure.
3072	* @param iCrReg The control register (either CR0 or CR4).
3073	* @param uGuestCrX The current guest CR0/CR4.
3074	* @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
3075	* VM-exit is caused.
3076	* @param iGReg The general register from which the CR0/CR4 value is being
3077	* loaded.
3078	* @param cbInstr The instruction length in bytes.
3079	*/
3080	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX,
3081	uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3082	{
3083	Assert(puNewCrX);
3084	Assert(iCrReg == 0 \|\| iCrReg == 4);
3085	Assert(iGReg < X86_GREG_COUNT);
3086
3087	uint64_t const uNewCrX = *puNewCrX;
3088	if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3089	{
3090	Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3091	VMXVEXITINFO const ExitInfo
3092	= VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3093	RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3094	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3095	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3096	cbInstr);
3097	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3098	}
3099
3100	/*
3101	* If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3102	* must not be modified the instruction.
3103	*
3104	* See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3105	*/
3106	uint64_t uGuestCrX;
3107	uint64_t fGstHostMask;
3108	if (iCrReg == 0)
3109	{
3110	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3111	uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3112	fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3113	}
3114	else
3115	{
3116	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3117	uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3118	fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
3119	}
3120
3121	puNewCrX = (uGuestCrX & fGstHostMask) \| (puNewCrX & ~fGstHostMask);
3122	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3123	}
3124
3125
3126	/**
3127	* VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3128	*
3129	* @returns VBox strict status code.
3130	* @param pVCpu The cross context virtual CPU structure.
3131	* @param iGReg The general register to which the CR3 value is being stored.
3132	* @param cbInstr The instruction length in bytes.
3133	*/
3134	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3135	{
3136	Assert(iGReg < X86_GREG_COUNT);
3137	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3138
3139	/*
3140	* If the CR3-store exiting control is set, we must cause a VM-exit.
3141	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3142	*/
3143	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3144	{
3145	Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3146	VMXVEXITINFO const ExitInfo
3147	= VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3148	RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3149	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3150	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3151	cbInstr);
3152	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3153	}
3154	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3155	}
3156
3157
3158	/**
3159	* VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3160	*
3161	* @returns VBox strict status code.
3162	* @param pVCpu The cross context virtual CPU structure.
3163	* @param uNewCr3 The new CR3 value.
3164	* @param iGReg The general register from which the CR3 value is being
3165	* loaded.
3166	* @param cbInstr The instruction length in bytes.
3167	*/
3168	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3169	{
3170	Assert(iGReg < X86_GREG_COUNT);
3171
3172	/*
3173	* If the CR3-load exiting control is set and the new CR3 value does not
3174	* match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3175	*
3176	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3177	*/
3178	if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3179	{
3180	Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3181	VMXVEXITINFO const ExitInfo
3182	= VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3183	RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3184	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3185	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
3186	VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3187	cbInstr);
3188	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3189	}
3190	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3191	}
3192
3193
3194	/**
3195	* VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3196	*
3197	* @returns VBox strict status code.
3198	* @param pVCpu The cross context virtual CPU structure.
3199	* @param iGReg The general register to which the CR8 value is being stored.
3200	* @param cbInstr The instruction length in bytes.
3201	*/
3202	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3203	{
3204	Assert(iGReg < X86_GREG_COUNT);
3205
3206	/*
3207	* If the CR8-store exiting control is set, we must cause a VM-exit.
3208	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3209	*/
3210	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3211	{
3212	Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3213	VMXVEXITINFO const ExitInfo
3214	= VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3215	RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3216	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3217	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3218	cbInstr);
3219	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3220	}
3221	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3222	}
3223
3224
3225	/**
3226	* VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3227	*
3228	* @returns VBox strict status code.
3229	* @param pVCpu The cross context virtual CPU structure.
3230	* @param iGReg The general register from which the CR8 value is being
3231	* loaded.
3232	* @param cbInstr The instruction length in bytes.
3233	*/
3234	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3235	{
3236	Assert(iGReg < X86_GREG_COUNT);
3237
3238	/*
3239	* If the CR8-load exiting control is set, we must cause a VM-exit.
3240	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3241	*/
3242	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3243	{
3244	Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3245	VMXVEXITINFO const ExitInfo
3246	= VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3247	RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3248	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3249	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3250	cbInstr);
3251	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3252	}
3253	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3254	}
3255
3256
3257	/**
3258	* VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3259	* GReg,DRx' (DRx read).
3260	*
3261	* @returns VBox strict status code.
3262	* @param pVCpu The cross context virtual CPU structure.
3263	* @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3264	* VMXINSTRID_MOV_FROM_DRX).
3265	* @param iDrReg The debug register being accessed.
3266	* @param iGReg The general register to/from which the DRx value is being
3267	* store/loaded.
3268	* @param cbInstr The instruction length in bytes.
3269	*/
3270	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg,
3271	uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3272	{
3273	Assert(iDrReg <= 7);
3274	Assert(uInstrId == VMXINSTRID_MOV_TO_DRX \|\| uInstrId == VMXINSTRID_MOV_FROM_DRX);
3275	Assert(iGReg < X86_GREG_COUNT);
3276
3277	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3278	{
3279	VMXVEXITINFO const ExitInfo
3280	= VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_DRX,
3281	RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3282	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg)
3283	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION,
3284	uInstrId == VMXINSTRID_MOV_TO_DRX
3285	? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3286	: VMX_EXIT_QUAL_DRX_DIRECTION_READ),
3287	cbInstr);
3288	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3289	}
3290
3291	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3292	}
3293
3294
3295	/**
3296	* VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3297	*
3298	* @returns VBox strict status code.
3299	* @param pVCpu The cross context virtual CPU structure.
3300	* @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3301	* VMXINSTRID_IO_OUT).
3302	* @param u16Port The I/O port being accessed.
3303	* @param fImm Whether the I/O port was encoded using an immediate operand
3304	* or the implicit DX register.
3305	* @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3306	* @param cbInstr The instruction length in bytes.
3307	*/
3308	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3309	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT
3310	{
3311	Assert(uInstrId == VMXINSTRID_IO_IN \|\| uInstrId == VMXINSTRID_IO_OUT);
3312	Assert(cbAccess == 1 \|\| cbAccess == 2 \|\| cbAccess == 4);
3313
3314	if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3315	{
3316	VMXVEXITINFO const ExitInfo
3317	= VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_IO_INSTR,
3318	RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3319	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3320	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port)
3321	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION,
3322	uInstrId == VMXINSTRID_IO_IN
3323	? VMX_EXIT_QUAL_IO_DIRECTION_IN
3324	: VMX_EXIT_QUAL_IO_DIRECTION_OUT),
3325	cbInstr);
3326	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3327	}
3328	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3329	}
3330
3331
3332	/**
3333	* VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3334	*
3335	* @returns VBox strict status code.
3336	* @param pVCpu The cross context virtual CPU structure.
3337	* @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3338	* VMXINSTRID_IO_OUTS).
3339	* @param u16Port The I/O port being accessed.
3340	* @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3341	* @param fRep Whether the instruction has a REP prefix or not.
3342	* @param ExitInstrInfo The VM-exit instruction info. field.
3343	* @param cbInstr The instruction length in bytes.
3344	*/
3345	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3346	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT
3347	{
3348	Assert(uInstrId == VMXINSTRID_IO_INS \|\| uInstrId == VMXINSTRID_IO_OUTS);
3349	Assert(cbAccess == 1 \|\| cbAccess == 2 \|\| cbAccess == 4);
3350	Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3351	Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 \|\| ExitInstrInfo.StrIo.u3AddrSize == 1 \|\| ExitInstrInfo.StrIo.u3AddrSize == 2);
3352	Assert(uInstrId != VMXINSTRID_IO_INS \|\| ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3353
3354	if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3355	{
3356	/*
3357	* Figure out the guest-linear address and the direction bit (INS/OUTS).
3358	*/
3359	/** @todo r=ramshankar: Is there something in IEM that already does this? */
3360	static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3361	uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3362	uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3363	uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3364
3365	uint32_t uDirection;
3366	uint64_t uGuestLinearAddr;
3367	if (uInstrId == VMXINSTRID_IO_INS)
3368	{
3369	uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3370	uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3371	}
3372	else
3373	{
3374	uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3375	uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3376	}
3377
3378	/*
3379	* If the segment is unusable, the guest-linear address in undefined.
3380	* We shall clear it for consistency.
3381	*
3382	* See Intel spec. 27.2.1 "Basic VM-Exit Information".
3383	*/
3384	if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3385	uGuestLinearAddr = 0;
3386
3387	VMXVEXITINFO const ExitInfo
3388	= VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO_AND_LIN_ADDR(VMX_EXIT_IO_INSTR,
3389	RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3390	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3391	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3392	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3393	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING,
3394	VMX_EXIT_QUAL_IO_ENCODING_DX)
3395	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port),
3396	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo
3397	? ExitInstrInfo.u : 0,
3398	cbInstr,
3399	uGuestLinearAddr);
3400	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3401	}
3402
3403	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3404	}
3405
3406
3407	/**
3408	* VMX VM-exit handler for VM-exits due to MWAIT.
3409	*
3410	* @returns VBox strict status code.
3411	* @param pVCpu The cross context virtual CPU structure.
3412	* @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3413	* @param cbInstr The instruction length in bytes.
3414	*/
3415	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT
3416	{
3417	VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MWAIT, fMonitorHwArmed, cbInstr);
3418	return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3419	}
3420
3421
3422	/**
3423	* VMX VM-exit handler for VM-exits due to PAUSE.
3424	*
3425	* @returns VBox strict status code.
3426	* @param pVCpu The cross context virtual CPU structure.
3427	* @param cbInstr The instruction length in bytes.
3428	*/
3429	static VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3430	{
3431	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3432
3433	/*
3434	* The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3435	* "PAUSE-loop exiting" control.
3436	*
3437	* The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3438	* the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3439	* of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3440	* a VM-exit.
3441	*
3442	* See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3443	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3444	*/
3445	bool fIntercept = false;
3446	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3447	fIntercept = true;
3448	else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3449	&& IEM_GET_CPL(pVCpu) == 0)
3450	{
3451	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3452
3453	/*
3454	* A previous-PAUSE-tick value of 0 is used to identify the first time
3455	* execution of a PAUSE instruction after VM-entry at CPL 0. We must
3456	* consider this to be the first execution of PAUSE in a loop according
3457	* to the Intel.
3458	*
3459	* All subsequent records for the previous-PAUSE-tick we ensure that it
3460	* cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3461	*/
3462	uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3463	uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3464	uint64_t const uTick = TMCpuTickGet(pVCpu);
3465	uint32_t const uPleGap = pVmcs->u32PleGap;
3466	uint32_t const uPleWindow = pVmcs->u32PleWindow;
3467	if ( *puPrevPauseTick == 0
3468	\|\| uTick - *puPrevPauseTick > uPleGap)
3469	*puFirstPauseLoopTick = uTick;
3470	else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3471	fIntercept = true;
3472
3473	*puPrevPauseTick = uTick \| 1;
3474	}
3475
3476	if (fIntercept)
3477	return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3478
3479	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3480	}
3481
3482
3483	/**
3484	* VMX VM-exit handler for VM-exits due to task switches.
3485	*
3486	* @returns VBox strict status code.
3487	* @param pVCpu The cross context virtual CPU structure.
3488	* @param enmTaskSwitch The cause of the task switch.
3489	* @param SelNewTss The selector of the new TSS.
3490	* @param cbInstr The instruction length in bytes.
3491	*/
3492	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT
3493	{
3494	/*
3495	* Task-switch VM-exits are unconditional and provide the Exit qualification.
3496	*
3497	* If the cause of the task switch is due to execution of CALL, IRET or the JMP
3498	* instruction or delivery of the exception generated by one of these instructions
3499	* lead to a task switch through a task gate in the IDT, we need to provide the
3500	* VM-exit instruction length. Any other means of invoking a task switch VM-exit
3501	* leaves the VM-exit instruction length field undefined.
3502	*
3503	* See Intel spec. 25.2 "Other Causes Of VM Exits".
3504	* See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3505	*/
3506	Assert(cbInstr <= 15);
3507
3508	uint8_t uType;
3509	switch (enmTaskSwitch)
3510	{
3511	case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3512	case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3513	case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3514	case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3515	IEM_NOT_REACHED_DEFAULT_CASE_RET();
3516	}
3517
3518	uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3519	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3520	iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3521	return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3522	}
3523
3524
3525	/**
3526	* VMX VM-exit handler for trap-like VM-exits.
3527	*
3528	* @returns VBox strict status code.
3529	* @param pVCpu The cross context virtual CPU structure.
3530	* @param pExitInfo Pointer to the VM-exit information.
3531	* @param pExitEventInfo Pointer to the VM-exit event information.
3532	*/
3533	static VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
3534	{
3535	Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3536	iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3537	return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3538	}
3539
3540
3541	/**
3542	* Interface for HM and EM to emulate a trap-like VM-exit (MTF, APIC-write,
3543	* Virtualized-EOI, TPR-below threshold).
3544	*
3545	* @returns Strict VBox status code.
3546	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
3547	* @param pExitInfo Pointer to the VM-exit information.
3548	* @thread EMT(pVCpu)
3549	*/
3550	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3551	{
3552	Assert(pExitInfo);
3553	VBOXSTRICTRC rcStrict = iemVmxVmexitTrapLikeWithInfo(pVCpu, pExitInfo);
3554	Assert(!pVCpu->iem.s.cActiveMappings);
3555	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3556	}
3557
3558
3559	/**
3560	* VMX VM-exit handler for VM-exits due to task switches.
3561	*
3562	* This is intended for task switches where the caller provides all the relevant
3563	* VM-exit information.
3564	*
3565	* @returns VBox strict status code.
3566	* @param pVCpu The cross context virtual CPU structure.
3567	* @param pExitInfo Pointer to the VM-exit information.
3568	* @param pExitEventInfo Pointer to the VM-exit event information.
3569	*/
3570	static VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3571	PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3572	{
3573	Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3574	iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3575	iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3576	iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3577	return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3578	}
3579
3580
3581	/**
3582	* Interface for HM and EM to emulate a VM-exit due to a task switch.
3583	*
3584	* @returns Strict VBox status code.
3585	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
3586	* @param pExitInfo Pointer to the VM-exit information.
3587	* @param pExitEventInfo Pointer to the VM-exit event information.
3588	* @thread EMT(pVCpu)
3589	*/
3590	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3591	{
3592	Assert(pExitInfo);
3593	Assert(pExitEventInfo);
3594	Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3595	VBOXSTRICTRC rcStrict = iemVmxVmexitTaskSwitchWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3596	Assert(!pVCpu->iem.s.cActiveMappings);
3597	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3598	}
3599
3600
3601	/**
3602	* VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3603	*
3604	* @returns VBox strict status code.
3605	* @param pVCpu The cross context virtual CPU structure.
3606	*/
3607	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
3608	{
3609	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3610	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3611
3612	/* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3613	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3614
3615	/* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3616	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3617	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3618
3619	/* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3620	return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3621	}
3622
3623
3624	/**
3625	* Interface for HM and EM to emulate VM-exit due to expiry of the preemption timer.
3626	*
3627	* @returns Strict VBox status code.
3628	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
3629	* @thread EMT(pVCpu)
3630	*/
3631	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3632	{
3633	VBOXSTRICTRC rcStrict = iemVmxVmexitPreemptTimer(pVCpu);
3634	Assert(!pVCpu->iem.s.cActiveMappings);
3635	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3636	}
3637
3638
3639	/**
3640	* VMX VM-exit handler for VM-exits due to external interrupts.
3641	*
3642	* @returns VBox strict status code.
3643	* @param pVCpu The cross context virtual CPU structure.
3644	* @param uVector The external interrupt vector (pass 0 if the interrupt
3645	* is still pending since we typically won't know the
3646	* vector).
3647	* @param fIntPending Whether the external interrupt is pending or
3648	* acknowledged in the interrupt controller.
3649	*/
3650	static VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending) RT_NOEXCEPT
3651	{
3652	Assert(!fIntPending \|\| uVector == 0);
3653
3654	/* The VM-exit is subject to "External interrupt exiting" being set. */
3655	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3656	{
3657	if (fIntPending)
3658	{
3659	/*
3660	* If the interrupt is pending and we don't need to acknowledge the
3661	* interrupt on VM-exit, cause the VM-exit immediately.
3662	*
3663	* See Intel spec 25.2 "Other Causes Of VM Exits".
3664	*/
3665	if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3666	return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3667
3668	/*
3669	* If the interrupt is pending and we -do- need to acknowledge the interrupt
3670	* on VM-exit, postpone VM-exit till after the interrupt controller has been
3671	* acknowledged that the interrupt has been consumed. Callers would have to call
3672	* us again after getting the vector (and ofc, with fIntPending with false).
3673	*/
3674	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3675	}
3676
3677	/*
3678	* If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3679	* "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3680	* all set, we need to record the vector of the external interrupt in the
3681	* VM-exit interruption information field. Otherwise, mark this field as invalid.
3682	*
3683	* See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3684	*/
3685	uint32_t uExitIntInfo;
3686	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3687	{
3688	bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3689	uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3690	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3691	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3692	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3693	}
3694	else
3695	uExitIntInfo = 0;
3696	iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3697
3698	/*
3699	* Cause the VM-exit whether or not the vector has been stored
3700	* in the VM-exit interruption-information field.
3701	*/
3702	return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3703	}
3704
3705	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3706	}
3707
3708
3709	/**
3710	* Interface for HM and EM to emulate VM-exit due to external interrupts.
3711	*
3712	* @returns Strict VBox status code.
3713	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
3714	* @param uVector The external interrupt vector (pass 0 if the external
3715	* interrupt is still pending).
3716	* @param fIntPending Whether the external interrupt is pending or
3717	* acknowledged in the interrupt controller.
3718	* @thread EMT(pVCpu)
3719	*/
3720	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3721	{
3722	VBOXSTRICTRC rcStrict = iemVmxVmexitExtInt(pVCpu, uVector, fIntPending);
3723	Assert(!pVCpu->iem.s.cActiveMappings);
3724	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3725	}
3726
3727
3728	/**
3729	* VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3730	* an event.
3731	*
3732	* @returns VBox strict status code.
3733	* @param pVCpu The cross context virtual CPU structure.
3734	*/
3735	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT
3736	{
3737	uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3738	if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3739	{
3740	/*
3741	* The NMI-unblocking due to IRET field need not be set for double faults.
3742	* See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3743	*/
3744	uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3745	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3746	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3747	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3748	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3749	iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3750	return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3751	}
3752
3753	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3754	}
3755
3756
3757	/**
3758	* VMX VM-exit handler for VM-exit due to delivery of an events.
3759	*
3760	* This is intended for VM-exit due to exceptions or NMIs where the caller provides
3761	* all the relevant VM-exit information.
3762	*
3763	* @returns VBox strict status code.
3764	* @param pVCpu The cross context virtual CPU structure.
3765	* @param pExitInfo Pointer to the VM-exit information.
3766	* @param pExitEventInfo Pointer to the VM-exit event information.
3767	*/
3768	static VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3769	{
3770	Assert(pExitInfo);
3771	Assert(pExitEventInfo);
3772	Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3773	Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3774
3775	iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3776	iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3777	iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3778	iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3779	iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3780	return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3781	}
3782
3783
3784	/**
3785	* Interface for HM and EM to emulate VM-exit due to NMIs.
3786	*
3787	* @returns Strict VBox status code.
3788	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
3789	* @thread EMT(pVCpu)
3790	*/
3791	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu)
3792	{
3793	VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_ONLY_REASON(VMX_EXIT_XCPT_OR_NMI);
3794	VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_INT( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1)
3795	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE,
3796	VMX_EXIT_INT_INFO_TYPE_NMI)
3797	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR,
3798	X86_XCPT_NMI),
3799	0);
3800	VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
3801	Assert(!pVCpu->iem.s.cActiveMappings);
3802	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3803	}
3804
3805
3806	/**
3807	* Interface for HM and EM to emulate VM-exit due to exceptions.
3808	*
3809	* Exception includes NMIs, software exceptions (those generated by INT3 or
3810	* INTO) and privileged software exceptions (those generated by INT1/ICEBP).
3811	*
3812	* @returns Strict VBox status code.
3813	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
3814	* @param pExitInfo Pointer to the VM-exit information.
3815	* @param pExitEventInfo Pointer to the VM-exit event information.
3816	* @thread EMT(pVCpu)
3817	*/
3818	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3819	{
3820	Assert(pExitInfo);
3821	Assert(pExitEventInfo);
3822	VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3823	Assert(!pVCpu->iem.s.cActiveMappings);
3824	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3825	}
3826
3827
3828	/**
3829	* VMX VM-exit handler for VM-exits due to delivery of an event.
3830	*
3831	* @returns VBox strict status code.
3832	* @param pVCpu The cross context virtual CPU structure.
3833	* @param uVector The interrupt / exception vector.
3834	* @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3835	* @param uErrCode The error code associated with the event.
3836	* @param uCr2 The CR2 value in case of a \#PF exception.
3837	* @param cbInstr The instruction length in bytes.
3838	*/
3839	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode,
3840	uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT
3841	{
3842	/*
3843	* If the event is being injected as part of VM-entry, it is -not- subject to event
3844	* intercepts in the nested-guest. However, secondary exceptions that occur during
3845	* injection of any event -are- subject to event interception.
3846	*
3847	* See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3848	*/
3849	if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3850	{
3851	/*
3852	* If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3853	* virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3854	*
3855	* See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3856	*/
3857	if ( uVector == X86_XCPT_NMI
3858	&& (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3859	&& (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3860	pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3861	else
3862	Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3863
3864	CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3865	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3866	}
3867
3868	/*
3869	* We are injecting an external interrupt, check if we need to cause a VM-exit now.
3870	* If not, the caller will continue delivery of the external interrupt as it would
3871	* normally. The interrupt is no longer pending in the interrupt controller at this
3872	* point.
3873	*/
3874	if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3875	{
3876	Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3877	return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3878	}
3879
3880	/*
3881	* Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3882	* and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3883	* interrupts.
3884	*/
3885	Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_T_SOFT_INT));
3886	bool fIntercept;
3887	if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3888	\|\| (fFlags & (IEM_XCPT_FLAGS_BP_INSTR \| IEM_XCPT_FLAGS_OF_INSTR \| IEM_XCPT_FLAGS_ICEBP_INSTR)))
3889	fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3890	else
3891	{
3892	/* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3893	fIntercept = false;
3894	}
3895
3896	/*
3897	* Now that we've determined whether the event causes a VM-exit, we need to construct the
3898	* relevant VM-exit information and cause the VM-exit.
3899	*/
3900	if (fIntercept)
3901	{
3902	Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3903
3904	/* Construct the rest of the event related information fields and cause the VM-exit. */
3905	uint64_t u64ExitQual;
3906	if (uVector == X86_XCPT_PF)
3907	{
3908	Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3909	u64ExitQual = uCr2;
3910	}
3911	else if (uVector == X86_XCPT_DB)
3912	{
3913	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3914	u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3915	}
3916	else
3917	u64ExitQual = 0;
3918
3919	uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3920	bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3921	uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3922	uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3923	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3924	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3925	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3926	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3927	iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3928	iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3929
3930	/*
3931	* For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3932	* software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3933	* length.
3934	*/
3935	if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3936	\|\| (fFlags & (IEM_XCPT_FLAGS_BP_INSTR \| IEM_XCPT_FLAGS_OF_INSTR \| IEM_XCPT_FLAGS_ICEBP_INSTR)))
3937	iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3938	else
3939	iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3940
3941	return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3942	}
3943
3944	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3945	}
3946
3947
3948	/**
3949	* VMX VM-exit handler for EPT misconfiguration.
3950	*
3951	* @param pVCpu The cross context virtual CPU structure.
3952	* @param GCPhysAddr The physical address causing the EPT misconfiguration.
3953	* This need not be page aligned (e.g. nested-guest in real
3954	* mode).
3955	*/
3956	static VBOXSTRICTRC iemVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr) RT_NOEXCEPT
3957	{
3958	iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3959	return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3960	}
3961
3962
3963	/**
3964	* VMX VM-exit handler for EPT misconfiguration.
3965	*
3966	* This is intended for EPT misconfigurations where the caller provides all the
3967	* relevant VM-exit information.
3968	*
3969	* @param pVCpu The cross context virtual CPU structure.
3970	* @param GCPhysAddr The physical address causing the EPT misconfiguration.
3971	* This need not be page aligned (e.g. nested-guest in real
3972	* mode).
3973	* @param pExitEventInfo Pointer to the VM-exit event information.
3974	*/
3975	static VBOXSTRICTRC iemVmxVmexitEptMisconfigWithInfo(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3976	{
3977	Assert(pExitEventInfo);
3978	Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3979	iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3980	iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3981	iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3982	return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3983	}
3984
3985
3986	/**
3987	* Interface for HM and EM to emulate a VM-exit due to an EPT misconfiguration.
3988	*
3989	* @returns Strict VBox status code.
3990	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
3991	* @param GCPhysAddr The nested-guest physical address causing the EPT
3992	* misconfiguration.
3993	* @param pExitEventInfo Pointer to the VM-exit event information.
3994	* @thread EMT(pVCpu)
3995	*/
3996	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo)
3997	{
3998	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI);
3999
4000	iemInitExec(pVCpu, 0 /fExecOpts/);
4001	VBOXSTRICTRC rcStrict = iemVmxVmexitEptMisconfigWithInfo(pVCpu, GCPhysAddr, pExitEventInfo);
4002	Assert(!pVCpu->iem.s.cActiveMappings);
4003	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
4004	}
4005
4006
4007	/**
4008	* VMX VM-exit handler for EPT violation.
4009	*
4010	* @param pVCpu The cross context virtual CPU structure.
4011	* @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
4012	* @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
4013	* @param fEptAccess The EPT paging structure bits.
4014	* @param GCPhysAddr The physical address causing the EPT violation. This
4015	* need not be page aligned (e.g. nested-guest in real
4016	* mode).
4017	* @param fIsLinearAddrValid Whether translation of a linear address caused this
4018	* EPT violation. If @c false, GCPtrAddr must be 0.
4019	* @param GCPtrAddr The linear address causing the EPT violation.
4020	* @param cbInstr The VM-exit instruction length.
4021	*/
4022	static VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail,
4023	uint64_t fEptAccess, RTGCPHYS GCPhysAddr, bool fIsLinearAddrValid,
4024	uint64_t GCPtrAddr, uint8_t cbInstr) RT_NOEXCEPT
4025	{
4026	/*
4027	* If the linear address isn't valid (can happen when loading PDPTEs
4028	* as part of MOV CR execution) the linear address field is undefined.
4029	* While we can leave it this way, it's preferable to zero it for consistency.
4030	*/
4031	Assert(fIsLinearAddrValid \|\| GCPtrAddr == 0);
4032
4033	uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
4034	bool const fSupportsAccessDirty = RT_BOOL(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
4035
4036	uint32_t const fDataRdMask = IEM_ACCESS_WHAT_MASK \| IEM_ACCESS_TYPE_READ;
4037	uint32_t const fDataWrMask = IEM_ACCESS_WHAT_MASK \| IEM_ACCESS_TYPE_WRITE;
4038	uint32_t const fInstrMask = IEM_ACCESS_WHAT_MASK \| IEM_ACCESS_TYPE_EXEC;
4039	bool const fDataRead = ((fAccess & fDataRdMask) == IEM_ACCESS_DATA_R) \| fSupportsAccessDirty;
4040	bool const fDataWrite = ((fAccess & fDataWrMask) == IEM_ACCESS_DATA_W) \| fSupportsAccessDirty;
4041	bool const fInstrFetch = ((fAccess & fInstrMask) == IEM_ACCESS_INSTRUCTION);
4042	bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
4043	bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
4044	bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
4045	bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4046	bool const fIsLinearToPhysAddr = fIsLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
4047
4048	uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
4049	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
4050	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
4051	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
4052	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
4053	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
4054	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fIsLinearAddrValid)
4055	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fIsLinearToPhysAddr)
4056	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
4057
4058	#ifdef VBOX_STRICT
4059	uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
4060	uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
4061	Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
4062	Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
4063	Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
4064	Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
4065	#endif
4066
4067	iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
4068	iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
4069	iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4070
4071	return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
4072	}
4073
4074
4075	/**
4076	* VMX VM-exit handler for EPT violation.
4077	*
4078	* This is intended for EPT violations where the caller provides all the
4079	* relevant VM-exit information.
4080	*
4081	* @returns VBox strict status code.
4082	* @param pVCpu The cross context virtual CPU structure.
4083	* @param pExitInfo Pointer to the VM-exit information.
4084	* @param pExitEventInfo Pointer to the VM-exit event information.
4085	*/
4086	static VBOXSTRICTRC iemVmxVmexitEptViolationWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4087	PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4088	{
4089	Assert(pExitInfo);
4090	Assert(pExitEventInfo);
4091	Assert(pExitInfo->uReason == VMX_EXIT_EPT_VIOLATION);
4092	Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4093
4094	iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4095	iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4096
4097	iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
4098	if (pExitInfo->u64Qual & VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK)
4099	iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
4100	else
4101	iemVmxVmcsSetExitGuestLinearAddr(pVCpu, 0);
4102	iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4103	return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, pExitInfo->u64Qual);
4104	}
4105
4106
4107	/**
4108	* Interface for HM and EM to emulate a VM-exit due to an EPT violation.
4109	*
4110	* @returns Strict VBox status code.
4111	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
4112	* @param pExitInfo Pointer to the VM-exit information.
4113	* @param pExitEventInfo Pointer to the VM-exit event information.
4114	* @thread EMT(pVCpu)
4115	*/
4116	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4117	PCVMXVEXITEVENTINFO pExitEventInfo)
4118	{
4119	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI);
4120
4121	iemInitExec(pVCpu, 0 /fExecOpts/);
4122	VBOXSTRICTRC rcStrict = iemVmxVmexitEptViolationWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4123	Assert(!pVCpu->iem.s.cActiveMappings);
4124	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
4125	}
4126
4127
4128	/**
4129	* VMX VM-exit handler for EPT-induced VM-exits.
4130	*
4131	* @param pVCpu The cross context virtual CPU structure.
4132	* @param pWalk The page walk info.
4133	* @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
4134	* @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
4135	* @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
4136	* applicable.
4137	*/
4138	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT
4139	{
4140	Assert(pWalk->fIsSlat);
4141	Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
4142	Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
4143	Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
4144
4145	if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
4146	{
4147	LogFlow(("EptViolation: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4148	uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
4149	return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
4150	pWalk->GCPtr, cbInstr);
4151	}
4152
4153	LogFlow(("EptMisconfig: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4154	Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
4155	return iemVmxVmexitEptMisconfig(pVCpu, pWalk->GCPhysNested);
4156	}
4157
4158
4159	/**
4160	* VMX VM-exit handler for APIC accesses.
4161	*
4162	* @param pVCpu The cross context virtual CPU structure.
4163	* @param offAccess The offset of the register being accessed.
4164	* @param fAccess The type of access, see IEM_ACCESS_XXX.
4165	*/
4166	static VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess) RT_NOEXCEPT
4167	{
4168	VMXAPICACCESS enmAccess;
4169	bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4170	if (fInEventDelivery)
4171	enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4172	else if ((fAccess & (IEM_ACCESS_WHAT_MASK \| IEM_ACCESS_TYPE_MASK)) == IEM_ACCESS_INSTRUCTION)
4173	enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4174	else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4175	enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4176	else
4177	enmAccess = VMXAPICACCESS_LINEAR_READ;
4178
4179	uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4180	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4181	return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4182	}
4183
4184
4185	/**
4186	* VMX VM-exit handler for APIC accesses.
4187	*
4188	* This is intended for APIC accesses where the caller provides all the
4189	* relevant VM-exit information.
4190	*
4191	* @returns VBox strict status code.
4192	* @param pVCpu The cross context virtual CPU structure.
4193	* @param pExitInfo Pointer to the VM-exit information.
4194	* @param pExitEventInfo Pointer to the VM-exit event information.
4195	*/
4196	static VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4197	PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4198	{
4199	/* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4200	Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4201	Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
4202	iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4203	iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4204	iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4205	iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4206	iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4207	return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4208	}
4209
4210
4211	/**
4212	* Interface for HM and EM to virtualize memory-mapped APIC accesses.
4213	*
4214	* @returns Strict VBox status code.
4215	* @retval VINF_VMX_MODIFIES_BEHAVIOR if the memory access was virtualized.
4216	* @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4217	*
4218	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
4219	* @param pExitInfo Pointer to the VM-exit information.
4220	* @param pExitEventInfo Pointer to the VM-exit event information.
4221	* @thread EMT(pVCpu)
4222	*/
4223	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
4224	{
4225	Assert(pExitInfo);
4226	Assert(pExitEventInfo);
4227	VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4228	Assert(!pVCpu->iem.s.cActiveMappings);
4229	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4230	}
4231
4232
4233	/**
4234	* VMX VM-exit handler for APIC-write VM-exits.
4235	*
4236	* @param pVCpu The cross context virtual CPU structure.
4237	* @param offApic The write to the virtual-APIC page offset that caused this
4238	* VM-exit.
4239	*/
4240	static VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic) RT_NOEXCEPT
4241	{
4242	Assert(offApic < XAPIC_OFF_END + 4);
4243	/* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4244	offApic &= UINT16_C(0xfff);
4245	return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4246	}
4247
4248
4249	/**
4250	* Clears any pending virtual-APIC write emulation.
4251	*
4252	* @returns The virtual-APIC offset that was written before clearing it.
4253	* @param pVCpu The cross context virtual CPU structure.
4254	*/
4255	DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
4256	{
4257	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4258	uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4259	pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4260	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4261	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4262	return offVirtApicWrite;
4263	}
4264
4265
4266	/**
4267	* Reads a 32-bit register from the virtual-APIC page at the given offset.
4268	*
4269	* @returns The register from the virtual-APIC page.
4270	* @param pVCpu The cross context virtual CPU structure.
4271	* @param offReg The offset of the register being read.
4272	*/
4273	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4274	{
4275	Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4276
4277	uint32_t uReg = 0;
4278	RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4279	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4280	AssertMsgStmt(RT_SUCCESS(rc),
4281	("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4282	sizeof(uReg), offReg, GCPhysVirtApic, rc),
4283	uReg = 0);
4284	return uReg;
4285	}
4286
4287
4288	/**
4289	* Reads a 64-bit register from the virtual-APIC page at the given offset.
4290	*
4291	* @returns The register from the virtual-APIC page.
4292	* @param pVCpu The cross context virtual CPU structure.
4293	* @param offReg The offset of the register being read.
4294	*/
4295	static uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4296	{
4297	Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4298
4299	uint64_t uReg = 0;
4300	RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4301	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4302	AssertMsgStmt(RT_SUCCESS(rc),
4303	("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4304	sizeof(uReg), offReg, GCPhysVirtApic, rc),
4305	uReg = 0);
4306	return uReg;
4307	}
4308
4309
4310	/**
4311	* Writes a 32-bit register to the virtual-APIC page at the given offset.
4312	*
4313	* @param pVCpu The cross context virtual CPU structure.
4314	* @param offReg The offset of the register being written.
4315	* @param uReg The register value to write.
4316	*/
4317	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT
4318	{
4319	Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4320
4321	RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4322	int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4323	AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4324	sizeof(uReg), offReg, GCPhysVirtApic, rc));
4325	}
4326
4327
4328	/**
4329	* Writes a 64-bit register to the virtual-APIC page at the given offset.
4330	*
4331	* @param pVCpu The cross context virtual CPU structure.
4332	* @param offReg The offset of the register being written.
4333	* @param uReg The register value to write.
4334	*/
4335	static void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg) RT_NOEXCEPT
4336	{
4337	Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4338
4339	RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4340	int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4341	AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4342	sizeof(uReg), offReg, GCPhysVirtApic, rc));
4343	}
4344
4345
4346	/**
4347	* Sets the vector in a virtual-APIC 256-bit sparse register.
4348	*
4349	* @param pVCpu The cross context virtual CPU structure.
4350	* @param offReg The offset of the 256-bit spare register.
4351	* @param uVector The vector to set.
4352	*
4353	* @remarks This is based on our APIC device code.
4354	*/
4355	static void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4356	{
4357	/* Determine the vector offset within the chunk. */
4358	uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4359
4360	/* Read the chunk at the offset. */
4361	uint32_t uReg;
4362	RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4363	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4364	if (RT_SUCCESS(rc))
4365	{
4366	/* Modify the chunk. */
4367	uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4368	uReg \|= RT_BIT(idxVectorBit);
4369
4370	/* Write the chunk. */
4371	rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4372	AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4373	uVector, offReg, GCPhysVirtApic, rc));
4374	}
4375	else
4376	AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4377	uVector, offReg, GCPhysVirtApic, rc));
4378	}
4379
4380
4381	/**
4382	* Clears the vector in a virtual-APIC 256-bit sparse register.
4383	*
4384	* @param pVCpu The cross context virtual CPU structure.
4385	* @param offReg The offset of the 256-bit spare register.
4386	* @param uVector The vector to clear.
4387	*
4388	* @remarks This is based on our APIC device code.
4389	*/
4390	static void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4391	{
4392	/* Determine the vector offset within the chunk. */
4393	uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4394
4395	/* Read the chunk at the offset. */
4396	uint32_t uReg;
4397	RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4398	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4399	if (RT_SUCCESS(rc))
4400	{
4401	/* Modify the chunk. */
4402	uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4403	uReg &= ~RT_BIT(idxVectorBit);
4404
4405	/* Write the chunk. */
4406	rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4407	AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4408	uVector, offReg, GCPhysVirtApic, rc));
4409	}
4410	else
4411	AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4412	uVector, offReg, GCPhysVirtApic, rc));
4413	}
4414
4415
4416	/**
4417	* Checks if a memory access to the APIC-access page must causes an APIC-access
4418	* VM-exit.
4419	*
4420	* @param pVCpu The cross context virtual CPU structure.
4421	* @param offAccess The offset of the register being accessed.
4422	* @param cbAccess The size of the access in bytes.
4423	* @param fAccess The type of access, see IEM_ACCESS_XXX.
4424	*
4425	* @remarks This must not be used for MSR-based APIC-access page accesses!
4426	* @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4427	*/
4428	static bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4429	{
4430	Assert(cbAccess > 0);
4431	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4432
4433	/*
4434	* We must cause a VM-exit if any of the following are true:
4435	* - TPR shadowing isn't active.
4436	* - The access size exceeds 32-bits.
4437	* - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4438	*
4439	* See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4440	* See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4441	*/
4442	if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4443	\|\| cbAccess > sizeof(uint32_t)
4444	\|\| ((offAccess + cbAccess - 1) & 0xc)
4445	\|\| offAccess >= XAPIC_OFF_END + 4)
4446	return true;
4447
4448	/*
4449	* If the access is part of an operation where we have already
4450	* virtualized a virtual-APIC write, we must cause a VM-exit.
4451	*/
4452	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4453	return true;
4454
4455	/*
4456	* Check write accesses to the APIC-access page that cause VM-exits.
4457	*/
4458	if (fAccess & IEM_ACCESS_TYPE_WRITE)
4459	{
4460	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4461	{
4462	/*
4463	* With APIC-register virtualization, a write access to any of the
4464	* following registers are virtualized. Accessing any other register
4465	* causes a VM-exit.
4466	*/
4467	uint16_t const offAlignedAccess = offAccess & 0xfffc;
4468	switch (offAlignedAccess)
4469	{
4470	case XAPIC_OFF_ID:
4471	case XAPIC_OFF_TPR:
4472	case XAPIC_OFF_EOI:
4473	case XAPIC_OFF_LDR:
4474	case XAPIC_OFF_DFR:
4475	case XAPIC_OFF_SVR:
4476	case XAPIC_OFF_ESR:
4477	case XAPIC_OFF_ICR_LO:
4478	case XAPIC_OFF_ICR_HI:
4479	case XAPIC_OFF_LVT_TIMER:
4480	case XAPIC_OFF_LVT_THERMAL:
4481	case XAPIC_OFF_LVT_PERF:
4482	case XAPIC_OFF_LVT_LINT0:
4483	case XAPIC_OFF_LVT_LINT1:
4484	case XAPIC_OFF_LVT_ERROR:
4485	case XAPIC_OFF_TIMER_ICR:
4486	case XAPIC_OFF_TIMER_DCR:
4487	break;
4488	default:
4489	return true;
4490	}
4491	}
4492	else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4493	{
4494	/*
4495	* With virtual-interrupt delivery, a write access to any of the
4496	* following registers are virtualized. Accessing any other register
4497	* causes a VM-exit.
4498	*
4499	* Note! The specification does not allow writing to offsets in-between
4500	* these registers (e.g. TPR + 1 byte) unlike read accesses.
4501	*/
4502	switch (offAccess)
4503	{
4504	case XAPIC_OFF_TPR:
4505	case XAPIC_OFF_EOI:
4506	case XAPIC_OFF_ICR_LO:
4507	break;
4508	default:
4509	return true;
4510	}
4511	}
4512	else
4513	{
4514	/*
4515	* Without APIC-register virtualization or virtual-interrupt delivery,
4516	* only TPR accesses are virtualized.
4517	*/
4518	if (offAccess == XAPIC_OFF_TPR)
4519	{ /* likely */ }
4520	else
4521	return true;
4522	}
4523	}
4524	else
4525	{
4526	/*
4527	* Check read accesses to the APIC-access page that cause VM-exits.
4528	*/
4529	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4530	{
4531	/*
4532	* With APIC-register virtualization, a read access to any of the
4533	* following registers are virtualized. Accessing any other register
4534	* causes a VM-exit.
4535	*/
4536	uint16_t const offAlignedAccess = offAccess & 0xfffc;
4537	switch (offAlignedAccess)
4538	{
4539	/** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4540	case XAPIC_OFF_ID:
4541	case XAPIC_OFF_VERSION:
4542	case XAPIC_OFF_TPR:
4543	case XAPIC_OFF_EOI:
4544	case XAPIC_OFF_LDR:
4545	case XAPIC_OFF_DFR:
4546	case XAPIC_OFF_SVR:
4547	case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4548	case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4549	case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4550	case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4551	case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4552	case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4553	case XAPIC_OFF_ESR:
4554	case XAPIC_OFF_ICR_LO:
4555	case XAPIC_OFF_ICR_HI:
4556	case XAPIC_OFF_LVT_TIMER:
4557	case XAPIC_OFF_LVT_THERMAL:
4558	case XAPIC_OFF_LVT_PERF:
4559	case XAPIC_OFF_LVT_LINT0:
4560	case XAPIC_OFF_LVT_LINT1:
4561	case XAPIC_OFF_LVT_ERROR:
4562	case XAPIC_OFF_TIMER_ICR:
4563	case XAPIC_OFF_TIMER_DCR:
4564	break;
4565	default:
4566	return true;
4567	}
4568	}
4569	else
4570	{
4571	/* Without APIC-register virtualization, only TPR accesses are virtualized. */
4572	if (offAccess == XAPIC_OFF_TPR)
4573	{ /* likely */ }
4574	else
4575	return true;
4576	}
4577	}
4578
4579	/* The APIC access is virtualized, does not cause a VM-exit. */
4580	return false;
4581	}
4582
4583
4584	/**
4585	* Virtualizes a memory-based APIC access by certain instructions even though they
4586	* do not use the address to access memory.
4587	*
4588	* This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4589	* page-faults but do not use the address to access memory.
4590	*
4591	* @param pVCpu The cross context virtual CPU structure.
4592	* @param pGCPhysAccess Pointer to the guest-physical address accessed.
4593	* @param cbAccess The size of the access in bytes.
4594	* @param fAccess The type of access, see IEM_ACCESS_XXX.
4595	*/
4596	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4597	{
4598	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4599	Assert(pGCPhysAccess);
4600
4601	RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
4602	RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4603	Assert(!(GCPhysApic & GUEST_PAGE_OFFSET_MASK));
4604
4605	if (GCPhysAccess == GCPhysApic)
4606	{
4607	uint16_t const offAccess = *pGCPhysAccess & GUEST_PAGE_OFFSET_MASK;
4608	bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4609	if (fIntercept)
4610	return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4611
4612	*pGCPhysAccess = GCPhysApic \| offAccess;
4613	return VINF_VMX_MODIFIES_BEHAVIOR;
4614	}
4615
4616	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4617	}
4618
4619
4620	/**
4621	* Virtualizes a memory-based APIC access.
4622	*
4623	* @returns VBox strict status code.
4624	* @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4625	* @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4626	*
4627	* @param pVCpu The cross context virtual CPU structure.
4628	* @param offAccess The offset of the register being accessed (within the
4629	* APIC-access page).
4630	* @param cbAccess The size of the access in bytes.
4631	* @param pvData Pointer to the data being written or where to store the data
4632	* being read.
4633	* @param fAccess The type of access, see IEM_ACCESS_XXX.
4634	*/
4635	static VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess,
4636	void *pvData, uint32_t fAccess) RT_NOEXCEPT
4637	{
4638	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4639	Assert(pvData);
4640
4641	bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4642	if (fIntercept)
4643	return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4644
4645	if (fAccess & IEM_ACCESS_TYPE_WRITE)
4646	{
4647	/*
4648	* A write access to the APIC-access page that is virtualized (rather than
4649	* causing a VM-exit) writes data to the virtual-APIC page.
4650	*/
4651	uint32_t const u32Data = (uint32_t )pvData;
4652	iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4653
4654	/*
4655	* Record the currently updated APIC offset, as we need this later for figuring
4656	* out whether to perform TPR, EOI or self-IPI virtualization as well as well
4657	* as for supplying the exit qualification when causing an APIC-write VM-exit.
4658	*
4659	* After completion of the current operation, we need to perform TPR virtualization,
4660	* EOI virtualization or APIC-write VM-exit depending on which register was written.
4661	*
4662	* The current operation may be a REP-prefixed string instruction, execution of any
4663	* other instruction, or delivery of an event through the IDT.
4664	*
4665	* Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4666	* performed now but later after completion of the current operation.
4667	*
4668	* See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4669	*/
4670	iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4671
4672	LogFlowFunc(("Write access at offset %#x not intercepted -> Wrote %#RX32\n", offAccess, u32Data));
4673	}
4674	else
4675	{
4676	/*
4677	* A read access from the APIC-access page that is virtualized (rather than
4678	* causing a VM-exit) returns data from the virtual-APIC page.
4679	*
4680	* See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4681	*/
4682	Assert(fAccess & IEM_ACCESS_TYPE_READ);
4683
4684	Assert(cbAccess <= 4);
4685	Assert(offAccess < XAPIC_OFF_END + 4);
4686	static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4687
4688	uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4689	u32Data &= s_auAccessSizeMasks[cbAccess];
4690	(uint32_t )pvData = u32Data;
4691
4692	LogFlowFunc(("Read access at offset %#x not intercepted -> Read %#RX32\n", offAccess, u32Data));
4693	}
4694
4695	return VINF_VMX_MODIFIES_BEHAVIOR;
4696	}
4697
4698
4699	/**
4700	* Virtualizes an MSR-based APIC read access.
4701	*
4702	* @returns VBox strict status code.
4703	* @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4704	* @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4705	* handled by the x2APIC device.
4706	* @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4707	* not within the range of valid MSRs, caller must raise \#GP(0).
4708	* @param pVCpu The cross context virtual CPU structure.
4709	* @param idMsr The x2APIC MSR being read.
4710	* @param pu64Value Where to store the read x2APIC MSR value (only valid when
4711	* VINF_VMX_MODIFIES_BEHAVIOR is returned).
4712	*/
4713	static VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value) RT_NOEXCEPT
4714	{
4715	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4716	Assert(pu64Value);
4717
4718	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4719	{
4720	if ( idMsr >= MSR_IA32_X2APIC_START
4721	&& idMsr <= MSR_IA32_X2APIC_END)
4722	{
4723	uint16_t const offReg = (idMsr & 0xff) << 4;
4724	uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4725	*pu64Value = u64Value;
4726	return VINF_VMX_MODIFIES_BEHAVIOR;
4727	}
4728	return VERR_OUT_OF_RANGE;
4729	}
4730
4731	if (idMsr == MSR_IA32_X2APIC_TPR)
4732	{
4733	uint16_t const offReg = (idMsr & 0xff) << 4;
4734	uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4735	*pu64Value = u64Value;
4736	return VINF_VMX_MODIFIES_BEHAVIOR;
4737	}
4738
4739	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4740	}
4741
4742
4743	/**
4744	* Virtualizes an MSR-based APIC write access.
4745	*
4746	* @returns VBox strict status code.
4747	* @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4748	* @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4749	* not within the range of valid MSRs, caller must raise \#GP(0).
4750	* @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4751	*
4752	* @param pVCpu The cross context virtual CPU structure.
4753	* @param idMsr The x2APIC MSR being written.
4754	* @param u64Value The value of the x2APIC MSR being written.
4755	*/
4756	static VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value) RT_NOEXCEPT
4757	{
4758	/*
4759	* Check if the access is to be virtualized.
4760	* See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4761	*/
4762	if ( idMsr == MSR_IA32_X2APIC_TPR
4763	\|\| ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4764	&& ( idMsr == MSR_IA32_X2APIC_EOI
4765	\|\| idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4766	{
4767	/* Validate the MSR write depending on the register. */
4768	switch (idMsr)
4769	{
4770	case MSR_IA32_X2APIC_TPR:
4771	case MSR_IA32_X2APIC_SELF_IPI:
4772	{
4773	if (u64Value & UINT64_C(0xffffffffffffff00))
4774	return VERR_OUT_OF_RANGE;
4775	break;
4776	}
4777	case MSR_IA32_X2APIC_EOI:
4778	{
4779	if (u64Value != 0)
4780	return VERR_OUT_OF_RANGE;
4781	break;
4782	}
4783	}
4784
4785	/* Write the MSR to the virtual-APIC page. */
4786	uint16_t const offReg = (idMsr & 0xff) << 4;
4787	iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4788
4789	/*
4790	* Record the currently updated APIC offset, as we need this later for figuring
4791	* out whether to perform TPR, EOI or self-IPI virtualization as well as well
4792	* as for supplying the exit qualification when causing an APIC-write VM-exit.
4793	*/
4794	iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4795
4796	return VINF_VMX_MODIFIES_BEHAVIOR;
4797	}
4798
4799	return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4800	}
4801
4802
4803	/**
4804	* Interface for HM and EM to virtualize x2APIC MSR accesses.
4805	*
4806	* @returns Strict VBox status code.
4807	* @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR access was virtualized.
4808	* @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR access must be handled by
4809	* the x2APIC device.
4810	* @retval VERR_OUT_RANGE if the caller must raise \#GP(0).
4811	*
4812	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
4813	* @param idMsr The MSR being read.
4814	* @param pu64Value Pointer to the value being written or where to store the
4815	* value being read.
4816	* @param fWrite Whether this is an MSR write or read access.
4817	* @thread EMT(pVCpu)
4818	*/
4819	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value, bool fWrite)
4820	{
4821	Assert(pu64Value);
4822
4823	VBOXSTRICTRC rcStrict;
4824	if (fWrite)
4825	rcStrict = iemVmxVirtApicAccessMsrWrite(pVCpu, idMsr, *pu64Value);
4826	else
4827	rcStrict = iemVmxVirtApicAccessMsrRead(pVCpu, idMsr, pu64Value);
4828	Assert(!pVCpu->iem.s.cActiveMappings);
4829	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4830
4831	}
4832
4833
4834	/**
4835	* Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4836	*
4837	* @returns VBox status code.
4838	* @retval VINF_SUCCESS when the highest set bit is found.
4839	* @retval VERR_NOT_FOUND when no bit is set.
4840	*
4841	* @param pVCpu The cross context virtual CPU structure.
4842	* @param offReg The offset of the APIC 256-bit sparse register.
4843	* @param pidxHighestBit Where to store the highest bit (most significant bit)
4844	* set in the register. Only valid when VINF_SUCCESS is
4845	* returned.
4846	*
4847	* @remarks The format of the 256-bit sparse register here mirrors that found in
4848	* real APIC hardware.
4849	*/
4850	static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4851	{
4852	Assert(offReg < XAPIC_OFF_END + 4);
4853	Assert(pidxHighestBit);
4854
4855	/*
4856	* There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4857	* However, in each fragment only the first 4 bytes are used.
4858	*/
4859	uint8_t const cFrags = 8;
4860	for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4861	{
4862	uint16_t const offFrag = iFrag * 16;
4863	uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4864	if (!u32Frag)
4865	continue;
4866
4867	unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4868	Assert(idxHighestBit > 0);
4869	--idxHighestBit;
4870	Assert(idxHighestBit <= UINT8_MAX);
4871	*pidxHighestBit = idxHighestBit;
4872	return VINF_SUCCESS;
4873	}
4874	return VERR_NOT_FOUND;
4875	}
4876
4877
4878	/**
4879	* Evaluates pending virtual interrupts.
4880	*
4881	* @param pVCpu The cross context virtual CPU structure.
4882	*/
4883	static void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu) RT_NOEXCEPT
4884	{
4885	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4886
4887	if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4888	{
4889	uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4890	uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4891
4892	if ((uRvi >> 4) > (uPpr >> 4))
4893	{
4894	Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4895	VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4896	}
4897	else
4898	Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4899	}
4900	}
4901
4902
4903	/**
4904	* Performs PPR virtualization.
4905	*
4906	* @returns VBox strict status code.
4907	* @param pVCpu The cross context virtual CPU structure.
4908	*/
4909	static void iemVmxPprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4910	{
4911	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4912	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4913
4914	/*
4915	* PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4916	* or EOI-virtualization.
4917	*
4918	* See Intel spec. 29.1.3 "PPR Virtualization".
4919	*/
4920	uint8_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4921	uint8_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus) & 0xf0;
4922
4923	uint32_t uPpr;
4924	if ((uTpr & 0xf0) >= uSvi)
4925	uPpr = uTpr;
4926	else
4927	uPpr = uSvi;
4928
4929	Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4930	iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4931	}
4932
4933
4934	/**
4935	* Performs VMX TPR virtualization.
4936	*
4937	* @returns VBox strict status code.
4938	* @param pVCpu The cross context virtual CPU structure.
4939	*/
4940	static VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4941	{
4942	Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4943
4944	/*
4945	* We should have already performed the virtual-APIC write to the TPR offset
4946	* in the virtual-APIC page. We now perform TPR virtualization.
4947	*
4948	* See Intel spec. 29.1.2 "TPR Virtualization".
4949	*/
4950	if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4951	{
4952	uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4953	uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4954
4955	/*
4956	* If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4957	* See Intel spec. 29.1.2 "TPR Virtualization".
4958	*/
4959	if (((uTpr >> 4) & 0xf) < uTprThreshold)
4960	{
4961	Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4962	return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4963	}
4964	}
4965	else
4966	{
4967	iemVmxPprVirtualization(pVCpu);
4968	iemVmxEvalPendingVirtIntrs(pVCpu);
4969	}
4970
4971	return VINF_SUCCESS;
4972	}
4973
4974
4975	/**
4976	* Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4977	* not.
4978	*
4979	* @returns @c true if the EOI write is intercepted, @c false otherwise.
4980	* @param pVCpu The cross context virtual CPU structure.
4981	* @param uVector The interrupt that was acknowledged using an EOI.
4982	*/
4983	static bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector) RT_NOEXCEPT
4984	{
4985	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4986	Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4987
4988	if (uVector < 64)
4989	return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4990	if (uVector < 128)
4991	return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4992	if (uVector < 192)
4993	return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4994	return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4995	}
4996
4997
4998	/**
4999	* Performs EOI virtualization.
5000	*
5001	* @returns VBox strict status code.
5002	* @param pVCpu The cross context virtual CPU structure.
5003	*/
5004	static VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
5005	{
5006	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5007	Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
5008
5009	/*
5010	* Clear the interrupt guest-interrupt as no longer in-service (ISR)
5011	* and get the next guest-interrupt that's in-service (if any).
5012	*
5013	* See Intel spec. 29.1.4 "EOI Virtualization".
5014	*/
5015	uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5016	uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5017	Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
5018
5019	uint8_t uVector = uSvi;
5020	iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
5021
5022	uVector = 0;
5023	iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
5024
5025	if (uVector)
5026	Log2(("eoi_virt: next interrupt %#x\n", uVector));
5027	else
5028	Log2(("eoi_virt: no interrupt pending in ISR\n"));
5029
5030	/* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
5031	pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
5032
5033	iemVmxPprVirtualization(pVCpu);
5034	if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
5035	return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
5036	iemVmxEvalPendingVirtIntrs(pVCpu);
5037	return VINF_SUCCESS;
5038	}
5039
5040
5041	/**
5042	* Performs self-IPI virtualization.
5043	*
5044	* @returns VBox strict status code.
5045	* @param pVCpu The cross context virtual CPU structure.
5046	*/
5047	static VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
5048	{
5049	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5050	Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5051
5052	/*
5053	* We should have already performed the virtual-APIC write to the self-IPI offset
5054	* in the virtual-APIC page. We now perform self-IPI virtualization.
5055	*
5056	* See Intel spec. 29.1.5 "Self-IPI Virtualization".
5057	*/
5058	uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5059	Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5060	iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5061	uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5062	uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5063	if (uVector > uRvi)
5064	pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5065	iemVmxEvalPendingVirtIntrs(pVCpu);
5066	return VINF_SUCCESS;
5067	}
5068
5069
5070	/**
5071	* Performs VMX APIC-write emulation.
5072	*
5073	* @returns VBox strict status code.
5074	* @param pVCpu The cross context virtual CPU structure.
5075	*/
5076	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT
5077	{
5078	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5079
5080	/* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5081	IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5082
5083	/*
5084	* Perform APIC-write emulation based on the virtual-APIC register written.
5085	* See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5086	*/
5087	uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5088	VBOXSTRICTRC rcStrict;
5089	switch (offApicWrite)
5090	{
5091	case XAPIC_OFF_TPR:
5092	{
5093	/* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5094	uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5095	uTpr &= UINT32_C(0x000000ff);
5096	iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5097	Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5098	rcStrict = iemVmxTprVirtualization(pVCpu);
5099	break;
5100	}
5101
5102	case XAPIC_OFF_EOI:
5103	{
5104	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5105	{
5106	/* Clear VEOI and perform EOI virtualization. */
5107	iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5108	Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5109	rcStrict = iemVmxEoiVirtualization(pVCpu);
5110	}
5111	else
5112	rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5113	break;
5114	}
5115
5116	case XAPIC_OFF_ICR_LO:
5117	{
5118	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5119	{
5120	/* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5121	uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5122	uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5123	uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5124	if ( !(uIcrLo & fIcrLoMb0)
5125	&& (uIcrLo & fIcrLoMb1))
5126	{
5127	Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5128	rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5129	}
5130	else
5131	rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5132	}
5133	else
5134	rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5135	break;
5136	}
5137
5138	case XAPIC_OFF_ICR_HI:
5139	{
5140	/* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5141	uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5142	uIcrHi &= UINT32_C(0xff000000);
5143	iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5144	rcStrict = VINF_SUCCESS;
5145	break;
5146	}
5147
5148	default:
5149	{
5150	/* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5151	rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5152	break;
5153	}
5154	}
5155
5156	return rcStrict;
5157	}
5158
5159
5160	/**
5161	* Interface for HM and EM to perform an APIC-write emulation which may cause a
5162	* VM-exit.
5163	*
5164	* @returns Strict VBox status code.
5165	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
5166	* @thread EMT(pVCpu)
5167	*/
5168	VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu)
5169	{
5170	VBOXSTRICTRC rcStrict = iemVmxApicWriteEmulation(pVCpu);
5171	Assert(!pVCpu->iem.s.cActiveMappings);
5172	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
5173	}
5174
5175
5176	/**
5177	* Checks guest control registers, debug registers and MSRs as part of VM-entry.
5178	*
5179	* @param pVCpu The cross context virtual CPU structure.
5180	* @param pszInstr The VMX instruction name (for logging purposes).
5181	*/
5182	DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
5183	{
5184	/*
5185	* Guest Control Registers, Debug Registers, and MSRs.
5186	* See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5187	*/
5188	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5189	const char * const pszFailure = "VM-exit";
5190	bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5191
5192	/* CR0 reserved bits. */
5193	{
5194	/* CR0 MB1 bits. */
5195	uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
5196	if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5197	{ /* likely */ }
5198	else
5199	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5200
5201	/* CR0 MBZ bits. */
5202	uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5203	if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5204	{ /* likely */ }
5205	else
5206	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5207
5208	/* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5209	if ( !fUnrestrictedGuest
5210	&& (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5211	&& !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5212	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5213	}
5214
5215	/* CR4 reserved bits. */
5216	{
5217	/* CR4 MB1 bits. */
5218	uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5219	if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5220	{ /* likely */ }
5221	else
5222	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5223
5224	/* CR4 MBZ bits. */
5225	uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5226	if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5227	{ /* likely */ }
5228	else
5229	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5230	}
5231
5232	/* DEBUGCTL MSR. */
5233	if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5234	\|\| !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5235	{ /* likely */ }
5236	else
5237	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5238
5239	/* 64-bit CPU checks. */
5240	bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5241	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5242	{
5243	if (fGstInLongMode)
5244	{
5245	/* PAE must be set. */
5246	if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5247	&& (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5248	{ /* likely */ }
5249	else
5250	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5251	}
5252	else
5253	{
5254	/* PCIDE should not be set. */
5255	if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5256	{ /* likely */ }
5257	else
5258	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5259	}
5260
5261	/* CR3. */
5262	if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5263	{ /* likely */ }
5264	else
5265	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5266
5267	/* DR7. */
5268	if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5269	\|\| !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5270	{ /* likely */ }
5271	else
5272	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5273
5274	/* SYSENTER ESP and SYSENTER EIP. */
5275	if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5276	&& X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5277	{ /* likely */ }
5278	else
5279	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5280	}
5281
5282	/* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5283	Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5284
5285	/* PAT MSR. */
5286	if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5287	\|\| CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5288	{ /* likely */ }
5289	else
5290	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5291
5292	/* EFER MSR. */
5293	if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5294	{
5295	uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5296	if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5297	{ /* likely */ }
5298	else
5299	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5300
5301	bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5302	bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5303	if ( fGstLma == fGstInLongMode
5304	&& ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5305	\|\| fGstLma == fGstLme))
5306	{ /* likely */ }
5307	else
5308	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5309	}
5310
5311	/* We don't support IA32_BNDCFGS MSR yet. */
5312	Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5313
5314	NOREF(pszInstr);
5315	NOREF(pszFailure);
5316	return VINF_SUCCESS;
5317	}
5318
5319
5320	/**
5321	* Checks guest segment registers, LDTR and TR as part of VM-entry.
5322	*
5323	* @param pVCpu The cross context virtual CPU structure.
5324	* @param pszInstr The VMX instruction name (for logging purposes).
5325	*/
5326	DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
5327	{
5328	/*
5329	* Segment registers.
5330	* See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5331	*/
5332	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5333	const char * const pszFailure = "VM-exit";
5334	bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5335	bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5336	bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5337
5338	/* Selectors. */
5339	if ( !fGstInV86Mode
5340	&& !fUnrestrictedGuest
5341	&& (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5342	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5343
5344	for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5345	{
5346	CPUMSELREG SelReg;
5347	int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5348	if (RT_LIKELY(rc == VINF_SUCCESS))
5349	{ /* likely */ }
5350	else
5351	return rc;
5352
5353	/*
5354	* Virtual-8086 mode checks.
5355	*/
5356	if (fGstInV86Mode)
5357	{
5358	/* Base address. */
5359	if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5360	{ /* likely */ }
5361	else
5362	{
5363	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5364	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5365	}
5366
5367	/* Limit. */
5368	if (SelReg.u32Limit == 0xffff)
5369	{ /* likely */ }
5370	else
5371	{
5372	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5373	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5374	}
5375
5376	/* Attribute. */
5377	if (SelReg.Attr.u == 0xf3)
5378	{ /* likely */ }
5379	else
5380	{
5381	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5382	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5383	}
5384
5385	/* We're done; move to checking the next segment. */
5386	continue;
5387	}
5388
5389	/* Checks done by 64-bit CPUs. */
5390	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5391	{
5392	/* Base address. */
5393	if ( iSegReg == X86_SREG_FS
5394	\|\| iSegReg == X86_SREG_GS)
5395	{
5396	if (X86_IS_CANONICAL(SelReg.u64Base))
5397	{ /* likely */ }
5398	else
5399	{
5400	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5401	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5402	}
5403	}
5404	else if (iSegReg == X86_SREG_CS)
5405	{
5406	if (!RT_HI_U32(SelReg.u64Base))
5407	{ /* likely */ }
5408	else
5409	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5410	}
5411	else
5412	{
5413	if ( SelReg.Attr.n.u1Unusable
5414	\|\| !RT_HI_U32(SelReg.u64Base))
5415	{ /* likely */ }
5416	else
5417	{
5418	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5419	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5420	}
5421	}
5422	}
5423
5424	/*
5425	* Checks outside Virtual-8086 mode.
5426	*/
5427	uint8_t const uSegType = SelReg.Attr.n.u4Type;
5428	uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5429	uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5430	uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5431	uint8_t const fPresent = SelReg.Attr.n.u1Present;
5432	uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5433	uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5434	uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5435
5436	/* Code or usable segment. */
5437	if ( iSegReg == X86_SREG_CS
5438	\|\| fUsable)
5439	{
5440	/* Reserved bits (bits 31:17 and bits 11:8). */
5441	if (!(SelReg.Attr.u & 0xfffe0f00))
5442	{ /* likely */ }
5443	else
5444	{
5445	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5446	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5447	}
5448
5449	/* Descriptor type. */
5450	if (fCodeDataSeg)
5451	{ /* likely */ }
5452	else
5453	{
5454	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5455	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5456	}
5457
5458	/* Present. */
5459	if (fPresent)
5460	{ /* likely */ }
5461	else
5462	{
5463	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5464	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5465	}
5466
5467	/* Granularity. */
5468	if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff \|\| !uGranularity)
5469	&& ((SelReg.u32Limit & 0xfff00000) == 0x00000000 \|\| uGranularity))
5470	{ /* likely */ }
5471	else
5472	{
5473	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5474	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5475	}
5476	}
5477
5478	if (iSegReg == X86_SREG_CS)
5479	{
5480	/* Segment Type and DPL. */
5481	if ( uSegType == (X86_SEL_TYPE_RW \| X86_SEL_TYPE_ACCESSED)
5482	&& fUnrestrictedGuest)
5483	{
5484	if (uDpl == 0)
5485	{ /* likely */ }
5486	else
5487	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5488	}
5489	else if ( uSegType == (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
5490	\|\| uSegType == (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_READ \| X86_SEL_TYPE_ACCESSED))
5491	{
5492	X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5493	if (uDpl == AttrSs.n.u2Dpl)
5494	{ /* likely */ }
5495	else
5496	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5497	}
5498	else if ((uSegType & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF \| X86_SEL_TYPE_ACCESSED))
5499	== (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF \| X86_SEL_TYPE_ACCESSED))
5500	{
5501	X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5502	if (uDpl <= AttrSs.n.u2Dpl)
5503	{ /* likely */ }
5504	else
5505	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5506	}
5507	else
5508	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5509
5510	/* Def/Big. */
5511	if ( fGstInLongMode
5512	&& fSegLong)
5513	{
5514	if (uDefBig == 0)
5515	{ /* likely */ }
5516	else
5517	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5518	}
5519	}
5520	else if (iSegReg == X86_SREG_SS)
5521	{
5522	/* Segment Type. */
5523	if ( !fUsable
5524	\|\| uSegType == (X86_SEL_TYPE_RW \| X86_SEL_TYPE_ACCESSED)
5525	\|\| uSegType == (X86_SEL_TYPE_DOWN \| X86_SEL_TYPE_RW \| X86_SEL_TYPE_ACCESSED))
5526	{ /* likely */ }
5527	else
5528	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5529
5530	/* DPL. */
5531	if (!fUnrestrictedGuest)
5532	{
5533	if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5534	{ /* likely */ }
5535	else
5536	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5537	}
5538	X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5539	if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW \| X86_SEL_TYPE_ACCESSED)
5540	\|\| !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5541	{
5542	if (uDpl == 0)
5543	{ /* likely */ }
5544	else
5545	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5546	}
5547	}
5548	else
5549	{
5550	/* DS, ES, FS, GS. */
5551	if (fUsable)
5552	{
5553	/* Segment type. */
5554	if (uSegType & X86_SEL_TYPE_ACCESSED)
5555	{ /* likely */ }
5556	else
5557	{
5558	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5559	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5560	}
5561
5562	if ( !(uSegType & X86_SEL_TYPE_CODE)
5563	\|\| (uSegType & X86_SEL_TYPE_READ))
5564	{ /* likely */ }
5565	else
5566	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5567
5568	/* DPL. */
5569	if ( !fUnrestrictedGuest
5570	&& uSegType <= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_READ \| X86_SEL_TYPE_ACCESSED))
5571	{
5572	if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5573	{ /* likely */ }
5574	else
5575	{
5576	VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5577	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5578	}
5579	}
5580	}
5581	}
5582	}
5583
5584	/*
5585	* LDTR.
5586	*/
5587	{
5588	CPUMSELREG Ldtr;
5589	Ldtr.Sel = pVmcs->GuestLdtr;
5590	Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5591	Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5592	Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5593
5594	if (!Ldtr.Attr.n.u1Unusable)
5595	{
5596	/* Selector. */
5597	if (!(Ldtr.Sel & X86_SEL_LDT))
5598	{ /* likely */ }
5599	else
5600	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5601
5602	/* Base. */
5603	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5604	{
5605	if (X86_IS_CANONICAL(Ldtr.u64Base))
5606	{ /* likely */ }
5607	else
5608	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5609	}
5610
5611	/* Attributes. */
5612	/* Reserved bits (bits 31:17 and bits 11:8). */
5613	if (!(Ldtr.Attr.u & 0xfffe0f00))
5614	{ /* likely */ }
5615	else
5616	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5617
5618	if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5619	{ /* likely */ }
5620	else
5621	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5622
5623	if (!Ldtr.Attr.n.u1DescType)
5624	{ /* likely */ }
5625	else
5626	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5627
5628	if (Ldtr.Attr.n.u1Present)
5629	{ /* likely */ }
5630	else
5631	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5632
5633	if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff \|\| !Ldtr.Attr.n.u1Granularity)
5634	&& ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 \|\| Ldtr.Attr.n.u1Granularity))
5635	{ /* likely */ }
5636	else
5637	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5638	}
5639	}
5640
5641	/*
5642	* TR.
5643	*/
5644	{
5645	CPUMSELREG Tr;
5646	Tr.Sel = pVmcs->GuestTr;
5647	Tr.u32Limit = pVmcs->u32GuestTrLimit;
5648	Tr.u64Base = pVmcs->u64GuestTrBase.u;
5649	Tr.Attr.u = pVmcs->u32GuestTrAttr;
5650
5651	/* Selector. */
5652	if (!(Tr.Sel & X86_SEL_LDT))
5653	{ /* likely */ }
5654	else
5655	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5656
5657	/* Base. */
5658	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5659	{
5660	if (X86_IS_CANONICAL(Tr.u64Base))
5661	{ /* likely */ }
5662	else
5663	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5664	}
5665
5666	/* Attributes. */
5667	/* Reserved bits (bits 31:17 and bits 11:8). */
5668	if (!(Tr.Attr.u & 0xfffe0f00))
5669	{ /* likely */ }
5670	else
5671	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5672
5673	if (!Tr.Attr.n.u1Unusable)
5674	{ /* likely */ }
5675	else
5676	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5677
5678	if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5679	\|\| ( !fGstInLongMode
5680	&& Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5681	{ /* likely */ }
5682	else
5683	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5684
5685	if (!Tr.Attr.n.u1DescType)
5686	{ /* likely */ }
5687	else
5688	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5689
5690	if (Tr.Attr.n.u1Present)
5691	{ /* likely */ }
5692	else
5693	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5694
5695	if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff \|\| !Tr.Attr.n.u1Granularity)
5696	&& ((Tr.u32Limit & 0xfff00000) == 0x00000000 \|\| Tr.Attr.n.u1Granularity))
5697	{ /* likely */ }
5698	else
5699	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5700	}
5701
5702	NOREF(pszInstr);
5703	NOREF(pszFailure);
5704	return VINF_SUCCESS;
5705	}
5706
5707
5708	/**
5709	* Checks guest GDTR and IDTR as part of VM-entry.
5710	*
5711	* @param pVCpu The cross context virtual CPU structure.
5712	* @param pszInstr The VMX instruction name (for logging purposes).
5713	*/
5714	DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5715	{
5716	/*
5717	* GDTR and IDTR.
5718	* See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5719	*/
5720	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5721	const char *const pszFailure = "VM-exit";
5722
5723	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5724	{
5725	/* Base. */
5726	if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5727	{ /* likely */ }
5728	else
5729	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5730
5731	if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5732	{ /* likely */ }
5733	else
5734	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5735	}
5736
5737	/* Limit. */
5738	if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5739	{ /* likely */ }
5740	else
5741	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5742
5743	if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5744	{ /* likely */ }
5745	else
5746	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5747
5748	NOREF(pszInstr);
5749	NOREF(pszFailure);
5750	return VINF_SUCCESS;
5751	}
5752
5753
5754	/**
5755	* Checks guest RIP and RFLAGS as part of VM-entry.
5756	*
5757	* @param pVCpu The cross context virtual CPU structure.
5758	* @param pszInstr The VMX instruction name (for logging purposes).
5759	*/
5760	DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5761	{
5762	/*
5763	* RIP and RFLAGS.
5764	* See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5765	*/
5766	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5767	const char *const pszFailure = "VM-exit";
5768	bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5769
5770	/* RIP. */
5771	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5772	{
5773	X86DESCATTR AttrCs;
5774	AttrCs.u = pVmcs->u32GuestCsAttr;
5775	if ( !fGstInLongMode
5776	\|\| !AttrCs.n.u1Long)
5777	{
5778	if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5779	{ /* likely */ }
5780	else
5781	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5782	}
5783
5784	if ( fGstInLongMode
5785	&& AttrCs.n.u1Long)
5786	{
5787	Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5788	if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5789	&& X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5790	{ /* likely */ }
5791	else
5792	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5793	}
5794	}
5795
5796	/* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5797	uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5798	: pVmcs->u64GuestRFlags.s.Lo;
5799	if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK \| X86_EFL_RA1_MASK))
5800	&& (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5801	{ /* likely */ }
5802	else
5803	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5804
5805	if (!(uGuestRFlags & X86_EFL_VM))
5806	{ /* likely */ }
5807	else
5808	{
5809	if ( fGstInLongMode
5810	\|\| !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5811	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5812	}
5813
5814	if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5815	{
5816	if (uGuestRFlags & X86_EFL_IF)
5817	{ /* likely */ }
5818	else
5819	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5820	}
5821
5822	NOREF(pszInstr);
5823	NOREF(pszFailure);
5824	return VINF_SUCCESS;
5825	}
5826
5827
5828	/**
5829	* Checks guest non-register state as part of VM-entry.
5830	*
5831	* @param pVCpu The cross context virtual CPU structure.
5832	* @param pszInstr The VMX instruction name (for logging purposes).
5833	*/
5834	DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5835	{
5836	/*
5837	* Guest non-register state.
5838	* See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5839	*/
5840	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5841	const char *const pszFailure = "VM-exit";
5842
5843	/*
5844	* Activity state.
5845	*/
5846	uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5847	uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5848	if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5849	{ /* likely */ }
5850	else
5851	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5852
5853	X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5854	if ( !AttrSs.n.u2Dpl
5855	\|\| pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5856	{ /* likely */ }
5857	else
5858	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5859
5860	if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5861	\|\| pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5862	{
5863	if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5864	{ /* likely */ }
5865	else
5866	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5867	}
5868
5869	if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5870	{
5871	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5872	uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5873	AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5874	switch (pVmcs->u32GuestActivityState)
5875	{
5876	case VMX_VMCS_GUEST_ACTIVITY_HLT:
5877	{
5878	if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5879	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5880	\|\| ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5881	&& ( uVector == X86_XCPT_DB
5882	\|\| uVector == X86_XCPT_MC))
5883	\|\| ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5884	&& uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5885	{ /* likely */ }
5886	else
5887	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5888	break;
5889	}
5890
5891	case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5892	{
5893	if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5894	\|\| ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5895	&& uVector == X86_XCPT_MC))
5896	{ /* likely */ }
5897	else
5898	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5899	break;
5900	}
5901
5902	case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5903	default:
5904	break;
5905	}
5906	}
5907
5908	/*
5909	* Interruptibility state.
5910	*/
5911	if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5912	{ /* likely */ }
5913	else
5914	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5915
5916	if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS \| VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5917	!= (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS \| VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5918	{ /* likely */ }
5919	else
5920	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5921
5922	if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5923	\|\| !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5924	{ /* likely */ }
5925	else
5926	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5927
5928	if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5929	{
5930	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5931	if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5932	{
5933	if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS \| VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5934	{ /* likely */ }
5935	else
5936	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5937	}
5938	else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5939	{
5940	if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS \| VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5941	{ /* likely */ }
5942	else
5943	{
5944	/*
5945	* We don't support injecting NMIs when blocking-by-STI would be in effect.
5946	* We update the Exit qualification only when blocking-by-STI is set
5947	* without blocking-by-MovSS being set. Although in practise it does not
5948	* make much difference since the order of checks are implementation defined.
5949	*/
5950	if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5951	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5952	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5953	}
5954
5955	if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5956	\|\| !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5957	{ /* likely */ }
5958	else
5959	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5960	}
5961	}
5962
5963	/* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5964	if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5965	{ /* likely */ }
5966	else
5967	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5968
5969	/* We don't support SGX yet. So enclave-interruption must not be set. */
5970	if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5971	{ /* likely */ }
5972	else
5973	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5974
5975	/*
5976	* Pending debug exceptions.
5977	*/
5978	uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5979	? pVmcs->u64GuestPendingDbgXcpts.u
5980	: pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5981	if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5982	{ /* likely */ }
5983	else
5984	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5985
5986	if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS \| VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5987	\|\| pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5988	{
5989	if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5990	&& !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5991	&& !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5992	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5993
5994	if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5995	\|\| (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5996	&& (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5997	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5998	}
5999
6000	/* We don't support RTM (Real-time Transactional Memory) yet. */
6001	if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
6002	{ /* likely */ }
6003	else
6004	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
6005
6006	/*
6007	* VMCS link pointer.
6008	*/
6009	if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
6010	{
6011	RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
6012	/* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
6013	if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
6014	{ /* likely */ }
6015	else
6016	{
6017	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6018	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
6019	}
6020
6021	/* Validate the address. */
6022	if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
6023	&& !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6024	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
6025	{ /* likely */ }
6026	else
6027	{
6028	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6029	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
6030	}
6031	}
6032
6033	NOREF(pszInstr);
6034	NOREF(pszFailure);
6035	return VINF_SUCCESS;
6036	}
6037
6038
6039	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6040	/**
6041	* Checks guest PDPTEs as part of VM-entry.
6042	*
6043	* @param pVCpu The cross context virtual CPU structure.
6044	* @param pszInstr The VMX instruction name (for logging purposes).
6045	*/
6046	static int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6047	{
6048	/*
6049	* Guest PDPTEs.
6050	* See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6051	*/
6052	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6053	const char * const pszFailure = "VM-exit";
6054
6055	/*
6056	* When EPT is used, we need to validate the PAE PDPTEs provided in the VMCS.
6057	* Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
6058	*/
6059	if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
6060	&& (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
6061	{
6062	/* Get PDPTEs from the VMCS. */
6063	X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6064	aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6065	aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6066	aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6067	aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6068
6069	/* Check validity of the PDPTEs. */
6070	if (PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]))
6071	{ /* likely */ }
6072	else
6073	{
6074	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6075	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6076	}
6077	}
6078
6079	NOREF(pszFailure);
6080	NOREF(pszInstr);
6081	return VINF_SUCCESS;
6082	}
6083	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
6084
6085
6086	/**
6087	* Checks guest-state as part of VM-entry.
6088	*
6089	* @returns VBox status code.
6090	* @param pVCpu The cross context virtual CPU structure.
6091	* @param pszInstr The VMX instruction name (for logging purposes).
6092	*/
6093	static int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6094	{
6095	int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6096	if (RT_SUCCESS(rc))
6097	{
6098	rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6099	if (RT_SUCCESS(rc))
6100	{
6101	rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6102	if (RT_SUCCESS(rc))
6103	{
6104	rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6105	if (RT_SUCCESS(rc))
6106	{
6107	rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6108	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6109	if (RT_SUCCESS(rc))
6110	rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6111	#endif
6112	}
6113	}
6114	}
6115	}
6116	return rc;
6117	}
6118
6119
6120	/**
6121	* Checks host-state as part of VM-entry.
6122	*
6123	* @returns VBox status code.
6124	* @param pVCpu The cross context virtual CPU structure.
6125	* @param pszInstr The VMX instruction name (for logging purposes).
6126	*/
6127	static int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6128	{
6129	/*
6130	* Host Control Registers and MSRs.
6131	* See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6132	*/
6133	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6134	const char * const pszFailure = "VMFail";
6135
6136	/* CR0 reserved bits. */
6137	{
6138	/* CR0 MB1 bits. */
6139	uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
6140	if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6141	{ /* likely */ }
6142	else
6143	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6144
6145	/* CR0 MBZ bits. */
6146	uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6147	if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6148	{ /* likely */ }
6149	else
6150	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6151	}
6152
6153	/* CR4 reserved bits. */
6154	{
6155	/* CR4 MB1 bits. */
6156	uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6157	if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6158	{ /* likely */ }
6159	else
6160	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6161
6162	/* CR4 MBZ bits. */
6163	uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6164	if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6165	{ /* likely */ }
6166	else
6167	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6168	}
6169
6170	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6171	{
6172	/* CR3 reserved bits. */
6173	if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6174	{ /* likely */ }
6175	else
6176	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6177
6178	/* SYSENTER ESP and SYSENTER EIP. */
6179	if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6180	&& X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6181	{ /* likely */ }
6182	else
6183	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6184	}
6185
6186	/* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6187	Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6188
6189	/* PAT MSR. */
6190	if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6191	\|\| CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6192	{ /* likely */ }
6193	else
6194	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6195
6196	/* EFER MSR. */
6197	bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6198	uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6199	if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6200	{
6201	if (!(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6202	{ /* likely */ }
6203	else
6204	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6205
6206	bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6207	bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6208	if ( fHostInLongMode == fHostLma
6209	&& fHostInLongMode == fHostLme)
6210	{ /* likely */ }
6211	else
6212	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6213	}
6214
6215	/*
6216	* Host Segment and Descriptor-Table Registers.
6217	* See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6218	*/
6219	/* Selector RPL and TI. */
6220	if ( !(pVmcs->HostCs & (X86_SEL_RPL \| X86_SEL_LDT))
6221	&& !(pVmcs->HostSs & (X86_SEL_RPL \| X86_SEL_LDT))
6222	&& !(pVmcs->HostDs & (X86_SEL_RPL \| X86_SEL_LDT))
6223	&& !(pVmcs->HostEs & (X86_SEL_RPL \| X86_SEL_LDT))
6224	&& !(pVmcs->HostFs & (X86_SEL_RPL \| X86_SEL_LDT))
6225	&& !(pVmcs->HostGs & (X86_SEL_RPL \| X86_SEL_LDT))
6226	&& !(pVmcs->HostTr & (X86_SEL_RPL \| X86_SEL_LDT)))
6227	{ /* likely */ }
6228	else
6229	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6230
6231	/* CS and TR selectors cannot be 0. */
6232	if ( pVmcs->HostCs
6233	&& pVmcs->HostTr)
6234	{ /* likely */ }
6235	else
6236	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6237
6238	/* SS cannot be 0 if 32-bit host. */
6239	if ( fHostInLongMode
6240	\|\| pVmcs->HostSs)
6241	{ /* likely */ }
6242	else
6243	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6244
6245	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6246	{
6247	/* FS, GS, GDTR, IDTR, TR base address. */
6248	if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6249	&& X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6250	&& X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6251	&& X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6252	&& X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6253	{ /* likely */ }
6254	else
6255	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6256	}
6257
6258	/*
6259	* Host address-space size for 64-bit CPUs.
6260	* See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6261	*/
6262	bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6263	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6264	{
6265	bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6266
6267	/* Logical processor in IA-32e mode. */
6268	if (fCpuInLongMode)
6269	{
6270	if (fHostInLongMode)
6271	{
6272	/* PAE must be set. */
6273	if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6274	{ /* likely */ }
6275	else
6276	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6277
6278	/* RIP must be canonical. */
6279	if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6280	{ /* likely */ }
6281	else
6282	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6283	}
6284	else
6285	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6286	}
6287	else
6288	{
6289	/* Logical processor is outside IA-32e mode. */
6290	if ( !fGstInLongMode
6291	&& !fHostInLongMode)
6292	{
6293	/* PCIDE should not be set. */
6294	if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6295	{ /* likely */ }
6296	else
6297	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6298
6299	/* The high 32-bits of RIP MBZ. */
6300	if (!pVmcs->u64HostRip.s.Hi)
6301	{ /* likely */ }
6302	else
6303	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6304	}
6305	else
6306	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6307	}
6308	}
6309	else
6310	{
6311	/* Host address-space size for 32-bit CPUs. */
6312	if ( !fGstInLongMode
6313	&& !fHostInLongMode)
6314	{ /* likely */ }
6315	else
6316	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6317	}
6318
6319	NOREF(pszInstr);
6320	NOREF(pszFailure);
6321	return VINF_SUCCESS;
6322	}
6323
6324
6325	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6326	/**
6327	* Checks the EPT pointer VMCS field as part of VM-entry.
6328	*
6329	* @returns VBox status code.
6330	* @param pVCpu The cross context virtual CPU structure.
6331	* @param uEptPtr The EPT pointer to check.
6332	* @param penmVmxDiag Where to store the diagnostic reason on failure (not
6333	* updated on success). Optional, can be NULL.
6334	*/
6335	static int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr, VMXVDIAG *penmVmxDiag) RT_NOEXCEPT
6336	{
6337	VMXVDIAG enmVmxDiag;
6338
6339	/* Reserved bits. */
6340	uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
6341	uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
6342	if (uEptPtr & fValidMask)
6343	{
6344	/* Memory Type. */
6345	uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
6346	uint8_t const fMemType = RT_BF_GET(uEptPtr, VMX_BF_EPTP_MEMTYPE);
6347	if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
6348	&& RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
6349	\|\| ( fMemType == VMX_EPTP_MEMTYPE_UC
6350	&& RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
6351	{
6352	/*
6353	* Page walk length (PML4).
6354	* Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
6355	* of 5 but that seems to be removed from the latest specs. leaving only PML4
6356	* as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
6357	*/
6358	Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
6359	if (RT_BF_GET(uEptPtr, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
6360	{
6361	/* Access and dirty bits support in EPT structures. */
6362	if ( !RT_BF_GET(uEptPtr, VMX_BF_EPTP_ACCESS_DIRTY)
6363	\|\| RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
6364	return VINF_SUCCESS;
6365
6366	enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
6367	}
6368	else
6369	enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
6370	}
6371	else
6372	enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
6373	}
6374	else
6375	enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
6376
6377	if (penmVmxDiag)
6378	*penmVmxDiag = enmVmxDiag;
6379	return VERR_VMX_VMENTRY_FAILED;
6380	}
6381	#endif
6382
6383
6384	/**
6385	* Checks VMCS controls fields as part of VM-entry.
6386	*
6387	* @returns VBox status code.
6388	* @param pVCpu The cross context virtual CPU structure.
6389	* @param pszInstr The VMX instruction name (for logging purposes).
6390	*
6391	* @remarks This may update secondary-processor based VM-execution control fields
6392	* in the current VMCS if necessary.
6393	*/
6394	static int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6395	{
6396	PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6397	const char * const pszFailure = "VMFail";
6398	bool const fVmxTrueMsrs = RT_BOOL(pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
6399
6400	/*
6401	* VM-execution controls.
6402	* See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6403	*/
6404	{
6405	/* Pin-based VM-execution controls. */
6406	{
6407	VMXCTLSMSR const PinCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TruePinCtls
6408	: pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6409	if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6410	{ /* likely */ }
6411	else
6412	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6413
6414	if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6415	{ /* likely */ }
6416	else
6417	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6418	}
6419
6420	/* Processor-based VM-execution controls. */
6421	{
6422	VMXCTLSMSR const ProcCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueProcCtls
6423	: pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6424	if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6425	{ /* likely */ }
6426	else
6427	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6428
6429	if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6430	{ /* likely */ }
6431	else
6432	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6433	}
6434
6435	/* Secondary processor-based VM-execution controls. */
6436	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6437	{
6438	VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6439	if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6440	{ /* likely */ }
6441	else
6442	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6443
6444	if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6445	{ /* likely */ }
6446	else
6447	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6448	}
6449	else if (pVmcs->u32ProcCtls2)
6450	{
6451	/*
6452	* If the "activate secondary controls" is clear, then the secondary processor-based VM-execution controls
6453	* is treated as 0.
6454	*
6455	* See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6456	*
6457	* Since this is a rather rare occurrence (only observed for a few VM-entries with Microsoft Hyper-V
6458	* enabled Windows Server 2008 R2 guest), it's not worth changing every place that reads this control to
6459	* also check the "activate secondary controls" bit. Instead, we temporarily save the guest programmed
6460	* control here, zero out the value the rest of our code uses and restore the guest programmed value
6461	* on VM-exit.
6462	*/
6463	pVmcs->u32RestoreProcCtls2 = pVmcs->u32ProcCtls2;
6464	pVmcs->u32ProcCtls2 = 0;
6465	}
6466
6467	/* CR3-target count. */
6468	if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6469	{ /* likely */ }
6470	else
6471	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6472
6473	/* I/O bitmaps physical addresses. */
6474	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6475	{
6476	RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6477	if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6478	&& !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6479	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6480	{ /* likely */ }
6481	else
6482	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6483
6484	RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6485	if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6486	&& !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6487	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6488	{ /* likely */ }
6489	else
6490	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6491	}
6492
6493	/* MSR bitmap physical address. */
6494	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6495	{
6496	RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6497	if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6498	&& !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6499	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6500	{ /* likely */ }
6501	else
6502	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6503	}
6504
6505	/* TPR shadow related controls. */
6506	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6507	{
6508	/* Virtual-APIC page physical address. */
6509	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6510	if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6511	&& !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6512	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6513	{ /* likely */ }
6514	else
6515	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6516
6517	/* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6518	if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6519	\|\| (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6520	{ /* likely */ }
6521	else
6522	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6523
6524	/* The rest done XXX document */
6525	}
6526	else
6527	{
6528	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6529	&& !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6530	&& !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6531	{ /* likely */ }
6532	else
6533	{
6534	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6535	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6536	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6537	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6538	Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6539	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6540	}
6541	}
6542
6543	/* NMI exiting and virtual-NMIs. */
6544	if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6545	\|\| !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6546	{ /* likely */ }
6547	else
6548	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6549
6550	/* Virtual-NMIs and NMI-window exiting. */
6551	if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6552	\|\| !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6553	{ /* likely */ }
6554	else
6555	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6556
6557	/* Virtualize APIC accesses. */
6558	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6559	{
6560	/* APIC-access physical address. */
6561	RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6562	if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6563	&& !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6564	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6565	{ /* likely */ }
6566	else
6567	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6568
6569	/*
6570	* Disallow APIC-access page and virtual-APIC page from being the same address.
6571	* Note! This is not an Intel requirement, but one imposed by our implementation.
6572	* This is done primarily to simplify recursion scenarios while redirecting accesses
6573	* between the APIC-access page and the virtual-APIC page. If any nested hypervisor
6574	* requires this, we can implement it later
6575	*/
6576	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6577	{
6578	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6579	if (GCPhysVirtApic != GCPhysApicAccess)
6580	{ /* likely */ }
6581	else
6582	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6583	}
6584	}
6585
6586	/* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6587	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6588	\|\| !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6589	{ /* likely */ }
6590	else
6591	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6592
6593	/* Virtual-interrupt delivery requires external interrupt exiting. */
6594	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6595	\|\| (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6596	{ /* likely */ }
6597	else
6598	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6599
6600	/* VPID. */
6601	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6602	\|\| pVmcs->u16Vpid != 0)
6603	{ /* likely */ }
6604	else
6605	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6606
6607	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6608	/* Extended-Page-Table Pointer (EPTP). */
6609	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6610	{
6611	VMXVDIAG enmVmxDiag;
6612	int const rc = iemVmxVmentryCheckEptPtr(pVCpu, pVmcs->u64EptPtr.u, &enmVmxDiag);
6613	if (RT_SUCCESS(rc))
6614	{ /* likely */ }
6615	else
6616	IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, enmVmxDiag, rc);
6617	}
6618	#else
6619	Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6620	Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST));
6621	#endif
6622	Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6623	Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6624	Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6625	Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6626	Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6627
6628	/* VMCS shadowing. */
6629	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6630	{
6631	/* VMREAD-bitmap physical address. */
6632	RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6633	if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6634	&& !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6635	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6636	{ /* likely */ }
6637	else
6638	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6639
6640	/* VMWRITE-bitmap physical address. */
6641	RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6642	if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6643	&& !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6644	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6645	{ /* likely */ }
6646	else
6647	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6648	}
6649	}
6650
6651	/*
6652	* VM-exit controls.
6653	* See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6654	*/
6655	{
6656	VMXCTLSMSR const ExitCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueExitCtls
6657	: pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6658	if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6659	{ /* likely */ }
6660	else
6661	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6662
6663	if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6664	{ /* likely */ }
6665	else
6666	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6667
6668	/* Save preemption timer without activating it. */
6669	if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6670	\|\| !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6671	{ /* likely */ }
6672	else
6673	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6674
6675	/* VM-exit MSR-store count and VM-exit MSR-store area address. */
6676	if (pVmcs->u32ExitMsrStoreCount)
6677	{
6678	if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6679	&& !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6680	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6681	{ /* likely */ }
6682	else
6683	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6684	}
6685
6686	/* VM-exit MSR-load count and VM-exit MSR-load area address. */
6687	if (pVmcs->u32ExitMsrLoadCount)
6688	{
6689	if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6690	&& !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6691	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6692	{ /* likely */ }
6693	else
6694	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6695	}
6696	}
6697
6698	/*
6699	* VM-entry controls.
6700	* See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6701	*/
6702	{
6703	VMXCTLSMSR const EntryCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueEntryCtls
6704	: pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6705	if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6706	{ /* likely */ }
6707	else
6708	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6709
6710	if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6711	{ /* likely */ }
6712	else
6713	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6714
6715	/* Event injection. */
6716	uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6717	if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6718	{
6719	/* Type and vector. */
6720	uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6721	uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6722	uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6723	if ( !uRsvd
6724	&& VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6725	&& VMXIsEntryIntInfoVectorValid(uVector, uType))
6726	{ /* likely */ }
6727	else
6728	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6729
6730	/* Exception error code. */
6731	if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6732	{
6733	/* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6734	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6735	\|\| (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6736	{ /* likely */ }
6737	else
6738	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6739
6740	/* Exceptions that provide an error code. */
6741	if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6742	&& ( uVector == X86_XCPT_DF
6743	\|\| uVector == X86_XCPT_TS
6744	\|\| uVector == X86_XCPT_NP
6745	\|\| uVector == X86_XCPT_SS
6746	\|\| uVector == X86_XCPT_GP
6747	\|\| uVector == X86_XCPT_PF
6748	\|\| uVector == X86_XCPT_AC))
6749	{ /* likely */ }
6750	else
6751	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6752
6753	/* Exception error-code reserved bits. */
6754	if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6755	{ /* likely */ }
6756	else
6757	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6758
6759	/* Injecting a software interrupt, software exception or privileged software exception. */
6760	if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6761	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6762	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6763	{
6764	/* Instruction length must be in the range 0-15. */
6765	if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6766	{ /* likely */ }
6767	else
6768	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6769
6770	/* However, instruction length of 0 is allowed only when its CPU feature is present. */
6771	if ( pVmcs->u32EntryInstrLen != 0
6772	\|\| IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6773	{ /* likely */ }
6774	else
6775	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6776	}
6777	}
6778	}
6779
6780	/* VM-entry MSR-load count and VM-entry MSR-load area address. */
6781	if (pVmcs->u32EntryMsrLoadCount)
6782	{
6783	if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6784	&& !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6785	&& PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6786	{ /* likely */ }
6787	else
6788	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6789	}
6790
6791	Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6792	Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6793	}
6794
6795	NOREF(pszInstr);
6796	NOREF(pszFailure);
6797	return VINF_SUCCESS;
6798	}
6799
6800
6801	/**
6802	* Loads the guest control registers, debug register and some MSRs as part of
6803	* VM-entry.
6804	*
6805	* @param pVCpu The cross context virtual CPU structure.
6806	*/
6807	static void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
6808	{
6809	/*
6810	* Load guest control registers, debug registers and MSRs.
6811	* See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6812	*/
6813	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6814
6815	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6816	uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6817	\| (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6818	pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6819	pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6820	pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6821
6822	if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6823	pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) \| VMX_ENTRY_GUEST_DR7_MB1_MASK;
6824
6825	pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6826	pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6827	pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6828
6829	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6830	{
6831	/* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6832
6833	/* EFER MSR. */
6834	if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6835	{
6836	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6837	uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6838	bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6839	bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6840	if (fGstInLongMode)
6841	{
6842	/* If the nested-guest is in long mode, LMA and LME are both set. */
6843	Assert(fGstPaging);
6844	pVCpu->cpum.GstCtx.msrEFER = uHostEfer \| (MSR_K6_EFER_LMA \| MSR_K6_EFER_LME);
6845	}
6846	else
6847	{
6848	/*
6849	* If the nested-guest is outside long mode:
6850	* - With paging: LMA is cleared, LME is cleared.
6851	* - Without paging: LMA is cleared, LME is left unmodified.
6852	*/
6853	uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA \| (fGstPaging ? MSR_K6_EFER_LME : 0);
6854	pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6855	}
6856	}
6857	/* else: see below. */
6858	}
6859
6860	/* PAT MSR. */
6861	if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6862	pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6863
6864	/* EFER MSR. */
6865	if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6866	pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6867
6868	/* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6869	Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6870
6871	/* We don't support IA32_BNDCFGS MSR yet. */
6872	Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6873
6874	/* Nothing to do for SMBASE register - We don't support SMM yet. */
6875	}
6876
6877
6878	/**
6879	* Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6880	*
6881	* @param pVCpu The cross context virtual CPU structure.
6882	*/
6883	static void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
6884	{
6885	/*
6886	* Load guest segment registers, GDTR, IDTR, LDTR and TR.
6887	* See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6888	*/
6889	/* CS, SS, ES, DS, FS, GS. */
6890	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6891	for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6892	{
6893	PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6894	CPUMSELREG VmcsSelReg;
6895	int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6896	AssertRC(rc); NOREF(rc);
6897	if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6898	{
6899	pGstSelReg->Sel = VmcsSelReg.Sel;
6900	pGstSelReg->ValidSel = VmcsSelReg.Sel;
6901	pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6902	pGstSelReg->u64Base = VmcsSelReg.u64Base;
6903	pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6904	pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6905	}
6906	else
6907	{
6908	pGstSelReg->Sel = VmcsSelReg.Sel;
6909	pGstSelReg->ValidSel = VmcsSelReg.Sel;
6910	pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6911	switch (iSegReg)
6912	{
6913	case X86_SREG_CS:
6914	pGstSelReg->u64Base = VmcsSelReg.u64Base;
6915	pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6916	pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6917	break;
6918
6919	case X86_SREG_SS:
6920	pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6921	pGstSelReg->u32Limit = 0;
6922	pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) \| X86DESCATTR_D \| X86DESCATTR_UNUSABLE;
6923	break;
6924
6925	case X86_SREG_ES:
6926	case X86_SREG_DS:
6927	pGstSelReg->u64Base = 0;
6928	pGstSelReg->u32Limit = 0;
6929	pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6930	break;
6931
6932	case X86_SREG_FS:
6933	case X86_SREG_GS:
6934	pGstSelReg->u64Base = VmcsSelReg.u64Base;
6935	pGstSelReg->u32Limit = 0;
6936	pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6937	break;
6938	}
6939	Assert(pGstSelReg->Attr.n.u1Unusable);
6940	}
6941	}
6942
6943	/* LDTR. */
6944	pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6945	pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6946	pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6947	if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6948	{
6949	pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6950	pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6951	pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6952	}
6953	else
6954	{
6955	pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6956	pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6957	pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6958	}
6959
6960	/* TR. */
6961	Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6962	pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6963	pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6964	pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6965	pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6966	pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6967	pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6968
6969	/* GDTR. */
6970	pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6971	pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6972
6973	/* IDTR. */
6974	pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6975	pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6976	}
6977
6978
6979	/**
6980	* Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6981	*
6982	* @returns VBox status code.
6983	* @param pVCpu The cross context virtual CPU structure.
6984	* @param pszInstr The VMX instruction name (for logging purposes).
6985	*/
6986	static int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6987	{
6988	/*
6989	* Load guest MSRs.
6990	* See Intel spec. 26.4 "Loading MSRs".
6991	*/
6992	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6993	const char *const pszFailure = "VM-exit";
6994
6995	/*
6996	* The VM-entry MSR-load area address need not be a valid guest-physical address if the
6997	* VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6998	* See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6999	*/
7000	uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
7001	if (!cMsrs)
7002	return VINF_SUCCESS;
7003
7004	/*
7005	* Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
7006	* exceeded including possibly raising #MC exceptions during VMX transition. Our
7007	* implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
7008	*/
7009	bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
7010	if (fIsMsrCountValid)
7011	{ /* likely */ }
7012	else
7013	{
7014	iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
7015	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
7016	}
7017
7018	RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
7019	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
7020	GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
7021	if (RT_SUCCESS(rc))
7022	{
7023	PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
7024	for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7025	{
7026	if ( !pMsr->u32Reserved
7027	&& pMsr->u32Msr != MSR_K8_FS_BASE
7028	&& pMsr->u32Msr != MSR_K8_GS_BASE
7029	&& pMsr->u32Msr != MSR_K6_EFER
7030	&& pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7031	&& pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7032	{
7033	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7034	if (rcStrict == VINF_SUCCESS)
7035	continue;
7036
7037	/*
7038	* If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7039	* If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7040	* recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
7041	* further by our own, specific diagnostic code. Later, we can try implement handling of the
7042	* MSR in ring-0 if possible, or come up with a better, generic solution.
7043	*/
7044	iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7045	VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7046	? kVmxVDiag_Vmentry_MsrLoadRing3
7047	: kVmxVDiag_Vmentry_MsrLoad;
7048	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7049	}
7050	else
7051	{
7052	iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7053	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7054	}
7055	}
7056	}
7057	else
7058	{
7059	AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7060	IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys, rc);
7061	}
7062
7063	NOREF(pszInstr);
7064	NOREF(pszFailure);
7065	return VINF_SUCCESS;
7066	}
7067
7068
7069	/**
7070	* Loads the guest-state non-register state as part of VM-entry.
7071	*
7072	* @returns VBox status code.
7073	* @param pVCpu The cross context virtual CPU structure.
7074	* @param pszInstr The VMX instruction name (for logging purposes).
7075	*
7076	* @remarks This must be called only after loading the nested-guest register state
7077	* (especially nested-guest RIP).
7078	*/
7079	static int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7080	{
7081	/*
7082	* Load guest non-register state.
7083	* See Intel spec. 26.6 "Special Features of VM Entry"
7084	*/
7085	const char *const pszFailure = "VM-exit";
7086	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7087
7088	/*
7089	* If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7090	* If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7091	*
7092	* See Intel spec. 26.6.1 "Interruptibility State".
7093	*/
7094	bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7095	if ( !fEntryVectoring
7096	&& (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI \| VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7097	CPUMSetInInterruptShadowEx(&pVCpu->cpum.GstCtx, pVmcs->u64GuestRip.u);
7098	else
7099	Assert(!CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx));
7100
7101	/* NMI blocking. */
7102	if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7103	{
7104	if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7105	{
7106	pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7107	Assert(!CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx));
7108	}
7109	else
7110	{
7111	pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7112	CPUMSetInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx);
7113	}
7114	}
7115	else
7116	{
7117	pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7118	Assert(!CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx));
7119	}
7120
7121	/* SMI blocking is irrelevant. We don't support SMIs yet. */
7122
7123	/*
7124	* Set PGM's copy of the EPT pointer.
7125	* The EPTP has already been validated while checking guest state.
7126	*
7127	* It is important to do this prior to mapping PAE PDPTEs (below).
7128	*/
7129	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7130	PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
7131
7132	/*
7133	* Load the guest's PAE PDPTEs.
7134	*/
7135	if (!iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
7136	{
7137	/*
7138	* When PAE paging is not used we clear the PAE PDPTEs for safety
7139	* in case we might be switching from a PAE host to a non-PAE guest.
7140	*/
7141	pVCpu->cpum.GstCtx.aPaePdpes[0].u = 0;
7142	pVCpu->cpum.GstCtx.aPaePdpes[1].u = 0;
7143	pVCpu->cpum.GstCtx.aPaePdpes[2].u = 0;
7144	pVCpu->cpum.GstCtx.aPaePdpes[3].u = 0;
7145	}
7146	else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7147	{
7148	/*
7149	* With EPT and the nested-guest using PAE paging, we've already validated the PAE PDPTEs
7150	* while checking the guest state. We can load them into the nested-guest CPU state now.
7151	* They'll later be used while mapping CR3 and the PAE PDPTEs.
7152	*/
7153	pVCpu->cpum.GstCtx.aPaePdpes[0].u = pVmcs->u64GuestPdpte0.u;
7154	pVCpu->cpum.GstCtx.aPaePdpes[1].u = pVmcs->u64GuestPdpte1.u;
7155	pVCpu->cpum.GstCtx.aPaePdpes[2].u = pVmcs->u64GuestPdpte2.u;
7156	pVCpu->cpum.GstCtx.aPaePdpes[3].u = pVmcs->u64GuestPdpte3.u;
7157	}
7158	else
7159	{
7160	/*
7161	* Without EPT and the nested-guest using PAE paging, we must load the PAE PDPTEs
7162	* referenced by CR3. This involves loading (and mapping) CR3 and validating them now.
7163	*/
7164	int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
7165	if (RT_SUCCESS(rc))
7166	{ /* likely */ }
7167	else
7168	{
7169	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
7170	IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte, rc);
7171	}
7172	}
7173
7174	/* VPID is irrelevant. We don't support VPID yet. */
7175
7176	/* Clear address-range monitoring. */
7177	EMMonitorWaitClear(pVCpu);
7178
7179	return VINF_SUCCESS;
7180	}
7181
7182
7183	/**
7184	* Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
7185	*
7186	* @param pVCpu The cross context virtual CPU structure.
7187	* @param pszInstr The VMX instruction name (for logging purposes).
7188	*
7189	* @remarks This assumes various VMCS related data structure pointers have already
7190	* been verified prior to calling this function.
7191	*/
7192	static int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7193	{
7194	const char *const pszFailure = "VM-exit";
7195	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7196
7197	/*
7198	* Virtualize APIC accesses.
7199	*/
7200	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7201	{
7202	/* APIC-access physical address. */
7203	RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
7204
7205	/*
7206	* Register the handler for the APIC-access page.
7207	*
7208	* We don't deregister the APIC-access page handler during the VM-exit as a different
7209	* nested-VCPU might be using the same guest-physical address for its APIC-access page.
7210	*
7211	* We leave the page registered until the first access that happens outside VMX non-root
7212	* mode. Guest software is allowed to access structures such as the APIC-access page
7213	* only when no logical processor with a current VMCS references it in VMX non-root mode,
7214	* otherwise it can lead to unpredictable behavior including guest triple-faults.
7215	*
7216	* See Intel spec. 24.11.4 "Software Access to Related Structures".
7217	*/
7218	/** @todo r=bird: The lazy deregistration of the page is potentially slightly
7219	* problematic, as the guest may cause us to create lots of access
7220	* handler entries. However, any slowdown or similar effects should
7221	* only ever affect the guest itself, so not a big issue. Though, I
7222	* wish there was most recently used approach or something to tracking
7223	* these... */
7224	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7225	int rc = PGMHandlerPhysicalRegisterVmxApicAccessPage(pVM, GCPhysApicAccess, pVM->iem.s.hVmxApicAccessPage);
7226	if (RT_SUCCESS(rc))
7227	{ /* likely */ }
7228	else
7229	IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg, rc);
7230	}
7231
7232	/*
7233	* VMCS shadowing.
7234	*/
7235	if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7236	{
7237	/* Read the VMREAD-bitmap. */
7238	RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
7239	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
7240	GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
7241	if (RT_SUCCESS(rc))
7242	{ /* likely */ }
7243	else
7244	IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys, rc);
7245
7246	/* Read the VMWRITE-bitmap. */
7247	RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
7248	rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
7249	GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
7250	if (RT_SUCCESS(rc))
7251	{ /* likely */ }
7252	else
7253	IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys, rc);
7254	}
7255
7256	/*
7257	* I/O bitmaps.
7258	*/
7259	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
7260	{
7261	/* Read the IO bitmap A. */
7262	RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
7263	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
7264	GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
7265	if (RT_SUCCESS(rc))
7266	{ /* likely */ }
7267	else
7268	IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys, rc);
7269
7270	/* Read the IO bitmap B. */
7271	RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
7272	rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
7273	GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
7274	if (RT_SUCCESS(rc))
7275	{ /* likely */ }
7276	else
7277	IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys, rc);
7278	}
7279
7280	/*
7281	* TPR shadow and Virtual-APIC page.
7282	*/
7283	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7284	{
7285	/* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
7286	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7287	&& !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
7288	{
7289	/* Read the VTPR from the virtual-APIC page. */
7290	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
7291	uint8_t u8VTpr;
7292	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
7293	if (RT_SUCCESS(rc))
7294	{ /* likely */ }
7295	else
7296	IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys, rc);
7297
7298	/* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
7299	if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
7300	{ /* likely */ }
7301	else
7302	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
7303	}
7304	}
7305
7306	/*
7307	* VMCS link pointer.
7308	*/
7309	if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
7310	{
7311	/* Read the VMCS-link pointer from guest memory. */
7312	RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
7313	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
7314	GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
7315	if (RT_SUCCESS(rc))
7316	{ /* likely */ }
7317	else
7318	{
7319	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7320	IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys, rc);
7321	}
7322
7323	/* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7324	if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
7325	{ /* likely */ }
7326	else
7327	{
7328	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7329	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
7330	}
7331
7332	/* Verify the shadow bit is set if VMCS shadowing is enabled . */
7333	if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7334	\|\| pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
7335	{ /* likely */ }
7336	else
7337	{
7338	iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7339	IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
7340	}
7341
7342	/* Update our cache of the guest physical address of the shadow VMCS. */
7343	pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
7344	}
7345
7346	/*
7347	* MSR bitmap.
7348	*/
7349	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7350	{
7351	/* Read the MSR bitmap. */
7352	RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
7353	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
7354	GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
7355	if (RT_SUCCESS(rc))
7356	{ /* likely */ }
7357	else
7358	IEM_VMX_VMENTRY_FAILED_RET_2(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys, rc);
7359	}
7360
7361	NOREF(pszFailure);
7362	NOREF(pszInstr);
7363	return VINF_SUCCESS;
7364	}
7365
7366
7367	/**
7368	* Loads the guest-state as part of VM-entry.
7369	*
7370	* @returns VBox status code.
7371	* @param pVCpu The cross context virtual CPU structure.
7372	* @param pszInstr The VMX instruction name (for logging purposes).
7373	*
7374	* @remarks This must be done after all the necessary steps prior to loading of
7375	* guest-state (e.g. checking various VMCS state).
7376	*/
7377	static int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7378	{
7379	/* Load guest control registers, MSRs (that are directly part of the VMCS). */
7380	iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7381
7382	/* Load guest segment registers. */
7383	iemVmxVmentryLoadGuestSegRegs(pVCpu);
7384
7385	/*
7386	* Load guest RIP, RSP and RFLAGS.
7387	* See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7388	*/
7389	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7390	pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7391	pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7392	pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7393
7394	/* Initialize the PAUSE-loop controls as part of VM-entry. */
7395	pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7396	pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7397
7398	/* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
7399	int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
7400	if (rc == VINF_SUCCESS)
7401	{ /* likely */ }
7402	else
7403	return rc;
7404
7405	/* Load VMX related structures and state referenced by the VMCS. */
7406	rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
7407	if (rc == VINF_SUCCESS)
7408	{ /* likely */ }
7409	else
7410	return rc;
7411
7412	NOREF(pszInstr);
7413	return VINF_SUCCESS;
7414	}
7415
7416
7417	/**
7418	* Returns whether there are is a pending debug exception on VM-entry.
7419	*
7420	* @param pVCpu The cross context virtual CPU structure.
7421	* @param pszInstr The VMX instruction name (for logging purposes).
7422	*/
7423	static bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7424	{
7425	/*
7426	* Pending debug exceptions.
7427	* See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7428	*/
7429	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7430	Assert(pVmcs);
7431
7432	bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7433	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7434	if (fPendingDbgXcpt)
7435	{
7436	uint8_t uEntryIntInfoType;
7437	bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7438	if (fEntryVectoring)
7439	{
7440	switch (uEntryIntInfoType)
7441	{
7442	case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7443	case VMX_ENTRY_INT_INFO_TYPE_NMI:
7444	case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7445	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7446	fPendingDbgXcpt = false;
7447	break;
7448
7449	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7450	{
7451	/*
7452	* Whether the pending debug exception for software exceptions other than
7453	* #BP and #OF is delivered after injecting the exception or is discard
7454	* is CPU implementation specific. We will discard them (easier).
7455	*/
7456	uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7457	if ( uVector != X86_XCPT_BP
7458	&& uVector != X86_XCPT_OF)
7459	fPendingDbgXcpt = false;
7460	RT_FALL_THRU();
7461	}
7462	case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7463	{
7464	if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7465	fPendingDbgXcpt = false;
7466	break;
7467	}
7468	}
7469	}
7470	else
7471	{
7472	/*
7473	* When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7474	* pending debug exception is held pending or is discarded is CPU implementation
7475	* specific. We will discard them (easier).
7476	*/
7477	if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7478	fPendingDbgXcpt = false;
7479
7480	/* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7481	if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN \| VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7482	fPendingDbgXcpt = false;
7483	}
7484	}
7485
7486	NOREF(pszInstr);
7487	return fPendingDbgXcpt;
7488	}
7489
7490
7491	/**
7492	* Set up the monitor-trap flag (MTF).
7493	*
7494	* @param pVCpu The cross context virtual CPU structure.
7495	* @param pszInstr The VMX instruction name (for logging purposes).
7496	*/
7497	static void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7498	{
7499	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7500	Assert(pVmcs);
7501	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7502	{
7503	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7504	Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7505	}
7506	else
7507	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7508	NOREF(pszInstr);
7509	}
7510
7511
7512	/**
7513	* Sets up NMI-window exiting.
7514	*
7515	* @param pVCpu The cross context virtual CPU structure.
7516	* @param pszInstr The VMX instruction name (for logging purposes).
7517	*/
7518	static void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7519	{
7520	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7521	Assert(pVmcs);
7522	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7523	{
7524	Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7525	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7526	Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7527	}
7528	else
7529	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7530	NOREF(pszInstr);
7531	}
7532
7533
7534	/**
7535	* Sets up interrupt-window exiting.
7536	*
7537	* @param pVCpu The cross context virtual CPU structure.
7538	* @param pszInstr The VMX instruction name (for logging purposes).
7539	*/
7540	static void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7541	{
7542	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7543	Assert(pVmcs);
7544	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7545	{
7546	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7547	Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7548	}
7549	else
7550	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7551	NOREF(pszInstr);
7552	}
7553
7554
7555	/**
7556	* Set up the VMX-preemption timer.
7557	*
7558	* @param pVCpu The cross context virtual CPU structure.
7559	* @param pszInstr The VMX instruction name (for logging purposes).
7560	*/
7561	static void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7562	{
7563	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7564	Assert(pVmcs);
7565	if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7566	{
7567	/*
7568	* If the timer is 0, we must cause a VM-exit before executing the first
7569	* nested-guest instruction. So we can flag as though the timer has already
7570	* expired and we will check and cause a VM-exit at the right priority elsewhere
7571	* in the code.
7572	*/
7573	uint64_t uEntryTick;
7574	uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7575	if (uPreemptTimer)
7576	{
7577	int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7578	AssertRC(rc);
7579	Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7580	}
7581	else
7582	{
7583	uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7584	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7585	Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7586	}
7587
7588	pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7589	}
7590	else
7591	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7592
7593	NOREF(pszInstr);
7594	}
7595
7596
7597	/**
7598	* Injects an event using TRPM given a VM-entry interruption info and related
7599	* fields.
7600	*
7601	* @param pVCpu The cross context virtual CPU structure.
7602	* @param pszInstr The VMX instruction name (for logging purposes).
7603	* @param uEntryIntInfo The VM-entry interruption info.
7604	* @param uErrCode The error code associated with the event if any.
7605	* @param cbInstr The VM-entry instruction length (for software
7606	* interrupts and software exceptions). Pass 0
7607	* otherwise.
7608	* @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7609	*/
7610	static void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7611	uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress) RT_NOEXCEPT
7612	{
7613	Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7614
7615	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7616	uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7617	TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7618
7619	Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7620
7621	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7622	AssertRC(rc);
7623	Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7624
7625	if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7626	{
7627	TRPMSetErrorCode(pVCpu, uErrCode);
7628	Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7629	}
7630
7631	if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7632	{
7633	TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7634	Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7635	}
7636	else
7637	{
7638	switch (uType)
7639	{
7640	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7641	TRPMSetTrapDueToIcebp(pVCpu);
7642	Log(("%s: Injecting: icebp\n", pszInstr));
7643	RT_FALL_THRU();
7644	case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7645	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7646	TRPMSetInstrLength(pVCpu, cbInstr);
7647	Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7648	break;
7649	}
7650	}
7651
7652	NOREF(pszInstr);
7653	}
7654
7655
7656	/**
7657	* Performs event injection (if any) as part of VM-entry.
7658	*
7659	* @param pVCpu The cross context virtual CPU structure.
7660	* @param pszInstr The VMX instruction name (for logging purposes).
7661	*/
7662	static void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7663	{
7664	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7665
7666	/*
7667	* Inject events.
7668	* The event that is going to be made pending for injection is not subject to VMX intercepts,
7669	* thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7670	* of the current event -are- subject to intercepts, hence this flag will be flipped during
7671	* the actually delivery of this event.
7672	*
7673	* See Intel spec. 26.5 "Event Injection".
7674	*/
7675	uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7676	bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7677
7678	CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7679	if (fEntryIntInfoValid)
7680	{
7681	if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7682	iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7683	pVCpu->cpum.GstCtx.cr2);
7684	else
7685	{
7686	Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7687	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7688	}
7689
7690	/*
7691	* We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7692	*
7693	* However, we do it here on VM-entry as well because while it isn't visible to guest
7694	* software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7695	* execution using hardware-assisted VMX, it will not try to inject the event again.
7696	*
7697	* See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7698	*/
7699	pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7700	}
7701	else
7702	{
7703	/*
7704	* Inject any pending guest debug exception.
7705	* Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7706	* See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7707	*/
7708	bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7709	if (fPendingDbgXcpt)
7710	{
7711	uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7712	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7713	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7714	iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7715	0 /* GCPtrFaultAddress */);
7716	}
7717	}
7718
7719	NOREF(pszInstr);
7720	}
7721
7722
7723	/**
7724	* Initializes all read-only VMCS fields as part of VM-entry.
7725	*
7726	* @param pVCpu The cross context virtual CPU structure.
7727	*/
7728	static void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu) RT_NOEXCEPT
7729	{
7730	/*
7731	* Any VMCS field which we do not establish on every VM-exit but may potentially
7732	* be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7733	* specified to be undefined, needs to be initialized here.
7734	*
7735	* Thus, it is especially important to clear the Exit qualification field
7736	* since it must be zero for VM-exits where it is not used. Similarly, the
7737	* VM-exit interruption information field's valid bit needs to be cleared for
7738	* the same reasons.
7739	*/
7740	PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7741	Assert(pVmcs);
7742
7743	/* 16-bit (none currently). */
7744	/* 32-bit. */
7745	pVmcs->u32RoVmInstrError = 0;
7746	pVmcs->u32RoExitReason = 0;
7747	pVmcs->u32RoExitIntInfo = 0;
7748	pVmcs->u32RoExitIntErrCode = 0;
7749	pVmcs->u32RoIdtVectoringInfo = 0;
7750	pVmcs->u32RoIdtVectoringErrCode = 0;
7751	pVmcs->u32RoExitInstrLen = 0;
7752	pVmcs->u32RoExitInstrInfo = 0;
7753
7754	/* 64-bit. */
7755	pVmcs->u64RoGuestPhysAddr.u = 0;
7756
7757	/* Natural-width. */
7758	pVmcs->u64RoExitQual.u = 0;
7759	pVmcs->u64RoIoRcx.u = 0;
7760	pVmcs->u64RoIoRsi.u = 0;
7761	pVmcs->u64RoIoRdi.u = 0;
7762	pVmcs->u64RoIoRip.u = 0;
7763	pVmcs->u64RoGuestLinearAddr.u = 0;
7764	}
7765
7766
7767	/**
7768	* VMLAUNCH/VMRESUME instruction execution worker.
7769	*
7770	* @returns Strict VBox status code.
7771	* @param pVCpu The cross context virtual CPU structure.
7772	* @param cbInstr The instruction length in bytes.
7773	* @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7774	* VMXINSTRID_VMRESUME).
7775	*
7776	* @remarks Common VMX instruction checks are already expected to by the caller,
7777	* i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7778	*/
7779	static VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId) RT_NOEXCEPT
7780	{
7781	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7782	RT_NOREF3(pVCpu, cbInstr, uInstrId);
7783	return VINF_EM_RAW_EMULATE_INSTR;
7784	# else
7785	Assert( uInstrId == VMXINSTRID_VMLAUNCH
7786	\|\| uInstrId == VMXINSTRID_VMRESUME);
7787	const char * const pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7788
7789	/* Nested-guest intercept. */
7790	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7791	return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7792
7793	Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7794
7795	/*
7796	* Basic VM-entry checks.
7797	* The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7798	* The checks following that do not have to follow a specific order.
7799	*
7800	* See Intel spec. 26.1 "Basic VM-entry Checks".
7801	*/
7802
7803	/* CPL. */
7804	if (IEM_GET_CPL(pVCpu) == 0)
7805	{ /* likely */ }
7806	else
7807	{
7808	Log(("%s: CPL %u -> #GP(0)\n", pszInstr, IEM_GET_CPL(pVCpu)));
7809	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7810	return iemRaiseGeneralProtectionFault0(pVCpu);
7811	}
7812
7813	/* Current VMCS valid. */
7814	if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7815	{ /* likely */ }
7816	else
7817	{
7818	Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7819	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7820	iemVmxVmFailInvalid(pVCpu);
7821	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7822	}
7823
7824	/* Current VMCS is not a shadow VMCS. */
7825	PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7826	if (!pVmcs->u32VmcsRevId.n.fIsShadowVmcs)
7827	{ /* likely */ }
7828	else
7829	{
7830	Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7831	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7832	iemVmxVmFailInvalid(pVCpu);
7833	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7834	}
7835
7836	/** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7837	* use block-by-STI here which is not quite correct. */
7838	if (!CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx))
7839	{ /* likely */ }
7840	else
7841	{
7842	Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7843	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7844	iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7845	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7846	}
7847
7848	if (uInstrId == VMXINSTRID_VMLAUNCH)
7849	{
7850	/* VMLAUNCH with non-clear VMCS. */
7851	if (pVmcs->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7852	{ /* likely */ }
7853	else if (pVmcs->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR_LEGACY)
7854	{
7855	/* Convert legacy launch-state value to current value, see @bugref{10318#c114} for reasons.*/
7856	pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
7857	Log(("vmlaunch: Updated legacy 'VMCLEAR' VMCS launch-state bit to current\n"));
7858	}
7859	else
7860	{
7861	Log(("vmlaunch: VMLAUNCH with non-clear VMCS %RGp -> VMFail\n", pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs));
7862	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7863	iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7864	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7865	}
7866	}
7867	else
7868	{
7869	/* VMRESUME with non-launched VMCS. */
7870	if (pVmcs->fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7871	{ /* likely */ }
7872	else
7873	{
7874	Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7875	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7876	iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7877	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7878	}
7879	}
7880
7881	/*
7882	* We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7883	* while entering VMX non-root mode. We do some of this while checking VM-execution
7884	* controls. The nested hypervisor should not make assumptions and cannot expect
7885	* predictable behavior if changes to these structures are made in guest memory while
7886	* executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7887	* modify them anyway as we cache them in host memory.
7888	*
7889	* See Intel spec. 24.11.4 "Software Access to Related Structures".
7890	*/
7891	Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7892
7893	int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7894	if (RT_SUCCESS(rc))
7895	{
7896	rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7897	if (RT_SUCCESS(rc))
7898	{
7899	/*
7900	* Initialize read-only VMCS fields before VM-entry since we don't update all of them
7901	* for every VM-exit. This needs to be done before invoking a VM-exit (even those
7902	* ones that may occur during VM-entry below).
7903	*/
7904	iemVmxVmentryInitReadOnlyFields(pVCpu);
7905
7906	/*
7907	* Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7908	* So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7909	* VM-exit when required.
7910	* See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7911	*/
7912	iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7913
7914	rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7915	if (RT_SUCCESS(rc))
7916	{
7917	/*
7918	* We've now entered nested-guest execution.
7919	*
7920	* It is important do this prior to loading the guest state because
7921	* as part of loading the guest state, PGM (and perhaps other components
7922	* in the future) relies on detecting whether VMX non-root mode has been
7923	* entered.
7924	*/
7925	pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7926
7927	rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7928	if (RT_SUCCESS(rc))
7929	{
7930	rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7931	if (RT_SUCCESS(rc))
7932	{
7933	Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7934
7935	/* VMLAUNCH instruction must update the VMCS launch state. */
7936	if (uInstrId == VMXINSTRID_VMLAUNCH)
7937	pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7938
7939	/* Perform the VMX transition (PGM updates). */
7940	VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu, cbInstr);
7941	if (rcStrict == VINF_SUCCESS)
7942	{ /* likely */ }
7943	else if (RT_SUCCESS(rcStrict))
7944	{
7945	Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7946	VBOXSTRICTRC_VAL(rcStrict)));
7947	rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7948	}
7949	else
7950	{
7951	Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7952	return rcStrict;
7953	}
7954
7955	/* Paranoia. */
7956	Assert(rcStrict == VINF_SUCCESS);
7957
7958	/*
7959	* The priority of potential VM-exits during VM-entry is important.
7960	* The priorities of VM-exits and events are listed from highest
7961	* to lowest as follows:
7962	*
7963	* 1. Event injection.
7964	* 2. Trap on task-switch (T flag set in TSS).
7965	* 3. TPR below threshold / APIC-write.
7966	* 4. SMI, INIT.
7967	* 5. MTF exit.
7968	* 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7969	* 7. VMX-preemption timer.
7970	* 9. NMI-window exit.
7971	* 10. NMI injection.
7972	* 11. Interrupt-window exit.
7973	* 12. Virtual-interrupt injection.
7974	* 13. Interrupt injection.
7975	* 14. Process next instruction (fetch, decode, execute).
7976	*/
7977
7978	/* Setup VMX-preemption timer. */
7979	iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7980
7981	/* Setup monitor-trap flag. */
7982	iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7983
7984	/* Setup NMI-window exiting. */
7985	iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7986
7987	/* Setup interrupt-window exiting. */
7988	iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7989
7990	/*
7991	* Inject any event that the nested hypervisor wants to inject.
7992	* Note! We cannot immediately perform the event injection here as we may have
7993	* pending PGM operations to perform due to switching page tables and/or
7994	* mode.
7995	*/
7996	iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7997
7998	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7999	/* Reschedule to IEM-only execution of the nested-guest. */
8000	LogFlow(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
8001	int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
8002	if (rcSched != VINF_SUCCESS)
8003	iemSetPassUpStatus(pVCpu, rcSched);
8004	# endif
8005
8006	/* Finally, done. */
8007	Log2(("vmentry: %s: cs:rip=%04x:%08RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64 (%#RX64)\n",
8008	pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
8009	pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
8010	pVCpu->cpum.GstCtx.msrEFER, pVmcs->u64GuestEferMsr.u));
8011	return VINF_SUCCESS;
8012	}
8013	return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD \| VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
8014	}
8015	}
8016	return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE \| VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
8017	}
8018
8019	iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
8020	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8021	}
8022
8023	iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
8024	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8025	# endif
8026	}
8027
8028
8029	/**
8030	* Interface for HM and EM to emulate the VMLAUNCH/VMRESUME instruction.
8031	*
8032	* @returns Strict VBox status code.
8033	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
8034	* @param cbInstr The instruction length in bytes.
8035	* @param uInstrId The instruction ID (VMXINSTRID_VMLAUNCH or
8036	* VMXINSTRID_VMRESUME).
8037	* @thread EMT(pVCpu)
8038	*/
8039	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
8040	{
8041	IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
8042	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
8043
8044	iemInitExec(pVCpu, 0 /fExecOpts/);
8045	VBOXSTRICTRC rcStrict = iemVmxVmlaunchVmresume(pVCpu, cbInstr, uInstrId);
8046	Assert(!pVCpu->iem.s.cActiveMappings);
8047	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8048	}
8049
8050
8051	/**
8052	* Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
8053	* (causes a VM-exit) or not.
8054	*
8055	* @returns @c true if the instruction is intercepted, @c false otherwise.
8056	* @param pVCpu The cross context virtual CPU structure.
8057	* @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
8058	* VMX_EXIT_WRMSR).
8059	* @param idMsr The MSR.
8060	*/
8061	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT
8062	{
8063	Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
8064	Assert( uExitReason == VMX_EXIT_RDMSR
8065	\|\| uExitReason == VMX_EXIT_WRMSR);
8066
8067	/* Consult the MSR bitmap if the feature is supported. */
8068	PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
8069	Assert(pVmcs);
8070	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
8071	{
8072	uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
8073	if (uExitReason == VMX_EXIT_RDMSR)
8074	return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
8075	return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
8076	}
8077
8078	/* Without MSR bitmaps, all MSR accesses are intercepted. */
8079	return true;
8080	}
8081
8082
8083	/**
8084	* VMREAD instruction execution worker that does not perform any validation checks.
8085	*
8086	* Callers are expected to have performed the necessary checks and to ensure the
8087	* VMREAD will succeed.
8088	*
8089	* @param pVmcs Pointer to the virtual VMCS.
8090	* @param pu64Dst Where to write the VMCS value.
8091	* @param u64VmcsField The VMCS field.
8092	*
8093	* @remarks May be called with interrupts disabled.
8094	*/
8095	static void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField) RT_NOEXCEPT
8096	{
8097	VMXVMCSFIELD VmcsField;
8098	VmcsField.u = u64VmcsField;
8099	uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8100	uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8101	uint8_t const uWidthType = (uWidth << 2) \| uType;
8102	uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8103	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8104	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8105	AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
8106	uWidth, uType, uIndex, uIndex));
8107	AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8108
8109	/*
8110	* Read the VMCS component based on the field's effective width.
8111	*
8112	* The effective width is 64-bit fields adjusted to 32-bits if the access-type
8113	* indicates high bits (little endian).
8114	*
8115	* Note! The caller is responsible to trim the result and update registers
8116	* or memory locations are required. Here we just zero-extend to the largest
8117	* type (i.e. 64-bits).
8118	*/
8119	uint8_t const pbVmcs = (uint8_t const )pVmcs;
8120	uint8_t const *pbField = pbVmcs + offField;
8121	uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8122	switch (uEffWidth)
8123	{
8124	case VMX_VMCSFIELD_WIDTH_64BIT:
8125	case VMX_VMCSFIELD_WIDTH_NATURAL: pu64Dst = (uint64_t const *)pbField; break;
8126	case VMX_VMCSFIELD_WIDTH_32BIT: pu64Dst = (uint32_t const *)pbField; break;
8127	case VMX_VMCSFIELD_WIDTH_16BIT: pu64Dst = (uint16_t const *)pbField; break;
8128	}
8129	}
8130
8131
8132	/**
8133	* Interface for HM and EM to read a VMCS field from the nested-guest VMCS.
8134	*
8135	* It is ASSUMED the caller knows what they're doing. No VMREAD instruction checks
8136	* are performed. Bounds checks are strict builds only.
8137	*
8138	* @param pVmcs Pointer to the virtual VMCS.
8139	* @param u64VmcsField The VMCS field.
8140	* @param pu64Dst Where to store the VMCS value.
8141	*
8142	* @remarks May be called with interrupts disabled.
8143	* @todo This should probably be moved to CPUM someday.
8144	*/
8145	VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst)
8146	{
8147	AssertPtr(pVmcs);
8148	AssertPtr(pu64Dst);
8149	iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8150	}
8151
8152
8153	/**
8154	* VMREAD common (memory/register) instruction execution worker.
8155	*
8156	* @returns Strict VBox status code.
8157	* @param pVCpu The cross context virtual CPU structure.
8158	* @param cbInstr The instruction length in bytes.
8159	* @param pu64Dst Where to write the VMCS value (only updated when
8160	* VINF_SUCCESS is returned).
8161	* @param u64VmcsField The VMCS field.
8162	* @param pExitInfo Pointer to the VM-exit information. Optional, can be
8163	* NULL.
8164	*/
8165	static VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8166	uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8167	{
8168	/* Nested-guest intercept. */
8169	if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8170	&& CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
8171	{
8172	if (pExitInfo)
8173	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8174	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
8175	}
8176
8177	/* CPL. */
8178	if (IEM_GET_CPL(pVCpu) == 0)
8179	{ /* likely */ }
8180	else
8181	{
8182	Log(("vmread: CPL %u -> #GP(0)\n", IEM_GET_CPL(pVCpu)));
8183	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
8184	return iemRaiseGeneralProtectionFault0(pVCpu);
8185	}
8186
8187	pVCpu->iem.s.cPotentialExits++;
8188
8189	/* VMCS pointer in root mode. */
8190	if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8191	\|\| IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8192	{ /* likely */ }
8193	else
8194	{
8195	Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8196	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
8197	iemVmxVmFailInvalid(pVCpu);
8198	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8199	}
8200
8201	/* VMCS-link pointer in non-root mode. */
8202	if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8203	\|\| IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8204	{ /* likely */ }
8205	else
8206	{
8207	Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8208	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
8209	iemVmxVmFailInvalid(pVCpu);
8210	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8211	}
8212
8213	/* Supported VMCS field. */
8214	if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8215	{ /* likely */ }
8216	else
8217	{
8218	Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8219	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
8220	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8221	iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
8222	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8223	}
8224
8225	/*
8226	* Reading from the current or shadow VMCS.
8227	*/
8228	PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8229	? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8230	: &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8231	iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8232	Log4(("vmread %#RX64 => %#RX64\n", u64VmcsField, *pu64Dst));
8233	return VINF_SUCCESS;
8234	}
8235
8236
8237	/**
8238	* VMREAD (64-bit register) instruction execution worker.
8239	*
8240	* @returns Strict VBox status code.
8241	* @param pVCpu The cross context virtual CPU structure.
8242	* @param cbInstr The instruction length in bytes.
8243	* @param pu64Dst Where to store the VMCS field's value.
8244	* @param u64VmcsField The VMCS field.
8245	* @param pExitInfo Pointer to the VM-exit information. Optional, can be
8246	* NULL.
8247	*/
8248	static VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8249	uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8250	{
8251	VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
8252	if (rcStrict == VINF_SUCCESS)
8253	{
8254	iemVmxVmSucceed(pVCpu);
8255	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8256	}
8257
8258	Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8259	return rcStrict;
8260	}
8261
8262
8263	/**
8264	* VMREAD (32-bit register) instruction execution worker.
8265	*
8266	* @returns Strict VBox status code.
8267	* @param pVCpu The cross context virtual CPU structure.
8268	* @param cbInstr The instruction length in bytes.
8269	* @param pu32Dst Where to store the VMCS field's value.
8270	* @param u32VmcsField The VMCS field.
8271	* @param pExitInfo Pointer to the VM-exit information. Optional, can be
8272	* NULL.
8273	*/
8274	static VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst,
8275	uint64_t u32VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8276	{
8277	uint64_t u64Dst;
8278	VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
8279	if (rcStrict == VINF_SUCCESS)
8280	{
8281	*pu32Dst = u64Dst;
8282	iemVmxVmSucceed(pVCpu);
8283	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8284	}
8285
8286	Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8287	return rcStrict;
8288	}
8289
8290
8291	/**
8292	* VMREAD (memory) instruction execution worker.
8293	*
8294	* @returns Strict VBox status code.
8295	* @param pVCpu The cross context virtual CPU structure.
8296	* @param cbInstr The instruction length in bytes.
8297	* @param iEffSeg The effective segment register to use with @a u64Val.
8298	* Pass UINT8_MAX if it is a register access.
8299	* @param GCPtrDst The guest linear address to store the VMCS field's
8300	* value.
8301	* @param u64VmcsField The VMCS field.
8302	* @param pExitInfo Pointer to the VM-exit information. Optional, can be
8303	* NULL.
8304	*/
8305	static VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst,
8306	uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8307	{
8308	uint64_t u64Dst;
8309	VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
8310	if (rcStrict == VINF_SUCCESS)
8311	{
8312	/*
8313	* Write the VMCS field's value to the location specified in guest-memory.
8314	*/
8315	if (IEM_IS_64BIT_CODE(pVCpu))
8316	rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8317	else
8318	rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8319	if (rcStrict == VINF_SUCCESS)
8320	{
8321	iemVmxVmSucceed(pVCpu);
8322	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8323	}
8324
8325	Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8326	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8327	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
8328	return rcStrict;
8329	}
8330
8331	Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8332	return rcStrict;
8333	}
8334
8335
8336	/**
8337	* Interface for HM and EM to emulate the VMREAD instruction.
8338	*
8339	* @returns Strict VBox status code.
8340	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
8341	* @param pExitInfo Pointer to the VM-exit information.
8342	* @thread EMT(pVCpu)
8343	*/
8344	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8345	{
8346	IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8347	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI);
8348	Assert(pExitInfo);
8349
8350	iemInitExec(pVCpu, 0 /fExecOpts/);
8351
8352	VBOXSTRICTRC rcStrict;
8353	uint8_t const cbInstr = pExitInfo->cbInstr;
8354	bool const fIs64BitMode = RT_BOOL(IEM_IS_64BIT_CODE(pVCpu));
8355	uint64_t const u64FieldEnc = fIs64BitMode
8356	? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8357	: iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8358	if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8359	{
8360	if (fIs64BitMode)
8361	{
8362	uint64_t *pu64Dst = iemGRegRefU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8363	rcStrict = iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
8364	}
8365	else
8366	{
8367	uint32_t *pu32Dst = iemGRegRefU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8368	rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u64FieldEnc, pExitInfo);
8369	}
8370	}
8371	else
8372	{
8373	RTGCPTR const GCPtrDst = pExitInfo->GCPtrEffAddr;
8374	uint8_t const iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8375	rcStrict = iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, pExitInfo);
8376	}
8377	Assert(!pVCpu->iem.s.cActiveMappings);
8378	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8379	}
8380
8381
8382	/**
8383	* VMWRITE instruction execution worker that does not perform any validation
8384	* checks.
8385	*
8386	* Callers are expected to have performed the necessary checks and to ensure the
8387	* VMWRITE will succeed.
8388	*
8389	* @param pVmcs Pointer to the virtual VMCS.
8390	* @param u64Val The value to write.
8391	* @param u64VmcsField The VMCS field.
8392	*
8393	* @remarks May be called with interrupts disabled.
8394	*/
8395	static void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField) RT_NOEXCEPT
8396	{
8397	VMXVMCSFIELD VmcsField;
8398	VmcsField.u = u64VmcsField;
8399	uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8400	uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8401	uint8_t const uWidthType = (uWidth << 2) \| uType;
8402	uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8403	Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8404	uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8405	Assert(offField < VMX_V_VMCS_SIZE);
8406	AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8407
8408	/*
8409	* Write the VMCS component based on the field's effective width.
8410	*
8411	* The effective width is 64-bit fields adjusted to 32-bits if the access-type
8412	* indicates high bits (little endian).
8413	*/
8414	uint8_t pbVmcs = (uint8_t )pVmcs;
8415	uint8_t *pbField = pbVmcs + offField;
8416	uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8417	switch (uEffWidth)
8418	{
8419	case VMX_VMCSFIELD_WIDTH_64BIT:
8420	case VMX_VMCSFIELD_WIDTH_NATURAL: (uint64_t )pbField = u64Val; break;
8421	case VMX_VMCSFIELD_WIDTH_32BIT: (uint32_t )pbField = u64Val; break;
8422	case VMX_VMCSFIELD_WIDTH_16BIT: (uint16_t )pbField = u64Val; break;
8423	}
8424	}
8425
8426
8427	/**
8428	* Interface for HM and EM to write a VMCS field in the nested-guest VMCS.
8429	*
8430	* It is ASSUMED the caller knows what they're doing. No VMWRITE instruction checks
8431	* are performed. Bounds checks are strict builds only.
8432	*
8433	* @param pVmcs Pointer to the virtual VMCS.
8434	* @param u64VmcsField The VMCS field.
8435	* @param u64Val The value to write.
8436	*
8437	* @remarks May be called with interrupts disabled.
8438	* @todo This should probably be moved to CPUM someday.
8439	*/
8440	VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val)
8441	{
8442	AssertPtr(pVmcs);
8443	iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8444	}
8445
8446
8447	/**
8448	* VMWRITE instruction execution worker.
8449	*
8450	* @returns Strict VBox status code.
8451	* @param pVCpu The cross context virtual CPU structure.
8452	* @param cbInstr The instruction length in bytes.
8453	* @param iEffSeg The effective segment register to use with @a u64Val.
8454	* Pass UINT8_MAX if it is a register access.
8455	* @param u64Val The value to write (or guest linear address to the
8456	* value), @a iEffSeg will indicate if it's a memory
8457	* operand.
8458	* @param u64VmcsField The VMCS field.
8459	* @param pExitInfo Pointer to the VM-exit information. Optional, can be
8460	* NULL.
8461	*/
8462	static VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val,
8463	uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8464	{
8465	/* Nested-guest intercept. */
8466	if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8467	&& CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8468	{
8469	if (pExitInfo)
8470	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8471	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8472	}
8473
8474	/* CPL. */
8475	if (IEM_GET_CPL(pVCpu) == 0)
8476	{ /* likely */ }
8477	else
8478	{
8479	Log(("vmwrite: CPL %u -> #GP(0)\n", IEM_GET_CPL(pVCpu)));
8480	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8481	return iemRaiseGeneralProtectionFault0(pVCpu);
8482	}
8483
8484	pVCpu->iem.s.cPotentialExits++;
8485
8486	/* VMCS pointer in root mode. */
8487	if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8488	\|\| IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8489	{ /* likely */ }
8490	else
8491	{
8492	Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8493	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8494	iemVmxVmFailInvalid(pVCpu);
8495	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8496	}
8497
8498	/* VMCS-link pointer in non-root mode. */
8499	if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8500	\|\| IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8501	{ /* likely */ }
8502	else
8503	{
8504	Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8505	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8506	iemVmxVmFailInvalid(pVCpu);
8507	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8508	}
8509
8510	/* If the VMWRITE instruction references memory, access the specified memory operand. */
8511	bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8512	if (!fIsRegOperand)
8513	{
8514	/* Read the value from the specified guest memory location. */
8515	VBOXSTRICTRC rcStrict;
8516	RTGCPTR const GCPtrVal = u64Val;
8517	if (IEM_IS_64BIT_CODE(pVCpu))
8518	rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8519	else
8520	rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8521	if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8522	{
8523	Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8524	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8525	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
8526	return rcStrict;
8527	}
8528	}
8529	else
8530	Assert(!pExitInfo \|\| pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8531
8532	/* Supported VMCS field. */
8533	if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8534	{ /* likely */ }
8535	else
8536	{
8537	Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8538	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8539	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8540	iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8541	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8542	}
8543
8544	/* Read-only VMCS field. */
8545	bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8546	if ( !fIsFieldReadOnly
8547	\|\| IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8548	{ /* likely */ }
8549	else
8550	{
8551	Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8552	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8553	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8554	iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8555	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8556	}
8557
8558	/*
8559	* Write to the current or shadow VMCS.
8560	*/
8561	bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8562	PVMXVVMCS pVmcs = !fInVmxNonRootMode
8563	? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8564	: &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8565	iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8566	Log4(("vmwrite %#RX64 <= %#RX64\n", u64VmcsField, u64Val));
8567
8568	if ( !fInVmxNonRootMode
8569	&& VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8570	{
8571	/* Notify HM that the VMCS content might have changed. */
8572	HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8573	}
8574
8575	iemVmxVmSucceed(pVCpu);
8576	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8577	}
8578
8579
8580	/**
8581	* Interface for HM and EM to emulate the VMWRITE instruction.
8582	*
8583	* @returns Strict VBox status code.
8584	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
8585	* @param pExitInfo Pointer to the VM-exit information.
8586	* @thread EMT(pVCpu)
8587	*/
8588	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8589	{
8590	IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8591	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI);
8592	Assert(pExitInfo);
8593
8594	iemInitExec(pVCpu, 0 /fExecOpts/);
8595
8596	uint64_t u64Val;
8597	uint8_t iEffSeg;
8598	if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8599	{
8600	u64Val = iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8601	iEffSeg = UINT8_MAX;
8602	}
8603	else
8604	{
8605	u64Val = pExitInfo->GCPtrEffAddr;
8606	iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8607	}
8608	uint8_t const cbInstr = pExitInfo->cbInstr;
8609	uint64_t const u64FieldEnc = IEM_IS_64BIT_CODE(pVCpu)
8610	? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8611	: iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8612	VBOXSTRICTRC rcStrict = iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, u64Val, u64FieldEnc, pExitInfo);
8613	Assert(!pVCpu->iem.s.cActiveMappings);
8614	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8615	}
8616
8617
8618	/**
8619	* VMCLEAR instruction execution worker.
8620	*
8621	* @returns Strict VBox status code.
8622	* @param pVCpu The cross context virtual CPU structure.
8623	* @param cbInstr The instruction length in bytes.
8624	* @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8625	* @param GCPtrVmcs The linear address of the VMCS pointer.
8626	* @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8627	*
8628	* @remarks Common VMX instruction checks are already expected to by the caller,
8629	* i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8630	*/
8631	static VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8632	RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8633	{
8634	/* Nested-guest intercept. */
8635	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8636	{
8637	if (pExitInfo)
8638	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8639	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8640	}
8641
8642	Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8643
8644	/* CPL. */
8645	if (IEM_GET_CPL(pVCpu) == 0)
8646	{ /* likely */ }
8647	else
8648	{
8649	Log(("vmclear: CPL %u -> #GP(0)\n", IEM_GET_CPL(pVCpu)));
8650	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8651	return iemRaiseGeneralProtectionFault0(pVCpu);
8652	}
8653
8654	/* Get the VMCS pointer from the location specified by the source memory operand. */
8655	RTGCPHYS GCPhysVmcs;
8656	VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8657	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8658	{ /* likely */ }
8659	else
8660	{
8661	Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8662	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8663	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8664	return rcStrict;
8665	}
8666
8667	/* VMCS pointer alignment. */
8668	if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8669	{ /* likely */ }
8670	else
8671	{
8672	Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8673	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8674	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8675	iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8676	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8677	}
8678
8679	/* VMCS physical-address width limits. */
8680	if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8681	{ /* likely */ }
8682	else
8683	{
8684	Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8685	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8686	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8687	iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8688	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8689	}
8690
8691	/* VMCS is not the VMXON region. */
8692	if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8693	{ /* likely */ }
8694	else
8695	{
8696	Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8697	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8698	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8699	iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8700	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8701	}
8702
8703	/* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8704	restriction imposed by our implementation. */
8705	if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8706	{ /* likely */ }
8707	else
8708	{
8709	Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8710	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8711	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8712	iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8713	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8714	}
8715
8716	/*
8717	* VMCLEAR allows committing and clearing any valid VMCS pointer.
8718	*
8719	* If the current VMCS is the one being cleared, set its state to 'clear' and commit
8720	* to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8721	* to 'clear'.
8722	*/
8723	uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8724	if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8725	&& IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8726	{
8727	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8728	iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8729	IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8730	}
8731	else
8732	{
8733	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8734	rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8735	(const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8736	if (RT_FAILURE(rcStrict))
8737	return rcStrict;
8738	}
8739
8740	iemVmxVmSucceed(pVCpu);
8741	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8742	}
8743
8744
8745	/**
8746	* Interface for HM and EM to emulate the VMCLEAR instruction.
8747	*
8748	* @returns Strict VBox status code.
8749	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
8750	* @param pExitInfo Pointer to the VM-exit information.
8751	* @thread EMT(pVCpu)
8752	*/
8753	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8754	{
8755	Assert(pExitInfo);
8756	IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8757	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI);
8758
8759	iemInitExec(pVCpu, 0 /fExecOpts/);
8760
8761	uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8762	uint8_t const cbInstr = pExitInfo->cbInstr;
8763	RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8764	VBOXSTRICTRC rcStrict = iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8765	Assert(!pVCpu->iem.s.cActiveMappings);
8766	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8767	}
8768
8769
8770	/**
8771	* VMPTRST instruction execution worker.
8772	*
8773	* @returns Strict VBox status code.
8774	* @param pVCpu The cross context virtual CPU structure.
8775	* @param cbInstr The instruction length in bytes.
8776	* @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8777	* @param GCPtrVmcs The linear address of where to store the current VMCS
8778	* pointer.
8779	* @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8780	*
8781	* @remarks Common VMX instruction checks are already expected to by the caller,
8782	* i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8783	*/
8784	static VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8785	RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8786	{
8787	/* Nested-guest intercept. */
8788	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8789	{
8790	if (pExitInfo)
8791	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8792	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8793	}
8794
8795	Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8796
8797	/* CPL. */
8798	if (IEM_GET_CPL(pVCpu) == 0)
8799	{ /* likely */ }
8800	else
8801	{
8802	Log(("vmptrst: CPL %u -> #GP(0)\n", IEM_GET_CPL(pVCpu)));
8803	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8804	return iemRaiseGeneralProtectionFault0(pVCpu);
8805	}
8806
8807	/* Set the VMCS pointer to the location specified by the destination memory operand. */
8808	AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8809	VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8810	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8811	{
8812	iemVmxVmSucceed(pVCpu);
8813	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8814	}
8815
8816	Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8817	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8818	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8819	return rcStrict;
8820	}
8821
8822
8823	/**
8824	* Interface for HM and EM to emulate the VMPTRST instruction.
8825	*
8826	* @returns Strict VBox status code.
8827	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
8828	* @param pExitInfo Pointer to the VM-exit information.
8829	* @thread EMT(pVCpu)
8830	*/
8831	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8832	{
8833	Assert(pExitInfo);
8834	IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8835	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI);
8836
8837	iemInitExec(pVCpu, 0 /fExecOpts/);
8838
8839	uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8840	uint8_t const cbInstr = pExitInfo->cbInstr;
8841	RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8842	VBOXSTRICTRC rcStrict = iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8843	Assert(!pVCpu->iem.s.cActiveMappings);
8844	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8845	}
8846
8847
8848	/**
8849	* VMPTRLD instruction execution worker.
8850	*
8851	* @returns Strict VBox status code.
8852	* @param pVCpu The cross context virtual CPU structure.
8853	* @param cbInstr The instruction length in bytes.
8854	* @param GCPtrVmcs The linear address of the current VMCS pointer.
8855	* @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8856	*
8857	* @remarks Common VMX instruction checks are already expected to by the caller,
8858	* i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8859	*/
8860	static VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8861	RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8862	{
8863	/* Nested-guest intercept. */
8864	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8865	{
8866	if (pExitInfo)
8867	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8868	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8869	}
8870
8871	Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8872
8873	/* CPL. */
8874	if (IEM_GET_CPL(pVCpu) == 0)
8875	{ /* likely */ }
8876	else
8877	{
8878	Log(("vmptrld: CPL %u -> #GP(0)\n", IEM_GET_CPL(pVCpu)));
8879	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8880	return iemRaiseGeneralProtectionFault0(pVCpu);
8881	}
8882
8883	/* Get the VMCS pointer from the location specified by the source memory operand. */
8884	RTGCPHYS GCPhysVmcs;
8885	VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8886	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8887	{ /* likely */ }
8888	else
8889	{
8890	Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8891	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8892	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8893	return rcStrict;
8894	}
8895
8896	/* VMCS pointer alignment. */
8897	if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8898	{ /* likely */ }
8899	else
8900	{
8901	Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8902	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8903	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8904	iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8905	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8906	}
8907
8908	/* VMCS physical-address width limits. */
8909	if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8910	{ /* likely */ }
8911	else
8912	{
8913	Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8914	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8915	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8916	iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8917	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8918	}
8919
8920	/* VMCS is not the VMXON region. */
8921	if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8922	{ /* likely */ }
8923	else
8924	{
8925	Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8926	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8927	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8928	iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8929	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8930	}
8931
8932	/* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8933	restriction imposed by our implementation. */
8934	if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8935	{ /* likely */ }
8936	else
8937	{
8938	Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8939	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8940	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8941	iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8942	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8943	}
8944
8945	/* Read just the VMCS revision from the VMCS. */
8946	VMXVMCSREVID VmcsRevId;
8947	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8948	if (RT_SUCCESS(rc))
8949	{ /* likely */ }
8950	else
8951	{
8952	Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8953	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8954	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8955	return rc;
8956	}
8957
8958	/*
8959	* Verify the VMCS revision specified by the guest matches what we reported to the guest.
8960	* Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8961	*/
8962	if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8963	&& ( !VmcsRevId.n.fIsShadowVmcs
8964	\|\| IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8965	{ /* likely */ }
8966	else
8967	{
8968	if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8969	{
8970	Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8971	VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8972	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8973	}
8974	else
8975	{
8976	Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8977	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8978	}
8979	iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8980	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8981	}
8982
8983	/*
8984	* We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8985	* the cache of an existing, current VMCS back to guest memory before loading a new,
8986	* different current VMCS.
8987	*/
8988	if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8989	{
8990	if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8991	{
8992	iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8993	IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8994	}
8995
8996	/* Set the new VMCS as the current VMCS and read it from guest memory. */
8997	IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8998	rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8999	if (RT_SUCCESS(rc))
9000	{
9001	/* Notify HM that a new, current VMCS is loaded. */
9002	if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
9003	HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
9004
9005	/* Convert legacy launch-state value to current value, see @bugref{10318#c114} for reasons.*/
9006	if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR_LEGACY)
9007	{
9008	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
9009	Log(("vmptrld: Updated legacy 'VMCLEAR' VMCS launch-state bit to current\n"));
9010	}
9011	}
9012	else
9013	{
9014	Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
9015	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
9016	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
9017	return rc;
9018	}
9019	}
9020	else if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
9021	&& pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR_LEGACY)
9022	{
9023	/* Convert legacy launch-state value to current value, see @bugref{10318#c114} for reasons.*/
9024	pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
9025	Log(("vmptrld: Updated legacy VMCLEAR launch-state bit to current\n"));
9026	}
9027
9028	Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
9029	iemVmxVmSucceed(pVCpu);
9030	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9031	}
9032
9033
9034	/**
9035	* Interface for HM and EM to emulate the VMPTRLD instruction.
9036	*
9037	* @returns Strict VBox status code.
9038	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
9039	* @param pExitInfo Pointer to the VM-exit information.
9040	* @thread EMT(pVCpu)
9041	*/
9042	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9043	{
9044	Assert(pExitInfo);
9045	IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
9046	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI);
9047
9048	iemInitExec(pVCpu, 0 /fExecOpts/);
9049
9050	uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
9051	uint8_t const cbInstr = pExitInfo->cbInstr;
9052	RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
9053	VBOXSTRICTRC rcStrict = iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
9054	Assert(!pVCpu->iem.s.cActiveMappings);
9055	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9056	}
9057
9058
9059	/**
9060	* INVVPID instruction execution worker.
9061	*
9062	* @returns Strict VBox status code.
9063	* @param pVCpu The cross context virtual CPU structure.
9064	* @param cbInstr The instruction length in bytes.
9065	* @param iEffSeg The segment of the invvpid descriptor.
9066	* @param GCPtrInvvpidDesc The address of invvpid descriptor.
9067	* @param u64InvvpidType The invalidation type.
9068	* @param pExitInfo Pointer to the VM-exit information. Optional, can be
9069	* NULL.
9070	*
9071	* @remarks Common VMX instruction checks are already expected to by the caller,
9072	* i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9073	*/
9074	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
9075	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9076	{
9077	/* Check if INVVPID instruction is supported, otherwise raise #UD. */
9078	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
9079	return iemRaiseUndefinedOpcode(pVCpu);
9080
9081	/* Nested-guest intercept. */
9082	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9083	{
9084	if (pExitInfo)
9085	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9086	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
9087	}
9088
9089	/* CPL. */
9090	if (IEM_GET_CPL(pVCpu) != 0)
9091	{
9092	Log(("invvpid: CPL != 0 -> #GP(0)\n"));
9093	return iemRaiseGeneralProtectionFault0(pVCpu);
9094	}
9095
9096	/*
9097	* Validate INVVPID invalidation type.
9098	*
9099	* The instruction specifies exactly ONE of the supported invalidation types.
9100	*
9101	* Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9102	* supported. In theory, it's possible for a CPU to not support flushing individual
9103	* addresses but all the other types or any other combination. We do not take any
9104	* shortcuts here by assuming the types we currently expose to the guest.
9105	*/
9106	uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9107	bool const fInvvpidSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID);
9108	bool const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
9109	bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
9110	bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
9111	bool const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
9112
9113	bool afSupportedTypes[4];
9114	afSupportedTypes[0] = fTypeIndivAddr;
9115	afSupportedTypes[1] = fTypeSingleCtx;
9116	afSupportedTypes[2] = fTypeAllCtx;
9117	afSupportedTypes[3] = fTypeSingleCtxRetainGlobals;
9118
9119	if ( fInvvpidSupported
9120	&& !(u64InvvpidType & ~(uint64_t)VMX_INVVPID_VALID_MASK)
9121	&& afSupportedTypes[u64InvvpidType & 3])
9122	{ /* likely */ }
9123	else
9124	{
9125	Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
9126	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
9127	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9128	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9129	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9130	}
9131
9132	/*
9133	* Fetch the invvpid descriptor from guest memory.
9134	*/
9135	RTUINT128U uDesc;
9136	VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
9137	if (rcStrict == VINF_SUCCESS)
9138	{
9139	/*
9140	* Validate the descriptor.
9141	*/
9142	if (uDesc.s.Lo <= 0xffff)
9143	{ /* likely */ }
9144	else
9145	{
9146	Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
9147	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
9148	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
9149	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9150	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9151	}
9152
9153	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9154	RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
9155	uint16_t const uVpid = uDesc.Words.w0;
9156	uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9157	switch (u64InvvpidType)
9158	{
9159	case VMXTLBFLUSHVPID_INDIV_ADDR:
9160	{
9161	if (uVpid != 0)
9162	{
9163	if (IEM_IS_CANONICAL(GCPtrInvAddr))
9164	{
9165	/* Invalidate mappings for the linear address tagged with VPID. */
9166	/** @todo PGM support for VPID? Currently just flush everything. */
9167	PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9168	iemVmxVmSucceed(pVCpu);
9169	}
9170	else
9171	{
9172	Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
9173	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
9174	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
9175	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9176	}
9177	}
9178	else
9179	{
9180	Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9181	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
9182	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9183	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9184	}
9185	break;
9186	}
9187
9188	case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
9189	{
9190	if (uVpid != 0)
9191	{
9192	/* Invalidate all mappings with VPID. */
9193	/** @todo PGM support for VPID? Currently just flush everything. */
9194	PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9195	iemVmxVmSucceed(pVCpu);
9196	}
9197	else
9198	{
9199	Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9200	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
9201	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9202	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9203	}
9204	break;
9205	}
9206
9207	case VMXTLBFLUSHVPID_ALL_CONTEXTS:
9208	{
9209	/* Invalidate all mappings with non-zero VPIDs. */
9210	/** @todo PGM support for VPID? Currently just flush everything. */
9211	PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9212	iemVmxVmSucceed(pVCpu);
9213	break;
9214	}
9215
9216	case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
9217	{
9218	if (uVpid != 0)
9219	{
9220	/* Invalidate all mappings with VPID except global translations. */
9221	/** @todo PGM support for VPID? Currently just flush everything. */
9222	PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9223	iemVmxVmSucceed(pVCpu);
9224	}
9225	else
9226	{
9227	Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9228	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
9229	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
9230	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9231	}
9232	break;
9233	}
9234	IEM_NOT_REACHED_DEFAULT_CASE_RET();
9235	}
9236	rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9237	}
9238	return rcStrict;
9239	}
9240
9241
9242	/**
9243	* Interface for HM and EM to emulate the INVVPID instruction.
9244	*
9245	* @returns Strict VBox status code.
9246	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
9247	* @param pExitInfo Pointer to the VM-exit information.
9248	* @thread EMT(pVCpu)
9249	*/
9250	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9251	{
9252	IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9253	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI);
9254	Assert(pExitInfo);
9255
9256	iemInitExec(pVCpu, 0 /fExecOpts/);
9257
9258	uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9259	uint8_t const cbInstr = pExitInfo->cbInstr;
9260	RTGCPTR const GCPtrInvvpidDesc = pExitInfo->GCPtrEffAddr;
9261	uint64_t const u64InvvpidType = IEM_IS_64BIT_CODE(pVCpu)
9262	? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9263	: iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9264	VBOXSTRICTRC rcStrict = iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, u64InvvpidType, pExitInfo);
9265	Assert(!pVCpu->iem.s.cActiveMappings);
9266	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9267	}
9268
9269	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9270
9271	/**
9272	* INVEPT instruction execution worker.
9273	*
9274	* @returns Strict VBox status code.
9275	* @param pVCpu The cross context virtual CPU structure.
9276	* @param cbInstr The instruction length in bytes.
9277	* @param iEffSeg The segment of the invept descriptor.
9278	* @param GCPtrInveptDesc The address of invept descriptor.
9279	* @param u64InveptType The invalidation type.
9280	* @param pExitInfo Pointer to the VM-exit information. Optional, can be
9281	* NULL.
9282	*
9283	* @remarks Common VMX instruction checks are already expected to by the caller,
9284	* i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9285	*/
9286	static VBOXSTRICTRC iemVmxInvept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInveptDesc,
9287	uint64_t u64InveptType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9288	{
9289	/* Check if EPT is supported, otherwise raise #UD. */
9290	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEpt)
9291	return iemRaiseUndefinedOpcode(pVCpu);
9292
9293	/* Nested-guest intercept. */
9294	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9295	{
9296	if (pExitInfo)
9297	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9298	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVEPT, VMXINSTRID_NONE, cbInstr);
9299	}
9300
9301	/* CPL. */
9302	if (IEM_GET_CPL(pVCpu) != 0)
9303	{
9304	Log(("invept: CPL != 0 -> #GP(0)\n"));
9305	return iemRaiseGeneralProtectionFault0(pVCpu);
9306	}
9307
9308	/*
9309	* Validate INVEPT invalidation type.
9310	*
9311	* The instruction specifies exactly ONE of the supported invalidation types.
9312	*
9313	* Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9314	* supported. In theory, it's possible for a CPU to not support flushing individual
9315	* addresses but all the other types or any other combination. We do not take any
9316	* shortcuts here by assuming the types we currently expose to the guest.
9317	*/
9318	uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9319	bool const fInveptSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT);
9320	bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
9321	bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
9322
9323	bool afSupportedTypes[4];
9324	afSupportedTypes[0] = false;
9325	afSupportedTypes[1] = fTypeSingleCtx;
9326	afSupportedTypes[2] = fTypeAllCtx;
9327	afSupportedTypes[3] = false;
9328
9329	if ( fInveptSupported
9330	&& !(u64InveptType & ~(uint64_t)VMX_INVEPT_VALID_MASK)
9331	&& afSupportedTypes[u64InveptType & 3])
9332	{ /* likely */ }
9333	else
9334	{
9335	Log(("invept: invalid/unsupported invvpid type %#x -> VMFail\n", u64InveptType));
9336	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_TypeInvalid;
9337	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType;
9338	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9339	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9340	}
9341
9342	/*
9343	* Fetch the invept descriptor from guest memory.
9344	*/
9345	RTUINT128U uDesc;
9346	VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInveptDesc);
9347	if (rcStrict == VINF_SUCCESS)
9348	{
9349	/*
9350	* Validate the descriptor.
9351	*
9352	* The Intel spec. does not explicit say the INVEPT instruction fails when reserved
9353	* bits in the descriptor are set, but it -does- for INVVPID. Until we test on real
9354	* hardware, it's assumed INVEPT behaves the same as INVVPID in this regard. It's
9355	* better to be strict in our emulation until proven otherwise.
9356	*/
9357	if (uDesc.s.Hi)
9358	{
9359	Log(("invept: reserved bits set in invept descriptor %#RX64 -> VMFail\n", uDesc.s.Hi));
9360	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_DescRsvd;
9361	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi;
9362	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9363	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9364	}
9365
9366	/*
9367	* Flush TLB mappings based on the EPT type.
9368	*/
9369	if (u64InveptType == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
9370	{
9371	uint64_t const GCPhysEptPtr = uDesc.s.Lo;
9372	int const rc = iemVmxVmentryCheckEptPtr(pVCpu, GCPhysEptPtr, NULL /* enmDiag */);
9373	if (RT_SUCCESS(rc))
9374	{ /* likely */ }
9375	else
9376	{
9377	Log(("invept: EPTP invalid %#RX64 -> VMFail\n", GCPhysEptPtr));
9378	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_EptpInvalid;
9379	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr;
9380	iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9381	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9382	}
9383	}
9384
9385	/** @todo PGM support for EPT tags? Currently just flush everything. */
9386	IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9387	uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9388	PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9389
9390	iemVmxVmSucceed(pVCpu);
9391	rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9392	}
9393
9394	return rcStrict;
9395	}
9396
9397
9398	/**
9399	* Interface for HM and EM to emulate the INVEPT instruction.
9400	*
9401	* @returns Strict VBox status code.
9402	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
9403	* @param pExitInfo Pointer to the VM-exit information.
9404	* @thread EMT(pVCpu)
9405	*/
9406	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9407	{
9408	IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9409	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI);
9410	Assert(pExitInfo);
9411
9412	iemInitExec(pVCpu, 0 /fExecOpts/);
9413
9414	uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9415	uint8_t const cbInstr = pExitInfo->cbInstr;
9416	RTGCPTR const GCPtrInveptDesc = pExitInfo->GCPtrEffAddr;
9417	uint64_t const u64InveptType = IEM_IS_64BIT_CODE(pVCpu)
9418	? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9419	: iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9420	VBOXSTRICTRC rcStrict = iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, u64InveptType, pExitInfo);
9421	Assert(!pVCpu->iem.s.cActiveMappings);
9422	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9423	}
9424
9425	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
9426
9427	/**
9428	* VMXON instruction execution worker.
9429	*
9430	* @returns Strict VBox status code.
9431	* @param pVCpu The cross context virtual CPU structure.
9432	* @param cbInstr The instruction length in bytes.
9433	* @param iEffSeg The effective segment register to use with @a
9434	* GCPtrVmxon.
9435	* @param GCPtrVmxon The linear address of the VMXON pointer.
9436	* @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
9437	*
9438	* @remarks Common VMX instruction checks are already expected to by the caller,
9439	* i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9440	*/
9441	static VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
9442	RTGCPHYS GCPtrVmxon, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9443	{
9444	if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
9445	{
9446	/* CPL. */
9447	if (IEM_GET_CPL(pVCpu) == 0)
9448	{ /* likely */ }
9449	else
9450	{
9451	Log(("vmxon: CPL %u -> #GP(0)\n", IEM_GET_CPL(pVCpu)));
9452	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
9453	return iemRaiseGeneralProtectionFault0(pVCpu);
9454	}
9455
9456	/* A20M (A20 Masked) mode. */
9457	if (PGMPhysIsA20Enabled(pVCpu))
9458	{ /* likely */ }
9459	else
9460	{
9461	Log(("vmxon: A20M mode -> #GP(0)\n"));
9462	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
9463	return iemRaiseGeneralProtectionFault0(pVCpu);
9464	}
9465
9466	/* CR0. */
9467	{
9468	/*
9469	* CR0 MB1 bits.
9470	*
9471	* We use VMX_V_CR0_FIXED0 below to ensure CR0.PE and CR0.PG are always set
9472	* while executing VMXON. CR0.PE and CR0.PG are only allowed to be clear
9473	* when the guest running in VMX non-root mode with unrestricted-guest control
9474	* enabled in the VMCS.
9475	*/
9476	uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
9477	if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
9478	{ /* likely */ }
9479	else
9480	{
9481	Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
9482	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
9483	return iemRaiseGeneralProtectionFault0(pVCpu);
9484	}
9485
9486	/* CR0 MBZ bits. */
9487	uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
9488	if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
9489	{ /* likely */ }
9490	else
9491	{
9492	Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
9493	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
9494	return iemRaiseGeneralProtectionFault0(pVCpu);
9495	}
9496	}
9497
9498	/* CR4. */
9499	{
9500	/* CR4 MB1 bits. */
9501	uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
9502	if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
9503	{ /* likely */ }
9504	else
9505	{
9506	Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
9507	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
9508	return iemRaiseGeneralProtectionFault0(pVCpu);
9509	}
9510
9511	/* CR4 MBZ bits. */
9512	uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
9513	if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
9514	{ /* likely */ }
9515	else
9516	{
9517	Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
9518	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
9519	return iemRaiseGeneralProtectionFault0(pVCpu);
9520	}
9521	}
9522
9523	/* Feature control MSR's LOCK and VMXON bits. */
9524	uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
9525	if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON))
9526	== (MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON))
9527	{ /* likely */ }
9528	else
9529	{
9530	Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
9531	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
9532	return iemRaiseGeneralProtectionFault0(pVCpu);
9533	}
9534
9535	/* Get the VMXON pointer from the location specified by the source memory operand. */
9536	RTGCPHYS GCPhysVmxon;
9537	VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
9538	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
9539	{ /* likely */ }
9540	else
9541	{
9542	Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
9543	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
9544	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
9545	return rcStrict;
9546	}
9547
9548	/* VMXON region pointer alignment. */
9549	if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
9550	{ /* likely */ }
9551	else
9552	{
9553	Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
9554	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
9555	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9556	iemVmxVmFailInvalid(pVCpu);
9557	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9558	}
9559
9560	/* VMXON physical-address width limits. */
9561	if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
9562	{ /* likely */ }
9563	else
9564	{
9565	Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
9566	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
9567	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9568	iemVmxVmFailInvalid(pVCpu);
9569	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9570	}
9571
9572	/* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
9573	restriction imposed by our implementation. */
9574	if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
9575	{ /* likely */ }
9576	else
9577	{
9578	Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
9579	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
9580	pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9581	iemVmxVmFailInvalid(pVCpu);
9582	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9583	}
9584
9585	/* Read the VMCS revision ID from the VMXON region. */
9586	VMXVMCSREVID VmcsRevId;
9587	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
9588	if (RT_SUCCESS(rc))
9589	{ /* likely */ }
9590	else
9591	{
9592	Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
9593	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
9594	return rc;
9595	}
9596
9597	/* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
9598	if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
9599	{ /* likely */ }
9600	else
9601	{
9602	/* Revision ID mismatch. */
9603	if (!VmcsRevId.n.fIsShadowVmcs)
9604	{
9605	Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
9606	VmcsRevId.n.u31RevisionId));
9607	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
9608	iemVmxVmFailInvalid(pVCpu);
9609	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9610	}
9611
9612	/* Shadow VMCS disallowed. */
9613	Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
9614	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
9615	iemVmxVmFailInvalid(pVCpu);
9616	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9617	}
9618
9619	/*
9620	* Record that we're in VMX operation, block INIT, block and disable A20M.
9621	*/
9622	pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
9623	IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
9624	pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
9625
9626	/* Clear address-range monitoring. */
9627	EMMonitorWaitClear(pVCpu);
9628	/** @todo NSTVMX: Intel PT. */
9629
9630	iemVmxVmSucceed(pVCpu);
9631	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9632	}
9633	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9634	{
9635	/* Nested-guest intercept. */
9636	if (pExitInfo)
9637	return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9638	return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
9639	}
9640
9641	Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
9642
9643	/* CPL. */
9644	if (IEM_GET_CPL(pVCpu) > 0)
9645	{
9646	Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", IEM_GET_CPL(pVCpu)));
9647	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
9648	return iemRaiseGeneralProtectionFault0(pVCpu);
9649	}
9650
9651	/* VMXON when already in VMX root mode. */
9652	iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
9653	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
9654	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9655	}
9656
9657
9658	/**
9659	* Interface for HM and EM to emulate the VMXON instruction.
9660	*
9661	* @returns Strict VBox status code.
9662	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
9663	* @param pExitInfo Pointer to the VM-exit information.
9664	* @thread EMT(pVCpu)
9665	*/
9666	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9667	{
9668	Assert(pExitInfo);
9669	IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
9670	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI);
9671
9672	iemInitExec(pVCpu, 0 /fExecOpts/);
9673
9674	uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
9675	uint8_t const cbInstr = pExitInfo->cbInstr;
9676	RTGCPTR const GCPtrVmxon = pExitInfo->GCPtrEffAddr;
9677	VBOXSTRICTRC rcStrict = iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
9678	Assert(!pVCpu->iem.s.cActiveMappings);
9679	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9680	}
9681
9682
9683	/**
9684	* Implements 'VMXOFF'.
9685	*
9686	* @remarks Common VMX instruction checks are already expected to by the caller,
9687	* i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9688	*/
9689	IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
9690	{
9691	/* Nested-guest intercept. */
9692	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9693	return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9694
9695	/* CPL. */
9696	if (IEM_GET_CPL(pVCpu) == 0)
9697	{ /* likely */ }
9698	else
9699	{
9700	Log(("vmxoff: CPL %u -> #GP(0)\n", IEM_GET_CPL(pVCpu)));
9701	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9702	return iemRaiseGeneralProtectionFault0(pVCpu);
9703	}
9704
9705	/* Dual monitor treatment of SMIs and SMM. */
9706	uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9707	if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9708	{ /* likely */ }
9709	else
9710	{
9711	iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9712	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9713	}
9714
9715	/* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9716	pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9717	Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9718
9719	if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9720	{ /** @todo NSTVMX: Unblock SMI. */ }
9721
9722	EMMonitorWaitClear(pVCpu);
9723	/** @todo NSTVMX: Unblock and enable A20M. */
9724
9725	iemVmxVmSucceed(pVCpu);
9726	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9727	}
9728
9729
9730	/**
9731	* Interface for HM and EM to emulate the VMXOFF instruction.
9732	*
9733	* @returns Strict VBox status code.
9734	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
9735	* @param cbInstr The instruction length in bytes.
9736	* @thread EMT(pVCpu)
9737	*/
9738	VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr)
9739	{
9740	IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
9741	IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI);
9742
9743	iemInitExec(pVCpu, 0 /fExecOpts/);
9744	VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmxoff);
9745	Assert(!pVCpu->iem.s.cActiveMappings);
9746	return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9747	}
9748
9749
9750	/**
9751	* Implements 'VMXON'.
9752	*/
9753	IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9754	{
9755	return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9756	}
9757
9758
9759	/**
9760	* Implements 'VMLAUNCH'.
9761	*/
9762	IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9763	{
9764	return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9765	}
9766
9767
9768	/**
9769	* Implements 'VMRESUME'.
9770	*/
9771	IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9772	{
9773	return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9774	}
9775
9776
9777	/**
9778	* Implements 'VMPTRLD'.
9779	*/
9780	IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9781	{
9782	return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9783	}
9784
9785
9786	/**
9787	* Implements 'VMPTRST'.
9788	*/
9789	IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9790	{
9791	return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9792	}
9793
9794
9795	/**
9796	* Implements 'VMCLEAR'.
9797	*/
9798	IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9799	{
9800	return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9801	}
9802
9803
9804	/**
9805	* Implements 'VMWRITE' register.
9806	*/
9807	IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9808	{
9809	return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg /, u64Val, u64VmcsField, NULL / pExitInfo */);
9810	}
9811
9812
9813	/**
9814	* Implements 'VMWRITE' memory.
9815	*/
9816	IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9817	{
9818	return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9819	}
9820
9821
9822	/**
9823	* Implements 'VMREAD' register (64-bit).
9824	*/
9825	IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9826	{
9827	return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9828	}
9829
9830
9831	/**
9832	* Implements 'VMREAD' register (32-bit).
9833	*/
9834	IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint64_t *, pu64Dst, uint32_t, u32VmcsField)
9835	{
9836	VBOXSTRICTRC const rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, (uint32_t )pu64Dst, u32VmcsField, NULL / pExitInfo */);
9837	/* Zero the high part of the register on success. */
9838	if (rcStrict == VINF_SUCCESS)
9839	pu64Dst = (uint32_t)pu64Dst;
9840	return rcStrict;
9841	}
9842
9843
9844	/**
9845	* Implements 'VMREAD' memory, 64-bit register.
9846	*/
9847	IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9848	{
9849	return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9850	}
9851
9852
9853	/**
9854	* Implements 'VMREAD' memory, 32-bit register.
9855	*/
9856	IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9857	{
9858	return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9859	}
9860
9861
9862	/**
9863	* Implements 'INVVPID'.
9864	*/
9865	IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9866	{
9867	return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9868	}
9869
9870
9871	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) \|\| defined(VBOX_WITH_IEM_RECOMPILER) /* HACK ALERT: Linking trick. */
9872	/**
9873	* Implements 'INVEPT'.
9874	*/
9875	IEM_CIMPL_DEF_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType)
9876	{
9877	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9878	return iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType, NULL /* pExitInfo */);
9879	# else
9880	RT_NOREF(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType);
9881	AssertFailedReturn(VERR_IEM_ASPECT_NOT_IMPLEMENTED);
9882	# endif
9883	}
9884	#endif
9885
9886
9887	/**
9888	* Implements VMX's implementation of PAUSE.
9889	*/
9890	IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9891	{
9892	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9893	{
9894	VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9895	if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9896	return rcStrict;
9897	}
9898
9899	/*
9900	* Outside VMX non-root operation or if the PAUSE instruction does not cause
9901	* a VM-exit, the instruction operates normally.
9902	*/
9903	return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9904	}
9905
9906	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9907
9908
9909	/**
9910	* Implements 'VMCALL'.
9911	*/
9912	IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9913	{
9914	pVCpu->iem.s.cPotentialExits++;
9915
9916	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9917	/* Nested-guest intercept. */
9918	if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9919	return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9920	#endif
9921
9922	/* Join forces with vmmcall. */
9923	return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9924	}
9925
9926
9927	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9928
9929	/**
9930	* @callback_method_impl{FNPGMPHYSHANDLER, VMX APIC-access page accesses}
9931	*
9932	* @remarks The @a uUser argument is currently unused.
9933	*/
9934	DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPageHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, void *pvPhys,
9935	void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
9936	PGMACCESSORIGIN enmOrigin, uint64_t uUser)
9937	{
9938	RT_NOREF3(pvPhys, enmOrigin, uUser);
9939
9940	RTGCPHYS const GCPhysAccessBase = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9941	if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9942	{
9943	Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9944	Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysAccessBase);
9945
9946	uint32_t const fAccess = enmAccessType == PGMACCESSTYPE_WRITE ? IEM_ACCESS_DATA_W : IEM_ACCESS_DATA_R;
9947	uint16_t const offAccess = GCPhysFault & GUEST_PAGE_OFFSET_MASK;
9948
9949	LogFlowFunc(("Fault at %#RGp (cbBuf=%u fAccess=%#x)\n", GCPhysFault, cbBuf, fAccess));
9950	VBOXSTRICTRC rcStrict = iemVmxVirtApicAccessMem(pVCpu, offAccess, cbBuf, pvBuf, fAccess);
9951	if (RT_FAILURE(rcStrict))
9952	return rcStrict;
9953
9954	/* Any access on this APIC-access page has been handled, caller should not carry out the access. */
9955	return VINF_SUCCESS;
9956	}
9957
9958	LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysAccessBase));
9959	int rc = PGMHandlerPhysicalDeregister(pVM, GCPhysAccessBase);
9960	if (RT_FAILURE(rc))
9961	return rc;
9962
9963	/* Instruct the caller of this handler to perform the read/write as normal memory. */
9964	return VINF_PGM_HANDLER_DO_DEFAULT;
9965	}
9966
9967
9968	# ifndef IN_RING3
9969	/**
9970	* @callback_method_impl{FNPGMRZPHYSPFHANDLER,
9971	* \#PF access handler callback for guest VMX APIC-access page.}
9972	*/
9973	DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
9974	RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
9975
9976	{
9977	RT_NOREF3(pVM, pCtx, uUser);
9978
9979	/*
9980	* Handle the VMX APIC-access page only when the guest is in VMX non-root mode.
9981	* Otherwise we must deregister the page and allow regular RAM access.
9982	* Failing to do so lands us with endless EPT VM-exits.
9983	*/
9984	RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9985	if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9986	{
9987	Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9988	Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysPage);
9989
9990	/*
9991	* Check if the access causes an APIC-access VM-exit.
9992	*/
9993	uint32_t fAccess;
9994	if (uErr & X86_TRAP_PF_ID)
9995	fAccess = IEM_ACCESS_INSTRUCTION;
9996	else if (uErr & X86_TRAP_PF_RW)
9997	fAccess = IEM_ACCESS_DATA_W;
9998	else
9999	fAccess = IEM_ACCESS_DATA_R;
10000
10001	RTGCPHYS const GCPhysNestedFault = (RTGCPHYS)pvFault;
10002	uint16_t const offAccess = GCPhysNestedFault & GUEST_PAGE_OFFSET_MASK;
10003	bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, 1 /* cbAccess */, fAccess);
10004	LogFlowFunc(("#PF at %#RGp (GCPhysNestedFault=%#RGp offAccess=%#x)\n", GCPhysFault, GCPhysNestedFault, offAccess));
10005	if (fIntercept)
10006	{
10007	/*
10008	* Query the source VM-exit (from the execution engine) that caused this access
10009	* within the APIC-access page. Currently only HM is supported.
10010	*/
10011	AssertMsg(VM_IS_HM_ENABLED(pVM),
10012	("VM-exit auxiliary info. fetching not supported for execution engine %d\n", pVM->bMainExecutionEngine));
10013
10014	HMEXITAUX HmExitAux;
10015	RT_ZERO(HmExitAux);
10016	int const rc = HMR0GetExitAuxInfo(pVCpu, &HmExitAux, HMVMX_READ_EXIT_INSTR_LEN
10017	\| HMVMX_READ_EXIT_QUALIFICATION
10018	\| HMVMX_READ_IDT_VECTORING_INFO
10019	\| HMVMX_READ_IDT_VECTORING_ERROR_CODE);
10020	AssertRC(rc);
10021
10022	/*
10023	* Verify the VM-exit reason must be an EPT violation.
10024	* Other accesses should go through the other handler (iemVmxApicAccessPageHandler).
10025	* Refer to @bugref{10092#c33s} for a more detailed explanation.
10026	*/
10027	AssertMsgReturn(HmExitAux.Vmx.uReason == VMX_EXIT_EPT_VIOLATION,
10028	("Unexpected call to APIC-access page #PF handler for %#RGp offAcesss=%u uErr=%#RGx uReason=%u\n",
10029	GCPhysPage, offAccess, uErr, HmExitAux.Vmx.uReason), VERR_IEM_IPE_7);
10030
10031	/*
10032	* Construct the virtual APIC-access VM-exit.
10033	*/
10034	VMXAPICACCESS enmAccess;
10035	if (HmExitAux.Vmx.u64Qual & VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID)
10036	{
10037	if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
10038	enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
10039	else if (fAccess == IEM_ACCESS_INSTRUCTION)
10040	enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
10041	else if (fAccess & IEM_ACCESS_TYPE_WRITE)
10042	enmAccess = VMXAPICACCESS_LINEAR_WRITE;
10043	else
10044	enmAccess = VMXAPICACCESS_LINEAR_READ;
10045
10046	/* For linear-address accesss the instruction length must be valid. */
10047	AssertMsg(HmExitAux.Vmx.cbInstr > 0,
10048	("Invalid APIC-access VM-exit instruction length. cbInstr=%u\n", HmExitAux.Vmx.cbInstr));
10049	}
10050	else
10051	{
10052	if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
10053	enmAccess = VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY;
10054	else
10055	{
10056	/** @todo How to distinguish between monitoring/trace vs other instructions
10057	* here? */
10058	enmAccess = VMXAPICACCESS_PHYSICAL_INSTR;
10059	}
10060
10061	/* For physical accesses the instruction length is undefined, we zero it for safety and consistency. */
10062	HmExitAux.Vmx.cbInstr = 0;
10063	}
10064
10065	/*
10066	* Raise the APIC-access VM-exit.
10067	*/
10068	LogFlowFunc(("Raising APIC-access VM-exit from #PF handler at offset %#x\n", offAccess));
10069	VMXVEXITINFO const ExitInfo
10070	= VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_APIC_ACCESS,
10071	RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
10072	\| RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess),
10073	HmExitAux.Vmx.cbInstr);
10074	VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_IDT(HmExitAux.Vmx.uIdtVectoringInfo,
10075	HmExitAux.Vmx.uIdtVectoringErrCode);
10076	VBOXSTRICTRC const rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
10077	return iemExecStatusCodeFiddling(pVCpu, rcStrict);
10078	}
10079
10080	/*
10081	* The access isn't intercepted, which means it needs to be virtualized.
10082	*
10083	* This requires emulating the instruction because we need the bytes being
10084	* read/written by the instruction not just the offset being accessed within
10085	* the APIC-access page (which we derive from the faulting address).
10086	*/
10087	LogFlowFunc(("Access at offset %#x not intercepted -> VINF_EM_RAW_EMULATE_INSTR\n", offAccess));
10088	return VINF_EM_RAW_EMULATE_INSTR;
10089	}
10090
10091	/** @todo This isn't ideal but works for now as nested-hypervisors generally play
10092	* nice because the spec states that this page should be modified only when
10093	* no CPU refers to it VMX non-root mode. Nonetheless, we could use an atomic
10094	* reference counter to ensure the aforementioned condition before
10095	* de-registering the page. */
10096	LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysPage));
10097	int const rc = PGMHandlerPhysicalDeregister(pVM, GCPhysPage);
10098	if (RT_FAILURE(rc))
10099	return rc;
10100
10101	return VINF_SUCCESS;
10102	}
10103	# endif /* !IN_RING3 */
10104
10105	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
10106

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp@ 102020

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