VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp@ 96748

Last change on this file since 96748 was 96407, checked in by vboxsync, 2 years ago

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1/* $Id: IEMAllCImplVmxInstr.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_IEM
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/iem.h>
35#include <VBox/vmm/cpum.h>
36#include <VBox/vmm/apic.h>
37#include <VBox/vmm/pgm.h>
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/hm.h>
40#include <VBox/vmm/gim.h>
41#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
42# include <VBox/vmm/hmvmxinline.h>
43#endif
44#include <VBox/vmm/tm.h>
45#include "IEMInternal.h"
46#include <VBox/vmm/vmcc.h>
47#include <VBox/log.h>
48#include <VBox/err.h>
49#include <VBox/param.h>
50#include <VBox/disopcode.h>
51#include <iprt/asm-math.h>
52#include <iprt/assert.h>
53#include <iprt/string.h>
54#include <iprt/x86.h>
55
56#include "IEMInline.h"
57
58
59/*********************************************************************************************************************************
60* Defined Constants And Macros *
61*********************************************************************************************************************************/
62#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
63/**
64 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
65 * relative offsets.
66 */
67# ifdef IEM_WITH_CODE_TLB /** @todo IEM TLB */
68# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { a_bModRm = 0; RT_NOREF(a_offModRm); } while (0)
69# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { a_bSib = 0; RT_NOREF(a_offSib); } while (0)
70# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
71# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
72# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
73# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
74# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
75# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
76# if 0
77# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
78# endif
79# else /* !IEM_WITH_CODE_TLB */
80# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
81 do \
82 { \
83 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
84 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
85 } while (0)
86
87# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
88
89# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
90 do \
91 { \
92 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
93 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
94 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
95 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
96 } while (0)
97
98# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
99 do \
100 { \
101 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
102 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
103 } while (0)
104
105# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
106 do \
107 { \
108 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
109 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
110 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
111 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
112 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
113 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
114 } while (0)
115
116# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
117 do \
118 { \
119 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
120 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
121 } while (0)
122
123# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
124 do \
125 { \
126 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
127 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
128 } while (0)
129
130# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
131 do \
132 { \
133 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
134 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
135 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
136 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
137 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
138 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
139 } while (0)
140# endif /* !IEM_WITH_CODE_TLB */
141
142/** Check for VMX instructions requiring to be in VMX operation.
143 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
144# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
145 do \
146 { \
147 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
148 { /* likely */ } \
149 else \
150 { \
151 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
152 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
153 return iemRaiseUndefinedOpcode(a_pVCpu); \
154 } \
155 } while (0)
156
157/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
158# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
159 do \
160 { \
161 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
162 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
163 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
164 return VERR_VMX_VMENTRY_FAILED; \
165 } while (0)
166
167/** Marks a VM-exit failure with a diagnostic reason and logs. */
168# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
169 do \
170 { \
171 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
172 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
173 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
174 } while (0)
175
176/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
177# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
178 do \
179 { \
180 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
181 return VERR_VMX_VMEXIT_FAILED; \
182 } while (0)
183
184
185/*********************************************************************************************************************************
186* Global Variables *
187*********************************************************************************************************************************/
188/** @todo NSTVMX: The following VM-exit intercepts are pending:
189 * VMX_EXIT_IO_SMI
190 * VMX_EXIT_SMI
191 * VMX_EXIT_GETSEC
192 * VMX_EXIT_RSM
193 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
194 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
195 * VMX_EXIT_RDRAND
196 * VMX_EXIT_VMFUNC
197 * VMX_EXIT_ENCLS
198 * VMX_EXIT_RDSEED
199 * VMX_EXIT_PML_FULL
200 * VMX_EXIT_XSAVES
201 * VMX_EXIT_XRSTORS
202 */
203/**
204 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
205 *
206 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
207 * second dimension is the Index, see VMXVMCSFIELD.
208 */
209uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
210{
211 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
212 {
213 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
214 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
215 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
216 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
217 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
218 /* 19-26 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
219 /* 27 */ UINT16_MAX,
220 },
221 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
222 {
223 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
224 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
225 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
227 },
228 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
233 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
234 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
235 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
236 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
237 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
238 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
239 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
240 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
241 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
242 /* 26-27 */ UINT16_MAX, UINT16_MAX
243 },
244 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
245 {
246 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
247 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
248 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
249 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
250 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
251 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
252 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
253 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
254 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
255 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
256 },
257 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
258 {
259 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
260 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
261 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
262 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
263 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
264 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
265 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
266 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
267 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
268 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
269 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
270 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
271 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
272 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
273 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
274 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
275 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
276 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
277 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
278 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
279 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
280 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
281 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
282 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
283 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
284 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
285 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
286 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap)
287 },
288 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
289 {
290 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
291 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
292 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
293 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
294 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
295 },
296 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
297 {
298 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
299 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
300 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
301 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
302 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
303 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
304 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
305 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
306 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
307 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
308 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
309 /* 11 */ UINT16_MAX,
310 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
311 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
312 /* 21-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
313 },
314 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
315 {
316 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
317 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
318 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
319 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
320 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
321 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
322 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
329 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
330 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
331 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
332 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
333 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
334 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
335 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
336 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
337 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
338 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
339 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
340 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
341 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
342 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
343 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
344 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
345 /* 26-27 */ UINT16_MAX, UINT16_MAX
346 },
347 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
348 {
349 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
350 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
351 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
352 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
353 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
354 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
355 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
356 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
357 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
358 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
359 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
360 },
361 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
362 {
363 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
364 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
365 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
366 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
367 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
368 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
369 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
370 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
371 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
372 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
373 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
374 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
375 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
376 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
377 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
378 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
379 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
380 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
381 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
382 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
383 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
384 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
385 /* 22 */ UINT16_MAX,
386 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
387 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
388 },
389 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
390 {
391 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
392 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
393 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
394 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
395 /* 25-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
396 },
397 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
398 {
399 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
400 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
401 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
402 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
403 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
404 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
405 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
406 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
407 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
408 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
409 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
410 },
411 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
412 {
413 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
414 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
415 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
416 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
417 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
418 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
419 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
420 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
421 /* 22-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
422 },
423 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
424 {
425 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
426 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
427 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
428 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
429 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
430 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
431 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
432 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
433 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
434 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
435 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
436 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
437 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
438 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
439 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
440 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
441 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
442 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
443 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
444 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
445 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
446 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
447 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
448 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
449 },
450 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
451 {
452 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
453 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
454 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
455 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
456 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
457 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
458 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
459 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
460 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
461 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
462 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
463 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
464 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
465 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
466 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
467 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
468 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
469 }
470};
471
472
473/**
474 * Gets a host selector from the VMCS.
475 *
476 * @param pVmcs Pointer to the virtual VMCS.
477 * @param iSelReg The index of the segment register (X86_SREG_XXX).
478 */
479DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
480{
481 Assert(iSegReg < X86_SREG_COUNT);
482 RTSEL HostSel;
483 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
484 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
485 uint8_t const uWidthType = (uWidth << 2) | uType;
486 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
487 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
488 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
489 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
490 uint8_t const *pbField = pbVmcs + offField;
491 HostSel = *(uint16_t *)pbField;
492 return HostSel;
493}
494
495
496/**
497 * Sets a guest segment register in the VMCS.
498 *
499 * @param pVmcs Pointer to the virtual VMCS.
500 * @param iSegReg The index of the segment register (X86_SREG_XXX).
501 * @param pSelReg Pointer to the segment register.
502 */
503static void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg) RT_NOEXCEPT
504{
505 Assert(pSelReg);
506 Assert(iSegReg < X86_SREG_COUNT);
507
508 /* Selector. */
509 {
510 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
511 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
512 uint8_t const uWidthType = (uWidth << 2) | uType;
513 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
514 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
515 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
516 uint8_t *pbVmcs = (uint8_t *)pVmcs;
517 uint8_t *pbField = pbVmcs + offField;
518 *(uint16_t *)pbField = pSelReg->Sel;
519 }
520
521 /* Limit. */
522 {
523 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
524 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
525 uint8_t const uWidthType = (uWidth << 2) | uType;
526 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
527 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
528 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
529 uint8_t *pbVmcs = (uint8_t *)pVmcs;
530 uint8_t *pbField = pbVmcs + offField;
531 *(uint32_t *)pbField = pSelReg->u32Limit;
532 }
533
534 /* Base. */
535 {
536 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
537 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
538 uint8_t const uWidthType = (uWidth << 2) | uType;
539 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
540 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
541 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
542 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
543 uint8_t const *pbField = pbVmcs + offField;
544 *(uint64_t *)pbField = pSelReg->u64Base;
545 }
546
547 /* Attributes. */
548 {
549 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
550 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
551 | X86DESCATTR_UNUSABLE;
552 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
553 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
554 uint8_t const uWidthType = (uWidth << 2) | uType;
555 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
556 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
557 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
558 uint8_t *pbVmcs = (uint8_t *)pVmcs;
559 uint8_t *pbField = pbVmcs + offField;
560 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
561 }
562}
563
564
565/**
566 * Gets a guest segment register from the VMCS.
567 *
568 * @returns VBox status code.
569 * @param pVmcs Pointer to the virtual VMCS.
570 * @param iSegReg The index of the segment register (X86_SREG_XXX).
571 * @param pSelReg Where to store the segment register (only updated when
572 * VINF_SUCCESS is returned).
573 *
574 * @remarks Warning! This does not validate the contents of the retrieved segment
575 * register.
576 */
577static int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg) RT_NOEXCEPT
578{
579 Assert(pSelReg);
580 Assert(iSegReg < X86_SREG_COUNT);
581
582 /* Selector. */
583 uint16_t u16Sel;
584 {
585 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
586 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
587 uint8_t const uWidthType = (uWidth << 2) | uType;
588 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
589 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
590 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
591 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
592 uint8_t const *pbField = pbVmcs + offField;
593 u16Sel = *(uint16_t *)pbField;
594 }
595
596 /* Limit. */
597 uint32_t u32Limit;
598 {
599 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
600 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
601 uint8_t const uWidthType = (uWidth << 2) | uType;
602 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
603 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
604 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
605 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
606 uint8_t const *pbField = pbVmcs + offField;
607 u32Limit = *(uint32_t *)pbField;
608 }
609
610 /* Base. */
611 uint64_t u64Base;
612 {
613 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
614 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
615 uint8_t const uWidthType = (uWidth << 2) | uType;
616 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
617 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
618 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
619 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
620 uint8_t const *pbField = pbVmcs + offField;
621 u64Base = *(uint64_t *)pbField;
622 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
623 }
624
625 /* Attributes. */
626 uint32_t u32Attr;
627 {
628 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
629 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
630 uint8_t const uWidthType = (uWidth << 2) | uType;
631 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
632 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
633 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
634 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
635 uint8_t const *pbField = pbVmcs + offField;
636 u32Attr = *(uint32_t *)pbField;
637 }
638
639 pSelReg->Sel = u16Sel;
640 pSelReg->ValidSel = u16Sel;
641 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
642 pSelReg->u32Limit = u32Limit;
643 pSelReg->u64Base = u64Base;
644 pSelReg->Attr.u = u32Attr;
645 return VINF_SUCCESS;
646}
647
648
649/**
650 * Converts an IEM exception event type to a VMX event type.
651 *
652 * @returns The VMX event type.
653 * @param uVector The interrupt / exception vector.
654 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
655 */
656DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
657{
658 /* Paranoia (callers may use these interchangeably). */
659 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
660 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
661 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
662 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
663 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
664 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
665 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
666 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
667 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
668 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
669 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
670 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
671
672 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
673 {
674 if (uVector == X86_XCPT_NMI)
675 return VMX_EXIT_INT_INFO_TYPE_NMI;
676 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
677 }
678
679 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
680 {
681 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
682 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
683 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
684 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
685 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
686 }
687
688 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
689 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
690}
691
692
693/**
694 * Determines whether the guest is using PAE paging given the VMCS.
695 *
696 * @returns @c true if PAE paging mode is used, @c false otherwise.
697 * @param pVmcs Pointer to the virtual VMCS.
698 */
699DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
700{
701 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
702 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
703 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
704}
705
706
707/**
708 * Sets the Exit qualification VMCS field.
709 *
710 * @param pVCpu The cross context virtual CPU structure.
711 * @param u64ExitQual The Exit qualification.
712 */
713DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
714{
715 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
716}
717
718
719/**
720 * Sets the VM-exit interruption information field.
721 *
722 * @param pVCpu The cross context virtual CPU structure.
723 * @param uExitIntInfo The VM-exit interruption information.
724 */
725DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
726{
727 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
728}
729
730
731/**
732 * Sets the VM-exit interruption error code.
733 *
734 * @param pVCpu The cross context virtual CPU structure.
735 * @param uErrCode The error code.
736 */
737DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
738{
739 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
740}
741
742
743/**
744 * Sets the IDT-vectoring information field.
745 *
746 * @param pVCpu The cross context virtual CPU structure.
747 * @param uIdtVectorInfo The IDT-vectoring information.
748 */
749DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
750{
751 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
752}
753
754
755/**
756 * Sets the IDT-vectoring error code field.
757 *
758 * @param pVCpu The cross context virtual CPU structure.
759 * @param uErrCode The error code.
760 */
761DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
762{
763 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
764}
765
766
767/**
768 * Sets the VM-exit guest-linear address VMCS field.
769 *
770 * @param pVCpu The cross context virtual CPU structure.
771 * @param uGuestLinearAddr The VM-exit guest-linear address.
772 */
773DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
774{
775 /* Bits 63:32 of guest-linear address MBZ if the guest isn't in long mode prior to the VM-exit. */
776 Assert(CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)) || !(uGuestLinearAddr & UINT64_C(0xffffffff00000000)));
777 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
778}
779
780
781/**
782 * Sets the VM-exit guest-physical address VMCS field.
783 *
784 * @param pVCpu The cross context virtual CPU structure.
785 * @param uGuestPhysAddr The VM-exit guest-physical address.
786 */
787DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
788{
789 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
790}
791
792
793/**
794 * Sets the VM-exit instruction length VMCS field.
795 *
796 * @param pVCpu The cross context virtual CPU structure.
797 * @param cbInstr The VM-exit instruction length in bytes.
798 *
799 * @remarks Callers may clear this field to 0. Hence, this function does not check
800 * the validity of the instruction length.
801 */
802DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
803{
804 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
805}
806
807
808/**
809 * Sets the VM-exit instruction info. VMCS field.
810 *
811 * @param pVCpu The cross context virtual CPU structure.
812 * @param uExitInstrInfo The VM-exit instruction information.
813 */
814DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
815{
816 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
817}
818
819
820/**
821 * Sets the guest pending-debug exceptions field.
822 *
823 * @param pVCpu The cross context virtual CPU structure.
824 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
825 */
826DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
827{
828 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
829 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
830}
831
832
833/**
834 * Implements VMSucceed for VMX instruction success.
835 *
836 * @param pVCpu The cross context virtual CPU structure.
837 */
838DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
839{
840 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
841}
842
843
844/**
845 * Implements VMFailInvalid for VMX instruction failure.
846 *
847 * @param pVCpu The cross context virtual CPU structure.
848 */
849DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
850{
851 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
852}
853
854
855/**
856 * Implements VMFail for VMX instruction failure.
857 *
858 * @param pVCpu The cross context virtual CPU structure.
859 * @param enmInsErr The VM instruction error.
860 */
861DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
862{
863 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
864}
865
866
867/**
868 * Checks if the given auto-load/store MSR area count is valid for the
869 * implementation.
870 *
871 * @returns @c true if it's within the valid limit, @c false otherwise.
872 * @param pVCpu The cross context virtual CPU structure.
873 * @param uMsrCount The MSR area count to check.
874 */
875DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
876{
877 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
878 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
879 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
880 if (uMsrCount <= cMaxSupportedMsrs)
881 return true;
882 return false;
883}
884
885
886/**
887 * Flushes the current VMCS contents back to guest memory.
888 *
889 * @returns VBox status code.
890 * @param pVCpu The cross context virtual CPU structure.
891 */
892DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
893{
894 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
895 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
896 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
897 return rc;
898}
899
900
901/**
902 * Populates the current VMCS contents from guest memory.
903 *
904 * @returns VBox status code.
905 * @param pVCpu The cross context virtual CPU structure.
906 */
907DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
908{
909 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
910 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
911 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
912 return rc;
913}
914
915
916/**
917 * Gets the instruction diagnostic for segment base checks during VM-entry of a
918 * nested-guest.
919 *
920 * @param iSegReg The segment index (X86_SREG_XXX).
921 */
922static VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg) RT_NOEXCEPT
923{
924 switch (iSegReg)
925 {
926 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
927 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
928 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
929 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
930 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
931 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
932 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
933 }
934}
935
936
937/**
938 * Gets the instruction diagnostic for segment base checks during VM-entry of a
939 * nested-guest that is in Virtual-8086 mode.
940 *
941 * @param iSegReg The segment index (X86_SREG_XXX).
942 */
943static VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg) RT_NOEXCEPT
944{
945 switch (iSegReg)
946 {
947 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
948 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
949 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
950 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
951 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
952 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
953 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
954 }
955}
956
957
958/**
959 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
960 * nested-guest that is in Virtual-8086 mode.
961 *
962 * @param iSegReg The segment index (X86_SREG_XXX).
963 */
964static VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg) RT_NOEXCEPT
965{
966 switch (iSegReg)
967 {
968 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
969 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
970 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
971 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
972 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
973 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
974 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
975 }
976}
977
978
979/**
980 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
981 * nested-guest that is in Virtual-8086 mode.
982 *
983 * @param iSegReg The segment index (X86_SREG_XXX).
984 */
985static VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg) RT_NOEXCEPT
986{
987 switch (iSegReg)
988 {
989 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
990 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
991 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
992 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
993 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
994 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
995 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
996 }
997}
998
999
1000/**
1001 * Gets the instruction diagnostic for segment attributes reserved bits failure
1002 * during VM-entry of a nested-guest.
1003 *
1004 * @param iSegReg The segment index (X86_SREG_XXX).
1005 */
1006static VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg) RT_NOEXCEPT
1007{
1008 switch (iSegReg)
1009 {
1010 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1011 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1012 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1013 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1014 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1015 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1016 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1017 }
1018}
1019
1020
1021/**
1022 * Gets the instruction diagnostic for segment attributes descriptor-type
1023 * (code/segment or system) failure during VM-entry of a nested-guest.
1024 *
1025 * @param iSegReg The segment index (X86_SREG_XXX).
1026 */
1027static VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg) RT_NOEXCEPT
1028{
1029 switch (iSegReg)
1030 {
1031 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1032 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1033 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1034 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1035 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1036 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1037 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1038 }
1039}
1040
1041
1042/**
1043 * Gets the instruction diagnostic for segment attributes descriptor-type
1044 * (code/segment or system) failure during VM-entry of a nested-guest.
1045 *
1046 * @param iSegReg The segment index (X86_SREG_XXX).
1047 */
1048static VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg) RT_NOEXCEPT
1049{
1050 switch (iSegReg)
1051 {
1052 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1053 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1054 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1055 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1056 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1057 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1058 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1059 }
1060}
1061
1062
1063/**
1064 * Gets the instruction diagnostic for segment attribute granularity failure during
1065 * VM-entry of a nested-guest.
1066 *
1067 * @param iSegReg The segment index (X86_SREG_XXX).
1068 */
1069static VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg) RT_NOEXCEPT
1070{
1071 switch (iSegReg)
1072 {
1073 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1074 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1075 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1076 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1077 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1078 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1079 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1080 }
1081}
1082
1083/**
1084 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1085 * VM-entry of a nested-guest.
1086 *
1087 * @param iSegReg The segment index (X86_SREG_XXX).
1088 */
1089static VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg) RT_NOEXCEPT
1090{
1091 switch (iSegReg)
1092 {
1093 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1094 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1095 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1096 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1097 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1098 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1099 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1100 }
1101}
1102
1103
1104/**
1105 * Gets the instruction diagnostic for segment attribute type accessed failure
1106 * during VM-entry of a nested-guest.
1107 *
1108 * @param iSegReg The segment index (X86_SREG_XXX).
1109 */
1110static VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg) RT_NOEXCEPT
1111{
1112 switch (iSegReg)
1113 {
1114 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1115 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1116 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1117 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1118 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1119 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1120 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1121 }
1122}
1123
1124
1125/**
1126 * Saves the guest control registers, debug registers and some MSRs are part of
1127 * VM-exit.
1128 *
1129 * @param pVCpu The cross context virtual CPU structure.
1130 */
1131static void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1132{
1133 /*
1134 * Saves the guest control registers, debug registers and some MSRs.
1135 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1136 */
1137 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1138
1139 /* Save control registers. */
1140 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1141 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1142 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1143
1144 /* Save SYSENTER CS, ESP, EIP. */
1145 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1146 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1147 {
1148 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1149 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1150 }
1151 else
1152 {
1153 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1154 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1155 }
1156
1157 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1158 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1159 {
1160 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1161 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1162 }
1163
1164 /* Save PAT MSR. */
1165 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1166 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1167
1168 /* Save EFER MSR. */
1169 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1170 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1171
1172 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1173 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1174
1175 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1176}
1177
1178
1179/**
1180 * Saves the guest force-flags in preparation of entering the nested-guest.
1181 *
1182 * @param pVCpu The cross context virtual CPU structure.
1183 */
1184static void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1185{
1186 /* We shouldn't be called multiple times during VM-entry. */
1187 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1188
1189 /* MTF should not be set outside VMX non-root mode. */
1190 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1191
1192 /*
1193 * Preserve the required force-flags.
1194 *
1195 * We cache and clear force-flags that would affect the execution of the
1196 * nested-guest. Cached flags are then restored while returning to the guest
1197 * if necessary.
1198 *
1199 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1200 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1201 * instruction. Interrupt inhibition for any nested-guest instruction
1202 * is supplied by the guest-interruptibility state VMCS field and will
1203 * be set up as part of loading the guest state.
1204 *
1205 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1206 * successful VM-entry (due to invalid guest-state) need to continue
1207 * blocking NMIs if it was in effect before VM-entry.
1208 *
1209 * - MTF need not be preserved as it's used only in VMX non-root mode and
1210 * is supplied through the VM-execution controls.
1211 *
1212 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1213 * we will be able to generate interrupts that may cause VM-exits for
1214 * the nested-guest.
1215 */
1216 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1217}
1218
1219
1220/**
1221 * Restores the guest force-flags in preparation of exiting the nested-guest.
1222 *
1223 * @param pVCpu The cross context virtual CPU structure.
1224 */
1225static void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1226{
1227 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1228 {
1229 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1230 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1231 }
1232}
1233
1234
1235/**
1236 * Performs the VMX transition to/from VMX non-root mode.
1237 *
1238 * @param pVCpu The cross context virtual CPU structure.
1239*/
1240static int iemVmxTransition(PVMCPUCC pVCpu) RT_NOEXCEPT
1241{
1242 /*
1243 * Inform PGM about paging mode changes.
1244 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1245 * see comment in iemMemPageTranslateAndCheckAccess().
1246 */
1247 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1248 true /* fForce */);
1249 AssertRCReturn(rc, rc);
1250
1251 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1252 IEMTlbInvalidateAll(pVCpu);
1253
1254 /* Inform CPUM (recompiler), can later be removed. */
1255 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1256
1257 /* Re-initialize IEM cache/state after the drastic mode switch. */
1258 iemReInitExec(pVCpu);
1259 return rc;
1260}
1261
1262
1263/**
1264 * Calculates the current VMX-preemption timer value.
1265 *
1266 * @returns The current VMX-preemption timer value.
1267 * @param pVCpu The cross context virtual CPU structure.
1268 */
1269static uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
1270{
1271 /*
1272 * Assume the following:
1273 * PreemptTimerShift = 5
1274 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1275 * EntryTick = 50000 (TSC at time of VM-entry)
1276 *
1277 * CurTick Delta PreemptTimerVal
1278 * ----------------------------------
1279 * 60000 10000 2
1280 * 80000 30000 1
1281 * 90000 40000 0 -> VM-exit.
1282 *
1283 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1284 * The saved VMX-preemption timer value is calculated as follows:
1285 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1286 * E.g.:
1287 * Delta = 10000
1288 * Tmp = 10000 / (2 * 10000) = 0.5
1289 * NewPt = 2 - 0.5 = 2
1290 * Delta = 30000
1291 * Tmp = 30000 / (2 * 10000) = 1.5
1292 * NewPt = 2 - 1.5 = 1
1293 * Delta = 40000
1294 * Tmp = 40000 / 20000 = 2
1295 * NewPt = 2 - 2 = 0
1296 */
1297 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1298 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1299 if (uVmcsPreemptVal > 0)
1300 {
1301 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1302 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1303 uint64_t const uDelta = uCurTick - uEntryTick;
1304 uint32_t const uPreemptTimer = uVmcsPreemptVal
1305 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1306 return uPreemptTimer;
1307 }
1308 return 0;
1309}
1310
1311
1312/**
1313 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1314 *
1315 * @param pVCpu The cross context virtual CPU structure.
1316 */
1317static void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1318{
1319 /*
1320 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1321 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1322 */
1323 /* CS, SS, ES, DS, FS, GS. */
1324 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1325 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1326 {
1327 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1328 if (!pSelReg->Attr.n.u1Unusable)
1329 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1330 else
1331 {
1332 /*
1333 * For unusable segments the attributes are undefined except for CS and SS.
1334 * For the rest we don't bother preserving anything but the unusable bit.
1335 */
1336 switch (iSegReg)
1337 {
1338 case X86_SREG_CS:
1339 pVmcs->GuestCs = pSelReg->Sel;
1340 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1341 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1342 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1343 | X86DESCATTR_UNUSABLE);
1344 break;
1345
1346 case X86_SREG_SS:
1347 pVmcs->GuestSs = pSelReg->Sel;
1348 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1349 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1350 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1351 break;
1352
1353 case X86_SREG_DS:
1354 pVmcs->GuestDs = pSelReg->Sel;
1355 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1356 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1357 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1358 break;
1359
1360 case X86_SREG_ES:
1361 pVmcs->GuestEs = pSelReg->Sel;
1362 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1363 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1364 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1365 break;
1366
1367 case X86_SREG_FS:
1368 pVmcs->GuestFs = pSelReg->Sel;
1369 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1370 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1371 break;
1372
1373 case X86_SREG_GS:
1374 pVmcs->GuestGs = pSelReg->Sel;
1375 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1376 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1377 break;
1378 }
1379 }
1380 }
1381
1382 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1383 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1384 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1385 | X86DESCATTR_UNUSABLE;
1386 /* LDTR. */
1387 {
1388 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1389 pVmcs->GuestLdtr = pSelReg->Sel;
1390 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1391 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1392 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1393 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1394 }
1395
1396 /* TR. */
1397 {
1398 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1399 pVmcs->GuestTr = pSelReg->Sel;
1400 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1401 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1402 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1403 }
1404
1405 /* GDTR. */
1406 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1407 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1408
1409 /* IDTR. */
1410 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1411 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1412}
1413
1414
1415/**
1416 * Saves guest non-register state as part of VM-exit.
1417 *
1418 * @param pVCpu The cross context virtual CPU structure.
1419 * @param uExitReason The VM-exit reason.
1420 */
1421static void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1422{
1423 /*
1424 * Save guest non-register state.
1425 * See Intel spec. 27.3.4 "Saving Non-Register State".
1426 */
1427 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1428
1429 /*
1430 * Activity state.
1431 * Most VM-exits will occur in the active state. However, if the first instruction
1432 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1433 * the VM-exit will be from the HLT activity state.
1434 *
1435 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1436 */
1437 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1438 * not? */
1439 EMSTATE const enmActivityState = EMGetState(pVCpu);
1440 switch (enmActivityState)
1441 {
1442 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1443 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1444 }
1445
1446 /*
1447 * Interruptibility-state.
1448 */
1449 /* NMI. */
1450 pVmcs->u32GuestIntrState = 0;
1451 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1452 {
1453 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1454 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1455 }
1456 else
1457 {
1458 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1459 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1460 }
1461
1462 /* Blocking-by-STI. */
1463 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1464 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1465 {
1466 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1467 * currently. */
1468 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1469 }
1470 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1471
1472 /*
1473 * Pending debug exceptions.
1474 *
1475 * For VM-exits where it is not applicable, we can safely zero out the field.
1476 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1477 */
1478 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1479 && uExitReason != VMX_EXIT_SMI
1480 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1481 && !VMXIsVmexitTrapLike(uExitReason))
1482 {
1483 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1484 * block-by-MovSS is in effect. */
1485 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1486 }
1487
1488 /*
1489 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1490 *
1491 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1492 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1493 */
1494 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1495 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1496 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1497
1498 /*
1499 * PAE PDPTEs.
1500 *
1501 * If EPT is enabled and PAE paging was used at the time of the VM-exit,
1502 * the PDPTEs are saved from the VMCS. Otherwise they're undefined but
1503 * we zero them for consistency.
1504 */
1505 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1506 {
1507 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
1508 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
1509 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG))
1510 {
1511 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1512 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1513 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1514 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1515 }
1516 else
1517 {
1518 pVmcs->u64GuestPdpte0.u = 0;
1519 pVmcs->u64GuestPdpte1.u = 0;
1520 pVmcs->u64GuestPdpte2.u = 0;
1521 pVmcs->u64GuestPdpte3.u = 0;
1522 }
1523
1524 /* Clear PGM's copy of the EPT pointer for added safety. */
1525 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1526 }
1527 else
1528 {
1529 pVmcs->u64GuestPdpte0.u = 0;
1530 pVmcs->u64GuestPdpte1.u = 0;
1531 pVmcs->u64GuestPdpte2.u = 0;
1532 pVmcs->u64GuestPdpte3.u = 0;
1533 }
1534}
1535
1536
1537/**
1538 * Saves the guest-state as part of VM-exit.
1539 *
1540 * @returns VBox status code.
1541 * @param pVCpu The cross context virtual CPU structure.
1542 * @param uExitReason The VM-exit reason.
1543 */
1544static void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1545{
1546 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1547 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1548
1549 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1550 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1551 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1552
1553 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1554}
1555
1556
1557/**
1558 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1559 *
1560 * @returns VBox status code.
1561 * @param pVCpu The cross context virtual CPU structure.
1562 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1563 */
1564static int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1565{
1566 /*
1567 * Save guest MSRs.
1568 * See Intel spec. 27.4 "Saving MSRs".
1569 */
1570 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1571 const char * const pszFailure = "VMX-abort";
1572
1573 /*
1574 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1575 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1576 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1577 */
1578 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1579 if (!cMsrs)
1580 return VINF_SUCCESS;
1581
1582 /*
1583 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1584 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1585 * implementation causes a VMX-abort followed by a triple-fault.
1586 */
1587 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1588 if (fIsMsrCountValid)
1589 { /* likely */ }
1590 else
1591 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1592
1593 /*
1594 * Optimization if the nested hypervisor is using the same guest-physical page for both
1595 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1596 */
1597 PVMXAUTOMSR pMsrArea;
1598 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1599 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1600 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1601 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1602 else
1603 {
1604 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1605 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1606 if (RT_SUCCESS(rc))
1607 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1608 else
1609 {
1610 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1611 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1612 }
1613 }
1614
1615 /*
1616 * Update VM-exit MSR store area.
1617 */
1618 PVMXAUTOMSR pMsr = pMsrArea;
1619 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1620 {
1621 if ( !pMsr->u32Reserved
1622 && pMsr->u32Msr != MSR_IA32_SMBASE
1623 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1624 {
1625 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1626 if (rcStrict == VINF_SUCCESS)
1627 continue;
1628
1629 /*
1630 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1631 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1632 * recording the MSR index in the auxiliary info. field and indicated further by our
1633 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1634 * if possible, or come up with a better, generic solution.
1635 */
1636 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1637 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1638 ? kVmxVDiag_Vmexit_MsrStoreRing3
1639 : kVmxVDiag_Vmexit_MsrStore;
1640 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1641 }
1642 else
1643 {
1644 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1645 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1646 }
1647 }
1648
1649 /*
1650 * Commit the VM-exit MSR store are to guest memory.
1651 */
1652 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1653 if (RT_SUCCESS(rc))
1654 return VINF_SUCCESS;
1655
1656 NOREF(uExitReason);
1657 NOREF(pszFailure);
1658
1659 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1660 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1661}
1662
1663
1664/**
1665 * Performs a VMX abort (due to an fatal error during VM-exit).
1666 *
1667 * @returns Strict VBox status code.
1668 * @param pVCpu The cross context virtual CPU structure.
1669 * @param enmAbort The VMX abort reason.
1670 */
1671static VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort) RT_NOEXCEPT
1672{
1673 /*
1674 * Perform the VMX abort.
1675 * See Intel spec. 27.7 "VMX Aborts".
1676 */
1677 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1678
1679 /* We don't support SMX yet. */
1680 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1681 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1682 {
1683 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1684 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1685 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1686 }
1687
1688 return VINF_EM_TRIPLE_FAULT;
1689}
1690
1691
1692/**
1693 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1694 *
1695 * @param pVCpu The cross context virtual CPU structure.
1696 */
1697static void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1698{
1699 /*
1700 * Load host control registers, debug registers and MSRs.
1701 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1702 */
1703 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1704 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1705
1706 /* CR0. */
1707 {
1708 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1709 uint64_t const uCr0Mb1 = iemVmxGetCr0Fixed0(pVCpu);
1710 uint64_t const uCr0Mb0 = VMX_V_CR0_FIXED1;
1711 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK | uCr0Mb1 | ~uCr0Mb0;
1712 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1713 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1714 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1715
1716 /* Verify we have not modified CR0 fixed bits in VMX non-root operation. */
1717 Assert((uGuestCr0 & uCr0Mb1) == uCr0Mb1);
1718 Assert((uGuestCr0 & ~uCr0Mb0) == 0);
1719 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1720 }
1721
1722 /* CR4. */
1723 {
1724 /* CR4 fixed bits are not modified. */
1725 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1726 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1727 uint64_t const fCr4IgnMask = uCr4Mb1 | ~uCr4Mb0;
1728 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1729 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
1730 uint64_t uValidHostCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
1731 if (fHostInLongMode)
1732 uValidHostCr4 |= X86_CR4_PAE;
1733 else
1734 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1735
1736 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1737 Assert((uGuestCr4 & uCr4Mb1) == uCr4Mb1);
1738 Assert((uGuestCr4 & ~uCr4Mb0) == 0);
1739 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1740 }
1741
1742 /* CR3 (host value validated while checking host-state during VM-entry). */
1743 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1744
1745 /* DR7. */
1746 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1747
1748 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1749
1750 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1751 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1752 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1753 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1754
1755 /* FS, GS bases are loaded later while we load host segment registers. */
1756
1757 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1758 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1759 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1760 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1761 {
1762 if (fHostInLongMode)
1763 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1764 else
1765 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1766 }
1767
1768 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1769
1770 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1771 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1772 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1773
1774 /* We don't support IA32_BNDCFGS MSR yet. */
1775}
1776
1777
1778/**
1779 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1780 *
1781 * @param pVCpu The cross context virtual CPU structure.
1782 */
1783static void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1784{
1785 /*
1786 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1787 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1788 *
1789 * Warning! Be careful to not touch fields that are reserved by VT-x,
1790 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1791 */
1792 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1793 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1794
1795 /* CS, SS, ES, DS, FS, GS. */
1796 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1797 {
1798 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1799 bool const fUnusable = RT_BOOL(HostSel == 0);
1800 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1801
1802 /* Selector. */
1803 pSelReg->Sel = HostSel;
1804 pSelReg->ValidSel = HostSel;
1805 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1806
1807 /* Limit. */
1808 pSelReg->u32Limit = 0xffffffff;
1809
1810 /* Base. */
1811 pSelReg->u64Base = 0;
1812
1813 /* Attributes. */
1814 if (iSegReg == X86_SREG_CS)
1815 {
1816 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1817 pSelReg->Attr.n.u1DescType = 1;
1818 pSelReg->Attr.n.u2Dpl = 0;
1819 pSelReg->Attr.n.u1Present = 1;
1820 pSelReg->Attr.n.u1Long = fHostInLongMode;
1821 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1822 pSelReg->Attr.n.u1Granularity = 1;
1823 Assert(!pSelReg->Attr.n.u1Unusable);
1824 Assert(!fUnusable);
1825 }
1826 else
1827 {
1828 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1829 pSelReg->Attr.n.u1DescType = 1;
1830 pSelReg->Attr.n.u2Dpl = 0;
1831 pSelReg->Attr.n.u1Present = 1;
1832 pSelReg->Attr.n.u1DefBig = 1;
1833 pSelReg->Attr.n.u1Granularity = 1;
1834 pSelReg->Attr.n.u1Unusable = fUnusable;
1835 }
1836 }
1837
1838 /* FS base. */
1839 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1840 || fHostInLongMode)
1841 {
1842 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1843 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1844 }
1845
1846 /* GS base. */
1847 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1848 || fHostInLongMode)
1849 {
1850 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1851 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1852 }
1853
1854 /* TR. */
1855 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1856 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1857 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1858 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1859 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1860 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1861 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1862 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1863 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1864 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1865 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1866 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1867 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1868
1869 /* LDTR (Warning! do not touch the base and limits here). */
1870 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1871 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1872 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1873 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1874
1875 /* GDTR. */
1876 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1877 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1878 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1879
1880 /* IDTR.*/
1881 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1882 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1883 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1884}
1885
1886
1887/**
1888 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1889 *
1890 * @returns VBox status code.
1891 * @param pVCpu The cross context virtual CPU structure.
1892 * @param uExitReason The VMX instruction name (for logging purposes).
1893 */
1894static int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1895{
1896 /*
1897 * Load host MSRs.
1898 * See Intel spec. 27.6 "Loading MSRs".
1899 */
1900 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1901 const char * const pszFailure = "VMX-abort";
1902
1903 /*
1904 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1905 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1906 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1907 */
1908 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1909 if (!cMsrs)
1910 return VINF_SUCCESS;
1911
1912 /*
1913 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1914 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1915 * implementation causes a VMX-abort followed by a triple-fault.
1916 */
1917 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1918 if (fIsMsrCountValid)
1919 { /* likely */ }
1920 else
1921 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1922
1923 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1924 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1925 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1926 if (RT_SUCCESS(rc))
1927 {
1928 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1929 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1930 {
1931 if ( !pMsr->u32Reserved
1932 && pMsr->u32Msr != MSR_K8_FS_BASE
1933 && pMsr->u32Msr != MSR_K8_GS_BASE
1934 && pMsr->u32Msr != MSR_K6_EFER
1935 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1936 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1937 {
1938 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1939 if (rcStrict == VINF_SUCCESS)
1940 continue;
1941
1942 /*
1943 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1944 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1945 * recording the MSR index in the auxiliary info. field and indicated further by our
1946 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1947 * if possible, or come up with a better, generic solution.
1948 */
1949 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1950 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
1951 ? kVmxVDiag_Vmexit_MsrLoadRing3
1952 : kVmxVDiag_Vmexit_MsrLoad;
1953 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1954 }
1955 else
1956 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
1957 }
1958 }
1959 else
1960 {
1961 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
1962 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
1963 }
1964
1965 NOREF(uExitReason);
1966 NOREF(pszFailure);
1967 return VINF_SUCCESS;
1968}
1969
1970
1971/**
1972 * Loads the host state as part of VM-exit.
1973 *
1974 * @returns Strict VBox status code.
1975 * @param pVCpu The cross context virtual CPU structure.
1976 * @param uExitReason The VM-exit reason (for logging purposes).
1977 */
1978static VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1979{
1980 /*
1981 * Load host state.
1982 * See Intel spec. 27.5 "Loading Host State".
1983 */
1984 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1985 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1986
1987 /* We cannot return from a long-mode guest to a host that is not in long mode. */
1988 if ( CPUMIsGuestInLongMode(pVCpu)
1989 && !fHostInLongMode)
1990 {
1991 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
1992 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
1993 }
1994
1995 /*
1996 * Check host PAE PDPTEs prior to loading the host state.
1997 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
1998 */
1999 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2000 && !fHostInLongMode
2001 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2002 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2003 {
2004 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2005 if (RT_SUCCESS(rc))
2006 { /* likely*/ }
2007 else
2008 {
2009 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2010 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2011 }
2012 }
2013
2014 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2015 iemVmxVmexitLoadHostSegRegs(pVCpu);
2016
2017 /*
2018 * Load host RIP, RSP and RFLAGS.
2019 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2020 */
2021 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2022 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2023 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2024
2025 /* Clear address range monitoring. */
2026 EMMonitorWaitClear(pVCpu);
2027
2028 /* Perform the VMX transition (PGM updates). */
2029 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2030 if (rcStrict == VINF_SUCCESS)
2031 { /* likely */ }
2032 else if (RT_SUCCESS(rcStrict))
2033 {
2034 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2035 uExitReason));
2036 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2037 }
2038 else
2039 {
2040 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2041 return VBOXSTRICTRC_VAL(rcStrict);
2042 }
2043
2044 Assert(rcStrict == VINF_SUCCESS);
2045
2046 /* Load MSRs from the VM-exit auto-load MSR area. */
2047 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2048 if (RT_FAILURE(rc))
2049 {
2050 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2051 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2052 }
2053 return VINF_SUCCESS;
2054}
2055
2056
2057/**
2058 * Gets VM-exit instruction information along with any displacement for an
2059 * instruction VM-exit.
2060 *
2061 * @returns The VM-exit instruction information.
2062 * @param pVCpu The cross context virtual CPU structure.
2063 * @param uExitReason The VM-exit reason.
2064 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2065 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2066 * NULL.
2067 */
2068static uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp) RT_NOEXCEPT
2069{
2070 RTGCPTR GCPtrDisp;
2071 VMXEXITINSTRINFO ExitInstrInfo;
2072 ExitInstrInfo.u = 0;
2073
2074 /*
2075 * Get and parse the ModR/M byte from our decoded opcodes.
2076 */
2077 uint8_t bRm;
2078 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2079 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2080 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2081 {
2082 /*
2083 * ModR/M indicates register addressing.
2084 *
2085 * The primary/secondary register operands are reported in the iReg1 or iReg2
2086 * fields depending on whether it is a read/write form.
2087 */
2088 uint8_t idxReg1;
2089 uint8_t idxReg2;
2090 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2091 {
2092 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2093 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2094 }
2095 else
2096 {
2097 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2098 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2099 }
2100 ExitInstrInfo.All.u2Scaling = 0;
2101 ExitInstrInfo.All.iReg1 = idxReg1;
2102 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2103 ExitInstrInfo.All.fIsRegOperand = 1;
2104 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2105 ExitInstrInfo.All.iSegReg = 0;
2106 ExitInstrInfo.All.iIdxReg = 0;
2107 ExitInstrInfo.All.fIdxRegInvalid = 1;
2108 ExitInstrInfo.All.iBaseReg = 0;
2109 ExitInstrInfo.All.fBaseRegInvalid = 1;
2110 ExitInstrInfo.All.iReg2 = idxReg2;
2111
2112 /* Displacement not applicable for register addressing. */
2113 GCPtrDisp = 0;
2114 }
2115 else
2116 {
2117 /*
2118 * ModR/M indicates memory addressing.
2119 */
2120 uint8_t uScale = 0;
2121 bool fBaseRegValid = false;
2122 bool fIdxRegValid = false;
2123 uint8_t iBaseReg = 0;
2124 uint8_t iIdxReg = 0;
2125 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2126 {
2127 /*
2128 * Parse the ModR/M, displacement for 16-bit addressing mode.
2129 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2130 */
2131 uint16_t u16Disp = 0;
2132 uint8_t const offDisp = offModRm + sizeof(bRm);
2133 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2134 {
2135 /* Displacement without any registers. */
2136 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2137 }
2138 else
2139 {
2140 /* Register (index and base). */
2141 switch (bRm & X86_MODRM_RM_MASK)
2142 {
2143 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2144 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2145 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2146 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2147 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2148 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2149 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2150 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2151 }
2152
2153 /* Register + displacement. */
2154 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2155 {
2156 case 0: break;
2157 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2158 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2159 default:
2160 {
2161 /* Register addressing, handled at the beginning. */
2162 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2163 break;
2164 }
2165 }
2166 }
2167
2168 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2169 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2170 }
2171 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2172 {
2173 /*
2174 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2175 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2176 */
2177 uint32_t u32Disp = 0;
2178 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2179 {
2180 /* Displacement without any registers. */
2181 uint8_t const offDisp = offModRm + sizeof(bRm);
2182 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2183 }
2184 else
2185 {
2186 /* Register (and perhaps scale, index and base). */
2187 uint8_t offDisp = offModRm + sizeof(bRm);
2188 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2189 if (iBaseReg == 4)
2190 {
2191 /* An SIB byte follows the ModR/M byte, parse it. */
2192 uint8_t bSib;
2193 uint8_t const offSib = offModRm + sizeof(bRm);
2194 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2195
2196 /* A displacement may follow SIB, update its offset. */
2197 offDisp += sizeof(bSib);
2198
2199 /* Get the scale. */
2200 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2201
2202 /* Get the index register. */
2203 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2204 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2205
2206 /* Get the base register. */
2207 iBaseReg = bSib & X86_SIB_BASE_MASK;
2208 fBaseRegValid = true;
2209 if (iBaseReg == 5)
2210 {
2211 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2212 {
2213 /* Mod is 0 implies a 32-bit displacement with no base. */
2214 fBaseRegValid = false;
2215 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2216 }
2217 else
2218 {
2219 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2220 iBaseReg = X86_GREG_xBP;
2221 }
2222 }
2223 }
2224
2225 /* Register + displacement. */
2226 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2227 {
2228 case 0: /* Handled above */ break;
2229 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2230 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2231 default:
2232 {
2233 /* Register addressing, handled at the beginning. */
2234 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2235 break;
2236 }
2237 }
2238 }
2239
2240 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2241 }
2242 else
2243 {
2244 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2245
2246 /*
2247 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2248 * See Intel instruction spec. 2.2 "IA-32e Mode".
2249 */
2250 uint64_t u64Disp = 0;
2251 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2252 if (fRipRelativeAddr)
2253 {
2254 /*
2255 * RIP-relative addressing mode.
2256 *
2257 * The displacement is 32-bit signed implying an offset range of +/-2G.
2258 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2259 */
2260 uint8_t const offDisp = offModRm + sizeof(bRm);
2261 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2262 }
2263 else
2264 {
2265 uint8_t offDisp = offModRm + sizeof(bRm);
2266
2267 /*
2268 * Register (and perhaps scale, index and base).
2269 *
2270 * REX.B extends the most-significant bit of the base register. However, REX.B
2271 * is ignored while determining whether an SIB follows the opcode. Hence, we
2272 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2273 *
2274 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2275 */
2276 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2277 if (iBaseReg == 4)
2278 {
2279 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2280 uint8_t bSib;
2281 uint8_t const offSib = offModRm + sizeof(bRm);
2282 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2283
2284 /* Displacement may follow SIB, update its offset. */
2285 offDisp += sizeof(bSib);
2286
2287 /* Get the scale. */
2288 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2289
2290 /* Get the index. */
2291 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2292 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2293
2294 /* Get the base. */
2295 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2296 fBaseRegValid = true;
2297 if (iBaseReg == 5)
2298 {
2299 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2300 {
2301 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2302 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2303 }
2304 else
2305 {
2306 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2307 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2308 }
2309 }
2310 }
2311 iBaseReg |= pVCpu->iem.s.uRexB;
2312
2313 /* Register + displacement. */
2314 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2315 {
2316 case 0: /* Handled above */ break;
2317 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2318 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2319 default:
2320 {
2321 /* Register addressing, handled at the beginning. */
2322 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2323 break;
2324 }
2325 }
2326 }
2327
2328 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2329 }
2330
2331 /*
2332 * The primary or secondary register operand is reported in iReg2 depending
2333 * on whether the primary operand is in read/write form.
2334 */
2335 uint8_t idxReg2;
2336 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2337 {
2338 idxReg2 = bRm & X86_MODRM_RM_MASK;
2339 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2340 idxReg2 |= pVCpu->iem.s.uRexB;
2341 }
2342 else
2343 {
2344 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2345 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2346 idxReg2 |= pVCpu->iem.s.uRexReg;
2347 }
2348 ExitInstrInfo.All.u2Scaling = uScale;
2349 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2350 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2351 ExitInstrInfo.All.fIsRegOperand = 0;
2352 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2353 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2354 ExitInstrInfo.All.iIdxReg = iIdxReg;
2355 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2356 ExitInstrInfo.All.iBaseReg = iBaseReg;
2357 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2358 ExitInstrInfo.All.iReg2 = idxReg2;
2359 }
2360
2361 /*
2362 * Handle exceptions to the norm for certain instructions.
2363 * (e.g. some instructions convey an instruction identity in place of iReg2).
2364 */
2365 switch (uExitReason)
2366 {
2367 case VMX_EXIT_GDTR_IDTR_ACCESS:
2368 {
2369 Assert(VMXINSTRID_IS_VALID(uInstrId));
2370 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2371 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2372 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2373 break;
2374 }
2375
2376 case VMX_EXIT_LDTR_TR_ACCESS:
2377 {
2378 Assert(VMXINSTRID_IS_VALID(uInstrId));
2379 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2380 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2381 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2382 break;
2383 }
2384
2385 case VMX_EXIT_RDRAND:
2386 case VMX_EXIT_RDSEED:
2387 {
2388 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2389 break;
2390 }
2391 }
2392
2393 /* Update displacement and return the constructed VM-exit instruction information field. */
2394 if (pGCPtrDisp)
2395 *pGCPtrDisp = GCPtrDisp;
2396
2397 return ExitInstrInfo.u;
2398}
2399
2400
2401/**
2402 * VMX VM-exit handler.
2403 *
2404 * @returns Strict VBox status code.
2405 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2406 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2407 * triple-fault.
2408 *
2409 * @param pVCpu The cross context virtual CPU structure.
2410 * @param uExitReason The VM-exit reason.
2411 * @param u64ExitQual The Exit qualification.
2412 *
2413 * @remarks We need not necessarily have completed VM-entry before a VM-exit is
2414 * called. Failures during VM-entry can cause VM-exits as well, so we
2415 * -cannot- assert we're in VMX non-root mode here.
2416 */
2417VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT
2418{
2419# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2420 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2421 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2422 return VERR_IEM_IPE_7;
2423# else
2424 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2425
2426 /*
2427 * Import all the guest-CPU state.
2428 *
2429 * HM on returning to guest execution would have to reset up a whole lot of state
2430 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2431 * the state and flag reloading the entire state on re-entry. So import the entire
2432 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2433 */
2434 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2435
2436 /*
2437 * Ensure VM-entry interruption information valid bit is cleared.
2438 *
2439 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2440 * by invalid-guest state or machine-check exceptions) also clear this bit.
2441 *
2442 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2443 */
2444 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2445 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2446
2447 /*
2448 * Update the VM-exit reason and Exit qualification.
2449 * Other VMCS read-only data fields are expected to be updated by the caller already.
2450 */
2451 pVmcs->u32RoExitReason = uExitReason;
2452 pVmcs->u64RoExitQual.u = u64ExitQual;
2453
2454 LogFlow(("vmexit: reason=%u qual=%#RX64 cs:rip=%04x:%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", uExitReason,
2455 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2456 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4));
2457
2458 /*
2459 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2460 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2461 */
2462 {
2463 uint8_t uVector;
2464 uint32_t fFlags;
2465 uint32_t uErrCode;
2466 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2467 if (fInEventDelivery)
2468 {
2469 /*
2470 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2471 * caused by a triple-fault or the original event results in a double-fault that
2472 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2473 * original event information into the IDT-vectoring information fields.
2474 *
2475 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2476 */
2477 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2478 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2479 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2480 {
2481 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2482 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2483 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2484 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2485 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2486 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2487 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2488 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2489 LogFlow(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2490 pVCpu->cpum.GstCtx.cr2));
2491 }
2492 }
2493 }
2494
2495 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2496 Assert(pVmcs->u64RoIoRcx.u == 0);
2497 Assert(pVmcs->u64RoIoRsi.u == 0);
2498 Assert(pVmcs->u64RoIoRdi.u == 0);
2499 Assert(pVmcs->u64RoIoRip.u == 0);
2500
2501 /*
2502 * Save the guest state back into the VMCS.
2503 * We only need to save the state when the VM-entry was successful.
2504 */
2505 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2506 if (!fVmentryFailed)
2507 {
2508 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2509 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2510 {
2511 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2512 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2513 }
2514
2515 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2516 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2517
2518 /*
2519 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2520 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2521 *
2522 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2523 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2524 * as guest-CPU state would not been modified. Hence for now, we do this only when
2525 * the VM-entry succeeded.
2526 */
2527 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2528 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2529 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2530 {
2531 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2532 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2533 else
2534 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2535 }
2536
2537 /*
2538 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2539 * occurs in enclave mode/SMM which we don't support yet.
2540 *
2541 * If we ever add support for it, we can pass just the lower bits to the functions
2542 * below, till then an assert should suffice.
2543 */
2544 Assert(!RT_HI_U16(uExitReason));
2545
2546 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2547 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2548 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2549 if (RT_SUCCESS(rc))
2550 { /* likely */ }
2551 else
2552 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2553
2554 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2555 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2556 }
2557 else
2558 {
2559 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2560 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2561 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2562 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2563 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2564 }
2565
2566 /*
2567 * Stop any running VMX-preemption timer if necessary.
2568 */
2569 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2570 CPUMStopGuestVmxPremptTimer(pVCpu);
2571
2572 /*
2573 * Clear any pending VMX nested-guest force-flags.
2574 * These force-flags have no effect on (outer) guest execution and will
2575 * be re-evaluated and setup on the next nested-guest VM-entry.
2576 */
2577 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2578
2579 /*
2580 * We're no longer in nested-guest execution mode.
2581 *
2582 * It is important to do this prior to loading the host state because
2583 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2584 * second-level address translation while switching to host CR3.
2585 */
2586 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2587
2588 /* Restore the host (outer guest) state. */
2589 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2590 if (RT_SUCCESS(rcStrict))
2591 {
2592 Assert(rcStrict == VINF_SUCCESS);
2593 rcStrict = VINF_VMX_VMEXIT;
2594 }
2595 else
2596 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2597
2598 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
2599 {
2600 /* Notify HM that the current VMCS fields have been modified. */
2601 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2602
2603 /* Notify HM that we've completed the VM-exit. */
2604 HMNotifyVmxNstGstVmexit(pVCpu);
2605 }
2606
2607# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2608 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2609 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2610 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2611 if (rcSched != VINF_SUCCESS)
2612 iemSetPassUpStatus(pVCpu, rcSched);
2613# endif
2614 return rcStrict;
2615# endif
2616}
2617
2618
2619/**
2620 * VMX VM-exit handler for VM-exits due to instruction execution.
2621 *
2622 * This is intended for instructions where the caller provides all the relevant
2623 * VM-exit information.
2624 *
2625 * @returns Strict VBox status code.
2626 * @param pVCpu The cross context virtual CPU structure.
2627 * @param pExitInfo Pointer to the VM-exit information.
2628 */
2629static VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
2630{
2631 /*
2632 * For instructions where any of the following fields are not applicable:
2633 * - Exit qualification must be cleared.
2634 * - VM-exit instruction info. is undefined.
2635 * - Guest-linear address is undefined.
2636 * - Guest-physical address is undefined.
2637 *
2638 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2639 * instruction execution. For VM-exits that are not due to instruction execution this
2640 * field is undefined.
2641 *
2642 * In our implementation in IEM, all undefined fields are generally cleared. However,
2643 * if the caller supplies information (from say the physical CPU directly) it is
2644 * then possible that the undefined fields are not cleared.
2645 *
2646 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2647 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2648 */
2649 Assert(pExitInfo);
2650 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2651 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2652 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2653
2654 /* Update all the relevant fields from the VM-exit instruction information struct. */
2655 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2656 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2657 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2658 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2659
2660 /* Perform the VM-exit. */
2661 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2662}
2663
2664
2665/**
2666 * VMX VM-exit handler for VM-exits due to instruction execution.
2667 *
2668 * This is intended for instructions that only provide the VM-exit instruction
2669 * length.
2670 *
2671 * @param pVCpu The cross context virtual CPU structure.
2672 * @param uExitReason The VM-exit reason.
2673 * @param cbInstr The instruction length in bytes.
2674 */
2675VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT
2676{
2677 VMXVEXITINFO ExitInfo;
2678 RT_ZERO(ExitInfo);
2679 ExitInfo.uReason = uExitReason;
2680 ExitInfo.cbInstr = cbInstr;
2681
2682#ifdef VBOX_STRICT
2683 /*
2684 * To prevent us from shooting ourselves in the foot.
2685 * The follow instructions should convey more than just the instruction length.
2686 */
2687 switch (uExitReason)
2688 {
2689 case VMX_EXIT_INVEPT:
2690 case VMX_EXIT_INVPCID:
2691 case VMX_EXIT_INVVPID:
2692 case VMX_EXIT_LDTR_TR_ACCESS:
2693 case VMX_EXIT_GDTR_IDTR_ACCESS:
2694 case VMX_EXIT_VMCLEAR:
2695 case VMX_EXIT_VMPTRLD:
2696 case VMX_EXIT_VMPTRST:
2697 case VMX_EXIT_VMREAD:
2698 case VMX_EXIT_VMWRITE:
2699 case VMX_EXIT_VMXON:
2700 case VMX_EXIT_XRSTORS:
2701 case VMX_EXIT_XSAVES:
2702 case VMX_EXIT_RDRAND:
2703 case VMX_EXIT_RDSEED:
2704 case VMX_EXIT_IO_INSTR:
2705 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2706 break;
2707 }
2708#endif
2709
2710 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2711}
2712
2713
2714/**
2715 * Interface for HM and EM to emulate VM-exit due to a triple-fault.
2716 *
2717 * @returns Strict VBox status code.
2718 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2719 * @thread EMT(pVCpu)
2720 */
2721VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu)
2722{
2723 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
2724 Assert(!pVCpu->iem.s.cActiveMappings);
2725 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2726}
2727
2728
2729/**
2730 * Interface for HM and EM to emulate VM-exit due to startup-IPI (SIPI).
2731 *
2732 * @returns Strict VBox status code.
2733 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2734 * @param uVector The SIPI vector.
2735 * @thread EMT(pVCpu)
2736 */
2737VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector)
2738{
2739 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_SIPI, uVector);
2740 Assert(!pVCpu->iem.s.cActiveMappings);
2741 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2742}
2743
2744
2745/**
2746 * Interface for HM and EM to emulate a VM-exit.
2747 *
2748 * If a specialized version of a VM-exit handler exists, that must be used instead.
2749 *
2750 * @returns Strict VBox status code.
2751 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2752 * @param uExitReason The VM-exit reason.
2753 * @param u64ExitQual The Exit qualification.
2754 * @thread EMT(pVCpu)
2755 */
2756VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2757{
2758 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, uExitReason, u64ExitQual);
2759 Assert(!pVCpu->iem.s.cActiveMappings);
2760 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2761}
2762
2763
2764/**
2765 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2766 *
2767 * This is meant to be used for those instructions that VMX provides additional
2768 * decoding information beyond just the instruction length!
2769 *
2770 * @returns Strict VBox status code.
2771 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2772 * @param pExitInfo Pointer to the VM-exit information.
2773 * @thread EMT(pVCpu)
2774 */
2775VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2776{
2777 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
2778 Assert(!pVCpu->iem.s.cActiveMappings);
2779 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2780}
2781
2782
2783/**
2784 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2785 *
2786 * This is meant to be used for those instructions that VMX provides only the
2787 * instruction length.
2788 *
2789 * @returns Strict VBox status code.
2790 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2791 * @param pExitInfo Pointer to the VM-exit information.
2792 * @param cbInstr The instruction length in bytes.
2793 * @thread EMT(pVCpu)
2794 */
2795VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2796{
2797 VBOXSTRICTRC rcStrict = iemVmxVmexitInstr(pVCpu, uExitReason, cbInstr);
2798 Assert(!pVCpu->iem.s.cActiveMappings);
2799 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2800}
2801
2802
2803/**
2804 * VMX VM-exit handler for VM-exits due to instruction execution.
2805 *
2806 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2807 * instruction information and Exit qualification fields.
2808 *
2809 * @param pVCpu The cross context virtual CPU structure.
2810 * @param uExitReason The VM-exit reason.
2811 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2812 * @param cbInstr The instruction length in bytes.
2813 *
2814 * @remarks Do not use this for INS/OUTS instruction.
2815 */
2816VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT
2817{
2818 VMXVEXITINFO ExitInfo;
2819 RT_ZERO(ExitInfo);
2820 ExitInfo.uReason = uExitReason;
2821 ExitInfo.cbInstr = cbInstr;
2822
2823 /*
2824 * Update the Exit qualification field with displacement bytes.
2825 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2826 */
2827 switch (uExitReason)
2828 {
2829 case VMX_EXIT_INVEPT:
2830 case VMX_EXIT_INVPCID:
2831 case VMX_EXIT_INVVPID:
2832 case VMX_EXIT_LDTR_TR_ACCESS:
2833 case VMX_EXIT_GDTR_IDTR_ACCESS:
2834 case VMX_EXIT_VMCLEAR:
2835 case VMX_EXIT_VMPTRLD:
2836 case VMX_EXIT_VMPTRST:
2837 case VMX_EXIT_VMREAD:
2838 case VMX_EXIT_VMWRITE:
2839 case VMX_EXIT_VMXON:
2840 case VMX_EXIT_XRSTORS:
2841 case VMX_EXIT_XSAVES:
2842 case VMX_EXIT_RDRAND:
2843 case VMX_EXIT_RDSEED:
2844 {
2845 /* Construct the VM-exit instruction information. */
2846 RTGCPTR GCPtrDisp;
2847 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2848
2849 /* Update the VM-exit instruction information. */
2850 ExitInfo.InstrInfo.u = uInstrInfo;
2851
2852 /* Update the Exit qualification. */
2853 ExitInfo.u64Qual = GCPtrDisp;
2854 break;
2855 }
2856
2857 default:
2858 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2859 break;
2860 }
2861
2862 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2863}
2864
2865
2866/**
2867 * VMX VM-exit handler for VM-exits due to INVLPG.
2868 *
2869 * @returns Strict VBox status code.
2870 * @param pVCpu The cross context virtual CPU structure.
2871 * @param GCPtrPage The guest-linear address of the page being invalidated.
2872 * @param cbInstr The instruction length in bytes.
2873 */
2874VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT
2875{
2876 VMXVEXITINFO ExitInfo;
2877 RT_ZERO(ExitInfo);
2878 ExitInfo.uReason = VMX_EXIT_INVLPG;
2879 ExitInfo.cbInstr = cbInstr;
2880 ExitInfo.u64Qual = GCPtrPage;
2881 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2882
2883 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2884}
2885
2886
2887/**
2888 * VMX VM-exit handler for VM-exits due to LMSW.
2889 *
2890 * @returns Strict VBox status code.
2891 * @param pVCpu The cross context virtual CPU structure.
2892 * @param uGuestCr0 The current guest CR0.
2893 * @param pu16NewMsw The machine-status word specified in LMSW's source
2894 * operand. This will be updated depending on the VMX
2895 * guest/host CR0 mask if LMSW is not intercepted.
2896 * @param GCPtrEffDst The guest-linear address of the source operand in case
2897 * of a memory operand. For register operand, pass
2898 * NIL_RTGCPTR.
2899 * @param cbInstr The instruction length in bytes.
2900 */
2901VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
2902 RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT
2903{
2904 Assert(pu16NewMsw);
2905
2906 uint16_t const uNewMsw = *pu16NewMsw;
2907 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2908 {
2909 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2910
2911 VMXVEXITINFO ExitInfo;
2912 RT_ZERO(ExitInfo);
2913 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2914 ExitInfo.cbInstr = cbInstr;
2915
2916 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2917 if (fMemOperand)
2918 {
2919 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2920 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2921 }
2922
2923 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2924 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
2925 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2926 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw);
2927
2928 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2929 }
2930
2931 /*
2932 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2933 * CR0 guest/host mask must be left unmodified.
2934 *
2935 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2936 */
2937 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2938 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2939 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2940
2941 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2942}
2943
2944
2945/**
2946 * VMX VM-exit handler for VM-exits due to CLTS.
2947 *
2948 * @returns Strict VBox status code.
2949 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2950 * VM-exit but must not modify the guest CR0.TS bit.
2951 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2952 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2953 * CR0 fixed bits in VMX operation).
2954 * @param pVCpu The cross context virtual CPU structure.
2955 * @param cbInstr The instruction length in bytes.
2956 */
2957VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
2958{
2959 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2960 uint32_t const fReadShadow = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2961
2962 /*
2963 * If CR0.TS is owned by the host:
2964 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
2965 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
2966 * CLTS instruction completes without clearing CR0.TS.
2967 *
2968 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2969 */
2970 if (fGstHostMask & X86_CR0_TS)
2971 {
2972 if (fReadShadow & X86_CR0_TS)
2973 {
2974 Log2(("clts: Guest intercept -> VM-exit\n"));
2975
2976 VMXVEXITINFO ExitInfo;
2977 RT_ZERO(ExitInfo);
2978 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
2979 ExitInfo.cbInstr = cbInstr;
2980 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2981 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
2982 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2983 }
2984
2985 return VINF_VMX_MODIFIES_BEHAVIOR;
2986 }
2987
2988 /*
2989 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
2990 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
2991 */
2992 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2993}
2994
2995
2996/**
2997 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
2998 * (CR0/CR4 write).
2999 *
3000 * @returns Strict VBox status code.
3001 * @param pVCpu The cross context virtual CPU structure.
3002 * @param iCrReg The control register (either CR0 or CR4).
3003 * @param uGuestCrX The current guest CR0/CR4.
3004 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
3005 * VM-exit is caused.
3006 * @param iGReg The general register from which the CR0/CR4 value is being
3007 * loaded.
3008 * @param cbInstr The instruction length in bytes.
3009 */
3010VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX,
3011 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3012{
3013 Assert(puNewCrX);
3014 Assert(iCrReg == 0 || iCrReg == 4);
3015 Assert(iGReg < X86_GREG_COUNT);
3016
3017 uint64_t const uNewCrX = *puNewCrX;
3018 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3019 {
3020 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3021
3022 VMXVEXITINFO ExitInfo;
3023 RT_ZERO(ExitInfo);
3024 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3025 ExitInfo.cbInstr = cbInstr;
3026 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3027 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3028 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3029 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3030 }
3031
3032 /*
3033 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3034 * must not be modified the instruction.
3035 *
3036 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3037 */
3038 uint64_t uGuestCrX;
3039 uint64_t fGstHostMask;
3040 if (iCrReg == 0)
3041 {
3042 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3043 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3044 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3045 }
3046 else
3047 {
3048 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3049 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3050 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
3051 }
3052
3053 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3054 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3055}
3056
3057
3058/**
3059 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3060 *
3061 * @returns VBox strict status code.
3062 * @param pVCpu The cross context virtual CPU structure.
3063 * @param iGReg The general register to which the CR3 value is being stored.
3064 * @param cbInstr The instruction length in bytes.
3065 */
3066VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3067{
3068 Assert(iGReg < X86_GREG_COUNT);
3069 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3070
3071 /*
3072 * If the CR3-store exiting control is set, we must cause a VM-exit.
3073 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3074 */
3075 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3076 {
3077 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3078
3079 VMXVEXITINFO ExitInfo;
3080 RT_ZERO(ExitInfo);
3081 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3082 ExitInfo.cbInstr = cbInstr;
3083 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3084 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3085 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3086 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3087 }
3088
3089 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3090}
3091
3092
3093/**
3094 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3095 *
3096 * @returns VBox strict status code.
3097 * @param pVCpu The cross context virtual CPU structure.
3098 * @param uNewCr3 The new CR3 value.
3099 * @param iGReg The general register from which the CR3 value is being
3100 * loaded.
3101 * @param cbInstr The instruction length in bytes.
3102 */
3103VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3104{
3105 Assert(iGReg < X86_GREG_COUNT);
3106
3107 /*
3108 * If the CR3-load exiting control is set and the new CR3 value does not
3109 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3110 *
3111 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3112 */
3113 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3114 {
3115 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3116
3117 VMXVEXITINFO ExitInfo;
3118 RT_ZERO(ExitInfo);
3119 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3120 ExitInfo.cbInstr = cbInstr;
3121 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3122 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3123 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3124 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3125 }
3126
3127 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3128}
3129
3130
3131/**
3132 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3133 *
3134 * @returns VBox strict status code.
3135 * @param pVCpu The cross context virtual CPU structure.
3136 * @param iGReg The general register to which the CR8 value is being stored.
3137 * @param cbInstr The instruction length in bytes.
3138 */
3139VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3140{
3141 Assert(iGReg < X86_GREG_COUNT);
3142
3143 /*
3144 * If the CR8-store exiting control is set, we must cause a VM-exit.
3145 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3146 */
3147 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3148 {
3149 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3150
3151 VMXVEXITINFO ExitInfo;
3152 RT_ZERO(ExitInfo);
3153 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3154 ExitInfo.cbInstr = cbInstr;
3155 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3156 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3157 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3158 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3159 }
3160
3161 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3162}
3163
3164
3165/**
3166 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3167 *
3168 * @returns VBox strict status code.
3169 * @param pVCpu The cross context virtual CPU structure.
3170 * @param iGReg The general register from which the CR8 value is being
3171 * loaded.
3172 * @param cbInstr The instruction length in bytes.
3173 */
3174VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3175{
3176 Assert(iGReg < X86_GREG_COUNT);
3177
3178 /*
3179 * If the CR8-load exiting control is set, we must cause a VM-exit.
3180 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3181 */
3182 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3183 {
3184 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3185
3186 VMXVEXITINFO ExitInfo;
3187 RT_ZERO(ExitInfo);
3188 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3189 ExitInfo.cbInstr = cbInstr;
3190 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3191 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3192 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3193 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3194 }
3195
3196 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3197}
3198
3199
3200/**
3201 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3202 * GReg,DRx' (DRx read).
3203 *
3204 * @returns VBox strict status code.
3205 * @param pVCpu The cross context virtual CPU structure.
3206 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3207 * VMXINSTRID_MOV_FROM_DRX).
3208 * @param iDrReg The debug register being accessed.
3209 * @param iGReg The general register to/from which the DRx value is being
3210 * store/loaded.
3211 * @param cbInstr The instruction length in bytes.
3212 */
3213VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg,
3214 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3215{
3216 Assert(iDrReg <= 7);
3217 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3218 Assert(iGReg < X86_GREG_COUNT);
3219
3220 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3221 {
3222 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3223 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3224 VMXVEXITINFO ExitInfo;
3225 RT_ZERO(ExitInfo);
3226 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3227 ExitInfo.cbInstr = cbInstr;
3228 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3229 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3230 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3231 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3232 }
3233
3234 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3235}
3236
3237
3238/**
3239 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3240 *
3241 * @returns VBox strict status code.
3242 * @param pVCpu The cross context virtual CPU structure.
3243 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3244 * VMXINSTRID_IO_OUT).
3245 * @param u16Port The I/O port being accessed.
3246 * @param fImm Whether the I/O port was encoded using an immediate operand
3247 * or the implicit DX register.
3248 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3249 * @param cbInstr The instruction length in bytes.
3250 */
3251VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3252 bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT
3253{
3254 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3255 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3256
3257 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3258 if (fIntercept)
3259 {
3260 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3261 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3262 VMXVEXITINFO ExitInfo;
3263 RT_ZERO(ExitInfo);
3264 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3265 ExitInfo.cbInstr = cbInstr;
3266 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3267 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3268 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3269 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3270 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3271 }
3272
3273 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3274}
3275
3276
3277/**
3278 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3279 *
3280 * @returns VBox strict status code.
3281 * @param pVCpu The cross context virtual CPU structure.
3282 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3283 * VMXINSTRID_IO_OUTS).
3284 * @param u16Port The I/O port being accessed.
3285 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3286 * @param fRep Whether the instruction has a REP prefix or not.
3287 * @param ExitInstrInfo The VM-exit instruction info. field.
3288 * @param cbInstr The instruction length in bytes.
3289 */
3290VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3291 bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT
3292{
3293 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3294 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3295 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3296 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3297 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3298
3299 bool const fIntercept = CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess);
3300 if (fIntercept)
3301 {
3302 /*
3303 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3304 */
3305 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3306 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3307 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3308 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3309 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3310
3311 uint32_t uDirection;
3312 uint64_t uGuestLinearAddr;
3313 if (uInstrId == VMXINSTRID_IO_INS)
3314 {
3315 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3316 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3317 }
3318 else
3319 {
3320 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3321 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3322 }
3323
3324 /*
3325 * If the segment is unusable, the guest-linear address in undefined.
3326 * We shall clear it for consistency.
3327 *
3328 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3329 */
3330 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3331 uGuestLinearAddr = 0;
3332
3333 VMXVEXITINFO ExitInfo;
3334 RT_ZERO(ExitInfo);
3335 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3336 ExitInfo.cbInstr = cbInstr;
3337 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3338 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3339 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3340 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3341 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3342 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3343 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3344 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo)
3345 ExitInfo.InstrInfo = ExitInstrInfo;
3346 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3347 }
3348
3349 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3350}
3351
3352
3353/**
3354 * VMX VM-exit handler for VM-exits due to MWAIT.
3355 *
3356 * @returns VBox strict status code.
3357 * @param pVCpu The cross context virtual CPU structure.
3358 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3359 * @param cbInstr The instruction length in bytes.
3360 */
3361VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT
3362{
3363 VMXVEXITINFO ExitInfo;
3364 RT_ZERO(ExitInfo);
3365 ExitInfo.uReason = VMX_EXIT_MWAIT;
3366 ExitInfo.cbInstr = cbInstr;
3367 ExitInfo.u64Qual = fMonitorHwArmed;
3368 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3369}
3370
3371
3372/**
3373 * VMX VM-exit handler for VM-exits due to PAUSE.
3374 *
3375 * @returns VBox strict status code.
3376 * @param pVCpu The cross context virtual CPU structure.
3377 * @param cbInstr The instruction length in bytes.
3378 */
3379static VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3380{
3381 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3382
3383 /*
3384 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3385 * "PAUSE-loop exiting" control.
3386 *
3387 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3388 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3389 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3390 * a VM-exit.
3391 *
3392 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3393 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3394 */
3395 bool fIntercept = false;
3396 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3397 fIntercept = true;
3398 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3399 && pVCpu->iem.s.uCpl == 0)
3400 {
3401 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3402
3403 /*
3404 * A previous-PAUSE-tick value of 0 is used to identify the first time
3405 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3406 * consider this to be the first execution of PAUSE in a loop according
3407 * to the Intel.
3408 *
3409 * All subsequent records for the previous-PAUSE-tick we ensure that it
3410 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3411 */
3412 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3413 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3414 uint64_t const uTick = TMCpuTickGet(pVCpu);
3415 uint32_t const uPleGap = pVmcs->u32PleGap;
3416 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3417 if ( *puPrevPauseTick == 0
3418 || uTick - *puPrevPauseTick > uPleGap)
3419 *puFirstPauseLoopTick = uTick;
3420 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3421 fIntercept = true;
3422
3423 *puPrevPauseTick = uTick | 1;
3424 }
3425
3426 if (fIntercept)
3427 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3428
3429 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3430}
3431
3432
3433/**
3434 * VMX VM-exit handler for VM-exits due to task switches.
3435 *
3436 * @returns VBox strict status code.
3437 * @param pVCpu The cross context virtual CPU structure.
3438 * @param enmTaskSwitch The cause of the task switch.
3439 * @param SelNewTss The selector of the new TSS.
3440 * @param cbInstr The instruction length in bytes.
3441 */
3442VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT
3443{
3444 /*
3445 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3446 *
3447 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3448 * instruction or delivery of the exception generated by one of these instructions
3449 * lead to a task switch through a task gate in the IDT, we need to provide the
3450 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3451 * leaves the VM-exit instruction length field undefined.
3452 *
3453 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3454 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3455 */
3456 Assert(cbInstr <= 15);
3457
3458 uint8_t uType;
3459 switch (enmTaskSwitch)
3460 {
3461 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3462 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3463 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3464 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3465 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3466 }
3467
3468 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3469 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3470 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3471 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3472}
3473
3474
3475/**
3476 * VMX VM-exit handler for trap-like VM-exits.
3477 *
3478 * @returns VBox strict status code.
3479 * @param pVCpu The cross context virtual CPU structure.
3480 * @param pExitInfo Pointer to the VM-exit information.
3481 * @param pExitEventInfo Pointer to the VM-exit event information.
3482 */
3483static VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
3484{
3485 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3486 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3487 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3488}
3489
3490
3491/**
3492 * Interface for HM and EM to emulate a trap-like VM-exit (MTF, APIC-write,
3493 * Virtualized-EOI, TPR-below threshold).
3494 *
3495 * @returns Strict VBox status code.
3496 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3497 * @param pExitInfo Pointer to the VM-exit information.
3498 * @thread EMT(pVCpu)
3499 */
3500VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3501{
3502 Assert(pExitInfo);
3503 VBOXSTRICTRC rcStrict = iemVmxVmexitTrapLikeWithInfo(pVCpu, pExitInfo);
3504 Assert(!pVCpu->iem.s.cActiveMappings);
3505 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3506}
3507
3508
3509/**
3510 * VMX VM-exit handler for VM-exits due to task switches.
3511 *
3512 * This is intended for task switches where the caller provides all the relevant
3513 * VM-exit information.
3514 *
3515 * @returns VBox strict status code.
3516 * @param pVCpu The cross context virtual CPU structure.
3517 * @param pExitInfo Pointer to the VM-exit information.
3518 * @param pExitEventInfo Pointer to the VM-exit event information.
3519 */
3520static VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3521 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3522{
3523 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3524 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3525 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3526 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3527 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3528}
3529
3530
3531/**
3532 * Interface for HM and EM to emulate a VM-exit due to a task switch.
3533 *
3534 * @returns Strict VBox status code.
3535 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3536 * @param pExitInfo Pointer to the VM-exit information.
3537 * @param pExitEventInfo Pointer to the VM-exit event information.
3538 * @thread EMT(pVCpu)
3539 */
3540VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3541{
3542 Assert(pExitInfo);
3543 Assert(pExitEventInfo);
3544 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3545 VBOXSTRICTRC rcStrict = iemVmxVmexitTaskSwitchWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3546 Assert(!pVCpu->iem.s.cActiveMappings);
3547 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3548}
3549
3550
3551/**
3552 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3553 *
3554 * @returns VBox strict status code.
3555 * @param pVCpu The cross context virtual CPU structure.
3556 */
3557VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
3558{
3559 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3560 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3561
3562 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3563 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3564
3565 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3566 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3567 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3568
3569 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3570 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3571}
3572
3573
3574/**
3575 * Interface for HM and EM to emulate VM-exit due to expiry of the preemption timer.
3576 *
3577 * @returns Strict VBox status code.
3578 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3579 * @thread EMT(pVCpu)
3580 */
3581VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3582{
3583 VBOXSTRICTRC rcStrict = iemVmxVmexitPreemptTimer(pVCpu);
3584 Assert(!pVCpu->iem.s.cActiveMappings);
3585 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3586}
3587
3588
3589/**
3590 * VMX VM-exit handler for VM-exits due to external interrupts.
3591 *
3592 * @returns VBox strict status code.
3593 * @param pVCpu The cross context virtual CPU structure.
3594 * @param uVector The external interrupt vector (pass 0 if the interrupt
3595 * is still pending since we typically won't know the
3596 * vector).
3597 * @param fIntPending Whether the external interrupt is pending or
3598 * acknowledged in the interrupt controller.
3599 */
3600static VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending) RT_NOEXCEPT
3601{
3602 Assert(!fIntPending || uVector == 0);
3603
3604 /* The VM-exit is subject to "External interrupt exiting" being set. */
3605 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3606 {
3607 if (fIntPending)
3608 {
3609 /*
3610 * If the interrupt is pending and we don't need to acknowledge the
3611 * interrupt on VM-exit, cause the VM-exit immediately.
3612 *
3613 * See Intel spec 25.2 "Other Causes Of VM Exits".
3614 */
3615 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3616 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3617
3618 /*
3619 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3620 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3621 * acknowledged that the interrupt has been consumed. Callers would have to call
3622 * us again after getting the vector (and ofc, with fIntPending with false).
3623 */
3624 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3625 }
3626
3627 /*
3628 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3629 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3630 * all set, we need to record the vector of the external interrupt in the
3631 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3632 *
3633 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3634 */
3635 uint32_t uExitIntInfo;
3636 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3637 {
3638 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3639 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3640 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3641 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3642 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3643 }
3644 else
3645 uExitIntInfo = 0;
3646 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3647
3648 /*
3649 * Cause the VM-exit whether or not the vector has been stored
3650 * in the VM-exit interruption-information field.
3651 */
3652 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3653 }
3654
3655 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3656}
3657
3658
3659/**
3660 * Interface for HM and EM to emulate VM-exit due to external interrupts.
3661 *
3662 * @returns Strict VBox status code.
3663 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3664 * @param uVector The external interrupt vector (pass 0 if the external
3665 * interrupt is still pending).
3666 * @param fIntPending Whether the external interrupt is pending or
3667 * acknowdledged in the interrupt controller.
3668 * @thread EMT(pVCpu)
3669 */
3670VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3671{
3672 VBOXSTRICTRC rcStrict = iemVmxVmexitExtInt(pVCpu, uVector, fIntPending);
3673 Assert(!pVCpu->iem.s.cActiveMappings);
3674 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3675}
3676
3677
3678/**
3679 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3680 * an event.
3681 *
3682 * @returns VBox strict status code.
3683 * @param pVCpu The cross context virtual CPU structure.
3684 */
3685VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT
3686{
3687 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3688 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3689 {
3690 /*
3691 * The NMI-unblocking due to IRET field need not be set for double faults.
3692 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3693 */
3694 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3695 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3696 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3697 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3698 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3699 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3700 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3701 }
3702
3703 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3704}
3705
3706
3707/**
3708 * VMX VM-exit handler for VM-exit due to delivery of an events.
3709 *
3710 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3711 * all the relevant VM-exit information.
3712 *
3713 * @returns VBox strict status code.
3714 * @param pVCpu The cross context virtual CPU structure.
3715 * @param pExitInfo Pointer to the VM-exit information.
3716 * @param pExitEventInfo Pointer to the VM-exit event information.
3717 */
3718static VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3719{
3720 Assert(pExitInfo);
3721 Assert(pExitEventInfo);
3722 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3723 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3724
3725 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3726 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3727 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3728 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3729 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3730 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3731}
3732
3733
3734/**
3735 * Interface for HM and EM to emulate VM-exit due to NMIs.
3736 *
3737 * @returns Strict VBox status code.
3738 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3739 * @thread EMT(pVCpu)
3740 */
3741VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu)
3742{
3743 VMXVEXITINFO ExitInfo;
3744 RT_ZERO(ExitInfo);
3745 ExitInfo.uReason = VMX_EXIT_XCPT_OR_NMI;
3746
3747 VMXVEXITEVENTINFO ExitEventInfo;
3748 RT_ZERO(ExitEventInfo);
3749 ExitEventInfo.uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1)
3750 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_NMI)
3751 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_NMI);
3752
3753 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
3754 Assert(!pVCpu->iem.s.cActiveMappings);
3755 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3756}
3757
3758
3759/**
3760 * Interface for HM and EM to emulate VM-exit due to exceptions.
3761 *
3762 * Exception includes NMIs, software exceptions (those generated by INT3 or
3763 * INTO) and privileged software exceptions (those generated by INT1/ICEBP).
3764 *
3765 * @returns Strict VBox status code.
3766 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3767 * @param pExitInfo Pointer to the VM-exit information.
3768 * @param pExitEventInfo Pointer to the VM-exit event information.
3769 * @thread EMT(pVCpu)
3770 */
3771VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3772{
3773 Assert(pExitInfo);
3774 Assert(pExitEventInfo);
3775 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3776 Assert(!pVCpu->iem.s.cActiveMappings);
3777 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3778}
3779
3780
3781/**
3782 * VMX VM-exit handler for VM-exits due to delivery of an event.
3783 *
3784 * @returns VBox strict status code.
3785 * @param pVCpu The cross context virtual CPU structure.
3786 * @param uVector The interrupt / exception vector.
3787 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3788 * @param uErrCode The error code associated with the event.
3789 * @param uCr2 The CR2 value in case of a \#PF exception.
3790 * @param cbInstr The instruction length in bytes.
3791 */
3792VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode,
3793 uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT
3794{
3795 /*
3796 * If the event is being injected as part of VM-entry, it is -not- subject to event
3797 * intercepts in the nested-guest. However, secondary exceptions that occur during
3798 * injection of any event -are- subject to event interception.
3799 *
3800 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3801 */
3802 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3803 {
3804 /*
3805 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3806 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3807 *
3808 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3809 */
3810 if ( uVector == X86_XCPT_NMI
3811 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3812 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3813 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3814 else
3815 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3816
3817 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3818 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3819 }
3820
3821 /*
3822 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3823 * If not, the caller will continue delivery of the external interrupt as it would
3824 * normally. The interrupt is no longer pending in the interrupt controller at this
3825 * point.
3826 */
3827 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3828 {
3829 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3830 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3831 }
3832
3833 /*
3834 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3835 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3836 * interrupts.
3837 */
3838 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3839 bool fIntercept;
3840 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3841 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3842 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3843 else
3844 {
3845 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3846 fIntercept = false;
3847 }
3848
3849 /*
3850 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3851 * relevant VM-exit information and cause the VM-exit.
3852 */
3853 if (fIntercept)
3854 {
3855 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3856
3857 /* Construct the rest of the event related information fields and cause the VM-exit. */
3858 uint64_t u64ExitQual;
3859 if (uVector == X86_XCPT_PF)
3860 {
3861 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3862 u64ExitQual = uCr2;
3863 }
3864 else if (uVector == X86_XCPT_DB)
3865 {
3866 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3867 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3868 }
3869 else
3870 u64ExitQual = 0;
3871
3872 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3873 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3874 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3875 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3876 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3877 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3878 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3879 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3880 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3881 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3882
3883 /*
3884 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3885 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3886 * length.
3887 */
3888 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3889 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3890 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3891 else
3892 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3893
3894 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3895 }
3896
3897 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3898}
3899
3900
3901/**
3902 * VMX VM-exit handler for EPT misconfiguration.
3903 *
3904 * @param pVCpu The cross context virtual CPU structure.
3905 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3906 * This need not be page aligned (e.g. nested-guest in real
3907 * mode).
3908 */
3909static VBOXSTRICTRC iemVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr) RT_NOEXCEPT
3910{
3911 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3912 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3913}
3914
3915
3916/**
3917 * VMX VM-exit handler for EPT misconfiguration.
3918 *
3919 * This is intended for EPT misconfigurations where the caller provides all the
3920 * relevant VM-exit information.
3921 *
3922 * @param pVCpu The cross context virtual CPU structure.
3923 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3924 * This need not be page aligned (e.g. nested-guest in real
3925 * mode).
3926 * @param pExitEventInfo Pointer to the VM-exit event information.
3927 */
3928static VBOXSTRICTRC iemVmxVmexitEptMisconfigWithInfo(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3929{
3930 Assert(pExitEventInfo);
3931 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3932 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3933 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3934 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3935 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3936}
3937
3938
3939/**
3940 * Interface for HM and EM to emulate a VM-exit due to an EPT misconfiguration.
3941 *
3942 * @returns Strict VBox status code.
3943 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3944 * @param GCPhysAddr The nested-guest physical address causing the EPT
3945 * misconfiguration.
3946 * @param pExitEventInfo Pointer to the VM-exit event information.
3947 * @thread EMT(pVCpu)
3948 */
3949VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo)
3950{
3951 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
3952
3953 iemInitExec(pVCpu, false /*fBypassHandlers*/);
3954 VBOXSTRICTRC rcStrict = iemVmxVmexitEptMisconfigWithInfo(pVCpu, GCPhysAddr, pExitEventInfo);
3955 Assert(!pVCpu->iem.s.cActiveMappings);
3956 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
3957}
3958
3959
3960/**
3961 * VMX VM-exit handler for EPT violation.
3962 *
3963 * @param pVCpu The cross context virtual CPU structure.
3964 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3965 * @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
3966 * @param fEptAccess The EPT paging structure bits.
3967 * @param GCPhysAddr The physical address causing the EPT violation. This
3968 * need not be page aligned (e.g. nested-guest in real
3969 * mode).
3970 * @param fIsLinearAddrValid Whether translation of a linear address caused this
3971 * EPT violation. If @c false, GCPtrAddr must be 0.
3972 * @param GCPtrAddr The linear address causing the EPT violation.
3973 * @param cbInstr The VM-exit instruction length.
3974 */
3975static VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail,
3976 uint64_t fEptAccess, RTGCPHYS GCPhysAddr, bool fIsLinearAddrValid,
3977 uint64_t GCPtrAddr, uint8_t cbInstr) RT_NOEXCEPT
3978{
3979 /*
3980 * If the linear address isn't valid (can happen when loading PDPTEs
3981 * as part of MOV CR execution) the linear address field is undefined.
3982 * While we can leave it this way, it's preferrable to zero it for consistency.
3983 */
3984 Assert(fIsLinearAddrValid || GCPtrAddr == 0);
3985
3986 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
3987 bool const fSupportsAccessDirty = RT_BOOL(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
3988
3989 uint32_t const fDataRdMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_READ;
3990 uint32_t const fDataWrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_WRITE;
3991 uint32_t const fInstrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_EXEC;
3992 bool const fDataRead = ((fAccess & fDataRdMask) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
3993 bool const fDataWrite = ((fAccess & fDataWrMask) == IEM_ACCESS_DATA_W) | fSupportsAccessDirty;
3994 bool const fInstrFetch = ((fAccess & fInstrMask) == IEM_ACCESS_INSTRUCTION);
3995 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
3996 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
3997 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
3998 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3999 bool const fIsLinearToPhysAddr = fIsLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
4000
4001 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
4002 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
4003 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
4004 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
4005 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
4006 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
4007 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fIsLinearAddrValid)
4008 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fIsLinearToPhysAddr)
4009 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
4010
4011#ifdef VBOX_STRICT
4012 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
4013 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
4014 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
4015 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
4016 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
4017 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
4018#endif
4019
4020 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
4021 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
4022 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4023
4024 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
4025}
4026
4027
4028/**
4029 * VMX VM-exit handler for EPT violation.
4030 *
4031 * This is intended for EPT violations where the caller provides all the
4032 * relevant VM-exit information.
4033 *
4034 * @returns VBox strict status code.
4035 * @param pVCpu The cross context virtual CPU structure.
4036 * @param pExitInfo Pointer to the VM-exit information.
4037 * @param pExitEventInfo Pointer to the VM-exit event information.
4038 */
4039static VBOXSTRICTRC iemVmxVmexitEptViolationWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4040 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4041{
4042 Assert(pExitInfo);
4043 Assert(pExitEventInfo);
4044 Assert(pExitInfo->uReason == VMX_EXIT_EPT_VIOLATION);
4045 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4046
4047 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4048 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4049
4050 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
4051 if (pExitInfo->u64Qual & VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK)
4052 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
4053 else
4054 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, 0);
4055 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4056 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, pExitInfo->u64Qual);
4057}
4058
4059
4060/**
4061 * Interface for HM and EM to emulate a VM-exit due to an EPT violation.
4062 *
4063 * @returns Strict VBox status code.
4064 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4065 * @param pExitInfo Pointer to the VM-exit information.
4066 * @param pExitEventInfo Pointer to the VM-exit event information.
4067 * @thread EMT(pVCpu)
4068 */
4069VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4070 PCVMXVEXITEVENTINFO pExitEventInfo)
4071{
4072 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
4073
4074 iemInitExec(pVCpu, false /*fBypassHandlers*/);
4075 VBOXSTRICTRC rcStrict = iemVmxVmexitEptViolationWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4076 Assert(!pVCpu->iem.s.cActiveMappings);
4077 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
4078}
4079
4080
4081/**
4082 * VMX VM-exit handler for EPT-induced VM-exits.
4083 *
4084 * @param pVCpu The cross context virtual CPU structure.
4085 * @param pWalk The page walk info.
4086 * @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
4087 * @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
4088 * @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
4089 * applicable.
4090 */
4091VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT
4092{
4093 Assert(pWalk->fIsSlat);
4094 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
4095 Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
4096 Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
4097
4098 if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
4099 {
4100 Log(("EptViolation: cs:rip=%x:%#RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4101 uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
4102 return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
4103 pWalk->GCPtr, cbInstr);
4104 }
4105
4106 Log(("EptMisconfig: cs:rip=%x:%#RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4107 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
4108 return iemVmxVmexitEptMisconfig(pVCpu, pWalk->GCPhysNested);
4109}
4110
4111
4112/**
4113 * VMX VM-exit handler for APIC accesses.
4114 *
4115 * @param pVCpu The cross context virtual CPU structure.
4116 * @param offAccess The offset of the register being accessed.
4117 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4118 */
4119static VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess) RT_NOEXCEPT
4120{
4121 VMXAPICACCESS enmAccess;
4122 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4123 if (fInEventDelivery)
4124 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4125 else if ((fAccess & (IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_MASK)) == IEM_ACCESS_INSTRUCTION)
4126 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4127 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4128 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4129 else
4130 enmAccess = VMXAPICACCESS_LINEAR_READ;
4131
4132 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4133 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4134 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4135}
4136
4137
4138/**
4139 * VMX VM-exit handler for APIC accesses.
4140 *
4141 * This is intended for APIC accesses where the caller provides all the
4142 * relevant VM-exit information.
4143 *
4144 * @returns VBox strict status code.
4145 * @param pVCpu The cross context virtual CPU structure.
4146 * @param pExitInfo Pointer to the VM-exit information.
4147 * @param pExitEventInfo Pointer to the VM-exit event information.
4148 */
4149static VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4150 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4151{
4152 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4153 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4154 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
4155 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4156 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4157 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4158 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4159 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4160 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4161}
4162
4163
4164/**
4165 * Interface for HM and EM to virtualize memory-mapped APIC accesses.
4166 *
4167 * @returns Strict VBox status code.
4168 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the memory access was virtualized.
4169 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4170 *
4171 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4172 * @param pExitInfo Pointer to the VM-exit information.
4173 * @param pExitEventInfo Pointer to the VM-exit event information.
4174 * @thread EMT(pVCpu)
4175 */
4176VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
4177{
4178 Assert(pExitInfo);
4179 Assert(pExitEventInfo);
4180 VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4181 Assert(!pVCpu->iem.s.cActiveMappings);
4182 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4183}
4184
4185
4186/**
4187 * VMX VM-exit handler for APIC-write VM-exits.
4188 *
4189 * @param pVCpu The cross context virtual CPU structure.
4190 * @param offApic The write to the virtual-APIC page offset that caused this
4191 * VM-exit.
4192 */
4193static VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic) RT_NOEXCEPT
4194{
4195 Assert(offApic < XAPIC_OFF_END + 4);
4196 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4197 offApic &= UINT16_C(0xfff);
4198 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4199}
4200
4201
4202/**
4203 * Clears any pending virtual-APIC write emulation.
4204 *
4205 * @returns The virtual-APIC offset that was written before clearing it.
4206 * @param pVCpu The cross context virtual CPU structure.
4207 */
4208DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
4209{
4210 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4211 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4212 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4213 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4214 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4215 return offVirtApicWrite;
4216}
4217
4218
4219/**
4220 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4221 *
4222 * @returns The register from the virtual-APIC page.
4223 * @param pVCpu The cross context virtual CPU structure.
4224 * @param offReg The offset of the register being read.
4225 */
4226uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4227{
4228 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4229
4230 uint32_t uReg = 0;
4231 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4232 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4233 AssertMsgStmt(RT_SUCCESS(rc),
4234 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4235 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4236 uReg = 0);
4237 return uReg;
4238}
4239
4240
4241/**
4242 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4243 *
4244 * @returns The register from the virtual-APIC page.
4245 * @param pVCpu The cross context virtual CPU structure.
4246 * @param offReg The offset of the register being read.
4247 */
4248static uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4249{
4250 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4251
4252 uint64_t uReg = 0;
4253 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4254 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4255 AssertMsgStmt(RT_SUCCESS(rc),
4256 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4257 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4258 uReg = 0);
4259 return uReg;
4260}
4261
4262
4263/**
4264 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4265 *
4266 * @param pVCpu The cross context virtual CPU structure.
4267 * @param offReg The offset of the register being written.
4268 * @param uReg The register value to write.
4269 */
4270void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT
4271{
4272 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4273
4274 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4275 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4276 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4277 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4278}
4279
4280
4281/**
4282 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4283 *
4284 * @param pVCpu The cross context virtual CPU structure.
4285 * @param offReg The offset of the register being written.
4286 * @param uReg The register value to write.
4287 */
4288static void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg) RT_NOEXCEPT
4289{
4290 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4291
4292 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4293 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4294 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4295 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4296}
4297
4298
4299/**
4300 * Sets the vector in a virtual-APIC 256-bit sparse register.
4301 *
4302 * @param pVCpu The cross context virtual CPU structure.
4303 * @param offReg The offset of the 256-bit spare register.
4304 * @param uVector The vector to set.
4305 *
4306 * @remarks This is based on our APIC device code.
4307 */
4308static void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4309{
4310 /* Determine the vector offset within the chunk. */
4311 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4312
4313 /* Read the chunk at the offset. */
4314 uint32_t uReg;
4315 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4316 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4317 if (RT_SUCCESS(rc))
4318 {
4319 /* Modify the chunk. */
4320 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4321 uReg |= RT_BIT(idxVectorBit);
4322
4323 /* Write the chunk. */
4324 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4325 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4326 uVector, offReg, GCPhysVirtApic, rc));
4327 }
4328 else
4329 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4330 uVector, offReg, GCPhysVirtApic, rc));
4331}
4332
4333
4334/**
4335 * Clears the vector in a virtual-APIC 256-bit sparse register.
4336 *
4337 * @param pVCpu The cross context virtual CPU structure.
4338 * @param offReg The offset of the 256-bit spare register.
4339 * @param uVector The vector to clear.
4340 *
4341 * @remarks This is based on our APIC device code.
4342 */
4343static void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4344{
4345 /* Determine the vector offset within the chunk. */
4346 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4347
4348 /* Read the chunk at the offset. */
4349 uint32_t uReg;
4350 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4351 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4352 if (RT_SUCCESS(rc))
4353 {
4354 /* Modify the chunk. */
4355 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4356 uReg &= ~RT_BIT(idxVectorBit);
4357
4358 /* Write the chunk. */
4359 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4360 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4361 uVector, offReg, GCPhysVirtApic, rc));
4362 }
4363 else
4364 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4365 uVector, offReg, GCPhysVirtApic, rc));
4366}
4367
4368
4369/**
4370 * Checks if a memory access to the APIC-access page must causes an APIC-access
4371 * VM-exit.
4372 *
4373 * @param pVCpu The cross context virtual CPU structure.
4374 * @param offAccess The offset of the register being accessed.
4375 * @param cbAccess The size of the access in bytes.
4376 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4377 *
4378 * @remarks This must not be used for MSR-based APIC-access page accesses!
4379 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4380 */
4381static bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4382{
4383 Assert(cbAccess > 0);
4384 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4385
4386 /*
4387 * We must cause a VM-exit if any of the following are true:
4388 * - TPR shadowing isn't active.
4389 * - The access size exceeds 32-bits.
4390 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4391 *
4392 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4393 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4394 */
4395 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4396 || cbAccess > sizeof(uint32_t)
4397 || ((offAccess + cbAccess - 1) & 0xc)
4398 || offAccess >= XAPIC_OFF_END + 4)
4399 return true;
4400
4401 /*
4402 * If the access is part of an operation where we have already
4403 * virtualized a virtual-APIC write, we must cause a VM-exit.
4404 */
4405 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4406 return true;
4407
4408 /*
4409 * Check write accesses to the APIC-access page that cause VM-exits.
4410 */
4411 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4412 {
4413 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4414 {
4415 /*
4416 * With APIC-register virtualization, a write access to any of the
4417 * following registers are virtualized. Accessing any other register
4418 * causes a VM-exit.
4419 */
4420 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4421 switch (offAlignedAccess)
4422 {
4423 case XAPIC_OFF_ID:
4424 case XAPIC_OFF_TPR:
4425 case XAPIC_OFF_EOI:
4426 case XAPIC_OFF_LDR:
4427 case XAPIC_OFF_DFR:
4428 case XAPIC_OFF_SVR:
4429 case XAPIC_OFF_ESR:
4430 case XAPIC_OFF_ICR_LO:
4431 case XAPIC_OFF_ICR_HI:
4432 case XAPIC_OFF_LVT_TIMER:
4433 case XAPIC_OFF_LVT_THERMAL:
4434 case XAPIC_OFF_LVT_PERF:
4435 case XAPIC_OFF_LVT_LINT0:
4436 case XAPIC_OFF_LVT_LINT1:
4437 case XAPIC_OFF_LVT_ERROR:
4438 case XAPIC_OFF_TIMER_ICR:
4439 case XAPIC_OFF_TIMER_DCR:
4440 break;
4441 default:
4442 return true;
4443 }
4444 }
4445 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4446 {
4447 /*
4448 * With virtual-interrupt delivery, a write access to any of the
4449 * following registers are virtualized. Accessing any other register
4450 * causes a VM-exit.
4451 *
4452 * Note! The specification does not allow writing to offsets in-between
4453 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4454 */
4455 switch (offAccess)
4456 {
4457 case XAPIC_OFF_TPR:
4458 case XAPIC_OFF_EOI:
4459 case XAPIC_OFF_ICR_LO:
4460 break;
4461 default:
4462 return true;
4463 }
4464 }
4465 else
4466 {
4467 /*
4468 * Without APIC-register virtualization or virtual-interrupt delivery,
4469 * only TPR accesses are virtualized.
4470 */
4471 if (offAccess == XAPIC_OFF_TPR)
4472 { /* likely */ }
4473 else
4474 return true;
4475 }
4476 }
4477 else
4478 {
4479 /*
4480 * Check read accesses to the APIC-access page that cause VM-exits.
4481 */
4482 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4483 {
4484 /*
4485 * With APIC-register virtualization, a read access to any of the
4486 * following registers are virtualized. Accessing any other register
4487 * causes a VM-exit.
4488 */
4489 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4490 switch (offAlignedAccess)
4491 {
4492 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4493 case XAPIC_OFF_ID:
4494 case XAPIC_OFF_VERSION:
4495 case XAPIC_OFF_TPR:
4496 case XAPIC_OFF_EOI:
4497 case XAPIC_OFF_LDR:
4498 case XAPIC_OFF_DFR:
4499 case XAPIC_OFF_SVR:
4500 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4501 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4502 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4503 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4504 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4505 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4506 case XAPIC_OFF_ESR:
4507 case XAPIC_OFF_ICR_LO:
4508 case XAPIC_OFF_ICR_HI:
4509 case XAPIC_OFF_LVT_TIMER:
4510 case XAPIC_OFF_LVT_THERMAL:
4511 case XAPIC_OFF_LVT_PERF:
4512 case XAPIC_OFF_LVT_LINT0:
4513 case XAPIC_OFF_LVT_LINT1:
4514 case XAPIC_OFF_LVT_ERROR:
4515 case XAPIC_OFF_TIMER_ICR:
4516 case XAPIC_OFF_TIMER_DCR:
4517 break;
4518 default:
4519 return true;
4520 }
4521 }
4522 else
4523 {
4524 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4525 if (offAccess == XAPIC_OFF_TPR)
4526 { /* likely */ }
4527 else
4528 return true;
4529 }
4530 }
4531
4532 /* The APIC access is virtualized, does not cause a VM-exit. */
4533 return false;
4534}
4535
4536
4537/**
4538 * Virtualizes a memory-based APIC access by certain instructions even though they
4539 * do not use the address to access memory.
4540 *
4541 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4542 * page-faults but do not use the address to access memory.
4543 *
4544 * @param pVCpu The cross context virtual CPU structure.
4545 * @param pGCPhysAccess Pointer to the guest-physical address accessed.
4546 * @param cbAccess The size of the access in bytes.
4547 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4548 */
4549VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4550{
4551 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4552 Assert(pGCPhysAccess);
4553
4554 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
4555 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4556 Assert(!(GCPhysApic & GUEST_PAGE_OFFSET_MASK));
4557
4558 if (GCPhysAccess == GCPhysApic)
4559 {
4560 uint16_t const offAccess = *pGCPhysAccess & GUEST_PAGE_OFFSET_MASK;
4561 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4562 if (fIntercept)
4563 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4564
4565 *pGCPhysAccess = GCPhysApic | offAccess;
4566 return VINF_VMX_MODIFIES_BEHAVIOR;
4567 }
4568
4569 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4570}
4571
4572
4573/**
4574 * Virtualizes a memory-based APIC access.
4575 *
4576 * @returns VBox strict status code.
4577 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4578 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4579 *
4580 * @param pVCpu The cross context virtual CPU structure.
4581 * @param offAccess The offset of the register being accessed (within the
4582 * APIC-access page).
4583 * @param cbAccess The size of the access in bytes.
4584 * @param pvData Pointer to the data being written or where to store the data
4585 * being read.
4586 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4587 */
4588static VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess,
4589 void *pvData, uint32_t fAccess) RT_NOEXCEPT
4590{
4591 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4592 Assert(pvData);
4593
4594 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4595 if (fIntercept)
4596 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4597
4598 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4599 {
4600 /*
4601 * A write access to the APIC-access page that is virtualized (rather than
4602 * causing a VM-exit) writes data to the virtual-APIC page.
4603 */
4604 uint32_t const u32Data = *(uint32_t *)pvData;
4605 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4606
4607 /*
4608 * Record the currently updated APIC offset, as we need this later for figuring
4609 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4610 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4611 *
4612 * After completion of the current operation, we need to perform TPR virtualization,
4613 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4614 *
4615 * The current operation may be a REP-prefixed string instruction, execution of any
4616 * other instruction, or delivery of an event through the IDT.
4617 *
4618 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4619 * performed now but later after completion of the current operation.
4620 *
4621 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4622 */
4623 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4624 }
4625 else
4626 {
4627 /*
4628 * A read access from the APIC-access page that is virtualized (rather than
4629 * causing a VM-exit) returns data from the virtual-APIC page.
4630 *
4631 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4632 */
4633 Assert(fAccess & IEM_ACCESS_TYPE_READ);
4634
4635 Assert(cbAccess <= 4);
4636 Assert(offAccess < XAPIC_OFF_END + 4);
4637 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4638
4639 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4640 u32Data &= s_auAccessSizeMasks[cbAccess];
4641 *(uint32_t *)pvData = u32Data;
4642 }
4643
4644 return VINF_VMX_MODIFIES_BEHAVIOR;
4645}
4646
4647
4648/**
4649 * Virtualizes an MSR-based APIC read access.
4650 *
4651 * @returns VBox strict status code.
4652 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4653 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4654 * handled by the x2APIC device.
4655 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4656 * not within the range of valid MSRs, caller must raise \#GP(0).
4657 * @param pVCpu The cross context virtual CPU structure.
4658 * @param idMsr The x2APIC MSR being read.
4659 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4660 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4661 */
4662static VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value) RT_NOEXCEPT
4663{
4664 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4665 Assert(pu64Value);
4666
4667 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4668 {
4669 if ( idMsr >= MSR_IA32_X2APIC_START
4670 && idMsr <= MSR_IA32_X2APIC_END)
4671 {
4672 uint16_t const offReg = (idMsr & 0xff) << 4;
4673 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4674 *pu64Value = u64Value;
4675 return VINF_VMX_MODIFIES_BEHAVIOR;
4676 }
4677 return VERR_OUT_OF_RANGE;
4678 }
4679
4680 if (idMsr == MSR_IA32_X2APIC_TPR)
4681 {
4682 uint16_t const offReg = (idMsr & 0xff) << 4;
4683 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4684 *pu64Value = u64Value;
4685 return VINF_VMX_MODIFIES_BEHAVIOR;
4686 }
4687
4688 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4689}
4690
4691
4692/**
4693 * Virtualizes an MSR-based APIC write access.
4694 *
4695 * @returns VBox strict status code.
4696 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4697 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4698 * not within the range of valid MSRs, caller must raise \#GP(0).
4699 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4700 *
4701 * @param pVCpu The cross context virtual CPU structure.
4702 * @param idMsr The x2APIC MSR being written.
4703 * @param u64Value The value of the x2APIC MSR being written.
4704 */
4705static VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value) RT_NOEXCEPT
4706{
4707 /*
4708 * Check if the access is to be virtualized.
4709 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4710 */
4711 if ( idMsr == MSR_IA32_X2APIC_TPR
4712 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4713 && ( idMsr == MSR_IA32_X2APIC_EOI
4714 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4715 {
4716 /* Validate the MSR write depending on the register. */
4717 switch (idMsr)
4718 {
4719 case MSR_IA32_X2APIC_TPR:
4720 case MSR_IA32_X2APIC_SELF_IPI:
4721 {
4722 if (u64Value & UINT64_C(0xffffffffffffff00))
4723 return VERR_OUT_OF_RANGE;
4724 break;
4725 }
4726 case MSR_IA32_X2APIC_EOI:
4727 {
4728 if (u64Value != 0)
4729 return VERR_OUT_OF_RANGE;
4730 break;
4731 }
4732 }
4733
4734 /* Write the MSR to the virtual-APIC page. */
4735 uint16_t const offReg = (idMsr & 0xff) << 4;
4736 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4737
4738 /*
4739 * Record the currently updated APIC offset, as we need this later for figuring
4740 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4741 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4742 */
4743 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4744
4745 return VINF_VMX_MODIFIES_BEHAVIOR;
4746 }
4747
4748 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4749}
4750
4751
4752/**
4753 * Interface for HM and EM to virtualize x2APIC MSR accesses.
4754 *
4755 * @returns Strict VBox status code.
4756 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR access was virtualized.
4757 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR access must be handled by
4758 * the x2APIC device.
4759 * @retval VERR_OUT_RANGE if the caller must raise \#GP(0).
4760 *
4761 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4762 * @param idMsr The MSR being read.
4763 * @param pu64Value Pointer to the value being written or where to store the
4764 * value being read.
4765 * @param fWrite Whether this is an MSR write or read access.
4766 * @thread EMT(pVCpu)
4767 */
4768VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value, bool fWrite)
4769{
4770 Assert(pu64Value);
4771
4772 VBOXSTRICTRC rcStrict;
4773 if (fWrite)
4774 rcStrict = iemVmxVirtApicAccessMsrWrite(pVCpu, idMsr, *pu64Value);
4775 else
4776 rcStrict = iemVmxVirtApicAccessMsrRead(pVCpu, idMsr, pu64Value);
4777 Assert(!pVCpu->iem.s.cActiveMappings);
4778 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4779
4780}
4781
4782
4783/**
4784 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4785 *
4786 * @returns VBox status code.
4787 * @retval VINF_SUCCESS when the highest set bit is found.
4788 * @retval VERR_NOT_FOUND when no bit is set.
4789 *
4790 * @param pVCpu The cross context virtual CPU structure.
4791 * @param offReg The offset of the APIC 256-bit sparse register.
4792 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4793 * set in the register. Only valid when VINF_SUCCESS is
4794 * returned.
4795 *
4796 * @remarks The format of the 256-bit sparse register here mirrors that found in
4797 * real APIC hardware.
4798 */
4799static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4800{
4801 Assert(offReg < XAPIC_OFF_END + 4);
4802 Assert(pidxHighestBit);
4803
4804 /*
4805 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4806 * However, in each fragment only the first 4 bytes are used.
4807 */
4808 uint8_t const cFrags = 8;
4809 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4810 {
4811 uint16_t const offFrag = iFrag * 16;
4812 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4813 if (!u32Frag)
4814 continue;
4815
4816 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4817 Assert(idxHighestBit > 0);
4818 --idxHighestBit;
4819 Assert(idxHighestBit <= UINT8_MAX);
4820 *pidxHighestBit = idxHighestBit;
4821 return VINF_SUCCESS;
4822 }
4823 return VERR_NOT_FOUND;
4824}
4825
4826
4827/**
4828 * Evaluates pending virtual interrupts.
4829 *
4830 * @param pVCpu The cross context virtual CPU structure.
4831 */
4832static void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu) RT_NOEXCEPT
4833{
4834 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4835
4836 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4837 {
4838 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4839 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4840
4841 if ((uRvi >> 4) > (uPpr >> 4))
4842 {
4843 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4844 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4845 }
4846 else
4847 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4848 }
4849}
4850
4851
4852/**
4853 * Performs PPR virtualization.
4854 *
4855 * @returns VBox strict status code.
4856 * @param pVCpu The cross context virtual CPU structure.
4857 */
4858static void iemVmxPprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4859{
4860 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4861 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4862
4863 /*
4864 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4865 * or EOI-virtualization.
4866 *
4867 * See Intel spec. 29.1.3 "PPR Virtualization".
4868 */
4869 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4870 uint32_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4871
4872 uint32_t uPpr;
4873 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4874 uPpr = uTpr & 0xff;
4875 else
4876 uPpr = uSvi & 0xf0;
4877
4878 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4879 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4880}
4881
4882
4883/**
4884 * Performs VMX TPR virtualization.
4885 *
4886 * @returns VBox strict status code.
4887 * @param pVCpu The cross context virtual CPU structure.
4888 */
4889static VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4890{
4891 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4892
4893 /*
4894 * We should have already performed the virtual-APIC write to the TPR offset
4895 * in the virtual-APIC page. We now perform TPR virtualization.
4896 *
4897 * See Intel spec. 29.1.2 "TPR Virtualization".
4898 */
4899 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4900 {
4901 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4902 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4903
4904 /*
4905 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4906 * See Intel spec. 29.1.2 "TPR Virtualization".
4907 */
4908 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4909 {
4910 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4911 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4912 }
4913 }
4914 else
4915 {
4916 iemVmxPprVirtualization(pVCpu);
4917 iemVmxEvalPendingVirtIntrs(pVCpu);
4918 }
4919
4920 return VINF_SUCCESS;
4921}
4922
4923
4924/**
4925 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4926 * not.
4927 *
4928 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4929 * @param pVCpu The cross context virtual CPU structure.
4930 * @param uVector The interrupt that was acknowledged using an EOI.
4931 */
4932static bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector) RT_NOEXCEPT
4933{
4934 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4935 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4936
4937 if (uVector < 64)
4938 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4939 if (uVector < 128)
4940 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4941 if (uVector < 192)
4942 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4943 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4944}
4945
4946
4947/**
4948 * Performs EOI virtualization.
4949 *
4950 * @returns VBox strict status code.
4951 * @param pVCpu The cross context virtual CPU structure.
4952 */
4953static VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4954{
4955 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4956 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4957
4958 /*
4959 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4960 * and get the next guest-interrupt that's in-service (if any).
4961 *
4962 * See Intel spec. 29.1.4 "EOI Virtualization".
4963 */
4964 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4965 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4966 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4967
4968 uint8_t uVector = uSvi;
4969 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4970
4971 uVector = 0;
4972 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4973
4974 if (uVector)
4975 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4976 else
4977 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4978
4979 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4980 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4981
4982 iemVmxPprVirtualization(pVCpu);
4983 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4984 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
4985 iemVmxEvalPendingVirtIntrs(pVCpu);
4986 return VINF_SUCCESS;
4987}
4988
4989
4990/**
4991 * Performs self-IPI virtualization.
4992 *
4993 * @returns VBox strict status code.
4994 * @param pVCpu The cross context virtual CPU structure.
4995 */
4996static VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4997{
4998 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4999 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5000
5001 /*
5002 * We should have already performed the virtual-APIC write to the self-IPI offset
5003 * in the virtual-APIC page. We now perform self-IPI virtualization.
5004 *
5005 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5006 */
5007 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5008 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5009 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5010 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5011 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5012 if (uVector > uRvi)
5013 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5014 iemVmxEvalPendingVirtIntrs(pVCpu);
5015 return VINF_SUCCESS;
5016}
5017
5018
5019/**
5020 * Performs VMX APIC-write emulation.
5021 *
5022 * @returns VBox strict status code.
5023 * @param pVCpu The cross context virtual CPU structure.
5024 */
5025VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT
5026{
5027 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5028
5029 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5030 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5031
5032 /*
5033 * Perform APIC-write emulation based on the virtual-APIC register written.
5034 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5035 */
5036 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5037 VBOXSTRICTRC rcStrict;
5038 switch (offApicWrite)
5039 {
5040 case XAPIC_OFF_TPR:
5041 {
5042 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5043 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5044 uTpr &= UINT32_C(0x000000ff);
5045 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5046 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5047 rcStrict = iemVmxTprVirtualization(pVCpu);
5048 break;
5049 }
5050
5051 case XAPIC_OFF_EOI:
5052 {
5053 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5054 {
5055 /* Clear VEOI and perform EOI virtualization. */
5056 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5057 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5058 rcStrict = iemVmxEoiVirtualization(pVCpu);
5059 }
5060 else
5061 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5062 break;
5063 }
5064
5065 case XAPIC_OFF_ICR_LO:
5066 {
5067 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5068 {
5069 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5070 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5071 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5072 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5073 if ( !(uIcrLo & fIcrLoMb0)
5074 && (uIcrLo & fIcrLoMb1))
5075 {
5076 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5077 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5078 }
5079 else
5080 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5081 }
5082 else
5083 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5084 break;
5085 }
5086
5087 case XAPIC_OFF_ICR_HI:
5088 {
5089 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5090 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5091 uIcrHi &= UINT32_C(0xff000000);
5092 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5093 rcStrict = VINF_SUCCESS;
5094 break;
5095 }
5096
5097 default:
5098 {
5099 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5100 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5101 break;
5102 }
5103 }
5104
5105 return rcStrict;
5106}
5107
5108
5109/**
5110 * Interface for HM and EM to perform an APIC-write emulation which may cause a
5111 * VM-exit.
5112 *
5113 * @returns Strict VBox status code.
5114 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
5115 * @thread EMT(pVCpu)
5116 */
5117VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu)
5118{
5119 VBOXSTRICTRC rcStrict = iemVmxApicWriteEmulation(pVCpu);
5120 Assert(!pVCpu->iem.s.cActiveMappings);
5121 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
5122}
5123
5124
5125/**
5126 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5127 *
5128 * @param pVCpu The cross context virtual CPU structure.
5129 * @param pszInstr The VMX instruction name (for logging purposes).
5130 */
5131DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
5132{
5133 /*
5134 * Guest Control Registers, Debug Registers, and MSRs.
5135 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5136 */
5137 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5138 const char * const pszFailure = "VM-exit";
5139 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5140
5141 /* CR0 reserved bits. */
5142 {
5143 /* CR0 MB1 bits. */
5144 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu);
5145 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5146 { /* likely */ }
5147 else
5148 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5149
5150 /* CR0 MBZ bits. */
5151 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5152 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5153 { /* likely */ }
5154 else
5155 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5156
5157 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5158 if ( !fUnrestrictedGuest
5159 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5160 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5161 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5162 }
5163
5164 /* CR4 reserved bits. */
5165 {
5166 /* CR4 MB1 bits. */
5167 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5168 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5169 { /* likely */ }
5170 else
5171 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5172
5173 /* CR4 MBZ bits. */
5174 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5175 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5176 { /* likely */ }
5177 else
5178 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5179 }
5180
5181 /* DEBUGCTL MSR. */
5182 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5183 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5184 { /* likely */ }
5185 else
5186 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5187
5188 /* 64-bit CPU checks. */
5189 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5190 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5191 {
5192 if (fGstInLongMode)
5193 {
5194 /* PAE must be set. */
5195 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5196 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5197 { /* likely */ }
5198 else
5199 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5200 }
5201 else
5202 {
5203 /* PCIDE should not be set. */
5204 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5205 { /* likely */ }
5206 else
5207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5208 }
5209
5210 /* CR3. */
5211 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5212 { /* likely */ }
5213 else
5214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5215
5216 /* DR7. */
5217 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5218 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5219 { /* likely */ }
5220 else
5221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5222
5223 /* SYSENTER ESP and SYSENTER EIP. */
5224 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5225 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5226 { /* likely */ }
5227 else
5228 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5229 }
5230
5231 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5232 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5233
5234 /* PAT MSR. */
5235 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5236 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5237 { /* likely */ }
5238 else
5239 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5240
5241 /* EFER MSR. */
5242 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5243 {
5244 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5245 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5246 { /* likely */ }
5247 else
5248 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5249
5250 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5251 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5252 if ( fGstLma == fGstInLongMode
5253 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5254 || fGstLma == fGstLme))
5255 { /* likely */ }
5256 else
5257 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5258 }
5259
5260 /* We don't support IA32_BNDCFGS MSR yet. */
5261 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5262
5263 NOREF(pszInstr);
5264 NOREF(pszFailure);
5265 return VINF_SUCCESS;
5266}
5267
5268
5269/**
5270 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5271 *
5272 * @param pVCpu The cross context virtual CPU structure.
5273 * @param pszInstr The VMX instruction name (for logging purposes).
5274 */
5275DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
5276{
5277 /*
5278 * Segment registers.
5279 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5280 */
5281 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5282 const char * const pszFailure = "VM-exit";
5283 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5284 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5285 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5286
5287 /* Selectors. */
5288 if ( !fGstInV86Mode
5289 && !fUnrestrictedGuest
5290 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5291 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5292
5293 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5294 {
5295 CPUMSELREG SelReg;
5296 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5297 if (RT_LIKELY(rc == VINF_SUCCESS))
5298 { /* likely */ }
5299 else
5300 return rc;
5301
5302 /*
5303 * Virtual-8086 mode checks.
5304 */
5305 if (fGstInV86Mode)
5306 {
5307 /* Base address. */
5308 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5309 { /* likely */ }
5310 else
5311 {
5312 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5313 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5314 }
5315
5316 /* Limit. */
5317 if (SelReg.u32Limit == 0xffff)
5318 { /* likely */ }
5319 else
5320 {
5321 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5322 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5323 }
5324
5325 /* Attribute. */
5326 if (SelReg.Attr.u == 0xf3)
5327 { /* likely */ }
5328 else
5329 {
5330 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5331 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5332 }
5333
5334 /* We're done; move to checking the next segment. */
5335 continue;
5336 }
5337
5338 /* Checks done by 64-bit CPUs. */
5339 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5340 {
5341 /* Base address. */
5342 if ( iSegReg == X86_SREG_FS
5343 || iSegReg == X86_SREG_GS)
5344 {
5345 if (X86_IS_CANONICAL(SelReg.u64Base))
5346 { /* likely */ }
5347 else
5348 {
5349 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5350 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5351 }
5352 }
5353 else if (iSegReg == X86_SREG_CS)
5354 {
5355 if (!RT_HI_U32(SelReg.u64Base))
5356 { /* likely */ }
5357 else
5358 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5359 }
5360 else
5361 {
5362 if ( SelReg.Attr.n.u1Unusable
5363 || !RT_HI_U32(SelReg.u64Base))
5364 { /* likely */ }
5365 else
5366 {
5367 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5368 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5369 }
5370 }
5371 }
5372
5373 /*
5374 * Checks outside Virtual-8086 mode.
5375 */
5376 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5377 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5378 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5379 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5380 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5381 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5382 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5383 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5384
5385 /* Code or usable segment. */
5386 if ( iSegReg == X86_SREG_CS
5387 || fUsable)
5388 {
5389 /* Reserved bits (bits 31:17 and bits 11:8). */
5390 if (!(SelReg.Attr.u & 0xfffe0f00))
5391 { /* likely */ }
5392 else
5393 {
5394 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5395 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5396 }
5397
5398 /* Descriptor type. */
5399 if (fCodeDataSeg)
5400 { /* likely */ }
5401 else
5402 {
5403 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5404 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5405 }
5406
5407 /* Present. */
5408 if (fPresent)
5409 { /* likely */ }
5410 else
5411 {
5412 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5413 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5414 }
5415
5416 /* Granularity. */
5417 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5418 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5419 { /* likely */ }
5420 else
5421 {
5422 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5423 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5424 }
5425 }
5426
5427 if (iSegReg == X86_SREG_CS)
5428 {
5429 /* Segment Type and DPL. */
5430 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5431 && fUnrestrictedGuest)
5432 {
5433 if (uDpl == 0)
5434 { /* likely */ }
5435 else
5436 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5437 }
5438 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5439 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5440 {
5441 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5442 if (uDpl == AttrSs.n.u2Dpl)
5443 { /* likely */ }
5444 else
5445 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5446 }
5447 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5448 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5449 {
5450 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5451 if (uDpl <= AttrSs.n.u2Dpl)
5452 { /* likely */ }
5453 else
5454 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5455 }
5456 else
5457 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5458
5459 /* Def/Big. */
5460 if ( fGstInLongMode
5461 && fSegLong)
5462 {
5463 if (uDefBig == 0)
5464 { /* likely */ }
5465 else
5466 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5467 }
5468 }
5469 else if (iSegReg == X86_SREG_SS)
5470 {
5471 /* Segment Type. */
5472 if ( !fUsable
5473 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5474 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5475 { /* likely */ }
5476 else
5477 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5478
5479 /* DPL. */
5480 if (!fUnrestrictedGuest)
5481 {
5482 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5483 { /* likely */ }
5484 else
5485 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5486 }
5487 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5488 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5489 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5490 {
5491 if (uDpl == 0)
5492 { /* likely */ }
5493 else
5494 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5495 }
5496 }
5497 else
5498 {
5499 /* DS, ES, FS, GS. */
5500 if (fUsable)
5501 {
5502 /* Segment type. */
5503 if (uSegType & X86_SEL_TYPE_ACCESSED)
5504 { /* likely */ }
5505 else
5506 {
5507 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5508 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5509 }
5510
5511 if ( !(uSegType & X86_SEL_TYPE_CODE)
5512 || (uSegType & X86_SEL_TYPE_READ))
5513 { /* likely */ }
5514 else
5515 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5516
5517 /* DPL. */
5518 if ( !fUnrestrictedGuest
5519 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5520 {
5521 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5522 { /* likely */ }
5523 else
5524 {
5525 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5526 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5527 }
5528 }
5529 }
5530 }
5531 }
5532
5533 /*
5534 * LDTR.
5535 */
5536 {
5537 CPUMSELREG Ldtr;
5538 Ldtr.Sel = pVmcs->GuestLdtr;
5539 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5540 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5541 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5542
5543 if (!Ldtr.Attr.n.u1Unusable)
5544 {
5545 /* Selector. */
5546 if (!(Ldtr.Sel & X86_SEL_LDT))
5547 { /* likely */ }
5548 else
5549 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5550
5551 /* Base. */
5552 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5553 {
5554 if (X86_IS_CANONICAL(Ldtr.u64Base))
5555 { /* likely */ }
5556 else
5557 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5558 }
5559
5560 /* Attributes. */
5561 /* Reserved bits (bits 31:17 and bits 11:8). */
5562 if (!(Ldtr.Attr.u & 0xfffe0f00))
5563 { /* likely */ }
5564 else
5565 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5566
5567 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5568 { /* likely */ }
5569 else
5570 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5571
5572 if (!Ldtr.Attr.n.u1DescType)
5573 { /* likely */ }
5574 else
5575 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5576
5577 if (Ldtr.Attr.n.u1Present)
5578 { /* likely */ }
5579 else
5580 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5581
5582 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5583 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5584 { /* likely */ }
5585 else
5586 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5587 }
5588 }
5589
5590 /*
5591 * TR.
5592 */
5593 {
5594 CPUMSELREG Tr;
5595 Tr.Sel = pVmcs->GuestTr;
5596 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5597 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5598 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5599
5600 /* Selector. */
5601 if (!(Tr.Sel & X86_SEL_LDT))
5602 { /* likely */ }
5603 else
5604 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5605
5606 /* Base. */
5607 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5608 {
5609 if (X86_IS_CANONICAL(Tr.u64Base))
5610 { /* likely */ }
5611 else
5612 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5613 }
5614
5615 /* Attributes. */
5616 /* Reserved bits (bits 31:17 and bits 11:8). */
5617 if (!(Tr.Attr.u & 0xfffe0f00))
5618 { /* likely */ }
5619 else
5620 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5621
5622 if (!Tr.Attr.n.u1Unusable)
5623 { /* likely */ }
5624 else
5625 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5626
5627 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5628 || ( !fGstInLongMode
5629 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5630 { /* likely */ }
5631 else
5632 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5633
5634 if (!Tr.Attr.n.u1DescType)
5635 { /* likely */ }
5636 else
5637 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5638
5639 if (Tr.Attr.n.u1Present)
5640 { /* likely */ }
5641 else
5642 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5643
5644 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5645 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5646 { /* likely */ }
5647 else
5648 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5649 }
5650
5651 NOREF(pszInstr);
5652 NOREF(pszFailure);
5653 return VINF_SUCCESS;
5654}
5655
5656
5657/**
5658 * Checks guest GDTR and IDTR as part of VM-entry.
5659 *
5660 * @param pVCpu The cross context virtual CPU structure.
5661 * @param pszInstr The VMX instruction name (for logging purposes).
5662 */
5663DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5664{
5665 /*
5666 * GDTR and IDTR.
5667 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5668 */
5669 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5670 const char *const pszFailure = "VM-exit";
5671
5672 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5673 {
5674 /* Base. */
5675 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5676 { /* likely */ }
5677 else
5678 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5679
5680 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5681 { /* likely */ }
5682 else
5683 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5684 }
5685
5686 /* Limit. */
5687 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5688 { /* likely */ }
5689 else
5690 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5691
5692 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5693 { /* likely */ }
5694 else
5695 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5696
5697 NOREF(pszInstr);
5698 NOREF(pszFailure);
5699 return VINF_SUCCESS;
5700}
5701
5702
5703/**
5704 * Checks guest RIP and RFLAGS as part of VM-entry.
5705 *
5706 * @param pVCpu The cross context virtual CPU structure.
5707 * @param pszInstr The VMX instruction name (for logging purposes).
5708 */
5709DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5710{
5711 /*
5712 * RIP and RFLAGS.
5713 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5714 */
5715 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5716 const char *const pszFailure = "VM-exit";
5717 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5718
5719 /* RIP. */
5720 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5721 {
5722 X86DESCATTR AttrCs;
5723 AttrCs.u = pVmcs->u32GuestCsAttr;
5724 if ( !fGstInLongMode
5725 || !AttrCs.n.u1Long)
5726 {
5727 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5728 { /* likely */ }
5729 else
5730 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5731 }
5732
5733 if ( fGstInLongMode
5734 && AttrCs.n.u1Long)
5735 {
5736 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5737 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5738 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5739 { /* likely */ }
5740 else
5741 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5742 }
5743 }
5744
5745 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5746 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5747 : pVmcs->u64GuestRFlags.s.Lo;
5748 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5749 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5750 { /* likely */ }
5751 else
5752 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5753
5754 if (!(uGuestRFlags & X86_EFL_VM))
5755 { /* likely */ }
5756 else
5757 {
5758 if ( fGstInLongMode
5759 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5760 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5761 }
5762
5763 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5764 {
5765 if (uGuestRFlags & X86_EFL_IF)
5766 { /* likely */ }
5767 else
5768 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5769 }
5770
5771 NOREF(pszInstr);
5772 NOREF(pszFailure);
5773 return VINF_SUCCESS;
5774}
5775
5776
5777/**
5778 * Checks guest non-register state as part of VM-entry.
5779 *
5780 * @param pVCpu The cross context virtual CPU structure.
5781 * @param pszInstr The VMX instruction name (for logging purposes).
5782 */
5783DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5784{
5785 /*
5786 * Guest non-register state.
5787 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5788 */
5789 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5790 const char *const pszFailure = "VM-exit";
5791
5792 /*
5793 * Activity state.
5794 */
5795 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5796 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5797 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5798 { /* likely */ }
5799 else
5800 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5801
5802 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5803 if ( !AttrSs.n.u2Dpl
5804 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5805 { /* likely */ }
5806 else
5807 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5808
5809 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5810 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5811 {
5812 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5813 { /* likely */ }
5814 else
5815 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5816 }
5817
5818 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5819 {
5820 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5821 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5822 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5823 switch (pVmcs->u32GuestActivityState)
5824 {
5825 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5826 {
5827 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5828 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5829 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5830 && ( uVector == X86_XCPT_DB
5831 || uVector == X86_XCPT_MC))
5832 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5833 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5834 { /* likely */ }
5835 else
5836 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5837 break;
5838 }
5839
5840 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5841 {
5842 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5843 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5844 && uVector == X86_XCPT_MC))
5845 { /* likely */ }
5846 else
5847 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5848 break;
5849 }
5850
5851 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5852 default:
5853 break;
5854 }
5855 }
5856
5857 /*
5858 * Interruptibility state.
5859 */
5860 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5861 { /* likely */ }
5862 else
5863 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5864
5865 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5866 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5867 { /* likely */ }
5868 else
5869 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5870
5871 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5872 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5873 { /* likely */ }
5874 else
5875 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5876
5877 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5878 {
5879 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5880 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5881 {
5882 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5883 { /* likely */ }
5884 else
5885 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5886 }
5887 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5888 {
5889 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5890 { /* likely */ }
5891 else
5892 {
5893 /*
5894 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5895 * We update the Exit qualification only when blocking-by-STI is set
5896 * without blocking-by-MovSS being set. Although in practise it does not
5897 * make much difference since the order of checks are implementation defined.
5898 */
5899 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5900 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5901 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5902 }
5903
5904 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5905 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5906 { /* likely */ }
5907 else
5908 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5909 }
5910 }
5911
5912 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5913 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5914 { /* likely */ }
5915 else
5916 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5917
5918 /* We don't support SGX yet. So enclave-interruption must not be set. */
5919 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5920 { /* likely */ }
5921 else
5922 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5923
5924 /*
5925 * Pending debug exceptions.
5926 */
5927 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5928 ? pVmcs->u64GuestPendingDbgXcpts.u
5929 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5930 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5931 { /* likely */ }
5932 else
5933 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5934
5935 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5936 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5937 {
5938 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5939 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5940 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5941 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5942
5943 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5944 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5945 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5946 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5947 }
5948
5949 /* We don't support RTM (Real-time Transactional Memory) yet. */
5950 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5951 { /* likely */ }
5952 else
5953 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5954
5955 /*
5956 * VMCS link pointer.
5957 */
5958 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5959 {
5960 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5961 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5962 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5963 { /* likely */ }
5964 else
5965 {
5966 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5967 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5968 }
5969
5970 /* Validate the address. */
5971 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5972 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5973 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5974 { /* likely */ }
5975 else
5976 {
5977 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5978 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5979 }
5980 }
5981
5982 NOREF(pszInstr);
5983 NOREF(pszFailure);
5984 return VINF_SUCCESS;
5985}
5986
5987
5988#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5989/**
5990 * Checks guest PDPTEs as part of VM-entry.
5991 *
5992 * @param pVCpu The cross context virtual CPU structure.
5993 * @param pszInstr The VMX instruction name (for logging purposes).
5994 */
5995static int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
5996{
5997 /*
5998 * Guest PDPTEs.
5999 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6000 */
6001 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6002 const char * const pszFailure = "VM-exit";
6003
6004 /*
6005 * When EPT is used, we only validate the PAE PDPTEs provided in the VMCS.
6006 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
6007 */
6008 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
6009 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
6010 {
6011 /* Get PDPTEs from the VMCS. */
6012 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6013 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6014 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6015 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6016 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6017
6018 /* Check validity of the PDPTEs. */
6019 bool const fValid = PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]);
6020 if (fValid)
6021 { /* likely */ }
6022 else
6023 {
6024 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6025 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6026 }
6027 }
6028
6029 NOREF(pszFailure);
6030 NOREF(pszInstr);
6031 return VINF_SUCCESS;
6032}
6033#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
6034
6035
6036/**
6037 * Checks guest-state as part of VM-entry.
6038 *
6039 * @returns VBox status code.
6040 * @param pVCpu The cross context virtual CPU structure.
6041 * @param pszInstr The VMX instruction name (for logging purposes).
6042 */
6043static int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6044{
6045 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6046 if (RT_SUCCESS(rc))
6047 {
6048 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6049 if (RT_SUCCESS(rc))
6050 {
6051 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6052 if (RT_SUCCESS(rc))
6053 {
6054 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6055 if (RT_SUCCESS(rc))
6056 {
6057 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6058#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6059 if (RT_SUCCESS(rc))
6060 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6061#endif
6062 }
6063 }
6064 }
6065 }
6066 return rc;
6067}
6068
6069
6070/**
6071 * Checks host-state as part of VM-entry.
6072 *
6073 * @returns VBox status code.
6074 * @param pVCpu The cross context virtual CPU structure.
6075 * @param pszInstr The VMX instruction name (for logging purposes).
6076 */
6077static int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6078{
6079 /*
6080 * Host Control Registers and MSRs.
6081 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6082 */
6083 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6084 const char * const pszFailure = "VMFail";
6085
6086 /* CR0 reserved bits. */
6087 {
6088 /* CR0 MB1 bits. */
6089 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu);
6090 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6091 { /* likely */ }
6092 else
6093 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6094
6095 /* CR0 MBZ bits. */
6096 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6097 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6098 { /* likely */ }
6099 else
6100 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6101 }
6102
6103 /* CR4 reserved bits. */
6104 {
6105 /* CR4 MB1 bits. */
6106 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6107 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6108 { /* likely */ }
6109 else
6110 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6111
6112 /* CR4 MBZ bits. */
6113 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6114 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6115 { /* likely */ }
6116 else
6117 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6118 }
6119
6120 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6121 {
6122 /* CR3 reserved bits. */
6123 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6124 { /* likely */ }
6125 else
6126 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6127
6128 /* SYSENTER ESP and SYSENTER EIP. */
6129 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6130 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6131 { /* likely */ }
6132 else
6133 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6134 }
6135
6136 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6137 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6138
6139 /* PAT MSR. */
6140 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6141 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6142 { /* likely */ }
6143 else
6144 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6145
6146 /* EFER MSR. */
6147 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6148 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6149 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6150 { /* likely */ }
6151 else
6152 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6153
6154 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6155 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6156 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6157 if ( fHostInLongMode == fHostLma
6158 && fHostInLongMode == fHostLme)
6159 { /* likely */ }
6160 else
6161 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6162
6163 /*
6164 * Host Segment and Descriptor-Table Registers.
6165 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6166 */
6167 /* Selector RPL and TI. */
6168 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6169 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6170 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6171 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6172 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6173 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6174 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6175 { /* likely */ }
6176 else
6177 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6178
6179 /* CS and TR selectors cannot be 0. */
6180 if ( pVmcs->HostCs
6181 && pVmcs->HostTr)
6182 { /* likely */ }
6183 else
6184 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6185
6186 /* SS cannot be 0 if 32-bit host. */
6187 if ( fHostInLongMode
6188 || pVmcs->HostSs)
6189 { /* likely */ }
6190 else
6191 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6192
6193 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6194 {
6195 /* FS, GS, GDTR, IDTR, TR base address. */
6196 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6197 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6198 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6199 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6200 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6201 { /* likely */ }
6202 else
6203 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6204 }
6205
6206 /*
6207 * Host address-space size for 64-bit CPUs.
6208 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6209 */
6210 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6211 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6212 {
6213 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6214
6215 /* Logical processor in IA-32e mode. */
6216 if (fCpuInLongMode)
6217 {
6218 if (fHostInLongMode)
6219 {
6220 /* PAE must be set. */
6221 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6222 { /* likely */ }
6223 else
6224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6225
6226 /* RIP must be canonical. */
6227 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6228 { /* likely */ }
6229 else
6230 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6231 }
6232 else
6233 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6234 }
6235 else
6236 {
6237 /* Logical processor is outside IA-32e mode. */
6238 if ( !fGstInLongMode
6239 && !fHostInLongMode)
6240 {
6241 /* PCIDE should not be set. */
6242 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6243 { /* likely */ }
6244 else
6245 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6246
6247 /* The high 32-bits of RIP MBZ. */
6248 if (!pVmcs->u64HostRip.s.Hi)
6249 { /* likely */ }
6250 else
6251 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6252 }
6253 else
6254 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6255 }
6256 }
6257 else
6258 {
6259 /* Host address-space size for 32-bit CPUs. */
6260 if ( !fGstInLongMode
6261 && !fHostInLongMode)
6262 { /* likely */ }
6263 else
6264 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6265 }
6266
6267 NOREF(pszInstr);
6268 NOREF(pszFailure);
6269 return VINF_SUCCESS;
6270}
6271
6272
6273#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6274/**
6275 * Checks the EPT pointer VMCS field as part of VM-entry.
6276 *
6277 * @returns VBox status code.
6278 * @param pVCpu The cross context virtual CPU structure.
6279 * @param uEptPtr The EPT pointer to check.
6280 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
6281 * updated on success). Optional, can be NULL.
6282 */
6283static int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr, VMXVDIAG *penmVmxDiag) RT_NOEXCEPT
6284{
6285 VMXVDIAG enmVmxDiag;
6286
6287 /* Reserved bits. */
6288 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
6289 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
6290 if (uEptPtr & fValidMask)
6291 {
6292 /* Memory Type. */
6293 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
6294 uint8_t const fMemType = RT_BF_GET(uEptPtr, VMX_BF_EPTP_MEMTYPE);
6295 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
6296 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
6297 || ( fMemType == VMX_EPTP_MEMTYPE_UC
6298 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
6299 {
6300 /*
6301 * Page walk length (PML4).
6302 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
6303 * of 5 but that seems to be removed from the latest specs. leaving only PML4
6304 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
6305 */
6306 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
6307 if (RT_BF_GET(uEptPtr, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
6308 {
6309 /* Access and dirty bits support in EPT structures. */
6310 if ( !RT_BF_GET(uEptPtr, VMX_BF_EPTP_ACCESS_DIRTY)
6311 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
6312 return VINF_SUCCESS;
6313
6314 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
6315 }
6316 else
6317 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
6318 }
6319 else
6320 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
6321 }
6322 else
6323 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
6324
6325 if (penmVmxDiag)
6326 *penmVmxDiag = enmVmxDiag;
6327 return VERR_VMX_VMENTRY_FAILED;
6328}
6329#endif
6330
6331
6332/**
6333 * Checks VMCS controls fields as part of VM-entry.
6334 *
6335 * @returns VBox status code.
6336 * @param pVCpu The cross context virtual CPU structure.
6337 * @param pszInstr The VMX instruction name (for logging purposes).
6338 *
6339 * @remarks This may update secondary-processor based VM-execution control fields
6340 * in the current VMCS if necessary.
6341 */
6342static int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6343{
6344 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6345 const char * const pszFailure = "VMFail";
6346 bool const fVmxTrueMsrs = RT_BOOL(pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
6347
6348 /*
6349 * VM-execution controls.
6350 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6351 */
6352 {
6353 /* Pin-based VM-execution controls. */
6354 {
6355 VMXCTLSMSR const PinCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TruePinCtls
6356 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6357 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6358 { /* likely */ }
6359 else
6360 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6361
6362 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6363 { /* likely */ }
6364 else
6365 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6366 }
6367
6368 /* Processor-based VM-execution controls. */
6369 {
6370 VMXCTLSMSR const ProcCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueProcCtls
6371 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6372 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6373 { /* likely */ }
6374 else
6375 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6376
6377 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6378 { /* likely */ }
6379 else
6380 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6381 }
6382
6383 /* Secondary processor-based VM-execution controls. */
6384 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6385 {
6386 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6387 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6388 { /* likely */ }
6389 else
6390 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6391
6392 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6393 { /* likely */ }
6394 else
6395 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6396 }
6397 else
6398 Assert(!pVmcs->u32ProcCtls2);
6399
6400 /* CR3-target count. */
6401 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6402 { /* likely */ }
6403 else
6404 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6405
6406 /* I/O bitmaps physical addresses. */
6407 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6408 {
6409 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6410 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6411 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6412 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6413 { /* likely */ }
6414 else
6415 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6416
6417 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6418 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6419 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6420 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6421 { /* likely */ }
6422 else
6423 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6424 }
6425
6426 /* MSR bitmap physical address. */
6427 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6428 {
6429 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6430 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6431 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6432 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6433 { /* likely */ }
6434 else
6435 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6436 }
6437
6438 /* TPR shadow related controls. */
6439 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6440 {
6441 /* Virtual-APIC page physical address. */
6442 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6443 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6444 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6445 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6446 { /* likely */ }
6447 else
6448 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6449
6450 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6451 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6452 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6453 { /* likely */ }
6454 else
6455 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6456
6457 /* The rest done XXX document */
6458 }
6459 else
6460 {
6461 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6462 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6463 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6464 { /* likely */ }
6465 else
6466 {
6467 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6468 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6469 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6470 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6471 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6472 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6473 }
6474 }
6475
6476 /* NMI exiting and virtual-NMIs. */
6477 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6478 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6479 { /* likely */ }
6480 else
6481 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6482
6483 /* Virtual-NMIs and NMI-window exiting. */
6484 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6485 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6486 { /* likely */ }
6487 else
6488 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6489
6490 /* Virtualize APIC accesses. */
6491 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6492 {
6493 /* APIC-access physical address. */
6494 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6495 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6496 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6497 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6498 { /* likely */ }
6499 else
6500 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6501
6502 /*
6503 * Disallow APIC-access page and virtual-APIC page from being the same address.
6504 * Note! This is not an Intel requirement, but one imposed by our implementation.
6505 */
6506 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6507 * redirecting accesses between the APIC-access page and the virtual-APIC
6508 * page. If any nested hypervisor requires this, we can implement it later. */
6509 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6510 {
6511 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6512 if (GCPhysVirtApic != GCPhysApicAccess)
6513 { /* likely */ }
6514 else
6515 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6516 }
6517 }
6518
6519 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6520 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6521 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6522 { /* likely */ }
6523 else
6524 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6525
6526 /* Virtual-interrupt delivery requires external interrupt exiting. */
6527 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6528 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6529 { /* likely */ }
6530 else
6531 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6532
6533 /* VPID. */
6534 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6535 || pVmcs->u16Vpid != 0)
6536 { /* likely */ }
6537 else
6538 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6539
6540#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6541 /* Extended-Page-Table Pointer (EPTP). */
6542 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6543 {
6544 VMXVDIAG enmVmxDiag;
6545 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, pVmcs->u64EptPtr.u, &enmVmxDiag);
6546 if (RT_SUCCESS(rc))
6547 { /* likely */ }
6548 else
6549 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6550 }
6551#else
6552 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6553 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST));
6554#endif
6555 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6556 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6557 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6558 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6559 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6560 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6561
6562 /* VMCS shadowing. */
6563 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6564 {
6565 /* VMREAD-bitmap physical address. */
6566 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6567 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6568 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6569 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6570 { /* likely */ }
6571 else
6572 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6573
6574 /* VMWRITE-bitmap physical address. */
6575 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6576 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6577 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6578 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6579 { /* likely */ }
6580 else
6581 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6582 }
6583 }
6584
6585 /*
6586 * VM-exit controls.
6587 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6588 */
6589 {
6590 VMXCTLSMSR const ExitCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueExitCtls
6591 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6592 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6593 { /* likely */ }
6594 else
6595 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6596
6597 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6598 { /* likely */ }
6599 else
6600 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6601
6602 /* Save preemption timer without activating it. */
6603 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6604 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6605 { /* likely */ }
6606 else
6607 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6608
6609 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6610 if (pVmcs->u32ExitMsrStoreCount)
6611 {
6612 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6613 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6614 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6615 { /* likely */ }
6616 else
6617 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6618 }
6619
6620 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6621 if (pVmcs->u32ExitMsrLoadCount)
6622 {
6623 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6624 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6625 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6626 { /* likely */ }
6627 else
6628 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6629 }
6630 }
6631
6632 /*
6633 * VM-entry controls.
6634 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6635 */
6636 {
6637 VMXCTLSMSR const EntryCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueEntryCtls
6638 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6639 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6640 { /* likely */ }
6641 else
6642 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6643
6644 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6645 { /* likely */ }
6646 else
6647 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6648
6649 /* Event injection. */
6650 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6651 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6652 {
6653 /* Type and vector. */
6654 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6655 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6656 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6657 if ( !uRsvd
6658 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6659 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6660 { /* likely */ }
6661 else
6662 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6663
6664 /* Exception error code. */
6665 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6666 {
6667 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6668 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6669 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6670 { /* likely */ }
6671 else
6672 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6673
6674 /* Exceptions that provide an error code. */
6675 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6676 && ( uVector == X86_XCPT_DF
6677 || uVector == X86_XCPT_TS
6678 || uVector == X86_XCPT_NP
6679 || uVector == X86_XCPT_SS
6680 || uVector == X86_XCPT_GP
6681 || uVector == X86_XCPT_PF
6682 || uVector == X86_XCPT_AC))
6683 { /* likely */ }
6684 else
6685 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6686
6687 /* Exception error-code reserved bits. */
6688 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6689 { /* likely */ }
6690 else
6691 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6692
6693 /* Injecting a software interrupt, software exception or privileged software exception. */
6694 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6695 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6696 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6697 {
6698 /* Instruction length must be in the range 0-15. */
6699 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6700 { /* likely */ }
6701 else
6702 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6703
6704 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6705 if ( pVmcs->u32EntryInstrLen != 0
6706 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6707 { /* likely */ }
6708 else
6709 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6710 }
6711 }
6712 }
6713
6714 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6715 if (pVmcs->u32EntryMsrLoadCount)
6716 {
6717 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6718 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6719 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6720 { /* likely */ }
6721 else
6722 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6723 }
6724
6725 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6726 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6727 }
6728
6729 NOREF(pszInstr);
6730 NOREF(pszFailure);
6731 return VINF_SUCCESS;
6732}
6733
6734
6735/**
6736 * Loads the guest control registers, debug register and some MSRs as part of
6737 * VM-entry.
6738 *
6739 * @param pVCpu The cross context virtual CPU structure.
6740 */
6741static void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
6742{
6743 /*
6744 * Load guest control registers, debug registers and MSRs.
6745 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6746 */
6747 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6748
6749 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6750 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6751 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6752 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6753 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6754 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6755
6756 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6757 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6758
6759 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6760 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6761 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6762
6763 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6764 {
6765 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6766
6767 /* EFER MSR. */
6768 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6769 {
6770 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6771 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6772 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6773 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6774 if (fGstInLongMode)
6775 {
6776 /* If the nested-guest is in long mode, LMA and LME are both set. */
6777 Assert(fGstPaging);
6778 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6779 }
6780 else
6781 {
6782 /*
6783 * If the nested-guest is outside long mode:
6784 * - With paging: LMA is cleared, LME is cleared.
6785 * - Without paging: LMA is cleared, LME is left unmodified.
6786 */
6787 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6788 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6789 }
6790 }
6791 /* else: see below. */
6792 }
6793
6794 /* PAT MSR. */
6795 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6796 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6797
6798 /* EFER MSR. */
6799 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6800 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6801
6802 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6803 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6804
6805 /* We don't support IA32_BNDCFGS MSR yet. */
6806 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6807
6808 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6809}
6810
6811
6812/**
6813 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6814 *
6815 * @param pVCpu The cross context virtual CPU structure.
6816 */
6817static void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
6818{
6819 /*
6820 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6821 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6822 */
6823 /* CS, SS, ES, DS, FS, GS. */
6824 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6825 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6826 {
6827 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6828 CPUMSELREG VmcsSelReg;
6829 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6830 AssertRC(rc); NOREF(rc);
6831 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6832 {
6833 pGstSelReg->Sel = VmcsSelReg.Sel;
6834 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6835 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6836 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6837 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6838 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6839 }
6840 else
6841 {
6842 pGstSelReg->Sel = VmcsSelReg.Sel;
6843 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6844 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6845 switch (iSegReg)
6846 {
6847 case X86_SREG_CS:
6848 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6849 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6850 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6851 break;
6852
6853 case X86_SREG_SS:
6854 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6855 pGstSelReg->u32Limit = 0;
6856 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6857 break;
6858
6859 case X86_SREG_ES:
6860 case X86_SREG_DS:
6861 pGstSelReg->u64Base = 0;
6862 pGstSelReg->u32Limit = 0;
6863 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6864 break;
6865
6866 case X86_SREG_FS:
6867 case X86_SREG_GS:
6868 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6869 pGstSelReg->u32Limit = 0;
6870 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6871 break;
6872 }
6873 Assert(pGstSelReg->Attr.n.u1Unusable);
6874 }
6875 }
6876
6877 /* LDTR. */
6878 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6879 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6880 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6881 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6882 {
6883 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6884 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6885 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6886 }
6887 else
6888 {
6889 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6890 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6891 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6892 }
6893
6894 /* TR. */
6895 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6896 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6897 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6898 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6899 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6900 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6901 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6902
6903 /* GDTR. */
6904 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6905 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6906
6907 /* IDTR. */
6908 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6909 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6910}
6911
6912
6913/**
6914 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6915 *
6916 * @returns VBox status code.
6917 * @param pVCpu The cross context virtual CPU structure.
6918 * @param pszInstr The VMX instruction name (for logging purposes).
6919 */
6920static int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6921{
6922 /*
6923 * Load guest MSRs.
6924 * See Intel spec. 26.4 "Loading MSRs".
6925 */
6926 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6927 const char *const pszFailure = "VM-exit";
6928
6929 /*
6930 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6931 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6932 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6933 */
6934 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6935 if (!cMsrs)
6936 return VINF_SUCCESS;
6937
6938 /*
6939 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6940 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6941 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6942 */
6943 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6944 if (fIsMsrCountValid)
6945 { /* likely */ }
6946 else
6947 {
6948 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6949 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6950 }
6951
6952 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6953 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6954 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6955 if (RT_SUCCESS(rc))
6956 {
6957 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6958 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6959 {
6960 if ( !pMsr->u32Reserved
6961 && pMsr->u32Msr != MSR_K8_FS_BASE
6962 && pMsr->u32Msr != MSR_K8_GS_BASE
6963 && pMsr->u32Msr != MSR_K6_EFER
6964 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
6965 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
6966 {
6967 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
6968 if (rcStrict == VINF_SUCCESS)
6969 continue;
6970
6971 /*
6972 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
6973 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
6974 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
6975 * further by our own, specific diagnostic code. Later, we can try implement handling of the
6976 * MSR in ring-0 if possible, or come up with a better, generic solution.
6977 */
6978 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6979 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
6980 ? kVmxVDiag_Vmentry_MsrLoadRing3
6981 : kVmxVDiag_Vmentry_MsrLoad;
6982 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6983 }
6984 else
6985 {
6986 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
6987 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
6988 }
6989 }
6990 }
6991 else
6992 {
6993 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
6994 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
6995 }
6996
6997 NOREF(pszInstr);
6998 NOREF(pszFailure);
6999 return VINF_SUCCESS;
7000}
7001
7002
7003/**
7004 * Loads the guest-state non-register state as part of VM-entry.
7005 *
7006 * @returns VBox status code.
7007 * @param pVCpu The cross context virtual CPU structure.
7008 * @param pszInstr The VMX instruction name (for logging purposes).
7009 *
7010 * @remarks This must be called only after loading the nested-guest register state
7011 * (especially nested-guest RIP).
7012 */
7013static int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7014{
7015 /*
7016 * Load guest non-register state.
7017 * See Intel spec. 26.6 "Special Features of VM Entry"
7018 */
7019 const char *const pszFailure = "VM-exit";
7020 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7021
7022 /*
7023 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7024 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7025 *
7026 * See Intel spec. 26.6.1 "Interruptibility State".
7027 */
7028 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7029 if ( !fEntryVectoring
7030 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7031 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7032 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7033 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7034
7035 /* NMI blocking. */
7036 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7037 {
7038 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7039 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7040 else
7041 {
7042 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7043 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7044 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7045 }
7046 }
7047 else
7048 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7049
7050 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7051
7052 /*
7053 * Set PGM's copy of the EPT pointer.
7054 * The EPTP has already been validated while checking guest state.
7055 *
7056 * It is important to do this prior to mapping PAE PDPTEs (below).
7057 */
7058 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7059 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
7060
7061 /*
7062 * Load the guest's PAE PDPTEs.
7063 */
7064 if (iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
7065 {
7066 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7067 {
7068 /*
7069 * With EPT, we've already validated these while checking the guest state.
7070 * Just load them directly from the VMCS here.
7071 */
7072 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
7073 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
7074 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
7075 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
7076 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
7077 AssertCompile(RT_ELEMENTS(aPaePdptes) == RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes));
7078 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.GstCtx.aPaePdpes); i++)
7079 pVCpu->cpum.GstCtx.aPaePdpes[i].u = aPaePdptes[i].u;
7080 }
7081 else
7082 {
7083 /*
7084 * Without EPT, we must load the PAE PDPTEs referenced by CR3.
7085 * This involves loading (and mapping) CR3 and validating them now.
7086 */
7087 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
7088 if (RT_SUCCESS(rc))
7089 { /* likely */ }
7090 else
7091 {
7092 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
7093 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
7094 }
7095 }
7096 }
7097
7098 /* VPID is irrelevant. We don't support VPID yet. */
7099
7100 /* Clear address-range monitoring. */
7101 EMMonitorWaitClear(pVCpu);
7102
7103 return VINF_SUCCESS;
7104}
7105
7106
7107/**
7108 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
7109 *
7110 * @param pVCpu The cross context virtual CPU structure.
7111 * @param pszInstr The VMX instruction name (for logging purposes).
7112 *
7113 * @remarks This assumes various VMCS related data structure pointers have already
7114 * been verified prior to calling this function.
7115 */
7116static int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7117{
7118 const char *const pszFailure = "VM-exit";
7119 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7120
7121 /*
7122 * Virtualize APIC accesses.
7123 */
7124 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7125 {
7126 /* APIC-access physical address. */
7127 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
7128
7129 /*
7130 * Register the handler for the APIC-access page.
7131 *
7132 * We don't deregister the APIC-access page handler during the VM-exit as a different
7133 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
7134 *
7135 * We leave the page registered until the first access that happens outside VMX non-root
7136 * mode. Guest software is allowed to access structures such as the APIC-access page
7137 * only when no logical processor with a current VMCS references it in VMX non-root mode,
7138 * otherwise it can lead to unpredictable behavior including guest triple-faults.
7139 *
7140 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7141 */
7142 if (!PGMHandlerPhysicalIsRegistered(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
7143 {
7144 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7145 int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess | X86_PAGE_4K_OFFSET_MASK,
7146 pVM->iem.s.hVmxApicAccessPage, 0 /*uUser*/, NULL /*pszDesc*/);
7147 if (RT_SUCCESS(rc))
7148 {
7149 /*
7150 * This to make double sure we trigger EPT violations (rather than EPT misconfigs)
7151 * in case we somehow managed to sync the page when CPUMIsGuestVmxApicAccessPageAddr
7152 * returned false while sycing its PTE in (SyncHandlerPte).
7153 */
7154 PGMShwMakePageNotPresent(pVCpu, GCPhysApicAccess, 0 /* fOpFlags */);
7155 }
7156 else
7157 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
7158 }
7159 }
7160
7161 /*
7162 * VMCS shadowing.
7163 */
7164 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7165 {
7166 /* Read the VMREAD-bitmap. */
7167 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
7168 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
7169 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
7170 if (RT_SUCCESS(rc))
7171 { /* likely */ }
7172 else
7173 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
7174
7175 /* Read the VMWRITE-bitmap. */
7176 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
7177 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
7178 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
7179 if (RT_SUCCESS(rc))
7180 { /* likely */ }
7181 else
7182 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
7183 }
7184
7185 /*
7186 * I/O bitmaps.
7187 */
7188 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
7189 {
7190 /* Read the IO bitmap A. */
7191 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
7192 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
7193 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
7194 if (RT_SUCCESS(rc))
7195 { /* likely */ }
7196 else
7197 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
7198
7199 /* Read the IO bitmap B. */
7200 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
7201 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
7202 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
7203 if (RT_SUCCESS(rc))
7204 { /* likely */ }
7205 else
7206 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
7207 }
7208
7209 /*
7210 * TPR shadow and Virtual-APIC page.
7211 */
7212 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7213 {
7214 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
7215 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7216 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
7217 {
7218 /* Read the VTPR from the virtual-APIC page. */
7219 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
7220 uint8_t u8VTpr;
7221 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
7222 if (RT_SUCCESS(rc))
7223 { /* likely */ }
7224 else
7225 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
7226
7227 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
7228 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
7229 { /* likely */ }
7230 else
7231 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
7232 }
7233 }
7234
7235 /*
7236 * VMCS link pointer.
7237 */
7238 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
7239 {
7240 /* Read the VMCS-link pointer from guest memory. */
7241 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
7242 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
7243 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
7244 if (RT_SUCCESS(rc))
7245 { /* likely */ }
7246 else
7247 {
7248 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7249 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
7250 }
7251
7252 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7253 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
7254 { /* likely */ }
7255 else
7256 {
7257 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7258 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
7259 }
7260
7261 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
7262 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7263 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
7264 { /* likely */ }
7265 else
7266 {
7267 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7268 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
7269 }
7270
7271 /* Update our cache of the guest physical address of the shadow VMCS. */
7272 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
7273 }
7274
7275 /*
7276 * MSR bitmap.
7277 */
7278 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7279 {
7280 /* Read the MSR bitmap. */
7281 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
7282 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
7283 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
7284 if (RT_SUCCESS(rc))
7285 { /* likely */ }
7286 else
7287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
7288 }
7289
7290 NOREF(pszFailure);
7291 NOREF(pszInstr);
7292 return VINF_SUCCESS;
7293}
7294
7295
7296/**
7297 * Loads the guest-state as part of VM-entry.
7298 *
7299 * @returns VBox status code.
7300 * @param pVCpu The cross context virtual CPU structure.
7301 * @param pszInstr The VMX instruction name (for logging purposes).
7302 *
7303 * @remarks This must be done after all the necessary steps prior to loading of
7304 * guest-state (e.g. checking various VMCS state).
7305 */
7306static int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7307{
7308 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
7309 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7310
7311 /* Load guest segment registers. */
7312 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7313
7314 /*
7315 * Load guest RIP, RSP and RFLAGS.
7316 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7317 */
7318 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7319 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7320 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7321 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7322
7323 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7324 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7325 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7326
7327 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
7328 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
7329 if (rc == VINF_SUCCESS)
7330 { /* likely */ }
7331 else
7332 return rc;
7333
7334 /* Load VMX related structures and state referenced by the VMCS. */
7335 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
7336 if (rc == VINF_SUCCESS)
7337 { /* likely */ }
7338 else
7339 return rc;
7340
7341 NOREF(pszInstr);
7342 return VINF_SUCCESS;
7343}
7344
7345
7346/**
7347 * Returns whether there are is a pending debug exception on VM-entry.
7348 *
7349 * @param pVCpu The cross context virtual CPU structure.
7350 * @param pszInstr The VMX instruction name (for logging purposes).
7351 */
7352static bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7353{
7354 /*
7355 * Pending debug exceptions.
7356 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7357 */
7358 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7359 Assert(pVmcs);
7360
7361 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7362 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7363 if (fPendingDbgXcpt)
7364 {
7365 uint8_t uEntryIntInfoType;
7366 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7367 if (fEntryVectoring)
7368 {
7369 switch (uEntryIntInfoType)
7370 {
7371 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7372 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7373 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7374 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7375 fPendingDbgXcpt = false;
7376 break;
7377
7378 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7379 {
7380 /*
7381 * Whether the pending debug exception for software exceptions other than
7382 * #BP and #OF is delivered after injecting the exception or is discard
7383 * is CPU implementation specific. We will discard them (easier).
7384 */
7385 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7386 if ( uVector != X86_XCPT_BP
7387 && uVector != X86_XCPT_OF)
7388 fPendingDbgXcpt = false;
7389 RT_FALL_THRU();
7390 }
7391 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7392 {
7393 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7394 fPendingDbgXcpt = false;
7395 break;
7396 }
7397 }
7398 }
7399 else
7400 {
7401 /*
7402 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7403 * pending debug exception is held pending or is discarded is CPU implementation
7404 * specific. We will discard them (easier).
7405 */
7406 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7407 fPendingDbgXcpt = false;
7408
7409 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7410 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7411 fPendingDbgXcpt = false;
7412 }
7413 }
7414
7415 NOREF(pszInstr);
7416 return fPendingDbgXcpt;
7417}
7418
7419
7420/**
7421 * Set up the monitor-trap flag (MTF).
7422 *
7423 * @param pVCpu The cross context virtual CPU structure.
7424 * @param pszInstr The VMX instruction name (for logging purposes).
7425 */
7426static void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7427{
7428 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7429 Assert(pVmcs);
7430 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7431 {
7432 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7433 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7434 }
7435 else
7436 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7437 NOREF(pszInstr);
7438}
7439
7440
7441/**
7442 * Sets up NMI-window exiting.
7443 *
7444 * @param pVCpu The cross context virtual CPU structure.
7445 * @param pszInstr The VMX instruction name (for logging purposes).
7446 */
7447static void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7448{
7449 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7450 Assert(pVmcs);
7451 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7452 {
7453 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7454 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7455 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7456 }
7457 else
7458 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7459 NOREF(pszInstr);
7460}
7461
7462
7463/**
7464 * Sets up interrupt-window exiting.
7465 *
7466 * @param pVCpu The cross context virtual CPU structure.
7467 * @param pszInstr The VMX instruction name (for logging purposes).
7468 */
7469static void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7470{
7471 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7472 Assert(pVmcs);
7473 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7474 {
7475 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7476 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7477 }
7478 else
7479 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7480 NOREF(pszInstr);
7481}
7482
7483
7484/**
7485 * Set up the VMX-preemption timer.
7486 *
7487 * @param pVCpu The cross context virtual CPU structure.
7488 * @param pszInstr The VMX instruction name (for logging purposes).
7489 */
7490static void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7491{
7492 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7493 Assert(pVmcs);
7494 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7495 {
7496 /*
7497 * If the timer is 0, we must cause a VM-exit before executing the first
7498 * nested-guest instruction. So we can flag as though the timer has already
7499 * expired and we will check and cause a VM-exit at the right priority elsewhere
7500 * in the code.
7501 */
7502 uint64_t uEntryTick;
7503 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7504 if (uPreemptTimer)
7505 {
7506 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7507 AssertRC(rc);
7508 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7509 }
7510 else
7511 {
7512 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7513 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7514 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7515 }
7516
7517 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7518 }
7519 else
7520 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7521
7522 NOREF(pszInstr);
7523}
7524
7525
7526/**
7527 * Injects an event using TRPM given a VM-entry interruption info. and related
7528 * fields.
7529 *
7530 * @param pVCpu The cross context virtual CPU structure.
7531 * @param pszInstr The VMX instruction name (for logging purposes).
7532 * @param uEntryIntInfo The VM-entry interruption info.
7533 * @param uErrCode The error code associated with the event if any.
7534 * @param cbInstr The VM-entry instruction length (for software
7535 * interrupts and software exceptions). Pass 0
7536 * otherwise.
7537 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7538 */
7539static void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7540 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress) RT_NOEXCEPT
7541{
7542 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7543
7544 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7545 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7546 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7547
7548 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7549
7550 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7551 AssertRC(rc);
7552 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7553
7554 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7555 {
7556 TRPMSetErrorCode(pVCpu, uErrCode);
7557 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7558 }
7559
7560 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7561 {
7562 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7563 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7564 }
7565 else
7566 {
7567 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7568 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7569 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7570 {
7571 TRPMSetInstrLength(pVCpu, cbInstr);
7572 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7573 }
7574 }
7575
7576 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7577 {
7578 TRPMSetTrapDueToIcebp(pVCpu);
7579 Log(("%s: Injecting: icebp\n", pszInstr));
7580 }
7581
7582 NOREF(pszInstr);
7583}
7584
7585
7586/**
7587 * Performs event injection (if any) as part of VM-entry.
7588 *
7589 * @param pVCpu The cross context virtual CPU structure.
7590 * @param pszInstr The VMX instruction name (for logging purposes).
7591 */
7592static void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7593{
7594 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7595
7596 /*
7597 * Inject events.
7598 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7599 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7600 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7601 * the actually delivery of this event.
7602 *
7603 * See Intel spec. 26.5 "Event Injection".
7604 */
7605 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7606 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7607
7608 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7609 if (fEntryIntInfoValid)
7610 {
7611 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7612 {
7613 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7614 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7615 }
7616 else
7617 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7618 pVCpu->cpum.GstCtx.cr2);
7619
7620 /*
7621 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7622 *
7623 * However, we do it here on VM-entry as well because while it isn't visible to guest
7624 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7625 * execution using hardware-assisted VMX, it will not be try to inject the event again.
7626 *
7627 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7628 */
7629 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7630 }
7631 else
7632 {
7633 /*
7634 * Inject any pending guest debug exception.
7635 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7636 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7637 */
7638 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7639 if (fPendingDbgXcpt)
7640 {
7641 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7642 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7643 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7644 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7645 0 /* GCPtrFaultAddress */);
7646 }
7647 }
7648
7649 NOREF(pszInstr);
7650}
7651
7652
7653/**
7654 * Initializes all read-only VMCS fields as part of VM-entry.
7655 *
7656 * @param pVCpu The cross context virtual CPU structure.
7657 */
7658static void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu) RT_NOEXCEPT
7659{
7660 /*
7661 * Any VMCS field which we do not establish on every VM-exit but may potentially
7662 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7663 * specified to be undefined, needs to be initialized here.
7664 *
7665 * Thus, it is especially important to clear the Exit qualification field
7666 * since it must be zero for VM-exits where it is not used. Similarly, the
7667 * VM-exit interruption information field's valid bit needs to be cleared for
7668 * the same reasons.
7669 */
7670 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7671 Assert(pVmcs);
7672
7673 /* 16-bit (none currently). */
7674 /* 32-bit. */
7675 pVmcs->u32RoVmInstrError = 0;
7676 pVmcs->u32RoExitReason = 0;
7677 pVmcs->u32RoExitIntInfo = 0;
7678 pVmcs->u32RoExitIntErrCode = 0;
7679 pVmcs->u32RoIdtVectoringInfo = 0;
7680 pVmcs->u32RoIdtVectoringErrCode = 0;
7681 pVmcs->u32RoExitInstrLen = 0;
7682 pVmcs->u32RoExitInstrInfo = 0;
7683
7684 /* 64-bit. */
7685 pVmcs->u64RoGuestPhysAddr.u = 0;
7686
7687 /* Natural-width. */
7688 pVmcs->u64RoExitQual.u = 0;
7689 pVmcs->u64RoIoRcx.u = 0;
7690 pVmcs->u64RoIoRsi.u = 0;
7691 pVmcs->u64RoIoRdi.u = 0;
7692 pVmcs->u64RoIoRip.u = 0;
7693 pVmcs->u64RoGuestLinearAddr.u = 0;
7694}
7695
7696
7697/**
7698 * VMLAUNCH/VMRESUME instruction execution worker.
7699 *
7700 * @returns Strict VBox status code.
7701 * @param pVCpu The cross context virtual CPU structure.
7702 * @param cbInstr The instruction length in bytes.
7703 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7704 * VMXINSTRID_VMRESUME).
7705 *
7706 * @remarks Common VMX instruction checks are already expected to by the caller,
7707 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7708 */
7709static VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId) RT_NOEXCEPT
7710{
7711# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7712 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7713 return VINF_EM_RAW_EMULATE_INSTR;
7714# else
7715 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7716 || uInstrId == VMXINSTRID_VMRESUME);
7717 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7718
7719 /* Nested-guest intercept. */
7720 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7721 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7722
7723 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7724
7725 /*
7726 * Basic VM-entry checks.
7727 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7728 * The checks following that do not have to follow a specific order.
7729 *
7730 * See Intel spec. 26.1 "Basic VM-entry Checks".
7731 */
7732
7733 /* CPL. */
7734 if (pVCpu->iem.s.uCpl == 0)
7735 { /* likely */ }
7736 else
7737 {
7738 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7739 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7740 return iemRaiseGeneralProtectionFault0(pVCpu);
7741 }
7742
7743 /* Current VMCS valid. */
7744 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7745 { /* likely */ }
7746 else
7747 {
7748 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7749 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7750 iemVmxVmFailInvalid(pVCpu);
7751 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7752 return VINF_SUCCESS;
7753 }
7754
7755 /* Current VMCS is not a shadow VMCS. */
7756 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7757 { /* likely */ }
7758 else
7759 {
7760 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7761 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7762 iemVmxVmFailInvalid(pVCpu);
7763 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7764 return VINF_SUCCESS;
7765 }
7766
7767 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7768 * use block-by-STI here which is not quite correct. */
7769 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7770 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7771 { /* likely */ }
7772 else
7773 {
7774 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7775 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7776 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7777 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7778 return VINF_SUCCESS;
7779 }
7780
7781 if (uInstrId == VMXINSTRID_VMLAUNCH)
7782 {
7783 /* VMLAUNCH with non-clear VMCS. */
7784 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7785 { /* likely */ }
7786 else
7787 {
7788 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7789 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7790 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7791 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7792 return VINF_SUCCESS;
7793 }
7794 }
7795 else
7796 {
7797 /* VMRESUME with non-launched VMCS. */
7798 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7799 { /* likely */ }
7800 else
7801 {
7802 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7803 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7804 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7805 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7806 return VINF_SUCCESS;
7807 }
7808 }
7809
7810 /*
7811 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7812 * while entering VMX non-root mode. We do some of this while checking VM-execution
7813 * controls. The nested hypervisor should not make assumptions and cannot expect
7814 * predictable behavior if changes to these structures are made in guest memory while
7815 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7816 * modify them anyway as we cache them in host memory.
7817 *
7818 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7819 */
7820 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7821 Assert(pVmcs);
7822 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7823
7824 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7825 if (RT_SUCCESS(rc))
7826 {
7827 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7828 if (RT_SUCCESS(rc))
7829 {
7830 /*
7831 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7832 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7833 * ones that may occur during VM-entry below).
7834 */
7835 iemVmxVmentryInitReadOnlyFields(pVCpu);
7836
7837 /*
7838 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7839 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7840 * VM-exit when required.
7841 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7842 */
7843 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7844
7845 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7846 if (RT_SUCCESS(rc))
7847 {
7848 /*
7849 * We've now entered nested-guest execution.
7850 *
7851 * It is important do this prior to loading the guest state because
7852 * as part of loading the guest state, PGM (and perhaps other components
7853 * in the future) relies on detecting whether VMX non-root mode has been
7854 * entered.
7855 */
7856 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7857
7858 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7859 if (RT_SUCCESS(rc))
7860 {
7861 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7862 if (RT_SUCCESS(rc))
7863 {
7864 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7865
7866 /* VMLAUNCH instruction must update the VMCS launch state. */
7867 if (uInstrId == VMXINSTRID_VMLAUNCH)
7868 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7869
7870 /* Perform the VMX transition (PGM updates). */
7871 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7872 if (rcStrict == VINF_SUCCESS)
7873 { /* likely */ }
7874 else if (RT_SUCCESS(rcStrict))
7875 {
7876 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7877 VBOXSTRICTRC_VAL(rcStrict)));
7878 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7879 }
7880 else
7881 {
7882 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7883 return rcStrict;
7884 }
7885
7886 /* Paranoia. */
7887 Assert(rcStrict == VINF_SUCCESS);
7888
7889 /*
7890 * The priority of potential VM-exits during VM-entry is important.
7891 * The priorities of VM-exits and events are listed from highest
7892 * to lowest as follows:
7893 *
7894 * 1. Event injection.
7895 * 2. Trap on task-switch (T flag set in TSS).
7896 * 3. TPR below threshold / APIC-write.
7897 * 4. SMI, INIT.
7898 * 5. MTF exit.
7899 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7900 * 7. VMX-preemption timer.
7901 * 9. NMI-window exit.
7902 * 10. NMI injection.
7903 * 11. Interrupt-window exit.
7904 * 12. Virtual-interrupt injection.
7905 * 13. Interrupt injection.
7906 * 14. Process next instruction (fetch, decode, execute).
7907 */
7908
7909 /* Setup VMX-preemption timer. */
7910 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7911
7912 /* Setup monitor-trap flag. */
7913 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7914
7915 /* Setup NMI-window exiting. */
7916 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7917
7918 /* Setup interrupt-window exiting. */
7919 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7920
7921 /*
7922 * Inject any event that the nested hypervisor wants to inject.
7923 * Note! We cannot immediately perform the event injection here as we may have
7924 * pending PGM operations to perform due to switching page tables and/or
7925 * mode.
7926 */
7927 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7928
7929# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7930 /* Reschedule to IEM-only execution of the nested-guest. */
7931 LogFlow(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7932 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7933 if (rcSched != VINF_SUCCESS)
7934 iemSetPassUpStatus(pVCpu, rcSched);
7935# endif
7936
7937 /* Finally, done. */
7938 LogFlow(("%s: cs:rip=%#04x:%#RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64 (%#RX64)\n",
7939 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7940 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7941 pVCpu->cpum.GstCtx.msrEFER, pVmcs->u64GuestEferMsr.u));
7942 return VINF_SUCCESS;
7943 }
7944 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7945 }
7946 }
7947 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7948 }
7949
7950 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7951 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7952 return VINF_SUCCESS;
7953 }
7954
7955 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7956 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7957 return VINF_SUCCESS;
7958# endif
7959}
7960
7961
7962/**
7963 * Interface for HM and EM to emulate the VMLAUNCH/VMRESUME instruction.
7964 *
7965 * @returns Strict VBox status code.
7966 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
7967 * @param cbInstr The instruction length in bytes.
7968 * @param uInstrId The instruction ID (VMXINSTRID_VMLAUNCH or
7969 * VMXINSTRID_VMRESUME).
7970 * @thread EMT(pVCpu)
7971 */
7972VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7973{
7974 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
7975 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
7976
7977 iemInitExec(pVCpu, false /*fBypassHandlers*/);
7978 VBOXSTRICTRC rcStrict = iemVmxVmlaunchVmresume(pVCpu, cbInstr, uInstrId);
7979 Assert(!pVCpu->iem.s.cActiveMappings);
7980 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
7981}
7982
7983
7984/**
7985 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7986 * (causes a VM-exit) or not.
7987 *
7988 * @returns @c true if the instruction is intercepted, @c false otherwise.
7989 * @param pVCpu The cross context virtual CPU structure.
7990 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7991 * VMX_EXIT_WRMSR).
7992 * @param idMsr The MSR.
7993 */
7994bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT
7995{
7996 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7997 Assert( uExitReason == VMX_EXIT_RDMSR
7998 || uExitReason == VMX_EXIT_WRMSR);
7999
8000 /* Consult the MSR bitmap if the feature is supported. */
8001 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
8002 Assert(pVmcs);
8003 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
8004 {
8005 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
8006 if (uExitReason == VMX_EXIT_RDMSR)
8007 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
8008 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
8009 }
8010
8011 /* Without MSR bitmaps, all MSR accesses are intercepted. */
8012 return true;
8013}
8014
8015
8016/**
8017 * VMREAD instruction execution worker that does not perform any validation checks.
8018 *
8019 * Callers are expected to have performed the necessary checks and to ensure the
8020 * VMREAD will succeed.
8021 *
8022 * @param pVmcs Pointer to the virtual VMCS.
8023 * @param pu64Dst Where to write the VMCS value.
8024 * @param u64VmcsField The VMCS field.
8025 *
8026 * @remarks May be called with interrupts disabled.
8027 */
8028static void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField) RT_NOEXCEPT
8029{
8030 VMXVMCSFIELD VmcsField;
8031 VmcsField.u = u64VmcsField;
8032 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8033 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8034 uint8_t const uWidthType = (uWidth << 2) | uType;
8035 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8036 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8037 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8038 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
8039 uWidth, uType, uIndex, uIndex));
8040 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8041
8042 /*
8043 * Read the VMCS component based on the field's effective width.
8044 *
8045 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8046 * indicates high bits (little endian).
8047 *
8048 * Note! The caller is responsible to trim the result and update registers
8049 * or memory locations are required. Here we just zero-extend to the largest
8050 * type (i.e. 64-bits).
8051 */
8052 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
8053 uint8_t const *pbField = pbVmcs + offField;
8054 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8055 switch (uEffWidth)
8056 {
8057 case VMX_VMCSFIELD_WIDTH_64BIT:
8058 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
8059 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
8060 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
8061 }
8062}
8063
8064/**
8065 * Interface for HM and EM to read a VMCS field from the nested-guest VMCS.
8066 *
8067 * It is ASSUMED the caller knows what they're doing. No VMREAD instruction checks
8068 * are performed. Bounds checks are strict builds only.
8069 *
8070 * @param pVmcs Pointer to the virtual VMCS.
8071 * @param u64VmcsField The VMCS field.
8072 * @param pu64Dst Where to store the VMCS value.
8073 *
8074 * @remarks May be called with interrupts disabled.
8075 * @todo This should probably be moved to CPUM someday.
8076 */
8077VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst)
8078{
8079 AssertPtr(pVmcs);
8080 AssertPtr(pu64Dst);
8081 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8082}
8083
8084
8085/**
8086 * VMREAD common (memory/register) instruction execution worker.
8087 *
8088 * @returns Strict VBox status code.
8089 * @param pVCpu The cross context virtual CPU structure.
8090 * @param cbInstr The instruction length in bytes.
8091 * @param pu64Dst Where to write the VMCS value (only updated when
8092 * VINF_SUCCESS is returned).
8093 * @param u64VmcsField The VMCS field.
8094 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8095 * NULL.
8096 */
8097static VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8098 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8099{
8100 /* Nested-guest intercept. */
8101 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8102 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
8103 {
8104 if (pExitInfo)
8105 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8106 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
8107 }
8108
8109 /* CPL. */
8110 if (pVCpu->iem.s.uCpl == 0)
8111 { /* likely */ }
8112 else
8113 {
8114 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8115 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
8116 return iemRaiseGeneralProtectionFault0(pVCpu);
8117 }
8118
8119 /* VMCS pointer in root mode. */
8120 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8121 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8122 { /* likely */ }
8123 else
8124 {
8125 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8126 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
8127 iemVmxVmFailInvalid(pVCpu);
8128 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8129 return VINF_SUCCESS;
8130 }
8131
8132 /* VMCS-link pointer in non-root mode. */
8133 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8134 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8135 { /* likely */ }
8136 else
8137 {
8138 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8139 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
8140 iemVmxVmFailInvalid(pVCpu);
8141 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8142 return VINF_SUCCESS;
8143 }
8144
8145 /* Supported VMCS field. */
8146 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8147 { /* likely */ }
8148 else
8149 {
8150 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8151 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
8152 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8153 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
8154 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8155 return VINF_SUCCESS;
8156 }
8157
8158 /*
8159 * Reading from the current or shadow VMCS.
8160 */
8161 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8162 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8163 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8164 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8165 return VINF_SUCCESS;
8166}
8167
8168
8169/**
8170 * VMREAD (64-bit register) instruction execution worker.
8171 *
8172 * @returns Strict VBox status code.
8173 * @param pVCpu The cross context virtual CPU structure.
8174 * @param cbInstr The instruction length in bytes.
8175 * @param pu64Dst Where to store the VMCS field's value.
8176 * @param u64VmcsField The VMCS field.
8177 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8178 * NULL.
8179 */
8180static VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8181 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8182{
8183 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
8184 if (rcStrict == VINF_SUCCESS)
8185 {
8186 iemVmxVmSucceed(pVCpu);
8187 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8188 return VINF_SUCCESS;
8189 }
8190
8191 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8192 return rcStrict;
8193}
8194
8195
8196/**
8197 * VMREAD (32-bit register) instruction execution worker.
8198 *
8199 * @returns Strict VBox status code.
8200 * @param pVCpu The cross context virtual CPU structure.
8201 * @param cbInstr The instruction length in bytes.
8202 * @param pu32Dst Where to store the VMCS field's value.
8203 * @param u32VmcsField The VMCS field.
8204 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8205 * NULL.
8206 */
8207static VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst,
8208 uint64_t u32VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8209{
8210 uint64_t u64Dst;
8211 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
8212 if (rcStrict == VINF_SUCCESS)
8213 {
8214 *pu32Dst = u64Dst;
8215 iemVmxVmSucceed(pVCpu);
8216 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8217 return VINF_SUCCESS;
8218 }
8219
8220 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8221 return rcStrict;
8222}
8223
8224
8225/**
8226 * VMREAD (memory) instruction execution worker.
8227 *
8228 * @returns Strict VBox status code.
8229 * @param pVCpu The cross context virtual CPU structure.
8230 * @param cbInstr The instruction length in bytes.
8231 * @param iEffSeg The effective segment register to use with @a u64Val.
8232 * Pass UINT8_MAX if it is a register access.
8233 * @param GCPtrDst The guest linear address to store the VMCS field's
8234 * value.
8235 * @param u64VmcsField The VMCS field.
8236 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8237 * NULL.
8238 */
8239static VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst,
8240 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8241{
8242 uint64_t u64Dst;
8243 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
8244 if (rcStrict == VINF_SUCCESS)
8245 {
8246 /*
8247 * Write the VMCS field's value to the location specified in guest-memory.
8248 */
8249 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8250 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8251 else
8252 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8253 if (rcStrict == VINF_SUCCESS)
8254 {
8255 iemVmxVmSucceed(pVCpu);
8256 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8257 return VINF_SUCCESS;
8258 }
8259
8260 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8261 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8262 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
8263 return rcStrict;
8264 }
8265
8266 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8267 return rcStrict;
8268}
8269
8270
8271/**
8272 * Interface for HM and EM to emulate the VMREAD instruction.
8273 *
8274 * @returns Strict VBox status code.
8275 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8276 * @param pExitInfo Pointer to the VM-exit information.
8277 * @thread EMT(pVCpu)
8278 */
8279VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8280{
8281 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8282 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8283 Assert(pExitInfo);
8284
8285 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8286
8287 VBOXSTRICTRC rcStrict;
8288 uint8_t const cbInstr = pExitInfo->cbInstr;
8289 bool const fIs64BitMode = RT_BOOL(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
8290 uint64_t const u64FieldEnc = fIs64BitMode
8291 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8292 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8293 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8294 {
8295 if (fIs64BitMode)
8296 {
8297 uint64_t *pu64Dst = iemGRegRefU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8298 rcStrict = iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
8299 }
8300 else
8301 {
8302 uint32_t *pu32Dst = iemGRegRefU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8303 rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u64FieldEnc, pExitInfo);
8304 }
8305 }
8306 else
8307 {
8308 RTGCPTR const GCPtrDst = pExitInfo->GCPtrEffAddr;
8309 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8310 rcStrict = iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, pExitInfo);
8311 }
8312 Assert(!pVCpu->iem.s.cActiveMappings);
8313 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8314}
8315
8316
8317/**
8318 * VMWRITE instruction execution worker that does not perform any validation
8319 * checks.
8320 *
8321 * Callers are expected to have performed the necessary checks and to ensure the
8322 * VMWRITE will succeed.
8323 *
8324 * @param pVmcs Pointer to the virtual VMCS.
8325 * @param u64Val The value to write.
8326 * @param u64VmcsField The VMCS field.
8327 *
8328 * @remarks May be called with interrupts disabled.
8329 */
8330static void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField) RT_NOEXCEPT
8331{
8332 VMXVMCSFIELD VmcsField;
8333 VmcsField.u = u64VmcsField;
8334 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8335 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8336 uint8_t const uWidthType = (uWidth << 2) | uType;
8337 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8338 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8339 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8340 Assert(offField < VMX_V_VMCS_SIZE);
8341 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8342
8343 /*
8344 * Write the VMCS component based on the field's effective width.
8345 *
8346 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8347 * indicates high bits (little endian).
8348 */
8349 uint8_t *pbVmcs = (uint8_t *)pVmcs;
8350 uint8_t *pbField = pbVmcs + offField;
8351 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8352 switch (uEffWidth)
8353 {
8354 case VMX_VMCSFIELD_WIDTH_64BIT:
8355 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8356 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8357 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8358 }
8359}
8360
8361
8362/**
8363 * Interface for HM and EM to write a VMCS field in the nested-guest VMCS.
8364 *
8365 * It is ASSUMED the caller knows what they're doing. No VMWRITE instruction checks
8366 * are performed. Bounds checks are strict builds only.
8367 *
8368 * @param pVmcs Pointer to the virtual VMCS.
8369 * @param u64VmcsField The VMCS field.
8370 * @param u64Val The value to write.
8371 *
8372 * @remarks May be called with interrupts disabled.
8373 * @todo This should probably be moved to CPUM someday.
8374 */
8375VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val)
8376{
8377 AssertPtr(pVmcs);
8378 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8379}
8380
8381
8382/**
8383 * VMWRITE instruction execution worker.
8384 *
8385 * @returns Strict VBox status code.
8386 * @param pVCpu The cross context virtual CPU structure.
8387 * @param cbInstr The instruction length in bytes.
8388 * @param iEffSeg The effective segment register to use with @a u64Val.
8389 * Pass UINT8_MAX if it is a register access.
8390 * @param u64Val The value to write (or guest linear address to the
8391 * value), @a iEffSeg will indicate if it's a memory
8392 * operand.
8393 * @param u64VmcsField The VMCS field.
8394 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8395 * NULL.
8396 */
8397static VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val,
8398 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8399{
8400 /* Nested-guest intercept. */
8401 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8402 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8403 {
8404 if (pExitInfo)
8405 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8406 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8407 }
8408
8409 /* CPL. */
8410 if (pVCpu->iem.s.uCpl == 0)
8411 { /* likely */ }
8412 else
8413 {
8414 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8415 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8416 return iemRaiseGeneralProtectionFault0(pVCpu);
8417 }
8418
8419 /* VMCS pointer in root mode. */
8420 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8421 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8422 { /* likely */ }
8423 else
8424 {
8425 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8426 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8427 iemVmxVmFailInvalid(pVCpu);
8428 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8429 return VINF_SUCCESS;
8430 }
8431
8432 /* VMCS-link pointer in non-root mode. */
8433 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8434 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8435 { /* likely */ }
8436 else
8437 {
8438 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8439 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8440 iemVmxVmFailInvalid(pVCpu);
8441 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8442 return VINF_SUCCESS;
8443 }
8444
8445 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8446 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8447 if (!fIsRegOperand)
8448 {
8449 /* Read the value from the specified guest memory location. */
8450 VBOXSTRICTRC rcStrict;
8451 RTGCPTR const GCPtrVal = u64Val;
8452 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8453 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8454 else
8455 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8456 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8457 {
8458 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8459 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8460 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
8461 return rcStrict;
8462 }
8463 }
8464 else
8465 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8466
8467 /* Supported VMCS field. */
8468 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8469 { /* likely */ }
8470 else
8471 {
8472 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8473 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8474 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8475 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8476 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8477 return VINF_SUCCESS;
8478 }
8479
8480 /* Read-only VMCS field. */
8481 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8482 if ( !fIsFieldReadOnly
8483 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8484 { /* likely */ }
8485 else
8486 {
8487 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8488 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8489 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8490 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8491 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8492 return VINF_SUCCESS;
8493 }
8494
8495 /*
8496 * Write to the current or shadow VMCS.
8497 */
8498 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8499 PVMXVVMCS pVmcs = !fInVmxNonRootMode
8500 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8501 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8502 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8503
8504 if ( !fInVmxNonRootMode
8505 && VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8506 {
8507 /* Notify HM that the VMCS content might have changed. */
8508 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8509 }
8510
8511 iemVmxVmSucceed(pVCpu);
8512 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8513 return VINF_SUCCESS;
8514}
8515
8516
8517/**
8518 * Interface for HM and EM to emulate the VMWRITE instruction.
8519 *
8520 * @returns Strict VBox status code.
8521 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8522 * @param pExitInfo Pointer to the VM-exit information.
8523 * @thread EMT(pVCpu)
8524 */
8525VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8526{
8527 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8528 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8529 Assert(pExitInfo);
8530
8531 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8532
8533 uint64_t u64Val;
8534 uint8_t iEffSeg;
8535 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8536 {
8537 u64Val = iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8538 iEffSeg = UINT8_MAX;
8539 }
8540 else
8541 {
8542 u64Val = pExitInfo->GCPtrEffAddr;
8543 iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8544 }
8545 uint8_t const cbInstr = pExitInfo->cbInstr;
8546 uint64_t const u64FieldEnc = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
8547 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8548 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8549 VBOXSTRICTRC rcStrict = iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, u64Val, u64FieldEnc, pExitInfo);
8550 Assert(!pVCpu->iem.s.cActiveMappings);
8551 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8552}
8553
8554
8555/**
8556 * VMCLEAR instruction execution worker.
8557 *
8558 * @returns Strict VBox status code.
8559 * @param pVCpu The cross context virtual CPU structure.
8560 * @param cbInstr The instruction length in bytes.
8561 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8562 * @param GCPtrVmcs The linear address of the VMCS pointer.
8563 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8564 *
8565 * @remarks Common VMX instruction checks are already expected to by the caller,
8566 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8567 */
8568static VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8569 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8570{
8571 /* Nested-guest intercept. */
8572 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8573 {
8574 if (pExitInfo)
8575 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8576 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8577 }
8578
8579 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8580
8581 /* CPL. */
8582 if (pVCpu->iem.s.uCpl == 0)
8583 { /* likely */ }
8584 else
8585 {
8586 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8587 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8588 return iemRaiseGeneralProtectionFault0(pVCpu);
8589 }
8590
8591 /* Get the VMCS pointer from the location specified by the source memory operand. */
8592 RTGCPHYS GCPhysVmcs;
8593 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8594 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8595 { /* likely */ }
8596 else
8597 {
8598 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8599 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8600 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8601 return rcStrict;
8602 }
8603
8604 /* VMCS pointer alignment. */
8605 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8606 { /* likely */ }
8607 else
8608 {
8609 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8610 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8611 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8612 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8613 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8614 return VINF_SUCCESS;
8615 }
8616
8617 /* VMCS physical-address width limits. */
8618 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8619 { /* likely */ }
8620 else
8621 {
8622 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8623 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8624 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8625 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8626 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8627 return VINF_SUCCESS;
8628 }
8629
8630 /* VMCS is not the VMXON region. */
8631 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8632 { /* likely */ }
8633 else
8634 {
8635 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8636 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8637 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8638 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8639 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8640 return VINF_SUCCESS;
8641 }
8642
8643 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8644 restriction imposed by our implementation. */
8645 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8646 { /* likely */ }
8647 else
8648 {
8649 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8650 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8651 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8652 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8653 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8654 return VINF_SUCCESS;
8655 }
8656
8657 /*
8658 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8659 *
8660 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8661 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8662 * to 'clear'.
8663 */
8664 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8665 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8666 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8667 {
8668 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8669 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8670 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8671 }
8672 else
8673 {
8674 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8675 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8676 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8677 if (RT_FAILURE(rcStrict))
8678 return rcStrict;
8679 }
8680
8681 iemVmxVmSucceed(pVCpu);
8682 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8683 return VINF_SUCCESS;
8684}
8685
8686
8687/**
8688 * Interface for HM and EM to emulate the VMCLEAR instruction.
8689 *
8690 * @returns Strict VBox status code.
8691 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8692 * @param pExitInfo Pointer to the VM-exit information.
8693 * @thread EMT(pVCpu)
8694 */
8695VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8696{
8697 Assert(pExitInfo);
8698 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8699 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8700
8701 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8702
8703 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8704 uint8_t const cbInstr = pExitInfo->cbInstr;
8705 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8706 VBOXSTRICTRC rcStrict = iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8707 Assert(!pVCpu->iem.s.cActiveMappings);
8708 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8709}
8710
8711
8712/**
8713 * VMPTRST instruction execution worker.
8714 *
8715 * @returns Strict VBox status code.
8716 * @param pVCpu The cross context virtual CPU structure.
8717 * @param cbInstr The instruction length in bytes.
8718 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8719 * @param GCPtrVmcs The linear address of where to store the current VMCS
8720 * pointer.
8721 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8722 *
8723 * @remarks Common VMX instruction checks are already expected to by the caller,
8724 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8725 */
8726static VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8727 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8728{
8729 /* Nested-guest intercept. */
8730 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8731 {
8732 if (pExitInfo)
8733 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8734 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8735 }
8736
8737 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8738
8739 /* CPL. */
8740 if (pVCpu->iem.s.uCpl == 0)
8741 { /* likely */ }
8742 else
8743 {
8744 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8745 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8746 return iemRaiseGeneralProtectionFault0(pVCpu);
8747 }
8748
8749 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8750 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8751 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8752 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8753 {
8754 iemVmxVmSucceed(pVCpu);
8755 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8756 return rcStrict;
8757 }
8758
8759 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8760 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8761 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8762 return rcStrict;
8763}
8764
8765
8766/**
8767 * Interface for HM and EM to emulate the VMPTRST instruction.
8768 *
8769 * @returns Strict VBox status code.
8770 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8771 * @param pExitInfo Pointer to the VM-exit information.
8772 * @thread EMT(pVCpu)
8773 */
8774VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8775{
8776 Assert(pExitInfo);
8777 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8778 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8779
8780 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8781
8782 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8783 uint8_t const cbInstr = pExitInfo->cbInstr;
8784 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8785 VBOXSTRICTRC rcStrict = iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8786 Assert(!pVCpu->iem.s.cActiveMappings);
8787 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8788}
8789
8790
8791/**
8792 * VMPTRLD instruction execution worker.
8793 *
8794 * @returns Strict VBox status code.
8795 * @param pVCpu The cross context virtual CPU structure.
8796 * @param cbInstr The instruction length in bytes.
8797 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8798 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8799 *
8800 * @remarks Common VMX instruction checks are already expected to by the caller,
8801 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8802 */
8803static VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8804 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8805{
8806 /* Nested-guest intercept. */
8807 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8808 {
8809 if (pExitInfo)
8810 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8811 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8812 }
8813
8814 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8815
8816 /* CPL. */
8817 if (pVCpu->iem.s.uCpl == 0)
8818 { /* likely */ }
8819 else
8820 {
8821 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8822 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8823 return iemRaiseGeneralProtectionFault0(pVCpu);
8824 }
8825
8826 /* Get the VMCS pointer from the location specified by the source memory operand. */
8827 RTGCPHYS GCPhysVmcs;
8828 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8829 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8830 { /* likely */ }
8831 else
8832 {
8833 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8834 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8835 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8836 return rcStrict;
8837 }
8838
8839 /* VMCS pointer alignment. */
8840 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8841 { /* likely */ }
8842 else
8843 {
8844 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8845 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8846 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8847 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8848 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8849 return VINF_SUCCESS;
8850 }
8851
8852 /* VMCS physical-address width limits. */
8853 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8854 { /* likely */ }
8855 else
8856 {
8857 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8858 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8859 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8860 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8861 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8862 return VINF_SUCCESS;
8863 }
8864
8865 /* VMCS is not the VMXON region. */
8866 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8867 { /* likely */ }
8868 else
8869 {
8870 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8871 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8872 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8873 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8874 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8875 return VINF_SUCCESS;
8876 }
8877
8878 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8879 restriction imposed by our implementation. */
8880 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8881 { /* likely */ }
8882 else
8883 {
8884 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8885 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8886 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8887 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8888 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8889 return VINF_SUCCESS;
8890 }
8891
8892 /* Read just the VMCS revision from the VMCS. */
8893 VMXVMCSREVID VmcsRevId;
8894 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8895 if (RT_SUCCESS(rc))
8896 { /* likely */ }
8897 else
8898 {
8899 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8900 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8901 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8902 return rc;
8903 }
8904
8905 /*
8906 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8907 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8908 */
8909 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8910 && ( !VmcsRevId.n.fIsShadowVmcs
8911 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8912 { /* likely */ }
8913 else
8914 {
8915 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8916 {
8917 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8918 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8919 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8920 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8921 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8922 return VINF_SUCCESS;
8923 }
8924
8925 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8926 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8927 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8928 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8929 return VINF_SUCCESS;
8930 }
8931
8932 /*
8933 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8934 * the cache of an existing, current VMCS back to guest memory before loading a new,
8935 * different current VMCS.
8936 */
8937 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8938 {
8939 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8940 {
8941 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8942 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8943 }
8944
8945 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8946 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8947 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8948 if (RT_SUCCESS(rc))
8949 {
8950 /* Notify HM that a new, current VMCS is loaded. */
8951 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8952 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8953 }
8954 else
8955 {
8956 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8957 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8958 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8959 return rc;
8960 }
8961 }
8962
8963 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8964 iemVmxVmSucceed(pVCpu);
8965 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8966 return VINF_SUCCESS;
8967}
8968
8969
8970/**
8971 * Interface for HM and EM to emulate the VMPTRLD instruction.
8972 *
8973 * @returns Strict VBox status code.
8974 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8975 * @param pExitInfo Pointer to the VM-exit information.
8976 * @thread EMT(pVCpu)
8977 */
8978VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8979{
8980 Assert(pExitInfo);
8981 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8982 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8983
8984 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8985
8986 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8987 uint8_t const cbInstr = pExitInfo->cbInstr;
8988 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8989 VBOXSTRICTRC rcStrict = iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8990 Assert(!pVCpu->iem.s.cActiveMappings);
8991 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8992}
8993
8994
8995/**
8996 * INVVPID instruction execution worker.
8997 *
8998 * @returns Strict VBox status code.
8999 * @param pVCpu The cross context virtual CPU structure.
9000 * @param cbInstr The instruction length in bytes.
9001 * @param iEffSeg The segment of the invvpid descriptor.
9002 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
9003 * @param u64InvvpidType The invalidation type.
9004 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9005 * NULL.
9006 *
9007 * @remarks Common VMX instruction checks are already expected to by the caller,
9008 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9009 */
9010VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
9011 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9012{
9013 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
9014 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
9015 return iemRaiseUndefinedOpcode(pVCpu);
9016
9017 /* Nested-guest intercept. */
9018 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9019 {
9020 if (pExitInfo)
9021 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9022 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
9023 }
9024
9025 /* CPL. */
9026 if (pVCpu->iem.s.uCpl != 0)
9027 {
9028 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
9029 return iemRaiseGeneralProtectionFault0(pVCpu);
9030 }
9031
9032 /*
9033 * Validate INVVPID invalidation type.
9034 *
9035 * The instruction specifies exactly ONE of the supported invalidation types.
9036 *
9037 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9038 * supported. In theory, it's possible for a CPU to not support flushing individual
9039 * addresses but all the other types or any other combination. We do not take any
9040 * shortcuts here by assuming the types we currently expose to the guest.
9041 */
9042 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9043 bool const fInvvpidSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID);
9044 bool const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
9045 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
9046 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
9047 bool const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
9048
9049 bool afSupportedTypes[4];
9050 afSupportedTypes[0] = fTypeIndivAddr;
9051 afSupportedTypes[1] = fTypeSingleCtx;
9052 afSupportedTypes[2] = fTypeAllCtx;
9053 afSupportedTypes[3] = fTypeSingleCtxRetainGlobals;
9054
9055 if ( fInvvpidSupported
9056 && !(u64InvvpidType & ~(uint64_t)VMX_INVVPID_VALID_MASK)
9057 && afSupportedTypes[u64InvvpidType & 3])
9058 { /* likely */ }
9059 else
9060 {
9061 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
9062 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
9063 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9064 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9065 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9066 return VINF_SUCCESS;
9067 }
9068
9069 /*
9070 * Fetch the invvpid descriptor from guest memory.
9071 */
9072 RTUINT128U uDesc;
9073 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
9074 if (rcStrict == VINF_SUCCESS)
9075 {
9076 /*
9077 * Validate the descriptor.
9078 */
9079 if (uDesc.s.Lo <= 0xffff)
9080 { /* likely */ }
9081 else
9082 {
9083 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
9084 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
9085 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
9086 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9087 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9088 return VINF_SUCCESS;
9089 }
9090
9091 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9092 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
9093 uint8_t const uVpid = uDesc.s.Lo & UINT64_C(0xfff);
9094 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9095 switch (u64InvvpidType)
9096 {
9097 case VMXTLBFLUSHVPID_INDIV_ADDR:
9098 {
9099 if (uVpid != 0)
9100 {
9101 if (IEM_IS_CANONICAL(GCPtrInvAddr))
9102 {
9103 /* Invalidate mappings for the linear address tagged with VPID. */
9104 /** @todo PGM support for VPID? Currently just flush everything. */
9105 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9106 iemVmxVmSucceed(pVCpu);
9107 }
9108 else
9109 {
9110 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
9111 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
9112 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
9113 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9114 }
9115 }
9116 else
9117 {
9118 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9119 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
9120 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9121 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9122 }
9123 break;
9124 }
9125
9126 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
9127 {
9128 if (uVpid != 0)
9129 {
9130 /* Invalidate all mappings with VPID. */
9131 /** @todo PGM support for VPID? Currently just flush everything. */
9132 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9133 iemVmxVmSucceed(pVCpu);
9134 }
9135 else
9136 {
9137 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9138 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
9139 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9140 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9141 }
9142 break;
9143 }
9144
9145 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
9146 {
9147 /* Invalidate all mappings with non-zero VPIDs. */
9148 /** @todo PGM support for VPID? Currently just flush everything. */
9149 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9150 iemVmxVmSucceed(pVCpu);
9151 break;
9152 }
9153
9154 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
9155 {
9156 if (uVpid != 0)
9157 {
9158 /* Invalidate all mappings with VPID except global translations. */
9159 /** @todo PGM support for VPID? Currently just flush everything. */
9160 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9161 iemVmxVmSucceed(pVCpu);
9162 }
9163 else
9164 {
9165 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9166 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
9167 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
9168 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9169 }
9170 break;
9171 }
9172 IEM_NOT_REACHED_DEFAULT_CASE_RET();
9173 }
9174 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9175 }
9176 return rcStrict;
9177}
9178
9179
9180/**
9181 * Interface for HM and EM to emulate the INVVPID instruction.
9182 *
9183 * @returns Strict VBox status code.
9184 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9185 * @param pExitInfo Pointer to the VM-exit information.
9186 * @thread EMT(pVCpu)
9187 */
9188VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9189{
9190 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9191 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9192 Assert(pExitInfo);
9193
9194 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9195
9196 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9197 uint8_t const cbInstr = pExitInfo->cbInstr;
9198 RTGCPTR const GCPtrInvvpidDesc = pExitInfo->GCPtrEffAddr;
9199 uint64_t const u64InvvpidType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9200 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9201 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9202 VBOXSTRICTRC rcStrict = iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, u64InvvpidType, pExitInfo);
9203 Assert(!pVCpu->iem.s.cActiveMappings);
9204 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9205}
9206
9207#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9208
9209/**
9210 * INVEPT instruction execution worker.
9211 *
9212 * @returns Strict VBox status code.
9213 * @param pVCpu The cross context virtual CPU structure.
9214 * @param cbInstr The instruction length in bytes.
9215 * @param iEffSeg The segment of the invept descriptor.
9216 * @param GCPtrInveptDesc The address of invept descriptor.
9217 * @param u64InveptType The invalidation type.
9218 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9219 * NULL.
9220 *
9221 * @remarks Common VMX instruction checks are already expected to by the caller,
9222 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9223 */
9224static VBOXSTRICTRC iemVmxInvept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInveptDesc,
9225 uint64_t u64InveptType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9226{
9227 /* Check if EPT is supported, otherwise raise #UD. */
9228 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEpt)
9229 return iemRaiseUndefinedOpcode(pVCpu);
9230
9231 /* Nested-guest intercept. */
9232 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9233 {
9234 if (pExitInfo)
9235 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9236 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVEPT, VMXINSTRID_NONE, cbInstr);
9237 }
9238
9239 /* CPL. */
9240 if (pVCpu->iem.s.uCpl != 0)
9241 {
9242 Log(("invept: CPL != 0 -> #GP(0)\n"));
9243 return iemRaiseGeneralProtectionFault0(pVCpu);
9244 }
9245
9246 /*
9247 * Validate INVEPT invalidation type.
9248 *
9249 * The instruction specifies exactly ONE of the supported invalidation types.
9250 *
9251 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9252 * supported. In theory, it's possible for a CPU to not support flushing individual
9253 * addresses but all the other types or any other combination. We do not take any
9254 * shortcuts here by assuming the types we currently expose to the guest.
9255 */
9256 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9257 bool const fInveptSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT);
9258 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
9259 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
9260
9261 bool afSupportedTypes[4];
9262 afSupportedTypes[0] = false;
9263 afSupportedTypes[1] = fTypeSingleCtx;
9264 afSupportedTypes[2] = fTypeAllCtx;
9265 afSupportedTypes[3] = false;
9266
9267 if ( fInveptSupported
9268 && !(u64InveptType & ~(uint64_t)VMX_INVEPT_VALID_MASK)
9269 && afSupportedTypes[u64InveptType & 3])
9270 { /* likely */ }
9271 else
9272 {
9273 Log(("invept: invalid/unsupported invvpid type %#x -> VMFail\n", u64InveptType));
9274 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_TypeInvalid;
9275 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType;
9276 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9277 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9278 return VINF_SUCCESS;
9279 }
9280
9281 /*
9282 * Fetch the invept descriptor from guest memory.
9283 */
9284 RTUINT128U uDesc;
9285 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInveptDesc);
9286 if (rcStrict == VINF_SUCCESS)
9287 {
9288 /*
9289 * Validate the descriptor.
9290 *
9291 * The Intel spec. does not explicit say the INVEPT instruction fails when reserved
9292 * bits in the descriptor are set, but it -does- for INVVPID. Until we test on real
9293 * hardware, it's assumed INVEPT behaves the same as INVVPID in this regard. It's
9294 * better to be strict in our emulation until proven otherwise.
9295 */
9296 if (uDesc.s.Hi)
9297 {
9298 Log(("invept: reserved bits set in invept descriptor %#RX64 -> VMFail\n", uDesc.s.Hi));
9299 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_DescRsvd;
9300 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi;
9301 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9302 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9303 return VINF_SUCCESS;
9304 }
9305
9306 /*
9307 * Flush TLB mappings based on the EPT type.
9308 */
9309 if (u64InveptType == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
9310 {
9311 uint64_t const GCPhysEptPtr = uDesc.s.Lo;
9312 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, GCPhysEptPtr, NULL /* enmDiag */);
9313 if (RT_SUCCESS(rc))
9314 { /* likely */ }
9315 else
9316 {
9317 Log(("invept: EPTP invalid %#RX64 -> VMFail\n", GCPhysEptPtr));
9318 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_EptpInvalid;
9319 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr;
9320 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9321 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9322 return VINF_SUCCESS;
9323 }
9324 }
9325
9326 /** @todo PGM support for EPT tags? Currently just flush everything. */
9327 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9328 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9329 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9330
9331 iemVmxVmSucceed(pVCpu);
9332 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9333 }
9334
9335 return rcStrict;
9336}
9337
9338
9339/**
9340 * Interface for HM and EM to emulate the INVEPT instruction.
9341 *
9342 * @returns Strict VBox status code.
9343 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9344 * @param pExitInfo Pointer to the VM-exit information.
9345 * @thread EMT(pVCpu)
9346 */
9347VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9348{
9349 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9350 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9351 Assert(pExitInfo);
9352
9353 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9354
9355 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9356 uint8_t const cbInstr = pExitInfo->cbInstr;
9357 RTGCPTR const GCPtrInveptDesc = pExitInfo->GCPtrEffAddr;
9358 uint64_t const u64InveptType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9359 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9360 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9361 VBOXSTRICTRC rcStrict = iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, u64InveptType, pExitInfo);
9362 Assert(!pVCpu->iem.s.cActiveMappings);
9363 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9364}
9365
9366#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
9367
9368/**
9369 * VMXON instruction execution worker.
9370 *
9371 * @returns Strict VBox status code.
9372 * @param pVCpu The cross context virtual CPU structure.
9373 * @param cbInstr The instruction length in bytes.
9374 * @param iEffSeg The effective segment register to use with @a
9375 * GCPtrVmxon.
9376 * @param GCPtrVmxon The linear address of the VMXON pointer.
9377 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
9378 *
9379 * @remarks Common VMX instruction checks are already expected to by the caller,
9380 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9381 */
9382static VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
9383 RTGCPHYS GCPtrVmxon, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9384{
9385 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
9386 {
9387 /* CPL. */
9388 if (pVCpu->iem.s.uCpl == 0)
9389 { /* likely */ }
9390 else
9391 {
9392 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9393 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
9394 return iemRaiseGeneralProtectionFault0(pVCpu);
9395 }
9396
9397 /* A20M (A20 Masked) mode. */
9398 if (PGMPhysIsA20Enabled(pVCpu))
9399 { /* likely */ }
9400 else
9401 {
9402 Log(("vmxon: A20M mode -> #GP(0)\n"));
9403 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
9404 return iemRaiseGeneralProtectionFault0(pVCpu);
9405 }
9406
9407 /* CR0. */
9408 {
9409 /*
9410 * CR0 MB1 bits.
9411 *
9412 * We use VMX_V_CR0_FIXED0 below to ensure CR0.PE and CR0.PG are always set
9413 * while executing VMXON. CR0.PE and CR0.PG are only allowed to be clear
9414 * when the guest running in VMX non-root mode with unrestricted-guest control
9415 * enabled in the VMCS.
9416 */
9417 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
9418 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
9419 { /* likely */ }
9420 else
9421 {
9422 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
9423 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
9424 return iemRaiseGeneralProtectionFault0(pVCpu);
9425 }
9426
9427 /* CR0 MBZ bits. */
9428 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
9429 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
9430 { /* likely */ }
9431 else
9432 {
9433 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
9434 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
9435 return iemRaiseGeneralProtectionFault0(pVCpu);
9436 }
9437 }
9438
9439 /* CR4. */
9440 {
9441 /* CR4 MB1 bits. */
9442 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
9443 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
9444 { /* likely */ }
9445 else
9446 {
9447 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
9448 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
9449 return iemRaiseGeneralProtectionFault0(pVCpu);
9450 }
9451
9452 /* CR4 MBZ bits. */
9453 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
9454 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
9455 { /* likely */ }
9456 else
9457 {
9458 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
9459 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
9460 return iemRaiseGeneralProtectionFault0(pVCpu);
9461 }
9462 }
9463
9464 /* Feature control MSR's LOCK and VMXON bits. */
9465 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
9466 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9467 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9468 { /* likely */ }
9469 else
9470 {
9471 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
9472 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
9473 return iemRaiseGeneralProtectionFault0(pVCpu);
9474 }
9475
9476 /* Get the VMXON pointer from the location specified by the source memory operand. */
9477 RTGCPHYS GCPhysVmxon;
9478 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
9479 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
9480 { /* likely */ }
9481 else
9482 {
9483 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
9484 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
9485 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
9486 return rcStrict;
9487 }
9488
9489 /* VMXON region pointer alignment. */
9490 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
9491 { /* likely */ }
9492 else
9493 {
9494 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
9495 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
9496 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9497 iemVmxVmFailInvalid(pVCpu);
9498 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9499 return VINF_SUCCESS;
9500 }
9501
9502 /* VMXON physical-address width limits. */
9503 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
9504 { /* likely */ }
9505 else
9506 {
9507 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
9508 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
9509 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9510 iemVmxVmFailInvalid(pVCpu);
9511 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9512 return VINF_SUCCESS;
9513 }
9514
9515 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
9516 restriction imposed by our implementation. */
9517 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
9518 { /* likely */ }
9519 else
9520 {
9521 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
9522 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
9523 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9524 iemVmxVmFailInvalid(pVCpu);
9525 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9526 return VINF_SUCCESS;
9527 }
9528
9529 /* Read the VMCS revision ID from the VMXON region. */
9530 VMXVMCSREVID VmcsRevId;
9531 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
9532 if (RT_SUCCESS(rc))
9533 { /* likely */ }
9534 else
9535 {
9536 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
9537 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
9538 return rc;
9539 }
9540
9541 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
9542 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
9543 { /* likely */ }
9544 else
9545 {
9546 /* Revision ID mismatch. */
9547 if (!VmcsRevId.n.fIsShadowVmcs)
9548 {
9549 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
9550 VmcsRevId.n.u31RevisionId));
9551 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
9552 iemVmxVmFailInvalid(pVCpu);
9553 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9554 return VINF_SUCCESS;
9555 }
9556
9557 /* Shadow VMCS disallowed. */
9558 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
9559 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
9560 iemVmxVmFailInvalid(pVCpu);
9561 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9562 return VINF_SUCCESS;
9563 }
9564
9565 /*
9566 * Record that we're in VMX operation, block INIT, block and disable A20M.
9567 */
9568 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
9569 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
9570 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
9571
9572 /* Clear address-range monitoring. */
9573 EMMonitorWaitClear(pVCpu);
9574 /** @todo NSTVMX: Intel PT. */
9575
9576 iemVmxVmSucceed(pVCpu);
9577 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9578 return VINF_SUCCESS;
9579 }
9580 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9581 {
9582 /* Nested-guest intercept. */
9583 if (pExitInfo)
9584 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9585 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
9586 }
9587
9588 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
9589
9590 /* CPL. */
9591 if (pVCpu->iem.s.uCpl > 0)
9592 {
9593 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9594 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
9595 return iemRaiseGeneralProtectionFault0(pVCpu);
9596 }
9597
9598 /* VMXON when already in VMX root mode. */
9599 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
9600 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
9601 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9602 return VINF_SUCCESS;
9603}
9604
9605
9606/**
9607 * Interface for HM and EM to emulate the VMXON instruction.
9608 *
9609 * @returns Strict VBox status code.
9610 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9611 * @param pExitInfo Pointer to the VM-exit information.
9612 * @thread EMT(pVCpu)
9613 */
9614VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9615{
9616 Assert(pExitInfo);
9617 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
9618 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9619
9620 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9621
9622 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
9623 uint8_t const cbInstr = pExitInfo->cbInstr;
9624 RTGCPTR const GCPtrVmxon = pExitInfo->GCPtrEffAddr;
9625 VBOXSTRICTRC rcStrict = iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
9626 Assert(!pVCpu->iem.s.cActiveMappings);
9627 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9628}
9629
9630
9631/**
9632 * Implements 'VMXOFF'.
9633 *
9634 * @remarks Common VMX instruction checks are already expected to by the caller,
9635 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9636 */
9637IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
9638{
9639 /* Nested-guest intercept. */
9640 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9641 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9642
9643 /* CPL. */
9644 if (pVCpu->iem.s.uCpl == 0)
9645 { /* likely */ }
9646 else
9647 {
9648 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9649 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9650 return iemRaiseGeneralProtectionFault0(pVCpu);
9651 }
9652
9653 /* Dual monitor treatment of SMIs and SMM. */
9654 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9655 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9656 { /* likely */ }
9657 else
9658 {
9659 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9660 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9661 return VINF_SUCCESS;
9662 }
9663
9664 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9665 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9666 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9667
9668 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9669 { /** @todo NSTVMX: Unblock SMI. */ }
9670
9671 EMMonitorWaitClear(pVCpu);
9672 /** @todo NSTVMX: Unblock and enable A20M. */
9673
9674 iemVmxVmSucceed(pVCpu);
9675 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9676 return VINF_SUCCESS;
9677}
9678
9679
9680/**
9681 * Interface for HM and EM to emulate the VMXOFF instruction.
9682 *
9683 * @returns Strict VBox status code.
9684 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9685 * @param cbInstr The instruction length in bytes.
9686 * @thread EMT(pVCpu)
9687 */
9688VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr)
9689{
9690 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
9691 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9692
9693 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9694 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmxoff);
9695 Assert(!pVCpu->iem.s.cActiveMappings);
9696 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9697}
9698
9699
9700/**
9701 * Implements 'VMXON'.
9702 */
9703IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9704{
9705 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9706}
9707
9708
9709/**
9710 * Implements 'VMLAUNCH'.
9711 */
9712IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9713{
9714 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9715}
9716
9717
9718/**
9719 * Implements 'VMRESUME'.
9720 */
9721IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9722{
9723 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9724}
9725
9726
9727/**
9728 * Implements 'VMPTRLD'.
9729 */
9730IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9731{
9732 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9733}
9734
9735
9736/**
9737 * Implements 'VMPTRST'.
9738 */
9739IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9740{
9741 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9742}
9743
9744
9745/**
9746 * Implements 'VMCLEAR'.
9747 */
9748IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9749{
9750 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9751}
9752
9753
9754/**
9755 * Implements 'VMWRITE' register.
9756 */
9757IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9758{
9759 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9760}
9761
9762
9763/**
9764 * Implements 'VMWRITE' memory.
9765 */
9766IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9767{
9768 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9769}
9770
9771
9772/**
9773 * Implements 'VMREAD' register (64-bit).
9774 */
9775IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9776{
9777 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9778}
9779
9780
9781/**
9782 * Implements 'VMREAD' register (32-bit).
9783 */
9784IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField)
9785{
9786 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32VmcsField, NULL /* pExitInfo */);
9787}
9788
9789
9790/**
9791 * Implements 'VMREAD' memory, 64-bit register.
9792 */
9793IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9794{
9795 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9796}
9797
9798
9799/**
9800 * Implements 'VMREAD' memory, 32-bit register.
9801 */
9802IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9803{
9804 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9805}
9806
9807
9808/**
9809 * Implements 'INVVPID'.
9810 */
9811IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9812{
9813 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9814}
9815
9816
9817#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9818/**
9819 * Implements 'INVEPT'.
9820 */
9821IEM_CIMPL_DEF_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType)
9822{
9823 return iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType, NULL /* pExitInfo */);
9824}
9825#endif
9826
9827
9828/**
9829 * Implements VMX's implementation of PAUSE.
9830 */
9831IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9832{
9833 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9834 {
9835 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9836 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9837 return rcStrict;
9838 }
9839
9840 /*
9841 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9842 * a VM-exit, the instruction operates normally.
9843 */
9844 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9845 return VINF_SUCCESS;
9846}
9847
9848#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9849
9850
9851/**
9852 * Implements 'VMCALL'.
9853 */
9854IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9855{
9856#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9857 /* Nested-guest intercept. */
9858 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9859 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9860#endif
9861
9862 /* Join forces with vmmcall. */
9863 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9864}
9865
9866
9867#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9868
9869/**
9870 * @callback_method_impl{FNPGMPHYSHANDLER, VMX APIC-access page accesses}
9871 *
9872 * @remarks The @a uUser argument is currently unused.
9873 */
9874DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPageHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, void *pvPhys,
9875 void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
9876 PGMACCESSORIGIN enmOrigin, uint64_t uUser)
9877{
9878 RT_NOREF3(pvPhys, enmOrigin, uUser);
9879
9880 RTGCPHYS const GCPhysAccessBase = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9881 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9882 {
9883 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9884 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysAccessBase);
9885
9886 uint32_t const fAccess = enmAccessType == PGMACCESSTYPE_WRITE ? IEM_ACCESS_DATA_W : IEM_ACCESS_DATA_R;
9887 uint16_t const offAccess = GCPhysFault & GUEST_PAGE_OFFSET_MASK;
9888 VBOXSTRICTRC rcStrict = iemVmxVirtApicAccessMem(pVCpu, offAccess, cbBuf, pvBuf, fAccess);
9889 if (RT_FAILURE(rcStrict))
9890 return rcStrict;
9891
9892 /* Any access on this APIC-access page has been handled, caller should not carry out the access. */
9893 return VINF_SUCCESS;
9894 }
9895
9896 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysAccessBase));
9897 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhysAccessBase);
9898 if (RT_FAILURE(rc))
9899 return rc;
9900
9901 /* Instruct the caller of this handler to perform the read/write as normal memory. */
9902 return VINF_PGM_HANDLER_DO_DEFAULT;
9903}
9904
9905
9906# ifndef IN_RING3
9907/**
9908 * @callback_method_impl{FNPGMRZPHYSPFHANDLER,
9909 * \#PF access handler callback for guest VMX APIC-access page.}
9910 */
9911DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
9912 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
9913
9914{
9915 RT_NOREF3(pVM, pRegFrame, uUser);
9916
9917 /*
9918 * Handle the VMX APIC-access page only when the guest is in VMX non-root mode.
9919 * Otherwise we must deregister the page and allow regular RAM access.
9920 * Failing to do so lands us with endless EPT misconfiguration VM-exits.
9921 */
9922 RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9923 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9924 {
9925 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9926 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysPage);
9927
9928 /*
9929 * Check if the access causes an APIC-access VM-exit.
9930 */
9931 uint32_t fAccess;
9932 if (uErr & X86_TRAP_PF_ID)
9933 fAccess = IEM_ACCESS_INSTRUCTION;
9934 else if (uErr & X86_TRAP_PF_RW)
9935 fAccess = IEM_ACCESS_DATA_W;
9936 else
9937 fAccess = IEM_ACCESS_DATA_R;
9938
9939 RTGCPHYS const GCPhysNestedFault = (RTGCPHYS)pvFault;
9940 uint16_t const offAccess = GCPhysNestedFault & GUEST_PAGE_OFFSET_MASK;
9941 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, 1 /* cbAccess */, fAccess);
9942 if (fIntercept)
9943 {
9944 /*
9945 * Query the source VM-exit (from the execution engine) that caused this access
9946 * within the APIC-access page. Currently only HM is supported.
9947 */
9948 AssertMsg(VM_IS_HM_ENABLED(pVM), ("VM-exit auxiliary info. fetching not supported for execution engine %d\n",
9949 pVM->bMainExecutionEngine));
9950 HMEXITAUX HmExitAux;
9951 RT_ZERO(HmExitAux);
9952 int const rc = HMR0GetExitAuxInfo(pVCpu, &HmExitAux, HMVMX_READ_EXIT_INSTR_LEN
9953 | HMVMX_READ_EXIT_QUALIFICATION
9954 | HMVMX_READ_IDT_VECTORING_INFO
9955 | HMVMX_READ_IDT_VECTORING_ERROR_CODE);
9956 AssertRC(rc);
9957
9958 /*
9959 * Verify the VM-exit reason must be an EPT violation.
9960 * Other accesses should go through the other handler (iemVmxApicAccessPageHandler).
9961 * Refer to @bugref{10092#c33s} for a more detailed explanation.
9962 */
9963 AssertMsg(HmExitAux.Vmx.uReason == VMX_EXIT_EPT_VIOLATION,
9964 ("Unexpected call to APIC-access page #PF handler for %#RGp off=%u uErr=%#RGx uReason=%u\n",
9965 GCPhysPage, offAccess, uErr, HmExitAux.Vmx.uReason));
9966
9967 /*
9968 * Construct the virtual APIC-access VM-exit.
9969 */
9970 VMXAPICACCESS enmAccess;
9971 if (HmExitAux.Vmx.u64Qual & VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID)
9972 {
9973 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9974 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
9975 else if (fAccess == IEM_ACCESS_INSTRUCTION)
9976 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
9977 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
9978 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
9979 else
9980 enmAccess = VMXAPICACCESS_LINEAR_READ;
9981 }
9982 else
9983 {
9984 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9985 enmAccess = VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY;
9986 else
9987 {
9988 /** @todo How to distinguish between monitoring/trace vs other instructions
9989 * here? */
9990 enmAccess = VMXAPICACCESS_PHYSICAL_INSTR;
9991 }
9992 }
9993
9994 VMXVEXITINFO ExitInfo;
9995 RT_ZERO(ExitInfo);
9996 ExitInfo.uReason = VMX_EXIT_APIC_ACCESS;
9997 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
9998 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
9999 ExitInfo.cbInstr = HmExitAux.Vmx.cbInstr;
10000
10001 VMXVEXITEVENTINFO ExitEventInfo;
10002 RT_ZERO(ExitEventInfo);
10003 ExitEventInfo.uIdtVectoringInfo = HmExitAux.Vmx.uIdtVectoringInfo;
10004 ExitEventInfo.uIdtVectoringErrCode = HmExitAux.Vmx.uIdtVectoringErrCode;
10005
10006 /*
10007 * Raise the APIC-access VM-exit.
10008 */
10009 VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
10010 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
10011 }
10012
10013 /*
10014 * The access isn't intercepted, which means it needs to be virtualized.
10015 *
10016 * This requires emulating the instruction because we need the bytes being
10017 * read/written by the instruction not just the offset being accessed within
10018 * the APIC-access page (which we derive from the faulting address).
10019 */
10020 return VINF_EM_RAW_EMULATE_INSTR;
10021 }
10022
10023 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysPage));
10024 int const rc = PGMHandlerPhysicalDeregister(pVM, GCPhysPage);
10025 if (RT_FAILURE(rc))
10026 return rc;
10027
10028 return VINF_SUCCESS;
10029}
10030# endif /* !IN_RING3 */
10031
10032#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
10033
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