VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp@ 99360

Last change on this file since 99360 was 99318, checked in by vboxsync, 21 months ago

VMM/IEM: Nested VMX: bugref:10318 Fixed race while registering the virtual VMX APIC-access page by multiple VCPUs.
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File size: 409.3 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp 99318 2023-04-06 16:02:43Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_IEM_VMX
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/iem.h>
35#include <VBox/vmm/apic.h>
36#include <VBox/vmm/cpum.h>
37#include <VBox/vmm/dbgf.h>
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/gim.h>
40#include <VBox/vmm/hm.h>
41#include <VBox/vmm/pgm.h>
42#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
43# include <VBox/vmm/hmvmxinline.h>
44#endif
45#include <VBox/vmm/tm.h>
46#include "IEMInternal.h"
47#include <VBox/vmm/vmcc.h>
48#include <VBox/log.h>
49#include <VBox/err.h>
50#include <VBox/param.h>
51#include <VBox/disopcode-x86-amd64.h>
52#include <iprt/asm-math.h>
53#include <iprt/assert.h>
54#include <iprt/string.h>
55#include <iprt/x86.h>
56
57#include "IEMInline.h"
58
59
60/*********************************************************************************************************************************
61* Defined Constants And Macros *
62*********************************************************************************************************************************/
63#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
64/**
65 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
66 * relative offsets.
67 */
68# ifdef IEM_WITH_CODE_TLB /** @todo IEM TLB */
69# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { a_bModRm = 0; RT_NOREF(a_offModRm); } while (0)
70# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { a_bSib = 0; RT_NOREF(a_offSib); } while (0)
71# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
72# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
73# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
75# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
76# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
77# if 0
78# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
79# endif
80# else /* !IEM_WITH_CODE_TLB */
81# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
82 do \
83 { \
84 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
86 } while (0)
87
88# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
89
90# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
91 do \
92 { \
93 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
94 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
95 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
96 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
97 } while (0)
98
99# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
100 do \
101 { \
102 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
103 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
104 } while (0)
105
106# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
107 do \
108 { \
109 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
110 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
111 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
112 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
113 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
114 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
115 } while (0)
116
117# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
118 do \
119 { \
120 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
121 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
122 } while (0)
123
124# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
125 do \
126 { \
127 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
128 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
129 } while (0)
130
131# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
132 do \
133 { \
134 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
135 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
136 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
137 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
138 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
139 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
140 } while (0)
141# endif /* !IEM_WITH_CODE_TLB */
142
143/** Check for VMX instructions requiring to be in VMX operation.
144 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
145# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
146 do \
147 { \
148 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
149 { /* likely */ } \
150 else \
151 { \
152 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
153 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
154 return iemRaiseUndefinedOpcode(a_pVCpu); \
155 } \
156 } while (0)
157
158/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
159# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
160 do \
161 { \
162 LogRel(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
163 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
164 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
165 return VERR_VMX_VMENTRY_FAILED; \
166 } while (0)
167
168/** Marks a VM-exit failure with a diagnostic reason and logs. */
169# define IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
170 do \
171 { \
172 LogRel(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
173 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
174 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
175 } while (0)
176
177/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
178# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
179 do \
180 { \
181 IEM_VMX_VMEXIT_FAILED(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag); \
182 return VERR_VMX_VMEXIT_FAILED; \
183 } while (0)
184
185
186/*********************************************************************************************************************************
187* Global Variables *
188*********************************************************************************************************************************/
189/** @todo NSTVMX: The following VM-exit intercepts are pending:
190 * VMX_EXIT_IO_SMI
191 * VMX_EXIT_SMI
192 * VMX_EXIT_GETSEC
193 * VMX_EXIT_RSM
194 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
195 * VMX_EXIT_ERR_MACHINE_CHECK (we never need to raise this?)
196 * VMX_EXIT_RDRAND
197 * VMX_EXIT_VMFUNC
198 * VMX_EXIT_ENCLS
199 * VMX_EXIT_RDSEED
200 * VMX_EXIT_PML_FULL
201 * VMX_EXIT_XSAVES
202 * VMX_EXIT_XRSTORS
203 */
204/**
205 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
206 *
207 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
208 * second dimension is the Index, see VMXVMCSFIELD.
209 */
210uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
211{
212 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
213 {
214 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
215 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
216 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
217 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u16HlatPrefixSize),
218 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
219 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
220 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
221 /* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
222 },
223 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
224 {
225 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
226 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
227 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
228 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
229 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
230 },
231 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
232 {
233 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
234 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
235 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
236 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
237 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
238 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
239 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
240 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
241 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
242 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
243 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
244 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
245 /* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
246 /* 34 */ UINT16_MAX
247 },
248 /* VMX_VMCSFIELD_WIDTH_16BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
249 {
250 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
251 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
252 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
253 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
254 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
255 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
256 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
257 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
258 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
259 /* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
260 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
261 },
262 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
263 {
264 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
265 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
266 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
267 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
268 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
269 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
270 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
271 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
272 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
273 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
274 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
275 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
276 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
277 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptPtr),
278 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
279 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
280 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
281 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
282 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
283 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
284 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
285 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
286 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssExitBitmap),
287 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64EnclsExitBitmap),
288 /* 24 */ RT_UOFFSETOF(VMXVVMCS, u64SppTablePtr),
289 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier),
290 /* 26 */ RT_UOFFSETOF(VMXVVMCS, u64ProcCtls3),
291 /* 27 */ RT_UOFFSETOF(VMXVVMCS, u64EnclvExitBitmap),
292 /* 28 */ UINT16_MAX,
293 /* 29 */ UINT16_MAX,
294 /* 30 */ UINT16_MAX,
295 /* 31 */ RT_UOFFSETOF(VMXVVMCS, u64PconfigExitBitmap),
296 /* 32 */ RT_UOFFSETOF(VMXVVMCS, u64HlatPtr),
297 /* 33 */ UINT16_MAX,
298 /* 34 */ RT_UOFFSETOF(VMXVVMCS, u64ExitCtls2)
299 },
300 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
301 {
302 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
303 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
304 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
307 /* 33-34*/ UINT16_MAX, UINT16_MAX
308 },
309 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
310 {
311 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
312 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
313 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
314 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
315 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
316 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
317 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
318 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
319 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
320 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
321 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRtitCtlMsr),
322 /* 11 */ UINT16_MAX,
323 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPkrsMsr),
324 /* 13-20 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
325 /* 21-28 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
326 /* 29-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
327 },
328 /* VMX_VMCSFIELD_WIDTH_64BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
329 {
330 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
331 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
332 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
333 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostPkrsMsr),
334 /* 4-11 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
335 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
336 /* 20-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
337 /* 28-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
338 },
339 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_CONTROL: */
340 {
341 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
342 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
343 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
344 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
345 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
346 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
347 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
348 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
349 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
350 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
351 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
352 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
353 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
354 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
355 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
356 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
357 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
358 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
359 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
360 /* 26-33 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
361 /* 34 */ UINT16_MAX
362 },
363 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
364 {
365 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
366 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
367 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
368 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
369 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
370 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
371 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
372 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
373 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
374 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
375 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
376 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
377 },
378 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
379 {
380 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
381 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
382 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
383 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
384 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
385 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
386 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
387 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
388 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
389 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
390 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
391 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
392 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
393 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
394 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
395 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
396 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
397 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
398 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
399 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
400 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
401 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
402 /* 22 */ UINT16_MAX,
403 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
404 /* 24-31 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
405 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
406 },
407 /* VMX_VMCSFIELD_WIDTH_32BIT | VMX_VMCSFIELD_TYPE_HOST_STATE: */
408 {
409 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
410 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
411 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
412 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
413 /* 25-32 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
414 /* 33-34 */ UINT16_MAX, UINT16_MAX
415 },
416 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_CONTROL: */
417 {
418 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
419 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
420 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
421 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
422 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
423 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
424 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
425 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
426 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
427 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
428 /* 24-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
429 /* 32-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
430 },
431 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_VMEXIT_INFO: */
432 {
433 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
434 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
435 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
436 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
437 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
438 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
439 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
440 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
441 /* 22-29 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
442 /* 30-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
443 },
444 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_GUEST_STATE: */
445 {
446 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
447 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
448 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
449 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
450 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
451 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
452 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
453 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
454 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
455 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
456 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
457 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
458 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
459 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
460 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
461 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
462 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
463 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpts),
464 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
465 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
466 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSCetMsr),
467 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsp),
468 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIntrSspTableAddrMsr),
469 /* 23-27 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
470 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
471 },
472 /* VMX_VMCSFIELD_WIDTH_NATURAL | VMX_VMCSFIELD_TYPE_HOST_STATE: */
473 {
474 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
475 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
476 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
477 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
478 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
479 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
480 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
481 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
482 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
483 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
484 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
485 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
486 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64HostSCetMsr),
487 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64HostSsp),
488 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64HostIntrSspTableAddrMsr),
489 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
490 /* 23-30 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
491 /* 31-34 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
492 }
493};
494
495
496/**
497 * Gets a host selector from the VMCS.
498 *
499 * @param pVmcs Pointer to the virtual VMCS.
500 * @param iSelReg The index of the segment register (X86_SREG_XXX).
501 */
502DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
503{
504 Assert(iSegReg < X86_SREG_COUNT);
505 RTSEL HostSel;
506 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
507 uint8_t const uType = VMX_VMCSFIELD_TYPE_HOST_STATE;
508 uint8_t const uWidthType = (uWidth << 2) | uType;
509 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
510 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
511 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
512 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
513 uint8_t const *pbField = pbVmcs + offField;
514 HostSel = *(uint16_t *)pbField;
515 return HostSel;
516}
517
518
519/**
520 * Sets a guest segment register in the VMCS.
521 *
522 * @param pVmcs Pointer to the virtual VMCS.
523 * @param iSegReg The index of the segment register (X86_SREG_XXX).
524 * @param pSelReg Pointer to the segment register.
525 */
526static void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg) RT_NOEXCEPT
527{
528 Assert(pSelReg);
529 Assert(iSegReg < X86_SREG_COUNT);
530
531 /* Selector. */
532 {
533 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
534 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
535 uint8_t const uWidthType = (uWidth << 2) | uType;
536 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
537 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
538 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
539 uint8_t *pbVmcs = (uint8_t *)pVmcs;
540 uint8_t *pbField = pbVmcs + offField;
541 *(uint16_t *)pbField = pSelReg->Sel;
542 }
543
544 /* Limit. */
545 {
546 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
547 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
548 uint8_t const uWidthType = (uWidth << 2) | uType;
549 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
550 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
551 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
552 uint8_t *pbVmcs = (uint8_t *)pVmcs;
553 uint8_t *pbField = pbVmcs + offField;
554 *(uint32_t *)pbField = pSelReg->u32Limit;
555 }
556
557 /* Base. */
558 {
559 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
560 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
561 uint8_t const uWidthType = (uWidth << 2) | uType;
562 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
563 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
564 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
565 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
566 uint8_t const *pbField = pbVmcs + offField;
567 *(uint64_t *)pbField = pSelReg->u64Base;
568 }
569
570 /* Attributes. */
571 {
572 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
573 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
574 | X86DESCATTR_UNUSABLE;
575 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
576 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
577 uint8_t const uWidthType = (uWidth << 2) | uType;
578 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
579 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
580 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
581 uint8_t *pbVmcs = (uint8_t *)pVmcs;
582 uint8_t *pbField = pbVmcs + offField;
583 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
584 }
585}
586
587
588/**
589 * Gets a guest segment register from the VMCS.
590 *
591 * @returns VBox status code.
592 * @param pVmcs Pointer to the virtual VMCS.
593 * @param iSegReg The index of the segment register (X86_SREG_XXX).
594 * @param pSelReg Where to store the segment register (only updated when
595 * VINF_SUCCESS is returned).
596 *
597 * @remarks Warning! This does not validate the contents of the retrieved segment
598 * register.
599 */
600static int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg) RT_NOEXCEPT
601{
602 Assert(pSelReg);
603 Assert(iSegReg < X86_SREG_COUNT);
604
605 /* Selector. */
606 uint16_t u16Sel;
607 {
608 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_16BIT;
609 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
610 uint8_t const uWidthType = (uWidth << 2) | uType;
611 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCSFIELD_INDEX);
612 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
613 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
614 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
615 uint8_t const *pbField = pbVmcs + offField;
616 u16Sel = *(uint16_t *)pbField;
617 }
618
619 /* Limit. */
620 uint32_t u32Limit;
621 {
622 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
623 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
624 uint8_t const uWidthType = (uWidth << 2) | uType;
625 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCSFIELD_INDEX);
626 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
627 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
628 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
629 uint8_t const *pbField = pbVmcs + offField;
630 u32Limit = *(uint32_t *)pbField;
631 }
632
633 /* Base. */
634 uint64_t u64Base;
635 {
636 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_NATURAL;
637 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
638 uint8_t const uWidthType = (uWidth << 2) | uType;
639 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCSFIELD_INDEX);
640 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
641 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
642 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
643 uint8_t const *pbField = pbVmcs + offField;
644 u64Base = *(uint64_t *)pbField;
645 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
646 }
647
648 /* Attributes. */
649 uint32_t u32Attr;
650 {
651 uint8_t const uWidth = VMX_VMCSFIELD_WIDTH_32BIT;
652 uint8_t const uType = VMX_VMCSFIELD_TYPE_GUEST_STATE;
653 uint8_t const uWidthType = (uWidth << 2) | uType;
654 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCSFIELD_INDEX);
655 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
656 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
657 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
658 uint8_t const *pbField = pbVmcs + offField;
659 u32Attr = *(uint32_t *)pbField;
660 }
661
662 pSelReg->Sel = u16Sel;
663 pSelReg->ValidSel = u16Sel;
664 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
665 pSelReg->u32Limit = u32Limit;
666 pSelReg->u64Base = u64Base;
667 pSelReg->Attr.u = u32Attr;
668 return VINF_SUCCESS;
669}
670
671
672/**
673 * Converts an IEM exception event type to a VMX event type.
674 *
675 * @returns The VMX event type.
676 * @param uVector The interrupt / exception vector.
677 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
678 */
679DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
680{
681 /* Paranoia (callers may use these interchangeably). */
682 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
683 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
684 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
685 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
686 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
687 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
688 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
689 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
690 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
691 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
692 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
693 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
694
695 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
696 {
697 if (uVector == X86_XCPT_NMI)
698 return VMX_EXIT_INT_INFO_TYPE_NMI;
699 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
700 }
701
702 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
703 {
704 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
705 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
706 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
707 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
708 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
709 }
710
711 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
712 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
713}
714
715
716/**
717 * Determines whether the guest is using PAE paging given the VMCS.
718 *
719 * @returns @c true if PAE paging mode is used, @c false otherwise.
720 * @param pVmcs Pointer to the virtual VMCS.
721 *
722 * @warning Only use this prior to switching the guest-CPU state with the
723 * nested-guest CPU state!
724 */
725DECL_FORCE_INLINE(bool) iemVmxVmcsIsGuestPaePagingEnabled(PCVMXVVMCS pVmcs)
726{
727 return ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST)
728 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
729 && (pVmcs->u64GuestCr0.u & X86_CR0_PG));
730}
731
732
733/**
734 * Sets the Exit qualification VMCS field.
735 *
736 * @param pVCpu The cross context virtual CPU structure.
737 * @param u64ExitQual The Exit qualification.
738 */
739DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPUCC pVCpu, uint64_t u64ExitQual)
740{
741 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoExitQual.u = u64ExitQual;
742}
743
744
745/**
746 * Sets the VM-exit interruption information field.
747 *
748 * @param pVCpu The cross context virtual CPU structure.
749 * @param uExitIntInfo The VM-exit interruption information.
750 */
751DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPUCC pVCpu, uint32_t uExitIntInfo)
752{
753 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntInfo = uExitIntInfo;
754}
755
756
757/**
758 * Sets the VM-exit interruption error code.
759 *
760 * @param pVCpu The cross context virtual CPU structure.
761 * @param uErrCode The error code.
762 */
763DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
764{
765 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitIntErrCode = uErrCode;
766}
767
768
769/**
770 * Sets the IDT-vectoring information field.
771 *
772 * @param pVCpu The cross context virtual CPU structure.
773 * @param uIdtVectorInfo The IDT-vectoring information.
774 */
775DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPUCC pVCpu, uint32_t uIdtVectorInfo)
776{
777 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo = uIdtVectorInfo;
778}
779
780
781/**
782 * Sets the IDT-vectoring error code field.
783 *
784 * @param pVCpu The cross context virtual CPU structure.
785 * @param uErrCode The error code.
786 */
787DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPUCC pVCpu, uint32_t uErrCode)
788{
789 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringErrCode = uErrCode;
790}
791
792
793/**
794 * Sets the VM-exit guest-linear address VMCS field.
795 *
796 * @param pVCpu The cross context virtual CPU structure.
797 * @param uGuestLinearAddr The VM-exit guest-linear address.
798 */
799DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPUCC pVCpu, uint64_t uGuestLinearAddr)
800{
801 /* Bits 63:32 of guest-linear address MBZ if the guest isn't in long mode prior to the VM-exit. */
802 Assert(CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)) || !(uGuestLinearAddr & UINT64_C(0xffffffff00000000)));
803 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestLinearAddr.u = uGuestLinearAddr;
804}
805
806
807/**
808 * Sets the VM-exit guest-physical address VMCS field.
809 *
810 * @param pVCpu The cross context virtual CPU structure.
811 * @param uGuestPhysAddr The VM-exit guest-physical address.
812 */
813DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPUCC pVCpu, uint64_t uGuestPhysAddr)
814{
815 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64RoGuestPhysAddr.u = uGuestPhysAddr;
816}
817
818
819/**
820 * Sets the VM-exit instruction length VMCS field.
821 *
822 * @param pVCpu The cross context virtual CPU structure.
823 * @param cbInstr The VM-exit instruction length in bytes.
824 *
825 * @remarks Callers may clear this field to 0. Hence, this function does not check
826 * the validity of the instruction length.
827 */
828DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPUCC pVCpu, uint32_t cbInstr)
829{
830 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrLen = cbInstr;
831}
832
833
834/**
835 * Sets the VM-exit instruction info. VMCS field.
836 *
837 * @param pVCpu The cross context virtual CPU structure.
838 * @param uExitInstrInfo The VM-exit instruction information.
839 */
840DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitInstrInfo)
841{
842 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoExitInstrInfo = uExitInstrInfo;
843}
844
845
846/**
847 * Sets the guest pending-debug exceptions field.
848 *
849 * @param pVCpu The cross context virtual CPU structure.
850 * @param uGuestPendingDbgXcpts The guest pending-debug exceptions.
851 */
852DECL_FORCE_INLINE(void) iemVmxVmcsSetGuestPendingDbgXcpts(PVMCPUCC pVCpu, uint64_t uGuestPendingDbgXcpts)
853{
854 Assert(!(uGuestPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK));
855 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestPendingDbgXcpts.u = uGuestPendingDbgXcpts;
856}
857
858
859/**
860 * Implements VMSucceed for VMX instruction success.
861 *
862 * @param pVCpu The cross context virtual CPU structure.
863 */
864DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPUCC pVCpu)
865{
866 return CPUMSetGuestVmxVmSucceed(&pVCpu->cpum.GstCtx);
867}
868
869
870/**
871 * Implements VMFailInvalid for VMX instruction failure.
872 *
873 * @param pVCpu The cross context virtual CPU structure.
874 */
875DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPUCC pVCpu)
876{
877 return CPUMSetGuestVmxVmFailInvalid(&pVCpu->cpum.GstCtx);
878}
879
880
881/**
882 * Implements VMFail for VMX instruction failure.
883 *
884 * @param pVCpu The cross context virtual CPU structure.
885 * @param enmInsErr The VM instruction error.
886 */
887DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPUCC pVCpu, VMXINSTRERR enmInsErr)
888{
889 return CPUMSetGuestVmxVmFail(&pVCpu->cpum.GstCtx, enmInsErr);
890}
891
892
893/**
894 * Checks if the given auto-load/store MSR area count is valid for the
895 * implementation.
896 *
897 * @returns @c true if it's within the valid limit, @c false otherwise.
898 * @param pVCpu The cross context virtual CPU structure.
899 * @param uMsrCount The MSR area count to check.
900 */
901DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PCVMCPU pVCpu, uint32_t uMsrCount)
902{
903 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
904 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
905 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
906 if (uMsrCount <= cMaxSupportedMsrs)
907 return true;
908 return false;
909}
910
911
912/**
913 * Flushes the current VMCS contents back to guest memory.
914 *
915 * @returns VBox status code.
916 * @param pVCpu The cross context virtual CPU structure.
917 */
918DECL_FORCE_INLINE(int) iemVmxWriteCurrentVmcsToGstMem(PVMCPUCC pVCpu)
919{
920 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
921 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
922 &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
923 return rc;
924}
925
926
927/**
928 * Populates the current VMCS contents from guest memory.
929 *
930 * @returns VBox status code.
931 * @param pVCpu The cross context virtual CPU structure.
932 */
933DECL_FORCE_INLINE(int) iemVmxReadCurrentVmcsFromGstMem(PVMCPUCC pVCpu)
934{
935 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
936 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs,
937 IEM_VMX_GET_CURRENT_VMCS(pVCpu), sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs));
938 return rc;
939}
940
941
942/**
943 * Gets the instruction diagnostic for segment base checks during VM-entry of a
944 * nested-guest.
945 *
946 * @param iSegReg The segment index (X86_SREG_XXX).
947 */
948static VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg) RT_NOEXCEPT
949{
950 switch (iSegReg)
951 {
952 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
953 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
954 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
955 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
956 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
957 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
958 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
959 }
960}
961
962
963/**
964 * Gets the instruction diagnostic for segment base checks during VM-entry of a
965 * nested-guest that is in Virtual-8086 mode.
966 *
967 * @param iSegReg The segment index (X86_SREG_XXX).
968 */
969static VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg) RT_NOEXCEPT
970{
971 switch (iSegReg)
972 {
973 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
974 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
975 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
976 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
977 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
978 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
979 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
980 }
981}
982
983
984/**
985 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
986 * nested-guest that is in Virtual-8086 mode.
987 *
988 * @param iSegReg The segment index (X86_SREG_XXX).
989 */
990static VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg) RT_NOEXCEPT
991{
992 switch (iSegReg)
993 {
994 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
995 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
996 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
997 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
998 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
999 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1000 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1001 }
1002}
1003
1004
1005/**
1006 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1007 * nested-guest that is in Virtual-8086 mode.
1008 *
1009 * @param iSegReg The segment index (X86_SREG_XXX).
1010 */
1011static VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg) RT_NOEXCEPT
1012{
1013 switch (iSegReg)
1014 {
1015 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1016 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1017 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1018 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1019 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1020 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1021 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1022 }
1023}
1024
1025
1026/**
1027 * Gets the instruction diagnostic for segment attributes reserved bits failure
1028 * during VM-entry of a nested-guest.
1029 *
1030 * @param iSegReg The segment index (X86_SREG_XXX).
1031 */
1032static VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg) RT_NOEXCEPT
1033{
1034 switch (iSegReg)
1035 {
1036 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1037 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1038 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1039 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1040 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1041 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1042 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1043 }
1044}
1045
1046
1047/**
1048 * Gets the instruction diagnostic for segment attributes descriptor-type
1049 * (code/segment or system) failure during VM-entry of a nested-guest.
1050 *
1051 * @param iSegReg The segment index (X86_SREG_XXX).
1052 */
1053static VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg) RT_NOEXCEPT
1054{
1055 switch (iSegReg)
1056 {
1057 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1058 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1059 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1060 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1061 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1062 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1063 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1064 }
1065}
1066
1067
1068/**
1069 * Gets the instruction diagnostic for segment attributes descriptor-type
1070 * (code/segment or system) failure during VM-entry of a nested-guest.
1071 *
1072 * @param iSegReg The segment index (X86_SREG_XXX).
1073 */
1074static VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg) RT_NOEXCEPT
1075{
1076 switch (iSegReg)
1077 {
1078 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1079 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1080 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1081 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1082 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1083 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1084 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1085 }
1086}
1087
1088
1089/**
1090 * Gets the instruction diagnostic for segment attribute granularity failure during
1091 * VM-entry of a nested-guest.
1092 *
1093 * @param iSegReg The segment index (X86_SREG_XXX).
1094 */
1095static VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg) RT_NOEXCEPT
1096{
1097 switch (iSegReg)
1098 {
1099 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1100 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1101 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1102 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1103 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1104 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1105 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1106 }
1107}
1108
1109/**
1110 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1111 * VM-entry of a nested-guest.
1112 *
1113 * @param iSegReg The segment index (X86_SREG_XXX).
1114 */
1115static VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg) RT_NOEXCEPT
1116{
1117 switch (iSegReg)
1118 {
1119 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1120 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1121 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1122 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1123 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1124 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1125 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1126 }
1127}
1128
1129
1130/**
1131 * Gets the instruction diagnostic for segment attribute type accessed failure
1132 * during VM-entry of a nested-guest.
1133 *
1134 * @param iSegReg The segment index (X86_SREG_XXX).
1135 */
1136static VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg) RT_NOEXCEPT
1137{
1138 switch (iSegReg)
1139 {
1140 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1141 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1142 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1143 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1144 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1145 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1146 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1147 }
1148}
1149
1150
1151/**
1152 * Saves the guest control registers, debug registers and some MSRs are part of
1153 * VM-exit.
1154 *
1155 * @param pVCpu The cross context virtual CPU structure.
1156 */
1157static void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1158{
1159 /*
1160 * Saves the guest control registers, debug registers and some MSRs.
1161 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1162 */
1163 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1164
1165 /* Save control registers. */
1166 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1167 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1168 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1169
1170 /* Save SYSENTER CS, ESP, EIP. */
1171 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1172 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1173 {
1174 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1175 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1176 }
1177 else
1178 {
1179 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1180 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1181 }
1182
1183 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1184 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1185 {
1186 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1187 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1188 }
1189
1190 /* Save PAT MSR. */
1191 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1192 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1193
1194 /* Save EFER MSR. */
1195 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1196 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1197
1198 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1199 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1200
1201 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1202}
1203
1204
1205/**
1206 * Saves the guest force-flags in preparation of entering the nested-guest.
1207 *
1208 * @param pVCpu The cross context virtual CPU structure.
1209 */
1210static void iemVmxVmentrySaveNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1211{
1212 /* We shouldn't be called multiple times during VM-entry. */
1213 Assert(pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit == 0);
1214
1215 /* MTF should not be set outside VMX non-root mode. */
1216 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1217
1218 /*
1219 * Preserve the required force-flags.
1220 *
1221 * We cache and clear force-flags that would affect the execution of the
1222 * nested-guest. Cached flags are then restored while returning to the guest
1223 * if necessary.
1224 *
1225 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1226 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1227 * instruction. Interrupt inhibition for any nested-guest instruction
1228 * is supplied by the guest-interruptibility state VMCS field and will
1229 * be set up as part of loading the guest state. Technically
1230 * blocking-by-STI is possible with VMLAUNCH/VMRESUME but we currently
1231 * disallow it since we can't distinguish it from blocking-by-MovSS
1232 * and no nested-hypervisor we care about uses STI immediately
1233 * followed by VMLAUNCH/VMRESUME.
1234 *
1235 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1236 * successful VM-entry (due to invalid guest-state) need to continue
1237 * blocking NMIs if it was in effect before VM-entry.
1238 *
1239 * - MTF need not be preserved as it's used only in VMX non-root mode and
1240 * is supplied through the VM-execution controls.
1241 *
1242 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1243 * we will be able to generate interrupts that may cause VM-exits for
1244 * the nested-guest.
1245 */
1246 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_INHIBIT_NMI;
1247}
1248
1249
1250/**
1251 * Restores the guest force-flags in preparation of exiting the nested-guest.
1252 *
1253 * @param pVCpu The cross context virtual CPU structure.
1254 */
1255static void iemVmxVmexitRestoreNmiBlockingFF(PVMCPUCC pVCpu) RT_NOEXCEPT
1256{
1257 /** @todo r=bird: why aren't we clearing the nested guest flags first here?
1258 * If there is some other code doing that already, it would be great
1259 * to point to it here... */
1260 pVCpu->cpum.GstCtx.eflags.uBoth |= pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit;
1261 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit = 0;
1262}
1263
1264
1265/**
1266 * Performs the VMX transition to/from VMX non-root mode.
1267 *
1268 * @param pVCpu The cross context virtual CPU structure.
1269*/
1270static int iemVmxTransition(PVMCPUCC pVCpu) RT_NOEXCEPT
1271{
1272 /*
1273 * Inform PGM about paging mode changes.
1274 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1275 * see comment in iemMemPageTranslateAndCheckAccess().
1276 */
1277 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1278 true /* fForce */);
1279 if (RT_SUCCESS(rc))
1280 { /* likely */ }
1281 else
1282 return rc;
1283
1284 /* Invalidate IEM TLBs now that we've forced a PGM mode change. */
1285 IEMTlbInvalidateAll(pVCpu);
1286
1287 /* Inform CPUM (recompiler), can later be removed. */
1288 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1289
1290 /* Re-initialize IEM cache/state after the drastic mode switch. */
1291 iemReInitExec(pVCpu);
1292 return rc;
1293}
1294
1295
1296/**
1297 * Calculates the current VMX-preemption timer value.
1298 *
1299 * @returns The current VMX-preemption timer value.
1300 * @param pVCpu The cross context virtual CPU structure.
1301 */
1302static uint32_t iemVmxCalcPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
1303{
1304 /*
1305 * Assume the following:
1306 * PreemptTimerShift = 5
1307 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1308 * EntryTick = 50000 (TSC at time of VM-entry)
1309 *
1310 * CurTick Delta PreemptTimerVal
1311 * ----------------------------------
1312 * 60000 10000 2
1313 * 80000 30000 1
1314 * 90000 40000 0 -> VM-exit.
1315 *
1316 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1317 * The saved VMX-preemption timer value is calculated as follows:
1318 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1319 * E.g.:
1320 * Delta = 10000
1321 * Tmp = 10000 / (2 * 10000) = 0.5
1322 * NewPt = 2 - 0.5 = 2
1323 * Delta = 30000
1324 * Tmp = 30000 / (2 * 10000) = 1.5
1325 * NewPt = 2 - 1.5 = 1
1326 * Delta = 40000
1327 * Tmp = 40000 / 20000 = 2
1328 * NewPt = 2 - 2 = 0
1329 */
1330 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1331 uint32_t const uVmcsPreemptVal = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer;
1332 if (uVmcsPreemptVal > 0)
1333 {
1334 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1335 uint64_t const uEntryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick;
1336 uint64_t const uDelta = uCurTick - uEntryTick;
1337 uint32_t const uPreemptTimer = uVmcsPreemptVal
1338 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1339 return uPreemptTimer;
1340 }
1341 return 0;
1342}
1343
1344
1345/**
1346 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1347 *
1348 * @param pVCpu The cross context virtual CPU structure.
1349 */
1350static void iemVmxVmexitSaveGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1351{
1352 /*
1353 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1354 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1355 */
1356 /* CS, SS, ES, DS, FS, GS. */
1357 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1358 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1359 {
1360 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1361 if (!pSelReg->Attr.n.u1Unusable)
1362 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1363 else
1364 {
1365 /*
1366 * For unusable segments the attributes are undefined except for CS and SS.
1367 * For the rest we don't bother preserving anything but the unusable bit.
1368 */
1369 switch (iSegReg)
1370 {
1371 case X86_SREG_CS:
1372 pVmcs->GuestCs = pSelReg->Sel;
1373 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1374 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1375 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1376 | X86DESCATTR_UNUSABLE);
1377 break;
1378
1379 case X86_SREG_SS:
1380 pVmcs->GuestSs = pSelReg->Sel;
1381 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1382 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1383 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1384 break;
1385
1386 case X86_SREG_DS:
1387 pVmcs->GuestDs = pSelReg->Sel;
1388 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1389 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1390 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1391 break;
1392
1393 case X86_SREG_ES:
1394 pVmcs->GuestEs = pSelReg->Sel;
1395 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1396 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1397 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1398 break;
1399
1400 case X86_SREG_FS:
1401 pVmcs->GuestFs = pSelReg->Sel;
1402 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1403 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1404 break;
1405
1406 case X86_SREG_GS:
1407 pVmcs->GuestGs = pSelReg->Sel;
1408 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1409 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1410 break;
1411 }
1412 }
1413 }
1414
1415 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1416 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1417 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1418 | X86DESCATTR_UNUSABLE;
1419 /* LDTR. */
1420 {
1421 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1422 pVmcs->GuestLdtr = pSelReg->Sel;
1423 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1424 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1425 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1426 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1427 }
1428
1429 /* TR. */
1430 {
1431 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1432 pVmcs->GuestTr = pSelReg->Sel;
1433 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1434 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1435 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1436 }
1437
1438 /* GDTR. */
1439 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1440 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1441
1442 /* IDTR. */
1443 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1444 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1445}
1446
1447
1448/**
1449 * Saves guest non-register state as part of VM-exit.
1450 *
1451 * @param pVCpu The cross context virtual CPU structure.
1452 * @param uExitReason The VM-exit reason.
1453 */
1454static void iemVmxVmexitSaveGuestNonRegState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1455{
1456 /*
1457 * Save guest non-register state.
1458 * See Intel spec. 27.3.4 "Saving Non-Register State".
1459 */
1460 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1461
1462 /*
1463 * Activity state.
1464 * Most VM-exits will occur in the active state. However, if the first instruction
1465 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1466 * the VM-exit will be from the HLT activity state.
1467 *
1468 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1469 */
1470 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1471 * not? */
1472 EMSTATE const enmActivityState = EMGetState(pVCpu);
1473 switch (enmActivityState)
1474 {
1475 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1476 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1477 }
1478
1479 /*
1480 * Interruptibility-state.
1481 */
1482 /* NMI. */
1483 pVmcs->u32GuestIntrState = 0;
1484 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
1485 {
1486 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking)
1487 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1488 }
1489 else
1490 {
1491 if (CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx))
1492 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1493 }
1494
1495 /* Blocking-by-STI or blocking-by-MovSS. */
1496 uint32_t fInhibitShw;
1497 if (!CPUMIsInInterruptShadowWithUpdateEx(&pVCpu->cpum.GstCtx, &fInhibitShw))
1498 { /* probable */}
1499 else
1500 {
1501 if (pVCpu->cpum.GstCtx.rip == pVCpu->cpum.GstCtx.uRipInhibitInt)
1502 {
1503 /*
1504 * We must ensure only one of these bits is set.
1505 * Our emulation can have both set (perhaps because AMD doesn't distinguish
1506 * between the two?). Hence, the 'else' with blocking-by-MovSS taking priority
1507 * since it blocks more. Nested Ubuntu 22.04.2 running inside a Hyper-V enabled
1508 * Windows Server 2008 R2 guest runs into this issue.
1509 *
1510 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
1511 */
1512 if (fInhibitShw & CPUMCTX_INHIBIT_SHADOW_SS)
1513 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS;
1514 else
1515 {
1516 Assert(fInhibitShw & CPUMCTX_INHIBIT_SHADOW_STI);
1517 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1518 }
1519 }
1520 }
1521 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1522
1523 /*
1524 * Pending debug exceptions.
1525 *
1526 * For VM-exits where it is not applicable, we can safely zero out the field.
1527 * For VM-exits where it is applicable, it's expected to be updated by the caller already.
1528 */
1529 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1530 && uExitReason != VMX_EXIT_SMI
1531 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1532 && !VMXIsVmexitTrapLike(uExitReason))
1533 {
1534 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1535 * block-by-MovSS is in effect. */
1536 pVmcs->u64GuestPendingDbgXcpts.u = 0;
1537 }
1538
1539 /*
1540 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1541 *
1542 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1543 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1544 */
1545 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1546 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1547 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1548
1549 /*
1550 * Save the guest PAE PDPTEs.
1551 */
1552 if ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
1553 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
1554 {
1555 /*
1556 * Without EPT or when the nested-guest is not using PAE paging, the values saved
1557 * in the VMCS during VM-exit are undefined. We zero them here for consistency.
1558 */
1559 pVmcs->u64GuestPdpte0.u = 0;
1560 pVmcs->u64GuestPdpte1.u = 0;
1561 pVmcs->u64GuestPdpte2.u = 0;
1562 pVmcs->u64GuestPdpte3.u = 0;
1563 }
1564 else
1565 {
1566 /*
1567 * With EPT and when the nested-guest is using PAE paging, we update the PDPTEs from
1568 * the nested-guest CPU context. Both IEM (Mov CRx) and hardware-assisted execution
1569 * of the nested-guest is expected to have updated them.
1570 */
1571 pVmcs->u64GuestPdpte0.u = pVCpu->cpum.GstCtx.aPaePdpes[0].u;
1572 pVmcs->u64GuestPdpte1.u = pVCpu->cpum.GstCtx.aPaePdpes[1].u;
1573 pVmcs->u64GuestPdpte2.u = pVCpu->cpum.GstCtx.aPaePdpes[2].u;
1574 pVmcs->u64GuestPdpte3.u = pVCpu->cpum.GstCtx.aPaePdpes[3].u;
1575 }
1576
1577 /* Clear PGM's copy of the EPT pointer for added safety. */
1578 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
1579 PGMSetGuestEptPtr(pVCpu, 0 /* uEptPtr */);
1580}
1581
1582
1583/**
1584 * Saves the guest-state as part of VM-exit.
1585 *
1586 * @returns VBox status code.
1587 * @param pVCpu The cross context virtual CPU structure.
1588 * @param uExitReason The VM-exit reason.
1589 */
1590static void iemVmxVmexitSaveGuestState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1591{
1592 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1593 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1594
1595 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1596 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1597 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1598
1599 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1600}
1601
1602
1603/**
1604 * Saves the guest MSRs into the VM-exit MSR-store area as part of VM-exit.
1605 *
1606 * @returns VBox status code.
1607 * @param pVCpu The cross context virtual CPU structure.
1608 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1609 */
1610static int iemVmxVmexitSaveGuestAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1611{
1612 /*
1613 * Save guest MSRs.
1614 * See Intel spec. 27.4 "Saving MSRs".
1615 */
1616 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1617 const char * const pszFailure = "VMX-abort";
1618
1619 /*
1620 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1621 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1622 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1623 */
1624 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrStoreCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea));
1625 if (!cMsrs)
1626 return VINF_SUCCESS;
1627
1628 /*
1629 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1630 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1631 * implementation causes a VMX-abort followed by a triple-fault.
1632 */
1633 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1634 if (fIsMsrCountValid)
1635 { /* likely */ }
1636 else
1637 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1638
1639 /*
1640 * Optimization if the nested hypervisor is using the same guest-physical page for both
1641 * the VM-entry MSR-load area as well as the VM-exit MSR store area.
1642 */
1643 PVMXAUTOMSR pMsrArea;
1644 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
1645 RTGCPHYS const GCPhysVmExitMsrStoreArea = pVmcs->u64AddrExitMsrStore.u;
1646 if (GCPhysVmEntryMsrLoadArea == GCPhysVmExitMsrStoreArea)
1647 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea;
1648 else
1649 {
1650 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea[0],
1651 GCPhysVmExitMsrStoreArea, cMsrs * sizeof(VMXAUTOMSR));
1652 if (RT_SUCCESS(rc))
1653 pMsrArea = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrStoreArea;
1654 else
1655 {
1656 AssertMsgFailed(("VM-exit: Failed to read MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1657 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrReadPhys);
1658 }
1659 }
1660
1661 /*
1662 * Update VM-exit MSR store area.
1663 */
1664 PVMXAUTOMSR pMsr = pMsrArea;
1665 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1666 {
1667 if ( !pMsr->u32Reserved
1668 && pMsr->u32Msr != MSR_IA32_SMBASE
1669 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1670 {
1671 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1672 if (rcStrict == VINF_SUCCESS)
1673 continue;
1674
1675 /*
1676 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1677 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1678 * recording the MSR index in the auxiliary info. field and indicated further by our
1679 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1680 * if possible, or come up with a better, generic solution.
1681 */
1682 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1683 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1684 ? kVmxVDiag_Vmexit_MsrStoreRing3
1685 : kVmxVDiag_Vmexit_MsrStore;
1686 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1687 }
1688 else
1689 {
1690 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1691 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1692 }
1693 }
1694
1695 /*
1696 * Commit the VM-exit MSR store are to guest memory.
1697 */
1698 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmExitMsrStoreArea, pMsrArea, cMsrs * sizeof(VMXAUTOMSR));
1699 if (RT_SUCCESS(rc))
1700 return VINF_SUCCESS;
1701
1702 NOREF(uExitReason);
1703 NOREF(pszFailure);
1704
1705 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrStoreArea, rc));
1706 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1707}
1708
1709
1710/**
1711 * Performs a VMX abort (due to an fatal error during VM-exit).
1712 *
1713 * @returns Strict VBox status code.
1714 * @param pVCpu The cross context virtual CPU structure.
1715 * @param enmAbort The VMX abort reason.
1716 */
1717static VBOXSTRICTRC iemVmxAbort(PVMCPUCC pVCpu, VMXABORT enmAbort) RT_NOEXCEPT
1718{
1719 /*
1720 * Perform the VMX abort.
1721 * See Intel spec. 27.7 "VMX Aborts".
1722 */
1723 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, VMXGetAbortDesc(enmAbort)));
1724
1725 /* We don't support SMX yet. */
1726 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
1727 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
1728 {
1729 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
1730 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
1731 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
1732 }
1733
1734 return VINF_EM_TRIPLE_FAULT;
1735}
1736
1737
1738/**
1739 * Loads host control registers, debug registers and MSRs as part of VM-exit.
1740 *
1741 * @param pVCpu The cross context virtual CPU structure.
1742 */
1743static void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
1744{
1745 /*
1746 * Load host control registers, debug registers and MSRs.
1747 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
1748 */
1749 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1750 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1751
1752 /* CR0. */
1753 {
1754 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 fixed bits are not modified. */
1755 uint64_t const fCr0IgnMask = VMX_EXIT_HOST_CR0_IGNORE_MASK;
1756 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
1757 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
1758 uint64_t const uValidHostCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
1759
1760 /* Verify we have not modified CR0 fixed bits in VMX operation. */
1761#ifdef VBOX_STRICT
1762 uint64_t const uCr0Mb1 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
1763 bool const fUx = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1764 AssertMsg( (uValidHostCr0 & uCr0Mb1) == uCr0Mb1
1765 && (uValidHostCr0 & ~VMX_V_CR0_FIXED1) == 0,
1766 ("host=%#RX64 guest=%#RX64 mb1=%#RX64 valid_host_cr0=%#RX64 fUx=%RTbool\n",
1767 uHostCr0, uGuestCr0, uCr0Mb1, uValidHostCr0, fUx));
1768#endif
1769 Assert(!(uValidHostCr0 >> 32));
1770 CPUMSetGuestCR0(pVCpu, uValidHostCr0);
1771 }
1772
1773 /* CR4. */
1774 {
1775 /* CR4 fixed bits are not modified. */
1776 uint64_t const uCr4Mb1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
1777 uint64_t const uCr4Mb0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
1778 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
1779 uint64_t uValidHostCr4 = (uHostCr4 & uCr4Mb0) | uCr4Mb1;
1780 if (fHostInLongMode)
1781 uValidHostCr4 |= X86_CR4_PAE;
1782 else
1783 uValidHostCr4 &= ~(uint64_t)X86_CR4_PCIDE;
1784
1785 /* Verify we have not modified CR4 fixed bits in VMX non-root operation. */
1786 AssertMsg( (uValidHostCr4 & uCr4Mb1) == uCr4Mb1
1787 && (uValidHostCr4 & ~uCr4Mb0) == 0,
1788 ("host=%#RX64 guest=%#RX64, uCr4Mb1=%#RX64 uCr4Mb0=%#RX64 valid_host_cr4=%#RX64\n",
1789 uHostCr4, pVCpu->cpum.GstCtx.cr4, uCr4Mb1, uCr4Mb0, uValidHostCr4));
1790 CPUMSetGuestCR4(pVCpu, uValidHostCr4);
1791 }
1792
1793 /* CR3 (host value validated while checking host-state during VM-entry). */
1794 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
1795
1796 /* DR7. */
1797 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
1798
1799 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1800
1801 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
1802 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
1803 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
1804 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
1805
1806 /* FS, GS bases are loaded later while we load host segment registers. */
1807
1808 /* EFER MSR (host value validated while checking host-state during VM-entry). */
1809 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1810 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
1811 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1812 {
1813 if (fHostInLongMode)
1814 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1815 else
1816 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
1817 }
1818
1819 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
1820
1821 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
1822 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
1823 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
1824
1825 /* We don't support IA32_BNDCFGS MSR yet. */
1826}
1827
1828
1829/**
1830 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
1831 *
1832 * @param pVCpu The cross context virtual CPU structure.
1833 */
1834static void iemVmxVmexitLoadHostSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
1835{
1836 /*
1837 * Load host segment registers, GDTR, IDTR, LDTR and TR.
1838 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
1839 *
1840 * Warning! Be careful to not touch fields that are reserved by VT-x,
1841 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
1842 */
1843 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1844 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1845
1846 /* CS, SS, ES, DS, FS, GS. */
1847 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1848 {
1849 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
1850 bool const fUnusable = RT_BOOL(HostSel == 0);
1851 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1852
1853 /* Selector. */
1854 pSelReg->Sel = HostSel;
1855 pSelReg->ValidSel = HostSel;
1856 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
1857
1858 /* Limit. */
1859 pSelReg->u32Limit = 0xffffffff;
1860
1861 /* Base. */
1862 pSelReg->u64Base = 0;
1863
1864 /* Attributes. */
1865 if (iSegReg == X86_SREG_CS)
1866 {
1867 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
1868 pSelReg->Attr.n.u1DescType = 1;
1869 pSelReg->Attr.n.u2Dpl = 0;
1870 pSelReg->Attr.n.u1Present = 1;
1871 pSelReg->Attr.n.u1Long = fHostInLongMode;
1872 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
1873 pSelReg->Attr.n.u1Granularity = 1;
1874 Assert(!pSelReg->Attr.n.u1Unusable);
1875 Assert(!fUnusable);
1876 }
1877 else
1878 {
1879 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
1880 pSelReg->Attr.n.u1DescType = 1;
1881 pSelReg->Attr.n.u2Dpl = 0;
1882 pSelReg->Attr.n.u1Present = 1;
1883 pSelReg->Attr.n.u1DefBig = 1;
1884 pSelReg->Attr.n.u1Granularity = 1;
1885 pSelReg->Attr.n.u1Unusable = fUnusable;
1886 }
1887 }
1888
1889 /* FS base. */
1890 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
1891 || fHostInLongMode)
1892 {
1893 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
1894 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
1895 }
1896
1897 /* GS base. */
1898 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
1899 || fHostInLongMode)
1900 {
1901 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
1902 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
1903 }
1904
1905 /* TR. */
1906 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
1907 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
1908 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
1909 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
1910 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1911 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
1912 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
1913 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1914 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
1915 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
1916 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
1917 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
1918 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
1919
1920 /* LDTR (Warning! do not touch the base and limits here). */
1921 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
1922 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
1923 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1924 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
1925
1926 /* GDTR. */
1927 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
1928 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
1929 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
1930
1931 /* IDTR.*/
1932 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
1933 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
1934 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
1935}
1936
1937
1938/**
1939 * Loads the host MSRs from the VM-exit MSR-load area as part of VM-exit.
1940 *
1941 * @returns VBox status code.
1942 * @param pVCpu The cross context virtual CPU structure.
1943 * @param uExitReason The VMX instruction name (for logging purposes).
1944 */
1945static int iemVmxVmexitLoadHostAutoMsrs(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
1946{
1947 /*
1948 * Load host MSRs.
1949 * See Intel spec. 27.6 "Loading MSRs".
1950 */
1951 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
1952 const char * const pszFailure = "VMX-abort";
1953
1954 /*
1955 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
1956 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
1957 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1958 */
1959 uint32_t const cMsrs = RT_MIN(pVmcs->u32ExitMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea));
1960 if (!cMsrs)
1961 return VINF_SUCCESS;
1962
1963 /*
1964 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
1965 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1966 * implementation causes a VMX-abort followed by a triple-fault.
1967 */
1968 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1969 if (fIsMsrCountValid)
1970 { /* likely */ }
1971 else
1972 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
1973
1974 RTGCPHYS const GCPhysVmExitMsrLoadArea = pVmcs->u64AddrExitMsrLoad.u;
1975 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea[0],
1976 GCPhysVmExitMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
1977 if (RT_SUCCESS(rc))
1978 {
1979 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.aExitMsrLoadArea;
1980 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1981 {
1982 if ( !pMsr->u32Reserved
1983 && pMsr->u32Msr != MSR_K8_FS_BASE
1984 && pMsr->u32Msr != MSR_K8_GS_BASE
1985 && pMsr->u32Msr != MSR_K6_EFER
1986 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
1987 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1988 {
1989 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
1990 if (rcStrict == VINF_SUCCESS)
1991 continue;
1992
1993 /*
1994 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1995 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1996 * recording the MSR index in the auxiliary info. field and indicated further by our
1997 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1998 * if possible, or come up with a better, generic solution.
1999 */
2000 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2001 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2002 ? kVmxVDiag_Vmexit_MsrLoadRing3
2003 : kVmxVDiag_Vmexit_MsrLoad;
2004 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2005 }
2006 else
2007 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2008 }
2009 }
2010 else
2011 {
2012 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysVmExitMsrLoadArea, rc));
2013 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2014 }
2015
2016 NOREF(uExitReason);
2017 NOREF(pszFailure);
2018 return VINF_SUCCESS;
2019}
2020
2021
2022/**
2023 * Loads the host state as part of VM-exit.
2024 *
2025 * @returns Strict VBox status code.
2026 * @param pVCpu The cross context virtual CPU structure.
2027 * @param uExitReason The VM-exit reason (for logging purposes).
2028 */
2029static VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPUCC pVCpu, uint32_t uExitReason) RT_NOEXCEPT
2030{
2031 /*
2032 * Load host state.
2033 * See Intel spec. 27.5 "Loading Host State".
2034 */
2035 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2036 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2037
2038 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2039 if ( CPUMIsGuestInLongMode(pVCpu)
2040 && !fHostInLongMode)
2041 {
2042 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2043 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2044 }
2045
2046 /*
2047 * Check host PAE PDPTEs prior to loading the host state.
2048 * See Intel spec. 26.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2049 */
2050 if ( (pVmcs->u64HostCr4.u & X86_CR4_PAE)
2051 && !fHostInLongMode
2052 && ( !CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx)
2053 || pVmcs->u64HostCr3.u != pVCpu->cpum.GstCtx.cr3))
2054 {
2055 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64HostCr3.u);
2056 if (RT_SUCCESS(rc))
2057 { /* likely*/ }
2058 else
2059 {
2060 IEM_VMX_VMEXIT_FAILED(pVCpu, uExitReason, "VMX-abort", kVmxVDiag_Vmexit_HostPdpte);
2061 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2062 }
2063 }
2064
2065 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2066 iemVmxVmexitLoadHostSegRegs(pVCpu);
2067
2068 /*
2069 * Load host RIP, RSP and RFLAGS.
2070 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2071 */
2072 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2073 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2074 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2075
2076 /* Clear address range monitoring. */
2077 EMMonitorWaitClear(pVCpu);
2078
2079 /* Perform the VMX transition (PGM updates). */
2080 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
2081 if (rcStrict == VINF_SUCCESS)
2082 { /* likely */ }
2083 else if (RT_SUCCESS(rcStrict))
2084 {
2085 Log3(("VM-exit: iemVmxTransition returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2086 uExitReason));
2087 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2088 }
2089 else
2090 {
2091 Log3(("VM-exit: iemVmxTransition failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2092 return VBOXSTRICTRC_VAL(rcStrict);
2093 }
2094
2095 Assert(rcStrict == VINF_SUCCESS);
2096
2097 /* Load MSRs from the VM-exit auto-load MSR area. */
2098 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2099 if (RT_FAILURE(rc))
2100 {
2101 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2102 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2103 }
2104 return VINF_SUCCESS;
2105}
2106
2107
2108/**
2109 * Gets VM-exit instruction information along with any displacement for an
2110 * instruction VM-exit.
2111 *
2112 * @returns The VM-exit instruction information.
2113 * @param pVCpu The cross context virtual CPU structure.
2114 * @param uExitReason The VM-exit reason.
2115 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2116 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2117 * NULL.
2118 */
2119static uint32_t iemVmxGetExitInstrInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp) RT_NOEXCEPT
2120{
2121 RTGCPTR GCPtrDisp;
2122 VMXEXITINSTRINFO ExitInstrInfo;
2123 ExitInstrInfo.u = 0;
2124
2125 /*
2126 * Get and parse the ModR/M byte from our decoded opcodes.
2127 */
2128 uint8_t bRm;
2129 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2130 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2131 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2132 {
2133 /*
2134 * ModR/M indicates register addressing.
2135 *
2136 * The primary/secondary register operands are reported in the iReg1 or iReg2
2137 * fields depending on whether it is a read/write form.
2138 */
2139 uint8_t idxReg1;
2140 uint8_t idxReg2;
2141 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2142 {
2143 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2144 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2145 }
2146 else
2147 {
2148 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2149 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2150 }
2151 ExitInstrInfo.All.u2Scaling = 0;
2152 ExitInstrInfo.All.iReg1 = idxReg1;
2153 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2154 ExitInstrInfo.All.fIsRegOperand = 1;
2155 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2156 ExitInstrInfo.All.iSegReg = 0;
2157 ExitInstrInfo.All.iIdxReg = 0;
2158 ExitInstrInfo.All.fIdxRegInvalid = 1;
2159 ExitInstrInfo.All.iBaseReg = 0;
2160 ExitInstrInfo.All.fBaseRegInvalid = 1;
2161 ExitInstrInfo.All.iReg2 = idxReg2;
2162
2163 /* Displacement not applicable for register addressing. */
2164 GCPtrDisp = 0;
2165 }
2166 else
2167 {
2168 /*
2169 * ModR/M indicates memory addressing.
2170 */
2171 uint8_t uScale = 0;
2172 bool fBaseRegValid = false;
2173 bool fIdxRegValid = false;
2174 uint8_t iBaseReg = 0;
2175 uint8_t iIdxReg = 0;
2176 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2177 {
2178 /*
2179 * Parse the ModR/M, displacement for 16-bit addressing mode.
2180 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2181 */
2182 uint16_t u16Disp = 0;
2183 uint8_t const offDisp = offModRm + sizeof(bRm);
2184 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2185 {
2186 /* Displacement without any registers. */
2187 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2188 }
2189 else
2190 {
2191 /* Register (index and base). */
2192 switch (bRm & X86_MODRM_RM_MASK)
2193 {
2194 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2195 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2196 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2197 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2198 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2199 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2200 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2201 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2202 }
2203
2204 /* Register + displacement. */
2205 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2206 {
2207 case 0: break;
2208 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2209 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2210 default:
2211 {
2212 /* Register addressing, handled at the beginning. */
2213 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2214 break;
2215 }
2216 }
2217 }
2218
2219 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2220 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2221 }
2222 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2223 {
2224 /*
2225 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2226 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2227 */
2228 uint32_t u32Disp = 0;
2229 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2230 {
2231 /* Displacement without any registers. */
2232 uint8_t const offDisp = offModRm + sizeof(bRm);
2233 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2234 }
2235 else
2236 {
2237 /* Register (and perhaps scale, index and base). */
2238 uint8_t offDisp = offModRm + sizeof(bRm);
2239 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2240 if (iBaseReg == 4)
2241 {
2242 /* An SIB byte follows the ModR/M byte, parse it. */
2243 uint8_t bSib;
2244 uint8_t const offSib = offModRm + sizeof(bRm);
2245 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2246
2247 /* A displacement may follow SIB, update its offset. */
2248 offDisp += sizeof(bSib);
2249
2250 /* Get the scale. */
2251 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2252
2253 /* Get the index register. */
2254 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2255 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2256
2257 /* Get the base register. */
2258 iBaseReg = bSib & X86_SIB_BASE_MASK;
2259 fBaseRegValid = true;
2260 if (iBaseReg == 5)
2261 {
2262 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2263 {
2264 /* Mod is 0 implies a 32-bit displacement with no base. */
2265 fBaseRegValid = false;
2266 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2267 }
2268 else
2269 {
2270 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2271 iBaseReg = X86_GREG_xBP;
2272 }
2273 }
2274 }
2275
2276 /* Register + displacement. */
2277 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2278 {
2279 case 0: /* Handled above */ break;
2280 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2281 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2282 default:
2283 {
2284 /* Register addressing, handled at the beginning. */
2285 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2286 break;
2287 }
2288 }
2289 }
2290
2291 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2292 }
2293 else
2294 {
2295 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2296
2297 /*
2298 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2299 * See Intel instruction spec. 2.2 "IA-32e Mode".
2300 */
2301 uint64_t u64Disp = 0;
2302 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2303 if (fRipRelativeAddr)
2304 {
2305 /*
2306 * RIP-relative addressing mode.
2307 *
2308 * The displacement is 32-bit signed implying an offset range of +/-2G.
2309 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2310 */
2311 uint8_t const offDisp = offModRm + sizeof(bRm);
2312 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2313 }
2314 else
2315 {
2316 uint8_t offDisp = offModRm + sizeof(bRm);
2317
2318 /*
2319 * Register (and perhaps scale, index and base).
2320 *
2321 * REX.B extends the most-significant bit of the base register. However, REX.B
2322 * is ignored while determining whether an SIB follows the opcode. Hence, we
2323 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2324 *
2325 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2326 */
2327 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2328 if (iBaseReg == 4)
2329 {
2330 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2331 uint8_t bSib;
2332 uint8_t const offSib = offModRm + sizeof(bRm);
2333 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2334
2335 /* Displacement may follow SIB, update its offset. */
2336 offDisp += sizeof(bSib);
2337
2338 /* Get the scale. */
2339 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2340
2341 /* Get the index. */
2342 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2343 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2344
2345 /* Get the base. */
2346 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2347 fBaseRegValid = true;
2348 if (iBaseReg == 5)
2349 {
2350 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2351 {
2352 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2353 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2354 }
2355 else
2356 {
2357 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2358 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2359 }
2360 }
2361 }
2362 iBaseReg |= pVCpu->iem.s.uRexB;
2363
2364 /* Register + displacement. */
2365 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2366 {
2367 case 0: /* Handled above */ break;
2368 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2369 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2370 default:
2371 {
2372 /* Register addressing, handled at the beginning. */
2373 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2374 break;
2375 }
2376 }
2377 }
2378
2379 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2380 }
2381
2382 /*
2383 * The primary or secondary register operand is reported in iReg2 depending
2384 * on whether the primary operand is in read/write form.
2385 */
2386 uint8_t idxReg2;
2387 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2388 {
2389 idxReg2 = bRm & X86_MODRM_RM_MASK;
2390 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2391 idxReg2 |= pVCpu->iem.s.uRexB;
2392 }
2393 else
2394 {
2395 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2396 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2397 idxReg2 |= pVCpu->iem.s.uRexReg;
2398 }
2399 ExitInstrInfo.All.u2Scaling = uScale;
2400 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2401 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2402 ExitInstrInfo.All.fIsRegOperand = 0;
2403 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2404 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2405 ExitInstrInfo.All.iIdxReg = iIdxReg;
2406 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2407 ExitInstrInfo.All.iBaseReg = iBaseReg;
2408 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2409 ExitInstrInfo.All.iReg2 = idxReg2;
2410 }
2411
2412 /*
2413 * Handle exceptions to the norm for certain instructions.
2414 * (e.g. some instructions convey an instruction identity in place of iReg2).
2415 */
2416 switch (uExitReason)
2417 {
2418 case VMX_EXIT_GDTR_IDTR_ACCESS:
2419 {
2420 Assert(VMXINSTRID_IS_VALID(uInstrId));
2421 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2422 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2423 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2424 break;
2425 }
2426
2427 case VMX_EXIT_LDTR_TR_ACCESS:
2428 {
2429 Assert(VMXINSTRID_IS_VALID(uInstrId));
2430 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2431 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2432 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2433 break;
2434 }
2435
2436 case VMX_EXIT_RDRAND:
2437 case VMX_EXIT_RDSEED:
2438 {
2439 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2440 break;
2441 }
2442 }
2443
2444 /* Update displacement and return the constructed VM-exit instruction information field. */
2445 if (pGCPtrDisp)
2446 *pGCPtrDisp = GCPtrDisp;
2447
2448 return ExitInstrInfo.u;
2449}
2450
2451
2452/**
2453 * VMX VM-exit handler.
2454 *
2455 * @returns Strict VBox status code.
2456 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2457 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2458 * triple-fault.
2459 *
2460 * @param pVCpu The cross context virtual CPU structure.
2461 * @param uExitReason The VM-exit reason.
2462 * @param u64ExitQual The Exit qualification.
2463 *
2464 * @remarks We need not necessarily have completed VM-entry before a VM-exit is
2465 * called. Failures during VM-entry can cause VM-exits as well, so we
2466 * -cannot- assert we're in VMX non-root mode here.
2467 */
2468VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT
2469{
2470# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2471 RT_NOREF3(pVCpu, uExitReason, u64ExitQual);
2472 AssertMsgFailed(("VM-exit should only be invoked from ring-3 when nested-guest executes only in ring-3!\n"));
2473 return VERR_IEM_IPE_7;
2474# else
2475 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
2476
2477 /* Just count this as an exit and be done with that. */
2478 pVCpu->iem.s.cPotentialExits++;
2479
2480 /*
2481 * Import all the guest-CPU state.
2482 *
2483 * HM on returning to guest execution would have to reset up a whole lot of state
2484 * anyway, (e.g., VM-entry/VM-exit controls) and we do not ever import a part of
2485 * the state and flag reloading the entire state on re-entry. So import the entire
2486 * state here, see HMNotifyVmxNstGstVmexit() for more comments.
2487 */
2488 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL);
2489
2490 /*
2491 * Ensure VM-entry interruption information valid bit is cleared.
2492 *
2493 * We do it here on every VM-exit so that even premature VM-exits (e.g. those caused
2494 * by invalid-guest state or machine-check exceptions) also clear this bit.
2495 *
2496 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry control fields".
2497 */
2498 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
2499 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2500
2501 /*
2502 * Update the VM-exit reason and Exit qualification.
2503 * Other VMCS read-only data fields are expected to be updated by the caller already.
2504 */
2505 pVmcs->u32RoExitReason = uExitReason;
2506 pVmcs->u64RoExitQual.u = u64ExitQual;
2507
2508 Log2(("vmexit: reason=%u qual=%#RX64 cs:rip=%04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 eflags=%#RX32\n", uExitReason,
2509 pVmcs->u64RoExitQual.u, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
2510 pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.eflags.u));
2511
2512 /*
2513 * Update the IDT-vectoring information fields if the VM-exit is triggered during delivery of an event.
2514 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2515 */
2516 {
2517 uint8_t uVector;
2518 uint32_t fFlags;
2519 uint32_t uErrCode;
2520 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* puCr2 */);
2521 if (fInEventDelivery)
2522 {
2523 /*
2524 * A VM-exit is not considered to occur during event delivery when the VM-exit is
2525 * caused by a triple-fault or the original event results in a double-fault that
2526 * causes the VM exit directly (exception bitmap). Therefore, we must not set the
2527 * original event information into the IDT-vectoring information fields.
2528 *
2529 * See Intel spec. 27.2.4 "Information for VM Exits During Event Delivery".
2530 */
2531 if ( uExitReason != VMX_EXIT_TRIPLE_FAULT
2532 && ( uExitReason != VMX_EXIT_XCPT_OR_NMI
2533 || !VMX_EXIT_INT_INFO_IS_XCPT_DF(pVmcs->u32RoExitIntInfo)))
2534 {
2535 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
2536 uint8_t const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
2537 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
2538 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
2539 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
2540 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
2541 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
2542 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
2543 Log2(("vmexit: idt_info=%#RX32 idt_err_code=%#RX32 cr2=%#RX64\n", uIdtVectoringInfo, uErrCode,
2544 pVCpu->cpum.GstCtx.cr2));
2545 }
2546 }
2547 }
2548
2549 /* The following VMCS fields should always be zero since we don't support injecting SMIs into a guest. */
2550 Assert(pVmcs->u64RoIoRcx.u == 0);
2551 Assert(pVmcs->u64RoIoRsi.u == 0);
2552 Assert(pVmcs->u64RoIoRdi.u == 0);
2553 Assert(pVmcs->u64RoIoRip.u == 0);
2554
2555 /*
2556 * Save the guest state back into the VMCS.
2557 * We only need to save the state when the VM-entry was successful.
2558 */
2559 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2560 if (!fVmentryFailed)
2561 {
2562 /* We should not cause an NMI-window/interrupt-window VM-exit when injecting events as part of VM-entry. */
2563 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
2564 {
2565 Assert(uExitReason != VMX_EXIT_NMI_WINDOW);
2566 Assert(uExitReason != VMX_EXIT_INT_WINDOW);
2567 }
2568
2569 /* For exception or NMI VM-exits the VM-exit interruption info. field must be valid. */
2570 Assert(uExitReason != VMX_EXIT_XCPT_OR_NMI || VMX_EXIT_INT_INFO_IS_VALID(pVmcs->u32RoExitIntInfo));
2571
2572 /*
2573 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2574 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2575 *
2576 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2577 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2578 * as guest-CPU state would not been modified. Hence for now, we do this only when
2579 * the VM-entry succeeded.
2580 */
2581 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2582 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2583 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2584 {
2585 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2586 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2587 else
2588 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2589 }
2590
2591 /*
2592 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2593 * occurs in enclave mode/SMM which we don't support yet.
2594 *
2595 * If we ever add support for it, we can pass just the lower bits to the functions
2596 * below, till then an assert should suffice.
2597 */
2598 Assert(!RT_HI_U16(uExitReason));
2599
2600 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2601 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2602 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2603 if (RT_SUCCESS(rc))
2604 { /* likely */ }
2605 else
2606 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2607
2608 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2609 pVCpu->cpum.GstCtx.hwvirt.fSavedInhibit &= ~CPUMCTX_INHIBIT_NMI;
2610 }
2611 else
2612 {
2613 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2614 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2615 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2616 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2617 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2618 }
2619
2620 /*
2621 * Stop any running VMX-preemption timer if necessary.
2622 */
2623 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
2624 CPUMStopGuestVmxPremptTimer(pVCpu);
2625
2626 /*
2627 * Clear any pending VMX nested-guest force-flags.
2628 * These force-flags have no effect on (outer) guest execution and will
2629 * be re-evaluated and setup on the next nested-guest VM-entry.
2630 */
2631 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
2632
2633 /*
2634 * We're no longer in nested-guest execution mode.
2635 *
2636 * It is important to do this prior to loading the host state because
2637 * PGM looks at fInVmxNonRootMode to determine if it needs to perform
2638 * second-level address translation while switching to host CR3.
2639 */
2640 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2641
2642 /* Restore the host (outer guest) state. */
2643 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2644 if (RT_SUCCESS(rcStrict))
2645 {
2646 Assert(rcStrict == VINF_SUCCESS);
2647 rcStrict = VINF_VMX_VMEXIT;
2648 }
2649 else
2650 Log(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2651
2652 /*
2653 * Restore non-zero Secondary-processor based VM-execution controls
2654 * when the "activate secondary controls" bit was not set.
2655 */
2656 if (pVmcs->u32RestoreProcCtls2)
2657 {
2658 Assert(!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS));
2659 pVmcs->u32ProcCtls2 = pVmcs->u32RestoreProcCtls2;
2660 pVmcs->u32RestoreProcCtls2 = 0;
2661 }
2662
2663 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
2664 {
2665 /* Notify HM that the current VMCS fields have been modified. */
2666 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
2667
2668 /* Notify HM that we've completed the VM-exit. */
2669 HMNotifyVmxNstGstVmexit(pVCpu);
2670 }
2671
2672# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
2673 /* Revert any IEM-only nested-guest execution policy, otherwise return rcStrict. */
2674 Log(("vmexit: Disabling IEM-only EM execution policy!\n"));
2675 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
2676 if (rcSched != VINF_SUCCESS)
2677 iemSetPassUpStatus(pVCpu, rcSched);
2678# endif
2679 return rcStrict;
2680# endif
2681}
2682
2683
2684/**
2685 * VMX VM-exit handler for VM-exits due to instruction execution.
2686 *
2687 * This is intended for instructions where the caller provides all the relevant
2688 * VM-exit information.
2689 *
2690 * @returns Strict VBox status code.
2691 * @param pVCpu The cross context virtual CPU structure.
2692 * @param pExitInfo Pointer to the VM-exit information.
2693 */
2694static VBOXSTRICTRC iemVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
2695{
2696 /*
2697 * For instructions where any of the following fields are not applicable:
2698 * - Exit qualification must be cleared.
2699 * - VM-exit instruction info. is undefined.
2700 * - Guest-linear address is undefined.
2701 * - Guest-physical address is undefined.
2702 *
2703 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2704 * instruction execution. For VM-exits that are not due to instruction execution this
2705 * field is undefined.
2706 *
2707 * In our implementation in IEM, all undefined fields are generally cleared. However,
2708 * if the caller supplies information (from say the physical CPU directly) it is
2709 * then possible that the undefined fields are not cleared.
2710 *
2711 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2712 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2713 */
2714 Assert(pExitInfo);
2715 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2716 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2717 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2718
2719 /* Update all the relevant fields from the VM-exit instruction information struct. */
2720 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2721 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2722 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2723 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2724
2725 /* Perform the VM-exit. */
2726 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
2727}
2728
2729
2730/**
2731 * VMX VM-exit handler for VM-exits due to instruction execution.
2732 *
2733 * This is intended for instructions that only provide the VM-exit instruction
2734 * length.
2735 *
2736 * @param pVCpu The cross context virtual CPU structure.
2737 * @param uExitReason The VM-exit reason.
2738 * @param cbInstr The instruction length in bytes.
2739 */
2740VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT
2741{
2742#ifdef VBOX_STRICT
2743 /*
2744 * To prevent us from shooting ourselves in the foot.
2745 * The follow instructions should convey more than just the instruction length.
2746 */
2747 switch (uExitReason)
2748 {
2749 case VMX_EXIT_INVEPT:
2750 case VMX_EXIT_INVPCID:
2751 case VMX_EXIT_INVVPID:
2752 case VMX_EXIT_LDTR_TR_ACCESS:
2753 case VMX_EXIT_GDTR_IDTR_ACCESS:
2754 case VMX_EXIT_VMCLEAR:
2755 case VMX_EXIT_VMPTRLD:
2756 case VMX_EXIT_VMPTRST:
2757 case VMX_EXIT_VMREAD:
2758 case VMX_EXIT_VMWRITE:
2759 case VMX_EXIT_VMXON:
2760 case VMX_EXIT_XRSTORS:
2761 case VMX_EXIT_XSAVES:
2762 case VMX_EXIT_RDRAND:
2763 case VMX_EXIT_RDSEED:
2764 case VMX_EXIT_IO_INSTR:
2765 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2766 break;
2767 }
2768#endif
2769
2770 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_INSTR_LEN(uExitReason, cbInstr);
2771 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2772}
2773
2774
2775/**
2776 * Interface for HM and EM to emulate VM-exit due to a triple-fault.
2777 *
2778 * @returns Strict VBox status code.
2779 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2780 * @thread EMT(pVCpu)
2781 */
2782VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu)
2783{
2784 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT, 0 /* u64ExitQual */);
2785 Assert(!pVCpu->iem.s.cActiveMappings);
2786 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2787}
2788
2789
2790/**
2791 * Interface for HM and EM to emulate VM-exit due to startup-IPI (SIPI).
2792 *
2793 * @returns Strict VBox status code.
2794 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2795 * @param uVector The SIPI vector.
2796 * @thread EMT(pVCpu)
2797 */
2798VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector)
2799{
2800 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, VMX_EXIT_SIPI, uVector);
2801 Assert(!pVCpu->iem.s.cActiveMappings);
2802 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2803}
2804
2805
2806/**
2807 * Interface for HM and EM to emulate a VM-exit.
2808 *
2809 * If a specialized version of a VM-exit handler exists, that must be used instead.
2810 *
2811 * @returns Strict VBox status code.
2812 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2813 * @param uExitReason The VM-exit reason.
2814 * @param u64ExitQual The Exit qualification.
2815 * @thread EMT(pVCpu)
2816 */
2817VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual)
2818{
2819 VBOXSTRICTRC rcStrict = iemVmxVmexit(pVCpu, uExitReason, u64ExitQual);
2820 Assert(!pVCpu->iem.s.cActiveMappings);
2821 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2822}
2823
2824
2825/**
2826 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2827 *
2828 * This is meant to be used for those instructions that VMX provides additional
2829 * decoding information beyond just the instruction length!
2830 *
2831 * @returns Strict VBox status code.
2832 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2833 * @param pExitInfo Pointer to the VM-exit information.
2834 * @thread EMT(pVCpu)
2835 */
2836VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
2837{
2838 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
2839 Assert(!pVCpu->iem.s.cActiveMappings);
2840 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2841}
2842
2843
2844/**
2845 * Interface for HM and EM to emulate a VM-exit due to an instruction.
2846 *
2847 * This is meant to be used for those instructions that VMX provides only the
2848 * instruction length.
2849 *
2850 * @returns Strict VBox status code.
2851 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2852 * @param pExitInfo Pointer to the VM-exit information.
2853 * @param cbInstr The instruction length in bytes.
2854 * @thread EMT(pVCpu)
2855 */
2856VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2857{
2858 VBOXSTRICTRC rcStrict = iemVmxVmexitInstr(pVCpu, uExitReason, cbInstr);
2859 Assert(!pVCpu->iem.s.cActiveMappings);
2860 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
2861}
2862
2863
2864/**
2865 * VMX VM-exit handler for VM-exits due to instruction execution.
2866 *
2867 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2868 * instruction information and Exit qualification fields.
2869 *
2870 * @param pVCpu The cross context virtual CPU structure.
2871 * @param uExitReason The VM-exit reason.
2872 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2873 * @param cbInstr The instruction length in bytes.
2874 *
2875 * @remarks Do not use this for INS/OUTS instruction.
2876 */
2877VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT
2878{
2879#ifdef VBOX_STRICT
2880 /*
2881 * To prevent us from shooting ourselves in the foot.
2882 * The follow instructions convey specific info that require using their respective handlers.
2883 */
2884 switch (uExitReason)
2885 {
2886 case VMX_EXIT_INVEPT:
2887 case VMX_EXIT_INVPCID:
2888 case VMX_EXIT_INVVPID:
2889 case VMX_EXIT_LDTR_TR_ACCESS:
2890 case VMX_EXIT_GDTR_IDTR_ACCESS:
2891 case VMX_EXIT_VMCLEAR:
2892 case VMX_EXIT_VMPTRLD:
2893 case VMX_EXIT_VMPTRST:
2894 case VMX_EXIT_VMREAD:
2895 case VMX_EXIT_VMWRITE:
2896 case VMX_EXIT_VMXON:
2897 case VMX_EXIT_XRSTORS:
2898 case VMX_EXIT_XSAVES:
2899 case VMX_EXIT_RDRAND:
2900 case VMX_EXIT_RDSEED:
2901 break;
2902 default:
2903 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
2904 break;
2905 }
2906#endif
2907
2908 /*
2909 * Update the Exit qualification field with displacement bytes.
2910 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2911 */
2912 /* Construct the VM-exit instruction information. */
2913 RTGCPTR GCPtrDisp;
2914 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
2915
2916 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO(uExitReason, GCPtrDisp, uInstrInfo, cbInstr);
2917 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2918}
2919
2920
2921/**
2922 * VMX VM-exit handler for VM-exits due to INVLPG.
2923 *
2924 * @returns Strict VBox status code.
2925 * @param pVCpu The cross context virtual CPU structure.
2926 * @param GCPtrPage The guest-linear address of the page being invalidated.
2927 * @param cbInstr The instruction length in bytes.
2928 */
2929VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT
2930{
2931 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_INVLPG, GCPtrPage, cbInstr);
2932 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
2933 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2934}
2935
2936
2937/**
2938 * VMX VM-exit handler for VM-exits due to LMSW.
2939 *
2940 * @returns Strict VBox status code.
2941 * @param pVCpu The cross context virtual CPU structure.
2942 * @param uGuestCr0 The current guest CR0.
2943 * @param pu16NewMsw The machine-status word specified in LMSW's source
2944 * operand. This will be updated depending on the VMX
2945 * guest/host CR0 mask if LMSW is not intercepted.
2946 * @param GCPtrEffDst The guest-linear address of the source operand in case
2947 * of a memory operand. For register operand, pass
2948 * NIL_RTGCPTR.
2949 * @param cbInstr The instruction length in bytes.
2950 */
2951VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
2952 RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT
2953{
2954 Assert(pu16NewMsw);
2955
2956 uint16_t const uNewMsw = *pu16NewMsw;
2957 if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
2958 {
2959 Log2(("lmsw: Guest intercept -> VM-exit\n"));
2960 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
2961 VMXVEXITINFO ExitInfo
2962 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
2963 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
2964 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
2965 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, uNewMsw)
2966 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW),
2967 cbInstr);
2968 if (fMemOperand)
2969 {
2970 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
2971 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
2972 }
2973 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2974 }
2975
2976 /*
2977 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
2978 * CR0 guest/host mask must be left unmodified.
2979 *
2980 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2981 */
2982 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2983 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2984 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (uNewMsw & ~fGstHostLmswMask);
2985
2986 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
2987}
2988
2989
2990/**
2991 * VMX VM-exit handler for VM-exits due to CLTS.
2992 *
2993 * @returns Strict VBox status code.
2994 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
2995 * VM-exit but must not modify the guest CR0.TS bit.
2996 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
2997 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
2998 * CR0 fixed bits in VMX operation).
2999 * @param pVCpu The cross context virtual CPU structure.
3000 * @param cbInstr The instruction length in bytes.
3001 */
3002VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3003{
3004 /*
3005 * If CR0.TS is owned by the host:
3006 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3007 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3008 * CLTS instruction completes without clearing CR0.TS.
3009 *
3010 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3011 */
3012 uint32_t const fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3013 if (fGstHostMask & X86_CR0_TS)
3014 {
3015 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u & X86_CR0_TS)
3016 {
3017 Log2(("clts: Guest intercept -> VM-exit\n"));
3018 VMXVEXITINFO const ExitInfo
3019 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3020 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3021 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
3022 VMX_EXIT_QUAL_CRX_ACCESS_CLTS),
3023 cbInstr);
3024 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3025 }
3026 return VINF_VMX_MODIFIES_BEHAVIOR;
3027 }
3028
3029 /*
3030 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3031 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3032 */
3033 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3034}
3035
3036
3037/**
3038 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3039 * (CR0/CR4 write).
3040 *
3041 * @returns Strict VBox status code.
3042 * @param pVCpu The cross context virtual CPU structure.
3043 * @param iCrReg The control register (either CR0 or CR4).
3044 * @param uGuestCrX The current guest CR0/CR4.
3045 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated if no
3046 * VM-exit is caused.
3047 * @param iGReg The general register from which the CR0/CR4 value is being
3048 * loaded.
3049 * @param cbInstr The instruction length in bytes.
3050 */
3051VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX,
3052 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3053{
3054 Assert(puNewCrX);
3055 Assert(iCrReg == 0 || iCrReg == 4);
3056 Assert(iGReg < X86_GREG_COUNT);
3057
3058 uint64_t const uNewCrX = *puNewCrX;
3059 if (CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX))
3060 {
3061 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3062 VMXVEXITINFO const ExitInfo
3063 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3064 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3065 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3066 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3067 cbInstr);
3068 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3069 }
3070
3071 /*
3072 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3073 * must not be modified the instruction.
3074 *
3075 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3076 */
3077 uint64_t uGuestCrX;
3078 uint64_t fGstHostMask;
3079 if (iCrReg == 0)
3080 {
3081 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3082 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3083 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u;
3084 }
3085 else
3086 {
3087 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3088 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3089 fGstHostMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u;
3090 }
3091
3092 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3093 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3094}
3095
3096
3097/**
3098 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3099 *
3100 * @returns VBox strict status code.
3101 * @param pVCpu The cross context virtual CPU structure.
3102 * @param iGReg The general register to which the CR3 value is being stored.
3103 * @param cbInstr The instruction length in bytes.
3104 */
3105VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3106{
3107 Assert(iGReg < X86_GREG_COUNT);
3108 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3109
3110 /*
3111 * If the CR3-store exiting control is set, we must cause a VM-exit.
3112 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3113 */
3114 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3115 {
3116 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3117 VMXVEXITINFO const ExitInfo
3118 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3119 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3120 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3121 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3122 cbInstr);
3123 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3124 }
3125 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3126}
3127
3128
3129/**
3130 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3131 *
3132 * @returns VBox strict status code.
3133 * @param pVCpu The cross context virtual CPU structure.
3134 * @param uNewCr3 The new CR3 value.
3135 * @param iGReg The general register from which the CR3 value is being
3136 * loaded.
3137 * @param cbInstr The instruction length in bytes.
3138 */
3139VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3140{
3141 Assert(iGReg < X86_GREG_COUNT);
3142
3143 /*
3144 * If the CR3-load exiting control is set and the new CR3 value does not
3145 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3146 *
3147 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3148 */
3149 if (CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCr3))
3150 {
3151 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3152 VMXVEXITINFO const ExitInfo
3153 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3154 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3155 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3156 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS,
3157 VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3158 cbInstr);
3159 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3160 }
3161 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3162}
3163
3164
3165/**
3166 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3167 *
3168 * @returns VBox strict status code.
3169 * @param pVCpu The cross context virtual CPU structure.
3170 * @param iGReg The general register to which the CR8 value is being stored.
3171 * @param cbInstr The instruction length in bytes.
3172 */
3173VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3174{
3175 Assert(iGReg < X86_GREG_COUNT);
3176
3177 /*
3178 * If the CR8-store exiting control is set, we must cause a VM-exit.
3179 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3180 */
3181 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3182 {
3183 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3184 VMXVEXITINFO const ExitInfo
3185 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3186 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3187 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3188 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ),
3189 cbInstr);
3190 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3191 }
3192 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3193}
3194
3195
3196/**
3197 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3198 *
3199 * @returns VBox strict status code.
3200 * @param pVCpu The cross context virtual CPU structure.
3201 * @param iGReg The general register from which the CR8 value is being
3202 * loaded.
3203 * @param cbInstr The instruction length in bytes.
3204 */
3205VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3206{
3207 Assert(iGReg < X86_GREG_COUNT);
3208
3209 /*
3210 * If the CR8-load exiting control is set, we must cause a VM-exit.
3211 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3212 */
3213 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3214 {
3215 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3216 VMXVEXITINFO const ExitInfo
3217 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_CRX,
3218 RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3219 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg)
3220 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE),
3221 cbInstr);
3222 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3223 }
3224 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3225}
3226
3227
3228/**
3229 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3230 * GReg,DRx' (DRx read).
3231 *
3232 * @returns VBox strict status code.
3233 * @param pVCpu The cross context virtual CPU structure.
3234 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3235 * VMXINSTRID_MOV_FROM_DRX).
3236 * @param iDrReg The debug register being accessed.
3237 * @param iGReg The general register to/from which the DRx value is being
3238 * store/loaded.
3239 * @param cbInstr The instruction length in bytes.
3240 */
3241VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg,
3242 uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT
3243{
3244 Assert(iDrReg <= 7);
3245 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3246 Assert(iGReg < X86_GREG_COUNT);
3247
3248 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3249 {
3250 VMXVEXITINFO const ExitInfo
3251 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MOV_DRX,
3252 RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3253 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg)
3254 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION,
3255 uInstrId == VMXINSTRID_MOV_TO_DRX
3256 ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3257 : VMX_EXIT_QUAL_DRX_DIRECTION_READ),
3258 cbInstr);
3259 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3260 }
3261
3262 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3263}
3264
3265
3266/**
3267 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3268 *
3269 * @returns VBox strict status code.
3270 * @param pVCpu The cross context virtual CPU structure.
3271 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3272 * VMXINSTRID_IO_OUT).
3273 * @param u16Port The I/O port being accessed.
3274 * @param fImm Whether the I/O port was encoded using an immediate operand
3275 * or the implicit DX register.
3276 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3277 * @param cbInstr The instruction length in bytes.
3278 */
3279VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3280 bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT
3281{
3282 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3283 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3284
3285 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3286 {
3287 VMXVEXITINFO const ExitInfo
3288 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_IO_INSTR,
3289 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3290 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3291 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port)
3292 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION,
3293 uInstrId == VMXINSTRID_IO_IN
3294 ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3295 : VMX_EXIT_QUAL_IO_DIRECTION_OUT),
3296 cbInstr);
3297 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3298 }
3299 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3300}
3301
3302
3303/**
3304 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3305 *
3306 * @returns VBox strict status code.
3307 * @param pVCpu The cross context virtual CPU structure.
3308 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3309 * VMXINSTRID_IO_OUTS).
3310 * @param u16Port The I/O port being accessed.
3311 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3312 * @param fRep Whether the instruction has a REP prefix or not.
3313 * @param ExitInstrInfo The VM-exit instruction info. field.
3314 * @param cbInstr The instruction length in bytes.
3315 */
3316VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3317 bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT
3318{
3319 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3320 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3321 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3322 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3323 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3324
3325 if (CPUMIsGuestVmxIoInterceptSet(pVCpu, u16Port, cbAccess))
3326 {
3327 /*
3328 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3329 */
3330 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3331 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3332 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3333 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3334 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3335
3336 uint32_t uDirection;
3337 uint64_t uGuestLinearAddr;
3338 if (uInstrId == VMXINSTRID_IO_INS)
3339 {
3340 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3341 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3342 }
3343 else
3344 {
3345 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3346 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3347 }
3348
3349 /*
3350 * If the segment is unusable, the guest-linear address in undefined.
3351 * We shall clear it for consistency.
3352 *
3353 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3354 */
3355 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3356 uGuestLinearAddr = 0;
3357
3358 VMXVEXITINFO const ExitInfo
3359 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO_AND_LIN_ADDR(VMX_EXIT_IO_INSTR,
3360 RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3361 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3362 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3363 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3364 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING,
3365 VMX_EXIT_QUAL_IO_ENCODING_DX)
3366 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port),
3367 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxInsOutInfo
3368 ? ExitInstrInfo.u : 0,
3369 cbInstr,
3370 uGuestLinearAddr);
3371 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3372 }
3373
3374 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3375}
3376
3377
3378/**
3379 * VMX VM-exit handler for VM-exits due to MWAIT.
3380 *
3381 * @returns VBox strict status code.
3382 * @param pVCpu The cross context virtual CPU structure.
3383 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3384 * @param cbInstr The instruction length in bytes.
3385 */
3386VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT
3387{
3388 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_MWAIT, fMonitorHwArmed, cbInstr);
3389 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3390}
3391
3392
3393/**
3394 * VMX VM-exit handler for VM-exits due to PAUSE.
3395 *
3396 * @returns VBox strict status code.
3397 * @param pVCpu The cross context virtual CPU structure.
3398 * @param cbInstr The instruction length in bytes.
3399 */
3400static VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
3401{
3402 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
3403
3404 /*
3405 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3406 * "PAUSE-loop exiting" control.
3407 *
3408 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3409 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3410 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3411 * a VM-exit.
3412 *
3413 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3414 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3415 */
3416 bool fIntercept = false;
3417 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3418 fIntercept = true;
3419 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3420 && pVCpu->iem.s.uCpl == 0)
3421 {
3422 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3423
3424 /*
3425 * A previous-PAUSE-tick value of 0 is used to identify the first time
3426 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3427 * consider this to be the first execution of PAUSE in a loop according
3428 * to the Intel.
3429 *
3430 * All subsequent records for the previous-PAUSE-tick we ensure that it
3431 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3432 */
3433 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3434 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3435 uint64_t const uTick = TMCpuTickGet(pVCpu);
3436 uint32_t const uPleGap = pVmcs->u32PleGap;
3437 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3438 if ( *puPrevPauseTick == 0
3439 || uTick - *puPrevPauseTick > uPleGap)
3440 *puFirstPauseLoopTick = uTick;
3441 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3442 fIntercept = true;
3443
3444 *puPrevPauseTick = uTick | 1;
3445 }
3446
3447 if (fIntercept)
3448 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_PAUSE, cbInstr);
3449
3450 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3451}
3452
3453
3454/**
3455 * VMX VM-exit handler for VM-exits due to task switches.
3456 *
3457 * @returns VBox strict status code.
3458 * @param pVCpu The cross context virtual CPU structure.
3459 * @param enmTaskSwitch The cause of the task switch.
3460 * @param SelNewTss The selector of the new TSS.
3461 * @param cbInstr The instruction length in bytes.
3462 */
3463VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT
3464{
3465 /*
3466 * Task-switch VM-exits are unconditional and provide the Exit qualification.
3467 *
3468 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3469 * instruction or delivery of the exception generated by one of these instructions
3470 * lead to a task switch through a task gate in the IDT, we need to provide the
3471 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3472 * leaves the VM-exit instruction length field undefined.
3473 *
3474 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3475 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3476 */
3477 Assert(cbInstr <= 15);
3478
3479 uint8_t uType;
3480 switch (enmTaskSwitch)
3481 {
3482 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3483 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3484 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3485 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3486 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3487 }
3488
3489 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3490 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3491 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3492 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, u64ExitQual);
3493}
3494
3495
3496/**
3497 * VMX VM-exit handler for trap-like VM-exits.
3498 *
3499 * @returns VBox strict status code.
3500 * @param pVCpu The cross context virtual CPU structure.
3501 * @param pExitInfo Pointer to the VM-exit information.
3502 * @param pExitEventInfo Pointer to the VM-exit event information.
3503 */
3504static VBOXSTRICTRC iemVmxVmexitTrapLikeWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
3505{
3506 Assert(VMXIsVmexitTrapLike(pExitInfo->uReason));
3507 iemVmxVmcsSetGuestPendingDbgXcpts(pVCpu, pExitInfo->u64GuestPendingDbgXcpts);
3508 return iemVmxVmexit(pVCpu, pExitInfo->uReason, pExitInfo->u64Qual);
3509}
3510
3511
3512/**
3513 * Interface for HM and EM to emulate a trap-like VM-exit (MTF, APIC-write,
3514 * Virtualized-EOI, TPR-below threshold).
3515 *
3516 * @returns Strict VBox status code.
3517 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3518 * @param pExitInfo Pointer to the VM-exit information.
3519 * @thread EMT(pVCpu)
3520 */
3521VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
3522{
3523 Assert(pExitInfo);
3524 VBOXSTRICTRC rcStrict = iemVmxVmexitTrapLikeWithInfo(pVCpu, pExitInfo);
3525 Assert(!pVCpu->iem.s.cActiveMappings);
3526 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3527}
3528
3529
3530/**
3531 * VMX VM-exit handler for VM-exits due to task switches.
3532 *
3533 * This is intended for task switches where the caller provides all the relevant
3534 * VM-exit information.
3535 *
3536 * @returns VBox strict status code.
3537 * @param pVCpu The cross context virtual CPU structure.
3538 * @param pExitInfo Pointer to the VM-exit information.
3539 * @param pExitEventInfo Pointer to the VM-exit event information.
3540 */
3541static VBOXSTRICTRC iemVmxVmexitTaskSwitchWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
3542 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3543{
3544 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3545 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3546 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3547 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3548 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH, pExitInfo->u64Qual);
3549}
3550
3551
3552/**
3553 * Interface for HM and EM to emulate a VM-exit due to a task switch.
3554 *
3555 * @returns Strict VBox status code.
3556 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3557 * @param pExitInfo Pointer to the VM-exit information.
3558 * @param pExitEventInfo Pointer to the VM-exit event information.
3559 * @thread EMT(pVCpu)
3560 */
3561VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3562{
3563 Assert(pExitInfo);
3564 Assert(pExitEventInfo);
3565 Assert(pExitInfo->uReason == VMX_EXIT_TASK_SWITCH);
3566 VBOXSTRICTRC rcStrict = iemVmxVmexitTaskSwitchWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3567 Assert(!pVCpu->iem.s.cActiveMappings);
3568 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3569}
3570
3571
3572/**
3573 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3574 *
3575 * @returns VBox strict status code.
3576 * @param pVCpu The cross context virtual CPU structure.
3577 */
3578VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT
3579{
3580 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
3581 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
3582
3583 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3584 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3585
3586 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3587 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3588 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PreemptTimer = 0;
3589
3590 /* Cause the VMX-preemption timer VM-exit. The Exit qualification MBZ. */
3591 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER, 0 /* u64ExitQual */);
3592}
3593
3594
3595/**
3596 * Interface for HM and EM to emulate VM-exit due to expiry of the preemption timer.
3597 *
3598 * @returns Strict VBox status code.
3599 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3600 * @thread EMT(pVCpu)
3601 */
3602VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu)
3603{
3604 VBOXSTRICTRC rcStrict = iemVmxVmexitPreemptTimer(pVCpu);
3605 Assert(!pVCpu->iem.s.cActiveMappings);
3606 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3607}
3608
3609
3610/**
3611 * VMX VM-exit handler for VM-exits due to external interrupts.
3612 *
3613 * @returns VBox strict status code.
3614 * @param pVCpu The cross context virtual CPU structure.
3615 * @param uVector The external interrupt vector (pass 0 if the interrupt
3616 * is still pending since we typically won't know the
3617 * vector).
3618 * @param fIntPending Whether the external interrupt is pending or
3619 * acknowledged in the interrupt controller.
3620 */
3621static VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending) RT_NOEXCEPT
3622{
3623 Assert(!fIntPending || uVector == 0);
3624
3625 /* The VM-exit is subject to "External interrupt exiting" being set. */
3626 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3627 {
3628 if (fIntPending)
3629 {
3630 /*
3631 * If the interrupt is pending and we don't need to acknowledge the
3632 * interrupt on VM-exit, cause the VM-exit immediately.
3633 *
3634 * See Intel spec 25.2 "Other Causes Of VM Exits".
3635 */
3636 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3637 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3638
3639 /*
3640 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3641 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3642 * acknowledged that the interrupt has been consumed. Callers would have to call
3643 * us again after getting the vector (and ofc, with fIntPending with false).
3644 */
3645 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3646 }
3647
3648 /*
3649 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3650 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3651 * all set, we need to record the vector of the external interrupt in the
3652 * VM-exit interruption information field. Otherwise, mark this field as invalid.
3653 *
3654 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3655 */
3656 uint32_t uExitIntInfo;
3657 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3658 {
3659 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3660 uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3661 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3662 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3663 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3664 }
3665 else
3666 uExitIntInfo = 0;
3667 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3668
3669 /*
3670 * Cause the VM-exit whether or not the vector has been stored
3671 * in the VM-exit interruption-information field.
3672 */
3673 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT, 0 /* u64ExitQual */);
3674 }
3675
3676 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3677}
3678
3679
3680/**
3681 * Interface for HM and EM to emulate VM-exit due to external interrupts.
3682 *
3683 * @returns Strict VBox status code.
3684 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3685 * @param uVector The external interrupt vector (pass 0 if the external
3686 * interrupt is still pending).
3687 * @param fIntPending Whether the external interrupt is pending or
3688 * acknowledged in the interrupt controller.
3689 * @thread EMT(pVCpu)
3690 */
3691VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending)
3692{
3693 VBOXSTRICTRC rcStrict = iemVmxVmexitExtInt(pVCpu, uVector, fIntPending);
3694 Assert(!pVCpu->iem.s.cActiveMappings);
3695 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3696}
3697
3698
3699/**
3700 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3701 * an event.
3702 *
3703 * @returns VBox strict status code.
3704 * @param pVCpu The cross context virtual CPU structure.
3705 */
3706VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT
3707{
3708 uint32_t const fXcptBitmap = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32XcptBitmap;
3709 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3710 {
3711 /*
3712 * The NMI-unblocking due to IRET field need not be set for double faults.
3713 * See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
3714 */
3715 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3716 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3717 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3718 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, 0)
3719 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3720 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3721 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, 0 /* u64ExitQual */);
3722 }
3723
3724 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3725}
3726
3727
3728/**
3729 * VMX VM-exit handler for VM-exit due to delivery of an events.
3730 *
3731 * This is intended for VM-exit due to exceptions or NMIs where the caller provides
3732 * all the relevant VM-exit information.
3733 *
3734 * @returns VBox strict status code.
3735 * @param pVCpu The cross context virtual CPU structure.
3736 * @param pExitInfo Pointer to the VM-exit information.
3737 * @param pExitEventInfo Pointer to the VM-exit event information.
3738 */
3739static VBOXSTRICTRC iemVmxVmexitEventWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3740{
3741 Assert(pExitInfo);
3742 Assert(pExitEventInfo);
3743 Assert(pExitInfo->uReason == VMX_EXIT_XCPT_OR_NMI);
3744 Assert(VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3745
3746 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
3747 iemVmxVmcsSetExitIntInfo(pVCpu, pExitEventInfo->uExitIntInfo);
3748 iemVmxVmcsSetExitIntErrCode(pVCpu, pExitEventInfo->uExitIntErrCode);
3749 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3750 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3751 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, pExitInfo->u64Qual);
3752}
3753
3754
3755/**
3756 * Interface for HM and EM to emulate VM-exit due to NMIs.
3757 *
3758 * @returns Strict VBox status code.
3759 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3760 * @thread EMT(pVCpu)
3761 */
3762VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu)
3763{
3764 VMXVEXITINFO const ExitInfo = VMXVEXITINFO_INIT_ONLY_REASON(VMX_EXIT_XCPT_OR_NMI);
3765 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_INT( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1)
3766 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE,
3767 VMX_EXIT_INT_INFO_TYPE_NMI)
3768 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR,
3769 X86_XCPT_NMI),
3770 0);
3771 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
3772 Assert(!pVCpu->iem.s.cActiveMappings);
3773 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3774}
3775
3776
3777/**
3778 * Interface for HM and EM to emulate VM-exit due to exceptions.
3779 *
3780 * Exception includes NMIs, software exceptions (those generated by INT3 or
3781 * INTO) and privileged software exceptions (those generated by INT1/ICEBP).
3782 *
3783 * @returns Strict VBox status code.
3784 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3785 * @param pExitInfo Pointer to the VM-exit information.
3786 * @param pExitEventInfo Pointer to the VM-exit event information.
3787 * @thread EMT(pVCpu)
3788 */
3789VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
3790{
3791 Assert(pExitInfo);
3792 Assert(pExitEventInfo);
3793 VBOXSTRICTRC rcStrict = iemVmxVmexitEventWithInfo(pVCpu, pExitInfo, pExitEventInfo);
3794 Assert(!pVCpu->iem.s.cActiveMappings);
3795 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
3796}
3797
3798
3799/**
3800 * VMX VM-exit handler for VM-exits due to delivery of an event.
3801 *
3802 * @returns VBox strict status code.
3803 * @param pVCpu The cross context virtual CPU structure.
3804 * @param uVector The interrupt / exception vector.
3805 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3806 * @param uErrCode The error code associated with the event.
3807 * @param uCr2 The CR2 value in case of a \#PF exception.
3808 * @param cbInstr The instruction length in bytes.
3809 */
3810VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode,
3811 uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT
3812{
3813 /*
3814 * If the event is being injected as part of VM-entry, it is -not- subject to event
3815 * intercepts in the nested-guest. However, secondary exceptions that occur during
3816 * injection of any event -are- subject to event interception.
3817 *
3818 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
3819 */
3820 if (!CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx))
3821 {
3822 /*
3823 * If the event is a virtual-NMI (which is an NMI being inject during VM-entry)
3824 * virtual-NMI blocking must be set in effect rather than physical NMI blocking.
3825 *
3826 * See Intel spec. 24.6.1 "Pin-Based VM-Execution Controls".
3827 */
3828 if ( uVector == X86_XCPT_NMI
3829 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3830 && (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3831 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
3832 else
3833 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking);
3834
3835 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
3836 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3837 }
3838
3839 /*
3840 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
3841 * If not, the caller will continue delivery of the external interrupt as it would
3842 * normally. The interrupt is no longer pending in the interrupt controller at this
3843 * point.
3844 */
3845 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
3846 {
3847 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32RoIdtVectoringInfo));
3848 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
3849 }
3850
3851 /*
3852 * Evaluate intercepts for hardware exceptions, software exceptions (#BP, #OF),
3853 * and privileged software exceptions (#DB generated by INT1/ICEBP) and software
3854 * interrupts.
3855 */
3856 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
3857 bool fIntercept;
3858 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3859 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3860 fIntercept = CPUMIsGuestVmxXcptInterceptSet(&pVCpu->cpum.GstCtx, uVector, uErrCode);
3861 else
3862 {
3863 /* Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
3864 fIntercept = false;
3865 }
3866
3867 /*
3868 * Now that we've determined whether the event causes a VM-exit, we need to construct the
3869 * relevant VM-exit information and cause the VM-exit.
3870 */
3871 if (fIntercept)
3872 {
3873 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
3874
3875 /* Construct the rest of the event related information fields and cause the VM-exit. */
3876 uint64_t u64ExitQual;
3877 if (uVector == X86_XCPT_PF)
3878 {
3879 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
3880 u64ExitQual = uCr2;
3881 }
3882 else if (uVector == X86_XCPT_DB)
3883 {
3884 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
3885 u64ExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
3886 }
3887 else
3888 u64ExitQual = 0;
3889
3890 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3891 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
3892 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
3893 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3894 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
3895 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
3896 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3897 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3898 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3899 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
3900
3901 /*
3902 * For VM-exits due to software exceptions (those generated by INT3 or INTO) or privileged
3903 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
3904 * length.
3905 */
3906 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3907 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
3908 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3909 else
3910 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3911
3912 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI, u64ExitQual);
3913 }
3914
3915 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3916}
3917
3918
3919/**
3920 * VMX VM-exit handler for EPT misconfiguration.
3921 *
3922 * @param pVCpu The cross context virtual CPU structure.
3923 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3924 * This need not be page aligned (e.g. nested-guest in real
3925 * mode).
3926 */
3927static VBOXSTRICTRC iemVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr) RT_NOEXCEPT
3928{
3929 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3930 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3931}
3932
3933
3934/**
3935 * VMX VM-exit handler for EPT misconfiguration.
3936 *
3937 * This is intended for EPT misconfigurations where the caller provides all the
3938 * relevant VM-exit information.
3939 *
3940 * @param pVCpu The cross context virtual CPU structure.
3941 * @param GCPhysAddr The physical address causing the EPT misconfiguration.
3942 * This need not be page aligned (e.g. nested-guest in real
3943 * mode).
3944 * @param pExitEventInfo Pointer to the VM-exit event information.
3945 */
3946static VBOXSTRICTRC iemVmxVmexitEptMisconfigWithInfo(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
3947{
3948 Assert(pExitEventInfo);
3949 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
3950 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
3951 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
3952 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
3953 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_MISCONFIG, 0 /* u64ExitQual */);
3954}
3955
3956
3957/**
3958 * Interface for HM and EM to emulate a VM-exit due to an EPT misconfiguration.
3959 *
3960 * @returns Strict VBox status code.
3961 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3962 * @param GCPhysAddr The nested-guest physical address causing the EPT
3963 * misconfiguration.
3964 * @param pExitEventInfo Pointer to the VM-exit event information.
3965 * @thread EMT(pVCpu)
3966 */
3967VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo)
3968{
3969 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
3970
3971 iemInitExec(pVCpu, false /*fBypassHandlers*/);
3972 VBOXSTRICTRC rcStrict = iemVmxVmexitEptMisconfigWithInfo(pVCpu, GCPhysAddr, pExitEventInfo);
3973 Assert(!pVCpu->iem.s.cActiveMappings);
3974 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
3975}
3976
3977
3978/**
3979 * VMX VM-exit handler for EPT violation.
3980 *
3981 * @param pVCpu The cross context virtual CPU structure.
3982 * @param fAccess The access causing the EPT violation, IEM_ACCESS_XXX.
3983 * @param fSlatFail The SLAT failure info, IEM_SLAT_FAIL_XXX.
3984 * @param fEptAccess The EPT paging structure bits.
3985 * @param GCPhysAddr The physical address causing the EPT violation. This
3986 * need not be page aligned (e.g. nested-guest in real
3987 * mode).
3988 * @param fIsLinearAddrValid Whether translation of a linear address caused this
3989 * EPT violation. If @c false, GCPtrAddr must be 0.
3990 * @param GCPtrAddr The linear address causing the EPT violation.
3991 * @param cbInstr The VM-exit instruction length.
3992 */
3993static VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint32_t fSlatFail,
3994 uint64_t fEptAccess, RTGCPHYS GCPhysAddr, bool fIsLinearAddrValid,
3995 uint64_t GCPtrAddr, uint8_t cbInstr) RT_NOEXCEPT
3996{
3997 /*
3998 * If the linear address isn't valid (can happen when loading PDPTEs
3999 * as part of MOV CR execution) the linear address field is undefined.
4000 * While we can leave it this way, it's preferable to zero it for consistency.
4001 */
4002 Assert(fIsLinearAddrValid || GCPtrAddr == 0);
4003
4004 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
4005 bool const fSupportsAccessDirty = RT_BOOL(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
4006
4007 uint32_t const fDataRdMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_READ;
4008 uint32_t const fDataWrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_WRITE;
4009 uint32_t const fInstrMask = IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_EXEC;
4010 bool const fDataRead = ((fAccess & fDataRdMask) == IEM_ACCESS_DATA_R) | fSupportsAccessDirty;
4011 bool const fDataWrite = ((fAccess & fDataWrMask) == IEM_ACCESS_DATA_W) | fSupportsAccessDirty;
4012 bool const fInstrFetch = ((fAccess & fInstrMask) == IEM_ACCESS_INSTRUCTION);
4013 bool const fEptRead = RT_BOOL(fEptAccess & EPT_E_READ);
4014 bool const fEptWrite = RT_BOOL(fEptAccess & EPT_E_WRITE);
4015 bool const fEptExec = RT_BOOL(fEptAccess & EPT_E_EXECUTE);
4016 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4017 bool const fIsLinearToPhysAddr = fIsLinearAddrValid & RT_BOOL(fSlatFail & IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR);
4018
4019 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ, fDataRead)
4020 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE, fDataWrite)
4021 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
4022 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ, fEptRead)
4023 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE, fEptWrite)
4024 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE, fEptExec)
4025 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID, fIsLinearAddrValid)
4026 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR, fIsLinearToPhysAddr)
4027 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET, fNmiUnblocking);
4028
4029#ifdef VBOX_STRICT
4030 uint64_t const fMiscCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
4031 uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
4032 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION)); /* Advanced VM-exit info. not supported */
4033 Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK)); /* Supervisor shadow stack control not supported. */
4034 Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT))); /* Intel PT not supported. */
4035 Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM)); /* Mode-based execute control not supported. */
4036#endif
4037
4038 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
4039 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
4040 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4041
4042 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
4043}
4044
4045
4046/**
4047 * VMX VM-exit handler for EPT violation.
4048 *
4049 * This is intended for EPT violations where the caller provides all the
4050 * relevant VM-exit information.
4051 *
4052 * @returns VBox strict status code.
4053 * @param pVCpu The cross context virtual CPU structure.
4054 * @param pExitInfo Pointer to the VM-exit information.
4055 * @param pExitEventInfo Pointer to the VM-exit event information.
4056 */
4057static VBOXSTRICTRC iemVmxVmexitEptViolationWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4058 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4059{
4060 Assert(pExitInfo);
4061 Assert(pExitEventInfo);
4062 Assert(pExitInfo->uReason == VMX_EXIT_EPT_VIOLATION);
4063 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4064
4065 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4066 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4067
4068 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
4069 if (pExitInfo->u64Qual & VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK)
4070 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
4071 else
4072 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, 0);
4073 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4074 return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, pExitInfo->u64Qual);
4075}
4076
4077
4078/**
4079 * Interface for HM and EM to emulate a VM-exit due to an EPT violation.
4080 *
4081 * @returns Strict VBox status code.
4082 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4083 * @param pExitInfo Pointer to the VM-exit information.
4084 * @param pExitEventInfo Pointer to the VM-exit event information.
4085 * @thread EMT(pVCpu)
4086 */
4087VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4088 PCVMXVEXITEVENTINFO pExitEventInfo)
4089{
4090 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
4091
4092 iemInitExec(pVCpu, false /*fBypassHandlers*/);
4093 VBOXSTRICTRC rcStrict = iemVmxVmexitEptViolationWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4094 Assert(!pVCpu->iem.s.cActiveMappings);
4095 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
4096}
4097
4098
4099/**
4100 * VMX VM-exit handler for EPT-induced VM-exits.
4101 *
4102 * @param pVCpu The cross context virtual CPU structure.
4103 * @param pWalk The page walk info.
4104 * @param fAccess The access causing the EPT event, IEM_ACCESS_XXX.
4105 * @param fSlatFail Additional SLAT info, IEM_SLAT_FAIL_XXX.
4106 * @param cbInstr The VM-exit instruction length if applicable. Pass 0 if not
4107 * applicable.
4108 */
4109VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT
4110{
4111 Assert(pWalk->fIsSlat);
4112 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT);
4113 Assert(!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEptXcptVe); /* #VE exceptions not supported. */
4114 Assert(!(pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE)); /* Without #VE, convertible violations not possible. */
4115
4116 if (pWalk->fFailed & PGM_WALKFAIL_EPT_VIOLATION)
4117 {
4118 LogFlow(("EptViolation: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4119 uint64_t const fEptAccess = (pWalk->fEffective & PGM_PTATTRS_EPT_MASK) >> PGM_PTATTRS_EPT_SHIFT;
4120 return iemVmxVmexitEptViolation(pVCpu, fAccess, fSlatFail, fEptAccess, pWalk->GCPhysNested, pWalk->fIsLinearAddrValid,
4121 pWalk->GCPtr, cbInstr);
4122 }
4123
4124 LogFlow(("EptMisconfig: cs:rip=%04x:%08RX64 fAccess=%#RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fAccess));
4125 Assert(pWalk->fFailed & PGM_WALKFAIL_EPT_MISCONFIG);
4126 return iemVmxVmexitEptMisconfig(pVCpu, pWalk->GCPhysNested);
4127}
4128
4129
4130/**
4131 * VMX VM-exit handler for APIC accesses.
4132 *
4133 * @param pVCpu The cross context virtual CPU structure.
4134 * @param offAccess The offset of the register being accessed.
4135 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4136 */
4137static VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPUCC pVCpu, uint16_t offAccess, uint32_t fAccess) RT_NOEXCEPT
4138{
4139 VMXAPICACCESS enmAccess;
4140 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4141 if (fInEventDelivery)
4142 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4143 else if ((fAccess & (IEM_ACCESS_WHAT_MASK | IEM_ACCESS_TYPE_MASK)) == IEM_ACCESS_INSTRUCTION)
4144 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4145 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4146 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4147 else
4148 enmAccess = VMXAPICACCESS_LINEAR_READ;
4149
4150 uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4151 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4152 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, u64ExitQual);
4153}
4154
4155
4156/**
4157 * VMX VM-exit handler for APIC accesses.
4158 *
4159 * This is intended for APIC accesses where the caller provides all the
4160 * relevant VM-exit information.
4161 *
4162 * @returns VBox strict status code.
4163 * @param pVCpu The cross context virtual CPU structure.
4164 * @param pExitInfo Pointer to the VM-exit information.
4165 * @param pExitEventInfo Pointer to the VM-exit event information.
4166 */
4167static VBOXSTRICTRC iemVmxVmexitApicAccessWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo,
4168 PCVMXVEXITEVENTINFO pExitEventInfo) RT_NOEXCEPT
4169{
4170 /* VM-exit interruption information should not be valid for APIC-access VM-exits. */
4171 Assert(!VMX_EXIT_INT_INFO_IS_VALID(pExitEventInfo->uExitIntInfo));
4172 Assert(pExitInfo->uReason == VMX_EXIT_APIC_ACCESS);
4173 iemVmxVmcsSetExitIntInfo(pVCpu, 0);
4174 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
4175 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
4176 iemVmxVmcsSetIdtVectoringInfo(pVCpu, pExitEventInfo->uIdtVectoringInfo);
4177 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, pExitEventInfo->uIdtVectoringErrCode);
4178 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS, pExitInfo->u64Qual);
4179}
4180
4181
4182/**
4183 * Interface for HM and EM to virtualize memory-mapped APIC accesses.
4184 *
4185 * @returns Strict VBox status code.
4186 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the memory access was virtualized.
4187 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4188 *
4189 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4190 * @param pExitInfo Pointer to the VM-exit information.
4191 * @param pExitEventInfo Pointer to the VM-exit event information.
4192 * @thread EMT(pVCpu)
4193 */
4194VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo)
4195{
4196 Assert(pExitInfo);
4197 Assert(pExitEventInfo);
4198 VBOXSTRICTRC rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, pExitInfo, pExitEventInfo);
4199 Assert(!pVCpu->iem.s.cActiveMappings);
4200 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4201}
4202
4203
4204/**
4205 * VMX VM-exit handler for APIC-write VM-exits.
4206 *
4207 * @param pVCpu The cross context virtual CPU structure.
4208 * @param offApic The write to the virtual-APIC page offset that caused this
4209 * VM-exit.
4210 */
4211static VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPUCC pVCpu, uint16_t offApic) RT_NOEXCEPT
4212{
4213 Assert(offApic < XAPIC_OFF_END + 4);
4214 /* Write only bits 11:0 of the APIC offset into the Exit qualification field. */
4215 offApic &= UINT16_C(0xfff);
4216 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE, offApic);
4217}
4218
4219
4220/**
4221 * Clears any pending virtual-APIC write emulation.
4222 *
4223 * @returns The virtual-APIC offset that was written before clearing it.
4224 * @param pVCpu The cross context virtual CPU structure.
4225 */
4226DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPUCC pVCpu)
4227{
4228 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4229 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4230 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4231 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4232 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4233 return offVirtApicWrite;
4234}
4235
4236
4237/**
4238 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4239 *
4240 * @returns The register from the virtual-APIC page.
4241 * @param pVCpu The cross context virtual CPU structure.
4242 * @param offReg The offset of the register being read.
4243 */
4244uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4245{
4246 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4247
4248 uint32_t uReg = 0;
4249 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4250 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4251 AssertMsgStmt(RT_SUCCESS(rc),
4252 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4253 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4254 uReg = 0);
4255 return uReg;
4256}
4257
4258
4259/**
4260 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4261 *
4262 * @returns The register from the virtual-APIC page.
4263 * @param pVCpu The cross context virtual CPU structure.
4264 * @param offReg The offset of the register being read.
4265 */
4266static uint64_t iemVmxVirtApicReadRaw64(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT
4267{
4268 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4269
4270 uint64_t uReg = 0;
4271 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4272 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg, sizeof(uReg));
4273 AssertMsgStmt(RT_SUCCESS(rc),
4274 ("Failed to read %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4275 sizeof(uReg), offReg, GCPhysVirtApic, rc),
4276 uReg = 0);
4277 return uReg;
4278}
4279
4280
4281/**
4282 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4283 *
4284 * @param pVCpu The cross context virtual CPU structure.
4285 * @param offReg The offset of the register being written.
4286 * @param uReg The register value to write.
4287 */
4288void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT
4289{
4290 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4291
4292 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4293 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4294 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4295 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4296}
4297
4298
4299/**
4300 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4301 *
4302 * @param pVCpu The cross context virtual CPU structure.
4303 * @param offReg The offset of the register being written.
4304 * @param uReg The register value to write.
4305 */
4306static void iemVmxVirtApicWriteRaw64(PVMCPUCC pVCpu, uint16_t offReg, uint64_t uReg) RT_NOEXCEPT
4307{
4308 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint64_t));
4309
4310 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4311 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg, &uReg, sizeof(uReg));
4312 AssertMsgRC(rc, ("Failed to write %u bytes at offset %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4313 sizeof(uReg), offReg, GCPhysVirtApic, rc));
4314}
4315
4316
4317/**
4318 * Sets the vector in a virtual-APIC 256-bit sparse register.
4319 *
4320 * @param pVCpu The cross context virtual CPU structure.
4321 * @param offReg The offset of the 256-bit spare register.
4322 * @param uVector The vector to set.
4323 *
4324 * @remarks This is based on our APIC device code.
4325 */
4326static void iemVmxVirtApicSetVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4327{
4328 /* Determine the vector offset within the chunk. */
4329 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4330
4331 /* Read the chunk at the offset. */
4332 uint32_t uReg;
4333 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4334 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4335 if (RT_SUCCESS(rc))
4336 {
4337 /* Modify the chunk. */
4338 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4339 uReg |= RT_BIT(idxVectorBit);
4340
4341 /* Write the chunk. */
4342 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4343 AssertMsgRC(rc, ("Failed to set vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4344 uVector, offReg, GCPhysVirtApic, rc));
4345 }
4346 else
4347 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4348 uVector, offReg, GCPhysVirtApic, rc));
4349}
4350
4351
4352/**
4353 * Clears the vector in a virtual-APIC 256-bit sparse register.
4354 *
4355 * @param pVCpu The cross context virtual CPU structure.
4356 * @param offReg The offset of the 256-bit spare register.
4357 * @param uVector The vector to clear.
4358 *
4359 * @remarks This is based on our APIC device code.
4360 */
4361static void iemVmxVirtApicClearVectorInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t uVector) RT_NOEXCEPT
4362{
4363 /* Determine the vector offset within the chunk. */
4364 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4365
4366 /* Read the chunk at the offset. */
4367 uint32_t uReg;
4368 RTGCPHYS const GCPhysVirtApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrVirtApic.u;
4369 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &uReg, GCPhysVirtApic + offReg + offVector, sizeof(uReg));
4370 if (RT_SUCCESS(rc))
4371 {
4372 /* Modify the chunk. */
4373 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4374 uReg &= ~RT_BIT(idxVectorBit);
4375
4376 /* Write the chunk. */
4377 rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic + offReg + offVector, &uReg, sizeof(uReg));
4378 AssertMsgRC(rc, ("Failed to clear vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4379 uVector, offReg, GCPhysVirtApic, rc));
4380 }
4381 else
4382 AssertMsgFailed(("Failed to get vector %#x in 256-bit register at %#x of the virtual-APIC page at %#RGp: %Rrc\n",
4383 uVector, offReg, GCPhysVirtApic, rc));
4384}
4385
4386
4387/**
4388 * Checks if a memory access to the APIC-access page must causes an APIC-access
4389 * VM-exit.
4390 *
4391 * @param pVCpu The cross context virtual CPU structure.
4392 * @param offAccess The offset of the register being accessed.
4393 * @param cbAccess The size of the access in bytes.
4394 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4395 *
4396 * @remarks This must not be used for MSR-based APIC-access page accesses!
4397 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4398 */
4399static bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4400{
4401 Assert(cbAccess > 0);
4402 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4403
4404 /*
4405 * We must cause a VM-exit if any of the following are true:
4406 * - TPR shadowing isn't active.
4407 * - The access size exceeds 32-bits.
4408 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4409 *
4410 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4411 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4412 */
4413 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4414 || cbAccess > sizeof(uint32_t)
4415 || ((offAccess + cbAccess - 1) & 0xc)
4416 || offAccess >= XAPIC_OFF_END + 4)
4417 return true;
4418
4419 /*
4420 * If the access is part of an operation where we have already
4421 * virtualized a virtual-APIC write, we must cause a VM-exit.
4422 */
4423 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4424 return true;
4425
4426 /*
4427 * Check write accesses to the APIC-access page that cause VM-exits.
4428 */
4429 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4430 {
4431 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4432 {
4433 /*
4434 * With APIC-register virtualization, a write access to any of the
4435 * following registers are virtualized. Accessing any other register
4436 * causes a VM-exit.
4437 */
4438 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4439 switch (offAlignedAccess)
4440 {
4441 case XAPIC_OFF_ID:
4442 case XAPIC_OFF_TPR:
4443 case XAPIC_OFF_EOI:
4444 case XAPIC_OFF_LDR:
4445 case XAPIC_OFF_DFR:
4446 case XAPIC_OFF_SVR:
4447 case XAPIC_OFF_ESR:
4448 case XAPIC_OFF_ICR_LO:
4449 case XAPIC_OFF_ICR_HI:
4450 case XAPIC_OFF_LVT_TIMER:
4451 case XAPIC_OFF_LVT_THERMAL:
4452 case XAPIC_OFF_LVT_PERF:
4453 case XAPIC_OFF_LVT_LINT0:
4454 case XAPIC_OFF_LVT_LINT1:
4455 case XAPIC_OFF_LVT_ERROR:
4456 case XAPIC_OFF_TIMER_ICR:
4457 case XAPIC_OFF_TIMER_DCR:
4458 break;
4459 default:
4460 return true;
4461 }
4462 }
4463 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4464 {
4465 /*
4466 * With virtual-interrupt delivery, a write access to any of the
4467 * following registers are virtualized. Accessing any other register
4468 * causes a VM-exit.
4469 *
4470 * Note! The specification does not allow writing to offsets in-between
4471 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4472 */
4473 switch (offAccess)
4474 {
4475 case XAPIC_OFF_TPR:
4476 case XAPIC_OFF_EOI:
4477 case XAPIC_OFF_ICR_LO:
4478 break;
4479 default:
4480 return true;
4481 }
4482 }
4483 else
4484 {
4485 /*
4486 * Without APIC-register virtualization or virtual-interrupt delivery,
4487 * only TPR accesses are virtualized.
4488 */
4489 if (offAccess == XAPIC_OFF_TPR)
4490 { /* likely */ }
4491 else
4492 return true;
4493 }
4494 }
4495 else
4496 {
4497 /*
4498 * Check read accesses to the APIC-access page that cause VM-exits.
4499 */
4500 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4501 {
4502 /*
4503 * With APIC-register virtualization, a read access to any of the
4504 * following registers are virtualized. Accessing any other register
4505 * causes a VM-exit.
4506 */
4507 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4508 switch (offAlignedAccess)
4509 {
4510 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4511 case XAPIC_OFF_ID:
4512 case XAPIC_OFF_VERSION:
4513 case XAPIC_OFF_TPR:
4514 case XAPIC_OFF_EOI:
4515 case XAPIC_OFF_LDR:
4516 case XAPIC_OFF_DFR:
4517 case XAPIC_OFF_SVR:
4518 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4519 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4520 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4521 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4522 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4523 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4524 case XAPIC_OFF_ESR:
4525 case XAPIC_OFF_ICR_LO:
4526 case XAPIC_OFF_ICR_HI:
4527 case XAPIC_OFF_LVT_TIMER:
4528 case XAPIC_OFF_LVT_THERMAL:
4529 case XAPIC_OFF_LVT_PERF:
4530 case XAPIC_OFF_LVT_LINT0:
4531 case XAPIC_OFF_LVT_LINT1:
4532 case XAPIC_OFF_LVT_ERROR:
4533 case XAPIC_OFF_TIMER_ICR:
4534 case XAPIC_OFF_TIMER_DCR:
4535 break;
4536 default:
4537 return true;
4538 }
4539 }
4540 else
4541 {
4542 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4543 if (offAccess == XAPIC_OFF_TPR)
4544 { /* likely */ }
4545 else
4546 return true;
4547 }
4548 }
4549
4550 /* The APIC access is virtualized, does not cause a VM-exit. */
4551 return false;
4552}
4553
4554
4555/**
4556 * Virtualizes a memory-based APIC access by certain instructions even though they
4557 * do not use the address to access memory.
4558 *
4559 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4560 * page-faults but do not use the address to access memory.
4561 *
4562 * @param pVCpu The cross context virtual CPU structure.
4563 * @param pGCPhysAccess Pointer to the guest-physical address accessed.
4564 * @param cbAccess The size of the access in bytes.
4565 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4566 */
4567VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT
4568{
4569 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4570 Assert(pGCPhysAccess);
4571
4572 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
4573 RTGCPHYS const GCPhysApic = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
4574 Assert(!(GCPhysApic & GUEST_PAGE_OFFSET_MASK));
4575
4576 if (GCPhysAccess == GCPhysApic)
4577 {
4578 uint16_t const offAccess = *pGCPhysAccess & GUEST_PAGE_OFFSET_MASK;
4579 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4580 if (fIntercept)
4581 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4582
4583 *pGCPhysAccess = GCPhysApic | offAccess;
4584 return VINF_VMX_MODIFIES_BEHAVIOR;
4585 }
4586
4587 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4588}
4589
4590
4591/**
4592 * Virtualizes a memory-based APIC access.
4593 *
4594 * @returns VBox strict status code.
4595 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4596 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4597 *
4598 * @param pVCpu The cross context virtual CPU structure.
4599 * @param offAccess The offset of the register being accessed (within the
4600 * APIC-access page).
4601 * @param cbAccess The size of the access in bytes.
4602 * @param pvData Pointer to the data being written or where to store the data
4603 * being read.
4604 * @param fAccess The type of access, see IEM_ACCESS_XXX.
4605 */
4606static VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPUCC pVCpu, uint16_t offAccess, size_t cbAccess,
4607 void *pvData, uint32_t fAccess) RT_NOEXCEPT
4608{
4609 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4610 Assert(pvData);
4611
4612 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4613 if (fIntercept)
4614 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4615
4616 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4617 {
4618 /*
4619 * A write access to the APIC-access page that is virtualized (rather than
4620 * causing a VM-exit) writes data to the virtual-APIC page.
4621 */
4622 uint32_t const u32Data = *(uint32_t *)pvData;
4623 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4624
4625 /*
4626 * Record the currently updated APIC offset, as we need this later for figuring
4627 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4628 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4629 *
4630 * After completion of the current operation, we need to perform TPR virtualization,
4631 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4632 *
4633 * The current operation may be a REP-prefixed string instruction, execution of any
4634 * other instruction, or delivery of an event through the IDT.
4635 *
4636 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4637 * performed now but later after completion of the current operation.
4638 *
4639 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4640 */
4641 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4642
4643 LogFlowFunc(("Write access at offset %#x not intercepted -> Wrote %#RX32\n", offAccess, u32Data));
4644 }
4645 else
4646 {
4647 /*
4648 * A read access from the APIC-access page that is virtualized (rather than
4649 * causing a VM-exit) returns data from the virtual-APIC page.
4650 *
4651 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4652 */
4653 Assert(fAccess & IEM_ACCESS_TYPE_READ);
4654
4655 Assert(cbAccess <= 4);
4656 Assert(offAccess < XAPIC_OFF_END + 4);
4657 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4658
4659 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4660 u32Data &= s_auAccessSizeMasks[cbAccess];
4661 *(uint32_t *)pvData = u32Data;
4662
4663 LogFlowFunc(("Read access at offset %#x not intercepted -> Read %#RX32\n", offAccess, u32Data));
4664 }
4665
4666 return VINF_VMX_MODIFIES_BEHAVIOR;
4667}
4668
4669
4670/**
4671 * Virtualizes an MSR-based APIC read access.
4672 *
4673 * @returns VBox strict status code.
4674 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4675 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4676 * handled by the x2APIC device.
4677 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4678 * not within the range of valid MSRs, caller must raise \#GP(0).
4679 * @param pVCpu The cross context virtual CPU structure.
4680 * @param idMsr The x2APIC MSR being read.
4681 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4682 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4683 */
4684static VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value) RT_NOEXCEPT
4685{
4686 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4687 Assert(pu64Value);
4688
4689 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4690 {
4691 if ( idMsr >= MSR_IA32_X2APIC_START
4692 && idMsr <= MSR_IA32_X2APIC_END)
4693 {
4694 uint16_t const offReg = (idMsr & 0xff) << 4;
4695 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4696 *pu64Value = u64Value;
4697 return VINF_VMX_MODIFIES_BEHAVIOR;
4698 }
4699 return VERR_OUT_OF_RANGE;
4700 }
4701
4702 if (idMsr == MSR_IA32_X2APIC_TPR)
4703 {
4704 uint16_t const offReg = (idMsr & 0xff) << 4;
4705 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4706 *pu64Value = u64Value;
4707 return VINF_VMX_MODIFIES_BEHAVIOR;
4708 }
4709
4710 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4711}
4712
4713
4714/**
4715 * Virtualizes an MSR-based APIC write access.
4716 *
4717 * @returns VBox strict status code.
4718 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4719 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4720 * not within the range of valid MSRs, caller must raise \#GP(0).
4721 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4722 *
4723 * @param pVCpu The cross context virtual CPU structure.
4724 * @param idMsr The x2APIC MSR being written.
4725 * @param u64Value The value of the x2APIC MSR being written.
4726 */
4727static VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Value) RT_NOEXCEPT
4728{
4729 /*
4730 * Check if the access is to be virtualized.
4731 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4732 */
4733 if ( idMsr == MSR_IA32_X2APIC_TPR
4734 || ( (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4735 && ( idMsr == MSR_IA32_X2APIC_EOI
4736 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4737 {
4738 /* Validate the MSR write depending on the register. */
4739 switch (idMsr)
4740 {
4741 case MSR_IA32_X2APIC_TPR:
4742 case MSR_IA32_X2APIC_SELF_IPI:
4743 {
4744 if (u64Value & UINT64_C(0xffffffffffffff00))
4745 return VERR_OUT_OF_RANGE;
4746 break;
4747 }
4748 case MSR_IA32_X2APIC_EOI:
4749 {
4750 if (u64Value != 0)
4751 return VERR_OUT_OF_RANGE;
4752 break;
4753 }
4754 }
4755
4756 /* Write the MSR to the virtual-APIC page. */
4757 uint16_t const offReg = (idMsr & 0xff) << 4;
4758 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4759
4760 /*
4761 * Record the currently updated APIC offset, as we need this later for figuring
4762 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4763 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4764 */
4765 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4766
4767 return VINF_VMX_MODIFIES_BEHAVIOR;
4768 }
4769
4770 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4771}
4772
4773
4774/**
4775 * Interface for HM and EM to virtualize x2APIC MSR accesses.
4776 *
4777 * @returns Strict VBox status code.
4778 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR access was virtualized.
4779 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR access must be handled by
4780 * the x2APIC device.
4781 * @retval VERR_OUT_RANGE if the caller must raise \#GP(0).
4782 *
4783 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4784 * @param idMsr The MSR being read.
4785 * @param pu64Value Pointer to the value being written or where to store the
4786 * value being read.
4787 * @param fWrite Whether this is an MSR write or read access.
4788 * @thread EMT(pVCpu)
4789 */
4790VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Value, bool fWrite)
4791{
4792 Assert(pu64Value);
4793
4794 VBOXSTRICTRC rcStrict;
4795 if (fWrite)
4796 rcStrict = iemVmxVirtApicAccessMsrWrite(pVCpu, idMsr, *pu64Value);
4797 else
4798 rcStrict = iemVmxVirtApicAccessMsrRead(pVCpu, idMsr, pu64Value);
4799 Assert(!pVCpu->iem.s.cActiveMappings);
4800 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
4801
4802}
4803
4804
4805/**
4806 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4807 *
4808 * @returns VBox status code.
4809 * @retval VINF_SUCCESS when the highest set bit is found.
4810 * @retval VERR_NOT_FOUND when no bit is set.
4811 *
4812 * @param pVCpu The cross context virtual CPU structure.
4813 * @param offReg The offset of the APIC 256-bit sparse register.
4814 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4815 * set in the register. Only valid when VINF_SUCCESS is
4816 * returned.
4817 *
4818 * @remarks The format of the 256-bit sparse register here mirrors that found in
4819 * real APIC hardware.
4820 */
4821static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPUCC pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4822{
4823 Assert(offReg < XAPIC_OFF_END + 4);
4824 Assert(pidxHighestBit);
4825
4826 /*
4827 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4828 * However, in each fragment only the first 4 bytes are used.
4829 */
4830 uint8_t const cFrags = 8;
4831 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4832 {
4833 uint16_t const offFrag = iFrag * 16;
4834 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4835 if (!u32Frag)
4836 continue;
4837
4838 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4839 Assert(idxHighestBit > 0);
4840 --idxHighestBit;
4841 Assert(idxHighestBit <= UINT8_MAX);
4842 *pidxHighestBit = idxHighestBit;
4843 return VINF_SUCCESS;
4844 }
4845 return VERR_NOT_FOUND;
4846}
4847
4848
4849/**
4850 * Evaluates pending virtual interrupts.
4851 *
4852 * @param pVCpu The cross context virtual CPU structure.
4853 */
4854static void iemVmxEvalPendingVirtIntrs(PVMCPUCC pVCpu) RT_NOEXCEPT
4855{
4856 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4857
4858 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4859 {
4860 uint8_t const uRvi = RT_LO_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus);
4861 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4862
4863 if ((uRvi >> 4) > (uPpr >> 4))
4864 {
4865 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signalling pending interrupt\n", uRvi, uPpr));
4866 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4867 }
4868 else
4869 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4870 }
4871}
4872
4873
4874/**
4875 * Performs PPR virtualization.
4876 *
4877 * @returns VBox strict status code.
4878 * @param pVCpu The cross context virtual CPU structure.
4879 */
4880static void iemVmxPprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4881{
4882 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4883 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4884
4885 /*
4886 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4887 * or EOI-virtualization.
4888 *
4889 * See Intel spec. 29.1.3 "PPR Virtualization".
4890 */
4891 uint8_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4892 uint8_t const uSvi = RT_HI_U8(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u16GuestIntStatus) & 0xf0;
4893
4894 uint32_t uPpr;
4895 if ((uTpr & 0xf0) >= uSvi)
4896 uPpr = uTpr;
4897 else
4898 uPpr = uSvi;
4899
4900 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4901 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4902}
4903
4904
4905/**
4906 * Performs VMX TPR virtualization.
4907 *
4908 * @returns VBox strict status code.
4909 * @param pVCpu The cross context virtual CPU structure.
4910 */
4911static VBOXSTRICTRC iemVmxTprVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4912{
4913 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4914
4915 /*
4916 * We should have already performed the virtual-APIC write to the TPR offset
4917 * in the virtual-APIC page. We now perform TPR virtualization.
4918 *
4919 * See Intel spec. 29.1.2 "TPR Virtualization".
4920 */
4921 if (!(pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4922 {
4923 uint32_t const uTprThreshold = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32TprThreshold;
4924 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4925
4926 /*
4927 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4928 * See Intel spec. 29.1.2 "TPR Virtualization".
4929 */
4930 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4931 {
4932 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4933 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD, 0 /* u64ExitQual */);
4934 }
4935 }
4936 else
4937 {
4938 iemVmxPprVirtualization(pVCpu);
4939 iemVmxEvalPendingVirtIntrs(pVCpu);
4940 }
4941
4942 return VINF_SUCCESS;
4943}
4944
4945
4946/**
4947 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4948 * not.
4949 *
4950 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4951 * @param pVCpu The cross context virtual CPU structure.
4952 * @param uVector The interrupt that was acknowledged using an EOI.
4953 */
4954static bool iemVmxIsEoiInterceptSet(PCVMCPU pVCpu, uint8_t uVector) RT_NOEXCEPT
4955{
4956 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4957 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4958
4959 if (uVector < 64)
4960 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4961 if (uVector < 128)
4962 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4963 if (uVector < 192)
4964 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4965 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4966}
4967
4968
4969/**
4970 * Performs EOI virtualization.
4971 *
4972 * @returns VBox strict status code.
4973 * @param pVCpu The cross context virtual CPU structure.
4974 */
4975static VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
4976{
4977 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
4978 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4979
4980 /*
4981 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4982 * and get the next guest-interrupt that's in-service (if any).
4983 *
4984 * See Intel spec. 29.1.4 "EOI Virtualization".
4985 */
4986 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4987 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4988 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4989
4990 uint8_t uVector = uSvi;
4991 iemVmxVirtApicClearVectorInReg(pVCpu, XAPIC_OFF_ISR0, uVector);
4992
4993 uVector = 0;
4994 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4995
4996 if (uVector)
4997 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4998 else
4999 Log2(("eoi_virt: no interrupt pending in ISR\n"));
5000
5001 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
5002 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
5003
5004 iemVmxPprVirtualization(pVCpu);
5005 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
5006 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI, uVector);
5007 iemVmxEvalPendingVirtIntrs(pVCpu);
5008 return VINF_SUCCESS;
5009}
5010
5011
5012/**
5013 * Performs self-IPI virtualization.
5014 *
5015 * @returns VBox strict status code.
5016 * @param pVCpu The cross context virtual CPU structure.
5017 */
5018static VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPUCC pVCpu) RT_NOEXCEPT
5019{
5020 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5021 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5022
5023 /*
5024 * We should have already performed the virtual-APIC write to the self-IPI offset
5025 * in the virtual-APIC page. We now perform self-IPI virtualization.
5026 *
5027 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
5028 */
5029 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
5030 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
5031 iemVmxVirtApicSetVectorInReg(pVCpu, XAPIC_OFF_IRR0, uVector);
5032 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
5033 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
5034 if (uVector > uRvi)
5035 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5036 iemVmxEvalPendingVirtIntrs(pVCpu);
5037 return VINF_SUCCESS;
5038}
5039
5040
5041/**
5042 * Performs VMX APIC-write emulation.
5043 *
5044 * @returns VBox strict status code.
5045 * @param pVCpu The cross context virtual CPU structure.
5046 */
5047VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT
5048{
5049 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5050
5051 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5052 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5053
5054 /*
5055 * Perform APIC-write emulation based on the virtual-APIC register written.
5056 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5057 */
5058 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5059 VBOXSTRICTRC rcStrict;
5060 switch (offApicWrite)
5061 {
5062 case XAPIC_OFF_TPR:
5063 {
5064 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5065 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5066 uTpr &= UINT32_C(0x000000ff);
5067 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5068 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5069 rcStrict = iemVmxTprVirtualization(pVCpu);
5070 break;
5071 }
5072
5073 case XAPIC_OFF_EOI:
5074 {
5075 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5076 {
5077 /* Clear VEOI and perform EOI virtualization. */
5078 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5079 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5080 rcStrict = iemVmxEoiVirtualization(pVCpu);
5081 }
5082 else
5083 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5084 break;
5085 }
5086
5087 case XAPIC_OFF_ICR_LO:
5088 {
5089 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5090 {
5091 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5092 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5093 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5094 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5095 if ( !(uIcrLo & fIcrLoMb0)
5096 && (uIcrLo & fIcrLoMb1))
5097 {
5098 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5099 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5100 }
5101 else
5102 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5103 }
5104 else
5105 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5106 break;
5107 }
5108
5109 case XAPIC_OFF_ICR_HI:
5110 {
5111 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5112 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5113 uIcrHi &= UINT32_C(0xff000000);
5114 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5115 rcStrict = VINF_SUCCESS;
5116 break;
5117 }
5118
5119 default:
5120 {
5121 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5122 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5123 break;
5124 }
5125 }
5126
5127 return rcStrict;
5128}
5129
5130
5131/**
5132 * Interface for HM and EM to perform an APIC-write emulation which may cause a
5133 * VM-exit.
5134 *
5135 * @returns Strict VBox status code.
5136 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
5137 * @thread EMT(pVCpu)
5138 */
5139VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu)
5140{
5141 VBOXSTRICTRC rcStrict = iemVmxApicWriteEmulation(pVCpu);
5142 Assert(!pVCpu->iem.s.cActiveMappings);
5143 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
5144}
5145
5146
5147/**
5148 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5149 *
5150 * @param pVCpu The cross context virtual CPU structure.
5151 * @param pszInstr The VMX instruction name (for logging purposes).
5152 */
5153DECLINLINE(int) iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPUCC pVCpu, const char *pszInstr)
5154{
5155 /*
5156 * Guest Control Registers, Debug Registers, and MSRs.
5157 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5158 */
5159 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5160 const char * const pszFailure = "VM-exit";
5161 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5162
5163 /* CR0 reserved bits. */
5164 {
5165 /* CR0 MB1 bits. */
5166 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
5167 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5168 { /* likely */ }
5169 else
5170 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5171
5172 /* CR0 MBZ bits. */
5173 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5174 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5175 { /* likely */ }
5176 else
5177 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5178
5179 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5180 if ( !fUnrestrictedGuest
5181 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5182 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5183 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5184 }
5185
5186 /* CR4 reserved bits. */
5187 {
5188 /* CR4 MB1 bits. */
5189 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5190 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5191 { /* likely */ }
5192 else
5193 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5194
5195 /* CR4 MBZ bits. */
5196 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5197 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5198 { /* likely */ }
5199 else
5200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5201 }
5202
5203 /* DEBUGCTL MSR. */
5204 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5205 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5206 { /* likely */ }
5207 else
5208 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5209
5210 /* 64-bit CPU checks. */
5211 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5212 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5213 {
5214 if (fGstInLongMode)
5215 {
5216 /* PAE must be set. */
5217 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5218 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5219 { /* likely */ }
5220 else
5221 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5222 }
5223 else
5224 {
5225 /* PCIDE should not be set. */
5226 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5227 { /* likely */ }
5228 else
5229 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5230 }
5231
5232 /* CR3. */
5233 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5234 { /* likely */ }
5235 else
5236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5237
5238 /* DR7. */
5239 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5240 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5241 { /* likely */ }
5242 else
5243 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5244
5245 /* SYSENTER ESP and SYSENTER EIP. */
5246 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5247 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5248 { /* likely */ }
5249 else
5250 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5251 }
5252
5253 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5254 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5255
5256 /* PAT MSR. */
5257 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5258 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5259 { /* likely */ }
5260 else
5261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5262
5263 /* EFER MSR. */
5264 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5265 {
5266 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5267 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5268 { /* likely */ }
5269 else
5270 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5271
5272 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5273 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5274 if ( fGstLma == fGstInLongMode
5275 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5276 || fGstLma == fGstLme))
5277 { /* likely */ }
5278 else
5279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5280 }
5281
5282 /* We don't support IA32_BNDCFGS MSR yet. */
5283 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5284
5285 NOREF(pszInstr);
5286 NOREF(pszFailure);
5287 return VINF_SUCCESS;
5288}
5289
5290
5291/**
5292 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5293 *
5294 * @param pVCpu The cross context virtual CPU structure.
5295 * @param pszInstr The VMX instruction name (for logging purposes).
5296 */
5297DECLINLINE(int) iemVmxVmentryCheckGuestSegRegs(PVMCPUCC pVCpu, const char *pszInstr)
5298{
5299 /*
5300 * Segment registers.
5301 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5302 */
5303 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5304 const char * const pszFailure = "VM-exit";
5305 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5306 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5307 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5308
5309 /* Selectors. */
5310 if ( !fGstInV86Mode
5311 && !fUnrestrictedGuest
5312 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5313 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5314
5315 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5316 {
5317 CPUMSELREG SelReg;
5318 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5319 if (RT_LIKELY(rc == VINF_SUCCESS))
5320 { /* likely */ }
5321 else
5322 return rc;
5323
5324 /*
5325 * Virtual-8086 mode checks.
5326 */
5327 if (fGstInV86Mode)
5328 {
5329 /* Base address. */
5330 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5331 { /* likely */ }
5332 else
5333 {
5334 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5335 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5336 }
5337
5338 /* Limit. */
5339 if (SelReg.u32Limit == 0xffff)
5340 { /* likely */ }
5341 else
5342 {
5343 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5344 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5345 }
5346
5347 /* Attribute. */
5348 if (SelReg.Attr.u == 0xf3)
5349 { /* likely */ }
5350 else
5351 {
5352 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5353 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5354 }
5355
5356 /* We're done; move to checking the next segment. */
5357 continue;
5358 }
5359
5360 /* Checks done by 64-bit CPUs. */
5361 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5362 {
5363 /* Base address. */
5364 if ( iSegReg == X86_SREG_FS
5365 || iSegReg == X86_SREG_GS)
5366 {
5367 if (X86_IS_CANONICAL(SelReg.u64Base))
5368 { /* likely */ }
5369 else
5370 {
5371 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5372 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5373 }
5374 }
5375 else if (iSegReg == X86_SREG_CS)
5376 {
5377 if (!RT_HI_U32(SelReg.u64Base))
5378 { /* likely */ }
5379 else
5380 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5381 }
5382 else
5383 {
5384 if ( SelReg.Attr.n.u1Unusable
5385 || !RT_HI_U32(SelReg.u64Base))
5386 { /* likely */ }
5387 else
5388 {
5389 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5390 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5391 }
5392 }
5393 }
5394
5395 /*
5396 * Checks outside Virtual-8086 mode.
5397 */
5398 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5399 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5400 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5401 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5402 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5403 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5404 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5405 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5406
5407 /* Code or usable segment. */
5408 if ( iSegReg == X86_SREG_CS
5409 || fUsable)
5410 {
5411 /* Reserved bits (bits 31:17 and bits 11:8). */
5412 if (!(SelReg.Attr.u & 0xfffe0f00))
5413 { /* likely */ }
5414 else
5415 {
5416 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5417 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5418 }
5419
5420 /* Descriptor type. */
5421 if (fCodeDataSeg)
5422 { /* likely */ }
5423 else
5424 {
5425 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5426 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5427 }
5428
5429 /* Present. */
5430 if (fPresent)
5431 { /* likely */ }
5432 else
5433 {
5434 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5435 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5436 }
5437
5438 /* Granularity. */
5439 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5440 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5441 { /* likely */ }
5442 else
5443 {
5444 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5445 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5446 }
5447 }
5448
5449 if (iSegReg == X86_SREG_CS)
5450 {
5451 /* Segment Type and DPL. */
5452 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5453 && fUnrestrictedGuest)
5454 {
5455 if (uDpl == 0)
5456 { /* likely */ }
5457 else
5458 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5459 }
5460 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5461 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5462 {
5463 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5464 if (uDpl == AttrSs.n.u2Dpl)
5465 { /* likely */ }
5466 else
5467 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5468 }
5469 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5470 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5471 {
5472 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5473 if (uDpl <= AttrSs.n.u2Dpl)
5474 { /* likely */ }
5475 else
5476 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5477 }
5478 else
5479 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5480
5481 /* Def/Big. */
5482 if ( fGstInLongMode
5483 && fSegLong)
5484 {
5485 if (uDefBig == 0)
5486 { /* likely */ }
5487 else
5488 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5489 }
5490 }
5491 else if (iSegReg == X86_SREG_SS)
5492 {
5493 /* Segment Type. */
5494 if ( !fUsable
5495 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5496 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5497 { /* likely */ }
5498 else
5499 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5500
5501 /* DPL. */
5502 if (!fUnrestrictedGuest)
5503 {
5504 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5505 { /* likely */ }
5506 else
5507 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5508 }
5509 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5510 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5511 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5512 {
5513 if (uDpl == 0)
5514 { /* likely */ }
5515 else
5516 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5517 }
5518 }
5519 else
5520 {
5521 /* DS, ES, FS, GS. */
5522 if (fUsable)
5523 {
5524 /* Segment type. */
5525 if (uSegType & X86_SEL_TYPE_ACCESSED)
5526 { /* likely */ }
5527 else
5528 {
5529 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5530 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5531 }
5532
5533 if ( !(uSegType & X86_SEL_TYPE_CODE)
5534 || (uSegType & X86_SEL_TYPE_READ))
5535 { /* likely */ }
5536 else
5537 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5538
5539 /* DPL. */
5540 if ( !fUnrestrictedGuest
5541 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5542 {
5543 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5544 { /* likely */ }
5545 else
5546 {
5547 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5548 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5549 }
5550 }
5551 }
5552 }
5553 }
5554
5555 /*
5556 * LDTR.
5557 */
5558 {
5559 CPUMSELREG Ldtr;
5560 Ldtr.Sel = pVmcs->GuestLdtr;
5561 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5562 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5563 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5564
5565 if (!Ldtr.Attr.n.u1Unusable)
5566 {
5567 /* Selector. */
5568 if (!(Ldtr.Sel & X86_SEL_LDT))
5569 { /* likely */ }
5570 else
5571 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5572
5573 /* Base. */
5574 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5575 {
5576 if (X86_IS_CANONICAL(Ldtr.u64Base))
5577 { /* likely */ }
5578 else
5579 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5580 }
5581
5582 /* Attributes. */
5583 /* Reserved bits (bits 31:17 and bits 11:8). */
5584 if (!(Ldtr.Attr.u & 0xfffe0f00))
5585 { /* likely */ }
5586 else
5587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5588
5589 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5590 { /* likely */ }
5591 else
5592 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5593
5594 if (!Ldtr.Attr.n.u1DescType)
5595 { /* likely */ }
5596 else
5597 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5598
5599 if (Ldtr.Attr.n.u1Present)
5600 { /* likely */ }
5601 else
5602 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5603
5604 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5605 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5606 { /* likely */ }
5607 else
5608 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5609 }
5610 }
5611
5612 /*
5613 * TR.
5614 */
5615 {
5616 CPUMSELREG Tr;
5617 Tr.Sel = pVmcs->GuestTr;
5618 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5619 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5620 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5621
5622 /* Selector. */
5623 if (!(Tr.Sel & X86_SEL_LDT))
5624 { /* likely */ }
5625 else
5626 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5627
5628 /* Base. */
5629 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5630 {
5631 if (X86_IS_CANONICAL(Tr.u64Base))
5632 { /* likely */ }
5633 else
5634 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5635 }
5636
5637 /* Attributes. */
5638 /* Reserved bits (bits 31:17 and bits 11:8). */
5639 if (!(Tr.Attr.u & 0xfffe0f00))
5640 { /* likely */ }
5641 else
5642 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5643
5644 if (!Tr.Attr.n.u1Unusable)
5645 { /* likely */ }
5646 else
5647 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5648
5649 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5650 || ( !fGstInLongMode
5651 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5652 { /* likely */ }
5653 else
5654 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5655
5656 if (!Tr.Attr.n.u1DescType)
5657 { /* likely */ }
5658 else
5659 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5660
5661 if (Tr.Attr.n.u1Present)
5662 { /* likely */ }
5663 else
5664 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5665
5666 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5667 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5668 { /* likely */ }
5669 else
5670 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5671 }
5672
5673 NOREF(pszInstr);
5674 NOREF(pszFailure);
5675 return VINF_SUCCESS;
5676}
5677
5678
5679/**
5680 * Checks guest GDTR and IDTR as part of VM-entry.
5681 *
5682 * @param pVCpu The cross context virtual CPU structure.
5683 * @param pszInstr The VMX instruction name (for logging purposes).
5684 */
5685DECLINLINE(int) iemVmxVmentryCheckGuestGdtrIdtr(PVMCPUCC pVCpu, const char *pszInstr)
5686{
5687 /*
5688 * GDTR and IDTR.
5689 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5690 */
5691 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5692 const char *const pszFailure = "VM-exit";
5693
5694 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5695 {
5696 /* Base. */
5697 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5698 { /* likely */ }
5699 else
5700 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5701
5702 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5703 { /* likely */ }
5704 else
5705 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5706 }
5707
5708 /* Limit. */
5709 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5710 { /* likely */ }
5711 else
5712 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5713
5714 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5715 { /* likely */ }
5716 else
5717 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5718
5719 NOREF(pszInstr);
5720 NOREF(pszFailure);
5721 return VINF_SUCCESS;
5722}
5723
5724
5725/**
5726 * Checks guest RIP and RFLAGS as part of VM-entry.
5727 *
5728 * @param pVCpu The cross context virtual CPU structure.
5729 * @param pszInstr The VMX instruction name (for logging purposes).
5730 */
5731DECLINLINE(int) iemVmxVmentryCheckGuestRipRFlags(PVMCPUCC pVCpu, const char *pszInstr)
5732{
5733 /*
5734 * RIP and RFLAGS.
5735 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5736 */
5737 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5738 const char *const pszFailure = "VM-exit";
5739 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5740
5741 /* RIP. */
5742 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5743 {
5744 X86DESCATTR AttrCs;
5745 AttrCs.u = pVmcs->u32GuestCsAttr;
5746 if ( !fGstInLongMode
5747 || !AttrCs.n.u1Long)
5748 {
5749 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5750 { /* likely */ }
5751 else
5752 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5753 }
5754
5755 if ( fGstInLongMode
5756 && AttrCs.n.u1Long)
5757 {
5758 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5759 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5760 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5761 { /* likely */ }
5762 else
5763 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5764 }
5765 }
5766
5767 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5768 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5769 : pVmcs->u64GuestRFlags.s.Lo;
5770 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5771 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5772 { /* likely */ }
5773 else
5774 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5775
5776 if (!(uGuestRFlags & X86_EFL_VM))
5777 { /* likely */ }
5778 else
5779 {
5780 if ( fGstInLongMode
5781 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5782 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5783 }
5784
5785 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(pVmcs->u32EntryIntInfo))
5786 {
5787 if (uGuestRFlags & X86_EFL_IF)
5788 { /* likely */ }
5789 else
5790 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5791 }
5792
5793 NOREF(pszInstr);
5794 NOREF(pszFailure);
5795 return VINF_SUCCESS;
5796}
5797
5798
5799/**
5800 * Checks guest non-register state as part of VM-entry.
5801 *
5802 * @param pVCpu The cross context virtual CPU structure.
5803 * @param pszInstr The VMX instruction name (for logging purposes).
5804 */
5805DECLINLINE(int) iemVmxVmentryCheckGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr)
5806{
5807 /*
5808 * Guest non-register state.
5809 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5810 */
5811 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
5812 const char *const pszFailure = "VM-exit";
5813
5814 /*
5815 * Activity state.
5816 */
5817 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5818 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5819 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5820 { /* likely */ }
5821 else
5822 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5823
5824 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5825 if ( !AttrSs.n.u2Dpl
5826 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5827 { /* likely */ }
5828 else
5829 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5830
5831 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5832 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5833 {
5834 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5835 { /* likely */ }
5836 else
5837 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5838 }
5839
5840 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5841 {
5842 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5843 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5844 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5845 switch (pVmcs->u32GuestActivityState)
5846 {
5847 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5848 {
5849 if ( uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5850 || uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5851 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5852 && ( uVector == X86_XCPT_DB
5853 || uVector == X86_XCPT_MC))
5854 || ( uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5855 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5856 { /* likely */ }
5857 else
5858 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5859 break;
5860 }
5861
5862 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5863 {
5864 if ( uType == VMX_ENTRY_INT_INFO_TYPE_NMI
5865 || ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5866 && uVector == X86_XCPT_MC))
5867 { /* likely */ }
5868 else
5869 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5870 break;
5871 }
5872
5873 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5874 default:
5875 break;
5876 }
5877 }
5878
5879 /*
5880 * Interruptibility state.
5881 */
5882 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5883 { /* likely */ }
5884 else
5885 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5886
5887 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5888 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5889 { /* likely */ }
5890 else
5891 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5892
5893 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5894 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5895 { /* likely */ }
5896 else
5897 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5898
5899 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5900 {
5901 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5902 if (uType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5903 {
5904 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5905 { /* likely */ }
5906 else
5907 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5908 }
5909 else if (uType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5910 {
5911 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5912 { /* likely */ }
5913 else
5914 {
5915 /*
5916 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5917 * We update the Exit qualification only when blocking-by-STI is set
5918 * without blocking-by-MovSS being set. Although in practise it does not
5919 * make much difference since the order of checks are implementation defined.
5920 */
5921 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5922 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5923 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5924 }
5925
5926 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5927 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5928 { /* likely */ }
5929 else
5930 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5931 }
5932 }
5933
5934 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5935 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5936 { /* likely */ }
5937 else
5938 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5939
5940 /* We don't support SGX yet. So enclave-interruption must not be set. */
5941 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5942 { /* likely */ }
5943 else
5944 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5945
5946 /*
5947 * Pending debug exceptions.
5948 */
5949 uint64_t const uPendingDbgXcpts = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5950 ? pVmcs->u64GuestPendingDbgXcpts.u
5951 : pVmcs->u64GuestPendingDbgXcpts.s.Lo;
5952 if (!(uPendingDbgXcpts & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5953 { /* likely */ }
5954 else
5955 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5956
5957 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5958 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5959 {
5960 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5961 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5962 && !(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5963 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5964
5965 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5966 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5967 && (uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5968 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5969 }
5970
5971 /* We don't support RTM (Real-time Transactional Memory) yet. */
5972 if (!(uPendingDbgXcpts & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5973 { /* likely */ }
5974 else
5975 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5976
5977 /*
5978 * VMCS link pointer.
5979 */
5980 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5981 {
5982 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5983 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5984 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5985 { /* likely */ }
5986 else
5987 {
5988 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5989 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5990 }
5991
5992 /* Validate the address. */
5993 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5994 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5995 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5996 { /* likely */ }
5997 else
5998 {
5999 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
6000 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
6001 }
6002 }
6003
6004 NOREF(pszInstr);
6005 NOREF(pszFailure);
6006 return VINF_SUCCESS;
6007}
6008
6009
6010#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6011/**
6012 * Checks guest PDPTEs as part of VM-entry.
6013 *
6014 * @param pVCpu The cross context virtual CPU structure.
6015 * @param pszInstr The VMX instruction name (for logging purposes).
6016 */
6017static int iemVmxVmentryCheckGuestPdptes(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6018{
6019 /*
6020 * Guest PDPTEs.
6021 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6022 */
6023 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6024 const char * const pszFailure = "VM-exit";
6025
6026 /*
6027 * When EPT is used, we need to validate the PAE PDPTEs provided in the VMCS.
6028 * Otherwise, we load any PAE PDPTEs referenced by CR3 at a later point.
6029 */
6030 if ( iemVmxVmcsIsGuestPaePagingEnabled(pVmcs)
6031 && (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT))
6032 {
6033 /* Get PDPTEs from the VMCS. */
6034 X86PDPE aPaePdptes[X86_PG_PAE_PDPE_ENTRIES];
6035 aPaePdptes[0].u = pVmcs->u64GuestPdpte0.u;
6036 aPaePdptes[1].u = pVmcs->u64GuestPdpte1.u;
6037 aPaePdptes[2].u = pVmcs->u64GuestPdpte2.u;
6038 aPaePdptes[3].u = pVmcs->u64GuestPdpte3.u;
6039
6040 /* Check validity of the PDPTEs. */
6041 if (PGMGstArePaePdpesValid(pVCpu, &aPaePdptes[0]))
6042 { /* likely */ }
6043 else
6044 {
6045 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6046 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
6047 }
6048 }
6049
6050 NOREF(pszFailure);
6051 NOREF(pszInstr);
6052 return VINF_SUCCESS;
6053}
6054#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
6055
6056
6057/**
6058 * Checks guest-state as part of VM-entry.
6059 *
6060 * @returns VBox status code.
6061 * @param pVCpu The cross context virtual CPU structure.
6062 * @param pszInstr The VMX instruction name (for logging purposes).
6063 */
6064static int iemVmxVmentryCheckGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6065{
6066 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6067 if (RT_SUCCESS(rc))
6068 {
6069 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6070 if (RT_SUCCESS(rc))
6071 {
6072 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6073 if (RT_SUCCESS(rc))
6074 {
6075 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6076 if (RT_SUCCESS(rc))
6077 {
6078 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6079#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6080 if (RT_SUCCESS(rc))
6081 rc = iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6082#endif
6083 }
6084 }
6085 }
6086 }
6087 return rc;
6088}
6089
6090
6091/**
6092 * Checks host-state as part of VM-entry.
6093 *
6094 * @returns VBox status code.
6095 * @param pVCpu The cross context virtual CPU structure.
6096 * @param pszInstr The VMX instruction name (for logging purposes).
6097 */
6098static int iemVmxVmentryCheckHostState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6099{
6100 /*
6101 * Host Control Registers and MSRs.
6102 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6103 */
6104 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6105 const char * const pszFailure = "VMFail";
6106
6107 /* CR0 reserved bits. */
6108 {
6109 /* CR0 MB1 bits. */
6110 uint64_t const u64Cr0Fixed0 = iemVmxGetCr0Fixed0(pVCpu, true /* fVmxNonRootMode */);
6111 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6112 { /* likely */ }
6113 else
6114 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6115
6116 /* CR0 MBZ bits. */
6117 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6118 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6119 { /* likely */ }
6120 else
6121 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6122 }
6123
6124 /* CR4 reserved bits. */
6125 {
6126 /* CR4 MB1 bits. */
6127 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6128 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6129 { /* likely */ }
6130 else
6131 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6132
6133 /* CR4 MBZ bits. */
6134 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6135 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6136 { /* likely */ }
6137 else
6138 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6139 }
6140
6141 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6142 {
6143 /* CR3 reserved bits. */
6144 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6145 { /* likely */ }
6146 else
6147 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6148
6149 /* SYSENTER ESP and SYSENTER EIP. */
6150 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6151 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6152 { /* likely */ }
6153 else
6154 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6155 }
6156
6157 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6158 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6159
6160 /* PAT MSR. */
6161 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6162 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6163 { /* likely */ }
6164 else
6165 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6166
6167 /* EFER MSR. */
6168 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6169 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6170 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6171 {
6172 if (!(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6173 { /* likely */ }
6174 else
6175 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6176
6177 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6178 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6179 if ( fHostInLongMode == fHostLma
6180 && fHostInLongMode == fHostLme)
6181 { /* likely */ }
6182 else
6183 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6184 }
6185
6186 /*
6187 * Host Segment and Descriptor-Table Registers.
6188 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6189 */
6190 /* Selector RPL and TI. */
6191 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6192 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6193 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6194 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6195 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6196 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6197 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6198 { /* likely */ }
6199 else
6200 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6201
6202 /* CS and TR selectors cannot be 0. */
6203 if ( pVmcs->HostCs
6204 && pVmcs->HostTr)
6205 { /* likely */ }
6206 else
6207 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6208
6209 /* SS cannot be 0 if 32-bit host. */
6210 if ( fHostInLongMode
6211 || pVmcs->HostSs)
6212 { /* likely */ }
6213 else
6214 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6215
6216 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6217 {
6218 /* FS, GS, GDTR, IDTR, TR base address. */
6219 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6220 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6221 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6222 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6223 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6224 { /* likely */ }
6225 else
6226 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6227 }
6228
6229 /*
6230 * Host address-space size for 64-bit CPUs.
6231 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6232 */
6233 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6234 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6235 {
6236 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6237
6238 /* Logical processor in IA-32e mode. */
6239 if (fCpuInLongMode)
6240 {
6241 if (fHostInLongMode)
6242 {
6243 /* PAE must be set. */
6244 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6245 { /* likely */ }
6246 else
6247 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6248
6249 /* RIP must be canonical. */
6250 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6251 { /* likely */ }
6252 else
6253 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6254 }
6255 else
6256 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6257 }
6258 else
6259 {
6260 /* Logical processor is outside IA-32e mode. */
6261 if ( !fGstInLongMode
6262 && !fHostInLongMode)
6263 {
6264 /* PCIDE should not be set. */
6265 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6266 { /* likely */ }
6267 else
6268 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6269
6270 /* The high 32-bits of RIP MBZ. */
6271 if (!pVmcs->u64HostRip.s.Hi)
6272 { /* likely */ }
6273 else
6274 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6275 }
6276 else
6277 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6278 }
6279 }
6280 else
6281 {
6282 /* Host address-space size for 32-bit CPUs. */
6283 if ( !fGstInLongMode
6284 && !fHostInLongMode)
6285 { /* likely */ }
6286 else
6287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6288 }
6289
6290 NOREF(pszInstr);
6291 NOREF(pszFailure);
6292 return VINF_SUCCESS;
6293}
6294
6295
6296#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6297/**
6298 * Checks the EPT pointer VMCS field as part of VM-entry.
6299 *
6300 * @returns VBox status code.
6301 * @param pVCpu The cross context virtual CPU structure.
6302 * @param uEptPtr The EPT pointer to check.
6303 * @param penmVmxDiag Where to store the diagnostic reason on failure (not
6304 * updated on success). Optional, can be NULL.
6305 */
6306static int iemVmxVmentryCheckEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr, VMXVDIAG *penmVmxDiag) RT_NOEXCEPT
6307{
6308 VMXVDIAG enmVmxDiag;
6309
6310 /* Reserved bits. */
6311 uint8_t const cMaxPhysAddrWidth = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth;
6312 uint64_t const fValidMask = VMX_EPTP_VALID_MASK & ~(UINT64_MAX << cMaxPhysAddrWidth);
6313 if (uEptPtr & fValidMask)
6314 {
6315 /* Memory Type. */
6316 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
6317 uint8_t const fMemType = RT_BF_GET(uEptPtr, VMX_BF_EPTP_MEMTYPE);
6318 if ( ( fMemType == VMX_EPTP_MEMTYPE_WB
6319 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB))
6320 || ( fMemType == VMX_EPTP_MEMTYPE_UC
6321 && RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC)))
6322 {
6323 /*
6324 * Page walk length (PML4).
6325 * Intel used to specify bit 7 of IA32_VMX_EPT_VPID_CAP as page walk length
6326 * of 5 but that seems to be removed from the latest specs. leaving only PML4
6327 * as the maximum supported page-walk level hence we hardcode it as 3 (1 less than 4)
6328 */
6329 Assert(RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4));
6330 if (RT_BF_GET(uEptPtr, VMX_BF_EPTP_PAGE_WALK_LENGTH) == 3)
6331 {
6332 /* Access and dirty bits support in EPT structures. */
6333 if ( !RT_BF_GET(uEptPtr, VMX_BF_EPTP_ACCESS_DIRTY)
6334 || RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY))
6335 return VINF_SUCCESS;
6336
6337 enmVmxDiag = kVmxVDiag_Vmentry_EptpAccessDirty;
6338 }
6339 else
6340 enmVmxDiag = kVmxVDiag_Vmentry_EptpPageWalkLength;
6341 }
6342 else
6343 enmVmxDiag = kVmxVDiag_Vmentry_EptpMemType;
6344 }
6345 else
6346 enmVmxDiag = kVmxVDiag_Vmentry_EptpRsvd;
6347
6348 if (penmVmxDiag)
6349 *penmVmxDiag = enmVmxDiag;
6350 return VERR_VMX_VMENTRY_FAILED;
6351}
6352#endif
6353
6354
6355/**
6356 * Checks VMCS controls fields as part of VM-entry.
6357 *
6358 * @returns VBox status code.
6359 * @param pVCpu The cross context virtual CPU structure.
6360 * @param pszInstr The VMX instruction name (for logging purposes).
6361 *
6362 * @remarks This may update secondary-processor based VM-execution control fields
6363 * in the current VMCS if necessary.
6364 */
6365static int iemVmxVmentryCheckCtls(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6366{
6367 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6368 const char * const pszFailure = "VMFail";
6369 bool const fVmxTrueMsrs = RT_BOOL(pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Basic & VMX_BF_BASIC_TRUE_CTLS_MASK);
6370
6371 /*
6372 * VM-execution controls.
6373 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6374 */
6375 {
6376 /* Pin-based VM-execution controls. */
6377 {
6378 VMXCTLSMSR const PinCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TruePinCtls
6379 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6380 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6381 { /* likely */ }
6382 else
6383 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6384
6385 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6386 { /* likely */ }
6387 else
6388 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6389 }
6390
6391 /* Processor-based VM-execution controls. */
6392 {
6393 VMXCTLSMSR const ProcCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueProcCtls
6394 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6395 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6396 { /* likely */ }
6397 else
6398 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6399
6400 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6401 { /* likely */ }
6402 else
6403 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6404 }
6405
6406 /* Secondary processor-based VM-execution controls. */
6407 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6408 {
6409 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6410 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6411 { /* likely */ }
6412 else
6413 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6414
6415 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6416 { /* likely */ }
6417 else
6418 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6419 }
6420 else if (pVmcs->u32ProcCtls2)
6421 {
6422 /*
6423 * If the "activate secondary controls" is clear, then the secondary processor-based VM-execution controls
6424 * is treated as 0.
6425 *
6426 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6427 *
6428 * Since this is a rather rare occurrence (only observed for a few VM-entries with Microsoft Hyper-V
6429 * enabled Windows Server 2008 R2 guest), it's not worth changing every place that reads this control to
6430 * also check the "activate secondary controls" bit. Instead, we temporarily save the guest programmed
6431 * control here, zero out the value the rest of our code uses and restore the guest programmed value
6432 * on VM-exit.
6433 */
6434 pVmcs->u32RestoreProcCtls2 = pVmcs->u32ProcCtls2;
6435 pVmcs->u32ProcCtls2 = 0;
6436 }
6437
6438 /* CR3-target count. */
6439 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6440 { /* likely */ }
6441 else
6442 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6443
6444 /* I/O bitmaps physical addresses. */
6445 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6446 {
6447 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
6448 if ( !(GCPhysIoBitmapA & X86_PAGE_4K_OFFSET_MASK)
6449 && !(GCPhysIoBitmapA >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6450 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapA))
6451 { /* likely */ }
6452 else
6453 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6454
6455 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
6456 if ( !(GCPhysIoBitmapB & X86_PAGE_4K_OFFSET_MASK)
6457 && !(GCPhysIoBitmapB >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6458 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysIoBitmapB))
6459 { /* likely */ }
6460 else
6461 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6462 }
6463
6464 /* MSR bitmap physical address. */
6465 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6466 {
6467 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6468 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6469 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6470 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6471 { /* likely */ }
6472 else
6473 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6474 }
6475
6476 /* TPR shadow related controls. */
6477 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6478 {
6479 /* Virtual-APIC page physical address. */
6480 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6481 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6482 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6483 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6484 { /* likely */ }
6485 else
6486 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6487
6488 /* TPR threshold bits 31:4 MBZ without virtual-interrupt delivery. */
6489 if ( !(pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)
6490 || (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6491 { /* likely */ }
6492 else
6493 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6494
6495 /* The rest done XXX document */
6496 }
6497 else
6498 {
6499 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6500 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6501 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6502 { /* likely */ }
6503 else
6504 {
6505 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6506 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6507 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6508 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6509 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6510 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6511 }
6512 }
6513
6514 /* NMI exiting and virtual-NMIs. */
6515 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6516 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6517 { /* likely */ }
6518 else
6519 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6520
6521 /* Virtual-NMIs and NMI-window exiting. */
6522 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6523 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6524 { /* likely */ }
6525 else
6526 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6527
6528 /* Virtualize APIC accesses. */
6529 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6530 {
6531 /* APIC-access physical address. */
6532 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6533 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6534 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6535 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6536 { /* likely */ }
6537 else
6538 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6539
6540 /*
6541 * Disallow APIC-access page and virtual-APIC page from being the same address.
6542 * Note! This is not an Intel requirement, but one imposed by our implementation.
6543 */
6544 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6545 * redirecting accesses between the APIC-access page and the virtual-APIC
6546 * page. If any nested hypervisor requires this, we can implement it later. */
6547 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6548 {
6549 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6550 if (GCPhysVirtApic != GCPhysApicAccess)
6551 { /* likely */ }
6552 else
6553 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6554 }
6555 }
6556
6557 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6558 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6559 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6560 { /* likely */ }
6561 else
6562 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6563
6564 /* Virtual-interrupt delivery requires external interrupt exiting. */
6565 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6566 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6567 { /* likely */ }
6568 else
6569 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6570
6571 /* VPID. */
6572 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6573 || pVmcs->u16Vpid != 0)
6574 { /* likely */ }
6575 else
6576 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6577
6578#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6579 /* Extended-Page-Table Pointer (EPTP). */
6580 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
6581 {
6582 VMXVDIAG enmVmxDiag;
6583 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, pVmcs->u64EptPtr.u, &enmVmxDiag);
6584 if (RT_SUCCESS(rc))
6585 { /* likely */ }
6586 else
6587 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmVmxDiag);
6588 }
6589#else
6590 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
6591 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST));
6592#endif
6593 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6594 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6595 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6596 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_XCPT_VE)); /* We don't support EPT-violation #VE yet. */
6597 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING)); /* We don't support TSC-scaling yet. */
6598
6599 /* VMCS shadowing. */
6600 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6601 {
6602 /* VMREAD-bitmap physical address. */
6603 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6604 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6605 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6606 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6607 { /* likely */ }
6608 else
6609 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6610
6611 /* VMWRITE-bitmap physical address. */
6612 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6613 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6614 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6615 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6616 { /* likely */ }
6617 else
6618 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6619 }
6620 }
6621
6622 /*
6623 * VM-exit controls.
6624 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6625 */
6626 {
6627 VMXCTLSMSR const ExitCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueExitCtls
6628 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6629 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6630 { /* likely */ }
6631 else
6632 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6633
6634 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6635 { /* likely */ }
6636 else
6637 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6638
6639 /* Save preemption timer without activating it. */
6640 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6641 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6642 { /* likely */ }
6643 else
6644 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6645
6646 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6647 if (pVmcs->u32ExitMsrStoreCount)
6648 {
6649 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6650 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6651 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6652 { /* likely */ }
6653 else
6654 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6655 }
6656
6657 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6658 if (pVmcs->u32ExitMsrLoadCount)
6659 {
6660 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6661 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6662 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6663 { /* likely */ }
6664 else
6665 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6666 }
6667 }
6668
6669 /*
6670 * VM-entry controls.
6671 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6672 */
6673 {
6674 VMXCTLSMSR const EntryCtls = fVmxTrueMsrs ? pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.TrueEntryCtls
6675 : pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6676 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6677 { /* likely */ }
6678 else
6679 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6680
6681 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6682 { /* likely */ }
6683 else
6684 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6685
6686 /* Event injection. */
6687 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6688 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6689 {
6690 /* Type and vector. */
6691 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6692 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6693 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6694 if ( !uRsvd
6695 && VMXIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6696 && VMXIsEntryIntInfoVectorValid(uVector, uType))
6697 { /* likely */ }
6698 else
6699 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6700
6701 /* Exception error code. */
6702 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6703 {
6704 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6705 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6706 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6707 { /* likely */ }
6708 else
6709 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6710
6711 /* Exceptions that provide an error code. */
6712 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6713 && ( uVector == X86_XCPT_DF
6714 || uVector == X86_XCPT_TS
6715 || uVector == X86_XCPT_NP
6716 || uVector == X86_XCPT_SS
6717 || uVector == X86_XCPT_GP
6718 || uVector == X86_XCPT_PF
6719 || uVector == X86_XCPT_AC))
6720 { /* likely */ }
6721 else
6722 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6723
6724 /* Exception error-code reserved bits. */
6725 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6726 { /* likely */ }
6727 else
6728 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6729
6730 /* Injecting a software interrupt, software exception or privileged software exception. */
6731 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6732 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6733 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6734 {
6735 /* Instruction length must be in the range 0-15. */
6736 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6737 { /* likely */ }
6738 else
6739 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6740
6741 /* However, instruction length of 0 is allowed only when its CPU feature is present. */
6742 if ( pVmcs->u32EntryInstrLen != 0
6743 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6744 { /* likely */ }
6745 else
6746 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6747 }
6748 }
6749 }
6750
6751 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6752 if (pVmcs->u32EntryMsrLoadCount)
6753 {
6754 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6755 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6756 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6757 { /* likely */ }
6758 else
6759 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6760 }
6761
6762 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6763 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6764 }
6765
6766 NOREF(pszInstr);
6767 NOREF(pszFailure);
6768 return VINF_SUCCESS;
6769}
6770
6771
6772/**
6773 * Loads the guest control registers, debug register and some MSRs as part of
6774 * VM-entry.
6775 *
6776 * @param pVCpu The cross context virtual CPU structure.
6777 */
6778static void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPUCC pVCpu) RT_NOEXCEPT
6779{
6780 /*
6781 * Load guest control registers, debug registers and MSRs.
6782 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6783 */
6784 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6785
6786 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6787 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_GUEST_CR0_IGNORE_MASK)
6788 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_GUEST_CR0_IGNORE_MASK);
6789 pVCpu->cpum.GstCtx.cr0 = uGstCr0;
6790 pVCpu->cpum.GstCtx.cr4 = pVmcs->u64GuestCr4.u;
6791 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6792
6793 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6794 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_GUEST_DR7_MBZ_MASK) | VMX_ENTRY_GUEST_DR7_MB1_MASK;
6795
6796 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6797 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6798 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6799
6800 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6801 {
6802 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6803
6804 /* EFER MSR. */
6805 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6806 {
6807 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6808 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6809 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6810 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6811 if (fGstInLongMode)
6812 {
6813 /* If the nested-guest is in long mode, LMA and LME are both set. */
6814 Assert(fGstPaging);
6815 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6816 }
6817 else
6818 {
6819 /*
6820 * If the nested-guest is outside long mode:
6821 * - With paging: LMA is cleared, LME is cleared.
6822 * - Without paging: LMA is cleared, LME is left unmodified.
6823 */
6824 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6825 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6826 }
6827 }
6828 /* else: see below. */
6829 }
6830
6831 /* PAT MSR. */
6832 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6833 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6834
6835 /* EFER MSR. */
6836 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6837 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6838
6839 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6840 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6841
6842 /* We don't support IA32_BNDCFGS MSR yet. */
6843 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6844
6845 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6846}
6847
6848
6849/**
6850 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6851 *
6852 * @param pVCpu The cross context virtual CPU structure.
6853 */
6854static void iemVmxVmentryLoadGuestSegRegs(PVMCPUCC pVCpu) RT_NOEXCEPT
6855{
6856 /*
6857 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6858 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6859 */
6860 /* CS, SS, ES, DS, FS, GS. */
6861 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6862 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6863 {
6864 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6865 CPUMSELREG VmcsSelReg;
6866 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6867 AssertRC(rc); NOREF(rc);
6868 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6869 {
6870 pGstSelReg->Sel = VmcsSelReg.Sel;
6871 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6872 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6873 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6874 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6875 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6876 }
6877 else
6878 {
6879 pGstSelReg->Sel = VmcsSelReg.Sel;
6880 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6881 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6882 switch (iSegReg)
6883 {
6884 case X86_SREG_CS:
6885 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6886 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6887 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6888 break;
6889
6890 case X86_SREG_SS:
6891 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6892 pGstSelReg->u32Limit = 0;
6893 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6894 break;
6895
6896 case X86_SREG_ES:
6897 case X86_SREG_DS:
6898 pGstSelReg->u64Base = 0;
6899 pGstSelReg->u32Limit = 0;
6900 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6901 break;
6902
6903 case X86_SREG_FS:
6904 case X86_SREG_GS:
6905 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6906 pGstSelReg->u32Limit = 0;
6907 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6908 break;
6909 }
6910 Assert(pGstSelReg->Attr.n.u1Unusable);
6911 }
6912 }
6913
6914 /* LDTR. */
6915 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6916 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6917 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6918 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6919 {
6920 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6921 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6922 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6923 }
6924 else
6925 {
6926 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6927 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6928 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6929 }
6930
6931 /* TR. */
6932 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6933 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6934 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6935 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6936 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6937 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6938 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6939
6940 /* GDTR. */
6941 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6942 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6943
6944 /* IDTR. */
6945 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6946 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6947}
6948
6949
6950/**
6951 * Loads the guest MSRs from the VM-entry MSR-load area as part of VM-entry.
6952 *
6953 * @returns VBox status code.
6954 * @param pVCpu The cross context virtual CPU structure.
6955 * @param pszInstr The VMX instruction name (for logging purposes).
6956 */
6957static int iemVmxVmentryLoadGuestAutoMsrs(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
6958{
6959 /*
6960 * Load guest MSRs.
6961 * See Intel spec. 26.4 "Loading MSRs".
6962 */
6963 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
6964 const char *const pszFailure = "VM-exit";
6965
6966 /*
6967 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6968 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6969 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6970 */
6971 uint32_t const cMsrs = RT_MIN(pVmcs->u32EntryMsrLoadCount, RT_ELEMENTS(pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea));
6972 if (!cMsrs)
6973 return VINF_SUCCESS;
6974
6975 /*
6976 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6977 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6978 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6979 */
6980 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6981 if (fIsMsrCountValid)
6982 { /* likely */ }
6983 else
6984 {
6985 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6986 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6987 }
6988
6989 RTGCPHYS const GCPhysVmEntryMsrLoadArea = pVmcs->u64AddrEntryMsrLoad.u;
6990 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0],
6991 GCPhysVmEntryMsrLoadArea, cMsrs * sizeof(VMXAUTOMSR));
6992 if (RT_SUCCESS(rc))
6993 {
6994 PCVMXAUTOMSR pMsr = &pVCpu->cpum.GstCtx.hwvirt.vmx.aEntryMsrLoadArea[0];
6995 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
6996 {
6997 if ( !pMsr->u32Reserved
6998 && pMsr->u32Msr != MSR_K8_FS_BASE
6999 && pMsr->u32Msr != MSR_K8_GS_BASE
7000 && pMsr->u32Msr != MSR_K6_EFER
7001 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7002 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7003 {
7004 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7005 if (rcStrict == VINF_SUCCESS)
7006 continue;
7007
7008 /*
7009 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7010 * If any nested hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7011 * recording the MSR index in the Exit qualification (as per the Intel spec.) and indicated
7012 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7013 * MSR in ring-0 if possible, or come up with a better, generic solution.
7014 */
7015 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7016 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7017 ? kVmxVDiag_Vmentry_MsrLoadRing3
7018 : kVmxVDiag_Vmentry_MsrLoad;
7019 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7020 }
7021 else
7022 {
7023 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7024 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7025 }
7026 }
7027 }
7028 else
7029 {
7030 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysVmEntryMsrLoadArea, rc));
7031 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7032 }
7033
7034 NOREF(pszInstr);
7035 NOREF(pszFailure);
7036 return VINF_SUCCESS;
7037}
7038
7039
7040/**
7041 * Loads the guest-state non-register state as part of VM-entry.
7042 *
7043 * @returns VBox status code.
7044 * @param pVCpu The cross context virtual CPU structure.
7045 * @param pszInstr The VMX instruction name (for logging purposes).
7046 *
7047 * @remarks This must be called only after loading the nested-guest register state
7048 * (especially nested-guest RIP).
7049 */
7050static int iemVmxVmentryLoadGuestNonRegState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7051{
7052 /*
7053 * Load guest non-register state.
7054 * See Intel spec. 26.6 "Special Features of VM Entry"
7055 */
7056 const char *const pszFailure = "VM-exit";
7057 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7058
7059 /*
7060 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7061 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7062 *
7063 * See Intel spec. 26.6.1 "Interruptibility State".
7064 */
7065 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7066 if ( !fEntryVectoring
7067 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7068 CPUMSetInInterruptShadowEx(&pVCpu->cpum.GstCtx, pVmcs->u64GuestRip.u);
7069 else
7070 Assert(!CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx));
7071
7072 /* NMI blocking. */
7073 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7074 {
7075 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
7076 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = true;
7077 else
7078 {
7079 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7080 CPUMSetInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx);
7081 }
7082 }
7083 else
7084 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
7085
7086 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7087
7088 /*
7089 * Set PGM's copy of the EPT pointer.
7090 * The EPTP has already been validated while checking guest state.
7091 *
7092 * It is important to do this prior to mapping PAE PDPTEs (below).
7093 */
7094 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7095 PGMSetGuestEptPtr(pVCpu, pVmcs->u64EptPtr.u);
7096
7097 /*
7098 * Load the guest's PAE PDPTEs.
7099 */
7100 if (!iemVmxVmcsIsGuestPaePagingEnabled(pVmcs))
7101 {
7102 /*
7103 * When PAE paging is not used we clear the PAE PDPTEs for safety
7104 * in case we might be switching from a PAE host to a non-PAE guest.
7105 */
7106 pVCpu->cpum.GstCtx.aPaePdpes[0].u = 0;
7107 pVCpu->cpum.GstCtx.aPaePdpes[1].u = 0;
7108 pVCpu->cpum.GstCtx.aPaePdpes[2].u = 0;
7109 pVCpu->cpum.GstCtx.aPaePdpes[3].u = 0;
7110 }
7111 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)
7112 {
7113 /*
7114 * With EPT and the nested-guest using PAE paging, we've already validated the PAE PDPTEs
7115 * while checking the guest state. We can load them into the nested-guest CPU state now.
7116 * They'll later be used while mapping CR3 and the PAE PDPTEs.
7117 */
7118 pVCpu->cpum.GstCtx.aPaePdpes[0].u = pVmcs->u64GuestPdpte0.u;
7119 pVCpu->cpum.GstCtx.aPaePdpes[1].u = pVmcs->u64GuestPdpte1.u;
7120 pVCpu->cpum.GstCtx.aPaePdpes[2].u = pVmcs->u64GuestPdpte2.u;
7121 pVCpu->cpum.GstCtx.aPaePdpes[3].u = pVmcs->u64GuestPdpte3.u;
7122 }
7123 else
7124 {
7125 /*
7126 * Without EPT and the nested-guest using PAE paging, we must load the PAE PDPTEs
7127 * referenced by CR3. This involves loading (and mapping) CR3 and validating them now.
7128 */
7129 int const rc = PGMGstMapPaePdpesAtCr3(pVCpu, pVmcs->u64GuestCr3.u);
7130 if (RT_SUCCESS(rc))
7131 { /* likely */ }
7132 else
7133 {
7134 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
7135 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpte);
7136 }
7137 }
7138
7139 /* VPID is irrelevant. We don't support VPID yet. */
7140
7141 /* Clear address-range monitoring. */
7142 EMMonitorWaitClear(pVCpu);
7143
7144 return VINF_SUCCESS;
7145}
7146
7147
7148/**
7149 * Loads the guest VMCS referenced state (such as MSR bitmaps, I/O bitmaps etc).
7150 *
7151 * @param pVCpu The cross context virtual CPU structure.
7152 * @param pszInstr The VMX instruction name (for logging purposes).
7153 *
7154 * @remarks This assumes various VMCS related data structure pointers have already
7155 * been verified prior to calling this function.
7156 */
7157static int iemVmxVmentryLoadGuestVmcsRefState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7158{
7159 const char *const pszFailure = "VM-exit";
7160 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7161
7162 /*
7163 * Virtualize APIC accesses.
7164 */
7165 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7166 {
7167 /* APIC-access physical address. */
7168 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
7169
7170 /*
7171 * Register the handler for the APIC-access page.
7172 *
7173 * We don't deregister the APIC-access page handler during the VM-exit as a different
7174 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
7175 *
7176 * We leave the page registered until the first access that happens outside VMX non-root
7177 * mode. Guest software is allowed to access structures such as the APIC-access page
7178 * only when no logical processor with a current VMCS references it in VMX non-root mode,
7179 * otherwise it can lead to unpredictable behavior including guest triple-faults.
7180 *
7181 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7182 */
7183 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7184 int rc = PGMHandlerPhysicalRegisterVmxApicAccessPage(pVM, GCPhysApicAccess, pVM->iem.s.hVmxApicAccessPage);
7185 if (RT_SUCCESS(rc))
7186 { /* likely */ }
7187 else
7188 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
7189 }
7190
7191 /*
7192 * VMCS shadowing.
7193 */
7194 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7195 {
7196 /* Read the VMREAD-bitmap. */
7197 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
7198 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap[0],
7199 GCPhysVmreadBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmreadBitmap));
7200 if (RT_SUCCESS(rc))
7201 { /* likely */ }
7202 else
7203 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
7204
7205 /* Read the VMWRITE-bitmap. */
7206 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmwriteBitmap.u;
7207 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap[0],
7208 GCPhysVmwriteBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abVmwriteBitmap));
7209 if (RT_SUCCESS(rc))
7210 { /* likely */ }
7211 else
7212 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
7213 }
7214
7215 /*
7216 * I/O bitmaps.
7217 */
7218 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
7219 {
7220 /* Read the IO bitmap A. */
7221 RTGCPHYS const GCPhysIoBitmapA = pVmcs->u64AddrIoBitmapA.u;
7222 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[0],
7223 GCPhysIoBitmapA, VMX_V_IO_BITMAP_A_SIZE);
7224 if (RT_SUCCESS(rc))
7225 { /* likely */ }
7226 else
7227 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys);
7228
7229 /* Read the IO bitmap B. */
7230 RTGCPHYS const GCPhysIoBitmapB = pVmcs->u64AddrIoBitmapB.u;
7231 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abIoBitmap[VMX_V_IO_BITMAP_A_SIZE],
7232 GCPhysIoBitmapB, VMX_V_IO_BITMAP_B_SIZE);
7233 if (RT_SUCCESS(rc))
7234 { /* likely */ }
7235 else
7236 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys);
7237 }
7238
7239 /*
7240 * TPR shadow and Virtual-APIC page.
7241 */
7242 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7243 {
7244 /* Verify TPR threshold and VTPR when both virtualize-APIC accesses and virtual-interrupt delivery aren't used. */
7245 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
7246 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
7247 {
7248 /* Read the VTPR from the virtual-APIC page. */
7249 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
7250 uint8_t u8VTpr;
7251 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &u8VTpr, GCPhysVirtApic + XAPIC_OFF_TPR, sizeof(u8VTpr));
7252 if (RT_SUCCESS(rc))
7253 { /* likely */ }
7254 else
7255 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
7256
7257 /* Bits 3:0 of the TPR-threshold must not be greater than bits 7:4 of VTPR. */
7258 if ((uint8_t)RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) <= (u8VTpr & 0xf0))
7259 { /* likely */ }
7260 else
7261 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
7262 }
7263 }
7264
7265 /*
7266 * VMCS link pointer.
7267 */
7268 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
7269 {
7270 /* Read the VMCS-link pointer from guest memory. */
7271 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
7272 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs,
7273 GCPhysShadowVmcs, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs));
7274 if (RT_SUCCESS(rc))
7275 { /* likely */ }
7276 else
7277 {
7278 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7279 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
7280 }
7281
7282 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
7283 if (pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
7284 { /* likely */ }
7285 else
7286 {
7287 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7288 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
7289 }
7290
7291 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
7292 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7293 || pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs.u32VmcsRevId.n.fIsShadowVmcs)
7294 { /* likely */ }
7295 else
7296 {
7297 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
7298 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
7299 }
7300
7301 /* Update our cache of the guest physical address of the shadow VMCS. */
7302 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
7303 }
7304
7305 /*
7306 * MSR bitmap.
7307 */
7308 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7309 {
7310 /* Read the MSR bitmap. */
7311 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
7312 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap[0],
7313 GCPhysMsrBitmap, sizeof(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap));
7314 if (RT_SUCCESS(rc))
7315 { /* likely */ }
7316 else
7317 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
7318 }
7319
7320 NOREF(pszFailure);
7321 NOREF(pszInstr);
7322 return VINF_SUCCESS;
7323}
7324
7325
7326/**
7327 * Loads the guest-state as part of VM-entry.
7328 *
7329 * @returns VBox status code.
7330 * @param pVCpu The cross context virtual CPU structure.
7331 * @param pszInstr The VMX instruction name (for logging purposes).
7332 *
7333 * @remarks This must be done after all the necessary steps prior to loading of
7334 * guest-state (e.g. checking various VMCS state).
7335 */
7336static int iemVmxVmentryLoadGuestState(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7337{
7338 /* Load guest control registers, MSRs (that are directly part of the VMCS). */
7339 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7340
7341 /* Load guest segment registers. */
7342 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7343
7344 /*
7345 * Load guest RIP, RSP and RFLAGS.
7346 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7347 */
7348 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7349 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7350 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7351 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7352
7353 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7354 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7355 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7356
7357 /* Load guest non-register state (such as interrupt shadows, NMI blocking etc). */
7358 int rc = iemVmxVmentryLoadGuestNonRegState(pVCpu, pszInstr);
7359 if (rc == VINF_SUCCESS)
7360 { /* likely */ }
7361 else
7362 return rc;
7363
7364 /* Load VMX related structures and state referenced by the VMCS. */
7365 rc = iemVmxVmentryLoadGuestVmcsRefState(pVCpu, pszInstr);
7366 if (rc == VINF_SUCCESS)
7367 { /* likely */ }
7368 else
7369 return rc;
7370
7371 NOREF(pszInstr);
7372 return VINF_SUCCESS;
7373}
7374
7375
7376/**
7377 * Returns whether there are is a pending debug exception on VM-entry.
7378 *
7379 * @param pVCpu The cross context virtual CPU structure.
7380 * @param pszInstr The VMX instruction name (for logging purposes).
7381 */
7382static bool iemVmxVmentryIsPendingDebugXcpt(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7383{
7384 /*
7385 * Pending debug exceptions.
7386 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7387 */
7388 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7389 Assert(pVmcs);
7390
7391 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpts.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7392 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7393 if (fPendingDbgXcpt)
7394 {
7395 uint8_t uEntryIntInfoType;
7396 bool const fEntryVectoring = VMXIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7397 if (fEntryVectoring)
7398 {
7399 switch (uEntryIntInfoType)
7400 {
7401 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7402 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7403 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7404 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7405 fPendingDbgXcpt = false;
7406 break;
7407
7408 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7409 {
7410 /*
7411 * Whether the pending debug exception for software exceptions other than
7412 * #BP and #OF is delivered after injecting the exception or is discard
7413 * is CPU implementation specific. We will discard them (easier).
7414 */
7415 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7416 if ( uVector != X86_XCPT_BP
7417 && uVector != X86_XCPT_OF)
7418 fPendingDbgXcpt = false;
7419 RT_FALL_THRU();
7420 }
7421 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7422 {
7423 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7424 fPendingDbgXcpt = false;
7425 break;
7426 }
7427 }
7428 }
7429 else
7430 {
7431 /*
7432 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7433 * pending debug exception is held pending or is discarded is CPU implementation
7434 * specific. We will discard them (easier).
7435 */
7436 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7437 fPendingDbgXcpt = false;
7438
7439 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7440 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7441 fPendingDbgXcpt = false;
7442 }
7443 }
7444
7445 NOREF(pszInstr);
7446 return fPendingDbgXcpt;
7447}
7448
7449
7450/**
7451 * Set up the monitor-trap flag (MTF).
7452 *
7453 * @param pVCpu The cross context virtual CPU structure.
7454 * @param pszInstr The VMX instruction name (for logging purposes).
7455 */
7456static void iemVmxVmentrySetupMtf(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7457{
7458 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7459 Assert(pVmcs);
7460 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7461 {
7462 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7463 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7464 }
7465 else
7466 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7467 NOREF(pszInstr);
7468}
7469
7470
7471/**
7472 * Sets up NMI-window exiting.
7473 *
7474 * @param pVCpu The cross context virtual CPU structure.
7475 * @param pszInstr The VMX instruction name (for logging purposes).
7476 */
7477static void iemVmxVmentrySetupNmiWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7478{
7479 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7480 Assert(pVmcs);
7481 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
7482 {
7483 Assert(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI);
7484 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW);
7485 Log(("%s: NMI-window set on VM-entry\n", pszInstr));
7486 }
7487 else
7488 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_NMI_WINDOW));
7489 NOREF(pszInstr);
7490}
7491
7492
7493/**
7494 * Sets up interrupt-window exiting.
7495 *
7496 * @param pVCpu The cross context virtual CPU structure.
7497 * @param pszInstr The VMX instruction name (for logging purposes).
7498 */
7499static void iemVmxVmentrySetupIntWindow(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7500{
7501 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7502 Assert(pVmcs);
7503 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
7504 {
7505 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW);
7506 Log(("%s: Interrupt-window set on VM-entry\n", pszInstr));
7507 }
7508 else
7509 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_INT_WINDOW));
7510 NOREF(pszInstr);
7511}
7512
7513
7514/**
7515 * Set up the VMX-preemption timer.
7516 *
7517 * @param pVCpu The cross context virtual CPU structure.
7518 * @param pszInstr The VMX instruction name (for logging purposes).
7519 */
7520static void iemVmxVmentrySetupPreemptTimer(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7521{
7522 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7523 Assert(pVmcs);
7524 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7525 {
7526 /*
7527 * If the timer is 0, we must cause a VM-exit before executing the first
7528 * nested-guest instruction. So we can flag as though the timer has already
7529 * expired and we will check and cause a VM-exit at the right priority elsewhere
7530 * in the code.
7531 */
7532 uint64_t uEntryTick;
7533 uint32_t const uPreemptTimer = pVmcs->u32PreemptTimer;
7534 if (uPreemptTimer)
7535 {
7536 int rc = CPUMStartGuestVmxPremptTimer(pVCpu, uPreemptTimer, VMX_V_PREEMPT_TIMER_SHIFT, &uEntryTick);
7537 AssertRC(rc);
7538 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uEntryTick));
7539 }
7540 else
7541 {
7542 uEntryTick = TMCpuTickGetNoCheck(pVCpu);
7543 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7544 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64 to expire immediately!\n", pszInstr, uEntryTick));
7545 }
7546
7547 pVCpu->cpum.GstCtx.hwvirt.vmx.uEntryTick = uEntryTick;
7548 }
7549 else
7550 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7551
7552 NOREF(pszInstr);
7553}
7554
7555
7556/**
7557 * Injects an event using TRPM given a VM-entry interruption info and related
7558 * fields.
7559 *
7560 * @param pVCpu The cross context virtual CPU structure.
7561 * @param pszInstr The VMX instruction name (for logging purposes).
7562 * @param uEntryIntInfo The VM-entry interruption info.
7563 * @param uErrCode The error code associated with the event if any.
7564 * @param cbInstr The VM-entry instruction length (for software
7565 * interrupts and software exceptions). Pass 0
7566 * otherwise.
7567 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7568 */
7569static void iemVmxVmentryInjectTrpmEvent(PVMCPUCC pVCpu, const char *pszInstr, uint32_t uEntryIntInfo, uint32_t uErrCode,
7570 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress) RT_NOEXCEPT
7571{
7572 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7573
7574 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7575 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7576 TRPMEVENT const enmTrpmEvent = HMVmxEventTypeToTrpmEventType(uEntryIntInfo);
7577
7578 Assert(uType != VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT);
7579
7580 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrpmEvent);
7581 AssertRC(rc);
7582 Log(("%s: Injecting: vector=%#x type=%#x (%s)\n", pszInstr, uVector, uType, VMXGetEntryIntInfoTypeDesc(uType)));
7583
7584 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo))
7585 {
7586 TRPMSetErrorCode(pVCpu, uErrCode);
7587 Log(("%s: Injecting: err_code=%#x\n", pszInstr, uErrCode));
7588 }
7589
7590 if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(uEntryIntInfo))
7591 {
7592 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7593 Log(("%s: Injecting: fault_addr=%RGp\n", pszInstr, GCPtrFaultAddress));
7594 }
7595 else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7596 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7597 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7598 {
7599 TRPMSetInstrLength(pVCpu, cbInstr);
7600 Log(("%s: Injecting: instr_len=%u\n", pszInstr, cbInstr));
7601 }
7602
7603 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7604 {
7605 TRPMSetTrapDueToIcebp(pVCpu);
7606 Log(("%s: Injecting: icebp\n", pszInstr));
7607 }
7608
7609 NOREF(pszInstr);
7610}
7611
7612
7613/**
7614 * Performs event injection (if any) as part of VM-entry.
7615 *
7616 * @param pVCpu The cross context virtual CPU structure.
7617 * @param pszInstr The VMX instruction name (for logging purposes).
7618 */
7619static void iemVmxVmentryInjectEvent(PVMCPUCC pVCpu, const char *pszInstr) RT_NOEXCEPT
7620{
7621 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7622
7623 /*
7624 * Inject events.
7625 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7626 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7627 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7628 * the actually delivery of this event.
7629 *
7630 * See Intel spec. 26.5 "Event Injection".
7631 */
7632 uint32_t const uEntryIntInfo = pVmcs->u32EntryIntInfo;
7633 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7634
7635 CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, !fEntryIntInfoValid);
7636 if (fEntryIntInfoValid)
7637 {
7638 if (VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7639 {
7640 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7641 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7642 }
7643 else
7644 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7645 pVCpu->cpum.GstCtx.cr2);
7646
7647 /*
7648 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
7649 *
7650 * However, we do it here on VM-entry as well because while it isn't visible to guest
7651 * software until VM-exit, when and if HM looks at the VMCS to continue nested-guest
7652 * execution using hardware-assisted VMX, it will not try to inject the event again.
7653 *
7654 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7655 */
7656 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
7657 }
7658 else
7659 {
7660 /*
7661 * Inject any pending guest debug exception.
7662 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7663 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7664 */
7665 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7666 if (fPendingDbgXcpt)
7667 {
7668 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7669 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7670 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7671 iemVmxVmentryInjectTrpmEvent(pVCpu, pszInstr, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7672 0 /* GCPtrFaultAddress */);
7673 }
7674 }
7675
7676 NOREF(pszInstr);
7677}
7678
7679
7680/**
7681 * Initializes all read-only VMCS fields as part of VM-entry.
7682 *
7683 * @param pVCpu The cross context virtual CPU structure.
7684 */
7685static void iemVmxVmentryInitReadOnlyFields(PVMCPUCC pVCpu) RT_NOEXCEPT
7686{
7687 /*
7688 * Any VMCS field which we do not establish on every VM-exit but may potentially
7689 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7690 * specified to be undefined, needs to be initialized here.
7691 *
7692 * Thus, it is especially important to clear the Exit qualification field
7693 * since it must be zero for VM-exits where it is not used. Similarly, the
7694 * VM-exit interruption information field's valid bit needs to be cleared for
7695 * the same reasons.
7696 */
7697 PVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7698 Assert(pVmcs);
7699
7700 /* 16-bit (none currently). */
7701 /* 32-bit. */
7702 pVmcs->u32RoVmInstrError = 0;
7703 pVmcs->u32RoExitReason = 0;
7704 pVmcs->u32RoExitIntInfo = 0;
7705 pVmcs->u32RoExitIntErrCode = 0;
7706 pVmcs->u32RoIdtVectoringInfo = 0;
7707 pVmcs->u32RoIdtVectoringErrCode = 0;
7708 pVmcs->u32RoExitInstrLen = 0;
7709 pVmcs->u32RoExitInstrInfo = 0;
7710
7711 /* 64-bit. */
7712 pVmcs->u64RoGuestPhysAddr.u = 0;
7713
7714 /* Natural-width. */
7715 pVmcs->u64RoExitQual.u = 0;
7716 pVmcs->u64RoIoRcx.u = 0;
7717 pVmcs->u64RoIoRsi.u = 0;
7718 pVmcs->u64RoIoRdi.u = 0;
7719 pVmcs->u64RoIoRip.u = 0;
7720 pVmcs->u64RoGuestLinearAddr.u = 0;
7721}
7722
7723
7724/**
7725 * VMLAUNCH/VMRESUME instruction execution worker.
7726 *
7727 * @returns Strict VBox status code.
7728 * @param pVCpu The cross context virtual CPU structure.
7729 * @param cbInstr The instruction length in bytes.
7730 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7731 * VMXINSTRID_VMRESUME).
7732 *
7733 * @remarks Common VMX instruction checks are already expected to by the caller,
7734 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7735 */
7736static VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId) RT_NOEXCEPT
7737{
7738# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7739 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7740 return VINF_EM_RAW_EMULATE_INSTR;
7741# else
7742 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7743 || uInstrId == VMXINSTRID_VMRESUME);
7744 const char * const pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7745
7746 /* Nested-guest intercept. */
7747 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7748 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7749
7750 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7751
7752 /*
7753 * Basic VM-entry checks.
7754 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7755 * The checks following that do not have to follow a specific order.
7756 *
7757 * See Intel spec. 26.1 "Basic VM-entry Checks".
7758 */
7759
7760 /* CPL. */
7761 if (pVCpu->iem.s.uCpl == 0)
7762 { /* likely */ }
7763 else
7764 {
7765 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7766 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7767 return iemRaiseGeneralProtectionFault0(pVCpu);
7768 }
7769
7770 /* Current VMCS valid. */
7771 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7772 { /* likely */ }
7773 else
7774 {
7775 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7776 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7777 iemVmxVmFailInvalid(pVCpu);
7778 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7779 }
7780
7781 /* Current VMCS is not a shadow VMCS. */
7782 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32VmcsRevId.n.fIsShadowVmcs)
7783 { /* likely */ }
7784 else
7785 {
7786 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7787 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7788 iemVmxVmFailInvalid(pVCpu);
7789 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7790 }
7791
7792 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7793 * use block-by-STI here which is not quite correct. */
7794 if (!CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx))
7795 { /* likely */ }
7796 else
7797 {
7798 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7799 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7800 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7801 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7802 }
7803
7804 if (uInstrId == VMXINSTRID_VMLAUNCH)
7805 {
7806 /* VMLAUNCH with non-clear VMCS. */
7807 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR)
7808 { /* likely */ }
7809 else
7810 {
7811 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7812 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7813 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7814 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7815 }
7816 }
7817 else
7818 {
7819 /* VMRESUME with non-launched VMCS. */
7820 if (pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState == VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
7821 { /* likely */ }
7822 else
7823 {
7824 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7825 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7826 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7827 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7828 }
7829 }
7830
7831 /*
7832 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7833 * while entering VMX non-root mode. We do some of this while checking VM-execution
7834 * controls. The nested hypervisor should not make assumptions and cannot expect
7835 * predictable behavior if changes to these structures are made in guest memory while
7836 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7837 * modify them anyway as we cache them in host memory.
7838 *
7839 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7840 */
7841 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7842
7843 int rc = iemVmxVmentryCheckCtls(pVCpu, pszInstr);
7844 if (RT_SUCCESS(rc))
7845 {
7846 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7847 if (RT_SUCCESS(rc))
7848 {
7849 /*
7850 * Initialize read-only VMCS fields before VM-entry since we don't update all of them
7851 * for every VM-exit. This needs to be done before invoking a VM-exit (even those
7852 * ones that may occur during VM-entry below).
7853 */
7854 iemVmxVmentryInitReadOnlyFields(pVCpu);
7855
7856 /*
7857 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7858 * So we save the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7859 * VM-exit when required.
7860 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7861 */
7862 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7863
7864 PVMXVVMCS pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
7865 Assert(pVmcs);
7866
7867 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7868 if (RT_SUCCESS(rc))
7869 {
7870 /*
7871 * We've now entered nested-guest execution.
7872 *
7873 * It is important do this prior to loading the guest state because
7874 * as part of loading the guest state, PGM (and perhaps other components
7875 * in the future) relies on detecting whether VMX non-root mode has been
7876 * entered.
7877 */
7878 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7879
7880 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7881 if (RT_SUCCESS(rc))
7882 {
7883 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7884 if (RT_SUCCESS(rc))
7885 {
7886 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7887
7888 /* VMLAUNCH instruction must update the VMCS launch state. */
7889 if (uInstrId == VMXINSTRID_VMLAUNCH)
7890 pVmcs->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_LAUNCHED;
7891
7892 /* Perform the VMX transition (PGM updates). */
7893 VBOXSTRICTRC rcStrict = iemVmxTransition(pVCpu);
7894 if (rcStrict == VINF_SUCCESS)
7895 { /* likely */ }
7896 else if (RT_SUCCESS(rcStrict))
7897 {
7898 Log3(("%s: iemVmxTransition returns %Rrc -> Setting passup status\n", pszInstr,
7899 VBOXSTRICTRC_VAL(rcStrict)));
7900 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7901 }
7902 else
7903 {
7904 Log3(("%s: iemVmxTransition failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7905 return rcStrict;
7906 }
7907
7908 /* Paranoia. */
7909 Assert(rcStrict == VINF_SUCCESS);
7910
7911 /*
7912 * The priority of potential VM-exits during VM-entry is important.
7913 * The priorities of VM-exits and events are listed from highest
7914 * to lowest as follows:
7915 *
7916 * 1. Event injection.
7917 * 2. Trap on task-switch (T flag set in TSS).
7918 * 3. TPR below threshold / APIC-write.
7919 * 4. SMI, INIT.
7920 * 5. MTF exit.
7921 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7922 * 7. VMX-preemption timer.
7923 * 9. NMI-window exit.
7924 * 10. NMI injection.
7925 * 11. Interrupt-window exit.
7926 * 12. Virtual-interrupt injection.
7927 * 13. Interrupt injection.
7928 * 14. Process next instruction (fetch, decode, execute).
7929 */
7930
7931 /* Setup VMX-preemption timer. */
7932 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7933
7934 /* Setup monitor-trap flag. */
7935 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7936
7937 /* Setup NMI-window exiting. */
7938 iemVmxVmentrySetupNmiWindow(pVCpu, pszInstr);
7939
7940 /* Setup interrupt-window exiting. */
7941 iemVmxVmentrySetupIntWindow(pVCpu, pszInstr);
7942
7943 /*
7944 * Inject any event that the nested hypervisor wants to inject.
7945 * Note! We cannot immediately perform the event injection here as we may have
7946 * pending PGM operations to perform due to switching page tables and/or
7947 * mode.
7948 */
7949 iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7950
7951# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
7952 /* Reschedule to IEM-only execution of the nested-guest. */
7953 LogFlow(("%s: Enabling IEM-only EM execution policy!\n", pszInstr));
7954 int rcSched = EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
7955 if (rcSched != VINF_SUCCESS)
7956 iemSetPassUpStatus(pVCpu, rcSched);
7957# endif
7958
7959 /* Finally, done. */
7960 Log2(("vmentry: %s: cs:rip=%04x:%08RX64 cr0=%#RX64 (%#RX64) cr4=%#RX64 (%#RX64) efer=%#RX64 (%#RX64)\n",
7961 pszInstr, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0,
7962 pVmcs->u64Cr0ReadShadow.u, pVCpu->cpum.GstCtx.cr4, pVmcs->u64Cr4ReadShadow.u,
7963 pVCpu->cpum.GstCtx.msrEFER, pVmcs->u64GuestEferMsr.u));
7964 return VINF_SUCCESS;
7965 }
7966 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7967 }
7968 }
7969 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED, pVmcs->u64RoExitQual.u);
7970 }
7971
7972 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7973 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7974 }
7975
7976 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7977 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
7978# endif
7979}
7980
7981
7982/**
7983 * Interface for HM and EM to emulate the VMLAUNCH/VMRESUME instruction.
7984 *
7985 * @returns Strict VBox status code.
7986 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
7987 * @param cbInstr The instruction length in bytes.
7988 * @param uInstrId The instruction ID (VMXINSTRID_VMLAUNCH or
7989 * VMXINSTRID_VMRESUME).
7990 * @thread EMT(pVCpu)
7991 */
7992VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7993{
7994 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
7995 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
7996
7997 iemInitExec(pVCpu, false /*fBypassHandlers*/);
7998 VBOXSTRICTRC rcStrict = iemVmxVmlaunchVmresume(pVCpu, cbInstr, uInstrId);
7999 Assert(!pVCpu->iem.s.cActiveMappings);
8000 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8001}
8002
8003
8004/**
8005 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
8006 * (causes a VM-exit) or not.
8007 *
8008 * @returns @c true if the instruction is intercepted, @c false otherwise.
8009 * @param pVCpu The cross context virtual CPU structure.
8010 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
8011 * VMX_EXIT_WRMSR).
8012 * @param idMsr The MSR.
8013 */
8014bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT
8015{
8016 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
8017 Assert( uExitReason == VMX_EXIT_RDMSR
8018 || uExitReason == VMX_EXIT_WRMSR);
8019
8020 /* Consult the MSR bitmap if the feature is supported. */
8021 PCVMXVVMCS const pVmcs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs;
8022 Assert(pVmcs);
8023 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
8024 {
8025 uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.abMsrBitmap, idMsr);
8026 if (uExitReason == VMX_EXIT_RDMSR)
8027 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_RD);
8028 return RT_BOOL(fMsrpm & VMXMSRPM_EXIT_WR);
8029 }
8030
8031 /* Without MSR bitmaps, all MSR accesses are intercepted. */
8032 return true;
8033}
8034
8035
8036/**
8037 * VMREAD instruction execution worker that does not perform any validation checks.
8038 *
8039 * Callers are expected to have performed the necessary checks and to ensure the
8040 * VMREAD will succeed.
8041 *
8042 * @param pVmcs Pointer to the virtual VMCS.
8043 * @param pu64Dst Where to write the VMCS value.
8044 * @param u64VmcsField The VMCS field.
8045 *
8046 * @remarks May be called with interrupts disabled.
8047 */
8048static void iemVmxVmreadNoCheck(PCVMXVVMCS pVmcs, uint64_t *pu64Dst, uint64_t u64VmcsField) RT_NOEXCEPT
8049{
8050 VMXVMCSFIELD VmcsField;
8051 VmcsField.u = u64VmcsField;
8052 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8053 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8054 uint8_t const uWidthType = (uWidth << 2) | uType;
8055 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8056 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8057 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8058 AssertMsg(offField < VMX_V_VMCS_SIZE, ("off=%u field=%#RX64 width=%#x type=%#x index=%#x (%u)\n", offField, u64VmcsField,
8059 uWidth, uType, uIndex, uIndex));
8060 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8061
8062 /*
8063 * Read the VMCS component based on the field's effective width.
8064 *
8065 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8066 * indicates high bits (little endian).
8067 *
8068 * Note! The caller is responsible to trim the result and update registers
8069 * or memory locations are required. Here we just zero-extend to the largest
8070 * type (i.e. 64-bits).
8071 */
8072 uint8_t const *pbVmcs = (uint8_t const *)pVmcs;
8073 uint8_t const *pbField = pbVmcs + offField;
8074 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8075 switch (uEffWidth)
8076 {
8077 case VMX_VMCSFIELD_WIDTH_64BIT:
8078 case VMX_VMCSFIELD_WIDTH_NATURAL: *pu64Dst = *(uint64_t const *)pbField; break;
8079 case VMX_VMCSFIELD_WIDTH_32BIT: *pu64Dst = *(uint32_t const *)pbField; break;
8080 case VMX_VMCSFIELD_WIDTH_16BIT: *pu64Dst = *(uint16_t const *)pbField; break;
8081 }
8082}
8083
8084
8085/**
8086 * Interface for HM and EM to read a VMCS field from the nested-guest VMCS.
8087 *
8088 * It is ASSUMED the caller knows what they're doing. No VMREAD instruction checks
8089 * are performed. Bounds checks are strict builds only.
8090 *
8091 * @param pVmcs Pointer to the virtual VMCS.
8092 * @param u64VmcsField The VMCS field.
8093 * @param pu64Dst Where to store the VMCS value.
8094 *
8095 * @remarks May be called with interrupts disabled.
8096 * @todo This should probably be moved to CPUM someday.
8097 */
8098VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst)
8099{
8100 AssertPtr(pVmcs);
8101 AssertPtr(pu64Dst);
8102 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8103}
8104
8105
8106/**
8107 * VMREAD common (memory/register) instruction execution worker.
8108 *
8109 * @returns Strict VBox status code.
8110 * @param pVCpu The cross context virtual CPU structure.
8111 * @param cbInstr The instruction length in bytes.
8112 * @param pu64Dst Where to write the VMCS value (only updated when
8113 * VINF_SUCCESS is returned).
8114 * @param u64VmcsField The VMCS field.
8115 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8116 * NULL.
8117 */
8118static VBOXSTRICTRC iemVmxVmreadCommon(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8119 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8120{
8121 /* Nested-guest intercept. */
8122 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8123 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64VmcsField))
8124 {
8125 if (pExitInfo)
8126 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8127 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
8128 }
8129
8130 /* CPL. */
8131 if (pVCpu->iem.s.uCpl == 0)
8132 { /* likely */ }
8133 else
8134 {
8135 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8136 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
8137 return iemRaiseGeneralProtectionFault0(pVCpu);
8138 }
8139
8140 pVCpu->iem.s.cPotentialExits++;
8141
8142 /* VMCS pointer in root mode. */
8143 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8144 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8145 { /* likely */ }
8146 else
8147 {
8148 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8149 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
8150 iemVmxVmFailInvalid(pVCpu);
8151 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8152 }
8153
8154 /* VMCS-link pointer in non-root mode. */
8155 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8156 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8157 { /* likely */ }
8158 else
8159 {
8160 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8161 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
8162 iemVmxVmFailInvalid(pVCpu);
8163 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8164 }
8165
8166 /* Supported VMCS field. */
8167 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8168 { /* likely */ }
8169 else
8170 {
8171 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8172 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
8173 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8174 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
8175 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8176 }
8177
8178 /*
8179 * Reading from the current or shadow VMCS.
8180 */
8181 PCVMXVVMCS pVmcs = !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8182 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8183 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8184 iemVmxVmreadNoCheck(pVmcs, pu64Dst, u64VmcsField);
8185 Log4(("vmread %#RX64 => %#RX64\n", u64VmcsField, *pu64Dst));
8186 return VINF_SUCCESS;
8187}
8188
8189
8190/**
8191 * VMREAD (64-bit register) instruction execution worker.
8192 *
8193 * @returns Strict VBox status code.
8194 * @param pVCpu The cross context virtual CPU structure.
8195 * @param cbInstr The instruction length in bytes.
8196 * @param pu64Dst Where to store the VMCS field's value.
8197 * @param u64VmcsField The VMCS field.
8198 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8199 * NULL.
8200 */
8201static VBOXSTRICTRC iemVmxVmreadReg64(PVMCPUCC pVCpu, uint8_t cbInstr, uint64_t *pu64Dst,
8202 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8203{
8204 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64VmcsField, pExitInfo);
8205 if (rcStrict == VINF_SUCCESS)
8206 {
8207 iemVmxVmSucceed(pVCpu);
8208 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8209 }
8210
8211 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8212 return rcStrict;
8213}
8214
8215
8216/**
8217 * VMREAD (32-bit register) instruction execution worker.
8218 *
8219 * @returns Strict VBox status code.
8220 * @param pVCpu The cross context virtual CPU structure.
8221 * @param cbInstr The instruction length in bytes.
8222 * @param pu32Dst Where to store the VMCS field's value.
8223 * @param u32VmcsField The VMCS field.
8224 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8225 * NULL.
8226 */
8227static VBOXSTRICTRC iemVmxVmreadReg32(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t *pu32Dst,
8228 uint64_t u32VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8229{
8230 uint64_t u64Dst;
8231 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32VmcsField, pExitInfo);
8232 if (rcStrict == VINF_SUCCESS)
8233 {
8234 *pu32Dst = u64Dst;
8235 iemVmxVmSucceed(pVCpu);
8236 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8237 }
8238
8239 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8240 return rcStrict;
8241}
8242
8243
8244/**
8245 * VMREAD (memory) instruction execution worker.
8246 *
8247 * @returns Strict VBox status code.
8248 * @param pVCpu The cross context virtual CPU structure.
8249 * @param cbInstr The instruction length in bytes.
8250 * @param iEffSeg The effective segment register to use with @a u64Val.
8251 * Pass UINT8_MAX if it is a register access.
8252 * @param GCPtrDst The guest linear address to store the VMCS field's
8253 * value.
8254 * @param u64VmcsField The VMCS field.
8255 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8256 * NULL.
8257 */
8258static VBOXSTRICTRC iemVmxVmreadMem(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDst,
8259 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8260{
8261 uint64_t u64Dst;
8262 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64VmcsField, pExitInfo);
8263 if (rcStrict == VINF_SUCCESS)
8264 {
8265 /*
8266 * Write the VMCS field's value to the location specified in guest-memory.
8267 */
8268 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8269 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8270 else
8271 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
8272 if (rcStrict == VINF_SUCCESS)
8273 {
8274 iemVmxVmSucceed(pVCpu);
8275 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8276 }
8277
8278 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
8279 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
8280 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrDst;
8281 return rcStrict;
8282 }
8283
8284 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8285 return rcStrict;
8286}
8287
8288
8289/**
8290 * Interface for HM and EM to emulate the VMREAD instruction.
8291 *
8292 * @returns Strict VBox status code.
8293 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8294 * @param pExitInfo Pointer to the VM-exit information.
8295 * @thread EMT(pVCpu)
8296 */
8297VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8298{
8299 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8300 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8301 Assert(pExitInfo);
8302
8303 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8304
8305 VBOXSTRICTRC rcStrict;
8306 uint8_t const cbInstr = pExitInfo->cbInstr;
8307 bool const fIs64BitMode = RT_BOOL(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
8308 uint64_t const u64FieldEnc = fIs64BitMode
8309 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8310 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8311 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8312 {
8313 if (fIs64BitMode)
8314 {
8315 uint64_t *pu64Dst = iemGRegRefU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8316 rcStrict = iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
8317 }
8318 else
8319 {
8320 uint32_t *pu32Dst = iemGRegRefU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8321 rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u64FieldEnc, pExitInfo);
8322 }
8323 }
8324 else
8325 {
8326 RTGCPTR const GCPtrDst = pExitInfo->GCPtrEffAddr;
8327 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8328 rcStrict = iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64FieldEnc, pExitInfo);
8329 }
8330 Assert(!pVCpu->iem.s.cActiveMappings);
8331 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8332}
8333
8334
8335/**
8336 * VMWRITE instruction execution worker that does not perform any validation
8337 * checks.
8338 *
8339 * Callers are expected to have performed the necessary checks and to ensure the
8340 * VMWRITE will succeed.
8341 *
8342 * @param pVmcs Pointer to the virtual VMCS.
8343 * @param u64Val The value to write.
8344 * @param u64VmcsField The VMCS field.
8345 *
8346 * @remarks May be called with interrupts disabled.
8347 */
8348static void iemVmxVmwriteNoCheck(PVMXVVMCS pVmcs, uint64_t u64Val, uint64_t u64VmcsField) RT_NOEXCEPT
8349{
8350 VMXVMCSFIELD VmcsField;
8351 VmcsField.u = u64VmcsField;
8352 uint8_t const uWidth = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_WIDTH);
8353 uint8_t const uType = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_TYPE);
8354 uint8_t const uWidthType = (uWidth << 2) | uType;
8355 uint8_t const uIndex = RT_BF_GET(VmcsField.u, VMX_BF_VMCSFIELD_INDEX);
8356 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
8357 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8358 Assert(offField < VMX_V_VMCS_SIZE);
8359 AssertCompile(VMX_V_SHADOW_VMCS_SIZE == VMX_V_VMCS_SIZE);
8360
8361 /*
8362 * Write the VMCS component based on the field's effective width.
8363 *
8364 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8365 * indicates high bits (little endian).
8366 */
8367 uint8_t *pbVmcs = (uint8_t *)pVmcs;
8368 uint8_t *pbField = pbVmcs + offField;
8369 uint8_t const uEffWidth = VMXGetVmcsFieldWidthEff(VmcsField.u);
8370 switch (uEffWidth)
8371 {
8372 case VMX_VMCSFIELD_WIDTH_64BIT:
8373 case VMX_VMCSFIELD_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8374 case VMX_VMCSFIELD_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8375 case VMX_VMCSFIELD_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8376 }
8377}
8378
8379
8380/**
8381 * Interface for HM and EM to write a VMCS field in the nested-guest VMCS.
8382 *
8383 * It is ASSUMED the caller knows what they're doing. No VMWRITE instruction checks
8384 * are performed. Bounds checks are strict builds only.
8385 *
8386 * @param pVmcs Pointer to the virtual VMCS.
8387 * @param u64VmcsField The VMCS field.
8388 * @param u64Val The value to write.
8389 *
8390 * @remarks May be called with interrupts disabled.
8391 * @todo This should probably be moved to CPUM someday.
8392 */
8393VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val)
8394{
8395 AssertPtr(pVmcs);
8396 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8397}
8398
8399
8400/**
8401 * VMWRITE instruction execution worker.
8402 *
8403 * @returns Strict VBox status code.
8404 * @param pVCpu The cross context virtual CPU structure.
8405 * @param cbInstr The instruction length in bytes.
8406 * @param iEffSeg The effective segment register to use with @a u64Val.
8407 * Pass UINT8_MAX if it is a register access.
8408 * @param u64Val The value to write (or guest linear address to the
8409 * value), @a iEffSeg will indicate if it's a memory
8410 * operand.
8411 * @param u64VmcsField The VMCS field.
8412 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
8413 * NULL.
8414 */
8415static VBOXSTRICTRC iemVmxVmwrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, uint64_t u64Val,
8416 uint64_t u64VmcsField, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8417{
8418 /* Nested-guest intercept. */
8419 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8420 && CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64VmcsField))
8421 {
8422 if (pExitInfo)
8423 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8424 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
8425 }
8426
8427 /* CPL. */
8428 if (pVCpu->iem.s.uCpl == 0)
8429 { /* likely */ }
8430 else
8431 {
8432 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8433 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8434 return iemRaiseGeneralProtectionFault0(pVCpu);
8435 }
8436
8437 pVCpu->iem.s.cPotentialExits++;
8438
8439 /* VMCS pointer in root mode. */
8440 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8441 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8442 { /* likely */ }
8443 else
8444 {
8445 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8446 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8447 iemVmxVmFailInvalid(pVCpu);
8448 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8449 }
8450
8451 /* VMCS-link pointer in non-root mode. */
8452 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8453 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8454 { /* likely */ }
8455 else
8456 {
8457 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8458 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8459 iemVmxVmFailInvalid(pVCpu);
8460 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8461 }
8462
8463 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8464 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8465 if (!fIsRegOperand)
8466 {
8467 /* Read the value from the specified guest memory location. */
8468 VBOXSTRICTRC rcStrict;
8469 RTGCPTR const GCPtrVal = u64Val;
8470 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8471 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8472 else
8473 rcStrict = iemMemFetchDataU32_ZX_U64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8474 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8475 {
8476 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8477 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8478 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVal;
8479 return rcStrict;
8480 }
8481 }
8482 else
8483 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8484
8485 /* Supported VMCS field. */
8486 if (CPUMIsGuestVmxVmcsFieldValid(pVCpu->CTX_SUFF(pVM), u64VmcsField))
8487 { /* likely */ }
8488 else
8489 {
8490 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64VmcsField));
8491 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8492 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8493 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8494 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8495 }
8496
8497 /* Read-only VMCS field. */
8498 bool const fIsFieldReadOnly = VMXIsVmcsFieldReadOnly(u64VmcsField);
8499 if ( !fIsFieldReadOnly
8500 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8501 { /* likely */ }
8502 else
8503 {
8504 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64VmcsField));
8505 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8506 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64VmcsField;
8507 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8508 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8509 }
8510
8511 /*
8512 * Write to the current or shadow VMCS.
8513 */
8514 bool const fInVmxNonRootMode = IEM_VMX_IS_NON_ROOT_MODE(pVCpu);
8515 PVMXVVMCS pVmcs = !fInVmxNonRootMode
8516 ? &pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs
8517 : &pVCpu->cpum.GstCtx.hwvirt.vmx.ShadowVmcs;
8518 iemVmxVmwriteNoCheck(pVmcs, u64Val, u64VmcsField);
8519 Log4(("vmwrite %#RX64 <= %#RX64\n", u64VmcsField, u64Val));
8520
8521 if ( !fInVmxNonRootMode
8522 && VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8523 {
8524 /* Notify HM that the VMCS content might have changed. */
8525 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8526 }
8527
8528 iemVmxVmSucceed(pVCpu);
8529 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8530}
8531
8532
8533/**
8534 * Interface for HM and EM to emulate the VMWRITE instruction.
8535 *
8536 * @returns Strict VBox status code.
8537 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8538 * @param pExitInfo Pointer to the VM-exit information.
8539 * @thread EMT(pVCpu)
8540 */
8541VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8542{
8543 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8544 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8545 Assert(pExitInfo);
8546
8547 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8548
8549 uint64_t u64Val;
8550 uint8_t iEffSeg;
8551 if (pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand)
8552 {
8553 u64Val = iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg1);
8554 iEffSeg = UINT8_MAX;
8555 }
8556 else
8557 {
8558 u64Val = pExitInfo->GCPtrEffAddr;
8559 iEffSeg = pExitInfo->InstrInfo.VmreadVmwrite.iSegReg;
8560 }
8561 uint8_t const cbInstr = pExitInfo->cbInstr;
8562 uint64_t const u64FieldEnc = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
8563 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2)
8564 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.VmreadVmwrite.iReg2);
8565 VBOXSTRICTRC rcStrict = iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, u64Val, u64FieldEnc, pExitInfo);
8566 Assert(!pVCpu->iem.s.cActiveMappings);
8567 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8568}
8569
8570
8571/**
8572 * VMCLEAR instruction execution worker.
8573 *
8574 * @returns Strict VBox status code.
8575 * @param pVCpu The cross context virtual CPU structure.
8576 * @param cbInstr The instruction length in bytes.
8577 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8578 * @param GCPtrVmcs The linear address of the VMCS pointer.
8579 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8580 *
8581 * @remarks Common VMX instruction checks are already expected to by the caller,
8582 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8583 */
8584static VBOXSTRICTRC iemVmxVmclear(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8585 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8586{
8587 /* Nested-guest intercept. */
8588 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8589 {
8590 if (pExitInfo)
8591 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8592 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8593 }
8594
8595 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8596
8597 /* CPL. */
8598 if (pVCpu->iem.s.uCpl == 0)
8599 { /* likely */ }
8600 else
8601 {
8602 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8603 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8604 return iemRaiseGeneralProtectionFault0(pVCpu);
8605 }
8606
8607 /* Get the VMCS pointer from the location specified by the source memory operand. */
8608 RTGCPHYS GCPhysVmcs;
8609 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8610 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8611 { /* likely */ }
8612 else
8613 {
8614 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8615 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8616 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8617 return rcStrict;
8618 }
8619
8620 /* VMCS pointer alignment. */
8621 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8622 { /* likely */ }
8623 else
8624 {
8625 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8626 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8627 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8628 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8629 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8630 }
8631
8632 /* VMCS physical-address width limits. */
8633 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8634 { /* likely */ }
8635 else
8636 {
8637 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8638 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8639 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8640 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8641 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8642 }
8643
8644 /* VMCS is not the VMXON region. */
8645 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8646 { /* likely */ }
8647 else
8648 {
8649 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8650 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8651 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8652 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8653 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8654 }
8655
8656 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8657 restriction imposed by our implementation. */
8658 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8659 { /* likely */ }
8660 else
8661 {
8662 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8663 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8664 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8665 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8666 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8667 }
8668
8669 /*
8670 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8671 *
8672 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8673 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8674 * to 'clear'.
8675 */
8676 uint8_t const fVmcsLaunchStateClear = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
8677 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8678 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8679 {
8680 pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.fVmcsState = fVmcsLaunchStateClear;
8681 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8682 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8683 }
8684 else
8685 {
8686 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsLaunchStateClear));
8687 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8688 (const void *)&fVmcsLaunchStateClear, sizeof(fVmcsLaunchStateClear));
8689 if (RT_FAILURE(rcStrict))
8690 return rcStrict;
8691 }
8692
8693 iemVmxVmSucceed(pVCpu);
8694 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8695}
8696
8697
8698/**
8699 * Interface for HM and EM to emulate the VMCLEAR instruction.
8700 *
8701 * @returns Strict VBox status code.
8702 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8703 * @param pExitInfo Pointer to the VM-exit information.
8704 * @thread EMT(pVCpu)
8705 */
8706VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8707{
8708 Assert(pExitInfo);
8709 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8710 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8711
8712 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8713
8714 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8715 uint8_t const cbInstr = pExitInfo->cbInstr;
8716 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8717 VBOXSTRICTRC rcStrict = iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8718 Assert(!pVCpu->iem.s.cActiveMappings);
8719 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8720}
8721
8722
8723/**
8724 * VMPTRST instruction execution worker.
8725 *
8726 * @returns Strict VBox status code.
8727 * @param pVCpu The cross context virtual CPU structure.
8728 * @param cbInstr The instruction length in bytes.
8729 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8730 * @param GCPtrVmcs The linear address of where to store the current VMCS
8731 * pointer.
8732 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8733 *
8734 * @remarks Common VMX instruction checks are already expected to by the caller,
8735 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8736 */
8737static VBOXSTRICTRC iemVmxVmptrst(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8738 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8739{
8740 /* Nested-guest intercept. */
8741 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8742 {
8743 if (pExitInfo)
8744 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8745 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8746 }
8747
8748 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8749
8750 /* CPL. */
8751 if (pVCpu->iem.s.uCpl == 0)
8752 { /* likely */ }
8753 else
8754 {
8755 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8756 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8757 return iemRaiseGeneralProtectionFault0(pVCpu);
8758 }
8759
8760 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8761 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8762 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8763 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8764 {
8765 iemVmxVmSucceed(pVCpu);
8766 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8767 }
8768
8769 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8770 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8771 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8772 return rcStrict;
8773}
8774
8775
8776/**
8777 * Interface for HM and EM to emulate the VMPTRST instruction.
8778 *
8779 * @returns Strict VBox status code.
8780 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8781 * @param pExitInfo Pointer to the VM-exit information.
8782 * @thread EMT(pVCpu)
8783 */
8784VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8785{
8786 Assert(pExitInfo);
8787 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8788 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8789
8790 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8791
8792 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8793 uint8_t const cbInstr = pExitInfo->cbInstr;
8794 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8795 VBOXSTRICTRC rcStrict = iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8796 Assert(!pVCpu->iem.s.cActiveMappings);
8797 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8798}
8799
8800
8801/**
8802 * VMPTRLD instruction execution worker.
8803 *
8804 * @returns Strict VBox status code.
8805 * @param pVCpu The cross context virtual CPU structure.
8806 * @param cbInstr The instruction length in bytes.
8807 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8808 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
8809 *
8810 * @remarks Common VMX instruction checks are already expected to by the caller,
8811 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8812 */
8813static VBOXSTRICTRC iemVmxVmptrld(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
8814 RTGCPHYS GCPtrVmcs, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
8815{
8816 /* Nested-guest intercept. */
8817 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8818 {
8819 if (pExitInfo)
8820 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8821 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8822 }
8823
8824 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8825
8826 /* CPL. */
8827 if (pVCpu->iem.s.uCpl == 0)
8828 { /* likely */ }
8829 else
8830 {
8831 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8832 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8833 return iemRaiseGeneralProtectionFault0(pVCpu);
8834 }
8835
8836 /* Get the VMCS pointer from the location specified by the source memory operand. */
8837 RTGCPHYS GCPhysVmcs;
8838 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8839 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8840 { /* likely */ }
8841 else
8842 {
8843 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8844 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8845 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmcs;
8846 return rcStrict;
8847 }
8848
8849 /* VMCS pointer alignment. */
8850 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8851 { /* likely */ }
8852 else
8853 {
8854 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8855 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8856 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8857 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8858 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8859 }
8860
8861 /* VMCS physical-address width limits. */
8862 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8863 { /* likely */ }
8864 else
8865 {
8866 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8867 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8868 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8869 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8870 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8871 }
8872
8873 /* VMCS is not the VMXON region. */
8874 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8875 { /* likely */ }
8876 else
8877 {
8878 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8879 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8880 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8881 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8882 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8883 }
8884
8885 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8886 restriction imposed by our implementation. */
8887 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8888 { /* likely */ }
8889 else
8890 {
8891 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8892 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8893 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8894 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8895 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8896 }
8897
8898 /* Read just the VMCS revision from the VMCS. */
8899 VMXVMCSREVID VmcsRevId;
8900 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8901 if (RT_SUCCESS(rc))
8902 { /* likely */ }
8903 else
8904 {
8905 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8906 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8907 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8908 return rc;
8909 }
8910
8911 /*
8912 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8913 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8914 */
8915 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8916 && ( !VmcsRevId.n.fIsShadowVmcs
8917 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8918 { /* likely */ }
8919 else
8920 {
8921 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8922 {
8923 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8924 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8925 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8926 }
8927 else
8928 {
8929 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8930 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8931 }
8932 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8933 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8934 }
8935
8936 /*
8937 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8938 * the cache of an existing, current VMCS back to guest memory before loading a new,
8939 * different current VMCS.
8940 */
8941 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8942 {
8943 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8944 {
8945 iemVmxWriteCurrentVmcsToGstMem(pVCpu);
8946 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8947 }
8948
8949 /* Set the new VMCS as the current VMCS and read it from guest memory. */
8950 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8951 rc = iemVmxReadCurrentVmcsFromGstMem(pVCpu);
8952 if (RT_SUCCESS(rc))
8953 {
8954 /* Notify HM that a new, current VMCS is loaded. */
8955 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
8956 HMNotifyVmxNstGstCurrentVmcsChanged(pVCpu);
8957 }
8958 else
8959 {
8960 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8961 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8962 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmcs;
8963 return rc;
8964 }
8965 }
8966
8967 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8968 iemVmxVmSucceed(pVCpu);
8969 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
8970}
8971
8972
8973/**
8974 * Interface for HM and EM to emulate the VMPTRLD instruction.
8975 *
8976 * @returns Strict VBox status code.
8977 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
8978 * @param pExitInfo Pointer to the VM-exit information.
8979 * @thread EMT(pVCpu)
8980 */
8981VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
8982{
8983 Assert(pExitInfo);
8984 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
8985 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
8986
8987 iemInitExec(pVCpu, false /*fBypassHandlers*/);
8988
8989 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
8990 uint8_t const cbInstr = pExitInfo->cbInstr;
8991 RTGCPTR const GCPtrVmcs = pExitInfo->GCPtrEffAddr;
8992 VBOXSTRICTRC rcStrict = iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, pExitInfo);
8993 Assert(!pVCpu->iem.s.cActiveMappings);
8994 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
8995}
8996
8997
8998/**
8999 * INVVPID instruction execution worker.
9000 *
9001 * @returns Strict VBox status code.
9002 * @param pVCpu The cross context virtual CPU structure.
9003 * @param cbInstr The instruction length in bytes.
9004 * @param iEffSeg The segment of the invvpid descriptor.
9005 * @param GCPtrInvvpidDesc The address of invvpid descriptor.
9006 * @param u64InvvpidType The invalidation type.
9007 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9008 * NULL.
9009 *
9010 * @remarks Common VMX instruction checks are already expected to by the caller,
9011 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9012 */
9013VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
9014 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9015{
9016 /* Check if INVVPID instruction is supported, otherwise raise #UD. */
9017 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVpid)
9018 return iemRaiseUndefinedOpcode(pVCpu);
9019
9020 /* Nested-guest intercept. */
9021 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9022 {
9023 if (pExitInfo)
9024 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9025 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVVPID, VMXINSTRID_NONE, cbInstr);
9026 }
9027
9028 /* CPL. */
9029 if (pVCpu->iem.s.uCpl != 0)
9030 {
9031 Log(("invvpid: CPL != 0 -> #GP(0)\n"));
9032 return iemRaiseGeneralProtectionFault0(pVCpu);
9033 }
9034
9035 /*
9036 * Validate INVVPID invalidation type.
9037 *
9038 * The instruction specifies exactly ONE of the supported invalidation types.
9039 *
9040 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9041 * supported. In theory, it's possible for a CPU to not support flushing individual
9042 * addresses but all the other types or any other combination. We do not take any
9043 * shortcuts here by assuming the types we currently expose to the guest.
9044 */
9045 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9046 bool const fInvvpidSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID);
9047 bool const fTypeIndivAddr = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
9048 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
9049 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
9050 bool const fTypeSingleCtxRetainGlobals = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
9051
9052 bool afSupportedTypes[4];
9053 afSupportedTypes[0] = fTypeIndivAddr;
9054 afSupportedTypes[1] = fTypeSingleCtx;
9055 afSupportedTypes[2] = fTypeAllCtx;
9056 afSupportedTypes[3] = fTypeSingleCtxRetainGlobals;
9057
9058 if ( fInvvpidSupported
9059 && !(u64InvvpidType & ~(uint64_t)VMX_INVVPID_VALID_MASK)
9060 && afSupportedTypes[u64InvvpidType & 3])
9061 { /* likely */ }
9062 else
9063 {
9064 Log(("invvpid: invalid/unsupported invvpid type %#x -> VMFail\n", u64InvvpidType));
9065 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_TypeInvalid;
9066 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9067 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9068 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9069 }
9070
9071 /*
9072 * Fetch the invvpid descriptor from guest memory.
9073 */
9074 RTUINT128U uDesc;
9075 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvvpidDesc);
9076 if (rcStrict == VINF_SUCCESS)
9077 {
9078 /*
9079 * Validate the descriptor.
9080 */
9081 if (uDesc.s.Lo <= 0xffff)
9082 { /* likely */ }
9083 else
9084 {
9085 Log(("invvpid: reserved bits set in invvpid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
9086 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_DescRsvd;
9087 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Lo;
9088 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9089 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9090 }
9091
9092 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9093 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
9094 uint16_t const uVpid = uDesc.Words.w0;
9095 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9096 switch (u64InvvpidType)
9097 {
9098 case VMXTLBFLUSHVPID_INDIV_ADDR:
9099 {
9100 if (uVpid != 0)
9101 {
9102 if (IEM_IS_CANONICAL(GCPtrInvAddr))
9103 {
9104 /* Invalidate mappings for the linear address tagged with VPID. */
9105 /** @todo PGM support for VPID? Currently just flush everything. */
9106 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9107 iemVmxVmSucceed(pVCpu);
9108 }
9109 else
9110 {
9111 Log(("invvpid: invalidation address %#RGP is not canonical -> VMFail\n", GCPtrInvAddr));
9112 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidAddr;
9113 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrInvAddr;
9114 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9115 }
9116 }
9117 else
9118 {
9119 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9120 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type0InvalidVpid;
9121 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9122 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9123 }
9124 break;
9125 }
9126
9127 case VMXTLBFLUSHVPID_SINGLE_CONTEXT:
9128 {
9129 if (uVpid != 0)
9130 {
9131 /* Invalidate all mappings with VPID. */
9132 /** @todo PGM support for VPID? Currently just flush everything. */
9133 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9134 iemVmxVmSucceed(pVCpu);
9135 }
9136 else
9137 {
9138 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9139 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type1InvalidVpid;
9140 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InvvpidType;
9141 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9142 }
9143 break;
9144 }
9145
9146 case VMXTLBFLUSHVPID_ALL_CONTEXTS:
9147 {
9148 /* Invalidate all mappings with non-zero VPIDs. */
9149 /** @todo PGM support for VPID? Currently just flush everything. */
9150 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9151 iemVmxVmSucceed(pVCpu);
9152 break;
9153 }
9154
9155 case VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS:
9156 {
9157 if (uVpid != 0)
9158 {
9159 /* Invalidate all mappings with VPID except global translations. */
9160 /** @todo PGM support for VPID? Currently just flush everything. */
9161 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9162 iemVmxVmSucceed(pVCpu);
9163 }
9164 else
9165 {
9166 Log(("invvpid: invalid VPID %#x for invalidation type %u -> VMFail\n", uVpid, u64InvvpidType));
9167 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invvpid_Type3InvalidVpid;
9168 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uVpid;
9169 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9170 }
9171 break;
9172 }
9173 IEM_NOT_REACHED_DEFAULT_CASE_RET();
9174 }
9175 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9176 }
9177 return rcStrict;
9178}
9179
9180
9181/**
9182 * Interface for HM and EM to emulate the INVVPID instruction.
9183 *
9184 * @returns Strict VBox status code.
9185 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9186 * @param pExitInfo Pointer to the VM-exit information.
9187 * @thread EMT(pVCpu)
9188 */
9189VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9190{
9191 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9192 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9193 Assert(pExitInfo);
9194
9195 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9196
9197 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9198 uint8_t const cbInstr = pExitInfo->cbInstr;
9199 RTGCPTR const GCPtrInvvpidDesc = pExitInfo->GCPtrEffAddr;
9200 uint64_t const u64InvvpidType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9201 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9202 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9203 VBOXSTRICTRC rcStrict = iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, u64InvvpidType, pExitInfo);
9204 Assert(!pVCpu->iem.s.cActiveMappings);
9205 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9206}
9207
9208#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9209
9210/**
9211 * INVEPT instruction execution worker.
9212 *
9213 * @returns Strict VBox status code.
9214 * @param pVCpu The cross context virtual CPU structure.
9215 * @param cbInstr The instruction length in bytes.
9216 * @param iEffSeg The segment of the invept descriptor.
9217 * @param GCPtrInveptDesc The address of invept descriptor.
9218 * @param u64InveptType The invalidation type.
9219 * @param pExitInfo Pointer to the VM-exit information. Optional, can be
9220 * NULL.
9221 *
9222 * @remarks Common VMX instruction checks are already expected to by the caller,
9223 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9224 */
9225static VBOXSTRICTRC iemVmxInvept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInveptDesc,
9226 uint64_t u64InveptType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9227{
9228 /* Check if EPT is supported, otherwise raise #UD. */
9229 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEpt)
9230 return iemRaiseUndefinedOpcode(pVCpu);
9231
9232 /* Nested-guest intercept. */
9233 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9234 {
9235 if (pExitInfo)
9236 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9237 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_INVEPT, VMXINSTRID_NONE, cbInstr);
9238 }
9239
9240 /* CPL. */
9241 if (pVCpu->iem.s.uCpl != 0)
9242 {
9243 Log(("invept: CPL != 0 -> #GP(0)\n"));
9244 return iemRaiseGeneralProtectionFault0(pVCpu);
9245 }
9246
9247 /*
9248 * Validate INVEPT invalidation type.
9249 *
9250 * The instruction specifies exactly ONE of the supported invalidation types.
9251 *
9252 * Each of the types has a bit in IA32_VMX_EPT_VPID_CAP MSR specifying if it is
9253 * supported. In theory, it's possible for a CPU to not support flushing individual
9254 * addresses but all the other types or any other combination. We do not take any
9255 * shortcuts here by assuming the types we currently expose to the guest.
9256 */
9257 uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
9258 bool const fInveptSupported = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT);
9259 bool const fTypeSingleCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
9260 bool const fTypeAllCtx = RT_BF_GET(fCaps, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
9261
9262 bool afSupportedTypes[4];
9263 afSupportedTypes[0] = false;
9264 afSupportedTypes[1] = fTypeSingleCtx;
9265 afSupportedTypes[2] = fTypeAllCtx;
9266 afSupportedTypes[3] = false;
9267
9268 if ( fInveptSupported
9269 && !(u64InveptType & ~(uint64_t)VMX_INVEPT_VALID_MASK)
9270 && afSupportedTypes[u64InveptType & 3])
9271 { /* likely */ }
9272 else
9273 {
9274 Log(("invept: invalid/unsupported invvpid type %#x -> VMFail\n", u64InveptType));
9275 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_TypeInvalid;
9276 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = u64InveptType;
9277 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9278 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9279 }
9280
9281 /*
9282 * Fetch the invept descriptor from guest memory.
9283 */
9284 RTUINT128U uDesc;
9285 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInveptDesc);
9286 if (rcStrict == VINF_SUCCESS)
9287 {
9288 /*
9289 * Validate the descriptor.
9290 *
9291 * The Intel spec. does not explicit say the INVEPT instruction fails when reserved
9292 * bits in the descriptor are set, but it -does- for INVVPID. Until we test on real
9293 * hardware, it's assumed INVEPT behaves the same as INVVPID in this regard. It's
9294 * better to be strict in our emulation until proven otherwise.
9295 */
9296 if (uDesc.s.Hi)
9297 {
9298 Log(("invept: reserved bits set in invept descriptor %#RX64 -> VMFail\n", uDesc.s.Hi));
9299 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_DescRsvd;
9300 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = uDesc.s.Hi;
9301 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9302 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9303 }
9304
9305 /*
9306 * Flush TLB mappings based on the EPT type.
9307 */
9308 if (u64InveptType == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
9309 {
9310 uint64_t const GCPhysEptPtr = uDesc.s.Lo;
9311 int const rc = iemVmxVmentryCheckEptPtr(pVCpu, GCPhysEptPtr, NULL /* enmDiag */);
9312 if (RT_SUCCESS(rc))
9313 { /* likely */ }
9314 else
9315 {
9316 Log(("invept: EPTP invalid %#RX64 -> VMFail\n", GCPhysEptPtr));
9317 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Invept_EptpInvalid;
9318 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysEptPtr;
9319 iemVmxVmFail(pVCpu, VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND);
9320 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9321 }
9322 }
9323
9324 /** @todo PGM support for EPT tags? Currently just flush everything. */
9325 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
9326 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
9327 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
9328
9329 iemVmxVmSucceed(pVCpu);
9330 rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9331 }
9332
9333 return rcStrict;
9334}
9335
9336
9337/**
9338 * Interface for HM and EM to emulate the INVEPT instruction.
9339 *
9340 * @returns Strict VBox status code.
9341 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9342 * @param pExitInfo Pointer to the VM-exit information.
9343 * @thread EMT(pVCpu)
9344 */
9345VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9346{
9347 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 4);
9348 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9349 Assert(pExitInfo);
9350
9351 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9352
9353 uint8_t const iEffSeg = pExitInfo->InstrInfo.Inv.iSegReg;
9354 uint8_t const cbInstr = pExitInfo->cbInstr;
9355 RTGCPTR const GCPtrInveptDesc = pExitInfo->GCPtrEffAddr;
9356 uint64_t const u64InveptType = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
9357 ? iemGRegFetchU64(pVCpu, pExitInfo->InstrInfo.Inv.iReg2)
9358 : iemGRegFetchU32(pVCpu, pExitInfo->InstrInfo.Inv.iReg2);
9359 VBOXSTRICTRC rcStrict = iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, u64InveptType, pExitInfo);
9360 Assert(!pVCpu->iem.s.cActiveMappings);
9361 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9362}
9363
9364#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
9365
9366/**
9367 * VMXON instruction execution worker.
9368 *
9369 * @returns Strict VBox status code.
9370 * @param pVCpu The cross context virtual CPU structure.
9371 * @param cbInstr The instruction length in bytes.
9372 * @param iEffSeg The effective segment register to use with @a
9373 * GCPtrVmxon.
9374 * @param GCPtrVmxon The linear address of the VMXON pointer.
9375 * @param pExitInfo Pointer to the VM-exit information. Optional, can be NULL.
9376 *
9377 * @remarks Common VMX instruction checks are already expected to by the caller,
9378 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9379 */
9380static VBOXSTRICTRC iemVmxVmxon(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg,
9381 RTGCPHYS GCPtrVmxon, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT
9382{
9383 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
9384 {
9385 /* CPL. */
9386 if (pVCpu->iem.s.uCpl == 0)
9387 { /* likely */ }
9388 else
9389 {
9390 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9391 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
9392 return iemRaiseGeneralProtectionFault0(pVCpu);
9393 }
9394
9395 /* A20M (A20 Masked) mode. */
9396 if (PGMPhysIsA20Enabled(pVCpu))
9397 { /* likely */ }
9398 else
9399 {
9400 Log(("vmxon: A20M mode -> #GP(0)\n"));
9401 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
9402 return iemRaiseGeneralProtectionFault0(pVCpu);
9403 }
9404
9405 /* CR0. */
9406 {
9407 /*
9408 * CR0 MB1 bits.
9409 *
9410 * We use VMX_V_CR0_FIXED0 below to ensure CR0.PE and CR0.PG are always set
9411 * while executing VMXON. CR0.PE and CR0.PG are only allowed to be clear
9412 * when the guest running in VMX non-root mode with unrestricted-guest control
9413 * enabled in the VMCS.
9414 */
9415 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
9416 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
9417 { /* likely */ }
9418 else
9419 {
9420 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
9421 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
9422 return iemRaiseGeneralProtectionFault0(pVCpu);
9423 }
9424
9425 /* CR0 MBZ bits. */
9426 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
9427 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
9428 { /* likely */ }
9429 else
9430 {
9431 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
9432 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
9433 return iemRaiseGeneralProtectionFault0(pVCpu);
9434 }
9435 }
9436
9437 /* CR4. */
9438 {
9439 /* CR4 MB1 bits. */
9440 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
9441 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
9442 { /* likely */ }
9443 else
9444 {
9445 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
9446 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
9447 return iemRaiseGeneralProtectionFault0(pVCpu);
9448 }
9449
9450 /* CR4 MBZ bits. */
9451 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
9452 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
9453 { /* likely */ }
9454 else
9455 {
9456 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
9457 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
9458 return iemRaiseGeneralProtectionFault0(pVCpu);
9459 }
9460 }
9461
9462 /* Feature control MSR's LOCK and VMXON bits. */
9463 uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
9464 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9465 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
9466 { /* likely */ }
9467 else
9468 {
9469 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
9470 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
9471 return iemRaiseGeneralProtectionFault0(pVCpu);
9472 }
9473
9474 /* Get the VMXON pointer from the location specified by the source memory operand. */
9475 RTGCPHYS GCPhysVmxon;
9476 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
9477 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
9478 { /* likely */ }
9479 else
9480 {
9481 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
9482 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
9483 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPtrVmxon;
9484 return rcStrict;
9485 }
9486
9487 /* VMXON region pointer alignment. */
9488 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
9489 { /* likely */ }
9490 else
9491 {
9492 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
9493 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
9494 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9495 iemVmxVmFailInvalid(pVCpu);
9496 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9497 }
9498
9499 /* VMXON physical-address width limits. */
9500 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
9501 { /* likely */ }
9502 else
9503 {
9504 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
9505 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
9506 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9507 iemVmxVmFailInvalid(pVCpu);
9508 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9509 }
9510
9511 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
9512 restriction imposed by our implementation. */
9513 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
9514 { /* likely */ }
9515 else
9516 {
9517 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
9518 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
9519 pVCpu->cpum.GstCtx.hwvirt.vmx.uDiagAux = GCPhysVmxon;
9520 iemVmxVmFailInvalid(pVCpu);
9521 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9522 }
9523
9524 /* Read the VMCS revision ID from the VMXON region. */
9525 VMXVMCSREVID VmcsRevId;
9526 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
9527 if (RT_SUCCESS(rc))
9528 { /* likely */ }
9529 else
9530 {
9531 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
9532 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
9533 return rc;
9534 }
9535
9536 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
9537 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
9538 { /* likely */ }
9539 else
9540 {
9541 /* Revision ID mismatch. */
9542 if (!VmcsRevId.n.fIsShadowVmcs)
9543 {
9544 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
9545 VmcsRevId.n.u31RevisionId));
9546 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
9547 iemVmxVmFailInvalid(pVCpu);
9548 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9549 }
9550
9551 /* Shadow VMCS disallowed. */
9552 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
9553 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
9554 iemVmxVmFailInvalid(pVCpu);
9555 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9556 }
9557
9558 /*
9559 * Record that we're in VMX operation, block INIT, block and disable A20M.
9560 */
9561 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
9562 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
9563 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
9564
9565 /* Clear address-range monitoring. */
9566 EMMonitorWaitClear(pVCpu);
9567 /** @todo NSTVMX: Intel PT. */
9568
9569 iemVmxVmSucceed(pVCpu);
9570 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9571 }
9572 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9573 {
9574 /* Nested-guest intercept. */
9575 if (pExitInfo)
9576 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
9577 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
9578 }
9579
9580 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
9581
9582 /* CPL. */
9583 if (pVCpu->iem.s.uCpl > 0)
9584 {
9585 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9586 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
9587 return iemRaiseGeneralProtectionFault0(pVCpu);
9588 }
9589
9590 /* VMXON when already in VMX root mode. */
9591 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
9592 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
9593 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9594}
9595
9596
9597/**
9598 * Interface for HM and EM to emulate the VMXON instruction.
9599 *
9600 * @returns Strict VBox status code.
9601 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9602 * @param pExitInfo Pointer to the VM-exit information.
9603 * @thread EMT(pVCpu)
9604 */
9605VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo)
9606{
9607 Assert(pExitInfo);
9608 IEMEXEC_ASSERT_INSTR_LEN_RETURN(pExitInfo->cbInstr, 3);
9609 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9610
9611 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9612
9613 uint8_t const iEffSeg = pExitInfo->InstrInfo.VmxXsave.iSegReg;
9614 uint8_t const cbInstr = pExitInfo->cbInstr;
9615 RTGCPTR const GCPtrVmxon = pExitInfo->GCPtrEffAddr;
9616 VBOXSTRICTRC rcStrict = iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, pExitInfo);
9617 Assert(!pVCpu->iem.s.cActiveMappings);
9618 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9619}
9620
9621
9622/**
9623 * Implements 'VMXOFF'.
9624 *
9625 * @remarks Common VMX instruction checks are already expected to by the caller,
9626 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
9627 */
9628IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
9629{
9630 /* Nested-guest intercept. */
9631 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9632 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
9633
9634 /* CPL. */
9635 if (pVCpu->iem.s.uCpl == 0)
9636 { /* likely */ }
9637 else
9638 {
9639 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
9640 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
9641 return iemRaiseGeneralProtectionFault0(pVCpu);
9642 }
9643
9644 /* Dual monitor treatment of SMIs and SMM. */
9645 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
9646 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
9647 { /* likely */ }
9648 else
9649 {
9650 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
9651 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9652 }
9653
9654 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
9655 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
9656 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
9657
9658 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
9659 { /** @todo NSTVMX: Unblock SMI. */ }
9660
9661 EMMonitorWaitClear(pVCpu);
9662 /** @todo NSTVMX: Unblock and enable A20M. */
9663
9664 iemVmxVmSucceed(pVCpu);
9665 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9666}
9667
9668
9669/**
9670 * Interface for HM and EM to emulate the VMXOFF instruction.
9671 *
9672 * @returns Strict VBox status code.
9673 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9674 * @param cbInstr The instruction length in bytes.
9675 * @thread EMT(pVCpu)
9676 */
9677VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr)
9678{
9679 IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 3);
9680 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI);
9681
9682 iemInitExec(pVCpu, false /*fBypassHandlers*/);
9683 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_0(iemCImpl_vmxoff);
9684 Assert(!pVCpu->iem.s.cActiveMappings);
9685 return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
9686}
9687
9688
9689/**
9690 * Implements 'VMXON'.
9691 */
9692IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
9693{
9694 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
9695}
9696
9697
9698/**
9699 * Implements 'VMLAUNCH'.
9700 */
9701IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
9702{
9703 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
9704}
9705
9706
9707/**
9708 * Implements 'VMRESUME'.
9709 */
9710IEM_CIMPL_DEF_0(iemCImpl_vmresume)
9711{
9712 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
9713}
9714
9715
9716/**
9717 * Implements 'VMPTRLD'.
9718 */
9719IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9720{
9721 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9722}
9723
9724
9725/**
9726 * Implements 'VMPTRST'.
9727 */
9728IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9729{
9730 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9731}
9732
9733
9734/**
9735 * Implements 'VMCLEAR'.
9736 */
9737IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
9738{
9739 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
9740}
9741
9742
9743/**
9744 * Implements 'VMWRITE' register.
9745 */
9746IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField)
9747{
9748 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, u64Val, u64VmcsField, NULL /* pExitInfo */);
9749}
9750
9751
9752/**
9753 * Implements 'VMWRITE' memory.
9754 */
9755IEM_CIMPL_DEF_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField)
9756{
9757 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, GCPtrVal, u64VmcsField, NULL /* pExitInfo */);
9758}
9759
9760
9761/**
9762 * Implements 'VMREAD' register (64-bit).
9763 */
9764IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField)
9765{
9766 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64VmcsField, NULL /* pExitInfo */);
9767}
9768
9769
9770/**
9771 * Implements 'VMREAD' register (32-bit).
9772 */
9773IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint64_t *, pu64Dst, uint32_t, u32VmcsField)
9774{
9775 VBOXSTRICTRC const rcStrict = iemVmxVmreadReg32(pVCpu, cbInstr, (uint32_t *)pu64Dst, u32VmcsField, NULL /* pExitInfo */);
9776 /* Zero the high part of the register on success. */
9777 if (rcStrict == VINF_SUCCESS)
9778 *pu64Dst = (uint32_t)*pu64Dst;
9779 return rcStrict;
9780}
9781
9782
9783/**
9784 * Implements 'VMREAD' memory, 64-bit register.
9785 */
9786IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField)
9787{
9788 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u64VmcsField, NULL /* pExitInfo */);
9789}
9790
9791
9792/**
9793 * Implements 'VMREAD' memory, 32-bit register.
9794 */
9795IEM_CIMPL_DEF_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField)
9796{
9797 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, GCPtrDst, u32VmcsField, NULL /* pExitInfo */);
9798}
9799
9800
9801/**
9802 * Implements 'INVVPID'.
9803 */
9804IEM_CIMPL_DEF_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType)
9805{
9806 return iemVmxInvvpid(pVCpu, cbInstr, iEffSeg, GCPtrInvvpidDesc, uInvvpidType, NULL /* pExitInfo */);
9807}
9808
9809
9810#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
9811/**
9812 * Implements 'INVEPT'.
9813 */
9814IEM_CIMPL_DEF_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType)
9815{
9816 return iemVmxInvept(pVCpu, cbInstr, iEffSeg, GCPtrInveptDesc, uInveptType, NULL /* pExitInfo */);
9817}
9818#endif
9819
9820
9821/**
9822 * Implements VMX's implementation of PAUSE.
9823 */
9824IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
9825{
9826 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9827 {
9828 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
9829 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9830 return rcStrict;
9831 }
9832
9833 /*
9834 * Outside VMX non-root operation or if the PAUSE instruction does not cause
9835 * a VM-exit, the instruction operates normally.
9836 */
9837 return iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
9838}
9839
9840#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
9841
9842
9843/**
9844 * Implements 'VMCALL'.
9845 */
9846IEM_CIMPL_DEF_0(iemCImpl_vmcall)
9847{
9848 pVCpu->iem.s.cPotentialExits++;
9849
9850#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9851 /* Nested-guest intercept. */
9852 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
9853 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
9854#endif
9855
9856 /* Join forces with vmmcall. */
9857 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
9858}
9859
9860
9861#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9862
9863/**
9864 * @callback_method_impl{FNPGMPHYSHANDLER, VMX APIC-access page accesses}
9865 *
9866 * @remarks The @a uUser argument is currently unused.
9867 */
9868DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPageHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, void *pvPhys,
9869 void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
9870 PGMACCESSORIGIN enmOrigin, uint64_t uUser)
9871{
9872 RT_NOREF3(pvPhys, enmOrigin, uUser);
9873
9874 RTGCPHYS const GCPhysAccessBase = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9875 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9876 {
9877 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9878 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysAccessBase);
9879
9880 uint32_t const fAccess = enmAccessType == PGMACCESSTYPE_WRITE ? IEM_ACCESS_DATA_W : IEM_ACCESS_DATA_R;
9881 uint16_t const offAccess = GCPhysFault & GUEST_PAGE_OFFSET_MASK;
9882
9883 LogFlowFunc(("Fault at %#RGp (cbBuf=%u fAccess=%#x)\n", GCPhysFault, cbBuf, fAccess));
9884 VBOXSTRICTRC rcStrict = iemVmxVirtApicAccessMem(pVCpu, offAccess, cbBuf, pvBuf, fAccess);
9885 if (RT_FAILURE(rcStrict))
9886 return rcStrict;
9887
9888 /* Any access on this APIC-access page has been handled, caller should not carry out the access. */
9889 return VINF_SUCCESS;
9890 }
9891
9892 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysAccessBase));
9893 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhysAccessBase);
9894 if (RT_FAILURE(rc))
9895 return rc;
9896
9897 /* Instruct the caller of this handler to perform the read/write as normal memory. */
9898 return VINF_PGM_HANDLER_DO_DEFAULT;
9899}
9900
9901
9902# ifndef IN_RING3
9903/**
9904 * @callback_method_impl{FNPGMRZPHYSPFHANDLER,
9905 * \#PF access handler callback for guest VMX APIC-access page.}
9906 */
9907DECLCALLBACK(VBOXSTRICTRC) iemVmxApicAccessPagePfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
9908 RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser)
9909
9910{
9911 RT_NOREF3(pVM, pCtx, uUser);
9912
9913 /*
9914 * Handle the VMX APIC-access page only when the guest is in VMX non-root mode.
9915 * Otherwise we must deregister the page and allow regular RAM access.
9916 * Failing to do so lands us with endless EPT VM-exits.
9917 */
9918 RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
9919 if (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu)))
9920 {
9921 Assert(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(pVCpu), VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
9922 Assert(CPUMGetGuestVmxApicAccessPageAddrEx(IEM_GET_CTX(pVCpu)) == GCPhysPage);
9923
9924 /*
9925 * Check if the access causes an APIC-access VM-exit.
9926 */
9927 uint32_t fAccess;
9928 if (uErr & X86_TRAP_PF_ID)
9929 fAccess = IEM_ACCESS_INSTRUCTION;
9930 else if (uErr & X86_TRAP_PF_RW)
9931 fAccess = IEM_ACCESS_DATA_W;
9932 else
9933 fAccess = IEM_ACCESS_DATA_R;
9934
9935 RTGCPHYS const GCPhysNestedFault = (RTGCPHYS)pvFault;
9936 uint16_t const offAccess = GCPhysNestedFault & GUEST_PAGE_OFFSET_MASK;
9937 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, 1 /* cbAccess */, fAccess);
9938 LogFlowFunc(("#PF at %#RGp (GCPhysNestedFault=%#RGp offAccess=%#x)\n", GCPhysFault, GCPhysNestedFault, offAccess));
9939 if (fIntercept)
9940 {
9941 /*
9942 * Query the source VM-exit (from the execution engine) that caused this access
9943 * within the APIC-access page. Currently only HM is supported.
9944 */
9945 AssertMsg(VM_IS_HM_ENABLED(pVM),
9946 ("VM-exit auxiliary info. fetching not supported for execution engine %d\n", pVM->bMainExecutionEngine));
9947
9948 HMEXITAUX HmExitAux;
9949 RT_ZERO(HmExitAux);
9950 int const rc = HMR0GetExitAuxInfo(pVCpu, &HmExitAux, HMVMX_READ_EXIT_INSTR_LEN
9951 | HMVMX_READ_EXIT_QUALIFICATION
9952 | HMVMX_READ_IDT_VECTORING_INFO
9953 | HMVMX_READ_IDT_VECTORING_ERROR_CODE);
9954 AssertRC(rc);
9955
9956 /*
9957 * Verify the VM-exit reason must be an EPT violation.
9958 * Other accesses should go through the other handler (iemVmxApicAccessPageHandler).
9959 * Refer to @bugref{10092#c33s} for a more detailed explanation.
9960 */
9961 AssertMsgReturn(HmExitAux.Vmx.uReason == VMX_EXIT_EPT_VIOLATION,
9962 ("Unexpected call to APIC-access page #PF handler for %#RGp offAcesss=%u uErr=%#RGx uReason=%u\n",
9963 GCPhysPage, offAccess, uErr, HmExitAux.Vmx.uReason), VERR_IEM_IPE_7);
9964
9965 /*
9966 * Construct the virtual APIC-access VM-exit.
9967 */
9968 VMXAPICACCESS enmAccess;
9969 if (HmExitAux.Vmx.u64Qual & VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID)
9970 {
9971 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9972 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
9973 else if (fAccess == IEM_ACCESS_INSTRUCTION)
9974 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
9975 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
9976 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
9977 else
9978 enmAccess = VMXAPICACCESS_LINEAR_READ;
9979
9980 /* For linear-address accesss the instruction length must be valid. */
9981 AssertMsg(HmExitAux.Vmx.cbInstr > 0,
9982 ("Invalid APIC-access VM-exit instruction length. cbInstr=%u\n", HmExitAux.Vmx.cbInstr));
9983 }
9984 else
9985 {
9986 if (VMX_IDT_VECTORING_INFO_IS_VALID(HmExitAux.Vmx.uIdtVectoringInfo))
9987 enmAccess = VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY;
9988 else
9989 {
9990 /** @todo How to distinguish between monitoring/trace vs other instructions
9991 * here? */
9992 enmAccess = VMXAPICACCESS_PHYSICAL_INSTR;
9993 }
9994
9995 /* For physical accesses the instruction length is undefined, we zero it for safety and consistency. */
9996 HmExitAux.Vmx.cbInstr = 0;
9997 }
9998
9999 /*
10000 * Raise the APIC-access VM-exit.
10001 */
10002 LogFlowFunc(("Raising APIC-access VM-exit from #PF handler at offset %#x\n", offAccess));
10003 VMXVEXITINFO const ExitInfo
10004 = VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(VMX_EXIT_APIC_ACCESS,
10005 RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
10006 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess),
10007 HmExitAux.Vmx.cbInstr);
10008 VMXVEXITEVENTINFO const ExitEventInfo = VMXVEXITEVENTINFO_INIT_ONLY_IDT(HmExitAux.Vmx.uIdtVectoringInfo,
10009 HmExitAux.Vmx.uIdtVectoringErrCode);
10010 VBOXSTRICTRC const rcStrict = iemVmxVmexitApicAccessWithInfo(pVCpu, &ExitInfo, &ExitEventInfo);
10011 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
10012 }
10013
10014 /*
10015 * The access isn't intercepted, which means it needs to be virtualized.
10016 *
10017 * This requires emulating the instruction because we need the bytes being
10018 * read/written by the instruction not just the offset being accessed within
10019 * the APIC-access page (which we derive from the faulting address).
10020 */
10021 LogFlowFunc(("Access at offset %#x not intercepted -> VINF_EM_RAW_EMULATE_INSTR\n", offAccess));
10022 return VINF_EM_RAW_EMULATE_INSTR;
10023 }
10024
10025 /** @todo This isn't ideal but works for now as nested-hypervisors generally play
10026 * nice because the spec states that this page should be modified only when
10027 * no CPU refers to it VMX non-root mode. Nonetheless, we could use an atomic
10028 * reference counter to ensure the aforementioned condition before
10029 * de-registering the page. */
10030 LogFunc(("Accessed outside VMX non-root mode, deregistering page handler for %#RGp\n", GCPhysPage));
10031 int const rc = PGMHandlerPhysicalDeregister(pVM, GCPhysPage);
10032 if (RT_FAILURE(rc))
10033 return rc;
10034
10035 return VINF_SUCCESS;
10036}
10037# endif /* !IN_RING3 */
10038
10039#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
10040
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