IEMAllInstThree0f3a.cpp.h@ 105277

Last change on this file since 105277 was 105277, checked in by vboxsync, 5 months ago
VMM/IEM: Rework roundps/roundpd which only have two operands instead of three, add vroundps/vroundpd, bugref:9898 [build fix]
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1	/* $Id: IEMAllInstThree0f3a.cpp.h 105277 2024-07-11 17:13:59Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4	*
5	* @remarks IEMAllInstVexMap3.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
11	*
12	* This file is part of VirtualBox base platform packages, as
13	* available from https://www.virtualbox.org.
14	*
15	* This program is free software; you can redistribute it and/or
16	* modify it under the terms of the GNU General Public License
17	* as published by the Free Software Foundation, in version 3 of the
18	* License.
19	*
20	* This program is distributed in the hope that it will be useful, but
21	* WITHOUT ANY WARRANTY; without even the implied warranty of
22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23	* General Public License for more details.
24	*
25	* You should have received a copy of the GNU General Public License
26	* along with this program; if not, see <https://www.gnu.org/licenses>.
27	*
28	* SPDX-License-Identifier: GPL-3.0-only
29	*/
30
31
32	/** @name Three byte opcodes with first two bytes 0x0f 0x3a
33	* @{
34	*/
35
36	/**
37	* Common worker for SSSE3 instructions on the forms:
38	* pxxx xmm1, xmm2/mem128, imm8
39	*
40	* Proper alignment of the 128-bit operand is enforced.
41	* Exceptions type 4. SSSE3 cpuid checks.
42	*
43	* @sa iemOpCommonSse41_FullFullImm8_To_Full
44	*/
45	FNIEMOP_DEF_1(iemOpCommonSsse3_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
46	{
47	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48	if (IEM_IS_MODRM_REG_MODE(bRm))
49	{
50	/*
51	* Register, register.
52	*/
53	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
54	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
55	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
56	IEM_MC_ARG(PRTUINT128U, puDst, 0);
57	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
58	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
59	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
60	IEM_MC_PREPARE_SSE_USAGE();
61	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
62	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
63	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
64	IEM_MC_ADVANCE_RIP_AND_FINISH();
65	IEM_MC_END();
66	}
67	else
68	{
69	/*
70	* Register, memory.
71	*/
72	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
73	IEM_MC_ARG(PRTUINT128U, puDst, 0);
74	IEM_MC_LOCAL(RTUINT128U, uSrc);
75	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
76	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
77
78	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
79	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
80	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
81	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
82	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
83	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
84
85	IEM_MC_PREPARE_SSE_USAGE();
86	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
87	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
88
89	IEM_MC_ADVANCE_RIP_AND_FINISH();
90	IEM_MC_END();
91	}
92	}
93
94
95	/**
96	* Common worker for SSE 4.1 instructions on the forms:
97	* pxxx xmm1, xmm2/mem128, imm8
98	*
99	* Proper alignment of the 128-bit operand is enforced.
100	* No SIMD exceptions. SSE 4.1 cpuid checks.
101	*
102	* @sa iemOpCommonSsse3_FullFullImm8_To_Full
103	*/
104	FNIEMOP_DEF_1(iemOpCommonSse41_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
105	{
106	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
107	if (IEM_IS_MODRM_REG_MODE(bRm))
108	{
109	/*
110	* XMM, XMM, imm8
111	*/
112	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
113	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
114	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
115	IEM_MC_ARG(PRTUINT128U, puDst, 0);
116	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
117	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
118	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
119	IEM_MC_PREPARE_SSE_USAGE();
120	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
121	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
122	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
123	IEM_MC_ADVANCE_RIP_AND_FINISH();
124	IEM_MC_END();
125	}
126	else
127	{
128	/*
129	* XMM, [mem128], imm8.
130	*/
131	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
132	IEM_MC_ARG(PRTUINT128U, puDst, 0);
133	IEM_MC_LOCAL(RTUINT128U, uSrc);
134	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
135	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
136
137	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
138	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
139	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
140	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
141	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
142	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
143
144	IEM_MC_PREPARE_SSE_USAGE();
145	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
146	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
147
148	IEM_MC_ADVANCE_RIP_AND_FINISH();
149	IEM_MC_END();
150	}
151	}
152
153
154	/**
155	* Common worker for SSE 4.1 instructions of the form:
156	* xxx xmm1, xmm2/mem128, imm8
157	*
158	* Proper alignment of the 128-bit operand is enforced.
159	* MXCSR is used as input and output.
160	* Exceptions type 4. SSE 4.1 cpuid checks.
161	*
162	* @sa iemOpCommonSse41_FullFullImm8_To_Full
163	*/
164	FNIEMOP_DEF_1(iemOpCommonSse41Fp_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAF3XMMIMM8, pfnU128)
165	{
166	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
167	if (IEM_IS_MODRM_REG_MODE(bRm))
168	{
169	/*
170	* XMM, XMM, imm8.
171	*/
172	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
173	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
174	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
175	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
176	IEM_MC_LOCAL(X86XMMREG, Dst);
177	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 0);
178	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 1);
179	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
180	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
181	IEM_MC_PREPARE_SSE_USAGE();
182
183	IEM_MC_FETCH_XREG_PAIR_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
184	IEM_MC_CALL_SSE_AIMPL_3(pfnU128, pDst, pSrc, bImmArg);
185	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
186	IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
187
188	IEM_MC_ADVANCE_RIP_AND_FINISH();
189	IEM_MC_END();
190	}
191	else
192	{
193	/*
194	* XMM, [mem128], imm8.
195	*/
196	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
197	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
198	IEM_MC_LOCAL(X86XMMREG, Dst);
199	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 0);
200	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 1);
201	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
202
203	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
204	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
205	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
206	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
207	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
208	IEM_MC_PREPARE_SSE_USAGE();
209
210	IEM_MC_FETCH_MEM_XMM_ALIGN_SSE_AND_XREG_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
211	IEM_MC_CALL_SSE_AIMPL_3(pfnU128, pDst, pSrc, bImmArg);
212	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
213	IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
214
215	IEM_MC_ADVANCE_RIP_AND_FINISH();
216	IEM_MC_END();
217	}
218	}
219
220
221	/**
222	* Common worker for SSE 4.1 instructions of the form:
223	* xxx xmm1, xmm2/mem128, imm8
224	*
225	* Proper alignment of the 128-bit operand is enforced.
226	* MXCSR is used as input and output.
227	* Exceptions type 4. SSE 4.1 cpuid checks.
228	*
229	* @sa iemOpCommonSse41_FullFullImm8_To_Full
230	*/
231	FNIEMOP_DEF_1(iemOpCommonSse41Fp_FullImm8_To_Full, PFNIEMAIMPLMEDIAF2U128IMM8, pfnU128)
232	{
233	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
234	if (IEM_IS_MODRM_REG_MODE(bRm))
235	{
236	/*
237	* XMM, XMM, imm8.
238	*/
239	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
240	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
241	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
242	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
243	IEM_MC_PREPARE_SSE_USAGE();
244	IEM_MC_LOCAL(X86XMMREG, uDst);
245	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
246	IEM_MC_ARG( PCX86XMMREG, puSrc, 1);
247	IEM_MC_REF_XREG_XMM_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
248	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
249	IEM_MC_CALL_SSE_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
250	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
251	IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
252	IEM_MC_ADVANCE_RIP_AND_FINISH();
253	IEM_MC_END();
254	}
255	else
256	{
257	/*
258	* XMM, [mem128], imm8.
259	*/
260	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
261	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
262	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
263	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
264	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
265	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
266	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
267	IEM_MC_PREPARE_SSE_USAGE();
268	IEM_MC_LOCAL(X86XMMREG, uSrc);
269	IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
270	IEM_MC_LOCAL(X86XMMREG, uDst);
271	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
272	IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc, uSrc, 1);
273	IEM_MC_CALL_SSE_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
274	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
275	IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
276	IEM_MC_ADVANCE_RIP_AND_FINISH();
277	IEM_MC_END();
278	}
279	}
280
281
282	/**
283	* Common worker for SSE-style AES-NI instructions of the form:
284	* aesxxx xmm1, xmm2/mem128, imm8
285	*
286	* Proper alignment of the 128-bit operand is enforced.
287	* Exceptions type 4. AES-NI cpuid checks.
288	*
289	* @sa iemOpCommonSsse3_FullFullImm8_To_Full
290	* @sa iemOpCommonSse41_FullFullImm8_To_Full
291	*/
292	FNIEMOP_DEF_1(iemOpCommonAesNi_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
293	{
294	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
295	if (IEM_IS_MODRM_REG_MODE(bRm))
296	{
297	/*
298	* Register, register.
299	*/
300	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
301	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
302	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
303	IEM_MC_ARG(PRTUINT128U, puDst, 0);
304	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
305	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
306	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
307	IEM_MC_PREPARE_SSE_USAGE();
308	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
309	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
310	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
311	IEM_MC_ADVANCE_RIP_AND_FINISH();
312	IEM_MC_END();
313	}
314	else
315	{
316	/*
317	* Register, memory.
318	*/
319	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
320	IEM_MC_ARG(PRTUINT128U, puDst, 0);
321	IEM_MC_LOCAL(RTUINT128U, uSrc);
322	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
323	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
324
325	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
326	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
327	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
328	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
329	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
330	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
331
332	IEM_MC_PREPARE_SSE_USAGE();
333	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
334	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
335
336	IEM_MC_ADVANCE_RIP_AND_FINISH();
337	IEM_MC_END();
338	}
339	}
340
341
342	/** Opcode 0x66 0x0f 0x00 - invalid (vex only). */
343	/** Opcode 0x66 0x0f 0x01 - invalid (vex only). */
344	/** Opcode 0x66 0x0f 0x02 - invalid (vex only). */
345	/* Opcode 0x66 0x0f 0x03 - invalid */
346	/** Opcode 0x66 0x0f 0x04 - invalid (vex only). */
347	/** Opcode 0x66 0x0f 0x05 - invalid (vex only). */
348	/* Opcode 0x66 0x0f 0x06 - invalid (vex only) */
349	/* Opcode 0x66 0x0f 0x07 - invalid */
350	/** Opcode 0x66 0x0f 0x08. */
351	FNIEMOP_DEF(iemOp_roundps_Vx_Wx_Ib)
352	{
353	IEMOP_MNEMONIC3(RMI, ROUNDPS, roundps, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
354	return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullImm8_To_Full,
355	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback));
356	}
357
358
359	/** Opcode 0x66 0x0f 0x09. */
360	FNIEMOP_DEF(iemOp_roundpd_Vx_Wx_Ib)
361	{
362	IEMOP_MNEMONIC3(RMI, ROUNDPD, roundpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
363	return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullImm8_To_Full,
364	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback));
365	}
366
367
368	/** Opcode 0x66 0x0f 0x0a. */
369	FNIEMOP_DEF(iemOp_roundss_Vss_Wss_Ib)
370	{
371	/* The instruction form is very similar to CMPSS. */
372	IEMOP_MNEMONIC3(RMI, ROUNDSS, roundss, Vss, Wss, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
373
374	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
375	if (IEM_IS_MODRM_REG_MODE(bRm))
376	{
377	/*
378	* XMM32, XMM32.
379	*/
380	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
381	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
382	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
383	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
384	IEM_MC_LOCAL(X86XMMREG, Dst);
385	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 0);
386	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 1);
387	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
388	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
389	IEM_MC_PREPARE_SSE_USAGE();
390	IEM_MC_FETCH_XREG_PAIR_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
391	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_roundss_u128, pDst, pSrc, bImmArg);
392	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
393	IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /a_iDword/, Dst);
394
395	IEM_MC_ADVANCE_RIP_AND_FINISH();
396	IEM_MC_END();
397	}
398	else
399	{
400	/*
401	* XMM32, [mem32].
402	*/
403	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
404	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
405	IEM_MC_LOCAL(X86XMMREG, Dst);
406	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 0);
407	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 1);
408	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
409
410	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
411	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
412	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
413	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
414	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
415	IEM_MC_PREPARE_SSE_USAGE();
416
417	IEM_MC_FETCH_MEM_XMM_U32_AND_XREG_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm),
418	0 /a_iDword/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
419	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_roundss_u128, pDst, pSrc, bImmArg);
420	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
421	IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /a_iDword/, Dst);
422
423	IEM_MC_ADVANCE_RIP_AND_FINISH();
424	IEM_MC_END();
425	}
426	}
427
428	/** Opcode 0x66 0x0f 0x0b. */
429	FNIEMOP_DEF(iemOp_roundsd_Vsd_Wsd_Ib)
430	{
431	/* The instruction form is very similar to CMPSD. */
432	IEMOP_MNEMONIC3(RMI, ROUNDSD, roundsd, Vsd, Wsd, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
433
434	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
435	if (IEM_IS_MODRM_REG_MODE(bRm))
436	{
437	/*
438	* XMM64, XMM64, imm8.
439	*/
440	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
441	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
442	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
443	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
444	IEM_MC_LOCAL(X86XMMREG, Dst);
445	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 0);
446	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 1);
447	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
448	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
449	IEM_MC_PREPARE_SSE_USAGE();
450	IEM_MC_FETCH_XREG_PAIR_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
451	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_roundsd_u128, pDst, pSrc, bImmArg);
452	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
453	IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /a_iQword/, Dst);
454
455	IEM_MC_ADVANCE_RIP_AND_FINISH();
456	IEM_MC_END();
457	}
458	else
459	{
460	/*
461	* XMM64, [mem64], imm8.
462	*/
463	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
464	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
465	IEM_MC_LOCAL(X86XMMREG, Dst);
466	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 0);
467	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 1);
468	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
469
470	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
471	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
472	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
473	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
474	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
475	IEM_MC_PREPARE_SSE_USAGE();
476
477	IEM_MC_FETCH_MEM_XMM_U64_AND_XREG_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm),
478	0 /a_iQword /, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
479	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_roundsd_u128, pDst, pSrc, bImmArg);
480	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
481	IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /a_iQword/, Dst);
482
483	IEM_MC_ADVANCE_RIP_AND_FINISH();
484	IEM_MC_END();
485	}
486	}
487
488
489	/** Opcode 0x66 0x0f 0x0c. */
490	FNIEMOP_DEF(iemOp_blendps_Vx_Wx_Ib)
491	{
492	IEMOP_MNEMONIC3(RMI, BLENDPS, blendps, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
493	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
494	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback));
495	}
496
497
498	/** Opcode 0x66 0x0f 0x0d. */
499	FNIEMOP_DEF(iemOp_blendpd_Vx_Wx_Ib)
500	{
501	IEMOP_MNEMONIC3(RMI, BLENDPD, blendpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
502	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
503	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback));
504	}
505
506
507	/** Opcode 0x66 0x0f 0x0e. */
508	FNIEMOP_DEF(iemOp_pblendw_Vx_Wx_Ib)
509	{
510	IEMOP_MNEMONIC3(RMI, PBLENDW, pblendw, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
511	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
512	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback));
513	}
514
515
516	/** Opcode 0x0f 0x0f. */
517	FNIEMOP_DEF(iemOp_palignr_Pq_Qq_Ib)
518	{
519	IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Pq, Qq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
520	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
521	if (IEM_IS_MODRM_REG_MODE(bRm))
522	{
523	/*
524	* Register, register.
525	*/
526	/** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
527	/** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
528	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
529	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
530	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
531	IEM_MC_ARG(uint64_t *, pDst, 0);
532	IEM_MC_ARG(uint64_t, uSrc, 1);
533	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
534	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
535	IEM_MC_PREPARE_FPU_USAGE();
536	IEM_MC_FPU_TO_MMX_MODE();
537	IEM_MC_FETCH_MREG_U64(uSrc, IEM_GET_MODRM_RM_8(bRm));
538	IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
539	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
540	pDst, uSrc, bImmArg);
541	IEM_MC_MODIFIED_MREG_BY_REF(pDst);
542	IEM_MC_ADVANCE_RIP_AND_FINISH();
543	IEM_MC_END();
544	}
545	else
546	{
547	/*
548	* Register, memory.
549	*/
550	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
551	IEM_MC_ARG(uint64_t *, pDst, 0);
552	IEM_MC_ARG(uint64_t, uSrc, 1);
553	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
554
555	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
556	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
557	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
558	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
559	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
560	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
561
562	IEM_MC_PREPARE_FPU_USAGE();
563	IEM_MC_FPU_TO_MMX_MODE();
564	IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
565	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
566	pDst, uSrc, bImmArg);
567	IEM_MC_MODIFIED_MREG_BY_REF(pDst);
568
569	IEM_MC_ADVANCE_RIP_AND_FINISH();
570	IEM_MC_END();
571	}
572	}
573
574
575	/** Opcode 0x66 0x0f 0x0f. */
576	FNIEMOP_DEF(iemOp_palignr_Vx_Wx_Ib)
577	{
578	IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
579	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFullImm8_To_Full,
580	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback));
581	}
582
583
584	/* Opcode 0x66 0x0f 0x10 - invalid */
585	/* Opcode 0x66 0x0f 0x11 - invalid */
586	/* Opcode 0x66 0x0f 0x12 - invalid */
587	/* Opcode 0x66 0x0f 0x13 - invalid */
588
589
590	/** Opcode 0x66 0x0f 0x14. */
591	FNIEMOP_DEF(iemOp_pextrb_RdMb_Vdq_Ib)
592	{
593	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
594	IEMOP_MNEMONIC3(MRI, PEXTRB, pextrb, Ev, Vq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
595	if (IEM_IS_MODRM_REG_MODE(bRm))
596	{
597	/*
598	* greg32, XMM.
599	*/
600	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
601	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
602	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
603	IEM_MC_LOCAL(uint8_t, uValue);
604	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
605	IEM_MC_PREPARE_SSE_USAGE();
606	IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /a_iByte/);
607	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
608	IEM_MC_ADVANCE_RIP_AND_FINISH();
609	IEM_MC_END();
610	}
611	else
612	{
613	/*
614	* [mem8], XMM.
615	*/
616	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
617	IEM_MC_LOCAL(uint8_t, uValue);
618	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
619
620	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
621	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
622	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
623	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
624	IEM_MC_PREPARE_SSE_USAGE();
625
626	IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /a_iByte/);
627	IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
628	IEM_MC_ADVANCE_RIP_AND_FINISH();
629	IEM_MC_END();
630	}
631	}
632
633
634	/** Opcode 0x66 0x0f 0x15. */
635	FNIEMOP_DEF(iemOp_pextrw_RdMw_Vdq_Ib)
636	{
637	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
638	IEMOP_MNEMONIC3(MRI, PEXTRW, pextrw, Ev, Vq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
639	if (IEM_IS_MODRM_REG_MODE(bRm))
640	{
641	/*
642	* greg32, XMM.
643	*/
644	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
645	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
646	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
647	IEM_MC_LOCAL(uint16_t, uValue);
648	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
649	IEM_MC_PREPARE_SSE_USAGE();
650	IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7 /a_iWord/);
651	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
652	IEM_MC_ADVANCE_RIP_AND_FINISH();
653	IEM_MC_END();
654	}
655	else
656	{
657	/*
658	* [mem16], XMM.
659	*/
660	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
661	IEM_MC_LOCAL(uint16_t, uValue);
662	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
663
664	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
665	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
666	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
667	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
668	IEM_MC_PREPARE_SSE_USAGE();
669
670	IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7 /a_iWord/);
671	IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
672	IEM_MC_ADVANCE_RIP_AND_FINISH();
673	IEM_MC_END();
674	}
675	}
676
677
678	FNIEMOP_DEF(iemOp_pextrd_q_RdMw_Vdq_Ib)
679	{
680	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
681	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
682	{
683	/**
684	* @opcode 0x16
685	* @opcodesub rex.w=1
686	* @oppfx 0x66
687	* @opcpuid sse
688	*/
689	IEMOP_MNEMONIC3(MRI, PEXTRQ, pextrq, Ev, Vq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
690	if (IEM_IS_MODRM_REG_MODE(bRm))
691	{
692	/*
693	* greg64, XMM.
694	*/
695	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
696	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
697	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
698	IEM_MC_LOCAL(uint64_t, uSrc);
699	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
700	IEM_MC_PREPARE_SSE_USAGE();
701	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /a_iQword/);
702	IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
703	IEM_MC_ADVANCE_RIP_AND_FINISH();
704	IEM_MC_END();
705	}
706	else
707	{
708	/*
709	* [mem64], XMM.
710	*/
711	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
712	IEM_MC_LOCAL(uint64_t, uSrc);
713	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
714
715	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
716	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
717	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
718	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
719	IEM_MC_PREPARE_SSE_USAGE();
720
721	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /a_iQword/);
722	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
723	IEM_MC_ADVANCE_RIP_AND_FINISH();
724	IEM_MC_END();
725	}
726	}
727	else
728	{
729	/**
730	* @opdone
731	* @opcode 0x16
732	* @opcodesub rex.w=0
733	* @oppfx 0x66
734	* @opcpuid sse
735	*/
736	IEMOP_MNEMONIC3(MRI, PEXTRD, pextrd, Ey, Vd, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
737	if (IEM_IS_MODRM_REG_MODE(bRm))
738	{
739	/*
740	* greg32, XMM.
741	*/
742	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
743	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
744	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
745	IEM_MC_LOCAL(uint32_t, uSrc);
746	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
747	IEM_MC_PREPARE_SSE_USAGE();
748	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /a_iDword/);
749	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
750	IEM_MC_ADVANCE_RIP_AND_FINISH();
751	IEM_MC_END();
752	}
753	else
754	{
755	/*
756	* [mem32], XMM.
757	*/
758	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
759	IEM_MC_LOCAL(uint32_t, uSrc);
760	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
761
762	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
763	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
764	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
765	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
766	IEM_MC_PREPARE_SSE_USAGE();
767	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /a_iDword/);
768	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
769	IEM_MC_ADVANCE_RIP_AND_FINISH();
770	IEM_MC_END();
771	}
772	}
773	}
774
775
776	/** Opcode 0x66 0x0f 0x17. */
777	FNIEMOP_DEF(iemOp_extractps_Ed_Vdq_Ib)
778	{
779	IEMOP_MNEMONIC3(MRI, EXTRACTPS, extractps, Ed, Vdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
780	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
781	if (IEM_IS_MODRM_REG_MODE(bRm))
782	{
783	/*
784	* greg32, XMM.
785	*/
786	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
787	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
788	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
789	IEM_MC_LOCAL(uint32_t, uSrc);
790	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
791	IEM_MC_PREPARE_SSE_USAGE();
792	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /a_iDword/);
793	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
794	IEM_MC_ADVANCE_RIP_AND_FINISH();
795	IEM_MC_END();
796	}
797	else
798	{
799	/*
800	* [mem32], XMM.
801	*/
802	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
803	IEM_MC_LOCAL(uint32_t, uSrc);
804	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
805
806	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
807	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
808	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
809	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
810	IEM_MC_PREPARE_SSE_USAGE();
811	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /a_iDword/);
812	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
813	IEM_MC_ADVANCE_RIP_AND_FINISH();
814	IEM_MC_END();
815	}
816	}
817
818
819	/* Opcode 0x66 0x0f 0x18 - invalid (vex only). */
820	/* Opcode 0x66 0x0f 0x19 - invalid (vex only). */
821	/* Opcode 0x66 0x0f 0x1a - invalid */
822	/* Opcode 0x66 0x0f 0x1b - invalid */
823	/* Opcode 0x66 0x0f 0x1c - invalid */
824	/* Opcode 0x66 0x0f 0x1d - invalid (vex only). */
825	/* Opcode 0x66 0x0f 0x1e - invalid */
826	/* Opcode 0x66 0x0f 0x1f - invalid */
827
828
829	/** Opcode 0x66 0x0f 0x20. */
830	FNIEMOP_DEF(iemOp_pinsrb_Vdq_RyMb_Ib)
831	{
832	IEMOP_MNEMONIC3(RMI, PINSRB, pinsrb, Vd, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
833	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
834	if (IEM_IS_MODRM_REG_MODE(bRm))
835	{
836	/*
837	* XMM, greg32.
838	*/
839	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
840	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
841	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
842	IEM_MC_LOCAL(uint8_t, uSrc);
843	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
844	IEM_MC_PREPARE_SSE_USAGE();
845	IEM_MC_FETCH_GREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
846	IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /a_iByte/, uSrc);
847	IEM_MC_ADVANCE_RIP_AND_FINISH();
848	IEM_MC_END();
849	}
850	else
851	{
852	/*
853	* XMM, [mem8].
854	*/
855	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
856	IEM_MC_LOCAL(uint8_t, uSrc);
857	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
858
859	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
860	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
861	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
862	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
863	IEM_MC_PREPARE_SSE_USAGE();
864
865	IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
866	IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /a_iByte/, uSrc);
867	IEM_MC_ADVANCE_RIP_AND_FINISH();
868	IEM_MC_END();
869	}
870	}
871
872	/** Opcode 0x66 0x0f 0x21, */
873	FNIEMOP_DEF(iemOp_insertps_Vdq_UdqMd_Ib)
874	{
875	IEMOP_MNEMONIC3(RMI, INSERTPS, insertps, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0); /// @todo
876	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
877	if (IEM_IS_MODRM_REG_MODE(bRm))
878	{
879	/*
880	* XMM, XMM.
881	*/
882	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
883	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
884	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
885	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
886	IEM_MC_PREPARE_SSE_USAGE();
887
888	IEM_MC_LOCAL(uint32_t, uSrc);
889	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), (bImm >> 6) & 3);
890	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), (bImm >> 4) & 3, uSrc);
891	IEM_MC_CLEAR_XREG_U32_MASK(IEM_GET_MODRM_REG(pVCpu, bRm), bImm);
892
893	IEM_MC_ADVANCE_RIP_AND_FINISH();
894	IEM_MC_END();
895	}
896	else
897	{
898	/*
899	* XMM, [mem32].
900	*/
901	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
902	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
903	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
904	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
905
906	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
907	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
908	IEM_MC_PREPARE_SSE_USAGE();
909
910	IEM_MC_LOCAL(uint32_t, uSrc);
911	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
912	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), (bImm >> 4) & 3, uSrc);
913	IEM_MC_CLEAR_XREG_U32_MASK(IEM_GET_MODRM_REG(pVCpu, bRm), bImm);
914	IEM_MC_ADVANCE_RIP_AND_FINISH();
915	IEM_MC_END();
916	}
917	}
918
919	FNIEMOP_DEF(iemOp_pinsrd_q_Vdq_Ey_Ib)
920	{
921	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
922	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
923	{
924	/**
925	* @opcode 0x22
926	* @opcodesub rex.w=1
927	* @oppfx 0x66
928	* @opcpuid sse
929	*/
930	IEMOP_MNEMONIC3(RMI, PINSRQ, pinsrq, Vq, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
931	if (IEM_IS_MODRM_REG_MODE(bRm))
932	{
933	/*
934	* XMM, greg64.
935	*/
936	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
937	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
938	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
939	IEM_MC_LOCAL(uint64_t, uSrc);
940	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
941	IEM_MC_PREPARE_SSE_USAGE();
942	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
943	IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /a_iQword/, uSrc);
944	IEM_MC_ADVANCE_RIP_AND_FINISH();
945	IEM_MC_END();
946	}
947	else
948	{
949	/*
950	* XMM, [mem64].
951	*/
952	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
953	IEM_MC_LOCAL(uint64_t, uSrc);
954	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
955
956	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
957	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
958	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
959	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
960	IEM_MC_PREPARE_SSE_USAGE();
961
962	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
963	IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /a_iQword/, uSrc);
964	IEM_MC_ADVANCE_RIP_AND_FINISH();
965	IEM_MC_END();
966	}
967	}
968	else
969	{
970	/**
971	* @opdone
972	* @opcode 0x22
973	* @opcodesub rex.w=0
974	* @oppfx 0x66
975	* @opcpuid sse
976	*/
977	IEMOP_MNEMONIC3(RMI, PINSRD, pinsrd, Vd, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
978	if (IEM_IS_MODRM_REG_MODE(bRm))
979	{
980	/*
981	* XMM, greg32.
982	*/
983	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
984	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
985	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
986	IEM_MC_LOCAL(uint32_t, uSrc);
987	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
988	IEM_MC_PREPARE_SSE_USAGE();
989	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
990	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /a_iDword/, uSrc);
991	IEM_MC_ADVANCE_RIP_AND_FINISH();
992	IEM_MC_END();
993	}
994	else
995	{
996	/*
997	* XMM, [mem32].
998	*/
999	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1000	IEM_MC_LOCAL(uint32_t, uSrc);
1001	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1002
1003	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1004	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1005	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
1006	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1007	IEM_MC_PREPARE_SSE_USAGE();
1008
1009	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1010	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /a_iDword/, uSrc);
1011	IEM_MC_ADVANCE_RIP_AND_FINISH();
1012	IEM_MC_END();
1013	}
1014	}
1015	}
1016
1017
1018	/* Opcode 0x66 0x0f 0x23 - invalid */
1019	/* Opcode 0x66 0x0f 0x24 - invalid */
1020	/* Opcode 0x66 0x0f 0x25 - invalid */
1021	/* Opcode 0x66 0x0f 0x26 - invalid */
1022	/* Opcode 0x66 0x0f 0x27 - invalid */
1023	/* Opcode 0x66 0x0f 0x28 - invalid */
1024	/* Opcode 0x66 0x0f 0x29 - invalid */
1025	/* Opcode 0x66 0x0f 0x2a - invalid */
1026	/* Opcode 0x66 0x0f 0x2b - invalid */
1027	/* Opcode 0x66 0x0f 0x2c - invalid */
1028	/* Opcode 0x66 0x0f 0x2d - invalid */
1029	/* Opcode 0x66 0x0f 0x2e - invalid */
1030	/* Opcode 0x66 0x0f 0x2f - invalid */
1031
1032
1033	/* Opcode 0x66 0x0f 0x30 - invalid */
1034	/* Opcode 0x66 0x0f 0x31 - invalid */
1035	/* Opcode 0x66 0x0f 0x32 - invalid */
1036	/* Opcode 0x66 0x0f 0x33 - invalid */
1037	/* Opcode 0x66 0x0f 0x34 - invalid */
1038	/* Opcode 0x66 0x0f 0x35 - invalid */
1039	/* Opcode 0x66 0x0f 0x36 - invalid */
1040	/* Opcode 0x66 0x0f 0x37 - invalid */
1041	/* Opcode 0x66 0x0f 0x38 - invalid (vex only). */
1042	/* Opcode 0x66 0x0f 0x39 - invalid (vex only). */
1043	/* Opcode 0x66 0x0f 0x3a - invalid */
1044	/* Opcode 0x66 0x0f 0x3b - invalid */
1045	/* Opcode 0x66 0x0f 0x3c - invalid */
1046	/* Opcode 0x66 0x0f 0x3d - invalid */
1047	/* Opcode 0x66 0x0f 0x3e - invalid */
1048	/* Opcode 0x66 0x0f 0x3f - invalid */
1049
1050
1051	/** Opcode 0x66 0x0f 0x40. */
1052	FNIEMOP_DEF(iemOp_dpps_Vx_Wx_Ib)
1053	{
1054	IEMOP_MNEMONIC3(RMI, DPPS, dpps, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1055	return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
1056	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback));
1057	}
1058
1059
1060	/** Opcode 0x66 0x0f 0x41, */
1061	FNIEMOP_DEF(iemOp_dppd_Vdq_Wdq_Ib)
1062	{
1063	IEMOP_MNEMONIC3(RMI, DPPD, dppd, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1064	return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
1065	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback));
1066	}
1067
1068
1069	/** Opcode 0x66 0x0f 0x42. */
1070	FNIEMOP_DEF(iemOp_mpsadbw_Vx_Wx_Ib)
1071	{
1072	IEMOP_MNEMONIC3(RMI, MPSADBW, mpsadbw, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1073	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
1074	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback));
1075	}
1076
1077
1078	/* Opcode 0x66 0x0f 0x43 - invalid */
1079
1080
1081	/** Opcode 0x66 0x0f 0x44. */
1082	FNIEMOP_DEF(iemOp_pclmulqdq_Vdq_Wdq_Ib)
1083	{
1084	IEMOP_MNEMONIC3(RMI, PCLMULQDQ, pclmulqdq, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1085
1086	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1087	if (IEM_IS_MODRM_REG_MODE(bRm))
1088	{
1089	/*
1090	* Register, register.
1091	*/
1092	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1093	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1094	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fPclMul);
1095	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1096	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1097	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
1098	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1099	IEM_MC_PREPARE_SSE_USAGE();
1100	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1101	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1102	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
1103	iemAImpl_pclmulqdq_u128,
1104	iemAImpl_pclmulqdq_u128_fallback),
1105	puDst, puSrc, bImmArg);
1106	IEM_MC_ADVANCE_RIP_AND_FINISH();
1107	IEM_MC_END();
1108	}
1109	else
1110	{
1111	/*
1112	* Register, memory.
1113	*/
1114	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1115	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1116	IEM_MC_LOCAL(RTUINT128U, uSrc);
1117	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1118	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1119
1120	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1121	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1122	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
1123	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fPclMul);
1124	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1125	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1126
1127	IEM_MC_PREPARE_SSE_USAGE();
1128	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1129	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
1130	iemAImpl_pclmulqdq_u128,
1131	iemAImpl_pclmulqdq_u128_fallback),
1132	puDst, puSrc, bImmArg);
1133
1134	IEM_MC_ADVANCE_RIP_AND_FINISH();
1135	IEM_MC_END();
1136	}
1137	}
1138
1139
1140	/* Opcode 0x66 0x0f 0x45 - invalid */
1141	/* Opcode 0x66 0x0f 0x46 - invalid (vex only) */
1142	/* Opcode 0x66 0x0f 0x47 - invalid */
1143	/* Opcode 0x66 0x0f 0x48 - invalid */
1144	/* Opcode 0x66 0x0f 0x49 - invalid */
1145	/* Opcode 0x66 0x0f 0x4a - invalid (vex only). */
1146	/* Opcode 0x66 0x0f 0x4b - invalid (vex only). */
1147	/* Opcode 0x66 0x0f 0x4c - invalid (vex only). */
1148	/* Opcode 0x66 0x0f 0x4d - invalid */
1149	/* Opcode 0x66 0x0f 0x4e - invalid */
1150	/* Opcode 0x66 0x0f 0x4f - invalid */
1151
1152
1153	/* Opcode 0x66 0x0f 0x50 - invalid */
1154	/* Opcode 0x66 0x0f 0x51 - invalid */
1155	/* Opcode 0x66 0x0f 0x52 - invalid */
1156	/* Opcode 0x66 0x0f 0x53 - invalid */
1157	/* Opcode 0x66 0x0f 0x54 - invalid */
1158	/* Opcode 0x66 0x0f 0x55 - invalid */
1159	/* Opcode 0x66 0x0f 0x56 - invalid */
1160	/* Opcode 0x66 0x0f 0x57 - invalid */
1161	/* Opcode 0x66 0x0f 0x58 - invalid */
1162	/* Opcode 0x66 0x0f 0x59 - invalid */
1163	/* Opcode 0x66 0x0f 0x5a - invalid */
1164	/* Opcode 0x66 0x0f 0x5b - invalid */
1165	/* Opcode 0x66 0x0f 0x5c - invalid */
1166	/* Opcode 0x66 0x0f 0x5d - invalid */
1167	/* Opcode 0x66 0x0f 0x5e - invalid */
1168	/* Opcode 0x66 0x0f 0x5f - invalid */
1169
1170
1171	/**
1172	* @opcode 0x60
1173	* @oppfx 0x66
1174	* @opflmodify cf,pf,af,zf,sf,of
1175	* @opflclear pf,af
1176	*/
1177	FNIEMOP_DEF(iemOp_pcmpestrm_Vdq_Wdq_Ib)
1178	{
1179	IEMOP_MNEMONIC3(RMI, PCMPESTRM, pcmpestrm, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1180
1181	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1182	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1183	{
1184	if (IEM_IS_MODRM_REG_MODE(bRm))
1185	{
1186	/*
1187	* Register, register.
1188	*/
1189	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1190	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1191	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1192	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1193	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1194	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1195	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1196	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1197	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1198	IEM_MC_PREPARE_SSE_USAGE();
1199	IEM_MC_FETCH_XREG_PAIR_U128_AND_RAX_RDX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
1200	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1201	IEM_MC_REF_EFLAGS(pEFlags);
1202	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1203	iemAImpl_pcmpestrm_u128,
1204	iemAImpl_pcmpestrm_u128_fallback),
1205	puDst, pEFlags, pSrc, bImmArg);
1206	IEM_MC_ADVANCE_RIP_AND_FINISH();
1207	IEM_MC_END();
1208	}
1209	else
1210	{
1211	/*
1212	* Register, memory.
1213	*/
1214	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1215	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1216	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1217	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1218	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1219	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1220
1221	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1222	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1223	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1224	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1225	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1226	IEM_MC_PREPARE_SSE_USAGE();
1227
1228	IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_RAX_RDX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm),
1229	pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1230	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1231	IEM_MC_REF_EFLAGS(pEFlags);
1232	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1233	iemAImpl_pcmpestrm_u128,
1234	iemAImpl_pcmpestrm_u128_fallback),
1235	puDst, pEFlags, pSrc, bImmArg);
1236	IEM_MC_ADVANCE_RIP_AND_FINISH();
1237	IEM_MC_END();
1238	}
1239	}
1240	else
1241	{
1242	if (IEM_IS_MODRM_REG_MODE(bRm))
1243	{
1244	/*
1245	* Register, register.
1246	*/
1247	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1248	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1249	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1250	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1251	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1252	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1253	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1254	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1255	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1256	IEM_MC_PREPARE_SSE_USAGE();
1257	IEM_MC_FETCH_XREG_PAIR_U128_AND_EAX_EDX_U32_SX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
1258	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1259	IEM_MC_REF_EFLAGS(pEFlags);
1260	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1261	iemAImpl_pcmpestrm_u128,
1262	iemAImpl_pcmpestrm_u128_fallback),
1263	puDst, pEFlags, pSrc, bImmArg);
1264	IEM_MC_ADVANCE_RIP_AND_FINISH();
1265	IEM_MC_END();
1266	}
1267	else
1268	{
1269	/*
1270	* Register, memory.
1271	*/
1272	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1273	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1274	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1275	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1276	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1277	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1278
1279	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1280	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1281	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1282	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1283	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1284	IEM_MC_PREPARE_SSE_USAGE();
1285
1286	IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm),
1287	pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1288	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1289	IEM_MC_REF_EFLAGS(pEFlags);
1290	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1291	iemAImpl_pcmpestrm_u128,
1292	iemAImpl_pcmpestrm_u128_fallback),
1293	puDst, pEFlags, pSrc, bImmArg);
1294	IEM_MC_ADVANCE_RIP_AND_FINISH();
1295	IEM_MC_END();
1296	}
1297	}
1298	}
1299
1300
1301	/**
1302	* @opcode 0x61
1303	* @oppfx 0x66
1304	* @opflmodify cf,pf,af,zf,sf,of
1305	* @opflclear pf,af
1306	*/
1307	FNIEMOP_DEF(iemOp_pcmpestri_Vdq_Wdq_Ib)
1308	{
1309	IEMOP_MNEMONIC3(RMI, PCMPESTRI, pcmpestri, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1310
1311	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1312	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1313	{
1314	if (IEM_IS_MODRM_REG_MODE(bRm))
1315	{
1316	/*
1317	* Register, register.
1318	*/
1319	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1320	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1321	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1322	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1323	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1324	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1325	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1326	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1327	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1328	IEM_MC_PREPARE_SSE_USAGE();
1329	IEM_MC_FETCH_XREG_PAIR_U128_AND_RAX_RDX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
1330	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1331	IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX);
1332	IEM_MC_REF_EFLAGS(pEFlags);
1333	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1334	iemAImpl_pcmpestri_u128,
1335	iemAImpl_pcmpestri_u128_fallback),
1336	pu32Ecx, pEFlags, pSrc, bImmArg);
1337	/** @todo testcase: High dword of RCX cleared? */
1338	IEM_MC_ADVANCE_RIP_AND_FINISH();
1339	IEM_MC_END();
1340	}
1341	else
1342	{
1343	/*
1344	* Register, memory.
1345	*/
1346	IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1347	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1348	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1349	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1350	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1351	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1352
1353	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1354	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1355	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1356	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1357	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1358	IEM_MC_PREPARE_SSE_USAGE();
1359
1360	IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_RAX_RDX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm),
1361	pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1362	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1363	IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX);
1364	IEM_MC_REF_EFLAGS(pEFlags);
1365	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1366	iemAImpl_pcmpestri_u128,
1367	iemAImpl_pcmpestri_u128_fallback),
1368	pu32Ecx, pEFlags, pSrc, bImmArg);
1369	/** @todo testcase: High dword of RCX cleared? */
1370	IEM_MC_ADVANCE_RIP_AND_FINISH();
1371	IEM_MC_END();
1372	}
1373	}
1374	else
1375	{
1376	if (IEM_IS_MODRM_REG_MODE(bRm))
1377	{
1378	/*
1379	* Register, register.
1380	*/
1381	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1382	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1383	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1384	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1385	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1386	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1387	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1388	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1389	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1390	IEM_MC_PREPARE_SSE_USAGE();
1391	IEM_MC_FETCH_XREG_PAIR_U128_AND_EAX_EDX_U32_SX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
1392	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1393	IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX);
1394	IEM_MC_REF_EFLAGS(pEFlags);
1395	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1396	iemAImpl_pcmpestri_u128,
1397	iemAImpl_pcmpestri_u128_fallback),
1398	pu32Ecx, pEFlags, pSrc, bImmArg);
1399	/** @todo testcase: High dword of RCX cleared? */
1400	IEM_MC_ADVANCE_RIP_AND_FINISH();
1401	IEM_MC_END();
1402	}
1403	else
1404	{
1405	/*
1406	* Register, memory.
1407	*/
1408	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1409	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1410	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1411	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1412	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1413	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1414
1415	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1416	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1417	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1418	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1419	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1420	IEM_MC_PREPARE_SSE_USAGE();
1421
1422	IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(Src, IEM_GET_MODRM_REG(pVCpu, bRm),
1423	pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1424	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1425	IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX);
1426	IEM_MC_REF_EFLAGS(pEFlags);
1427	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1428	iemAImpl_pcmpestri_u128,
1429	iemAImpl_pcmpestri_u128_fallback),
1430	pu32Ecx, pEFlags, pSrc, bImmArg);
1431	/** @todo testcase: High dword of RCX cleared? */
1432	IEM_MC_ADVANCE_RIP_AND_FINISH();
1433	IEM_MC_END();
1434	}
1435	}
1436	}
1437
1438
1439	/**
1440	* @opcode 0x62
1441	* @oppfx 0x66
1442	* @opflmodify cf,pf,af,zf,sf,of
1443	* @opflclear pf,af
1444	*/
1445	FNIEMOP_DEF(iemOp_pcmpistrm_Vdq_Wdq_Ib)
1446	{
1447	IEMOP_MNEMONIC3(RMI, PCMPISTRM, pcmpistrm, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1448
1449	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1450	if (IEM_IS_MODRM_REG_MODE(bRm))
1451	{
1452	/*
1453	* Register, register.
1454	*/
1455	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1456	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1457	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1458	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1459	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1460	IEM_MC_LOCAL(IEMPCMPISTRXSRC, Src);
1461	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2);
1462	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1463	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1464	IEM_MC_PREPARE_SSE_USAGE();
1465	IEM_MC_FETCH_XREG_PAIR_U128(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
1466	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1467	IEM_MC_REF_EFLAGS(pEFlags);
1468	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1469	iemAImpl_pcmpistrm_u128,
1470	iemAImpl_pcmpistrm_u128_fallback),
1471	puDst, pEFlags, pSrc, bImmArg);
1472	IEM_MC_ADVANCE_RIP_AND_FINISH();
1473	IEM_MC_END();
1474	}
1475	else
1476	{
1477	/*
1478	* Register, memory.
1479	*/
1480	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1481	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1482	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1483	IEM_MC_LOCAL(IEMPCMPISTRXSRC, Src);
1484	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2);
1485	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1486
1487	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1488	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1489	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1490	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1491	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1492	IEM_MC_PREPARE_SSE_USAGE();
1493
1494	IEM_MC_FETCH_MEM_U128_AND_XREG_U128(Src, IEM_GET_MODRM_REG(pVCpu, bRm), pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1495	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1496	IEM_MC_REF_EFLAGS(pEFlags);
1497	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1498	iemAImpl_pcmpistrm_u128,
1499	iemAImpl_pcmpistrm_u128_fallback),
1500	puDst, pEFlags, pSrc, bImmArg);
1501	IEM_MC_ADVANCE_RIP_AND_FINISH();
1502	IEM_MC_END();
1503	}
1504	}
1505
1506
1507	/**
1508	* @opcode 0x63
1509	* @oppfx 0x66
1510	* @opflmodify cf,pf,af,zf,sf,of
1511	* @opflclear pf,af
1512	*/
1513	FNIEMOP_DEF(iemOp_pcmpistri_Vdq_Wdq_Ib)
1514	{
1515	IEMOP_MNEMONIC3(RMI, PCMPISTRI, pcmpistri, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1516
1517	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1518	if (IEM_IS_MODRM_REG_MODE(bRm))
1519	{
1520	/*
1521	* Register, register.
1522	*/
1523	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1524	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1525	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1526	IEM_MC_ARG(uint32_t *, pEFlags, 0);
1527	IEM_MC_ARG(PCRTUINT128U, pSrc1, 1);
1528	IEM_MC_ARG(PCRTUINT128U, pSrc2, 2);
1529	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1530	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1531	IEM_MC_PREPARE_SSE_USAGE();
1532	IEM_MC_REF_XREG_U128_CONST(pSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1533	IEM_MC_REF_XREG_U128_CONST(pSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1534	IEM_MC_REF_EFLAGS(pEFlags);
1535	IEM_MC_CALL_AIMPL_4(uint32_t, u32Ecx,
1536	IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1537	iemAImpl_pcmpistri_u128,
1538	iemAImpl_pcmpistri_u128_fallback),
1539	pEFlags, pSrc1, pSrc2, bImmArg);
1540	/** @todo testcase: High dword of RCX cleared? */
1541	IEM_MC_STORE_GREG_U32(X86_GREG_xCX, u32Ecx);
1542	IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX);
1543
1544	IEM_MC_ADVANCE_RIP_AND_FINISH();
1545	IEM_MC_END();
1546	}
1547	else
1548	{
1549	/*
1550	* Register, memory.
1551	*/
1552	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1553	IEM_MC_ARG(uint32_t *, pEFlags, 0);
1554	IEM_MC_ARG(PCRTUINT128U, pSrc1, 1);
1555	IEM_MC_LOCAL(RTUINT128U, Src2);
1556	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc2, Src2, 2);
1557	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1558
1559	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1560	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1561	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1562	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
1563	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1564	IEM_MC_PREPARE_SSE_USAGE();
1565
1566	IEM_MC_FETCH_MEM_U128(Src2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1567	IEM_MC_REF_XREG_U128_CONST(pSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1568	IEM_MC_REF_EFLAGS(pEFlags);
1569	IEM_MC_CALL_AIMPL_4(uint32_t, u32Ecx,
1570	IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1571	iemAImpl_pcmpistri_u128,
1572	iemAImpl_pcmpistri_u128_fallback),
1573	pEFlags, pSrc1, pSrc2, bImmArg);
1574	/** @todo testcase: High dword of RCX cleared? */
1575	IEM_MC_STORE_GREG_U32(X86_GREG_xCX, u32Ecx);
1576	IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX);
1577	IEM_MC_ADVANCE_RIP_AND_FINISH();
1578	IEM_MC_END();
1579	}
1580	}
1581
1582
1583	/* Opcode 0x66 0x0f 0x64 - invalid */
1584	/* Opcode 0x66 0x0f 0x65 - invalid */
1585	/* Opcode 0x66 0x0f 0x66 - invalid */
1586	/* Opcode 0x66 0x0f 0x67 - invalid */
1587	/* Opcode 0x66 0x0f 0x68 - invalid */
1588	/* Opcode 0x66 0x0f 0x69 - invalid */
1589	/* Opcode 0x66 0x0f 0x6a - invalid */
1590	/* Opcode 0x66 0x0f 0x6b - invalid */
1591	/* Opcode 0x66 0x0f 0x6c - invalid */
1592	/* Opcode 0x66 0x0f 0x6d - invalid */
1593	/* Opcode 0x66 0x0f 0x6e - invalid */
1594	/* Opcode 0x66 0x0f 0x6f - invalid */
1595
1596	/* Opcodes 0x0f 0x70 thru 0x0f 0xb0 are unused. */
1597
1598
1599	/* Opcode 0x0f 0xc0 - invalid */
1600	/* Opcode 0x0f 0xc1 - invalid */
1601	/* Opcode 0x0f 0xc2 - invalid */
1602	/* Opcode 0x0f 0xc3 - invalid */
1603	/* Opcode 0x0f 0xc4 - invalid */
1604	/* Opcode 0x0f 0xc5 - invalid */
1605	/* Opcode 0x0f 0xc6 - invalid */
1606	/* Opcode 0x0f 0xc7 - invalid */
1607	/* Opcode 0x0f 0xc8 - invalid */
1608	/* Opcode 0x0f 0xc9 - invalid */
1609	/* Opcode 0x0f 0xca - invalid */
1610	/* Opcode 0x0f 0xcb - invalid */
1611
1612
1613	/* Opcode 0x0f 0xcc */
1614	FNIEMOP_DEF(iemOp_sha1rnds4_Vdq_Wdq_Ib)
1615	{
1616	IEMOP_MNEMONIC3(RMI, SHA1RNDS4, sha1rnds4, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1617
1618	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1619	if (IEM_IS_MODRM_REG_MODE(bRm))
1620	{
1621	/*
1622	* XMM, XMM, imm8
1623	*/
1624	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1625	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1626	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
1627	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1628	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1629	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
1630	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1631	IEM_MC_PREPARE_SSE_USAGE();
1632	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1633	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1634	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha,
1635	iemAImpl_sha1rnds4_u128,
1636	iemAImpl_sha1rnds4_u128_fallback),
1637	puDst, puSrc, bImmArg);
1638	IEM_MC_ADVANCE_RIP_AND_FINISH();
1639	IEM_MC_END();
1640	}
1641	else
1642	{
1643	/*
1644	* XMM, [mem128], imm8.
1645	*/
1646	IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1647	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1648	IEM_MC_LOCAL(RTUINT128U, uSrc);
1649	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1650	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1651
1652	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1653	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1654	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
1655	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
1656	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1657	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1658
1659	IEM_MC_PREPARE_SSE_USAGE();
1660	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1661	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha,
1662	iemAImpl_sha1rnds4_u128,
1663	iemAImpl_sha1rnds4_u128_fallback),
1664	puDst, puSrc, bImmArg);
1665	IEM_MC_ADVANCE_RIP_AND_FINISH();
1666	IEM_MC_END();
1667	}
1668	}
1669
1670
1671	/* Opcode 0x0f 0xcd - invalid */
1672	/* Opcode 0x0f 0xce - invalid */
1673	/* Opcode 0x0f 0xcf - invalid */
1674
1675
1676	/* Opcode 0x66 0x0f 0xd0 - invalid */
1677	/* Opcode 0x66 0x0f 0xd1 - invalid */
1678	/* Opcode 0x66 0x0f 0xd2 - invalid */
1679	/* Opcode 0x66 0x0f 0xd3 - invalid */
1680	/* Opcode 0x66 0x0f 0xd4 - invalid */
1681	/* Opcode 0x66 0x0f 0xd5 - invalid */
1682	/* Opcode 0x66 0x0f 0xd6 - invalid */
1683	/* Opcode 0x66 0x0f 0xd7 - invalid */
1684	/* Opcode 0x66 0x0f 0xd8 - invalid */
1685	/* Opcode 0x66 0x0f 0xd9 - invalid */
1686	/* Opcode 0x66 0x0f 0xda - invalid */
1687	/* Opcode 0x66 0x0f 0xdb - invalid */
1688	/* Opcode 0x66 0x0f 0xdc - invalid */
1689	/* Opcode 0x66 0x0f 0xdd - invalid */
1690	/* Opcode 0x66 0x0f 0xde - invalid */
1691
1692
1693	/* Opcode 0x66 0x0f 0xdf - (aeskeygenassist). */
1694	FNIEMOP_DEF(iemOp_aeskeygen_Vdq_Wdq_Ib)
1695	{
1696	IEMOP_MNEMONIC3(RMI, AESKEYGEN, aeskeygen, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1697	return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFullImm8_To_Full,
1698	IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback));
1699	}
1700
1701
1702	/* Opcode 0xf2 0x0f 0xf0 - invalid (vex only) */
1703
1704
1705	/**
1706	* Three byte opcode map, first two bytes are 0x0f 0x3a.
1707	* @sa g_apfnVexMap2
1708	*/
1709	const PFNIEMOP g_apfnThreeByte0f3a[] =
1710	{
1711	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1712	/* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1713	/* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1714	/* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1715	/* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1716	/* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1717	/* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1718	/* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1719	/* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1720	/* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_roundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1721	/* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_roundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1722	/* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_roundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1723	/* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_roundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1724	/* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_blendps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1725	/* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_blendpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1726	/* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_pblendw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1727	/* 0x0f */ iemOp_palignr_Pq_Qq_Ib, iemOp_palignr_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1728
1729	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1730	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1731	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1732	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1733	/* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_pextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1734	/* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_pextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1735	/* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_pextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1736	/* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_extractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1737	/* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1738	/* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1739	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1740	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1741	/* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1742	/* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1743	/* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1744	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1745
1746	/* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrb_Vdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1747	/* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_insertps_Vdq_UdqMd_Ib,iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1748	/* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrd_q_Vdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1749	/* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1750	/* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1751	/* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1752	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1753	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1754	/* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1755	/* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1756	/* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1757	/* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1758	/* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1759	/* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1760	/* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1761	/* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1762
1763	/* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1764	/* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1765	/* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1766	/* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1767	/* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1768	/* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1769	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1770	/* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1771	/* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1772	/* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1773	/* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1774	/* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1775	/* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1776	/* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1777	/* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1778	/* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1779
1780	/* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_dpps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1781	/* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_dppd_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1782	/* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_mpsadbw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1783	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1784	/* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_pclmulqdq_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1785	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1786	/* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1787	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1788	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1789	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1790	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1791	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1792	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1793	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1794	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1795	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1796
1797	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1798	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1799	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1800	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1801	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1802	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1803	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1804	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1805	/* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1806	/* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1807	/* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1808	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1809	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1810	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1811	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1812	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1813
1814	/* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1815	/* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1816	/* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1817	/* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1818	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1819	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1820	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1821	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1822	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1823	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1824	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1825	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1826	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1827	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1828	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1829	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1830
1831	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1832	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1833	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1834	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1835	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1836	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1837	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1838	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1839	/* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1840	/* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1841	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1842	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1843	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1844	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1845	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1846	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1847
1848	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1849	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1850	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1851	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1852	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1853	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1854	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1855	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1856	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1857	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1858	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1859	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1860	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1861	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1862	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1863	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1864
1865	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1866	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1867	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1868	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1869	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1870	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1871	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1872	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1873	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1874	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1875	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1876	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1877	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1878	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1879	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1880	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1881
1882	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1883	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1884	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1885	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1886	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1887	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1888	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1889	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1890	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1891	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1892	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1893	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1894	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1895	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1896	/* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1897	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1898
1899	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1900	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1901	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1902	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1903	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1904	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1905	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1906	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1907	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1908	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1909	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1910	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1911	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1912	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1913	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1914	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1915
1916	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1917	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1918	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1919	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1920	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1921	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1922	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1923	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1924	/* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1925	/* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1926	/* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1927	/* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1928	/* 0xcc */ iemOp_sha1rnds4_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1929	/* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1930	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1931	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1932
1933	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1934	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1935	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1936	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1937	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1938	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1939	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1940	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1941	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1942	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1943	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1944	/* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1945	/* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1946	/* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1947	/* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1948	/* 0xdf */ iemOp_InvalidNeedRMImm8, iemOp_aeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1949
1950	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1951	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1952	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1953	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1954	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1955	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1956	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1957	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1958	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1959	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1960	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1961	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1962	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1963	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1964	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1965	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1966
1967	/* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1968	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1969	/* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1970	/* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1971	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1972	/* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1973	/* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1974	/* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1975	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1976	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1977	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1978	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1979	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1980	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1981	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1982	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1983	};
1984	AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f3a) == 1024);
1985
1986	/** @} */
1987

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstThree0f3a.cpp.h@ 105277

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