VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h@ 101504

Last change on this file since 101504 was 101387, checked in by vboxsync, 14 months ago

VMM/IEM: Added a new class of threaded function variants, the 16f/32f/64f variants that will clear RF (and vbox internal friends) and check for TF (and vbox internal friends). The variants w/o the 'f' after the bitcount will skip this test+branch. The motivation of this was to deal with this issue that the threaded recompiler level rather than try optimize away the test+branch++ code when generating native code, make the IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32 a very simple place to start emitting native code (compared to IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32_WITH_FLAGS). bugref:10371
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File size: 212.0 KB
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1/* $Id: IEMAllInstVexMap1.cpp.h 101387 2023-10-07 23:34:54Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstTwoByte0f.cpp.h is a legacy mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 1
33 * @{
34 */
35
36/**
37 * Common worker for AVX2 instructions on the forms:
38 * - vpxxx xmm0, xmm1, xmm2/mem128
39 * - vpxxx ymm0, ymm1, ymm2/mem256
40 *
41 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
42 */
43FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, PCIEMOPMEDIAF3, pImpl)
44{
45 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
46 if (IEM_IS_MODRM_REG_MODE(bRm))
47 {
48 /*
49 * Register, register.
50 */
51 if (pVCpu->iem.s.uVexLength)
52 {
53 IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
54 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
55 IEM_MC_LOCAL(RTUINT256U, uDst);
56 IEM_MC_LOCAL(RTUINT256U, uSrc1);
57 IEM_MC_LOCAL(RTUINT256U, uSrc2);
58 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
59 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 1);
60 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 2);
61 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 3);
62 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
63 IEM_MC_PREPARE_AVX_USAGE();
64 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
65 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
66 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
67 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
68 IEM_MC_ADVANCE_RIP_AND_FINISH();
69 IEM_MC_END();
70 }
71 else
72 {
73 IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
74 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
75 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
76 IEM_MC_ARG(PRTUINT128U, puDst, 1);
77 IEM_MC_ARG(PCRTUINT128U, puSrc1, 2);
78 IEM_MC_ARG(PCRTUINT128U, puSrc2, 3);
79 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
80 IEM_MC_PREPARE_AVX_USAGE();
81 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
82 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
83 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
84 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
85 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
86 IEM_MC_ADVANCE_RIP_AND_FINISH();
87 IEM_MC_END();
88 }
89 }
90 else
91 {
92 /*
93 * Register, memory.
94 */
95 if (pVCpu->iem.s.uVexLength)
96 {
97 IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
98 IEM_MC_LOCAL(RTUINT256U, uDst);
99 IEM_MC_LOCAL(RTUINT256U, uSrc1);
100 IEM_MC_LOCAL(RTUINT256U, uSrc2);
101 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
102 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
103 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 1);
104 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 2);
105 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 3);
106
107 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
108 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
109 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
110 IEM_MC_PREPARE_AVX_USAGE();
111
112 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
113 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
114 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
115 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
116
117 IEM_MC_ADVANCE_RIP_AND_FINISH();
118 IEM_MC_END();
119 }
120 else
121 {
122 IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
123 IEM_MC_LOCAL(RTUINT128U, uSrc2);
124 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
125 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
126 IEM_MC_ARG(PRTUINT128U, puDst, 1);
127 IEM_MC_ARG(PCRTUINT128U, puSrc1, 2);
128 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 3);
129
130 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
131 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
132 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
133 IEM_MC_PREPARE_AVX_USAGE();
134
135 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
136 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
137 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
138 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
139 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
140
141 IEM_MC_ADVANCE_RIP_AND_FINISH();
142 IEM_MC_END();
143 }
144 }
145}
146
147
148/**
149 * Common worker for AVX2 instructions on the forms:
150 * - vpxxx xmm0, xmm1, xmm2/mem128
151 * - vpxxx ymm0, ymm1, ymm2/mem256
152 *
153 * Takes function table for function w/o implicit state parameter.
154 *
155 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
156 */
157FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, PCIEMOPMEDIAOPTF3, pImpl)
158{
159 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
160 if (IEM_IS_MODRM_REG_MODE(bRm))
161 {
162 /*
163 * Register, register.
164 */
165 if (pVCpu->iem.s.uVexLength)
166 {
167 IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
168 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
169 IEM_MC_LOCAL(RTUINT256U, uDst);
170 IEM_MC_LOCAL(RTUINT256U, uSrc1);
171 IEM_MC_LOCAL(RTUINT256U, uSrc2);
172 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
173 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
174 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
175 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
176 IEM_MC_PREPARE_AVX_USAGE();
177 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
178 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
179 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
180 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
181 IEM_MC_ADVANCE_RIP_AND_FINISH();
182 IEM_MC_END();
183 }
184 else
185 {
186 IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
187 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
188 IEM_MC_ARG(PRTUINT128U, puDst, 0);
189 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
190 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
191 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
192 IEM_MC_PREPARE_AVX_USAGE();
193 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
194 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
195 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
196 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
197 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
198 IEM_MC_ADVANCE_RIP_AND_FINISH();
199 IEM_MC_END();
200 }
201 }
202 else
203 {
204 /*
205 * Register, memory.
206 */
207 if (pVCpu->iem.s.uVexLength)
208 {
209 IEM_MC_BEGIN(3, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
210 IEM_MC_LOCAL(RTUINT256U, uDst);
211 IEM_MC_LOCAL(RTUINT256U, uSrc1);
212 IEM_MC_LOCAL(RTUINT256U, uSrc2);
213 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
214 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
215 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
216 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
217
218 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
219 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
220 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
221 IEM_MC_PREPARE_AVX_USAGE();
222
223 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
224 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
225 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
226 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
227
228 IEM_MC_ADVANCE_RIP_AND_FINISH();
229 IEM_MC_END();
230 }
231 else
232 {
233 IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
234 IEM_MC_LOCAL(RTUINT128U, uSrc2);
235 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
236 IEM_MC_ARG(PRTUINT128U, puDst, 0);
237 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
238 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
239
240 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
241 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
242 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
243 IEM_MC_PREPARE_AVX_USAGE();
244
245 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
246 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
247 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
248 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
249 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
250
251 IEM_MC_ADVANCE_RIP_AND_FINISH();
252 IEM_MC_END();
253 }
254 }
255}
256
257
258/**
259 * Common worker for AVX2 instructions on the forms:
260 * - vpunpckhxx xmm0, xmm1, xmm2/mem128
261 * - vpunpckhxx ymm0, ymm1, ymm2/mem256
262 *
263 * The 128-bit memory version of this instruction may elect to skip fetching the
264 * lower 64 bits of the operand. We, however, do not.
265 *
266 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
267 */
268FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, PCIEMOPMEDIAOPTF3, pImpl)
269{
270 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
271}
272
273
274/**
275 * Common worker for AVX2 instructions on the forms:
276 * - vpunpcklxx xmm0, xmm1, xmm2/mem128
277 * - vpunpcklxx ymm0, ymm1, ymm2/mem256
278 *
279 * The 128-bit memory version of this instruction may elect to skip fetching the
280 * higher 64 bits of the operand. We, however, do not.
281 *
282 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
283 */
284FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, PCIEMOPMEDIAOPTF3, pImpl)
285{
286 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
287}
288
289
290/**
291 * Common worker for AVX2 instructions on the forms:
292 * - vpxxx xmm0, xmm1/mem128
293 * - vpxxx ymm0, ymm1/mem256
294 *
295 * Takes function table for function w/o implicit state parameter.
296 *
297 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
298 */
299FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, PCIEMOPMEDIAOPTF2, pImpl)
300{
301 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
302 if (IEM_IS_MODRM_REG_MODE(bRm))
303 {
304 /*
305 * Register, register.
306 */
307 if (pVCpu->iem.s.uVexLength)
308 {
309 IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
310 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
311 IEM_MC_LOCAL(RTUINT256U, uDst);
312 IEM_MC_LOCAL(RTUINT256U, uSrc);
313 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
314 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
315 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
316 IEM_MC_PREPARE_AVX_USAGE();
317 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
318 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
319 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
320 IEM_MC_ADVANCE_RIP_AND_FINISH();
321 IEM_MC_END();
322 }
323 else
324 {
325 IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
326 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
327 IEM_MC_ARG(PRTUINT128U, puDst, 0);
328 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
329 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
330 IEM_MC_PREPARE_AVX_USAGE();
331 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
332 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
333 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
334 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
335 IEM_MC_ADVANCE_RIP_AND_FINISH();
336 IEM_MC_END();
337 }
338 }
339 else
340 {
341 /*
342 * Register, memory.
343 */
344 if (pVCpu->iem.s.uVexLength)
345 {
346 IEM_MC_BEGIN(2, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
347 IEM_MC_LOCAL(RTUINT256U, uDst);
348 IEM_MC_LOCAL(RTUINT256U, uSrc);
349 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
350 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
351 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
352
353 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
354 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
355 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
356 IEM_MC_PREPARE_AVX_USAGE();
357
358 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
359 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
360 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
361
362 IEM_MC_ADVANCE_RIP_AND_FINISH();
363 IEM_MC_END();
364 }
365 else
366 {
367 IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
368 IEM_MC_LOCAL(RTUINT128U, uSrc);
369 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
370 IEM_MC_ARG(PRTUINT128U, puDst, 0);
371 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
372
373 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
374 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
375 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
376 IEM_MC_PREPARE_AVX_USAGE();
377
378 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
379 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
380 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
381 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
382
383 IEM_MC_ADVANCE_RIP_AND_FINISH();
384 IEM_MC_END();
385 }
386 }
387}
388
389
390/* Opcode VEX.0F 0x00 - invalid */
391/* Opcode VEX.0F 0x01 - invalid */
392/* Opcode VEX.0F 0x02 - invalid */
393/* Opcode VEX.0F 0x03 - invalid */
394/* Opcode VEX.0F 0x04 - invalid */
395/* Opcode VEX.0F 0x05 - invalid */
396/* Opcode VEX.0F 0x06 - invalid */
397/* Opcode VEX.0F 0x07 - invalid */
398/* Opcode VEX.0F 0x08 - invalid */
399/* Opcode VEX.0F 0x09 - invalid */
400/* Opcode VEX.0F 0x0a - invalid */
401
402/** Opcode VEX.0F 0x0b. */
403FNIEMOP_DEF(iemOp_vud2)
404{
405 IEMOP_MNEMONIC(vud2, "vud2");
406 IEMOP_RAISE_INVALID_OPCODE_RET();
407}
408
409/* Opcode VEX.0F 0x0c - invalid */
410/* Opcode VEX.0F 0x0d - invalid */
411/* Opcode VEX.0F 0x0e - invalid */
412/* Opcode VEX.0F 0x0f - invalid */
413
414
415/**
416 * @opcode 0x10
417 * @oppfx none
418 * @opcpuid avx
419 * @opgroup og_avx_simdfp_datamove
420 * @opxcpttype 4UA
421 * @optest op1=1 op2=2 -> op1=2
422 * @optest op1=0 op2=-22 -> op1=-22
423 */
424FNIEMOP_DEF(iemOp_vmovups_Vps_Wps)
425{
426 IEMOP_MNEMONIC2(VEX_RM, VMOVUPS, vmovups, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
427 Assert(pVCpu->iem.s.uVexLength <= 1);
428 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
429 if (IEM_IS_MODRM_REG_MODE(bRm))
430 {
431 /*
432 * Register, register.
433 */
434 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
435 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
436 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
437 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
438 if (pVCpu->iem.s.uVexLength == 0)
439 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
440 IEM_GET_MODRM_RM(pVCpu, bRm));
441 else
442 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
443 IEM_GET_MODRM_RM(pVCpu, bRm));
444 IEM_MC_ADVANCE_RIP_AND_FINISH();
445 IEM_MC_END();
446 }
447 else if (pVCpu->iem.s.uVexLength == 0)
448 {
449 /*
450 * 128-bit: Register, Memory
451 */
452 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
453 IEM_MC_LOCAL(RTUINT128U, uSrc);
454 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
455
456 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
457 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
458 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
459 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
460
461 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
462 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
463
464 IEM_MC_ADVANCE_RIP_AND_FINISH();
465 IEM_MC_END();
466 }
467 else
468 {
469 /*
470 * 256-bit: Register, Memory
471 */
472 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
473 IEM_MC_LOCAL(RTUINT256U, uSrc);
474 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
475
476 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
477 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
478 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
479 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
480
481 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
482 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
483
484 IEM_MC_ADVANCE_RIP_AND_FINISH();
485 IEM_MC_END();
486 }
487}
488
489
490/**
491 * @opcode 0x10
492 * @oppfx 0x66
493 * @opcpuid avx
494 * @opgroup og_avx_simdfp_datamove
495 * @opxcpttype 4UA
496 * @optest op1=1 op2=2 -> op1=2
497 * @optest op1=0 op2=-22 -> op1=-22
498 */
499FNIEMOP_DEF(iemOp_vmovupd_Vpd_Wpd)
500{
501 IEMOP_MNEMONIC2(VEX_RM, VMOVUPD, vmovupd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
502 Assert(pVCpu->iem.s.uVexLength <= 1);
503 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
504 if (IEM_IS_MODRM_REG_MODE(bRm))
505 {
506 /*
507 * Register, register.
508 */
509 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
510 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
511 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
512 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
513 if (pVCpu->iem.s.uVexLength == 0)
514 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
515 IEM_GET_MODRM_RM(pVCpu, bRm));
516 else
517 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
518 IEM_GET_MODRM_RM(pVCpu, bRm));
519 IEM_MC_ADVANCE_RIP_AND_FINISH();
520 IEM_MC_END();
521 }
522 else if (pVCpu->iem.s.uVexLength == 0)
523 {
524 /*
525 * 128-bit: Memory, register.
526 */
527 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
528 IEM_MC_LOCAL(RTUINT128U, uSrc);
529 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
530
531 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
532 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
533 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
534 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
535
536 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
537 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
538
539 IEM_MC_ADVANCE_RIP_AND_FINISH();
540 IEM_MC_END();
541 }
542 else
543 {
544 /*
545 * 256-bit: Memory, register.
546 */
547 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
548 IEM_MC_LOCAL(RTUINT256U, uSrc);
549 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
550
551 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
552 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
553 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
554 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
555
556 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
557 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
558
559 IEM_MC_ADVANCE_RIP_AND_FINISH();
560 IEM_MC_END();
561 }
562}
563
564
565FNIEMOP_DEF(iemOp_vmovss_Vss_Hss_Wss)
566{
567 Assert(pVCpu->iem.s.uVexLength <= 1);
568 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
569 if (IEM_IS_MODRM_REG_MODE(bRm))
570 {
571 /**
572 * @opcode 0x10
573 * @oppfx 0xf3
574 * @opcodesub 11 mr/reg
575 * @opcpuid avx
576 * @opgroup og_avx_simdfp_datamerge
577 * @opxcpttype 5
578 * @optest op1=1 op2=0 op3=2 -> op1=2
579 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
580 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
581 * @optest op1=3 op2=-2 op3=0x77 -> op1=-8589934473
582 * @note HssHi refers to bits 127:32.
583 */
584 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
585 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
586 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
587 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
588 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
589 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
590 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
591 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
592 IEM_MC_ADVANCE_RIP_AND_FINISH();
593 IEM_MC_END();
594 }
595 else
596 {
597 /**
598 * @opdone
599 * @opcode 0x10
600 * @oppfx 0xf3
601 * @opcodesub !11 mr/reg
602 * @opcpuid avx
603 * @opgroup og_avx_simdfp_datamove
604 * @opxcpttype 5
605 * @opfunction iemOp_vmovss_Vss_Hss_Wss
606 * @optest op1=1 op2=2 -> op1=2
607 * @optest op1=0 op2=-22 -> op1=-22
608 */
609 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSS, vmovss, VssZx_WO, Md, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
610 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
611 IEM_MC_LOCAL(uint32_t, uSrc);
612 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
613
614 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
615 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
616 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
617 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
618
619 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
620 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
621
622 IEM_MC_ADVANCE_RIP_AND_FINISH();
623 IEM_MC_END();
624 }
625}
626
627
628FNIEMOP_DEF(iemOp_vmovsd_Vsd_Hsd_Wsd)
629{
630 Assert(pVCpu->iem.s.uVexLength <= 1);
631 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
632 if (IEM_IS_MODRM_REG_MODE(bRm))
633 {
634 /**
635 * @opcode 0x10
636 * @oppfx 0xf2
637 * @opcodesub 11 mr/reg
638 * @opcpuid avx
639 * @opgroup og_avx_simdfp_datamerge
640 * @opxcpttype 5
641 * @optest op1=1 op2=0 op3=2 -> op1=2
642 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
643 * @optest op1=3 op2=-1 op3=0x77 ->
644 * op1=0xffffffffffffffff0000000000000077
645 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x420000000000000077
646 */
647 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
648 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
649 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
650
651 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
652 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
653 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
654 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
655 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
656 IEM_MC_ADVANCE_RIP_AND_FINISH();
657 IEM_MC_END();
658 }
659 else
660 {
661 /**
662 * @opdone
663 * @opcode 0x10
664 * @oppfx 0xf2
665 * @opcodesub !11 mr/reg
666 * @opcpuid avx
667 * @opgroup og_avx_simdfp_datamove
668 * @opxcpttype 5
669 * @opfunction iemOp_vmovsd_Vsd_Hsd_Wsd
670 * @optest op1=1 op2=2 -> op1=2
671 * @optest op1=0 op2=-22 -> op1=-22
672 */
673 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSD, vmovsd, VsdZx_WO, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
674 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
675 IEM_MC_LOCAL(uint64_t, uSrc);
676 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
677
678 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
679 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
680 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
681 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
682
683 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
684 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
685
686 IEM_MC_ADVANCE_RIP_AND_FINISH();
687 IEM_MC_END();
688 }
689}
690
691
692/**
693 * @opcode 0x11
694 * @oppfx none
695 * @opcpuid avx
696 * @opgroup og_avx_simdfp_datamove
697 * @opxcpttype 4UA
698 * @optest op1=1 op2=2 -> op1=2
699 * @optest op1=0 op2=-22 -> op1=-22
700 */
701FNIEMOP_DEF(iemOp_vmovups_Wps_Vps)
702{
703 IEMOP_MNEMONIC2(VEX_MR, VMOVUPS, vmovups, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
704 Assert(pVCpu->iem.s.uVexLength <= 1);
705 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
706 if (IEM_IS_MODRM_REG_MODE(bRm))
707 {
708 /*
709 * Register, register.
710 */
711 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
712 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
713 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
714 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
715 if (pVCpu->iem.s.uVexLength == 0)
716 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
717 IEM_GET_MODRM_REG(pVCpu, bRm));
718 else
719 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
720 IEM_GET_MODRM_REG(pVCpu, bRm));
721 IEM_MC_ADVANCE_RIP_AND_FINISH();
722 IEM_MC_END();
723 }
724 else if (pVCpu->iem.s.uVexLength == 0)
725 {
726 /*
727 * 128-bit: Memory, register.
728 */
729 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
730 IEM_MC_LOCAL(RTUINT128U, uSrc);
731 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
732
733 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
734 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
735 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
736 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
737
738 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
739 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
740
741 IEM_MC_ADVANCE_RIP_AND_FINISH();
742 IEM_MC_END();
743 }
744 else
745 {
746 /*
747 * 256-bit: Memory, register.
748 */
749 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
750 IEM_MC_LOCAL(RTUINT256U, uSrc);
751 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
752
753 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
754 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
755 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
756 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
757
758 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
759 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
760
761 IEM_MC_ADVANCE_RIP_AND_FINISH();
762 IEM_MC_END();
763 }
764}
765
766
767/**
768 * @opcode 0x11
769 * @oppfx 0x66
770 * @opcpuid avx
771 * @opgroup og_avx_simdfp_datamove
772 * @opxcpttype 4UA
773 * @optest op1=1 op2=2 -> op1=2
774 * @optest op1=0 op2=-22 -> op1=-22
775 */
776FNIEMOP_DEF(iemOp_vmovupd_Wpd_Vpd)
777{
778 IEMOP_MNEMONIC2(VEX_MR, VMOVUPD, vmovupd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
779 Assert(pVCpu->iem.s.uVexLength <= 1);
780 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
781 if (IEM_IS_MODRM_REG_MODE(bRm))
782 {
783 /*
784 * Register, register.
785 */
786 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
787 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
788 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
789 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
790 if (pVCpu->iem.s.uVexLength == 0)
791 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
792 IEM_GET_MODRM_REG(pVCpu, bRm));
793 else
794 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
795 IEM_GET_MODRM_REG(pVCpu, bRm));
796 IEM_MC_ADVANCE_RIP_AND_FINISH();
797 IEM_MC_END();
798 }
799 else if (pVCpu->iem.s.uVexLength == 0)
800 {
801 /*
802 * 128-bit: Memory, register.
803 */
804 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
805 IEM_MC_LOCAL(RTUINT128U, uSrc);
806 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
807
808 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
809 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
810 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
811 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
812
813 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
814 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
815
816 IEM_MC_ADVANCE_RIP_AND_FINISH();
817 IEM_MC_END();
818 }
819 else
820 {
821 /*
822 * 256-bit: Memory, register.
823 */
824 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
825 IEM_MC_LOCAL(RTUINT256U, uSrc);
826 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
827
828 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
829 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
830 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
831 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
832
833 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
834 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
835
836 IEM_MC_ADVANCE_RIP_AND_FINISH();
837 IEM_MC_END();
838 }
839}
840
841
842FNIEMOP_DEF(iemOp_vmovss_Wss_Hss_Vss)
843{
844 Assert(pVCpu->iem.s.uVexLength <= 1);
845 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
846 if (IEM_IS_MODRM_REG_MODE(bRm))
847 {
848 /**
849 * @opcode 0x11
850 * @oppfx 0xf3
851 * @opcodesub 11 mr/reg
852 * @opcpuid avx
853 * @opgroup og_avx_simdfp_datamerge
854 * @opxcpttype 5
855 * @optest op1=1 op2=0 op3=2 -> op1=2
856 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
857 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
858 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x4200000077
859 */
860 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
861 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
862 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
863
864 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
865 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
866 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
867 IEM_GET_MODRM_REG(pVCpu, bRm),
868 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
869 IEM_MC_ADVANCE_RIP_AND_FINISH();
870 IEM_MC_END();
871 }
872 else
873 {
874 /**
875 * @opdone
876 * @opcode 0x11
877 * @oppfx 0xf3
878 * @opcodesub !11 mr/reg
879 * @opcpuid avx
880 * @opgroup og_avx_simdfp_datamove
881 * @opxcpttype 5
882 * @opfunction iemOp_vmovss_Vss_Hss_Wss
883 * @optest op1=1 op2=2 -> op1=2
884 * @optest op1=0 op2=-22 -> op1=-22
885 */
886 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
887 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
888 IEM_MC_LOCAL(uint32_t, uSrc);
889 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
890
891 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
892 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
893 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
894 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
895
896 IEM_MC_FETCH_YREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
897 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
898
899 IEM_MC_ADVANCE_RIP_AND_FINISH();
900 IEM_MC_END();
901 }
902}
903
904
905FNIEMOP_DEF(iemOp_vmovsd_Wsd_Hsd_Vsd)
906{
907 Assert(pVCpu->iem.s.uVexLength <= 1);
908 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
909 if (IEM_IS_MODRM_REG_MODE(bRm))
910 {
911 /**
912 * @opcode 0x11
913 * @oppfx 0xf2
914 * @opcodesub 11 mr/reg
915 * @opcpuid avx
916 * @opgroup og_avx_simdfp_datamerge
917 * @opxcpttype 5
918 * @optest op1=1 op2=0 op3=2 -> op1=2
919 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
920 * @optest op1=3 op2=-1 op3=0x77 ->
921 * op1=0xffffffffffffffff0000000000000077
922 * @optest op2=0x42 op3=0x77 -> op1=0x420000000000000077
923 */
924 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
925 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
926 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
927
928 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
929 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
930 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
931 IEM_GET_MODRM_REG(pVCpu, bRm),
932 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
933 IEM_MC_ADVANCE_RIP_AND_FINISH();
934 IEM_MC_END();
935 }
936 else
937 {
938 /**
939 * @opdone
940 * @opcode 0x11
941 * @oppfx 0xf2
942 * @opcodesub !11 mr/reg
943 * @opcpuid avx
944 * @opgroup og_avx_simdfp_datamove
945 * @opxcpttype 5
946 * @opfunction iemOp_vmovsd_Wsd_Hsd_Vsd
947 * @optest op1=1 op2=2 -> op1=2
948 * @optest op1=0 op2=-22 -> op1=-22
949 */
950 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSD, vmovsd, Mq_WO, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
951 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
952 IEM_MC_LOCAL(uint64_t, uSrc);
953 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
954
955 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
956 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
957 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
958 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
959
960 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
961 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
962
963 IEM_MC_ADVANCE_RIP_AND_FINISH();
964 IEM_MC_END();
965 }
966}
967
968
969FNIEMOP_DEF(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps)
970{
971 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
972 if (IEM_IS_MODRM_REG_MODE(bRm))
973 {
974 /**
975 * @opcode 0x12
976 * @opcodesub 11 mr/reg
977 * @oppfx none
978 * @opcpuid avx
979 * @opgroup og_avx_simdfp_datamerge
980 * @opxcpttype 7LZ
981 * @optest op2=0x2200220122022203
982 * op3=0x3304330533063307
983 * -> op1=0x22002201220222033304330533063307
984 * @optest op2=-1 op3=-42 -> op1=-42
985 * @note op3 and op2 are only the 8-byte high XMM register halfs.
986 */
987 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
988 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
989 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
990
991 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
992 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
993 IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
994 IEM_GET_MODRM_RM(pVCpu, bRm),
995 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
996
997 IEM_MC_ADVANCE_RIP_AND_FINISH();
998 IEM_MC_END();
999 }
1000 else
1001 {
1002 /**
1003 * @opdone
1004 * @opcode 0x12
1005 * @opcodesub !11 mr/reg
1006 * @oppfx none
1007 * @opcpuid avx
1008 * @opgroup og_avx_simdfp_datamove
1009 * @opxcpttype 5LZ
1010 * @opfunction iemOp_vmovlps_Vq_Hq_Mq__vmovhlps
1011 * @optest op1=1 op2=0 op3=0 -> op1=0
1012 * @optest op1=0 op2=-1 op3=-1 -> op1=-1
1013 * @optest op1=1 op2=2 op3=3 -> op1=0x20000000000000003
1014 * @optest op2=-1 op3=0x42 -> op1=0xffffffffffffffff0000000000000042
1015 */
1016 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPS, vmovlps, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1017
1018 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1019 IEM_MC_LOCAL(uint64_t, uSrc);
1020 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1021
1022 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1023 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1024 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1025 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1026
1027 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1028 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1029 uSrc,
1030 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1031
1032 IEM_MC_ADVANCE_RIP_AND_FINISH();
1033 IEM_MC_END();
1034 }
1035}
1036
1037
1038/**
1039 * @opcode 0x12
1040 * @opcodesub !11 mr/reg
1041 * @oppfx 0x66
1042 * @opcpuid avx
1043 * @opgroup og_avx_pcksclr_datamerge
1044 * @opxcpttype 5LZ
1045 * @optest op2=0 op3=2 -> op1=2
1046 * @optest op2=0x22 op3=0x33 -> op1=0x220000000000000033
1047 * @optest op2=0xfffffff0fffffff1 op3=0xeeeeeee8eeeeeee9
1048 * -> op1=0xfffffff0fffffff1eeeeeee8eeeeeee9
1049 */
1050FNIEMOP_DEF(iemOp_vmovlpd_Vq_Hq_Mq)
1051{
1052 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1053 if (IEM_IS_MODRM_MEM_MODE(bRm))
1054 {
1055 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPD, vmovlpd, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1056
1057 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1058 IEM_MC_LOCAL(uint64_t, uSrc);
1059 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1060
1061 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1062 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1063 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1064 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1065
1066 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1067 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1068 uSrc,
1069 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1070
1071 IEM_MC_ADVANCE_RIP_AND_FINISH();
1072 IEM_MC_END();
1073 }
1074
1075 /**
1076 * @opdone
1077 * @opmnemonic udvex660f12m3
1078 * @opcode 0x12
1079 * @opcodesub 11 mr/reg
1080 * @oppfx 0x66
1081 * @opunused immediate
1082 * @opcpuid avx
1083 * @optest ->
1084 */
1085 else
1086 IEMOP_RAISE_INVALID_OPCODE_RET();
1087}
1088
1089
1090/**
1091 * @opcode 0x12
1092 * @oppfx 0xf3
1093 * @opcpuid avx
1094 * @opgroup og_avx_pcksclr_datamove
1095 * @opxcpttype 4
1096 * @optest vex.l==0 / op1=-1 op2=0xdddddddd00000002eeeeeeee00000001
1097 * -> op1=0x00000002000000020000000100000001
1098 * @optest vex.l==1 /
1099 * op2=0xbbbbbbbb00000004cccccccc00000003dddddddd00000002eeeeeeee00000001
1100 * -> op1=0x0000000400000004000000030000000300000002000000020000000100000001
1101 */
1102FNIEMOP_DEF(iemOp_vmovsldup_Vx_Wx)
1103{
1104 IEMOP_MNEMONIC2(VEX_RM, VMOVSLDUP, vmovsldup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1105 Assert(pVCpu->iem.s.uVexLength <= 1);
1106 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1107 if (IEM_IS_MODRM_REG_MODE(bRm))
1108 {
1109 /*
1110 * Register, register.
1111 */
1112 if (pVCpu->iem.s.uVexLength == 0)
1113 {
1114 IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1115 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1116 IEM_MC_LOCAL(RTUINT128U, uSrc);
1117
1118 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1119 IEM_MC_PREPARE_AVX_USAGE();
1120
1121 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1122 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1123 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1124 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1125 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1126 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1127
1128 IEM_MC_ADVANCE_RIP_AND_FINISH();
1129 IEM_MC_END();
1130 }
1131 else
1132 {
1133 IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1134 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1135 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1136 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1137 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 2);
1138
1139 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1140 IEM_MC_PREPARE_AVX_USAGE();
1141 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rr, iYRegDst, iYRegSrc);
1142
1143 IEM_MC_ADVANCE_RIP_AND_FINISH();
1144 IEM_MC_END();
1145 }
1146 }
1147 else
1148 {
1149 /*
1150 * Register, memory.
1151 */
1152 if (pVCpu->iem.s.uVexLength == 0)
1153 {
1154 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1155 IEM_MC_LOCAL(RTUINT128U, uSrc);
1156 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1157
1158 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1159 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1160 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1161 IEM_MC_PREPARE_AVX_USAGE();
1162
1163 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1164 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1165 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1166 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1167 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1168 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1169
1170 IEM_MC_ADVANCE_RIP_AND_FINISH();
1171 IEM_MC_END();
1172 }
1173 else
1174 {
1175 IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1176 IEM_MC_LOCAL(RTUINT256U, uSrc);
1177 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1178 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1179 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1180 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
1181
1182 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1183 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1184 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1185 IEM_MC_PREPARE_AVX_USAGE();
1186
1187 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1188 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rm, iYRegDst, puSrc);
1189
1190 IEM_MC_ADVANCE_RIP_AND_FINISH();
1191 IEM_MC_END();
1192 }
1193 }
1194}
1195
1196
1197/**
1198 * @opcode 0x12
1199 * @oppfx 0xf2
1200 * @opcpuid avx
1201 * @opgroup og_avx_pcksclr_datamove
1202 * @opxcpttype 5
1203 * @optest vex.l==0 / op2=0xddddddddeeeeeeee2222222211111111
1204 * -> op1=0x22222222111111112222222211111111
1205 * @optest vex.l==1 / op2=0xbbbbbbbbcccccccc4444444433333333ddddddddeeeeeeee2222222211111111
1206 * -> op1=0x4444444433333333444444443333333322222222111111112222222211111111
1207 */
1208FNIEMOP_DEF(iemOp_vmovddup_Vx_Wx)
1209{
1210 IEMOP_MNEMONIC2(VEX_RM, VMOVDDUP, vmovddup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1211 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1212 if (IEM_IS_MODRM_REG_MODE(bRm))
1213 {
1214 /*
1215 * Register, register.
1216 */
1217 if (pVCpu->iem.s.uVexLength == 0)
1218 {
1219 IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1220 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1221 IEM_MC_ARG(uint64_t, uSrc, 0);
1222
1223 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1224 IEM_MC_PREPARE_AVX_USAGE();
1225
1226 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /* a_iQword*/);
1227 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc);
1228 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc);
1229 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1230
1231 IEM_MC_ADVANCE_RIP_AND_FINISH();
1232 IEM_MC_END();
1233 }
1234 else
1235 {
1236 IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1237 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1238 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1239 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1240 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 2);
1241
1242 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1243 IEM_MC_PREPARE_AVX_USAGE();
1244 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rr, iYRegDst, iYRegSrc);
1245
1246 IEM_MC_ADVANCE_RIP_AND_FINISH();
1247 IEM_MC_END();
1248 }
1249 }
1250 else
1251 {
1252 /*
1253 * Register, memory.
1254 */
1255 if (pVCpu->iem.s.uVexLength == 0)
1256 {
1257 IEM_MC_BEGIN(1, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1258 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1259 IEM_MC_ARG(uint64_t, uSrc, 0);
1260
1261 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1262 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1263 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1264 IEM_MC_PREPARE_AVX_USAGE();
1265
1266 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1267 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc);
1268 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc);
1269 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1270
1271 IEM_MC_ADVANCE_RIP_AND_FINISH();
1272 IEM_MC_END();
1273 }
1274 else
1275 {
1276 IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1277 IEM_MC_LOCAL(RTUINT256U, uSrc);
1278 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1279 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1280 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1281 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
1282
1283 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1284 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1285 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1286 IEM_MC_PREPARE_AVX_USAGE();
1287
1288 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1289 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rm, iYRegDst, puSrc);
1290
1291 IEM_MC_ADVANCE_RIP_AND_FINISH();
1292 IEM_MC_END();
1293 }
1294 }
1295}
1296
1297
1298/**
1299 * @opcode 0x13
1300 * @opcodesub !11 mr/reg
1301 * @oppfx none
1302 * @opcpuid avx
1303 * @opgroup og_avx_simdfp_datamove
1304 * @opxcpttype 5
1305 * @optest op1=1 op2=2 -> op1=2
1306 * @optest op1=0 op2=-42 -> op1=-42
1307 */
1308FNIEMOP_DEF(iemOp_vmovlps_Mq_Vq)
1309{
1310 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1311 if (IEM_IS_MODRM_MEM_MODE(bRm))
1312 {
1313 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPS, vmovlps, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1314
1315 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1316 IEM_MC_LOCAL(uint64_t, uSrc);
1317 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1318
1319 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1320 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1321 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1322 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1323
1324 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1325 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1326
1327 IEM_MC_ADVANCE_RIP_AND_FINISH();
1328 IEM_MC_END();
1329 }
1330
1331 /**
1332 * @opdone
1333 * @opmnemonic udvex0f13m3
1334 * @opcode 0x13
1335 * @opcodesub 11 mr/reg
1336 * @oppfx none
1337 * @opunused immediate
1338 * @opcpuid avx
1339 * @optest ->
1340 */
1341 else
1342 IEMOP_RAISE_INVALID_OPCODE_RET();
1343}
1344
1345
1346/**
1347 * @opcode 0x13
1348 * @opcodesub !11 mr/reg
1349 * @oppfx 0x66
1350 * @opcpuid avx
1351 * @opgroup og_avx_pcksclr_datamove
1352 * @opxcpttype 5
1353 * @optest op1=1 op2=2 -> op1=2
1354 * @optest op1=0 op2=-42 -> op1=-42
1355 */
1356FNIEMOP_DEF(iemOp_vmovlpd_Mq_Vq)
1357{
1358 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1359 if (IEM_IS_MODRM_MEM_MODE(bRm))
1360 {
1361 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPD, vmovlpd, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1362 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1363 IEM_MC_LOCAL(uint64_t, uSrc);
1364 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1365
1366 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1367 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1368 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1369 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1370
1371 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1372 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1373
1374 IEM_MC_ADVANCE_RIP_AND_FINISH();
1375 IEM_MC_END();
1376 }
1377
1378 /**
1379 * @opdone
1380 * @opmnemonic udvex660f13m3
1381 * @opcode 0x13
1382 * @opcodesub 11 mr/reg
1383 * @oppfx 0x66
1384 * @opunused immediate
1385 * @opcpuid avx
1386 * @optest ->
1387 */
1388 else
1389 IEMOP_RAISE_INVALID_OPCODE_RET();
1390}
1391
1392/* Opcode VEX.F3.0F 0x13 - invalid */
1393/* Opcode VEX.F2.0F 0x13 - invalid */
1394
1395/** Opcode VEX.0F 0x14 - vunpcklps Vx, Hx, Wx*/
1396FNIEMOP_DEF(iemOp_vunpcklps_Vx_Hx_Wx)
1397{
1398 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPS, vunpcklps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1399 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklps);
1400 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1401}
1402
1403
1404/** Opcode VEX.66.0F 0x14 - vunpcklpd Vx,Hx,Wx */
1405FNIEMOP_DEF(iemOp_vunpcklpd_Vx_Hx_Wx)
1406{
1407 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPD, vunpcklpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1408 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklpd);
1409 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1410}
1411
1412
1413/* Opcode VEX.F3.0F 0x14 - invalid */
1414/* Opcode VEX.F2.0F 0x14 - invalid */
1415
1416
1417/** Opcode VEX.0F 0x15 - vunpckhps Vx, Hx, Wx */
1418FNIEMOP_DEF(iemOp_vunpckhps_Vx_Hx_Wx)
1419{
1420 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPS, vunpckhps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1421 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhps);
1422 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1423}
1424
1425
1426/** Opcode VEX.66.0F 0x15 - vunpckhpd Vx,Hx,Wx */
1427FNIEMOP_DEF(iemOp_vunpckhpd_Vx_Hx_Wx)
1428{
1429 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPD, vunpckhpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1430 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhpd);
1431 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1432}
1433
1434
1435/* Opcode VEX.F3.0F 0x15 - invalid */
1436/* Opcode VEX.F2.0F 0x15 - invalid */
1437
1438
1439FNIEMOP_DEF(iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq)
1440{
1441 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1442 if (IEM_IS_MODRM_REG_MODE(bRm))
1443 {
1444 /**
1445 * @opcode 0x16
1446 * @opcodesub 11 mr/reg
1447 * @oppfx none
1448 * @opcpuid avx
1449 * @opgroup og_avx_simdfp_datamerge
1450 * @opxcpttype 7LZ
1451 */
1452 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVLHPS, vmovlhps, Vq_WO, Hq, Uq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1453
1454 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1455 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1456
1457 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1458 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1459 IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1460 IEM_GET_MODRM_RM(pVCpu, bRm),
1461 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1462
1463 IEM_MC_ADVANCE_RIP_AND_FINISH();
1464 IEM_MC_END();
1465 }
1466 else
1467 {
1468 /**
1469 * @opdone
1470 * @opcode 0x16
1471 * @opcodesub !11 mr/reg
1472 * @oppfx none
1473 * @opcpuid avx
1474 * @opgroup og_avx_simdfp_datamove
1475 * @opxcpttype 5LZ
1476 * @opfunction iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq
1477 */
1478 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPS, vmovhps, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1479
1480 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1481 IEM_MC_LOCAL(uint64_t, uSrc);
1482 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1483
1484 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1485 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1486 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1487 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1488
1489 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1490 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1491 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1492 uSrc);
1493
1494 IEM_MC_ADVANCE_RIP_AND_FINISH();
1495 IEM_MC_END();
1496 }
1497}
1498
1499
1500/**
1501 * @opcode 0x16
1502 * @opcodesub !11 mr/reg
1503 * @oppfx 0x66
1504 * @opcpuid avx
1505 * @opgroup og_avx_pcksclr_datamerge
1506 * @opxcpttype 5LZ
1507 */
1508FNIEMOP_DEF(iemOp_vmovhpd_Vdq_Hq_Mq)
1509{
1510 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1511 if (IEM_IS_MODRM_MEM_MODE(bRm))
1512 {
1513 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPD, vmovhpd, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1514
1515 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1516 IEM_MC_LOCAL(uint64_t, uSrc);
1517 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1518
1519 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1520 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1521 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1522 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1523
1524 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1525 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1526 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1527 uSrc);
1528
1529 IEM_MC_ADVANCE_RIP_AND_FINISH();
1530 IEM_MC_END();
1531 }
1532
1533 /**
1534 * @opdone
1535 * @opmnemonic udvex660f16m3
1536 * @opcode 0x12
1537 * @opcodesub 11 mr/reg
1538 * @oppfx 0x66
1539 * @opunused immediate
1540 * @opcpuid avx
1541 * @optest ->
1542 */
1543 else
1544 IEMOP_RAISE_INVALID_OPCODE_RET();
1545}
1546
1547
1548/** Opcode VEX.F3.0F 0x16 - vmovshdup Vx, Wx */
1549/**
1550 * @opcode 0x16
1551 * @oppfx 0xf3
1552 * @opcpuid avx
1553 * @opgroup og_avx_pcksclr_datamove
1554 * @opxcpttype 4
1555 */
1556FNIEMOP_DEF(iemOp_vmovshdup_Vx_Wx)
1557{
1558 IEMOP_MNEMONIC2(VEX_RM, VMOVSHDUP, vmovshdup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1559 Assert(pVCpu->iem.s.uVexLength <= 1);
1560 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1561 if (IEM_IS_MODRM_REG_MODE(bRm))
1562 {
1563 /*
1564 * Register, register.
1565 */
1566 if (pVCpu->iem.s.uVexLength == 0)
1567 {
1568 IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1569 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1570 IEM_MC_LOCAL(RTUINT128U, uSrc);
1571
1572 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1573 IEM_MC_PREPARE_AVX_USAGE();
1574
1575 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1576 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1577 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1578 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1579 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1580 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1581
1582 IEM_MC_ADVANCE_RIP_AND_FINISH();
1583 IEM_MC_END();
1584 }
1585 else
1586 {
1587 IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1588 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1589 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1590 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1591 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 2);
1592
1593 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1594 IEM_MC_PREPARE_AVX_USAGE();
1595 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovshdup_256_rr, iYRegDst, iYRegSrc);
1596
1597 IEM_MC_ADVANCE_RIP_AND_FINISH();
1598 IEM_MC_END();
1599 }
1600 }
1601 else
1602 {
1603 /*
1604 * Register, memory.
1605 */
1606 if (pVCpu->iem.s.uVexLength == 0)
1607 {
1608 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1609 IEM_MC_LOCAL(RTUINT128U, uSrc);
1610 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1611
1612 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1613 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1614 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1615 IEM_MC_PREPARE_AVX_USAGE();
1616
1617 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1618 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1619 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1620 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1621 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1622 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1623
1624 IEM_MC_ADVANCE_RIP_AND_FINISH();
1625 IEM_MC_END();
1626 }
1627 else
1628 {
1629 IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1630 IEM_MC_LOCAL(RTUINT256U, uSrc);
1631 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1632 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
1633 IEM_MC_ARG_CONST(uint8_t, iYRegDst, IEM_GET_MODRM_REG(pVCpu, bRm), 1);
1634 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
1635
1636 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1637 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1638 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1639 IEM_MC_PREPARE_AVX_USAGE();
1640
1641 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1642 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovshdup_256_rm, iYRegDst, puSrc);
1643
1644 IEM_MC_ADVANCE_RIP_AND_FINISH();
1645 IEM_MC_END();
1646 }
1647 }
1648}
1649
1650
1651/* Opcode VEX.F2.0F 0x16 - invalid */
1652
1653
1654/**
1655 * @opcode 0x17
1656 * @opcodesub !11 mr/reg
1657 * @oppfx none
1658 * @opcpuid avx
1659 * @opgroup og_avx_simdfp_datamove
1660 * @opxcpttype 5
1661 */
1662FNIEMOP_DEF(iemOp_vmovhps_Mq_Vq)
1663{
1664 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1665 if (IEM_IS_MODRM_MEM_MODE(bRm))
1666 {
1667 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPS, vmovhps, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1668
1669 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1670 IEM_MC_LOCAL(uint64_t, uSrc);
1671 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1672
1673 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1674 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1675 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1676 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1677
1678 IEM_MC_FETCH_YREG_2ND_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1679 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1680
1681 IEM_MC_ADVANCE_RIP_AND_FINISH();
1682 IEM_MC_END();
1683 }
1684
1685 /**
1686 * @opdone
1687 * @opmnemonic udvex0f17m3
1688 * @opcode 0x17
1689 * @opcodesub 11 mr/reg
1690 * @oppfx none
1691 * @opunused immediate
1692 * @opcpuid avx
1693 * @optest ->
1694 */
1695 else
1696 IEMOP_RAISE_INVALID_OPCODE_RET();
1697}
1698
1699
1700/**
1701 * @opcode 0x17
1702 * @opcodesub !11 mr/reg
1703 * @oppfx 0x66
1704 * @opcpuid avx
1705 * @opgroup og_avx_pcksclr_datamove
1706 * @opxcpttype 5
1707 */
1708FNIEMOP_DEF(iemOp_vmovhpd_Mq_Vq)
1709{
1710 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1711 if (IEM_IS_MODRM_MEM_MODE(bRm))
1712 {
1713 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPD, vmovhpd, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1714
1715 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1716 IEM_MC_LOCAL(uint64_t, uSrc);
1717 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1718
1719 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1720 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1721 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1722 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1723
1724 IEM_MC_FETCH_YREG_2ND_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1725 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1726
1727 IEM_MC_ADVANCE_RIP_AND_FINISH();
1728 IEM_MC_END();
1729 }
1730
1731 /**
1732 * @opdone
1733 * @opmnemonic udvex660f17m3
1734 * @opcode 0x17
1735 * @opcodesub 11 mr/reg
1736 * @oppfx 0x66
1737 * @opunused immediate
1738 * @opcpuid avx
1739 * @optest ->
1740 */
1741 else
1742 IEMOP_RAISE_INVALID_OPCODE_RET();
1743}
1744
1745
1746/* Opcode VEX.F3.0F 0x17 - invalid */
1747/* Opcode VEX.F2.0F 0x17 - invalid */
1748
1749
1750/* Opcode VEX.0F 0x18 - invalid */
1751/* Opcode VEX.0F 0x19 - invalid */
1752/* Opcode VEX.0F 0x1a - invalid */
1753/* Opcode VEX.0F 0x1b - invalid */
1754/* Opcode VEX.0F 0x1c - invalid */
1755/* Opcode VEX.0F 0x1d - invalid */
1756/* Opcode VEX.0F 0x1e - invalid */
1757/* Opcode VEX.0F 0x1f - invalid */
1758
1759/* Opcode VEX.0F 0x20 - invalid */
1760/* Opcode VEX.0F 0x21 - invalid */
1761/* Opcode VEX.0F 0x22 - invalid */
1762/* Opcode VEX.0F 0x23 - invalid */
1763/* Opcode VEX.0F 0x24 - invalid */
1764/* Opcode VEX.0F 0x25 - invalid */
1765/* Opcode VEX.0F 0x26 - invalid */
1766/* Opcode VEX.0F 0x27 - invalid */
1767
1768/**
1769 * @opcode 0x28
1770 * @oppfx none
1771 * @opcpuid avx
1772 * @opgroup og_avx_pcksclr_datamove
1773 * @opxcpttype 1
1774 * @optest op1=1 op2=2 -> op1=2
1775 * @optest op1=0 op2=-42 -> op1=-42
1776 * @note Almost identical to vmovapd.
1777 */
1778FNIEMOP_DEF(iemOp_vmovaps_Vps_Wps)
1779{
1780 IEMOP_MNEMONIC2(VEX_RM, VMOVAPS, vmovaps, Vps_WO, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1781 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1782 Assert(pVCpu->iem.s.uVexLength <= 1);
1783 if (IEM_IS_MODRM_REG_MODE(bRm))
1784 {
1785 /*
1786 * Register, register.
1787 */
1788 IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1789 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1790
1791 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1792 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1793 if (pVCpu->iem.s.uVexLength == 0)
1794 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1795 IEM_GET_MODRM_RM(pVCpu, bRm));
1796 else
1797 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1798 IEM_GET_MODRM_RM(pVCpu, bRm));
1799 IEM_MC_ADVANCE_RIP_AND_FINISH();
1800 IEM_MC_END();
1801 }
1802 else
1803 {
1804 /*
1805 * Register, memory.
1806 */
1807 if (pVCpu->iem.s.uVexLength == 0)
1808 {
1809 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1810 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1811 IEM_MC_LOCAL(RTUINT128U, uSrc);
1812
1813 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1814 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1815 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1816 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1817
1818 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1819 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1820
1821 IEM_MC_ADVANCE_RIP_AND_FINISH();
1822 IEM_MC_END();
1823 }
1824 else
1825 {
1826 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1827 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1828 IEM_MC_LOCAL(RTUINT256U, uSrc);
1829
1830 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1831 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1832 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1833 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1834
1835 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1836 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1837
1838 IEM_MC_ADVANCE_RIP_AND_FINISH();
1839 IEM_MC_END();
1840 }
1841 }
1842}
1843
1844
1845/**
1846 * @opcode 0x28
1847 * @oppfx 66
1848 * @opcpuid avx
1849 * @opgroup og_avx_pcksclr_datamove
1850 * @opxcpttype 1
1851 * @optest op1=1 op2=2 -> op1=2
1852 * @optest op1=0 op2=-42 -> op1=-42
1853 * @note Almost identical to vmovaps
1854 */
1855FNIEMOP_DEF(iemOp_vmovapd_Vpd_Wpd)
1856{
1857 IEMOP_MNEMONIC2(VEX_RM, VMOVAPD, vmovapd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1858 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1859 Assert(pVCpu->iem.s.uVexLength <= 1);
1860 if (IEM_IS_MODRM_REG_MODE(bRm))
1861 {
1862 /*
1863 * Register, register.
1864 */
1865 IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1866 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1867
1868 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1869 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1870 if (pVCpu->iem.s.uVexLength == 0)
1871 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1872 IEM_GET_MODRM_RM(pVCpu, bRm));
1873 else
1874 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1875 IEM_GET_MODRM_RM(pVCpu, bRm));
1876 IEM_MC_ADVANCE_RIP_AND_FINISH();
1877 IEM_MC_END();
1878 }
1879 else
1880 {
1881 /*
1882 * Register, memory.
1883 */
1884 if (pVCpu->iem.s.uVexLength == 0)
1885 {
1886 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1887 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1888 IEM_MC_LOCAL(RTUINT128U, uSrc);
1889
1890 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1891 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1892 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1893 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1894
1895 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1896 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1897
1898 IEM_MC_ADVANCE_RIP_AND_FINISH();
1899 IEM_MC_END();
1900 }
1901 else
1902 {
1903 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1904 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1905 IEM_MC_LOCAL(RTUINT256U, uSrc);
1906
1907 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1908 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1909 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1910 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1911
1912 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1913 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1914
1915 IEM_MC_ADVANCE_RIP_AND_FINISH();
1916 IEM_MC_END();
1917 }
1918 }
1919}
1920
1921/**
1922 * @opmnemonic udvexf30f28
1923 * @opcode 0x28
1924 * @oppfx 0xf3
1925 * @opunused vex.modrm
1926 * @opcpuid avx
1927 * @optest ->
1928 * @opdone
1929 */
1930
1931/**
1932 * @opmnemonic udvexf20f28
1933 * @opcode 0x28
1934 * @oppfx 0xf2
1935 * @opunused vex.modrm
1936 * @opcpuid avx
1937 * @optest ->
1938 * @opdone
1939 */
1940
1941/**
1942 * @opcode 0x29
1943 * @oppfx none
1944 * @opcpuid avx
1945 * @opgroup og_avx_pcksclr_datamove
1946 * @opxcpttype 1
1947 * @optest op1=1 op2=2 -> op1=2
1948 * @optest op1=0 op2=-42 -> op1=-42
1949 * @note Almost identical to vmovapd.
1950 */
1951FNIEMOP_DEF(iemOp_vmovaps_Wps_Vps)
1952{
1953 IEMOP_MNEMONIC2(VEX_MR, VMOVAPS, vmovaps, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1954 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1955 Assert(pVCpu->iem.s.uVexLength <= 1);
1956 if (IEM_IS_MODRM_REG_MODE(bRm))
1957 {
1958 /*
1959 * Register, register.
1960 */
1961 IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1962 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1963
1964 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1965 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1966 if (pVCpu->iem.s.uVexLength == 0)
1967 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
1968 IEM_GET_MODRM_REG(pVCpu, bRm));
1969 else
1970 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
1971 IEM_GET_MODRM_REG(pVCpu, bRm));
1972 IEM_MC_ADVANCE_RIP_AND_FINISH();
1973 IEM_MC_END();
1974 }
1975 else
1976 {
1977 /*
1978 * Register, memory.
1979 */
1980 if (pVCpu->iem.s.uVexLength == 0)
1981 {
1982 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1983 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1984 IEM_MC_LOCAL(RTUINT128U, uSrc);
1985
1986 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1987 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1988 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1989 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1990
1991 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1992 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1993
1994 IEM_MC_ADVANCE_RIP_AND_FINISH();
1995 IEM_MC_END();
1996 }
1997 else
1998 {
1999 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
2000 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2001 IEM_MC_LOCAL(RTUINT256U, uSrc);
2002
2003 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2004 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2005 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2006 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2007
2008 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2009 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2010
2011 IEM_MC_ADVANCE_RIP_AND_FINISH();
2012 IEM_MC_END();
2013 }
2014 }
2015}
2016
2017/**
2018 * @opcode 0x29
2019 * @oppfx 66
2020 * @opcpuid avx
2021 * @opgroup og_avx_pcksclr_datamove
2022 * @opxcpttype 1
2023 * @optest op1=1 op2=2 -> op1=2
2024 * @optest op1=0 op2=-42 -> op1=-42
2025 * @note Almost identical to vmovaps
2026 */
2027FNIEMOP_DEF(iemOp_vmovapd_Wpd_Vpd)
2028{
2029 IEMOP_MNEMONIC2(VEX_MR, VMOVAPD, vmovapd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2030 Assert(pVCpu->iem.s.uVexLength <= 1);
2031 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2032 if (IEM_IS_MODRM_REG_MODE(bRm))
2033 {
2034 /*
2035 * Register, register.
2036 */
2037 IEM_MC_BEGIN(1, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
2038 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2039
2040 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2041 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2042 if (pVCpu->iem.s.uVexLength == 0)
2043 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2044 IEM_GET_MODRM_REG(pVCpu, bRm));
2045 else
2046 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2047 IEM_GET_MODRM_REG(pVCpu, bRm));
2048 IEM_MC_ADVANCE_RIP_AND_FINISH();
2049 IEM_MC_END();
2050 }
2051 else
2052 {
2053 /*
2054 * Register, memory.
2055 */
2056 if (pVCpu->iem.s.uVexLength == 0)
2057 {
2058 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
2059 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2060 IEM_MC_LOCAL(RTUINT128U, uSrc);
2061
2062 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2063 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2064 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2065 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2066
2067 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2068 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2069
2070 IEM_MC_ADVANCE_RIP_AND_FINISH();
2071 IEM_MC_END();
2072 }
2073 else
2074 {
2075 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
2076 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2077 IEM_MC_LOCAL(RTUINT256U, uSrc);
2078
2079 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2080 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2081 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2082 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2083
2084 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2085 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2086
2087 IEM_MC_ADVANCE_RIP_AND_FINISH();
2088 IEM_MC_END();
2089 }
2090 }
2091}
2092
2093
2094/**
2095 * @opmnemonic udvexf30f29
2096 * @opcode 0x29
2097 * @oppfx 0xf3
2098 * @opunused vex.modrm
2099 * @opcpuid avx
2100 * @optest ->
2101 * @opdone
2102 */
2103
2104/**
2105 * @opmnemonic udvexf20f29
2106 * @opcode 0x29
2107 * @oppfx 0xf2
2108 * @opunused vex.modrm
2109 * @opcpuid avx
2110 * @optest ->
2111 * @opdone
2112 */
2113
2114
2115/** Opcode VEX.0F 0x2a - invalid */
2116/** Opcode VEX.66.0F 0x2a - invalid */
2117/** Opcode VEX.F3.0F 0x2a - vcvtsi2ss Vss, Hss, Ey */
2118FNIEMOP_STUB(iemOp_vcvtsi2ss_Vss_Hss_Ey);
2119/** Opcode VEX.F2.0F 0x2a - vcvtsi2sd Vsd, Hsd, Ey */
2120FNIEMOP_STUB(iemOp_vcvtsi2sd_Vsd_Hsd_Ey);
2121
2122
2123/**
2124 * @opcode 0x2b
2125 * @opcodesub !11 mr/reg
2126 * @oppfx none
2127 * @opcpuid avx
2128 * @opgroup og_avx_cachect
2129 * @opxcpttype 1
2130 * @optest op1=1 op2=2 -> op1=2
2131 * @optest op1=0 op2=-42 -> op1=-42
2132 * @note Identical implementation to vmovntpd
2133 */
2134FNIEMOP_DEF(iemOp_vmovntps_Mps_Vps)
2135{
2136 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPS, vmovntps, Mps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2137 Assert(pVCpu->iem.s.uVexLength <= 1);
2138 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2139 if (IEM_IS_MODRM_MEM_MODE(bRm))
2140 {
2141 /*
2142 * memory, register.
2143 */
2144 if (pVCpu->iem.s.uVexLength == 0)
2145 {
2146 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
2147 IEM_MC_LOCAL(RTUINT128U, uSrc);
2148 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2149
2150 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2151 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2152 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2153 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2154
2155 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2156 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2157
2158 IEM_MC_ADVANCE_RIP_AND_FINISH();
2159 IEM_MC_END();
2160 }
2161 else
2162 {
2163 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
2164 IEM_MC_LOCAL(RTUINT256U, uSrc);
2165 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2166
2167 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2168 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2169 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2170 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2171
2172 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2173 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2174
2175 IEM_MC_ADVANCE_RIP_AND_FINISH();
2176 IEM_MC_END();
2177 }
2178 }
2179 /* The register, register encoding is invalid. */
2180 else
2181 IEMOP_RAISE_INVALID_OPCODE_RET();
2182}
2183
2184/**
2185 * @opcode 0x2b
2186 * @opcodesub !11 mr/reg
2187 * @oppfx 0x66
2188 * @opcpuid avx
2189 * @opgroup og_avx_cachect
2190 * @opxcpttype 1
2191 * @optest op1=1 op2=2 -> op1=2
2192 * @optest op1=0 op2=-42 -> op1=-42
2193 * @note Identical implementation to vmovntps
2194 */
2195FNIEMOP_DEF(iemOp_vmovntpd_Mpd_Vpd)
2196{
2197 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPD, vmovntpd, Mpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2198 Assert(pVCpu->iem.s.uVexLength <= 1);
2199 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2200 if (IEM_IS_MODRM_MEM_MODE(bRm))
2201 {
2202 /*
2203 * memory, register.
2204 */
2205 if (pVCpu->iem.s.uVexLength == 0)
2206 {
2207 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
2208 IEM_MC_LOCAL(RTUINT128U, uSrc);
2209 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2210
2211 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2212 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2213 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2214 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2215
2216 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2217 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2218
2219 IEM_MC_ADVANCE_RIP_AND_FINISH();
2220 IEM_MC_END();
2221 }
2222 else
2223 {
2224 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
2225 IEM_MC_LOCAL(RTUINT256U, uSrc);
2226 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2227
2228 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2229 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2230 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2231 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2232
2233 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2234 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2235
2236 IEM_MC_ADVANCE_RIP_AND_FINISH();
2237 IEM_MC_END();
2238 }
2239 }
2240 /* The register, register encoding is invalid. */
2241 else
2242 IEMOP_RAISE_INVALID_OPCODE_RET();
2243}
2244
2245/**
2246 * @opmnemonic udvexf30f2b
2247 * @opcode 0x2b
2248 * @oppfx 0xf3
2249 * @opunused vex.modrm
2250 * @opcpuid avx
2251 * @optest ->
2252 * @opdone
2253 */
2254
2255/**
2256 * @opmnemonic udvexf20f2b
2257 * @opcode 0x2b
2258 * @oppfx 0xf2
2259 * @opunused vex.modrm
2260 * @opcpuid avx
2261 * @optest ->
2262 * @opdone
2263 */
2264
2265
2266/* Opcode VEX.0F 0x2c - invalid */
2267/* Opcode VEX.66.0F 0x2c - invalid */
2268/** Opcode VEX.F3.0F 0x2c - vcvttss2si Gy, Wss */
2269FNIEMOP_STUB(iemOp_vcvttss2si_Gy_Wss);
2270/** Opcode VEX.F2.0F 0x2c - vcvttsd2si Gy, Wsd */
2271FNIEMOP_STUB(iemOp_vcvttsd2si_Gy_Wsd);
2272
2273/* Opcode VEX.0F 0x2d - invalid */
2274/* Opcode VEX.66.0F 0x2d - invalid */
2275/** Opcode VEX.F3.0F 0x2d - vcvtss2si Gy, Wss */
2276FNIEMOP_STUB(iemOp_vcvtss2si_Gy_Wss);
2277/** Opcode VEX.F2.0F 0x2d - vcvtsd2si Gy, Wsd */
2278FNIEMOP_STUB(iemOp_vcvtsd2si_Gy_Wsd);
2279
2280
2281/** Opcode VEX.0F 0x2e - vucomiss Vss, Wss */
2282FNIEMOP_DEF(iemOp_vucomiss_Vss_Wss)
2283{
2284 IEMOP_MNEMONIC2(VEX_RM, VUCOMISS, vucomiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2285 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2286 if (IEM_IS_MODRM_REG_MODE(bRm))
2287 {
2288 /*
2289 * Register, register.
2290 */
2291 IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
2292 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2293 IEM_MC_LOCAL(uint32_t, fEFlags);
2294 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2295 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2296 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2297 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3);
2298 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2299 IEM_MC_PREPARE_AVX_USAGE();
2300 IEM_MC_FETCH_EFLAGS(fEFlags);
2301 IEM_MC_REF_MXCSR(pfMxcsr);
2302 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2303 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2304 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
2305 pfMxcsr, pEFlags, puSrc1, puSrc2);
2306 IEM_MC_IF_MXCSR_XCPT_PENDING() {
2307 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2308 } IEM_MC_ELSE() {
2309 IEM_MC_COMMIT_EFLAGS(fEFlags);
2310 } IEM_MC_ENDIF();
2311
2312 IEM_MC_ADVANCE_RIP_AND_FINISH();
2313 IEM_MC_END();
2314 }
2315 else
2316 {
2317 /*
2318 * Register, memory.
2319 */
2320 IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
2321 IEM_MC_LOCAL(uint32_t, fEFlags);
2322 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2323 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2324 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2325 IEM_MC_LOCAL(X86XMMREG, uSrc2);
2326 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);
2327 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2328
2329 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2330 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2331 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2332 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2333
2334 IEM_MC_PREPARE_AVX_USAGE();
2335 IEM_MC_FETCH_EFLAGS(fEFlags);
2336 IEM_MC_REF_MXCSR(pfMxcsr);
2337 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2338 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
2339 pfMxcsr, pEFlags, puSrc1, puSrc2);
2340 IEM_MC_IF_MXCSR_XCPT_PENDING() {
2341 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2342 } IEM_MC_ELSE() {
2343 IEM_MC_COMMIT_EFLAGS(fEFlags);
2344 } IEM_MC_ENDIF();
2345
2346 IEM_MC_ADVANCE_RIP_AND_FINISH();
2347 IEM_MC_END();
2348 }
2349}
2350
2351
2352/** Opcode VEX.66.0F 0x2e - vucomisd Vsd, Wsd */
2353FNIEMOP_DEF(iemOp_vucomisd_Vsd_Wsd)
2354{
2355 IEMOP_MNEMONIC2(VEX_RM, VUCOMISD, vucomisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2356 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2357 if (IEM_IS_MODRM_REG_MODE(bRm))
2358 {
2359 /*
2360 * Register, register.
2361 */
2362 IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
2363 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2364 IEM_MC_LOCAL(uint32_t, fEFlags);
2365 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2366 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2367 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2368 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3);
2369 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2370 IEM_MC_PREPARE_AVX_USAGE();
2371 IEM_MC_FETCH_EFLAGS(fEFlags);
2372 IEM_MC_REF_MXCSR(pfMxcsr);
2373 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2374 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2375 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
2376 pfMxcsr, pEFlags, puSrc1, puSrc2);
2377 IEM_MC_IF_MXCSR_XCPT_PENDING() {
2378 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2379 } IEM_MC_ELSE() {
2380 IEM_MC_COMMIT_EFLAGS(fEFlags);
2381 } IEM_MC_ENDIF();
2382
2383 IEM_MC_ADVANCE_RIP_AND_FINISH();
2384 IEM_MC_END();
2385 }
2386 else
2387 {
2388 /*
2389 * Register, memory.
2390 */
2391 IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
2392 IEM_MC_LOCAL(uint32_t, fEFlags);
2393 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2394 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2395 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2396 IEM_MC_LOCAL(X86XMMREG, uSrc2);
2397 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);
2398 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2399
2400 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2401 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2402 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2403 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2404
2405 IEM_MC_PREPARE_AVX_USAGE();
2406 IEM_MC_FETCH_EFLAGS(fEFlags);
2407 IEM_MC_REF_MXCSR(pfMxcsr);
2408 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2409 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
2410 pfMxcsr, pEFlags, puSrc1, puSrc2);
2411 IEM_MC_IF_MXCSR_XCPT_PENDING() {
2412 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2413 } IEM_MC_ELSE() {
2414 IEM_MC_COMMIT_EFLAGS(fEFlags);
2415 } IEM_MC_ENDIF();
2416
2417 IEM_MC_ADVANCE_RIP_AND_FINISH();
2418 IEM_MC_END();
2419 }
2420}
2421
2422
2423/* Opcode VEX.F3.0F 0x2e - invalid */
2424/* Opcode VEX.F2.0F 0x2e - invalid */
2425
2426/** Opcode VEX.0F 0x2f - vcomiss Vss, Wss */
2427FNIEMOP_DEF(iemOp_vcomiss_Vss_Wss)
2428{
2429 IEMOP_MNEMONIC2(VEX_RM, VCOMISS, vcomiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2430 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2431 if (IEM_IS_MODRM_REG_MODE(bRm))
2432 {
2433 /*
2434 * Register, register.
2435 */
2436 IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
2437 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2438 IEM_MC_LOCAL(uint32_t, fEFlags);
2439 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2440 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2441 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2442 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3);
2443 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2444 IEM_MC_PREPARE_AVX_USAGE();
2445 IEM_MC_FETCH_EFLAGS(fEFlags);
2446 IEM_MC_REF_MXCSR(pfMxcsr);
2447 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2448 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2449 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
2450 pfMxcsr, pEFlags, puSrc1, puSrc2);
2451 IEM_MC_IF_MXCSR_XCPT_PENDING() {
2452 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2453 } IEM_MC_ELSE() {
2454 IEM_MC_COMMIT_EFLAGS(fEFlags);
2455 } IEM_MC_ENDIF();
2456
2457 IEM_MC_ADVANCE_RIP_AND_FINISH();
2458 IEM_MC_END();
2459 }
2460 else
2461 {
2462 /*
2463 * Register, memory.
2464 */
2465 IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
2466 IEM_MC_LOCAL(uint32_t, fEFlags);
2467 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2468 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2469 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2470 IEM_MC_LOCAL(X86XMMREG, uSrc2);
2471 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);
2472 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2473
2474 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2475 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2476 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2477 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2478
2479 IEM_MC_PREPARE_AVX_USAGE();
2480 IEM_MC_FETCH_EFLAGS(fEFlags);
2481 IEM_MC_REF_MXCSR(pfMxcsr);
2482 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2483 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
2484 pfMxcsr, pEFlags, puSrc1, puSrc2);
2485 IEM_MC_IF_MXCSR_XCPT_PENDING() {
2486 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2487 } IEM_MC_ELSE() {
2488 IEM_MC_COMMIT_EFLAGS(fEFlags);
2489 } IEM_MC_ENDIF();
2490
2491 IEM_MC_ADVANCE_RIP_AND_FINISH();
2492 IEM_MC_END();
2493 }
2494}
2495
2496
2497/** Opcode VEX.66.0F 0x2f - vcomisd Vsd, Wsd */
2498FNIEMOP_DEF(iemOp_vcomisd_Vsd_Wsd)
2499{
2500 IEMOP_MNEMONIC2(VEX_RM, VCOMISD, vcomisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2501 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2502 if (IEM_IS_MODRM_REG_MODE(bRm))
2503 {
2504 /*
2505 * Register, register.
2506 */
2507 IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
2508 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2509 IEM_MC_LOCAL(uint32_t, fEFlags);
2510 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2511 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2512 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2513 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3);
2514 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2515 IEM_MC_PREPARE_AVX_USAGE();
2516 IEM_MC_FETCH_EFLAGS(fEFlags);
2517 IEM_MC_REF_MXCSR(pfMxcsr);
2518 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2519 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2520 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
2521 pfMxcsr, pEFlags, puSrc1, puSrc2);
2522 IEM_MC_IF_MXCSR_XCPT_PENDING() {
2523 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2524 } IEM_MC_ELSE() {
2525 IEM_MC_COMMIT_EFLAGS(fEFlags);
2526 } IEM_MC_ENDIF();
2527
2528 IEM_MC_ADVANCE_RIP_AND_FINISH();
2529 IEM_MC_END();
2530 }
2531 else
2532 {
2533 /*
2534 * Register, memory.
2535 */
2536 IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
2537 IEM_MC_LOCAL(uint32_t, fEFlags);
2538 IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
2539 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1);
2540 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2);
2541 IEM_MC_LOCAL(X86XMMREG, uSrc2);
2542 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);
2543 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2544
2545 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2546 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2547 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2548 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2549
2550 IEM_MC_PREPARE_AVX_USAGE();
2551 IEM_MC_FETCH_EFLAGS(fEFlags);
2552 IEM_MC_REF_MXCSR(pfMxcsr);
2553 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
2554 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
2555 pfMxcsr, pEFlags, puSrc1, puSrc2);
2556 IEM_MC_IF_MXCSR_XCPT_PENDING() {
2557 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2558 } IEM_MC_ELSE() {
2559 IEM_MC_COMMIT_EFLAGS(fEFlags);
2560 } IEM_MC_ENDIF();
2561
2562 IEM_MC_ADVANCE_RIP_AND_FINISH();
2563 IEM_MC_END();
2564 }
2565}
2566
2567
2568/* Opcode VEX.F3.0F 0x2f - invalid */
2569/* Opcode VEX.F2.0F 0x2f - invalid */
2570
2571/* Opcode VEX.0F 0x30 - invalid */
2572/* Opcode VEX.0F 0x31 - invalid */
2573/* Opcode VEX.0F 0x32 - invalid */
2574/* Opcode VEX.0F 0x33 - invalid */
2575/* Opcode VEX.0F 0x34 - invalid */
2576/* Opcode VEX.0F 0x35 - invalid */
2577/* Opcode VEX.0F 0x36 - invalid */
2578/* Opcode VEX.0F 0x37 - invalid */
2579/* Opcode VEX.0F 0x38 - invalid */
2580/* Opcode VEX.0F 0x39 - invalid */
2581/* Opcode VEX.0F 0x3a - invalid */
2582/* Opcode VEX.0F 0x3b - invalid */
2583/* Opcode VEX.0F 0x3c - invalid */
2584/* Opcode VEX.0F 0x3d - invalid */
2585/* Opcode VEX.0F 0x3e - invalid */
2586/* Opcode VEX.0F 0x3f - invalid */
2587/* Opcode VEX.0F 0x40 - invalid */
2588/* Opcode VEX.0F 0x41 - invalid */
2589/* Opcode VEX.0F 0x42 - invalid */
2590/* Opcode VEX.0F 0x43 - invalid */
2591/* Opcode VEX.0F 0x44 - invalid */
2592/* Opcode VEX.0F 0x45 - invalid */
2593/* Opcode VEX.0F 0x46 - invalid */
2594/* Opcode VEX.0F 0x47 - invalid */
2595/* Opcode VEX.0F 0x48 - invalid */
2596/* Opcode VEX.0F 0x49 - invalid */
2597/* Opcode VEX.0F 0x4a - invalid */
2598/* Opcode VEX.0F 0x4b - invalid */
2599/* Opcode VEX.0F 0x4c - invalid */
2600/* Opcode VEX.0F 0x4d - invalid */
2601/* Opcode VEX.0F 0x4e - invalid */
2602/* Opcode VEX.0F 0x4f - invalid */
2603
2604
2605/** Opcode VEX.0F 0x50 - vmovmskps Gy, Ups */
2606FNIEMOP_DEF(iemOp_vmovmskps_Gy_Ups)
2607{
2608 IEMOP_MNEMONIC2(VEX_RM_REG, VMOVMSKPS, vmovmskps, Gd, Ux, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2609 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2610 if (IEM_IS_MODRM_REG_MODE(bRm))
2611 {
2612 /*
2613 * Register, register.
2614 */
2615 if (pVCpu->iem.s.uVexLength == 0)
2616 {
2617 IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
2618 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2619 IEM_MC_LOCAL(uint8_t, u8Dst);
2620 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2621 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
2622 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2623 IEM_MC_PREPARE_AVX_USAGE();
2624 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2625 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmovmskps_u128, iemAImpl_vmovmskps_u128_fallback),
2626 pu8Dst, puSrc);
2627 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2628 IEM_MC_ADVANCE_RIP_AND_FINISH();
2629 IEM_MC_END();
2630 }
2631 else
2632 {
2633 IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
2634 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
2635 IEM_MC_LOCAL(uint8_t, u8Dst);
2636 IEM_MC_LOCAL(RTUINT256U, uSrc);
2637 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2638 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
2639
2640 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2641 IEM_MC_PREPARE_AVX_USAGE();
2642 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2643 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vmovmskps_u256, iemAImpl_vmovmskps_u256_fallback),
2644 pu8Dst, puSrc);
2645 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2646 IEM_MC_ADVANCE_RIP_AND_FINISH();
2647 IEM_MC_END();
2648 }
2649 }
2650 /* No memory operand. */
2651 else
2652 IEMOP_RAISE_INVALID_OPCODE_RET();
2653}
2654
2655
2656/** Opcode VEX.66.0F 0x50 - vmovmskpd Gy,Upd */
2657FNIEMOP_DEF(iemOp_vmovmskpd_Gy_Upd)
2658{
2659 IEMOP_MNEMONIC2(VEX_RM_REG, VMOVMSKPD, vmovmskpd, Gd, Ux, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2660 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2661 if (IEM_IS_MODRM_REG_MODE(bRm))
2662 {
2663 /*
2664 * Register, register.
2665 */
2666 if (pVCpu->iem.s.uVexLength == 0)
2667 {
2668 IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
2669 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2670 IEM_MC_LOCAL(uint8_t, u8Dst);
2671 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2672 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
2673 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2674 IEM_MC_PREPARE_AVX_USAGE();
2675 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2676 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmovmskpd_u128, iemAImpl_vmovmskpd_u128_fallback),
2677 pu8Dst, puSrc);
2678 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2679 IEM_MC_ADVANCE_RIP_AND_FINISH();
2680 IEM_MC_END();
2681 }
2682 else
2683 {
2684 IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
2685 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
2686 IEM_MC_LOCAL(uint8_t, u8Dst);
2687 IEM_MC_LOCAL(RTUINT256U, uSrc);
2688 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2689 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
2690
2691 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2692 IEM_MC_PREPARE_AVX_USAGE();
2693 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2694 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vmovmskpd_u256, iemAImpl_vmovmskpd_u256_fallback),
2695 pu8Dst, puSrc);
2696 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2697 IEM_MC_ADVANCE_RIP_AND_FINISH();
2698 IEM_MC_END();
2699 }
2700 }
2701 /* No memory operand. */
2702 else
2703 IEMOP_RAISE_INVALID_OPCODE_RET();
2704}
2705
2706
2707/* Opcode VEX.F3.0F 0x50 - invalid */
2708/* Opcode VEX.F2.0F 0x50 - invalid */
2709
2710/** Opcode VEX.0F 0x51 - vsqrtps Vps, Wps */
2711FNIEMOP_STUB(iemOp_vsqrtps_Vps_Wps);
2712/** Opcode VEX.66.0F 0x51 - vsqrtpd Vpd, Wpd */
2713FNIEMOP_STUB(iemOp_vsqrtpd_Vpd_Wpd);
2714/** Opcode VEX.F3.0F 0x51 - vsqrtss Vss, Hss, Wss */
2715FNIEMOP_STUB(iemOp_vsqrtss_Vss_Hss_Wss);
2716/** Opcode VEX.F2.0F 0x51 - vsqrtsd Vsd, Hsd, Wsd */
2717FNIEMOP_STUB(iemOp_vsqrtsd_Vsd_Hsd_Wsd);
2718
2719/** Opcode VEX.0F 0x52 - vrsqrtps Vps, Wps */
2720FNIEMOP_STUB(iemOp_vrsqrtps_Vps_Wps);
2721/* Opcode VEX.66.0F 0x52 - invalid */
2722/** Opcode VEX.F3.0F 0x52 - vrsqrtss Vss, Hss, Wss */
2723FNIEMOP_STUB(iemOp_vrsqrtss_Vss_Hss_Wss);
2724/* Opcode VEX.F2.0F 0x52 - invalid */
2725
2726/** Opcode VEX.0F 0x53 - vrcpps Vps, Wps */
2727FNIEMOP_STUB(iemOp_vrcpps_Vps_Wps);
2728/* Opcode VEX.66.0F 0x53 - invalid */
2729/** Opcode VEX.F3.0F 0x53 - vrcpss Vss, Hss, Wss */
2730FNIEMOP_STUB(iemOp_vrcpss_Vss_Hss_Wss);
2731/* Opcode VEX.F2.0F 0x53 - invalid */
2732
2733
2734/** Opcode VEX.0F 0x54 - vandps Vps, Hps, Wps */
2735FNIEMOP_DEF(iemOp_vandps_Vps_Hps_Wps)
2736{
2737 IEMOP_MNEMONIC3(VEX_RVM, VANDPS, vandps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2738 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2739 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2740}
2741
2742
2743/** Opcode VEX.66.0F 0x54 - vandpd Vpd, Hpd, Wpd */
2744FNIEMOP_DEF(iemOp_vandpd_Vpd_Hpd_Wpd)
2745{
2746 IEMOP_MNEMONIC3(VEX_RVM, VANDPD, vandpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2747 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2748 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2749}
2750
2751
2752/* Opcode VEX.F3.0F 0x54 - invalid */
2753/* Opcode VEX.F2.0F 0x54 - invalid */
2754
2755
2756/** Opcode VEX.0F 0x55 - vandnps Vps, Hps, Wps */
2757FNIEMOP_DEF(iemOp_vandnps_Vps_Hps_Wps)
2758{
2759 IEMOP_MNEMONIC3(VEX_RVM, VANDNPS, vandnps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2760 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2761 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2762}
2763
2764
2765/** Opcode VEX.66.0F 0x55 - vandnpd Vpd, Hpd, Wpd */
2766FNIEMOP_DEF(iemOp_vandnpd_Vpd_Hpd_Wpd)
2767{
2768 IEMOP_MNEMONIC3(VEX_RVM, VANDNPD, vandnpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2769 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2770 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2771}
2772
2773
2774/* Opcode VEX.F3.0F 0x55 - invalid */
2775/* Opcode VEX.F2.0F 0x55 - invalid */
2776
2777/** Opcode VEX.0F 0x56 - vorps Vps, Hps, Wps */
2778FNIEMOP_DEF(iemOp_vorps_Vps_Hps_Wps)
2779{
2780 IEMOP_MNEMONIC3(VEX_RVM, VORPS, vorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2781 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2782 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2783}
2784
2785
2786/** Opcode VEX.66.0F 0x56 - vorpd Vpd, Hpd, Wpd */
2787FNIEMOP_DEF(iemOp_vorpd_Vpd_Hpd_Wpd)
2788{
2789 IEMOP_MNEMONIC3(VEX_RVM, VORPD, vorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2790 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2791 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2792}
2793
2794
2795/* Opcode VEX.F3.0F 0x56 - invalid */
2796/* Opcode VEX.F2.0F 0x56 - invalid */
2797
2798
2799/** Opcode VEX.0F 0x57 - vxorps Vps, Hps, Wps */
2800FNIEMOP_DEF(iemOp_vxorps_Vps_Hps_Wps)
2801{
2802 IEMOP_MNEMONIC3(VEX_RVM, VXORPS, vxorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2803 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2804 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2805}
2806
2807
2808/** Opcode VEX.66.0F 0x57 - vxorpd Vpd, Hpd, Wpd */
2809FNIEMOP_DEF(iemOp_vxorpd_Vpd_Hpd_Wpd)
2810{
2811 IEMOP_MNEMONIC3(VEX_RVM, VXORPD, vxorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2812 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
2813 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2814}
2815
2816
2817/* Opcode VEX.F3.0F 0x57 - invalid */
2818/* Opcode VEX.F2.0F 0x57 - invalid */
2819
2820/** Opcode VEX.0F 0x58 - vaddps Vps, Hps, Wps */
2821FNIEMOP_STUB(iemOp_vaddps_Vps_Hps_Wps);
2822/** Opcode VEX.66.0F 0x58 - vaddpd Vpd, Hpd, Wpd */
2823FNIEMOP_STUB(iemOp_vaddpd_Vpd_Hpd_Wpd);
2824/** Opcode VEX.F3.0F 0x58 - vaddss Vss, Hss, Wss */
2825FNIEMOP_STUB(iemOp_vaddss_Vss_Hss_Wss);
2826/** Opcode VEX.F2.0F 0x58 - vaddsd Vsd, Hsd, Wsd */
2827FNIEMOP_STUB(iemOp_vaddsd_Vsd_Hsd_Wsd);
2828
2829/** Opcode VEX.0F 0x59 - vmulps Vps, Hps, Wps */
2830FNIEMOP_STUB(iemOp_vmulps_Vps_Hps_Wps);
2831/** Opcode VEX.66.0F 0x59 - vmulpd Vpd, Hpd, Wpd */
2832FNIEMOP_STUB(iemOp_vmulpd_Vpd_Hpd_Wpd);
2833/** Opcode VEX.F3.0F 0x59 - vmulss Vss, Hss, Wss */
2834FNIEMOP_STUB(iemOp_vmulss_Vss_Hss_Wss);
2835/** Opcode VEX.F2.0F 0x59 - vmulsd Vsd, Hsd, Wsd */
2836FNIEMOP_STUB(iemOp_vmulsd_Vsd_Hsd_Wsd);
2837
2838/** Opcode VEX.0F 0x5a - vcvtps2pd Vpd, Wps */
2839FNIEMOP_STUB(iemOp_vcvtps2pd_Vpd_Wps);
2840/** Opcode VEX.66.0F 0x5a - vcvtpd2ps Vps, Wpd */
2841FNIEMOP_STUB(iemOp_vcvtpd2ps_Vps_Wpd);
2842/** Opcode VEX.F3.0F 0x5a - vcvtss2sd Vsd, Hx, Wss */
2843FNIEMOP_STUB(iemOp_vcvtss2sd_Vsd_Hx_Wss);
2844/** Opcode VEX.F2.0F 0x5a - vcvtsd2ss Vss, Hx, Wsd */
2845FNIEMOP_STUB(iemOp_vcvtsd2ss_Vss_Hx_Wsd);
2846
2847/** Opcode VEX.0F 0x5b - vcvtdq2ps Vps, Wdq */
2848FNIEMOP_STUB(iemOp_vcvtdq2ps_Vps_Wdq);
2849/** Opcode VEX.66.0F 0x5b - vcvtps2dq Vdq, Wps */
2850FNIEMOP_STUB(iemOp_vcvtps2dq_Vdq_Wps);
2851/** Opcode VEX.F3.0F 0x5b - vcvttps2dq Vdq, Wps */
2852FNIEMOP_STUB(iemOp_vcvttps2dq_Vdq_Wps);
2853/* Opcode VEX.F2.0F 0x5b - invalid */
2854
2855/** Opcode VEX.0F 0x5c - vsubps Vps, Hps, Wps */
2856FNIEMOP_STUB(iemOp_vsubps_Vps_Hps_Wps);
2857/** Opcode VEX.66.0F 0x5c - vsubpd Vpd, Hpd, Wpd */
2858FNIEMOP_STUB(iemOp_vsubpd_Vpd_Hpd_Wpd);
2859/** Opcode VEX.F3.0F 0x5c - vsubss Vss, Hss, Wss */
2860FNIEMOP_STUB(iemOp_vsubss_Vss_Hss_Wss);
2861/** Opcode VEX.F2.0F 0x5c - vsubsd Vsd, Hsd, Wsd */
2862FNIEMOP_STUB(iemOp_vsubsd_Vsd_Hsd_Wsd);
2863
2864/** Opcode VEX.0F 0x5d - vminps Vps, Hps, Wps */
2865FNIEMOP_STUB(iemOp_vminps_Vps_Hps_Wps);
2866/** Opcode VEX.66.0F 0x5d - vminpd Vpd, Hpd, Wpd */
2867FNIEMOP_STUB(iemOp_vminpd_Vpd_Hpd_Wpd);
2868/** Opcode VEX.F3.0F 0x5d - vminss Vss, Hss, Wss */
2869FNIEMOP_STUB(iemOp_vminss_Vss_Hss_Wss);
2870/** Opcode VEX.F2.0F 0x5d - vminsd Vsd, Hsd, Wsd */
2871FNIEMOP_STUB(iemOp_vminsd_Vsd_Hsd_Wsd);
2872
2873/** Opcode VEX.0F 0x5e - vdivps Vps, Hps, Wps */
2874FNIEMOP_STUB(iemOp_vdivps_Vps_Hps_Wps);
2875/** Opcode VEX.66.0F 0x5e - vdivpd Vpd, Hpd, Wpd */
2876FNIEMOP_STUB(iemOp_vdivpd_Vpd_Hpd_Wpd);
2877/** Opcode VEX.F3.0F 0x5e - vdivss Vss, Hss, Wss */
2878FNIEMOP_STUB(iemOp_vdivss_Vss_Hss_Wss);
2879/** Opcode VEX.F2.0F 0x5e - vdivsd Vsd, Hsd, Wsd */
2880FNIEMOP_STUB(iemOp_vdivsd_Vsd_Hsd_Wsd);
2881
2882/** Opcode VEX.0F 0x5f - vmaxps Vps, Hps, Wps */
2883FNIEMOP_STUB(iemOp_vmaxps_Vps_Hps_Wps);
2884/** Opcode VEX.66.0F 0x5f - vmaxpd Vpd, Hpd, Wpd */
2885FNIEMOP_STUB(iemOp_vmaxpd_Vpd_Hpd_Wpd);
2886/** Opcode VEX.F3.0F 0x5f - vmaxss Vss, Hss, Wss */
2887FNIEMOP_STUB(iemOp_vmaxss_Vss_Hss_Wss);
2888/** Opcode VEX.F2.0F 0x5f - vmaxsd Vsd, Hsd, Wsd */
2889FNIEMOP_STUB(iemOp_vmaxsd_Vsd_Hsd_Wsd);
2890
2891
2892/* Opcode VEX.0F 0x60 - invalid */
2893
2894
2895/** Opcode VEX.66.0F 0x60 - vpunpcklbw Vx, Hx, Wx */
2896FNIEMOP_DEF(iemOp_vpunpcklbw_Vx_Hx_Wx)
2897{
2898 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLBW, vpunpcklbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2899 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklbw);
2900 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2901}
2902
2903
2904/* Opcode VEX.F3.0F 0x60 - invalid */
2905
2906
2907/* Opcode VEX.0F 0x61 - invalid */
2908
2909
2910/** Opcode VEX.66.0F 0x61 - vpunpcklwd Vx, Hx, Wx */
2911FNIEMOP_DEF(iemOp_vpunpcklwd_Vx_Hx_Wx)
2912{
2913 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLWD, vpunpcklwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2914 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklwd);
2915 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2916}
2917
2918
2919/* Opcode VEX.F3.0F 0x61 - invalid */
2920
2921
2922/* Opcode VEX.0F 0x62 - invalid */
2923
2924/** Opcode VEX.66.0F 0x62 - vpunpckldq Vx, Hx, Wx */
2925FNIEMOP_DEF(iemOp_vpunpckldq_Vx_Hx_Wx)
2926{
2927 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLDQ, vpunpckldq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2928 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckldq);
2929 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2930}
2931
2932
2933/* Opcode VEX.F3.0F 0x62 - invalid */
2934
2935
2936
2937/* Opcode VEX.0F 0x63 - invalid */
2938
2939
2940/** Opcode VEX.66.0F 0x63 - vpacksswb Vx, Hx, Wx */
2941FNIEMOP_DEF(iemOp_vpacksswb_Vx_Hx_Wx)
2942{
2943 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSWB, vpacksswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2944 IEMOPMEDIAOPTF3_INIT_VARS( vpacksswb);
2945 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2946}
2947
2948
2949/* Opcode VEX.F3.0F 0x63 - invalid */
2950
2951/* Opcode VEX.0F 0x64 - invalid */
2952
2953
2954/** Opcode VEX.66.0F 0x64 - vpcmpgtb Vx, Hx, Wx */
2955FNIEMOP_DEF(iemOp_vpcmpgtb_Vx_Hx_Wx)
2956{
2957 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTB, vpcmpgtb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
2958 IEMOPMEDIAF3_INIT_VARS( vpcmpgtb);
2959 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2960}
2961
2962
2963/* Opcode VEX.F3.0F 0x64 - invalid */
2964
2965/* Opcode VEX.0F 0x65 - invalid */
2966
2967
2968/** Opcode VEX.66.0F 0x65 - vpcmpgtw Vx, Hx, Wx */
2969FNIEMOP_DEF(iemOp_vpcmpgtw_Vx_Hx_Wx)
2970{
2971 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTW, vpcmpgtw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
2972 IEMOPMEDIAF3_INIT_VARS( vpcmpgtw);
2973 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2974}
2975
2976
2977/* Opcode VEX.F3.0F 0x65 - invalid */
2978
2979/* Opcode VEX.0F 0x66 - invalid */
2980
2981
2982/** Opcode VEX.66.0F 0x66 - vpcmpgtd Vx, Hx, Wx */
2983FNIEMOP_DEF(iemOp_vpcmpgtd_Vx_Hx_Wx)
2984{
2985 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTD, vpcmpgtd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
2986 IEMOPMEDIAF3_INIT_VARS( vpcmpgtd);
2987 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
2988}
2989
2990
2991/* Opcode VEX.F3.0F 0x66 - invalid */
2992
2993/* Opcode VEX.0F 0x67 - invalid */
2994
2995
2996/** Opcode VEX.66.0F 0x67 - vpackuswb Vx, Hx, W */
2997FNIEMOP_DEF(iemOp_vpackuswb_Vx_Hx_W)
2998{
2999 IEMOP_MNEMONIC3(VEX_RVM, VPACKUSWB, vpackuswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3000 IEMOPMEDIAOPTF3_INIT_VARS( vpackuswb);
3001 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3002}
3003
3004
3005/* Opcode VEX.F3.0F 0x67 - invalid */
3006
3007
3008///**
3009// * Common worker for SSE2 instructions on the form:
3010// * pxxxx xmm1, xmm2/mem128
3011// *
3012// * The 2nd operand is the second half of a register, which in the memory case
3013// * means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
3014// * where it may read the full 128 bits or only the upper 64 bits.
3015// *
3016// * Exceptions type 4.
3017// */
3018//FNIEMOP_DEF_1(iemOpCommonSse_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
3019//{
3020// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3021// if (IEM_IS_MODRM_REG_MODE(bRm))
3022// {
3023// /*
3024// * Register, register.
3025// */
3026// IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
3027// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
3028// IEM_MC_ARG(PRTUINT128U, pDst, 0);
3029// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
3030// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
3031// IEM_MC_PREPARE_SSE_USAGE();
3032// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3033// IEM_MC_REF_XREG_U128_CONST(pSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3034// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3035// IEM_MC_ADVANCE_RIP_AND_FINISH();
3036// IEM_MC_END();
3037// }
3038// else
3039// {
3040// /*
3041// * Register, memory.
3042// */
3043// IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
3044// IEM_MC_ARG(PRTUINT128U, pDst, 0);
3045// IEM_MC_LOCAL(RTUINT128U, uSrc);
3046// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
3047// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3048//
3049// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3050// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
3051// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
3052// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */
3053//
3054// IEM_MC_PREPARE_SSE_USAGE();
3055// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3056// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3057//
3058// IEM_MC_ADVANCE_RIP_AND_FINISH();
3059// IEM_MC_END();
3060// }
3061// return VINF_SUCCESS;
3062//}
3063
3064
3065/* Opcode VEX.0F 0x68 - invalid */
3066
3067/** Opcode VEX.66.0F 0x68 - vpunpckhbw Vx, Hx, Wx */
3068FNIEMOP_DEF(iemOp_vpunpckhbw_Vx_Hx_Wx)
3069{
3070 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHBW, vpunpckhbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3071 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhbw);
3072 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3073}
3074
3075
3076/* Opcode VEX.F3.0F 0x68 - invalid */
3077
3078
3079/* Opcode VEX.0F 0x69 - invalid */
3080
3081
3082/** Opcode VEX.66.0F 0x69 - vpunpckhwd Vx, Hx, Wx */
3083FNIEMOP_DEF(iemOp_vpunpckhwd_Vx_Hx_Wx)
3084{
3085 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHWD, vpunpckhwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3086 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhwd);
3087 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3088}
3089
3090
3091/* Opcode VEX.F3.0F 0x69 - invalid */
3092
3093
3094/* Opcode VEX.0F 0x6a - invalid */
3095
3096
3097/** Opcode VEX.66.0F 0x6a - vpunpckhdq Vx, Hx, W */
3098FNIEMOP_DEF(iemOp_vpunpckhdq_Vx_Hx_W)
3099{
3100 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHDQ, vpunpckhdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3101 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhdq);
3102 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3103}
3104
3105
3106/* Opcode VEX.F3.0F 0x6a - invalid */
3107
3108
3109/* Opcode VEX.0F 0x6b - invalid */
3110
3111
3112/** Opcode VEX.66.0F 0x6b - vpackssdw Vx, Hx, Wx */
3113FNIEMOP_DEF(iemOp_vpackssdw_Vx_Hx_Wx)
3114{
3115 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSDW, vpackssdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3116 IEMOPMEDIAOPTF3_INIT_VARS( vpackssdw);
3117 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3118}
3119
3120
3121/* Opcode VEX.F3.0F 0x6b - invalid */
3122
3123
3124/* Opcode VEX.0F 0x6c - invalid */
3125
3126
3127/** Opcode VEX.66.0F 0x6c - vpunpcklqdq Vx, Hx, Wx */
3128FNIEMOP_DEF(iemOp_vpunpcklqdq_Vx_Hx_Wx)
3129{
3130 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLQDQ, vpunpcklqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3131 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklqdq);
3132 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3133}
3134
3135
3136/* Opcode VEX.F3.0F 0x6c - invalid */
3137/* Opcode VEX.F2.0F 0x6c - invalid */
3138
3139
3140/* Opcode VEX.0F 0x6d - invalid */
3141
3142
3143/** Opcode VEX.66.0F 0x6d - vpunpckhqdq Vx, Hx, W */
3144FNIEMOP_DEF(iemOp_vpunpckhqdq_Vx_Hx_W)
3145{
3146 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHQDQ, vpunpckhqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3147 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhqdq);
3148 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3149}
3150
3151
3152/* Opcode VEX.F3.0F 0x6d - invalid */
3153
3154
3155/* Opcode VEX.0F 0x6e - invalid */
3156
3157FNIEMOP_DEF(iemOp_vmovd_q_Vy_Ey)
3158{
3159 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3160 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3161 {
3162 /**
3163 * @opcode 0x6e
3164 * @opcodesub rex.w=1
3165 * @oppfx 0x66
3166 * @opcpuid avx
3167 * @opgroup og_avx_simdint_datamov
3168 * @opxcpttype 5
3169 * @optest 64-bit / op1=1 op2=2 -> op1=2
3170 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
3171 */
3172 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Eq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3173 if (IEM_IS_MODRM_REG_MODE(bRm))
3174 {
3175 /* XMM, greg64 */
3176 IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
3177 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3178 IEM_MC_LOCAL(uint64_t, u64Tmp);
3179
3180 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3181 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3182
3183 IEM_MC_FETCH_GREG_U64(u64Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
3184 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
3185
3186 IEM_MC_ADVANCE_RIP_AND_FINISH();
3187 IEM_MC_END();
3188 }
3189 else
3190 {
3191 /* XMM, [mem64] */
3192 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
3193 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3194 IEM_MC_LOCAL(uint64_t, u64Tmp);
3195
3196 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3197 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3198 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3199 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3200
3201 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3202 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
3203
3204 IEM_MC_ADVANCE_RIP_AND_FINISH();
3205 IEM_MC_END();
3206 }
3207 }
3208 else
3209 {
3210 /**
3211 * @opdone
3212 * @opcode 0x6e
3213 * @opcodesub rex.w=0
3214 * @oppfx 0x66
3215 * @opcpuid avx
3216 * @opgroup og_avx_simdint_datamov
3217 * @opxcpttype 5
3218 * @opfunction iemOp_vmovd_q_Vy_Ey
3219 * @optest op1=1 op2=2 -> op1=2
3220 * @optest op1=0 op2=-42 -> op1=-42
3221 */
3222 IEMOP_MNEMONIC2(VEX_RM, VMOVD, vmovd, Vd_WO, Ed, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3223 if (IEM_IS_MODRM_REG_MODE(bRm))
3224 {
3225 /* XMM, greg32 */
3226 IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
3227 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3228 IEM_MC_LOCAL(uint32_t, u32Tmp);
3229
3230 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3231 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3232
3233 IEM_MC_FETCH_GREG_U32(u32Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
3234 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
3235
3236 IEM_MC_ADVANCE_RIP_AND_FINISH();
3237 IEM_MC_END();
3238 }
3239 else
3240 {
3241 /* XMM, [mem32] */
3242 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
3243 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3244 IEM_MC_LOCAL(uint32_t, u32Tmp);
3245
3246 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3247 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3248 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3249 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3250
3251 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3252 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
3253
3254 IEM_MC_ADVANCE_RIP_AND_FINISH();
3255 IEM_MC_END();
3256 }
3257 }
3258}
3259
3260
3261/* Opcode VEX.F3.0F 0x6e - invalid */
3262
3263
3264/* Opcode VEX.0F 0x6f - invalid */
3265
3266/**
3267 * @opcode 0x6f
3268 * @oppfx 0x66
3269 * @opcpuid avx
3270 * @opgroup og_avx_simdint_datamove
3271 * @opxcpttype 1
3272 * @optest op1=1 op2=2 -> op1=2
3273 * @optest op1=0 op2=-42 -> op1=-42
3274 */
3275FNIEMOP_DEF(iemOp_vmovdqa_Vx_Wx)
3276{
3277 IEMOP_MNEMONIC2(VEX_RM, VMOVDQA, vmovdqa, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3278 Assert(pVCpu->iem.s.uVexLength <= 1);
3279 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3280 if (IEM_IS_MODRM_REG_MODE(bRm))
3281 {
3282 /*
3283 * Register, register.
3284 */
3285 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
3286 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3287
3288 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3289 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3290 if (pVCpu->iem.s.uVexLength == 0)
3291 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3292 IEM_GET_MODRM_RM(pVCpu, bRm));
3293 else
3294 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3295 IEM_GET_MODRM_RM(pVCpu, bRm));
3296 IEM_MC_ADVANCE_RIP_AND_FINISH();
3297 IEM_MC_END();
3298 }
3299 else if (pVCpu->iem.s.uVexLength == 0)
3300 {
3301 /*
3302 * Register, memory128.
3303 */
3304 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
3305 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3306 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3307
3308 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3309 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3310 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3311 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3312
3313 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3314 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
3315
3316 IEM_MC_ADVANCE_RIP_AND_FINISH();
3317 IEM_MC_END();
3318 }
3319 else
3320 {
3321 /*
3322 * Register, memory256.
3323 */
3324 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
3325 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3326 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3327
3328 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3329 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3330 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3331 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3332
3333 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3334 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
3335
3336 IEM_MC_ADVANCE_RIP_AND_FINISH();
3337 IEM_MC_END();
3338 }
3339}
3340
3341/**
3342 * @opcode 0x6f
3343 * @oppfx 0xf3
3344 * @opcpuid avx
3345 * @opgroup og_avx_simdint_datamove
3346 * @opxcpttype 4UA
3347 * @optest op1=1 op2=2 -> op1=2
3348 * @optest op1=0 op2=-42 -> op1=-42
3349 */
3350FNIEMOP_DEF(iemOp_vmovdqu_Vx_Wx)
3351{
3352 IEMOP_MNEMONIC2(VEX_RM, VMOVDQU, vmovdqu, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3353 Assert(pVCpu->iem.s.uVexLength <= 1);
3354 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3355 if (IEM_IS_MODRM_REG_MODE(bRm))
3356 {
3357 /*
3358 * Register, register.
3359 */
3360 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
3361 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3362
3363 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3364 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3365 if (pVCpu->iem.s.uVexLength == 0)
3366 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3367 IEM_GET_MODRM_RM(pVCpu, bRm));
3368 else
3369 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3370 IEM_GET_MODRM_RM(pVCpu, bRm));
3371 IEM_MC_ADVANCE_RIP_AND_FINISH();
3372 IEM_MC_END();
3373 }
3374 else if (pVCpu->iem.s.uVexLength == 0)
3375 {
3376 /*
3377 * Register, memory128.
3378 */
3379 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
3380 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3381 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3382
3383 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3384 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3385 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3386 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3387
3388 IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3389 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
3390
3391 IEM_MC_ADVANCE_RIP_AND_FINISH();
3392 IEM_MC_END();
3393 }
3394 else
3395 {
3396 /*
3397 * Register, memory256.
3398 */
3399 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
3400 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3401 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3402
3403 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3404 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3405 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3406 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3407
3408 IEM_MC_FETCH_MEM_U256(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3409 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
3410
3411 IEM_MC_ADVANCE_RIP_AND_FINISH();
3412 IEM_MC_END();
3413 }
3414}
3415
3416
3417/* Opcode VEX.0F 0x70 - invalid */
3418
3419
3420/**
3421 * Common worker for AVX/AVX2 instructions on the forms:
3422 * - vpxxx xmm0, xmm2/mem128, imm8
3423 * - vpxxx ymm0, ymm2/mem256, imm8
3424 *
3425 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
3426 */
3427FNIEMOP_DEF_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, PFNIEMAIMPLMEDIAPSHUFU128, pfnU128, PFNIEMAIMPLMEDIAPSHUFU256, pfnU256)
3428{
3429 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3430 if (IEM_IS_MODRM_REG_MODE(bRm))
3431 {
3432 /*
3433 * Register, register.
3434 */
3435 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3436 if (pVCpu->iem.s.uVexLength)
3437 {
3438 IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
3439 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3440 IEM_MC_LOCAL(RTUINT256U, uDst);
3441 IEM_MC_LOCAL(RTUINT256U, uSrc);
3442 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3443 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3444 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3445 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3446 IEM_MC_PREPARE_AVX_USAGE();
3447 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3448 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg);
3449 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3450 IEM_MC_ADVANCE_RIP_AND_FINISH();
3451 IEM_MC_END();
3452 }
3453 else
3454 {
3455 IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
3456 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3457 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3458 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
3459 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3460 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3461 IEM_MC_PREPARE_AVX_USAGE();
3462 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3463 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3464 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
3465 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3466 IEM_MC_ADVANCE_RIP_AND_FINISH();
3467 IEM_MC_END();
3468 }
3469 }
3470 else
3471 {
3472 /*
3473 * Register, memory.
3474 */
3475 if (pVCpu->iem.s.uVexLength)
3476 {
3477 IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
3478 IEM_MC_LOCAL(RTUINT256U, uDst);
3479 IEM_MC_LOCAL(RTUINT256U, uSrc);
3480 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3481 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3482 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3483
3484 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
3485 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3486 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3487 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3488 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3489 IEM_MC_PREPARE_AVX_USAGE();
3490
3491 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3492 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg);
3493 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3494
3495 IEM_MC_ADVANCE_RIP_AND_FINISH();
3496 IEM_MC_END();
3497 }
3498 else
3499 {
3500 IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
3501 IEM_MC_LOCAL(RTUINT128U, uSrc);
3502 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3503 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3504 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
3505
3506 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
3507 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3508 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3509 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3510 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3511 IEM_MC_PREPARE_AVX_USAGE();
3512
3513 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3514 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3515 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
3516 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3517
3518 IEM_MC_ADVANCE_RIP_AND_FINISH();
3519 IEM_MC_END();
3520 }
3521 }
3522}
3523
3524
3525/** Opcode VEX.66.0F 0x70 - vpshufd Vx, Wx, Ib */
3526FNIEMOP_DEF(iemOp_vpshufd_Vx_Wx_Ib)
3527{
3528 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFD, vpshufd, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3529 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufd_u128,
3530 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufd_u256, iemAImpl_vpshufd_u256_fallback));
3531
3532}
3533
3534
3535/** Opcode VEX.F3.0F 0x70 - vpshufhw Vx, Wx, Ib */
3536FNIEMOP_DEF(iemOp_vpshufhw_Vx_Wx_Ib)
3537{
3538 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFHW, vpshufhw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3539 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufhw_u128,
3540 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufhw_u256, iemAImpl_vpshufhw_u256_fallback));
3541
3542}
3543
3544
3545/** Opcode VEX.F2.0F 0x70 - vpshuflw Vx, Wx, Ib */
3546FNIEMOP_DEF(iemOp_vpshuflw_Vx_Wx_Ib)
3547{
3548 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFLW, vpshuflw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3549 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshuflw_u128,
3550 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshuflw_u256, iemAImpl_vpshuflw_u256_fallback));
3551}
3552
3553
3554/* Opcode VEX.0F 0x71 11/2 - invalid. */
3555/** Opcode VEX.66.0F 0x71 11/2. */
3556FNIEMOP_STUB_1(iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, uint8_t, bRm);
3557
3558/* Opcode VEX.0F 0x71 11/4 - invalid */
3559/** Opcode VEX.66.0F 0x71 11/4. */
3560FNIEMOP_STUB_1(iemOp_VGrp12_vpsraw_Hx_Ux_Ib, uint8_t, bRm);
3561
3562/* Opcode VEX.0F 0x71 11/6 - invalid */
3563/** Opcode VEX.66.0F 0x71 11/6. */
3564FNIEMOP_STUB_1(iemOp_VGrp12_vpsllw_Hx_Ux_Ib, uint8_t, bRm);
3565
3566
3567/**
3568 * VEX Group 12 jump table for register variant.
3569 */
3570IEM_STATIC const PFNIEMOPRM g_apfnVexGroup12RegReg[] =
3571{
3572 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3573 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3574 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3575 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3576 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsraw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3577 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3578 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsllw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3579 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3580};
3581AssertCompile(RT_ELEMENTS(g_apfnVexGroup12RegReg) == 8*4);
3582
3583
3584/** Opcode VEX.0F 0x71. */
3585FNIEMOP_DEF(iemOp_VGrp12)
3586{
3587 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3588 if (IEM_IS_MODRM_REG_MODE(bRm))
3589 /* register, register */
3590 return FNIEMOP_CALL_1(g_apfnVexGroup12RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3591 + pVCpu->iem.s.idxPrefix], bRm);
3592 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3593}
3594
3595
3596/* Opcode VEX.0F 0x72 11/2 - invalid. */
3597/** Opcode VEX.66.0F 0x72 11/2. */
3598FNIEMOP_STUB_1(iemOp_VGrp13_vpsrld_Hx_Ux_Ib, uint8_t, bRm);
3599
3600/* Opcode VEX.0F 0x72 11/4 - invalid. */
3601/** Opcode VEX.66.0F 0x72 11/4. */
3602FNIEMOP_STUB_1(iemOp_VGrp13_vpsrad_Hx_Ux_Ib, uint8_t, bRm);
3603
3604/* Opcode VEX.0F 0x72 11/6 - invalid. */
3605/** Opcode VEX.66.0F 0x72 11/6. */
3606FNIEMOP_STUB_1(iemOp_VGrp13_vpslld_Hx_Ux_Ib, uint8_t, bRm);
3607
3608
3609/**
3610 * Group 13 jump table for register variant.
3611 */
3612IEM_STATIC const PFNIEMOPRM g_apfnVexGroup13RegReg[] =
3613{
3614 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3615 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3616 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3617 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3618 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrad_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3619 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3620 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpslld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3621 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3622};
3623AssertCompile(RT_ELEMENTS(g_apfnVexGroup13RegReg) == 8*4);
3624
3625/** Opcode VEX.0F 0x72. */
3626FNIEMOP_DEF(iemOp_VGrp13)
3627{
3628 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3629 if (IEM_IS_MODRM_REG_MODE(bRm))
3630 /* register, register */
3631 return FNIEMOP_CALL_1(g_apfnVexGroup13RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3632 + pVCpu->iem.s.idxPrefix], bRm);
3633 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3634}
3635
3636
3637/* Opcode VEX.0F 0x73 11/2 - invalid. */
3638/** Opcode VEX.66.0F 0x73 11/2. */
3639FNIEMOP_STUB_1(iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, uint8_t, bRm);
3640
3641/** Opcode VEX.66.0F 0x73 11/3. */
3642FNIEMOP_STUB_1(iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, uint8_t, bRm);
3643
3644/* Opcode VEX.0F 0x73 11/6 - invalid. */
3645/** Opcode VEX.66.0F 0x73 11/6. */
3646FNIEMOP_STUB_1(iemOp_VGrp14_vpsllq_Hx_Ux_Ib, uint8_t, bRm);
3647
3648/** Opcode VEX.66.0F 0x73 11/7. */
3649FNIEMOP_STUB_1(iemOp_VGrp14_vpslldq_Hx_Ux_Ib, uint8_t, bRm);
3650
3651/**
3652 * Group 14 jump table for register variant.
3653 */
3654IEM_STATIC const PFNIEMOPRM g_apfnVexGroup14RegReg[] =
3655{
3656 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3657 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3658 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3659 /* /3 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3660 /* /4 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3661 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3662 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsllq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3663 /* /7 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpslldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3664};
3665AssertCompile(RT_ELEMENTS(g_apfnVexGroup14RegReg) == 8*4);
3666
3667
3668/** Opcode VEX.0F 0x73. */
3669FNIEMOP_DEF(iemOp_VGrp14)
3670{
3671 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3672 if (IEM_IS_MODRM_REG_MODE(bRm))
3673 /* register, register */
3674 return FNIEMOP_CALL_1(g_apfnVexGroup14RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3675 + pVCpu->iem.s.idxPrefix], bRm);
3676 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3677}
3678
3679
3680/* Opcode VEX.0F 0x74 - invalid */
3681
3682
3683/** Opcode VEX.66.0F 0x74 - vpcmpeqb Vx, Hx, Wx */
3684FNIEMOP_DEF(iemOp_vpcmpeqb_Vx_Hx_Wx)
3685{
3686 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQB, vpcmpeqb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3687 IEMOPMEDIAF3_INIT_VARS( vpcmpeqb);
3688 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3689}
3690
3691/* Opcode VEX.F3.0F 0x74 - invalid */
3692/* Opcode VEX.F2.0F 0x74 - invalid */
3693
3694
3695/* Opcode VEX.0F 0x75 - invalid */
3696
3697
3698/** Opcode VEX.66.0F 0x75 - vpcmpeqw Vx, Hx, Wx */
3699FNIEMOP_DEF(iemOp_vpcmpeqw_Vx_Hx_Wx)
3700{
3701 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQW, vpcmpeqw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3702 IEMOPMEDIAF3_INIT_VARS( vpcmpeqw);
3703 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3704}
3705
3706
3707/* Opcode VEX.F3.0F 0x75 - invalid */
3708/* Opcode VEX.F2.0F 0x75 - invalid */
3709
3710
3711/* Opcode VEX.0F 0x76 - invalid */
3712
3713
3714/** Opcode VEX.66.0F 0x76 - vpcmpeqd Vx, Hx, Wx */
3715FNIEMOP_DEF(iemOp_vpcmpeqd_Vx_Hx_Wx)
3716{
3717 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQD, vpcmpeqd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3718 IEMOPMEDIAF3_INIT_VARS( vpcmpeqd);
3719 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3720}
3721
3722
3723/* Opcode VEX.F3.0F 0x76 - invalid */
3724/* Opcode VEX.F2.0F 0x76 - invalid */
3725
3726
3727/** Opcode VEX.0F 0x77 - vzeroupperv vzeroallv */
3728FNIEMOP_DEF(iemOp_vzeroupperv__vzeroallv)
3729{
3730 Assert(pVCpu->iem.s.uVexLength <= 1);
3731 if (pVCpu->iem.s.uVexLength == 0)
3732 {
3733 /*
3734 * 128-bit: vzeroupper
3735 */
3736 IEMOP_MNEMONIC(vzeroupper, "vzeroupper");
3737 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
3738
3739 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3740 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3741 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3742
3743 IEM_MC_CLEAR_YREG_128_UP(0);
3744 IEM_MC_CLEAR_YREG_128_UP(1);
3745 IEM_MC_CLEAR_YREG_128_UP(2);
3746 IEM_MC_CLEAR_YREG_128_UP(3);
3747 IEM_MC_CLEAR_YREG_128_UP(4);
3748 IEM_MC_CLEAR_YREG_128_UP(5);
3749 IEM_MC_CLEAR_YREG_128_UP(6);
3750 IEM_MC_CLEAR_YREG_128_UP(7);
3751
3752 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
3753 {
3754 IEM_MC_CLEAR_YREG_128_UP( 8);
3755 IEM_MC_CLEAR_YREG_128_UP( 9);
3756 IEM_MC_CLEAR_YREG_128_UP(10);
3757 IEM_MC_CLEAR_YREG_128_UP(11);
3758 IEM_MC_CLEAR_YREG_128_UP(12);
3759 IEM_MC_CLEAR_YREG_128_UP(13);
3760 IEM_MC_CLEAR_YREG_128_UP(14);
3761 IEM_MC_CLEAR_YREG_128_UP(15);
3762 }
3763
3764 IEM_MC_ADVANCE_RIP_AND_FINISH();
3765 IEM_MC_END();
3766 }
3767 else
3768 {
3769 /*
3770 * 256-bit: vzeroall
3771 */
3772 IEMOP_MNEMONIC(vzeroall, "vzeroall");
3773 IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
3774 IEM_MC_LOCAL(uint32_t, uZero);
3775
3776 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3777 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3778 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3779
3780 IEM_MC_ASSIGN(uZero, 0);
3781 IEM_MC_STORE_YREG_U32_ZX_VLMAX(0, uZero);
3782 IEM_MC_STORE_YREG_U32_ZX_VLMAX(1, uZero);
3783 IEM_MC_STORE_YREG_U32_ZX_VLMAX(2, uZero);
3784 IEM_MC_STORE_YREG_U32_ZX_VLMAX(3, uZero);
3785 IEM_MC_STORE_YREG_U32_ZX_VLMAX(4, uZero);
3786 IEM_MC_STORE_YREG_U32_ZX_VLMAX(5, uZero);
3787 IEM_MC_STORE_YREG_U32_ZX_VLMAX(6, uZero);
3788 IEM_MC_STORE_YREG_U32_ZX_VLMAX(7, uZero);
3789
3790 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
3791 {
3792 IEM_MC_STORE_YREG_U32_ZX_VLMAX( 8, uZero);
3793 IEM_MC_STORE_YREG_U32_ZX_VLMAX( 9, uZero);
3794 IEM_MC_STORE_YREG_U32_ZX_VLMAX(10, uZero);
3795 IEM_MC_STORE_YREG_U32_ZX_VLMAX(11, uZero);
3796 IEM_MC_STORE_YREG_U32_ZX_VLMAX(12, uZero);
3797 IEM_MC_STORE_YREG_U32_ZX_VLMAX(13, uZero);
3798 IEM_MC_STORE_YREG_U32_ZX_VLMAX(14, uZero);
3799 IEM_MC_STORE_YREG_U32_ZX_VLMAX(15, uZero);
3800 }
3801
3802 IEM_MC_ADVANCE_RIP_AND_FINISH();
3803 IEM_MC_END();
3804 }
3805}
3806
3807
3808/* Opcode VEX.66.0F 0x77 - invalid */
3809/* Opcode VEX.F3.0F 0x77 - invalid */
3810/* Opcode VEX.F2.0F 0x77 - invalid */
3811
3812/* Opcode VEX.0F 0x78 - invalid */
3813/* Opcode VEX.66.0F 0x78 - invalid */
3814/* Opcode VEX.F3.0F 0x78 - invalid */
3815/* Opcode VEX.F2.0F 0x78 - invalid */
3816
3817/* Opcode VEX.0F 0x79 - invalid */
3818/* Opcode VEX.66.0F 0x79 - invalid */
3819/* Opcode VEX.F3.0F 0x79 - invalid */
3820/* Opcode VEX.F2.0F 0x79 - invalid */
3821
3822/* Opcode VEX.0F 0x7a - invalid */
3823/* Opcode VEX.66.0F 0x7a - invalid */
3824/* Opcode VEX.F3.0F 0x7a - invalid */
3825/* Opcode VEX.F2.0F 0x7a - invalid */
3826
3827/* Opcode VEX.0F 0x7b - invalid */
3828/* Opcode VEX.66.0F 0x7b - invalid */
3829/* Opcode VEX.F3.0F 0x7b - invalid */
3830/* Opcode VEX.F2.0F 0x7b - invalid */
3831
3832/* Opcode VEX.0F 0x7c - invalid */
3833/** Opcode VEX.66.0F 0x7c - vhaddpd Vpd, Hpd, Wpd */
3834FNIEMOP_STUB(iemOp_vhaddpd_Vpd_Hpd_Wpd);
3835/* Opcode VEX.F3.0F 0x7c - invalid */
3836/** Opcode VEX.F2.0F 0x7c - vhaddps Vps, Hps, Wps */
3837FNIEMOP_STUB(iemOp_vhaddps_Vps_Hps_Wps);
3838
3839/* Opcode VEX.0F 0x7d - invalid */
3840/** Opcode VEX.66.0F 0x7d - vhsubpd Vpd, Hpd, Wpd */
3841FNIEMOP_STUB(iemOp_vhsubpd_Vpd_Hpd_Wpd);
3842/* Opcode VEX.F3.0F 0x7d - invalid */
3843/** Opcode VEX.F2.0F 0x7d - vhsubps Vps, Hps, Wps */
3844FNIEMOP_STUB(iemOp_vhsubps_Vps_Hps_Wps);
3845
3846
3847/* Opcode VEX.0F 0x7e - invalid */
3848
3849FNIEMOP_DEF(iemOp_vmovd_q_Ey_Vy)
3850{
3851 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3852 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3853 {
3854 /**
3855 * @opcode 0x7e
3856 * @opcodesub rex.w=1
3857 * @oppfx 0x66
3858 * @opcpuid avx
3859 * @opgroup og_avx_simdint_datamov
3860 * @opxcpttype 5
3861 * @optest 64-bit / op1=1 op2=2 -> op1=2
3862 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
3863 */
3864 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Eq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3865 if (IEM_IS_MODRM_REG_MODE(bRm))
3866 {
3867 /* greg64, XMM */
3868 IEM_MC_BEGIN(0, 1, IEM_MC_F_64BIT, 0);
3869 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3870 IEM_MC_LOCAL(uint64_t, u64Tmp);
3871
3872 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3873 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3874
3875 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3876 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Tmp);
3877
3878 IEM_MC_ADVANCE_RIP_AND_FINISH();
3879 IEM_MC_END();
3880 }
3881 else
3882 {
3883 /* [mem64], XMM */
3884 IEM_MC_BEGIN(0, 2, IEM_MC_F_64BIT, 0);
3885 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3886 IEM_MC_LOCAL(uint64_t, u64Tmp);
3887
3888 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3889 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3890 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3891 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3892
3893 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3894 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
3895
3896 IEM_MC_ADVANCE_RIP_AND_FINISH();
3897 IEM_MC_END();
3898 }
3899 }
3900 else
3901 {
3902 /**
3903 * @opdone
3904 * @opcode 0x7e
3905 * @opcodesub rex.w=0
3906 * @oppfx 0x66
3907 * @opcpuid avx
3908 * @opgroup og_avx_simdint_datamov
3909 * @opxcpttype 5
3910 * @opfunction iemOp_vmovd_q_Vy_Ey
3911 * @optest op1=1 op2=2 -> op1=2
3912 * @optest op1=0 op2=-42 -> op1=-42
3913 */
3914 IEMOP_MNEMONIC2(VEX_MR, VMOVD, vmovd, Ed_WO, Vd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3915 if (IEM_IS_MODRM_REG_MODE(bRm))
3916 {
3917 /* greg32, XMM */
3918 IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
3919 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3920 IEM_MC_LOCAL(uint32_t, u32Tmp);
3921
3922 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3923 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3924
3925 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3926 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Tmp);
3927
3928 IEM_MC_ADVANCE_RIP_AND_FINISH();
3929 IEM_MC_END();
3930 }
3931 else
3932 {
3933 /* [mem32], XMM */
3934 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
3935 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3936 IEM_MC_LOCAL(uint32_t, u32Tmp);
3937
3938 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3939 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3940 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3941 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
3942
3943 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
3944 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
3945
3946 IEM_MC_ADVANCE_RIP_AND_FINISH();
3947 IEM_MC_END();
3948 }
3949 }
3950}
3951
3952
3953/**
3954 * @opcode 0x7e
3955 * @oppfx 0xf3
3956 * @opcpuid avx
3957 * @opgroup og_avx_pcksclr_datamove
3958 * @opxcpttype none
3959 * @optest op1=1 op2=2 -> op1=2
3960 * @optest op1=0 op2=-42 -> op1=-42
3961 */
3962FNIEMOP_DEF(iemOp_vmovq_Vq_Wq)
3963{
3964 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
3965 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3966 if (IEM_IS_MODRM_REG_MODE(bRm))
3967 {
3968 /*
3969 * Register, register.
3970 */
3971 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
3972 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3973
3974 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3975 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3976
3977 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3978 IEM_GET_MODRM_RM(pVCpu, bRm));
3979 IEM_MC_ADVANCE_RIP_AND_FINISH();
3980 IEM_MC_END();
3981 }
3982 else
3983 {
3984 /*
3985 * Memory, register.
3986 */
3987 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
3988 IEM_MC_LOCAL(uint64_t, uSrc);
3989 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3990
3991 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3992 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3993 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3994 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3995
3996 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3997 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
3998
3999 IEM_MC_ADVANCE_RIP_AND_FINISH();
4000 IEM_MC_END();
4001 }
4002
4003}
4004/* Opcode VEX.F2.0F 0x7e - invalid */
4005
4006
4007/* Opcode VEX.0F 0x7f - invalid */
4008
4009/**
4010 * @opcode 0x7f
4011 * @oppfx 0x66
4012 * @opcpuid avx
4013 * @opgroup og_avx_simdint_datamove
4014 * @opxcpttype 1
4015 * @optest op1=1 op2=2 -> op1=2
4016 * @optest op1=0 op2=-42 -> op1=-42
4017 */
4018FNIEMOP_DEF(iemOp_vmovdqa_Wx_Vx)
4019{
4020 IEMOP_MNEMONIC2(VEX_MR, VMOVDQA, vmovdqa, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4021 Assert(pVCpu->iem.s.uVexLength <= 1);
4022 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4023 if (IEM_IS_MODRM_REG_MODE(bRm))
4024 {
4025 /*
4026 * Register, register.
4027 */
4028 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
4029 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4030
4031 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4032 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4033 if (pVCpu->iem.s.uVexLength == 0)
4034 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4035 IEM_GET_MODRM_REG(pVCpu, bRm));
4036 else
4037 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4038 IEM_GET_MODRM_REG(pVCpu, bRm));
4039 IEM_MC_ADVANCE_RIP_AND_FINISH();
4040 IEM_MC_END();
4041 }
4042 else if (pVCpu->iem.s.uVexLength == 0)
4043 {
4044 /*
4045 * Register, memory128.
4046 */
4047 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
4048 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4049 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4050
4051 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4052 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4053 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4054 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4055
4056 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4057 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
4058
4059 IEM_MC_ADVANCE_RIP_AND_FINISH();
4060 IEM_MC_END();
4061 }
4062 else
4063 {
4064 /*
4065 * Register, memory256.
4066 */
4067 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
4068 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
4069 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4070
4071 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4072 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4073 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4074 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4075
4076 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4077 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
4078
4079 IEM_MC_ADVANCE_RIP_AND_FINISH();
4080 IEM_MC_END();
4081 }
4082}
4083
4084
4085/**
4086 * @opcode 0x7f
4087 * @oppfx 0xf3
4088 * @opcpuid avx
4089 * @opgroup og_avx_simdint_datamove
4090 * @opxcpttype 4UA
4091 * @optest op1=1 op2=2 -> op1=2
4092 * @optest op1=0 op2=-42 -> op1=-42
4093 */
4094FNIEMOP_DEF(iemOp_vmovdqu_Wx_Vx)
4095{
4096 IEMOP_MNEMONIC2(VEX_MR, VMOVDQU, vmovdqu, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4097 Assert(pVCpu->iem.s.uVexLength <= 1);
4098 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4099 if (IEM_IS_MODRM_REG_MODE(bRm))
4100 {
4101 /*
4102 * Register, register.
4103 */
4104 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
4105 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4106
4107 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4108 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4109 if (pVCpu->iem.s.uVexLength == 0)
4110 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4111 IEM_GET_MODRM_REG(pVCpu, bRm));
4112 else
4113 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4114 IEM_GET_MODRM_REG(pVCpu, bRm));
4115 IEM_MC_ADVANCE_RIP_AND_FINISH();
4116 IEM_MC_END();
4117 }
4118 else if (pVCpu->iem.s.uVexLength == 0)
4119 {
4120 /*
4121 * Register, memory128.
4122 */
4123 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
4124 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4125 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4126
4127 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4128 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4129 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4130 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4131
4132 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4133 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
4134
4135 IEM_MC_ADVANCE_RIP_AND_FINISH();
4136 IEM_MC_END();
4137 }
4138 else
4139 {
4140 /*
4141 * Register, memory256.
4142 */
4143 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
4144 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
4145 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4146
4147 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4148 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4149 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4150 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4151
4152 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4153 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
4154
4155 IEM_MC_ADVANCE_RIP_AND_FINISH();
4156 IEM_MC_END();
4157 }
4158}
4159
4160/* Opcode VEX.F2.0F 0x7f - invalid */
4161
4162
4163/* Opcode VEX.0F 0x80 - invalid */
4164/* Opcode VEX.0F 0x81 - invalid */
4165/* Opcode VEX.0F 0x82 - invalid */
4166/* Opcode VEX.0F 0x83 - invalid */
4167/* Opcode VEX.0F 0x84 - invalid */
4168/* Opcode VEX.0F 0x85 - invalid */
4169/* Opcode VEX.0F 0x86 - invalid */
4170/* Opcode VEX.0F 0x87 - invalid */
4171/* Opcode VEX.0F 0x88 - invalid */
4172/* Opcode VEX.0F 0x89 - invalid */
4173/* Opcode VEX.0F 0x8a - invalid */
4174/* Opcode VEX.0F 0x8b - invalid */
4175/* Opcode VEX.0F 0x8c - invalid */
4176/* Opcode VEX.0F 0x8d - invalid */
4177/* Opcode VEX.0F 0x8e - invalid */
4178/* Opcode VEX.0F 0x8f - invalid */
4179/* Opcode VEX.0F 0x90 - invalid */
4180/* Opcode VEX.0F 0x91 - invalid */
4181/* Opcode VEX.0F 0x92 - invalid */
4182/* Opcode VEX.0F 0x93 - invalid */
4183/* Opcode VEX.0F 0x94 - invalid */
4184/* Opcode VEX.0F 0x95 - invalid */
4185/* Opcode VEX.0F 0x96 - invalid */
4186/* Opcode VEX.0F 0x97 - invalid */
4187/* Opcode VEX.0F 0x98 - invalid */
4188/* Opcode VEX.0F 0x99 - invalid */
4189/* Opcode VEX.0F 0x9a - invalid */
4190/* Opcode VEX.0F 0x9b - invalid */
4191/* Opcode VEX.0F 0x9c - invalid */
4192/* Opcode VEX.0F 0x9d - invalid */
4193/* Opcode VEX.0F 0x9e - invalid */
4194/* Opcode VEX.0F 0x9f - invalid */
4195/* Opcode VEX.0F 0xa0 - invalid */
4196/* Opcode VEX.0F 0xa1 - invalid */
4197/* Opcode VEX.0F 0xa2 - invalid */
4198/* Opcode VEX.0F 0xa3 - invalid */
4199/* Opcode VEX.0F 0xa4 - invalid */
4200/* Opcode VEX.0F 0xa5 - invalid */
4201/* Opcode VEX.0F 0xa6 - invalid */
4202/* Opcode VEX.0F 0xa7 - invalid */
4203/* Opcode VEX.0F 0xa8 - invalid */
4204/* Opcode VEX.0F 0xa9 - invalid */
4205/* Opcode VEX.0F 0xaa - invalid */
4206/* Opcode VEX.0F 0xab - invalid */
4207/* Opcode VEX.0F 0xac - invalid */
4208/* Opcode VEX.0F 0xad - invalid */
4209
4210
4211/* Opcode VEX.0F 0xae mem/0 - invalid. */
4212/* Opcode VEX.0F 0xae mem/1 - invalid. */
4213
4214/**
4215 * @ opmaps grp15
4216 * @ opcode !11/2
4217 * @ oppfx none
4218 * @ opcpuid sse
4219 * @ opgroup og_sse_mxcsrsm
4220 * @ opxcpttype 5
4221 * @ optest op1=0 -> mxcsr=0
4222 * @ optest op1=0x2083 -> mxcsr=0x2083
4223 * @ optest op1=0xfffffffe -> value.xcpt=0xd
4224 * @ optest op1=0x2083 cr0|=ts -> value.xcpt=0x7
4225 * @ optest op1=0x2083 cr0|=em -> value.xcpt=0x6
4226 * @ optest op1=0x2083 cr0|=mp -> mxcsr=0x2083
4227 * @ optest op1=0x2083 cr4&~=osfxsr -> value.xcpt=0x6
4228 * @ optest op1=0x2083 cr0|=ts,em -> value.xcpt=0x6
4229 * @ optest op1=0x2083 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
4230 * @ optest op1=0x2083 cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
4231 * @ optest op1=0x2083 cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
4232 */
4233FNIEMOP_STUB_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm);
4234//FNIEMOP_DEF_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm)
4235//{
4236// IEMOP_MNEMONIC1(M_MEM, VLDMXCSR, vldmxcsr, MdRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
4237// IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
4238// IEM_MC_ARG(uint8_t, iEffSeg, 0);
4239// IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
4240// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
4241// IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4242// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4243// IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
4244// IEM_MC_CALL_CIMPL_2(iemCImpl_ldmxcsr, iEffSeg, GCPtrEff);
4245// IEM_MC_END();
4246// return VINF_SUCCESS;
4247//}
4248
4249
4250/**
4251 * @opmaps vexgrp15
4252 * @opcode !11/3
4253 * @oppfx none
4254 * @opcpuid avx
4255 * @opgroup og_avx_mxcsrsm
4256 * @opxcpttype 5
4257 * @optest mxcsr=0 -> op1=0
4258 * @optest mxcsr=0x2083 -> op1=0x2083
4259 * @optest mxcsr=0x2084 cr0|=ts -> value.xcpt=0x7
4260 * @optest !amd / mxcsr=0x2085 cr0|=em -> op1=0x2085
4261 * @optest amd / mxcsr=0x2085 cr0|=em -> value.xcpt=0x6
4262 * @optest mxcsr=0x2086 cr0|=mp -> op1=0x2086
4263 * @optest mxcsr=0x2087 cr4&~=osfxsr -> op1=0x2087
4264 * @optest mxcsr=0x208f cr4&~=osxsave -> value.xcpt=0x6
4265 * @optest mxcsr=0x2087 cr4&~=osfxsr,osxsave -> value.xcpt=0x6
4266 * @optest !amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x7
4267 * @optest amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x6
4268 * @optest !amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> op1=0x2089
4269 * @optest amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
4270 * @optest !amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x7
4271 * @optest amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
4272 * @optest !amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x7
4273 * @optest amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
4274 * @optest !amd / mxcsr=0x208c xcr0&~=all_avx -> value.xcpt=0x6
4275 * @optest amd / mxcsr=0x208c xcr0&~=all_avx -> op1=0x208c
4276 * @optest !amd / mxcsr=0x208d xcr0&~=all_avx_sse -> value.xcpt=0x6
4277 * @optest amd / mxcsr=0x208d xcr0&~=all_avx_sse -> op1=0x208d
4278 * @optest !amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x6
4279 * @optest amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x7
4280 * @optest mxcsr=0x2082 cr0|=ts cr4&~=osxsave -> value.xcpt=0x6
4281 * @optest mxcsr=0x2081 xcr0&~=all_avx cr0|=ts cr4&~=osxsave
4282 * -> value.xcpt=0x6
4283 * @remarks AMD Jaguar CPU (f0x16,m0,s1) \#UD when CR0.EM is set. It also
4284 * doesn't seem to check XCR0[2:1] != 11b. This does not match the
4285 * APMv4 rev 3.17 page 509.
4286 * @todo Test this instruction on AMD Ryzen.
4287 */
4288FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr, uint8_t, bRm)
4289{
4290 IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
4291 IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
4292 IEM_MC_ARG(uint8_t, iEffSeg, 0);
4293 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
4294 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
4295 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4296 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4297 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
4298 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_FPU, iemCImpl_vstmxcsr, iEffSeg, GCPtrEff);
4299 IEM_MC_END();
4300}
4301
4302/* Opcode VEX.0F 0xae mem/4 - invalid. */
4303/* Opcode VEX.0F 0xae mem/5 - invalid. */
4304/* Opcode VEX.0F 0xae mem/6 - invalid. */
4305/* Opcode VEX.0F 0xae mem/7 - invalid. */
4306
4307/* Opcode VEX.0F 0xae 11b/0 - invalid. */
4308/* Opcode VEX.0F 0xae 11b/1 - invalid. */
4309/* Opcode VEX.0F 0xae 11b/2 - invalid. */
4310/* Opcode VEX.0F 0xae 11b/3 - invalid. */
4311/* Opcode VEX.0F 0xae 11b/4 - invalid. */
4312/* Opcode VEX.0F 0xae 11b/5 - invalid. */
4313/* Opcode VEX.0F 0xae 11b/6 - invalid. */
4314/* Opcode VEX.0F 0xae 11b/7 - invalid. */
4315
4316/**
4317 * Vex group 15 jump table for memory variant.
4318 */
4319IEM_STATIC const PFNIEMOPRM g_apfnVexGroup15MemReg[] =
4320{ /* pfx: none, 066h, 0f3h, 0f2h */
4321 /* /0 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4322 /* /1 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4323 /* /2 */ iemOp_VGrp15_vldmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4324 /* /3 */ iemOp_VGrp15_vstmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4325 /* /4 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4326 /* /5 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4327 /* /6 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4328 /* /7 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4329};
4330AssertCompile(RT_ELEMENTS(g_apfnVexGroup15MemReg) == 8*4);
4331
4332
4333/** Opcode vex. 0xae. */
4334FNIEMOP_DEF(iemOp_VGrp15)
4335{
4336 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4337 if (IEM_IS_MODRM_REG_MODE(bRm))
4338 /* register, register */
4339 return FNIEMOP_CALL_1(iemOp_InvalidWithRM, bRm);
4340
4341 /* memory, register */
4342 return FNIEMOP_CALL_1(g_apfnVexGroup15MemReg[ IEM_GET_MODRM_REG_8(bRm) * 4
4343 + pVCpu->iem.s.idxPrefix], bRm);
4344}
4345
4346
4347/* Opcode VEX.0F 0xaf - invalid. */
4348
4349/* Opcode VEX.0F 0xb0 - invalid. */
4350/* Opcode VEX.0F 0xb1 - invalid. */
4351/* Opcode VEX.0F 0xb2 - invalid. */
4352/* Opcode VEX.0F 0xb2 - invalid. */
4353/* Opcode VEX.0F 0xb3 - invalid. */
4354/* Opcode VEX.0F 0xb4 - invalid. */
4355/* Opcode VEX.0F 0xb5 - invalid. */
4356/* Opcode VEX.0F 0xb6 - invalid. */
4357/* Opcode VEX.0F 0xb7 - invalid. */
4358/* Opcode VEX.0F 0xb8 - invalid. */
4359/* Opcode VEX.0F 0xb9 - invalid. */
4360/* Opcode VEX.0F 0xba - invalid. */
4361/* Opcode VEX.0F 0xbb - invalid. */
4362/* Opcode VEX.0F 0xbc - invalid. */
4363/* Opcode VEX.0F 0xbd - invalid. */
4364/* Opcode VEX.0F 0xbe - invalid. */
4365/* Opcode VEX.0F 0xbf - invalid. */
4366
4367/* Opcode VEX.0F 0xc0 - invalid. */
4368/* Opcode VEX.66.0F 0xc0 - invalid. */
4369/* Opcode VEX.F3.0F 0xc0 - invalid. */
4370/* Opcode VEX.F2.0F 0xc0 - invalid. */
4371
4372/* Opcode VEX.0F 0xc1 - invalid. */
4373/* Opcode VEX.66.0F 0xc1 - invalid. */
4374/* Opcode VEX.F3.0F 0xc1 - invalid. */
4375/* Opcode VEX.F2.0F 0xc1 - invalid. */
4376
4377/** Opcode VEX.0F 0xc2 - vcmpps Vps,Hps,Wps,Ib */
4378FNIEMOP_STUB(iemOp_vcmpps_Vps_Hps_Wps_Ib);
4379/** Opcode VEX.66.0F 0xc2 - vcmppd Vpd,Hpd,Wpd,Ib */
4380FNIEMOP_STUB(iemOp_vcmppd_Vpd_Hpd_Wpd_Ib);
4381/** Opcode VEX.F3.0F 0xc2 - vcmpss Vss,Hss,Wss,Ib */
4382FNIEMOP_STUB(iemOp_vcmpss_Vss_Hss_Wss_Ib);
4383/** Opcode VEX.F2.0F 0xc2 - vcmpsd Vsd,Hsd,Wsd,Ib */
4384FNIEMOP_STUB(iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib);
4385
4386/* Opcode VEX.0F 0xc3 - invalid */
4387/* Opcode VEX.66.0F 0xc3 - invalid */
4388/* Opcode VEX.F3.0F 0xc3 - invalid */
4389/* Opcode VEX.F2.0F 0xc3 - invalid */
4390
4391/* Opcode VEX.0F 0xc4 - invalid */
4392
4393
4394/** Opcode VEX.66.0F 0xc4 - vpinsrw Vdq,Hdq,Ry/Mw,Ib */
4395FNIEMOP_DEF(iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib)
4396{
4397 /*IEMOP_MNEMONIC4(VEX_RMV, VPINSRW, vpinsrw, Vdq, Vdq, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);*/ /** @todo */
4398 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4399 if (IEM_IS_MODRM_REG_MODE(bRm))
4400 {
4401 /*
4402 * Register, register.
4403 */
4404 IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
4405 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4406 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4407 IEM_MC_ARG(PRTUINT128U, puDst, 0);
4408 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
4409 IEM_MC_ARG(uint16_t, u16Src, 2);
4410 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
4411 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4412 IEM_MC_PREPARE_AVX_USAGE();
4413 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4414 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4415 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, bRm));
4416 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vpinsrw_u128, iemAImpl_vpinsrw_u128_fallback),
4417 puDst, puSrc, u16Src, bImmArg);
4418 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
4419 IEM_MC_ADVANCE_RIP_AND_FINISH();
4420 IEM_MC_END();
4421 }
4422 else
4423 {
4424 /*
4425 * Register, memory.
4426 */
4427 IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
4428 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4429 IEM_MC_ARG(PRTUINT128U, puDst, 0);
4430 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
4431 IEM_MC_ARG(uint16_t, u16Src, 2);
4432
4433 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4434 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4435 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
4436 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4437 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4438 IEM_MC_PREPARE_AVX_USAGE();
4439
4440 IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4441 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4442 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4443 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vpinsrw_u128, iemAImpl_vpinsrw_u128_fallback),
4444 puDst, puSrc, u16Src, bImmArg);
4445 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
4446
4447 IEM_MC_ADVANCE_RIP_AND_FINISH();
4448 IEM_MC_END();
4449 }
4450}
4451
4452
4453/* Opcode VEX.F3.0F 0xc4 - invalid */
4454/* Opcode VEX.F2.0F 0xc4 - invalid */
4455
4456/* Opcode VEX.0F 0xc5 - invlid */
4457
4458
4459/** Opcode VEX.66.0F 0xc5 - vpextrw Gd, Udq, Ib */
4460FNIEMOP_DEF(iemOp_vpextrw_Gd_Udq_Ib)
4461{
4462 IEMOP_MNEMONIC3(VEX_RMI_REG, VPEXTRW, vpextrw, Gd, Ux, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
4463 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4464 if (IEM_IS_MODRM_REG_MODE(bRm))
4465 {
4466 /*
4467 * Register, register.
4468 */
4469 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4470 IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
4471 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4472 IEM_MC_LOCAL(uint16_t, u16Dst);
4473 IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Dst, u16Dst, 0);
4474 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
4475 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
4476 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4477 IEM_MC_PREPARE_AVX_USAGE();
4478 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4479 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vpextrw_u128, iemAImpl_vpextrw_u128_fallback),
4480 pu16Dst, puSrc, bImmArg);
4481 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst);
4482 IEM_MC_ADVANCE_RIP_AND_FINISH();
4483 IEM_MC_END();
4484 }
4485 /* No memory operand. */
4486 else
4487 IEMOP_RAISE_INVALID_OPCODE_RET();
4488}
4489
4490
4491/* Opcode VEX.F3.0F 0xc5 - invalid */
4492/* Opcode VEX.F2.0F 0xc5 - invalid */
4493
4494
4495#define VSHUFP_X(a_Instr) \
4496 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
4497 if (IEM_IS_MODRM_REG_MODE(bRm)) \
4498 { \
4499 /* \
4500 * Register, register. \
4501 */ \
4502 if (pVCpu->iem.s.uVexLength) \
4503 { \
4504 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4505 IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0); \
4506 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
4507 IEM_MC_LOCAL(RTUINT256U, uDst); \
4508 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
4509 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
4510 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
4511 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
4512 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
4513 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4514 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
4515 IEM_MC_PREPARE_AVX_USAGE(); \
4516 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4517 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
4518 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
4519 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4520 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
4521 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4522 IEM_MC_END(); \
4523 } \
4524 else \
4525 { \
4526 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4527 IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
4528 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
4529 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
4530 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
4531 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2); \
4532 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4533 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
4534 IEM_MC_PREPARE_AVX_USAGE(); \
4535 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
4536 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4537 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
4538 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
4539 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4540 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
4541 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4542 IEM_MC_END(); \
4543 } \
4544 } \
4545 else \
4546 { \
4547 /* \
4548 * Register, memory. \
4549 */ \
4550 if (pVCpu->iem.s.uVexLength) \
4551 { \
4552 IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0); \
4553 IEM_MC_LOCAL(RTUINT256U, uDst); \
4554 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
4555 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
4556 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
4557 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
4558 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
4559 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
4560 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
4561 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4562 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4563 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
4564 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
4565 IEM_MC_PREPARE_AVX_USAGE(); \
4566 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
4567 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4568 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
4569 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4570 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
4571 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4572 IEM_MC_END(); \
4573 } \
4574 else \
4575 { \
4576 IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0); \
4577 IEM_MC_LOCAL(RTUINT128U, uSrc2); \
4578 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
4579 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
4580 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
4581 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2); \
4582 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
4583 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4584 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4585 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
4586 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
4587 IEM_MC_PREPARE_AVX_USAGE(); \
4588 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
4589 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
4590 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4591 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
4592 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4593 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
4594 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4595 IEM_MC_END(); \
4596 } \
4597 } \
4598 (void)0
4599
4600/** Opcode VEX.0F 0xc6 - vshufps Vps,Hps,Wps,Ib */
4601FNIEMOP_DEF(iemOp_vshufps_Vps_Hps_Wps_Ib)
4602{
4603 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPS, vshufps, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
4604 VSHUFP_X(vshufps);
4605}
4606
4607
4608/** Opcode VEX.66.0F 0xc6 - vshufpd Vpd,Hpd,Wpd,Ib */
4609FNIEMOP_DEF(iemOp_vshufpd_Vpd_Hpd_Wpd_Ib)
4610{
4611 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPD, vshufpd, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
4612 VSHUFP_X(vshufpd);
4613}
4614#undef VSHUFP_X
4615
4616
4617/* Opcode VEX.F3.0F 0xc6 - invalid */
4618/* Opcode VEX.F2.0F 0xc6 - invalid */
4619
4620/* Opcode VEX.0F 0xc7 - invalid */
4621/* Opcode VEX.66.0F 0xc7 - invalid */
4622/* Opcode VEX.F3.0F 0xc7 - invalid */
4623/* Opcode VEX.F2.0F 0xc7 - invalid */
4624
4625/* Opcode VEX.0F 0xc8 - invalid */
4626/* Opcode VEX.0F 0xc9 - invalid */
4627/* Opcode VEX.0F 0xca - invalid */
4628/* Opcode VEX.0F 0xcb - invalid */
4629/* Opcode VEX.0F 0xcc - invalid */
4630/* Opcode VEX.0F 0xcd - invalid */
4631/* Opcode VEX.0F 0xce - invalid */
4632/* Opcode VEX.0F 0xcf - invalid */
4633
4634
4635/* Opcode VEX.0F 0xd0 - invalid */
4636/** Opcode VEX.66.0F 0xd0 - vaddsubpd Vpd, Hpd, Wpd */
4637FNIEMOP_STUB(iemOp_vaddsubpd_Vpd_Hpd_Wpd);
4638/* Opcode VEX.F3.0F 0xd0 - invalid */
4639/** Opcode VEX.F2.0F 0xd0 - vaddsubps Vps, Hps, Wps */
4640FNIEMOP_STUB(iemOp_vaddsubps_Vps_Hps_Wps);
4641
4642/* Opcode VEX.0F 0xd1 - invalid */
4643/** Opcode VEX.66.0F 0xd1 - vpsrlw Vx, Hx, W */
4644FNIEMOP_STUB(iemOp_vpsrlw_Vx_Hx_W);
4645/* Opcode VEX.F3.0F 0xd1 - invalid */
4646/* Opcode VEX.F2.0F 0xd1 - invalid */
4647
4648/* Opcode VEX.0F 0xd2 - invalid */
4649/** Opcode VEX.66.0F 0xd2 - vpsrld Vx, Hx, Wx */
4650FNIEMOP_STUB(iemOp_vpsrld_Vx_Hx_Wx);
4651/* Opcode VEX.F3.0F 0xd2 - invalid */
4652/* Opcode VEX.F2.0F 0xd2 - invalid */
4653
4654/* Opcode VEX.0F 0xd3 - invalid */
4655/** Opcode VEX.66.0F 0xd3 - vpsrlq Vx, Hx, Wx */
4656FNIEMOP_STUB(iemOp_vpsrlq_Vx_Hx_Wx);
4657/* Opcode VEX.F3.0F 0xd3 - invalid */
4658/* Opcode VEX.F2.0F 0xd3 - invalid */
4659
4660/* Opcode VEX.0F 0xd4 - invalid */
4661
4662
4663/** Opcode VEX.66.0F 0xd4 - vpaddq Vx, Hx, W */
4664FNIEMOP_DEF(iemOp_vpaddq_Vx_Hx_Wx)
4665{
4666 IEMOP_MNEMONIC3(VEX_RVM, VPADDQ, vpaddq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4667 IEMOPMEDIAF3_INIT_VARS( vpaddq);
4668 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4669}
4670
4671
4672/* Opcode VEX.F3.0F 0xd4 - invalid */
4673/* Opcode VEX.F2.0F 0xd4 - invalid */
4674
4675/* Opcode VEX.0F 0xd5 - invalid */
4676
4677
4678/** Opcode VEX.66.0F 0xd5 - vpmullw Vx, Hx, Wx */
4679FNIEMOP_DEF(iemOp_vpmullw_Vx_Hx_Wx)
4680{
4681 IEMOP_MNEMONIC3(VEX_RVM, VPMULLW, vpmullw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4682 IEMOPMEDIAOPTF3_INIT_VARS(vpmullw);
4683 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4684}
4685
4686
4687/* Opcode VEX.F3.0F 0xd5 - invalid */
4688/* Opcode VEX.F2.0F 0xd5 - invalid */
4689
4690/* Opcode VEX.0F 0xd6 - invalid */
4691
4692/**
4693 * @opcode 0xd6
4694 * @oppfx 0x66
4695 * @opcpuid avx
4696 * @opgroup og_avx_pcksclr_datamove
4697 * @opxcpttype none
4698 * @optest op1=-1 op2=2 -> op1=2
4699 * @optest op1=0 op2=-42 -> op1=-42
4700 */
4701FNIEMOP_DEF(iemOp_vmovq_Wq_Vq)
4702{
4703 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Wq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
4704 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4705 if (IEM_IS_MODRM_REG_MODE(bRm))
4706 {
4707 /*
4708 * Register, register.
4709 */
4710 IEM_MC_BEGIN(0, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
4711 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4712
4713 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4714 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4715
4716 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4717 IEM_GET_MODRM_REG(pVCpu, bRm));
4718 IEM_MC_ADVANCE_RIP_AND_FINISH();
4719 IEM_MC_END();
4720 }
4721 else
4722 {
4723 /*
4724 * Memory, register.
4725 */
4726 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
4727 IEM_MC_LOCAL(uint64_t, uSrc);
4728 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4729
4730 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4731 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4732 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4733 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4734
4735 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
4736 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
4737
4738 IEM_MC_ADVANCE_RIP_AND_FINISH();
4739 IEM_MC_END();
4740 }
4741}
4742
4743/* Opcode VEX.F3.0F 0xd6 - invalid */
4744/* Opcode VEX.F2.0F 0xd6 - invalid */
4745
4746
4747/* Opcode VEX.0F 0xd7 - invalid */
4748
4749/** Opcode VEX.66.0F 0xd7 - */
4750FNIEMOP_DEF(iemOp_vpmovmskb_Gd_Ux)
4751{
4752 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4753 /* Docs says register only. */
4754 if (IEM_IS_MODRM_REG_MODE(bRm)) /** @todo test that this is registers only. */
4755 {
4756 /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
4757 IEMOP_MNEMONIC2(VEX_RM_REG, VPMOVMSKB, vpmovmskb, Gd, Ux, DISOPTYPE_X86_SSE | DISOPTYPE_HARMLESS, 0);
4758 if (pVCpu->iem.s.uVexLength)
4759 {
4760 IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
4761 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
4762 IEM_MC_ARG(uint64_t *, puDst, 0);
4763 IEM_MC_LOCAL(RTUINT256U, uSrc);
4764 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
4765 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4766 IEM_MC_PREPARE_AVX_USAGE();
4767 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4768 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4769 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpmovmskb_u256,
4770 iemAImpl_vpmovmskb_u256_fallback), puDst, puSrc);
4771 IEM_MC_ADVANCE_RIP_AND_FINISH();
4772 IEM_MC_END();
4773 }
4774 else
4775 {
4776 IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
4777 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4778 IEM_MC_ARG(uint64_t *, puDst, 0);
4779 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
4780 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4781 IEM_MC_PREPARE_AVX_USAGE();
4782 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
4783 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
4784 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_pmovmskb_u128, puDst, puSrc);
4785 IEM_MC_ADVANCE_RIP_AND_FINISH();
4786 IEM_MC_END();
4787 }
4788 }
4789 else
4790 IEMOP_RAISE_INVALID_OPCODE_RET();
4791}
4792
4793
4794/* Opcode VEX.F3.0F 0xd7 - invalid */
4795/* Opcode VEX.F2.0F 0xd7 - invalid */
4796
4797
4798/* Opcode VEX.0F 0xd8 - invalid */
4799
4800/** Opcode VEX.66.0F 0xd8 - vpsubusb Vx, Hx, Wx */
4801FNIEMOP_DEF(iemOp_vpsubusb_Vx_Hx_Wx)
4802{
4803 IEMOP_MNEMONIC3(VEX_RVM, VPSUBUSB, vpsubusb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4804 IEMOPMEDIAOPTF3_INIT_VARS(vpsubusb);
4805 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4806}
4807
4808
4809/* Opcode VEX.F3.0F 0xd8 - invalid */
4810/* Opcode VEX.F2.0F 0xd8 - invalid */
4811
4812/* Opcode VEX.0F 0xd9 - invalid */
4813
4814
4815/** Opcode VEX.66.0F 0xd9 - vpsubusw Vx, Hx, Wx */
4816FNIEMOP_DEF(iemOp_vpsubusw_Vx_Hx_Wx)
4817{
4818 IEMOP_MNEMONIC3(VEX_RVM, VPSUBUSW, vpsubusw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4819 IEMOPMEDIAOPTF3_INIT_VARS(vpsubusw);
4820 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4821}
4822
4823
4824/* Opcode VEX.F3.0F 0xd9 - invalid */
4825/* Opcode VEX.F2.0F 0xd9 - invalid */
4826
4827/* Opcode VEX.0F 0xda - invalid */
4828
4829
4830/** Opcode VEX.66.0F 0xda - vpminub Vx, Hx, Wx */
4831FNIEMOP_DEF(iemOp_vpminub_Vx_Hx_Wx)
4832{
4833 IEMOP_MNEMONIC3(VEX_RVM, VPMINUB, vpminub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4834 IEMOPMEDIAF3_INIT_VARS(vpminub);
4835 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4836}
4837
4838
4839/* Opcode VEX.F3.0F 0xda - invalid */
4840/* Opcode VEX.F2.0F 0xda - invalid */
4841
4842/* Opcode VEX.0F 0xdb - invalid */
4843
4844
4845/** Opcode VEX.66.0F 0xdb - vpand Vx, Hx, Wx */
4846FNIEMOP_DEF(iemOp_vpand_Vx_Hx_Wx)
4847{
4848 IEMOP_MNEMONIC3(VEX_RVM, VPAND, vpand, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4849 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
4850 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
4851}
4852
4853
4854/* Opcode VEX.F3.0F 0xdb - invalid */
4855/* Opcode VEX.F2.0F 0xdb - invalid */
4856
4857/* Opcode VEX.0F 0xdc - invalid */
4858
4859
4860/** Opcode VEX.66.0F 0xdc - vpaddusb Vx, Hx, Wx */
4861FNIEMOP_DEF(iemOp_vpaddusb_Vx_Hx_Wx)
4862{
4863 IEMOP_MNEMONIC3(VEX_RVM, VPADDUSB, vpaddusb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4864 IEMOPMEDIAOPTF3_INIT_VARS(vpaddusb);
4865 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4866}
4867
4868
4869/* Opcode VEX.F3.0F 0xdc - invalid */
4870/* Opcode VEX.F2.0F 0xdc - invalid */
4871
4872/* Opcode VEX.0F 0xdd - invalid */
4873
4874
4875/** Opcode VEX.66.0F 0xdd - vpaddusw Vx, Hx, Wx */
4876FNIEMOP_DEF(iemOp_vpaddusw_Vx_Hx_Wx)
4877{
4878 IEMOP_MNEMONIC3(VEX_RVM, VPADDUSW, vpaddusw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4879 IEMOPMEDIAOPTF3_INIT_VARS(vpaddusw);
4880 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4881}
4882
4883
4884/* Opcode VEX.F3.0F 0xdd - invalid */
4885/* Opcode VEX.F2.0F 0xdd - invalid */
4886
4887/* Opcode VEX.0F 0xde - invalid */
4888
4889
4890/** Opcode VEX.66.0F 0xde - vpmaxub Vx, Hx, Wx */
4891FNIEMOP_DEF(iemOp_vpmaxub_Vx_Hx_Wx)
4892{
4893 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUB, vpmaxub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4894 IEMOPMEDIAF3_INIT_VARS(vpmaxub);
4895 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4896}
4897
4898
4899/* Opcode VEX.F3.0F 0xde - invalid */
4900/* Opcode VEX.F2.0F 0xde - invalid */
4901
4902/* Opcode VEX.0F 0xdf - invalid */
4903
4904
4905/** Opcode VEX.66.0F 0xdf - vpandn Vx, Hx, Wx */
4906FNIEMOP_DEF(iemOp_vpandn_Vx_Hx_Wx)
4907{
4908 IEMOP_MNEMONIC3(VEX_RVM, VPANDN, vpandn, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4909 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
4910 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
4911}
4912
4913
4914/* Opcode VEX.F3.0F 0xdf - invalid */
4915/* Opcode VEX.F2.0F 0xdf - invalid */
4916
4917/* Opcode VEX.0F 0xe0 - invalid */
4918
4919
4920/** Opcode VEX.66.0F 0xe0 - vpavgb Vx, Hx, Wx */
4921FNIEMOP_DEF(iemOp_vpavgb_Vx_Hx_Wx)
4922{
4923 IEMOP_MNEMONIC3(VEX_RVM, VPAVGB, vpavgb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4924 IEMOPMEDIAOPTF3_INIT_VARS(vpavgb);
4925 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4926}
4927
4928
4929/* Opcode VEX.F3.0F 0xe0 - invalid */
4930/* Opcode VEX.F2.0F 0xe0 - invalid */
4931
4932/* Opcode VEX.0F 0xe1 - invalid */
4933/** Opcode VEX.66.0F 0xe1 - vpsraw Vx, Hx, W */
4934FNIEMOP_STUB(iemOp_vpsraw_Vx_Hx_W);
4935/* Opcode VEX.F3.0F 0xe1 - invalid */
4936/* Opcode VEX.F2.0F 0xe1 - invalid */
4937
4938/* Opcode VEX.0F 0xe2 - invalid */
4939/** Opcode VEX.66.0F 0xe2 - vpsrad Vx, Hx, Wx */
4940FNIEMOP_STUB(iemOp_vpsrad_Vx_Hx_Wx);
4941/* Opcode VEX.F3.0F 0xe2 - invalid */
4942/* Opcode VEX.F2.0F 0xe2 - invalid */
4943
4944/* Opcode VEX.0F 0xe3 - invalid */
4945
4946
4947/** Opcode VEX.66.0F 0xe3 - vpavgw Vx, Hx, Wx */
4948FNIEMOP_DEF(iemOp_vpavgw_Vx_Hx_Wx)
4949{
4950 IEMOP_MNEMONIC3(VEX_RVM, VPAVGW, vpavgw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4951 IEMOPMEDIAOPTF3_INIT_VARS(vpavgw);
4952 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4953}
4954
4955
4956/* Opcode VEX.F3.0F 0xe3 - invalid */
4957/* Opcode VEX.F2.0F 0xe3 - invalid */
4958
4959/* Opcode VEX.0F 0xe4 - invalid */
4960
4961
4962/** Opcode VEX.66.0F 0xe4 - vpmulhuw Vx, Hx, Wx */
4963FNIEMOP_DEF(iemOp_vpmulhuw_Vx_Hx_Wx)
4964{
4965 IEMOP_MNEMONIC3(VEX_RVM, VPMULHUW, vpmulhuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4966 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhuw);
4967 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4968}
4969
4970
4971/* Opcode VEX.F3.0F 0xe4 - invalid */
4972/* Opcode VEX.F2.0F 0xe4 - invalid */
4973
4974/* Opcode VEX.0F 0xe5 - invalid */
4975
4976
4977/** Opcode VEX.66.0F 0xe5 - vpmulhw Vx, Hx, Wx */
4978FNIEMOP_DEF(iemOp_vpmulhw_Vx_Hx_Wx)
4979{
4980 IEMOP_MNEMONIC3(VEX_RVM, VPMULHW, vpmulhw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4981 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhw);
4982 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4983}
4984
4985
4986/* Opcode VEX.F3.0F 0xe5 - invalid */
4987/* Opcode VEX.F2.0F 0xe5 - invalid */
4988
4989/* Opcode VEX.0F 0xe6 - invalid */
4990/** Opcode VEX.66.0F 0xe6 - vcvttpd2dq Vx, Wpd */
4991FNIEMOP_STUB(iemOp_vcvttpd2dq_Vx_Wpd);
4992/** Opcode VEX.F3.0F 0xe6 - vcvtdq2pd Vx, Wpd */
4993FNIEMOP_STUB(iemOp_vcvtdq2pd_Vx_Wpd);
4994/** Opcode VEX.F2.0F 0xe6 - vcvtpd2dq Vx, Wpd */
4995FNIEMOP_STUB(iemOp_vcvtpd2dq_Vx_Wpd);
4996
4997
4998/* Opcode VEX.0F 0xe7 - invalid */
4999
5000/**
5001 * @opcode 0xe7
5002 * @opcodesub !11 mr/reg
5003 * @oppfx 0x66
5004 * @opcpuid avx
5005 * @opgroup og_avx_cachect
5006 * @opxcpttype 1
5007 * @optest op1=-1 op2=2 -> op1=2
5008 * @optest op1=0 op2=-42 -> op1=-42
5009 */
5010FNIEMOP_DEF(iemOp_vmovntdq_Mx_Vx)
5011{
5012 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTDQ, vmovntdq, Mx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
5013 Assert(pVCpu->iem.s.uVexLength <= 1);
5014 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5015 if (IEM_IS_MODRM_MEM_MODE(bRm))
5016 {
5017 if (pVCpu->iem.s.uVexLength == 0)
5018 {
5019 /*
5020 * 128-bit: Memory, register.
5021 */
5022 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
5023 IEM_MC_LOCAL(RTUINT128U, uSrc);
5024 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5025
5026 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5027 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5028 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5029 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
5030
5031 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
5032 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
5033
5034 IEM_MC_ADVANCE_RIP_AND_FINISH();
5035 IEM_MC_END();
5036 }
5037 else
5038 {
5039 /*
5040 * 256-bit: Memory, register.
5041 */
5042 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
5043 IEM_MC_LOCAL(RTUINT256U, uSrc);
5044 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5045
5046 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5047 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5048 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5049 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
5050
5051 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
5052 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
5053
5054 IEM_MC_ADVANCE_RIP_AND_FINISH();
5055 IEM_MC_END();
5056 }
5057 }
5058 /**
5059 * @opdone
5060 * @opmnemonic udvex660fe7reg
5061 * @opcode 0xe7
5062 * @opcodesub 11 mr/reg
5063 * @oppfx 0x66
5064 * @opunused immediate
5065 * @opcpuid avx
5066 * @optest ->
5067 */
5068 else
5069 IEMOP_RAISE_INVALID_OPCODE_RET();
5070}
5071
5072/* Opcode VEX.F3.0F 0xe7 - invalid */
5073/* Opcode VEX.F2.0F 0xe7 - invalid */
5074
5075
5076/* Opcode VEX.0F 0xe8 - invalid */
5077
5078
5079/** Opcode VEX.66.0F 0xe8 - vpsubsb Vx, Hx, Wx */
5080FNIEMOP_DEF(iemOp_vpsubsb_Vx_Hx_Wx)
5081{
5082 IEMOP_MNEMONIC3(VEX_RVM, VPSUBSB, vpsubsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5083 IEMOPMEDIAOPTF3_INIT_VARS(vpsubsb);
5084 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5085}
5086
5087
5088/* Opcode VEX.F3.0F 0xe8 - invalid */
5089/* Opcode VEX.F2.0F 0xe8 - invalid */
5090
5091/* Opcode VEX.0F 0xe9 - invalid */
5092
5093
5094/** Opcode VEX.66.0F 0xe9 - vpsubsw Vx, Hx, Wx */
5095FNIEMOP_DEF(iemOp_vpsubsw_Vx_Hx_Wx)
5096{
5097 IEMOP_MNEMONIC3(VEX_RVM, VPSUBSW, vpsubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5098 IEMOPMEDIAOPTF3_INIT_VARS(vpsubsw);
5099 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5100}
5101
5102
5103/* Opcode VEX.F3.0F 0xe9 - invalid */
5104/* Opcode VEX.F2.0F 0xe9 - invalid */
5105
5106/* Opcode VEX.0F 0xea - invalid */
5107
5108
5109/** Opcode VEX.66.0F 0xea - vpminsw Vx, Hx, Wx */
5110FNIEMOP_DEF(iemOp_vpminsw_Vx_Hx_Wx)
5111{
5112 IEMOP_MNEMONIC3(VEX_RVM, VPMINSW, vpminsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5113 IEMOPMEDIAF3_INIT_VARS(vpminsw);
5114 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5115}
5116
5117
5118/* Opcode VEX.F3.0F 0xea - invalid */
5119/* Opcode VEX.F2.0F 0xea - invalid */
5120
5121/* Opcode VEX.0F 0xeb - invalid */
5122
5123
5124/** Opcode VEX.66.0F 0xeb - vpor Vx, Hx, Wx */
5125FNIEMOP_DEF(iemOp_vpor_Vx_Hx_Wx)
5126{
5127 IEMOP_MNEMONIC3(VEX_RVM, VPOR, vpor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5128 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
5129 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
5130}
5131
5132
5133
5134/* Opcode VEX.F3.0F 0xeb - invalid */
5135/* Opcode VEX.F2.0F 0xeb - invalid */
5136
5137/* Opcode VEX.0F 0xec - invalid */
5138
5139
5140/** Opcode VEX.66.0F 0xec - vpaddsb Vx, Hx, Wx */
5141FNIEMOP_DEF(iemOp_vpaddsb_Vx_Hx_Wx)
5142{
5143 IEMOP_MNEMONIC3(VEX_RVM, VPADDSB, vpaddsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5144 IEMOPMEDIAOPTF3_INIT_VARS(vpaddsb);
5145 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5146}
5147
5148
5149/* Opcode VEX.F3.0F 0xec - invalid */
5150/* Opcode VEX.F2.0F 0xec - invalid */
5151
5152/* Opcode VEX.0F 0xed - invalid */
5153
5154
5155/** Opcode VEX.66.0F 0xed - vpaddsw Vx, Hx, Wx */
5156FNIEMOP_DEF(iemOp_vpaddsw_Vx_Hx_Wx)
5157{
5158 IEMOP_MNEMONIC3(VEX_RVM, VPADDSW, vpaddsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5159 IEMOPMEDIAOPTF3_INIT_VARS(vpaddsw);
5160 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5161}
5162
5163
5164/* Opcode VEX.F3.0F 0xed - invalid */
5165/* Opcode VEX.F2.0F 0xed - invalid */
5166
5167/* Opcode VEX.0F 0xee - invalid */
5168
5169
5170/** Opcode VEX.66.0F 0xee - vpmaxsw Vx, Hx, Wx */
5171FNIEMOP_DEF(iemOp_vpmaxsw_Vx_Hx_Wx)
5172{
5173 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSW, vpmaxsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5174 IEMOPMEDIAF3_INIT_VARS(vpmaxsw);
5175 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5176}
5177
5178
5179/* Opcode VEX.F3.0F 0xee - invalid */
5180/* Opcode VEX.F2.0F 0xee - invalid */
5181
5182
5183/* Opcode VEX.0F 0xef - invalid */
5184
5185
5186/** Opcode VEX.66.0F 0xef - vpxor Vx, Hx, Wx */
5187FNIEMOP_DEF(iemOp_vpxor_Vx_Hx_Wx)
5188{
5189 IEMOP_MNEMONIC3(VEX_RVM, VPXOR, vpxor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5190 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx,
5191 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
5192}
5193
5194
5195/* Opcode VEX.F3.0F 0xef - invalid */
5196/* Opcode VEX.F2.0F 0xef - invalid */
5197
5198/* Opcode VEX.0F 0xf0 - invalid */
5199/* Opcode VEX.66.0F 0xf0 - invalid */
5200
5201
5202/** Opcode VEX.F2.0F 0xf0 - vlddqu Vx, Mx */
5203FNIEMOP_DEF(iemOp_vlddqu_Vx_Mx)
5204{
5205 IEMOP_MNEMONIC2(VEX_RM_MEM, VLDDQU, vlddqu, Vx_WO, Mx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
5206 Assert(pVCpu->iem.s.uVexLength <= 1);
5207 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5208 if (IEM_IS_MODRM_REG_MODE(bRm))
5209 {
5210 /*
5211 * Register, register - (not implemented, assuming it raises \#UD).
5212 */
5213 IEMOP_RAISE_INVALID_OPCODE_RET();
5214 }
5215 else if (pVCpu->iem.s.uVexLength == 0)
5216 {
5217 /*
5218 * Register, memory128.
5219 */
5220 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
5221 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
5222 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5223
5224 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5225 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5226 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5227 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
5228
5229 IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
5230 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
5231
5232 IEM_MC_ADVANCE_RIP_AND_FINISH();
5233 IEM_MC_END();
5234 }
5235 else
5236 {
5237 /*
5238 * Register, memory256.
5239 */
5240 IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
5241 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
5242 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5243
5244 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5245 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5246 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5247 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
5248
5249 IEM_MC_FETCH_MEM_U256(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
5250 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
5251
5252 IEM_MC_ADVANCE_RIP_AND_FINISH();
5253 IEM_MC_END();
5254 }
5255}
5256
5257
5258/* Opcode VEX.0F 0xf1 - invalid */
5259/** Opcode VEX.66.0F 0xf1 - vpsllw Vx, Hx, W */
5260FNIEMOP_STUB(iemOp_vpsllw_Vx_Hx_W);
5261/* Opcode VEX.F2.0F 0xf1 - invalid */
5262
5263/* Opcode VEX.0F 0xf2 - invalid */
5264/** Opcode VEX.66.0F 0xf2 - vpslld Vx, Hx, Wx */
5265FNIEMOP_STUB(iemOp_vpslld_Vx_Hx_Wx);
5266/* Opcode VEX.F2.0F 0xf2 - invalid */
5267
5268/* Opcode VEX.0F 0xf3 - invalid */
5269/** Opcode VEX.66.0F 0xf3 - vpsllq Vx, Hx, Wx */
5270FNIEMOP_STUB(iemOp_vpsllq_Vx_Hx_Wx);
5271/* Opcode VEX.F2.0F 0xf3 - invalid */
5272
5273/* Opcode VEX.0F 0xf4 - invalid */
5274
5275
5276/** Opcode VEX.66.0F 0xf4 - vpmuludq Vx, Hx, W */
5277FNIEMOP_DEF(iemOp_vpmuludq_Vx_Hx_W)
5278{
5279 IEMOP_MNEMONIC3(VEX_RVM, VPMULUDQ, vpmuludq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5280 IEMOPMEDIAOPTF3_INIT_VARS(vpmuludq);
5281 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5282}
5283
5284
5285/* Opcode VEX.F2.0F 0xf4 - invalid */
5286
5287/* Opcode VEX.0F 0xf5 - invalid */
5288/** Opcode VEX.66.0F 0xf5 - vpmaddwd Vx, Hx, Wx */
5289FNIEMOP_STUB(iemOp_vpmaddwd_Vx_Hx_Wx);
5290/* Opcode VEX.F2.0F 0xf5 - invalid */
5291
5292/* Opcode VEX.0F 0xf6 - invalid */
5293
5294
5295/** Opcode VEX.66.0F 0xf6 - vpsadbw Vx, Hx, Wx */
5296FNIEMOP_DEF(iemOp_vpsadbw_Vx_Hx_Wx)
5297{
5298 IEMOP_MNEMONIC3(VEX_RVM, VPSADBW, vpsadbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5299 IEMOPMEDIAOPTF3_INIT_VARS(vpsadbw);
5300 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5301}
5302
5303
5304/* Opcode VEX.F2.0F 0xf6 - invalid */
5305
5306/* Opcode VEX.0F 0xf7 - invalid */
5307/** Opcode VEX.66.0F 0xf7 - vmaskmovdqu Vdq, Udq */
5308FNIEMOP_STUB(iemOp_vmaskmovdqu_Vdq_Udq);
5309/* Opcode VEX.F2.0F 0xf7 - invalid */
5310
5311/* Opcode VEX.0F 0xf8 - invalid */
5312
5313
5314/** Opcode VEX.66.0F 0xf8 - vpsubb Vx, Hx, W */
5315FNIEMOP_DEF(iemOp_vpsubb_Vx_Hx_Wx)
5316{
5317 IEMOP_MNEMONIC3(VEX_RVM, VPSUBB, vpsubb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5318 IEMOPMEDIAF3_INIT_VARS( vpsubb);
5319 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5320}
5321
5322
5323/* Opcode VEX.F2.0F 0xf8 - invalid */
5324
5325/* Opcode VEX.0F 0xf9 - invalid */
5326
5327
5328/** Opcode VEX.66.0F 0xf9 - vpsubw Vx, Hx, Wx */
5329FNIEMOP_DEF(iemOp_vpsubw_Vx_Hx_Wx)
5330{
5331 IEMOP_MNEMONIC3(VEX_RVM, VPSUBW, vpsubw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5332 IEMOPMEDIAF3_INIT_VARS( vpsubw);
5333 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5334}
5335
5336
5337/* Opcode VEX.F2.0F 0xf9 - invalid */
5338
5339/* Opcode VEX.0F 0xfa - invalid */
5340
5341
5342/** Opcode VEX.66.0F 0xfa - vpsubd Vx, Hx, Wx */
5343FNIEMOP_DEF(iemOp_vpsubd_Vx_Hx_Wx)
5344{
5345 IEMOP_MNEMONIC3(VEX_RVM, VPSUBD, vpsubd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5346 IEMOPMEDIAF3_INIT_VARS( vpsubd);
5347 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5348}
5349
5350
5351/* Opcode VEX.F2.0F 0xfa - invalid */
5352
5353/* Opcode VEX.0F 0xfb - invalid */
5354
5355
5356/** Opcode VEX.66.0F 0xfb - vpsubq Vx, Hx, W */
5357FNIEMOP_DEF(iemOp_vpsubq_Vx_Hx_Wx)
5358{
5359 IEMOP_MNEMONIC3(VEX_RVM, VPSUBQ, vpsubq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5360 IEMOPMEDIAF3_INIT_VARS( vpsubq);
5361 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5362}
5363
5364
5365/* Opcode VEX.F2.0F 0xfb - invalid */
5366
5367/* Opcode VEX.0F 0xfc - invalid */
5368
5369
5370/** Opcode VEX.66.0F 0xfc - vpaddb Vx, Hx, Wx */
5371FNIEMOP_DEF(iemOp_vpaddb_Vx_Hx_Wx)
5372{
5373 IEMOP_MNEMONIC3(VEX_RVM, VPADDB, vpaddb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5374 IEMOPMEDIAF3_INIT_VARS( vpaddb);
5375 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5376}
5377
5378
5379/* Opcode VEX.F2.0F 0xfc - invalid */
5380
5381/* Opcode VEX.0F 0xfd - invalid */
5382
5383
5384/** Opcode VEX.66.0F 0xfd - vpaddw Vx, Hx, Wx */
5385FNIEMOP_DEF(iemOp_vpaddw_Vx_Hx_Wx)
5386{
5387 IEMOP_MNEMONIC3(VEX_RVM, VPADDW, vpaddw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5388 IEMOPMEDIAF3_INIT_VARS( vpaddw);
5389 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5390}
5391
5392
5393/* Opcode VEX.F2.0F 0xfd - invalid */
5394
5395/* Opcode VEX.0F 0xfe - invalid */
5396
5397
5398/** Opcode VEX.66.0F 0xfe - vpaddd Vx, Hx, W */
5399FNIEMOP_DEF(iemOp_vpaddd_Vx_Hx_Wx)
5400{
5401 IEMOP_MNEMONIC3(VEX_RVM, VPADDD, vpaddd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5402 IEMOPMEDIAF3_INIT_VARS( vpaddd);
5403 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5404}
5405
5406
5407/* Opcode VEX.F2.0F 0xfe - invalid */
5408
5409
5410/** Opcode **** 0x0f 0xff - UD0 */
5411FNIEMOP_DEF(iemOp_vud0)
5412{
5413/** @todo testcase: vud0 */
5414 IEMOP_MNEMONIC(vud0, "vud0");
5415 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
5416 {
5417 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
5418 if (IEM_IS_MODRM_MEM_MODE(bRm))
5419 IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(bRm);
5420 }
5421 IEMOP_HLP_DONE_DECODING();
5422 IEMOP_RAISE_INVALID_OPCODE_RET();
5423}
5424
5425
5426
5427/**
5428 * VEX opcode map \#1.
5429 *
5430 * @sa g_apfnTwoByteMap
5431 */
5432const PFNIEMOP g_apfnVexMap1[] =
5433{
5434 /* no prefix, 066h prefix f3h prefix, f2h prefix */
5435 /* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRM),
5436 /* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRM),
5437 /* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRM),
5438 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRM),
5439 /* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRM),
5440 /* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRM),
5441 /* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRM),
5442 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRM),
5443 /* 0x08 */ IEMOP_X4(iemOp_InvalidNeedRM),
5444 /* 0x09 */ IEMOP_X4(iemOp_InvalidNeedRM),
5445 /* 0x0a */ IEMOP_X4(iemOp_InvalidNeedRM),
5446 /* 0x0b */ IEMOP_X4(iemOp_vud2), /* ?? */
5447 /* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
5448 /* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
5449 /* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
5450 /* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
5451
5452 /* 0x10 */ iemOp_vmovups_Vps_Wps, iemOp_vmovupd_Vpd_Wpd, iemOp_vmovss_Vss_Hss_Wss, iemOp_vmovsd_Vsd_Hsd_Wsd,
5453 /* 0x11 */ iemOp_vmovups_Wps_Vps, iemOp_vmovupd_Wpd_Vpd, iemOp_vmovss_Wss_Hss_Vss, iemOp_vmovsd_Wsd_Hsd_Vsd,
5454 /* 0x12 */ iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx, iemOp_vmovddup_Vx_Wx,
5455 /* 0x13 */ iemOp_vmovlps_Mq_Vq, iemOp_vmovlpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5456 /* 0x14 */ iemOp_vunpcklps_Vx_Hx_Wx, iemOp_vunpcklpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5457 /* 0x15 */ iemOp_vunpckhps_Vx_Hx_Wx, iemOp_vunpckhpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5458 /* 0x16 */ iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq, iemOp_vmovhpd_Vdq_Hq_Mq, iemOp_vmovshdup_Vx_Wx, iemOp_InvalidNeedRM,
5459 /* 0x17 */ iemOp_vmovhps_Mq_Vq, iemOp_vmovhpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5460 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
5461 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
5462 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
5463 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
5464 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRM),
5465 /* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRM),
5466 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRM),
5467 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
5468
5469 /* 0x20 */ IEMOP_X4(iemOp_InvalidNeedRM),
5470 /* 0x21 */ IEMOP_X4(iemOp_InvalidNeedRM),
5471 /* 0x22 */ IEMOP_X4(iemOp_InvalidNeedRM),
5472 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRM),
5473 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRM),
5474 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRM),
5475 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
5476 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
5477 /* 0x28 */ iemOp_vmovaps_Vps_Wps, iemOp_vmovapd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5478 /* 0x29 */ iemOp_vmovaps_Wps_Vps, iemOp_vmovapd_Wpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5479 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtsi2ss_Vss_Hss_Ey, iemOp_vcvtsi2sd_Vsd_Hsd_Ey,
5480 /* 0x2b */ iemOp_vmovntps_Mps_Vps, iemOp_vmovntpd_Mpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5481 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvttss2si_Gy_Wss, iemOp_vcvttsd2si_Gy_Wsd,
5482 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtss2si_Gy_Wss, iemOp_vcvtsd2si_Gy_Wsd,
5483 /* 0x2e */ iemOp_vucomiss_Vss_Wss, iemOp_vucomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5484 /* 0x2f */ iemOp_vcomiss_Vss_Wss, iemOp_vcomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5485
5486 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRM),
5487 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRM),
5488 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRM),
5489 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRM),
5490 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRM),
5491 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRM),
5492 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
5493 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRM),
5494 /* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5495 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5496 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5497 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5498 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5499 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5500 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5501 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5502
5503 /* 0x40 */ IEMOP_X4(iemOp_InvalidNeedRM),
5504 /* 0x41 */ IEMOP_X4(iemOp_InvalidNeedRM),
5505 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
5506 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
5507 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
5508 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
5509 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
5510 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
5511 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
5512 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
5513 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
5514 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
5515 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
5516 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
5517 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
5518 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
5519
5520 /* 0x50 */ iemOp_vmovmskps_Gy_Ups, iemOp_vmovmskpd_Gy_Upd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5521 /* 0x51 */ iemOp_vsqrtps_Vps_Wps, iemOp_vsqrtpd_Vpd_Wpd, iemOp_vsqrtss_Vss_Hss_Wss, iemOp_vsqrtsd_Vsd_Hsd_Wsd,
5522 /* 0x52 */ iemOp_vrsqrtps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrsqrtss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
5523 /* 0x53 */ iemOp_vrcpps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrcpss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
5524 /* 0x54 */ iemOp_vandps_Vps_Hps_Wps, iemOp_vandpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5525 /* 0x55 */ iemOp_vandnps_Vps_Hps_Wps, iemOp_vandnpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5526 /* 0x56 */ iemOp_vorps_Vps_Hps_Wps, iemOp_vorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5527 /* 0x57 */ iemOp_vxorps_Vps_Hps_Wps, iemOp_vxorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5528 /* 0x58 */ iemOp_vaddps_Vps_Hps_Wps, iemOp_vaddpd_Vpd_Hpd_Wpd, iemOp_vaddss_Vss_Hss_Wss, iemOp_vaddsd_Vsd_Hsd_Wsd,
5529 /* 0x59 */ iemOp_vmulps_Vps_Hps_Wps, iemOp_vmulpd_Vpd_Hpd_Wpd, iemOp_vmulss_Vss_Hss_Wss, iemOp_vmulsd_Vsd_Hsd_Wsd,
5530 /* 0x5a */ iemOp_vcvtps2pd_Vpd_Wps, iemOp_vcvtpd2ps_Vps_Wpd, iemOp_vcvtss2sd_Vsd_Hx_Wss, iemOp_vcvtsd2ss_Vss_Hx_Wsd,
5531 /* 0x5b */ iemOp_vcvtdq2ps_Vps_Wdq, iemOp_vcvtps2dq_Vdq_Wps, iemOp_vcvttps2dq_Vdq_Wps, iemOp_InvalidNeedRM,
5532 /* 0x5c */ iemOp_vsubps_Vps_Hps_Wps, iemOp_vsubpd_Vpd_Hpd_Wpd, iemOp_vsubss_Vss_Hss_Wss, iemOp_vsubsd_Vsd_Hsd_Wsd,
5533 /* 0x5d */ iemOp_vminps_Vps_Hps_Wps, iemOp_vminpd_Vpd_Hpd_Wpd, iemOp_vminss_Vss_Hss_Wss, iemOp_vminsd_Vsd_Hsd_Wsd,
5534 /* 0x5e */ iemOp_vdivps_Vps_Hps_Wps, iemOp_vdivpd_Vpd_Hpd_Wpd, iemOp_vdivss_Vss_Hss_Wss, iemOp_vdivsd_Vsd_Hsd_Wsd,
5535 /* 0x5f */ iemOp_vmaxps_Vps_Hps_Wps, iemOp_vmaxpd_Vpd_Hpd_Wpd, iemOp_vmaxss_Vss_Hss_Wss, iemOp_vmaxsd_Vsd_Hsd_Wsd,
5536
5537 /* 0x60 */ iemOp_InvalidNeedRM, iemOp_vpunpcklbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5538 /* 0x61 */ iemOp_InvalidNeedRM, iemOp_vpunpcklwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5539 /* 0x62 */ iemOp_InvalidNeedRM, iemOp_vpunpckldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5540 /* 0x63 */ iemOp_InvalidNeedRM, iemOp_vpacksswb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5541 /* 0x64 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5542 /* 0x65 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5543 /* 0x66 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5544 /* 0x67 */ iemOp_InvalidNeedRM, iemOp_vpackuswb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5545 /* 0x68 */ iemOp_InvalidNeedRM, iemOp_vpunpckhbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5546 /* 0x69 */ iemOp_InvalidNeedRM, iemOp_vpunpckhwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5547 /* 0x6a */ iemOp_InvalidNeedRM, iemOp_vpunpckhdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5548 /* 0x6b */ iemOp_InvalidNeedRM, iemOp_vpackssdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5549 /* 0x6c */ iemOp_InvalidNeedRM, iemOp_vpunpcklqdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5550 /* 0x6d */ iemOp_InvalidNeedRM, iemOp_vpunpckhqdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5551 /* 0x6e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Vy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5552 /* 0x6f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Vx_Wx, iemOp_vmovdqu_Vx_Wx, iemOp_InvalidNeedRM,
5553
5554 /* 0x70 */ iemOp_InvalidNeedRM, iemOp_vpshufd_Vx_Wx_Ib, iemOp_vpshufhw_Vx_Wx_Ib, iemOp_vpshuflw_Vx_Wx_Ib,
5555 /* 0x71 */ iemOp_InvalidNeedRM, iemOp_VGrp12, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5556 /* 0x72 */ iemOp_InvalidNeedRM, iemOp_VGrp13, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5557 /* 0x73 */ iemOp_InvalidNeedRM, iemOp_VGrp14, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5558 /* 0x74 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5559 /* 0x75 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5560 /* 0x76 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5561 /* 0x77 */ iemOp_vzeroupperv__vzeroallv, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5562 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
5563 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
5564 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
5565 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
5566 /* 0x7c */ iemOp_InvalidNeedRM, iemOp_vhaddpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhaddps_Vps_Hps_Wps,
5567 /* 0x7d */ iemOp_InvalidNeedRM, iemOp_vhsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhsubps_Vps_Hps_Wps,
5568 /* 0x7e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Ey_Vy, iemOp_vmovq_Vq_Wq, iemOp_InvalidNeedRM,
5569 /* 0x7f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Wx_Vx, iemOp_vmovdqu_Wx_Vx, iemOp_InvalidNeedRM,
5570
5571 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
5572 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
5573 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
5574 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
5575 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
5576 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
5577 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
5578 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
5579 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
5580 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
5581 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
5582 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
5583 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
5584 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
5585 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
5586 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
5587
5588 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
5589 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
5590 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
5591 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
5592 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
5593 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
5594 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
5595 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
5596 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
5597 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
5598 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
5599 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
5600 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
5601 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
5602 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
5603 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
5604
5605 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
5606 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
5607 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
5608 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
5609 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
5610 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
5611 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
5612 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
5613 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
5614 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
5615 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
5616 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
5617 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
5618 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
5619 /* 0xae */ IEMOP_X4(iemOp_VGrp15),
5620 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
5621
5622 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
5623 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
5624 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
5625 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
5626 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
5627 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
5628 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
5629 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
5630 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
5631 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
5632 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
5633 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
5634 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
5635 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
5636 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
5637 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
5638
5639 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
5640 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
5641 /* 0xc2 */ iemOp_vcmpps_Vps_Hps_Wps_Ib, iemOp_vcmppd_Vpd_Hpd_Wpd_Ib, iemOp_vcmpss_Vss_Hss_Wss_Ib, iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib,
5642 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
5643 /* 0xc4 */ iemOp_InvalidNeedRM, iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
5644 /* 0xc5 */ iemOp_InvalidNeedRM, iemOp_vpextrw_Gd_Udq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
5645 /* 0xc6 */ iemOp_vshufps_Vps_Hps_Wps_Ib, iemOp_vshufpd_Vpd_Hpd_Wpd_Ib, iemOp_InvalidNeedRMImm8,iemOp_InvalidNeedRMImm8,
5646 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
5647 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
5648 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
5649 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
5650 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
5651 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
5652 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
5653 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
5654 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
5655
5656 /* 0xd0 */ iemOp_InvalidNeedRM, iemOp_vaddsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vaddsubps_Vps_Hps_Wps,
5657 /* 0xd1 */ iemOp_InvalidNeedRM, iemOp_vpsrlw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5658 /* 0xd2 */ iemOp_InvalidNeedRM, iemOp_vpsrld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5659 /* 0xd3 */ iemOp_InvalidNeedRM, iemOp_vpsrlq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5660 /* 0xd4 */ iemOp_InvalidNeedRM, iemOp_vpaddq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5661 /* 0xd5 */ iemOp_InvalidNeedRM, iemOp_vpmullw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5662 /* 0xd6 */ iemOp_InvalidNeedRM, iemOp_vmovq_Wq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5663 /* 0xd7 */ iemOp_InvalidNeedRM, iemOp_vpmovmskb_Gd_Ux, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5664 /* 0xd8 */ iemOp_InvalidNeedRM, iemOp_vpsubusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5665 /* 0xd9 */ iemOp_InvalidNeedRM, iemOp_vpsubusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5666 /* 0xda */ iemOp_InvalidNeedRM, iemOp_vpminub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5667 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vpand_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5668 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vpaddusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5669 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vpaddusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5670 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vpmaxub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5671 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vpandn_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5672
5673 /* 0xe0 */ iemOp_InvalidNeedRM, iemOp_vpavgb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5674 /* 0xe1 */ iemOp_InvalidNeedRM, iemOp_vpsraw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5675 /* 0xe2 */ iemOp_InvalidNeedRM, iemOp_vpsrad_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5676 /* 0xe3 */ iemOp_InvalidNeedRM, iemOp_vpavgw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5677 /* 0xe4 */ iemOp_InvalidNeedRM, iemOp_vpmulhuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5678 /* 0xe5 */ iemOp_InvalidNeedRM, iemOp_vpmulhw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5679 /* 0xe6 */ iemOp_InvalidNeedRM, iemOp_vcvttpd2dq_Vx_Wpd, iemOp_vcvtdq2pd_Vx_Wpd, iemOp_vcvtpd2dq_Vx_Wpd,
5680 /* 0xe7 */ iemOp_InvalidNeedRM, iemOp_vmovntdq_Mx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5681 /* 0xe8 */ iemOp_InvalidNeedRM, iemOp_vpsubsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5682 /* 0xe9 */ iemOp_InvalidNeedRM, iemOp_vpsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5683 /* 0xea */ iemOp_InvalidNeedRM, iemOp_vpminsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5684 /* 0xeb */ iemOp_InvalidNeedRM, iemOp_vpor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5685 /* 0xec */ iemOp_InvalidNeedRM, iemOp_vpaddsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5686 /* 0xed */ iemOp_InvalidNeedRM, iemOp_vpaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5687 /* 0xee */ iemOp_InvalidNeedRM, iemOp_vpmaxsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5688 /* 0xef */ iemOp_InvalidNeedRM, iemOp_vpxor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5689
5690 /* 0xf0 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vlddqu_Vx_Mx,
5691 /* 0xf1 */ iemOp_InvalidNeedRM, iemOp_vpsllw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5692 /* 0xf2 */ iemOp_InvalidNeedRM, iemOp_vpslld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5693 /* 0xf3 */ iemOp_InvalidNeedRM, iemOp_vpsllq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5694 /* 0xf4 */ iemOp_InvalidNeedRM, iemOp_vpmuludq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5695 /* 0xf5 */ iemOp_InvalidNeedRM, iemOp_vpmaddwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5696 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_vpsadbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5697 /* 0xf7 */ iemOp_InvalidNeedRM, iemOp_vmaskmovdqu_Vdq_Udq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5698 /* 0xf8 */ iemOp_InvalidNeedRM, iemOp_vpsubb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5699 /* 0xf9 */ iemOp_InvalidNeedRM, iemOp_vpsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5700 /* 0xfa */ iemOp_InvalidNeedRM, iemOp_vpsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5701 /* 0xfb */ iemOp_InvalidNeedRM, iemOp_vpsubq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5702 /* 0xfc */ iemOp_InvalidNeedRM, iemOp_vpaddb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5703 /* 0xfd */ iemOp_InvalidNeedRM, iemOp_vpaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5704 /* 0xfe */ iemOp_InvalidNeedRM, iemOp_vpaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5705 /* 0xff */ IEMOP_X4(iemOp_vud0) /* ?? */
5706};
5707AssertCompile(RT_ELEMENTS(g_apfnVexMap1) == 1024);
5708/** @} */
5709
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