VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h@ 105214

Last change on this file since 105214 was 105214, checked in by vboxsync, 5 months ago

VMM/IEM: Implement vsubps instruction emulation, bugref:9898
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1/* $Id: IEMAllInstVexMap1.cpp.h 105214 2024-07-09 08:27:57Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstTwoByte0f.cpp.h is a legacy mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 1
33 * @{
34 */
35
36/**
37 * Common worker for AVX2 instructions on the forms:
38 * - vpxxx xmm0, xmm1, xmm2/mem128
39 * - vpxxx ymm0, ymm1, ymm2/mem256
40 *
41 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
42 */
43FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, PCIEMOPMEDIAF3, pImpl)
44{
45 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
46 if (IEM_IS_MODRM_REG_MODE(bRm))
47 {
48 /*
49 * Register, register.
50 */
51 if (pVCpu->iem.s.uVexLength)
52 {
53 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
54 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
55 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
56 IEM_MC_PREPARE_AVX_USAGE();
57
58 IEM_MC_LOCAL(X86YMMREG, uSrc1);
59 IEM_MC_ARG_LOCAL_REF(PCX86YMMREG, puSrc1, uSrc1, 1);
60 IEM_MC_FETCH_YREG_YMM(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
61 IEM_MC_LOCAL(X86YMMREG, uSrc2);
62 IEM_MC_ARG_LOCAL_REF(PCX86YMMREG, puSrc2, uSrc2, 2);
63 IEM_MC_FETCH_YREG_YMM(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
64 IEM_MC_LOCAL(X86YMMREG, uDst);
65 IEM_MC_ARG_LOCAL_REF(PX86YMMREG, puDst, uDst, 0);
66 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
67 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
68 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
69 IEM_MC_ADVANCE_RIP_AND_FINISH();
70 IEM_MC_END();
71 }
72 else
73 {
74 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
75 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
76 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
77 IEM_MC_PREPARE_AVX_USAGE();
78
79 IEM_MC_LOCAL(X86XMMREG, uDst);
80 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
81 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
82 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
83 IEM_MC_ARG(PCX86XMMREG, puSrc2, 2);
84 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
85 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
86 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
87 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
88 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
89 IEM_MC_ADVANCE_RIP_AND_FINISH();
90 IEM_MC_END();
91 }
92 }
93 else
94 {
95 /*
96 * Register, memory.
97 */
98 if (pVCpu->iem.s.uVexLength)
99 {
100 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
101 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
102 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
103 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
104 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
105 IEM_MC_PREPARE_AVX_USAGE();
106
107 IEM_MC_LOCAL(X86YMMREG, uSrc2);
108 IEM_MC_ARG_LOCAL_REF(PCX86YMMREG, puSrc2, uSrc2, 2);
109 IEM_MC_FETCH_MEM_YMM_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
110 IEM_MC_LOCAL(X86YMMREG, uSrc1);
111 IEM_MC_ARG_LOCAL_REF(PCX86YMMREG, puSrc1, uSrc1, 1);
112 IEM_MC_FETCH_YREG_YMM(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
113 IEM_MC_LOCAL(X86YMMREG, uDst);
114 IEM_MC_ARG_LOCAL_REF(PX86YMMREG, puDst, uDst, 0);
115 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
116 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
117 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
118 IEM_MC_ADVANCE_RIP_AND_FINISH();
119 IEM_MC_END();
120 }
121 else
122 {
123 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
124 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
125 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
126 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
127 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
128 IEM_MC_PREPARE_AVX_USAGE();
129
130 IEM_MC_LOCAL(X86XMMREG, uDst);
131 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
132 IEM_MC_LOCAL(X86XMMREG, uSrc2);
133 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 2);
134 IEM_MC_FETCH_MEM_XMM_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
135 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
136 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
137
138 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
139 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
140 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
141 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
142 IEM_MC_ADVANCE_RIP_AND_FINISH();
143 IEM_MC_END();
144 }
145 }
146}
147
148
149/**
150 * Common worker for scalar AVX/AVX2 instructions on the forms (addss,addsd,etc.):
151 * - vxxxs{s,d} xmm0, xmm1, xmm2/mem32
152 *
153 * Exceptions type 4. AVX cpuid check for 128-bit operation.
154 * Ignores VEX.L, from SDM:
155 * Software should ensure VADDSS is encoded with VEX.L=0.
156 * Encoding VADDSS with VEX.L=1 may encounter unpredictable behavior
157 * across different processor generations.
158 */
159FNIEMOP_DEF_1(iemOpCommonAvx_Vx_Hx_R32, PFNIEMAIMPLFPAVXF3U128R32, pfnU128)
160{
161 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
162 if (IEM_IS_MODRM_REG_MODE(bRm))
163 {
164 /*
165 * Register, register.
166 */
167 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
168 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
169 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
170 IEM_MC_PREPARE_AVX_USAGE();
171
172 IEM_MC_LOCAL(X86XMMREG, uDst);
173 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
174 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
175 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
176 IEM_MC_ARG(PCRTFLOAT32U, pr32Src2, 2);
177 IEM_MC_REF_XREG_R32_CONST(pr32Src2, IEM_GET_MODRM_RM(pVCpu, bRm));
178 IEM_MC_CALL_AVX_AIMPL_3(pfnU128, puDst, puSrc1, pr32Src2);
179 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
180 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
181 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
182 IEM_MC_ADVANCE_RIP_AND_FINISH();
183 IEM_MC_END();
184 }
185 else
186 {
187 /*
188 * Register, memory.
189 */
190 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
191 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
192 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
193 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
194 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
195 IEM_MC_PREPARE_AVX_USAGE();
196
197 IEM_MC_LOCAL(RTFLOAT32U, r32Src2);
198 IEM_MC_ARG_LOCAL_REF(PCRTFLOAT32U, pr32Src2, r32Src2, 2);
199 IEM_MC_FETCH_MEM_R32(r32Src2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
200 IEM_MC_LOCAL(X86XMMREG, uDst);
201 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
202 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
203 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
204 IEM_MC_CALL_AVX_AIMPL_3(pfnU128, puDst, puSrc1, pr32Src2);
205 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
206 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
207 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
208 IEM_MC_ADVANCE_RIP_AND_FINISH();
209 IEM_MC_END();
210 }
211}
212
213
214/**
215 * Common worker for AVX2 instructions on the forms:
216 * - vpxxx xmm0, xmm1, xmm2/mem128
217 * - vpxxx ymm0, ymm1, ymm2/mem256
218 *
219 * Takes function table for function w/o implicit state parameter.
220 *
221 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
222 */
223FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, PCIEMOPMEDIAOPTF3, pImpl)
224{
225 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
226 if (IEM_IS_MODRM_REG_MODE(bRm))
227 {
228 /*
229 * Register, register.
230 */
231 if (pVCpu->iem.s.uVexLength)
232 {
233 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
234 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
235 IEM_MC_LOCAL(RTUINT256U, uDst);
236 IEM_MC_LOCAL(RTUINT256U, uSrc1);
237 IEM_MC_LOCAL(RTUINT256U, uSrc2);
238 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
239 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
240 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
241 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
242 IEM_MC_PREPARE_AVX_USAGE();
243 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
244 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
245 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
246 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
247 IEM_MC_ADVANCE_RIP_AND_FINISH();
248 IEM_MC_END();
249 }
250 else
251 {
252 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
253 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
254 IEM_MC_ARG(PRTUINT128U, puDst, 0);
255 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
256 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
257 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
258 IEM_MC_PREPARE_AVX_USAGE();
259 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
260 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
261 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
262 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
263 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
264 IEM_MC_ADVANCE_RIP_AND_FINISH();
265 IEM_MC_END();
266 }
267 }
268 else
269 {
270 /*
271 * Register, memory.
272 */
273 if (pVCpu->iem.s.uVexLength)
274 {
275 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
276 IEM_MC_LOCAL(RTUINT256U, uDst);
277 IEM_MC_LOCAL(RTUINT256U, uSrc1);
278 IEM_MC_LOCAL(RTUINT256U, uSrc2);
279 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
280 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
281 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
282 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
283
284 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
285 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
286 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
287 IEM_MC_PREPARE_AVX_USAGE();
288
289 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
290 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
291 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
292 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
293
294 IEM_MC_ADVANCE_RIP_AND_FINISH();
295 IEM_MC_END();
296 }
297 else
298 {
299 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
300 IEM_MC_LOCAL(RTUINT128U, uSrc2);
301 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
302 IEM_MC_ARG(PRTUINT128U, puDst, 0);
303 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
304 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
305
306 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
307 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
308 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
309 IEM_MC_PREPARE_AVX_USAGE();
310
311 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
312 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
313 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
314 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
315 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
316
317 IEM_MC_ADVANCE_RIP_AND_FINISH();
318 IEM_MC_END();
319 }
320 }
321}
322
323
324/**
325 * Common worker for AVX2 instructions on the forms:
326 * - vpunpckhxx xmm0, xmm1, xmm2/mem128
327 * - vpunpckhxx ymm0, ymm1, ymm2/mem256
328 *
329 * The 128-bit memory version of this instruction may elect to skip fetching the
330 * lower 64 bits of the operand. We, however, do not.
331 *
332 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
333 */
334FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, PCIEMOPMEDIAOPTF3, pImpl)
335{
336 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
337}
338
339
340/**
341 * Common worker for AVX2 instructions on the forms:
342 * - vpunpcklxx xmm0, xmm1, xmm2/mem128
343 * - vpunpcklxx ymm0, ymm1, ymm2/mem256
344 *
345 * The 128-bit memory version of this instruction may elect to skip fetching the
346 * higher 64 bits of the operand. We, however, do not.
347 *
348 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
349 */
350FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, PCIEMOPMEDIAOPTF3, pImpl)
351{
352 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
353}
354
355
356/**
357 * Common worker for AVX2 instructions on the forms:
358 * - vpxxx xmm0, xmm1/mem128
359 * - vpxxx ymm0, ymm1/mem256
360 *
361 * Takes function table for function w/o implicit state parameter.
362 *
363 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
364 */
365FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, PCIEMOPMEDIAOPTF2, pImpl)
366{
367 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
368 if (IEM_IS_MODRM_REG_MODE(bRm))
369 {
370 /*
371 * Register, register.
372 */
373 if (pVCpu->iem.s.uVexLength)
374 {
375 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
376 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
377 IEM_MC_LOCAL(RTUINT256U, uDst);
378 IEM_MC_LOCAL(RTUINT256U, uSrc);
379 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
380 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
381 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
382 IEM_MC_PREPARE_AVX_USAGE();
383 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
384 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
385 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
386 IEM_MC_ADVANCE_RIP_AND_FINISH();
387 IEM_MC_END();
388 }
389 else
390 {
391 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
392 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
393 IEM_MC_ARG(PRTUINT128U, puDst, 0);
394 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
395 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
396 IEM_MC_PREPARE_AVX_USAGE();
397 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
398 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
399 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
400 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
401 IEM_MC_ADVANCE_RIP_AND_FINISH();
402 IEM_MC_END();
403 }
404 }
405 else
406 {
407 /*
408 * Register, memory.
409 */
410 if (pVCpu->iem.s.uVexLength)
411 {
412 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
413 IEM_MC_LOCAL(RTUINT256U, uDst);
414 IEM_MC_LOCAL(RTUINT256U, uSrc);
415 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
416 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
417 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
418
419 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
420 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
421 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
422 IEM_MC_PREPARE_AVX_USAGE();
423
424 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
425 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
426 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
427
428 IEM_MC_ADVANCE_RIP_AND_FINISH();
429 IEM_MC_END();
430 }
431 else
432 {
433 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
434 IEM_MC_LOCAL(RTUINT128U, uSrc);
435 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
436 IEM_MC_ARG(PRTUINT128U, puDst, 0);
437 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
438
439 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
440 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
441 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
442 IEM_MC_PREPARE_AVX_USAGE();
443
444 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
445 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
446 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
447 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
448
449 IEM_MC_ADVANCE_RIP_AND_FINISH();
450 IEM_MC_END();
451 }
452 }
453}
454
455
456/* Opcode VEX.0F 0x00 - invalid */
457/* Opcode VEX.0F 0x01 - invalid */
458/* Opcode VEX.0F 0x02 - invalid */
459/* Opcode VEX.0F 0x03 - invalid */
460/* Opcode VEX.0F 0x04 - invalid */
461/* Opcode VEX.0F 0x05 - invalid */
462/* Opcode VEX.0F 0x06 - invalid */
463/* Opcode VEX.0F 0x07 - invalid */
464/* Opcode VEX.0F 0x08 - invalid */
465/* Opcode VEX.0F 0x09 - invalid */
466/* Opcode VEX.0F 0x0a - invalid */
467
468/** Opcode VEX.0F 0x0b. */
469FNIEMOP_DEF(iemOp_vud2)
470{
471 IEMOP_MNEMONIC(vud2, "vud2");
472 IEMOP_RAISE_INVALID_OPCODE_RET();
473}
474
475/* Opcode VEX.0F 0x0c - invalid */
476/* Opcode VEX.0F 0x0d - invalid */
477/* Opcode VEX.0F 0x0e - invalid */
478/* Opcode VEX.0F 0x0f - invalid */
479
480
481/**
482 * @opcode 0x10
483 * @oppfx none
484 * @opcpuid avx
485 * @opgroup og_avx_simdfp_datamove
486 * @opxcpttype 4UA
487 * @optest op1=1 op2=2 -> op1=2
488 * @optest op1=0 op2=-22 -> op1=-22
489 */
490FNIEMOP_DEF(iemOp_vmovups_Vps_Wps)
491{
492 IEMOP_MNEMONIC2(VEX_RM, VMOVUPS, vmovups, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
493 Assert(pVCpu->iem.s.uVexLength <= 1);
494 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
495 if (IEM_IS_MODRM_REG_MODE(bRm))
496 {
497 /*
498 * Register, register.
499 */
500 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
501 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
502 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
503 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
504 if (pVCpu->iem.s.uVexLength == 0)
505 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
506 IEM_GET_MODRM_RM(pVCpu, bRm));
507 else
508 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
509 IEM_GET_MODRM_RM(pVCpu, bRm));
510 IEM_MC_ADVANCE_RIP_AND_FINISH();
511 IEM_MC_END();
512 }
513 else if (pVCpu->iem.s.uVexLength == 0)
514 {
515 /*
516 * 128-bit: Register, Memory
517 */
518 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
519 IEM_MC_LOCAL(RTUINT128U, uSrc);
520 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
521
522 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
523 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
524 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
525 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
526
527 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
528 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
529
530 IEM_MC_ADVANCE_RIP_AND_FINISH();
531 IEM_MC_END();
532 }
533 else
534 {
535 /*
536 * 256-bit: Register, Memory
537 */
538 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
539 IEM_MC_LOCAL(RTUINT256U, uSrc);
540 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
541
542 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
543 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
544 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
545 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
546
547 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
548 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
549
550 IEM_MC_ADVANCE_RIP_AND_FINISH();
551 IEM_MC_END();
552 }
553}
554
555
556/**
557 * @opcode 0x10
558 * @oppfx 0x66
559 * @opcpuid avx
560 * @opgroup og_avx_simdfp_datamove
561 * @opxcpttype 4UA
562 * @optest op1=1 op2=2 -> op1=2
563 * @optest op1=0 op2=-22 -> op1=-22
564 */
565FNIEMOP_DEF(iemOp_vmovupd_Vpd_Wpd)
566{
567 IEMOP_MNEMONIC2(VEX_RM, VMOVUPD, vmovupd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
568 Assert(pVCpu->iem.s.uVexLength <= 1);
569 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
570 if (IEM_IS_MODRM_REG_MODE(bRm))
571 {
572 /*
573 * Register, register.
574 */
575 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
576 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
577 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
578 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
579 if (pVCpu->iem.s.uVexLength == 0)
580 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
581 IEM_GET_MODRM_RM(pVCpu, bRm));
582 else
583 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
584 IEM_GET_MODRM_RM(pVCpu, bRm));
585 IEM_MC_ADVANCE_RIP_AND_FINISH();
586 IEM_MC_END();
587 }
588 else if (pVCpu->iem.s.uVexLength == 0)
589 {
590 /*
591 * 128-bit: Memory, register.
592 */
593 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
594 IEM_MC_LOCAL(RTUINT128U, uSrc);
595 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
596
597 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
598 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
599 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
600 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
601
602 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
603 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
604
605 IEM_MC_ADVANCE_RIP_AND_FINISH();
606 IEM_MC_END();
607 }
608 else
609 {
610 /*
611 * 256-bit: Memory, register.
612 */
613 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
614 IEM_MC_LOCAL(RTUINT256U, uSrc);
615 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
616
617 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
618 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
619 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
620 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
621
622 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
623 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
624
625 IEM_MC_ADVANCE_RIP_AND_FINISH();
626 IEM_MC_END();
627 }
628}
629
630
631FNIEMOP_DEF(iemOp_vmovss_Vss_Hss_Wss)
632{
633 Assert(pVCpu->iem.s.uVexLength <= 1);
634 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
635 if (IEM_IS_MODRM_REG_MODE(bRm))
636 {
637 /**
638 * @opcode 0x10
639 * @oppfx 0xf3
640 * @opcodesub 11 mr/reg
641 * @opcpuid avx
642 * @opgroup og_avx_simdfp_datamerge
643 * @opxcpttype 5
644 * @optest op1=1 op2=0 op3=2 -> op1=2
645 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
646 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
647 * @optest op1=3 op2=-2 op3=0x77 -> op1=-8589934473
648 * @note HssHi refers to bits 127:32.
649 */
650 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
651 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
652 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
653 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
654 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
655 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
656 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
657 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
658 IEM_MC_ADVANCE_RIP_AND_FINISH();
659 IEM_MC_END();
660 }
661 else
662 {
663 /**
664 * @opdone
665 * @opcode 0x10
666 * @oppfx 0xf3
667 * @opcodesub !11 mr/reg
668 * @opcpuid avx
669 * @opgroup og_avx_simdfp_datamove
670 * @opxcpttype 5
671 * @opfunction iemOp_vmovss_Vss_Hss_Wss
672 * @optest op1=1 op2=2 -> op1=2
673 * @optest op1=0 op2=-22 -> op1=-22
674 */
675 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSS, vmovss, VssZx_WO, Md, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
676 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
677 IEM_MC_LOCAL(uint32_t, uSrc);
678 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
679
680 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
681 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
682 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
683 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
684
685 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
686 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
687
688 IEM_MC_ADVANCE_RIP_AND_FINISH();
689 IEM_MC_END();
690 }
691}
692
693
694FNIEMOP_DEF(iemOp_vmovsd_Vsd_Hsd_Wsd)
695{
696 Assert(pVCpu->iem.s.uVexLength <= 1);
697 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
698 if (IEM_IS_MODRM_REG_MODE(bRm))
699 {
700 /**
701 * @opcode 0x10
702 * @oppfx 0xf2
703 * @opcodesub 11 mr/reg
704 * @opcpuid avx
705 * @opgroup og_avx_simdfp_datamerge
706 * @opxcpttype 5
707 * @optest op1=1 op2=0 op3=2 -> op1=2
708 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
709 * @optest op1=3 op2=-1 op3=0x77 ->
710 * op1=0xffffffffffffffff0000000000000077
711 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x420000000000000077
712 */
713 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
714 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
715 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
716
717 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
718 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
719 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
720 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
721 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
722 IEM_MC_ADVANCE_RIP_AND_FINISH();
723 IEM_MC_END();
724 }
725 else
726 {
727 /**
728 * @opdone
729 * @opcode 0x10
730 * @oppfx 0xf2
731 * @opcodesub !11 mr/reg
732 * @opcpuid avx
733 * @opgroup og_avx_simdfp_datamove
734 * @opxcpttype 5
735 * @opfunction iemOp_vmovsd_Vsd_Hsd_Wsd
736 * @optest op1=1 op2=2 -> op1=2
737 * @optest op1=0 op2=-22 -> op1=-22
738 */
739 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSD, vmovsd, VsdZx_WO, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
740 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
741 IEM_MC_LOCAL(uint64_t, uSrc);
742 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
743
744 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
745 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
746 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
747 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
748
749 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
750 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
751
752 IEM_MC_ADVANCE_RIP_AND_FINISH();
753 IEM_MC_END();
754 }
755}
756
757
758/**
759 * @opcode 0x11
760 * @oppfx none
761 * @opcpuid avx
762 * @opgroup og_avx_simdfp_datamove
763 * @opxcpttype 4UA
764 * @optest op1=1 op2=2 -> op1=2
765 * @optest op1=0 op2=-22 -> op1=-22
766 */
767FNIEMOP_DEF(iemOp_vmovups_Wps_Vps)
768{
769 IEMOP_MNEMONIC2(VEX_MR, VMOVUPS, vmovups, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
770 Assert(pVCpu->iem.s.uVexLength <= 1);
771 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
772 if (IEM_IS_MODRM_REG_MODE(bRm))
773 {
774 /*
775 * Register, register.
776 */
777 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
778 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
779 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
780 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
781 if (pVCpu->iem.s.uVexLength == 0)
782 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
783 IEM_GET_MODRM_REG(pVCpu, bRm));
784 else
785 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
786 IEM_GET_MODRM_REG(pVCpu, bRm));
787 IEM_MC_ADVANCE_RIP_AND_FINISH();
788 IEM_MC_END();
789 }
790 else if (pVCpu->iem.s.uVexLength == 0)
791 {
792 /*
793 * 128-bit: Memory, register.
794 */
795 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
796 IEM_MC_LOCAL(RTUINT128U, uSrc);
797 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
798
799 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
800 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
801 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
802 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
803
804 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
805 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
806
807 IEM_MC_ADVANCE_RIP_AND_FINISH();
808 IEM_MC_END();
809 }
810 else
811 {
812 /*
813 * 256-bit: Memory, register.
814 */
815 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
816 IEM_MC_LOCAL(RTUINT256U, uSrc);
817 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
818
819 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
820 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
821 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
822 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
823
824 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
825 IEM_MC_STORE_MEM_U256_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
826
827 IEM_MC_ADVANCE_RIP_AND_FINISH();
828 IEM_MC_END();
829 }
830}
831
832
833/**
834 * @opcode 0x11
835 * @oppfx 0x66
836 * @opcpuid avx
837 * @opgroup og_avx_simdfp_datamove
838 * @opxcpttype 4UA
839 * @optest op1=1 op2=2 -> op1=2
840 * @optest op1=0 op2=-22 -> op1=-22
841 */
842FNIEMOP_DEF(iemOp_vmovupd_Wpd_Vpd)
843{
844 IEMOP_MNEMONIC2(VEX_MR, VMOVUPD, vmovupd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
845 Assert(pVCpu->iem.s.uVexLength <= 1);
846 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
847 if (IEM_IS_MODRM_REG_MODE(bRm))
848 {
849 /*
850 * Register, register.
851 */
852 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
853 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
854 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
855 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
856 if (pVCpu->iem.s.uVexLength == 0)
857 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
858 IEM_GET_MODRM_REG(pVCpu, bRm));
859 else
860 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
861 IEM_GET_MODRM_REG(pVCpu, bRm));
862 IEM_MC_ADVANCE_RIP_AND_FINISH();
863 IEM_MC_END();
864 }
865 else if (pVCpu->iem.s.uVexLength == 0)
866 {
867 /*
868 * 128-bit: Memory, register.
869 */
870 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
871 IEM_MC_LOCAL(RTUINT128U, uSrc);
872 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
873
874 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
875 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
876 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
877 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
878
879 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
880 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
881
882 IEM_MC_ADVANCE_RIP_AND_FINISH();
883 IEM_MC_END();
884 }
885 else
886 {
887 /*
888 * 256-bit: Memory, register.
889 */
890 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
891 IEM_MC_LOCAL(RTUINT256U, uSrc);
892 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
893
894 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
895 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
896 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
897 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
898
899 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
900 IEM_MC_STORE_MEM_U256_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
901
902 IEM_MC_ADVANCE_RIP_AND_FINISH();
903 IEM_MC_END();
904 }
905}
906
907
908FNIEMOP_DEF(iemOp_vmovss_Wss_Hss_Vss)
909{
910 Assert(pVCpu->iem.s.uVexLength <= 1);
911 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
912 if (IEM_IS_MODRM_REG_MODE(bRm))
913 {
914 /**
915 * @opcode 0x11
916 * @oppfx 0xf3
917 * @opcodesub 11 mr/reg
918 * @opcpuid avx
919 * @opgroup og_avx_simdfp_datamerge
920 * @opxcpttype 5
921 * @optest op1=1 op2=0 op3=2 -> op1=2
922 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
923 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
924 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x4200000077
925 */
926 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
927 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
928 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
929
930 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
931 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
932 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
933 IEM_GET_MODRM_REG(pVCpu, bRm),
934 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
935 IEM_MC_ADVANCE_RIP_AND_FINISH();
936 IEM_MC_END();
937 }
938 else
939 {
940 /**
941 * @opdone
942 * @opcode 0x11
943 * @oppfx 0xf3
944 * @opcodesub !11 mr/reg
945 * @opcpuid avx
946 * @opgroup og_avx_simdfp_datamove
947 * @opxcpttype 5
948 * @opfunction iemOp_vmovss_Vss_Hss_Wss
949 * @optest op1=1 op2=2 -> op1=2
950 * @optest op1=0 op2=-22 -> op1=-22
951 */
952 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
953 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
954 IEM_MC_LOCAL(uint32_t, uSrc);
955 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
956
957 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
958 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
959 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
960 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
961
962 IEM_MC_FETCH_YREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
963 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
964
965 IEM_MC_ADVANCE_RIP_AND_FINISH();
966 IEM_MC_END();
967 }
968}
969
970
971FNIEMOP_DEF(iemOp_vmovsd_Wsd_Hsd_Vsd)
972{
973 Assert(pVCpu->iem.s.uVexLength <= 1);
974 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
975 if (IEM_IS_MODRM_REG_MODE(bRm))
976 {
977 /**
978 * @opcode 0x11
979 * @oppfx 0xf2
980 * @opcodesub 11 mr/reg
981 * @opcpuid avx
982 * @opgroup og_avx_simdfp_datamerge
983 * @opxcpttype 5
984 * @optest op1=1 op2=0 op3=2 -> op1=2
985 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
986 * @optest op1=3 op2=-1 op3=0x77 ->
987 * op1=0xffffffffffffffff0000000000000077
988 * @optest op2=0x42 op3=0x77 -> op1=0x420000000000000077
989 */
990 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
991 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
992 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
993
994 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
995 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
996 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
997 IEM_GET_MODRM_REG(pVCpu, bRm),
998 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
999 IEM_MC_ADVANCE_RIP_AND_FINISH();
1000 IEM_MC_END();
1001 }
1002 else
1003 {
1004 /**
1005 * @opdone
1006 * @opcode 0x11
1007 * @oppfx 0xf2
1008 * @opcodesub !11 mr/reg
1009 * @opcpuid avx
1010 * @opgroup og_avx_simdfp_datamove
1011 * @opxcpttype 5
1012 * @opfunction iemOp_vmovsd_Wsd_Hsd_Vsd
1013 * @optest op1=1 op2=2 -> op1=2
1014 * @optest op1=0 op2=-22 -> op1=-22
1015 */
1016 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSD, vmovsd, Mq_WO, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
1017 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1018 IEM_MC_LOCAL(uint64_t, uSrc);
1019 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1020
1021 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1022 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1023 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1024 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1025
1026 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
1027 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1028
1029 IEM_MC_ADVANCE_RIP_AND_FINISH();
1030 IEM_MC_END();
1031 }
1032}
1033
1034
1035FNIEMOP_DEF(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps)
1036{
1037 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1038 if (IEM_IS_MODRM_REG_MODE(bRm))
1039 {
1040 /**
1041 * @opcode 0x12
1042 * @opcodesub 11 mr/reg
1043 * @oppfx none
1044 * @opcpuid avx
1045 * @opgroup og_avx_simdfp_datamerge
1046 * @opxcpttype 7LZ
1047 * @optest op2=0x2200220122022203
1048 * op3=0x3304330533063307
1049 * -> op1=0x22002201220222033304330533063307
1050 * @optest op2=-1 op3=-42 -> op1=-42
1051 * @note op3 and op2 are only the 8-byte high XMM register halfs.
1052 */
1053 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1054 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1055 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1056
1057 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1058 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1059 IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1060 IEM_GET_MODRM_RM(pVCpu, bRm),
1061 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1062
1063 IEM_MC_ADVANCE_RIP_AND_FINISH();
1064 IEM_MC_END();
1065 }
1066 else
1067 {
1068 /**
1069 * @opdone
1070 * @opcode 0x12
1071 * @opcodesub !11 mr/reg
1072 * @oppfx none
1073 * @opcpuid avx
1074 * @opgroup og_avx_simdfp_datamove
1075 * @opxcpttype 5LZ
1076 * @opfunction iemOp_vmovlps_Vq_Hq_Mq__vmovhlps
1077 * @optest op1=1 op2=0 op3=0 -> op1=0
1078 * @optest op1=0 op2=-1 op3=-1 -> op1=-1
1079 * @optest op1=1 op2=2 op3=3 -> op1=0x20000000000000003
1080 * @optest op2=-1 op3=0x42 -> op1=0xffffffffffffffff0000000000000042
1081 */
1082 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPS, vmovlps, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1083
1084 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1085 IEM_MC_LOCAL(uint64_t, uSrc);
1086 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1087
1088 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1089 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1090 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1091 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1092
1093 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1094 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1095 uSrc,
1096 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1097
1098 IEM_MC_ADVANCE_RIP_AND_FINISH();
1099 IEM_MC_END();
1100 }
1101}
1102
1103
1104/**
1105 * @opcode 0x12
1106 * @opcodesub !11 mr/reg
1107 * @oppfx 0x66
1108 * @opcpuid avx
1109 * @opgroup og_avx_pcksclr_datamerge
1110 * @opxcpttype 5LZ
1111 * @optest op2=0 op3=2 -> op1=2
1112 * @optest op2=0x22 op3=0x33 -> op1=0x220000000000000033
1113 * @optest op2=0xfffffff0fffffff1 op3=0xeeeeeee8eeeeeee9
1114 * -> op1=0xfffffff0fffffff1eeeeeee8eeeeeee9
1115 */
1116FNIEMOP_DEF(iemOp_vmovlpd_Vq_Hq_Mq)
1117{
1118 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1119 if (IEM_IS_MODRM_MEM_MODE(bRm))
1120 {
1121 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPD, vmovlpd, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1122
1123 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1124 IEM_MC_LOCAL(uint64_t, uSrc);
1125 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1126
1127 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1128 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1129 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1130 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1131
1132 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1133 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1134 uSrc,
1135 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1136
1137 IEM_MC_ADVANCE_RIP_AND_FINISH();
1138 IEM_MC_END();
1139 }
1140
1141 /**
1142 * @opdone
1143 * @opmnemonic udvex660f12m3
1144 * @opcode 0x12
1145 * @opcodesub 11 mr/reg
1146 * @oppfx 0x66
1147 * @opunused immediate
1148 * @opcpuid avx
1149 * @optest ->
1150 */
1151 else
1152 IEMOP_RAISE_INVALID_OPCODE_RET();
1153}
1154
1155
1156/**
1157 * @opcode 0x12
1158 * @oppfx 0xf3
1159 * @opcpuid avx
1160 * @opgroup og_avx_pcksclr_datamove
1161 * @opxcpttype 4
1162 * @optest vex.l==0 / op1=-1 op2=0xdddddddd00000002eeeeeeee00000001
1163 * -> op1=0x00000002000000020000000100000001
1164 * @optest vex.l==1 /
1165 * op2=0xbbbbbbbb00000004cccccccc00000003dddddddd00000002eeeeeeee00000001
1166 * -> op1=0x0000000400000004000000030000000300000002000000020000000100000001
1167 */
1168FNIEMOP_DEF(iemOp_vmovsldup_Vx_Wx)
1169{
1170 IEMOP_MNEMONIC2(VEX_RM, VMOVSLDUP, vmovsldup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1171 Assert(pVCpu->iem.s.uVexLength <= 1);
1172 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1173 if (IEM_IS_MODRM_REG_MODE(bRm))
1174 {
1175 /*
1176 * Register, register.
1177 */
1178 if (pVCpu->iem.s.uVexLength == 0)
1179 {
1180 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1181 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1182 IEM_MC_LOCAL(RTUINT128U, uSrc);
1183
1184 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1185 IEM_MC_PREPARE_AVX_USAGE();
1186
1187 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1188 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1189 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1190 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1191 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1192 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1193
1194 IEM_MC_ADVANCE_RIP_AND_FINISH();
1195 IEM_MC_END();
1196 }
1197 else
1198 {
1199 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1200 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1201 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1202 IEM_MC_PREPARE_AVX_USAGE();
1203
1204 IEM_MC_LOCAL(RTUINT256U, uSrc);
1205 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1206 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1207 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1208 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1209 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1210 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 4);
1211 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 4);
1212 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 6);
1213 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 6);
1214 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1215
1216 IEM_MC_ADVANCE_RIP_AND_FINISH();
1217 IEM_MC_END();
1218 }
1219 }
1220 else
1221 {
1222 /*
1223 * Register, memory.
1224 */
1225 if (pVCpu->iem.s.uVexLength == 0)
1226 {
1227 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1228 IEM_MC_LOCAL(RTUINT128U, uSrc);
1229 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1230
1231 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1232 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1233 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1234 IEM_MC_PREPARE_AVX_USAGE();
1235
1236 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1237 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1238 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1239 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1240 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1241 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1242
1243 IEM_MC_ADVANCE_RIP_AND_FINISH();
1244 IEM_MC_END();
1245 }
1246 else
1247 {
1248 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1249 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1250 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1251 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1252 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1253 IEM_MC_PREPARE_AVX_USAGE();
1254
1255 IEM_MC_LOCAL(RTUINT256U, uSrc);
1256 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1257
1258 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1259 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1260 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1261 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1262 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 4);
1263 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 4);
1264 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 6);
1265 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 6);
1266 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1267
1268 IEM_MC_ADVANCE_RIP_AND_FINISH();
1269 IEM_MC_END();
1270 }
1271 }
1272}
1273
1274
1275/**
1276 * @opcode 0x12
1277 * @oppfx 0xf2
1278 * @opcpuid avx
1279 * @opgroup og_avx_pcksclr_datamove
1280 * @opxcpttype 5
1281 * @optest vex.l==0 / op2=0xddddddddeeeeeeee2222222211111111
1282 * -> op1=0x22222222111111112222222211111111
1283 * @optest vex.l==1 / op2=0xbbbbbbbbcccccccc4444444433333333ddddddddeeeeeeee2222222211111111
1284 * -> op1=0x4444444433333333444444443333333322222222111111112222222211111111
1285 */
1286FNIEMOP_DEF(iemOp_vmovddup_Vx_Wx)
1287{
1288 IEMOP_MNEMONIC2(VEX_RM, VMOVDDUP, vmovddup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1289 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1290 if (IEM_IS_MODRM_REG_MODE(bRm))
1291 {
1292 /*
1293 * Register, register.
1294 */
1295 if (pVCpu->iem.s.uVexLength == 0)
1296 {
1297 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1298 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1299 IEM_MC_LOCAL(uint64_t, uSrc);
1300
1301 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1302 IEM_MC_PREPARE_AVX_USAGE();
1303
1304 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /* a_iQword*/);
1305 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc);
1306 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc);
1307 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1308
1309 IEM_MC_ADVANCE_RIP_AND_FINISH();
1310 IEM_MC_END();
1311 }
1312 else
1313 {
1314 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1315 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1316 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1317 IEM_MC_PREPARE_AVX_USAGE();
1318
1319 IEM_MC_LOCAL(uint64_t, uSrc1);
1320 IEM_MC_LOCAL(uint64_t, uSrc2);
1321 IEM_MC_FETCH_YREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /* a_iQword*/);
1322 IEM_MC_FETCH_YREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 2 /* a_iQword*/);
1323
1324 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc1);
1325 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc1);
1326 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 2 /* a_iQword*/, uSrc2);
1327 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 3 /* a_iQword*/, uSrc2);
1328 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1329
1330 IEM_MC_ADVANCE_RIP_AND_FINISH();
1331 IEM_MC_END();
1332 }
1333 }
1334 else
1335 {
1336 /*
1337 * Register, memory.
1338 */
1339 if (pVCpu->iem.s.uVexLength == 0)
1340 {
1341 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1342 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1343 IEM_MC_LOCAL(uint64_t, uSrc);
1344
1345 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1346 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1347 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1348 IEM_MC_PREPARE_AVX_USAGE();
1349
1350 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1351 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc);
1352 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc);
1353 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1354
1355 IEM_MC_ADVANCE_RIP_AND_FINISH();
1356 IEM_MC_END();
1357 }
1358 else
1359 {
1360 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1361 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1362
1363 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1364 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1365 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1366 IEM_MC_PREPARE_AVX_USAGE();
1367
1368 IEM_MC_LOCAL(RTUINT256U, uSrc);
1369 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1370
1371 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQwDst*/, uSrc, 0 /*a_iQwSrc*/);
1372 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /*a_iQwDst*/, uSrc, 0 /*a_iQwSrc*/);
1373 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2 /*a_iQwDst*/, uSrc, 2 /*a_iQwSrc*/);
1374 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3 /*a_iQwDst*/, uSrc, 2 /*a_iQwSrc*/);
1375 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1376
1377 IEM_MC_ADVANCE_RIP_AND_FINISH();
1378 IEM_MC_END();
1379 }
1380 }
1381}
1382
1383
1384/**
1385 * @opcode 0x13
1386 * @opcodesub !11 mr/reg
1387 * @oppfx none
1388 * @opcpuid avx
1389 * @opgroup og_avx_simdfp_datamove
1390 * @opxcpttype 5
1391 * @optest op1=1 op2=2 -> op1=2
1392 * @optest op1=0 op2=-42 -> op1=-42
1393 */
1394FNIEMOP_DEF(iemOp_vmovlps_Mq_Vq)
1395{
1396 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1397 if (IEM_IS_MODRM_MEM_MODE(bRm))
1398 {
1399 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPS, vmovlps, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1400
1401 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1402 IEM_MC_LOCAL(uint64_t, uSrc);
1403 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1404
1405 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1406 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1407 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1408 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1409
1410 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
1411 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1412
1413 IEM_MC_ADVANCE_RIP_AND_FINISH();
1414 IEM_MC_END();
1415 }
1416
1417 /**
1418 * @opdone
1419 * @opmnemonic udvex0f13m3
1420 * @opcode 0x13
1421 * @opcodesub 11 mr/reg
1422 * @oppfx none
1423 * @opunused immediate
1424 * @opcpuid avx
1425 * @optest ->
1426 */
1427 else
1428 IEMOP_RAISE_INVALID_OPCODE_RET();
1429}
1430
1431
1432/**
1433 * @opcode 0x13
1434 * @opcodesub !11 mr/reg
1435 * @oppfx 0x66
1436 * @opcpuid avx
1437 * @opgroup og_avx_pcksclr_datamove
1438 * @opxcpttype 5
1439 * @optest op1=1 op2=2 -> op1=2
1440 * @optest op1=0 op2=-42 -> op1=-42
1441 */
1442FNIEMOP_DEF(iemOp_vmovlpd_Mq_Vq)
1443{
1444 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1445 if (IEM_IS_MODRM_MEM_MODE(bRm))
1446 {
1447 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPD, vmovlpd, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1448 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1449 IEM_MC_LOCAL(uint64_t, uSrc);
1450 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1451
1452 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1453 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1454 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1455 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1456
1457 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
1458 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1459
1460 IEM_MC_ADVANCE_RIP_AND_FINISH();
1461 IEM_MC_END();
1462 }
1463
1464 /**
1465 * @opdone
1466 * @opmnemonic udvex660f13m3
1467 * @opcode 0x13
1468 * @opcodesub 11 mr/reg
1469 * @oppfx 0x66
1470 * @opunused immediate
1471 * @opcpuid avx
1472 * @optest ->
1473 */
1474 else
1475 IEMOP_RAISE_INVALID_OPCODE_RET();
1476}
1477
1478/* Opcode VEX.F3.0F 0x13 - invalid */
1479/* Opcode VEX.F2.0F 0x13 - invalid */
1480
1481/** Opcode VEX.0F 0x14 - vunpcklps Vx, Hx, Wx*/
1482FNIEMOP_DEF(iemOp_vunpcklps_Vx_Hx_Wx)
1483{
1484 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPS, vunpcklps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1485 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklps);
1486 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1487}
1488
1489
1490/** Opcode VEX.66.0F 0x14 - vunpcklpd Vx,Hx,Wx */
1491FNIEMOP_DEF(iemOp_vunpcklpd_Vx_Hx_Wx)
1492{
1493 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPD, vunpcklpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1494 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklpd);
1495 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1496}
1497
1498
1499/* Opcode VEX.F3.0F 0x14 - invalid */
1500/* Opcode VEX.F2.0F 0x14 - invalid */
1501
1502
1503/** Opcode VEX.0F 0x15 - vunpckhps Vx, Hx, Wx */
1504FNIEMOP_DEF(iemOp_vunpckhps_Vx_Hx_Wx)
1505{
1506 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPS, vunpckhps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1507 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhps);
1508 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1509}
1510
1511
1512/** Opcode VEX.66.0F 0x15 - vunpckhpd Vx,Hx,Wx */
1513FNIEMOP_DEF(iemOp_vunpckhpd_Vx_Hx_Wx)
1514{
1515 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPD, vunpckhpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1516 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhpd);
1517 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1518}
1519
1520
1521/* Opcode VEX.F3.0F 0x15 - invalid */
1522/* Opcode VEX.F2.0F 0x15 - invalid */
1523
1524
1525FNIEMOP_DEF(iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq)
1526{
1527 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1528 if (IEM_IS_MODRM_REG_MODE(bRm))
1529 {
1530 /**
1531 * @opcode 0x16
1532 * @opcodesub 11 mr/reg
1533 * @oppfx none
1534 * @opcpuid avx
1535 * @opgroup og_avx_simdfp_datamerge
1536 * @opxcpttype 7LZ
1537 */
1538 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVLHPS, vmovlhps, Vq_WO, Hq, Uq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1539
1540 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1541 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1542
1543 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1544 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1545 IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1546 IEM_GET_MODRM_RM(pVCpu, bRm),
1547 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1548
1549 IEM_MC_ADVANCE_RIP_AND_FINISH();
1550 IEM_MC_END();
1551 }
1552 else
1553 {
1554 /**
1555 * @opdone
1556 * @opcode 0x16
1557 * @opcodesub !11 mr/reg
1558 * @oppfx none
1559 * @opcpuid avx
1560 * @opgroup og_avx_simdfp_datamove
1561 * @opxcpttype 5LZ
1562 * @opfunction iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq
1563 */
1564 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPS, vmovhps, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1565
1566 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1567 IEM_MC_LOCAL(uint64_t, uSrc);
1568 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1569
1570 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1571 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1572 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1573 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1574
1575 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1576 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1577 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1578 uSrc);
1579
1580 IEM_MC_ADVANCE_RIP_AND_FINISH();
1581 IEM_MC_END();
1582 }
1583}
1584
1585
1586/**
1587 * @opcode 0x16
1588 * @opcodesub !11 mr/reg
1589 * @oppfx 0x66
1590 * @opcpuid avx
1591 * @opgroup og_avx_pcksclr_datamerge
1592 * @opxcpttype 5LZ
1593 */
1594FNIEMOP_DEF(iemOp_vmovhpd_Vdq_Hq_Mq)
1595{
1596 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1597 if (IEM_IS_MODRM_MEM_MODE(bRm))
1598 {
1599 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPD, vmovhpd, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1600
1601 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1602 IEM_MC_LOCAL(uint64_t, uSrc);
1603 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1604
1605 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1606 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1607 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1608 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1609
1610 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1611 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1612 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1613 uSrc);
1614
1615 IEM_MC_ADVANCE_RIP_AND_FINISH();
1616 IEM_MC_END();
1617 }
1618
1619 /**
1620 * @opdone
1621 * @opmnemonic udvex660f16m3
1622 * @opcode 0x12
1623 * @opcodesub 11 mr/reg
1624 * @oppfx 0x66
1625 * @opunused immediate
1626 * @opcpuid avx
1627 * @optest ->
1628 */
1629 else
1630 IEMOP_RAISE_INVALID_OPCODE_RET();
1631}
1632
1633
1634/** Opcode VEX.F3.0F 0x16 - vmovshdup Vx, Wx */
1635/**
1636 * @opcode 0x16
1637 * @oppfx 0xf3
1638 * @opcpuid avx
1639 * @opgroup og_avx_pcksclr_datamove
1640 * @opxcpttype 4
1641 */
1642FNIEMOP_DEF(iemOp_vmovshdup_Vx_Wx)
1643{
1644 IEMOP_MNEMONIC2(VEX_RM, VMOVSHDUP, vmovshdup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1645 Assert(pVCpu->iem.s.uVexLength <= 1);
1646 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1647 if (IEM_IS_MODRM_REG_MODE(bRm))
1648 {
1649 /*
1650 * Register, register.
1651 */
1652 if (pVCpu->iem.s.uVexLength == 0)
1653 {
1654 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1655 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1656 IEM_MC_LOCAL(RTUINT128U, uSrc);
1657
1658 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1659 IEM_MC_PREPARE_AVX_USAGE();
1660
1661 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1662 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1663 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1664 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1665 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1666 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1667
1668 IEM_MC_ADVANCE_RIP_AND_FINISH();
1669 IEM_MC_END();
1670 }
1671 else
1672 {
1673 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1674 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1675 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1676 IEM_MC_PREPARE_AVX_USAGE();
1677
1678 IEM_MC_LOCAL(RTUINT256U, uSrc);
1679 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1680 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1681 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1682 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1683 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1684 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 5);
1685 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 5);
1686 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 7);
1687 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 7);
1688 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1689
1690 IEM_MC_ADVANCE_RIP_AND_FINISH();
1691 IEM_MC_END();
1692 }
1693 }
1694 else
1695 {
1696 /*
1697 * Register, memory.
1698 */
1699 if (pVCpu->iem.s.uVexLength == 0)
1700 {
1701 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1702 IEM_MC_LOCAL(RTUINT128U, uSrc);
1703 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1704
1705 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1706 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1707 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1708 IEM_MC_PREPARE_AVX_USAGE();
1709
1710 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1711 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1712 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1713 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1714 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1715 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1716
1717 IEM_MC_ADVANCE_RIP_AND_FINISH();
1718 IEM_MC_END();
1719 }
1720 else
1721 {
1722 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1723 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1724 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1725 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1726 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1727 IEM_MC_PREPARE_AVX_USAGE();
1728
1729 IEM_MC_LOCAL(RTUINT256U, uSrc);
1730 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1731
1732 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1733 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1734 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1735 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1736 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 5);
1737 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 5);
1738 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 7);
1739 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 7);
1740 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1741
1742 IEM_MC_ADVANCE_RIP_AND_FINISH();
1743 IEM_MC_END();
1744 }
1745 }
1746}
1747
1748
1749/* Opcode VEX.F2.0F 0x16 - invalid */
1750
1751
1752/**
1753 * @opcode 0x17
1754 * @opcodesub !11 mr/reg
1755 * @oppfx none
1756 * @opcpuid avx
1757 * @opgroup og_avx_simdfp_datamove
1758 * @opxcpttype 5
1759 */
1760FNIEMOP_DEF(iemOp_vmovhps_Mq_Vq)
1761{
1762 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1763 if (IEM_IS_MODRM_MEM_MODE(bRm))
1764 {
1765 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPS, vmovhps, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1766
1767 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1768 IEM_MC_LOCAL(uint64_t, uSrc);
1769 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1770
1771 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1772 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1773 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1774 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1775
1776 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 1 /*a_iQWord*/);
1777 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1778
1779 IEM_MC_ADVANCE_RIP_AND_FINISH();
1780 IEM_MC_END();
1781 }
1782
1783 /**
1784 * @opdone
1785 * @opmnemonic udvex0f17m3
1786 * @opcode 0x17
1787 * @opcodesub 11 mr/reg
1788 * @oppfx none
1789 * @opunused immediate
1790 * @opcpuid avx
1791 * @optest ->
1792 */
1793 else
1794 IEMOP_RAISE_INVALID_OPCODE_RET();
1795}
1796
1797
1798/**
1799 * @opcode 0x17
1800 * @opcodesub !11 mr/reg
1801 * @oppfx 0x66
1802 * @opcpuid avx
1803 * @opgroup og_avx_pcksclr_datamove
1804 * @opxcpttype 5
1805 */
1806FNIEMOP_DEF(iemOp_vmovhpd_Mq_Vq)
1807{
1808 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1809 if (IEM_IS_MODRM_MEM_MODE(bRm))
1810 {
1811 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPD, vmovhpd, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1812
1813 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1814 IEM_MC_LOCAL(uint64_t, uSrc);
1815 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1816
1817 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1818 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1819 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1820 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1821
1822 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 1 /*a_iQWord*/);
1823 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1824
1825 IEM_MC_ADVANCE_RIP_AND_FINISH();
1826 IEM_MC_END();
1827 }
1828
1829 /**
1830 * @opdone
1831 * @opmnemonic udvex660f17m3
1832 * @opcode 0x17
1833 * @opcodesub 11 mr/reg
1834 * @oppfx 0x66
1835 * @opunused immediate
1836 * @opcpuid avx
1837 * @optest ->
1838 */
1839 else
1840 IEMOP_RAISE_INVALID_OPCODE_RET();
1841}
1842
1843
1844/* Opcode VEX.F3.0F 0x17 - invalid */
1845/* Opcode VEX.F2.0F 0x17 - invalid */
1846
1847
1848/* Opcode VEX.0F 0x18 - invalid */
1849/* Opcode VEX.0F 0x19 - invalid */
1850/* Opcode VEX.0F 0x1a - invalid */
1851/* Opcode VEX.0F 0x1b - invalid */
1852/* Opcode VEX.0F 0x1c - invalid */
1853/* Opcode VEX.0F 0x1d - invalid */
1854/* Opcode VEX.0F 0x1e - invalid */
1855/* Opcode VEX.0F 0x1f - invalid */
1856
1857/* Opcode VEX.0F 0x20 - invalid */
1858/* Opcode VEX.0F 0x21 - invalid */
1859/* Opcode VEX.0F 0x22 - invalid */
1860/* Opcode VEX.0F 0x23 - invalid */
1861/* Opcode VEX.0F 0x24 - invalid */
1862/* Opcode VEX.0F 0x25 - invalid */
1863/* Opcode VEX.0F 0x26 - invalid */
1864/* Opcode VEX.0F 0x27 - invalid */
1865
1866/**
1867 * @opcode 0x28
1868 * @oppfx none
1869 * @opcpuid avx
1870 * @opgroup og_avx_pcksclr_datamove
1871 * @opxcpttype 1
1872 * @optest op1=1 op2=2 -> op1=2
1873 * @optest op1=0 op2=-42 -> op1=-42
1874 * @note Almost identical to vmovapd.
1875 */
1876FNIEMOP_DEF(iemOp_vmovaps_Vps_Wps)
1877{
1878 IEMOP_MNEMONIC2(VEX_RM, VMOVAPS, vmovaps, Vps_WO, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1879 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1880 Assert(pVCpu->iem.s.uVexLength <= 1);
1881 if (IEM_IS_MODRM_REG_MODE(bRm))
1882 {
1883 /*
1884 * Register, register.
1885 */
1886 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1887 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1888
1889 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1890 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1891 if (pVCpu->iem.s.uVexLength == 0)
1892 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1893 IEM_GET_MODRM_RM(pVCpu, bRm));
1894 else
1895 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1896 IEM_GET_MODRM_RM(pVCpu, bRm));
1897 IEM_MC_ADVANCE_RIP_AND_FINISH();
1898 IEM_MC_END();
1899 }
1900 else
1901 {
1902 /*
1903 * Register, memory.
1904 */
1905 if (pVCpu->iem.s.uVexLength == 0)
1906 {
1907 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1908 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1909 IEM_MC_LOCAL(RTUINT128U, uSrc);
1910
1911 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1912 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1913 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1914 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1915
1916 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1917 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1918
1919 IEM_MC_ADVANCE_RIP_AND_FINISH();
1920 IEM_MC_END();
1921 }
1922 else
1923 {
1924 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1925 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1926 IEM_MC_LOCAL(RTUINT256U, uSrc);
1927
1928 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1929 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1930 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1931 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1932
1933 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1934 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1935
1936 IEM_MC_ADVANCE_RIP_AND_FINISH();
1937 IEM_MC_END();
1938 }
1939 }
1940}
1941
1942
1943/**
1944 * @opcode 0x28
1945 * @oppfx 66
1946 * @opcpuid avx
1947 * @opgroup og_avx_pcksclr_datamove
1948 * @opxcpttype 1
1949 * @optest op1=1 op2=2 -> op1=2
1950 * @optest op1=0 op2=-42 -> op1=-42
1951 * @note Almost identical to vmovaps
1952 */
1953FNIEMOP_DEF(iemOp_vmovapd_Vpd_Wpd)
1954{
1955 IEMOP_MNEMONIC2(VEX_RM, VMOVAPD, vmovapd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1956 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1957 Assert(pVCpu->iem.s.uVexLength <= 1);
1958 if (IEM_IS_MODRM_REG_MODE(bRm))
1959 {
1960 /*
1961 * Register, register.
1962 */
1963 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1964 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1965
1966 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1967 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1968 if (pVCpu->iem.s.uVexLength == 0)
1969 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1970 IEM_GET_MODRM_RM(pVCpu, bRm));
1971 else
1972 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1973 IEM_GET_MODRM_RM(pVCpu, bRm));
1974 IEM_MC_ADVANCE_RIP_AND_FINISH();
1975 IEM_MC_END();
1976 }
1977 else
1978 {
1979 /*
1980 * Register, memory.
1981 */
1982 if (pVCpu->iem.s.uVexLength == 0)
1983 {
1984 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1985 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1986 IEM_MC_LOCAL(RTUINT128U, uSrc);
1987
1988 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1989 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1990 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1991 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1992
1993 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1994 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1995
1996 IEM_MC_ADVANCE_RIP_AND_FINISH();
1997 IEM_MC_END();
1998 }
1999 else
2000 {
2001 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2002 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2003 IEM_MC_LOCAL(RTUINT256U, uSrc);
2004
2005 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2006 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2007 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2008 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2009
2010 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2011 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
2012
2013 IEM_MC_ADVANCE_RIP_AND_FINISH();
2014 IEM_MC_END();
2015 }
2016 }
2017}
2018
2019/**
2020 * @opmnemonic udvexf30f28
2021 * @opcode 0x28
2022 * @oppfx 0xf3
2023 * @opunused vex.modrm
2024 * @opcpuid avx
2025 * @optest ->
2026 * @opdone
2027 */
2028
2029/**
2030 * @opmnemonic udvexf20f28
2031 * @opcode 0x28
2032 * @oppfx 0xf2
2033 * @opunused vex.modrm
2034 * @opcpuid avx
2035 * @optest ->
2036 * @opdone
2037 */
2038
2039/**
2040 * @opcode 0x29
2041 * @oppfx none
2042 * @opcpuid avx
2043 * @opgroup og_avx_pcksclr_datamove
2044 * @opxcpttype 1
2045 * @optest op1=1 op2=2 -> op1=2
2046 * @optest op1=0 op2=-42 -> op1=-42
2047 * @note Almost identical to vmovapd.
2048 */
2049FNIEMOP_DEF(iemOp_vmovaps_Wps_Vps)
2050{
2051 IEMOP_MNEMONIC2(VEX_MR, VMOVAPS, vmovaps, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2052 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2053 Assert(pVCpu->iem.s.uVexLength <= 1);
2054 if (IEM_IS_MODRM_REG_MODE(bRm))
2055 {
2056 /*
2057 * Register, register.
2058 */
2059 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2060 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2061
2062 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2063 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2064 if (pVCpu->iem.s.uVexLength == 0)
2065 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2066 IEM_GET_MODRM_REG(pVCpu, bRm));
2067 else
2068 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2069 IEM_GET_MODRM_REG(pVCpu, bRm));
2070 IEM_MC_ADVANCE_RIP_AND_FINISH();
2071 IEM_MC_END();
2072 }
2073 else
2074 {
2075 /*
2076 * Register, memory.
2077 */
2078 if (pVCpu->iem.s.uVexLength == 0)
2079 {
2080 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2081 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2082 IEM_MC_LOCAL(RTUINT128U, uSrc);
2083
2084 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2085 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2086 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2087 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2088
2089 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
2090 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2091
2092 IEM_MC_ADVANCE_RIP_AND_FINISH();
2093 IEM_MC_END();
2094 }
2095 else
2096 {
2097 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2098 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2099 IEM_MC_LOCAL(RTUINT256U, uSrc);
2100
2101 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2102 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2103 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2104 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2105
2106 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2107 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2108
2109 IEM_MC_ADVANCE_RIP_AND_FINISH();
2110 IEM_MC_END();
2111 }
2112 }
2113}
2114
2115/**
2116 * @opcode 0x29
2117 * @oppfx 66
2118 * @opcpuid avx
2119 * @opgroup og_avx_pcksclr_datamove
2120 * @opxcpttype 1
2121 * @optest op1=1 op2=2 -> op1=2
2122 * @optest op1=0 op2=-42 -> op1=-42
2123 * @note Almost identical to vmovaps
2124 */
2125FNIEMOP_DEF(iemOp_vmovapd_Wpd_Vpd)
2126{
2127 IEMOP_MNEMONIC2(VEX_MR, VMOVAPD, vmovapd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2128 Assert(pVCpu->iem.s.uVexLength <= 1);
2129 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2130 if (IEM_IS_MODRM_REG_MODE(bRm))
2131 {
2132 /*
2133 * Register, register.
2134 */
2135 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2136 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2137
2138 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2139 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2140 if (pVCpu->iem.s.uVexLength == 0)
2141 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2142 IEM_GET_MODRM_REG(pVCpu, bRm));
2143 else
2144 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2145 IEM_GET_MODRM_REG(pVCpu, bRm));
2146 IEM_MC_ADVANCE_RIP_AND_FINISH();
2147 IEM_MC_END();
2148 }
2149 else
2150 {
2151 /*
2152 * Register, memory.
2153 */
2154 if (pVCpu->iem.s.uVexLength == 0)
2155 {
2156 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2157 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2158 IEM_MC_LOCAL(RTUINT128U, uSrc);
2159
2160 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2161 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2162 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2163 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2164
2165 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
2166 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2167
2168 IEM_MC_ADVANCE_RIP_AND_FINISH();
2169 IEM_MC_END();
2170 }
2171 else
2172 {
2173 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2174 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2175 IEM_MC_LOCAL(RTUINT256U, uSrc);
2176
2177 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2178 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2179 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2180 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2181
2182 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2183 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2184
2185 IEM_MC_ADVANCE_RIP_AND_FINISH();
2186 IEM_MC_END();
2187 }
2188 }
2189}
2190
2191
2192/**
2193 * @opmnemonic udvexf30f29
2194 * @opcode 0x29
2195 * @oppfx 0xf3
2196 * @opunused vex.modrm
2197 * @opcpuid avx
2198 * @optest ->
2199 * @opdone
2200 */
2201
2202/**
2203 * @opmnemonic udvexf20f29
2204 * @opcode 0x29
2205 * @oppfx 0xf2
2206 * @opunused vex.modrm
2207 * @opcpuid avx
2208 * @optest ->
2209 * @opdone
2210 */
2211
2212
2213/** Opcode VEX.0F 0x2a - invalid */
2214/** Opcode VEX.66.0F 0x2a - invalid */
2215/** Opcode VEX.F3.0F 0x2a - vcvtsi2ss Vss, Hss, Ey */
2216FNIEMOP_STUB(iemOp_vcvtsi2ss_Vss_Hss_Ey);
2217/** Opcode VEX.F2.0F 0x2a - vcvtsi2sd Vsd, Hsd, Ey */
2218FNIEMOP_STUB(iemOp_vcvtsi2sd_Vsd_Hsd_Ey);
2219
2220
2221/**
2222 * @opcode 0x2b
2223 * @opcodesub !11 mr/reg
2224 * @oppfx none
2225 * @opcpuid avx
2226 * @opgroup og_avx_cachect
2227 * @opxcpttype 1
2228 * @optest op1=1 op2=2 -> op1=2
2229 * @optest op1=0 op2=-42 -> op1=-42
2230 * @note Identical implementation to vmovntpd
2231 */
2232FNIEMOP_DEF(iemOp_vmovntps_Mps_Vps)
2233{
2234 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPS, vmovntps, Mps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2235 Assert(pVCpu->iem.s.uVexLength <= 1);
2236 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2237 if (IEM_IS_MODRM_MEM_MODE(bRm))
2238 {
2239 /*
2240 * memory, register.
2241 */
2242 if (pVCpu->iem.s.uVexLength == 0)
2243 {
2244 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2245 IEM_MC_LOCAL(RTUINT128U, uSrc);
2246 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2247
2248 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2249 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2250 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2251 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2252
2253 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2254 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2255
2256 IEM_MC_ADVANCE_RIP_AND_FINISH();
2257 IEM_MC_END();
2258 }
2259 else
2260 {
2261 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2262 IEM_MC_LOCAL(RTUINT256U, uSrc);
2263 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2264
2265 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2266 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2267 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2268 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2269
2270 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2271 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2272
2273 IEM_MC_ADVANCE_RIP_AND_FINISH();
2274 IEM_MC_END();
2275 }
2276 }
2277 /* The register, register encoding is invalid. */
2278 else
2279 IEMOP_RAISE_INVALID_OPCODE_RET();
2280}
2281
2282/**
2283 * @opcode 0x2b
2284 * @opcodesub !11 mr/reg
2285 * @oppfx 0x66
2286 * @opcpuid avx
2287 * @opgroup og_avx_cachect
2288 * @opxcpttype 1
2289 * @optest op1=1 op2=2 -> op1=2
2290 * @optest op1=0 op2=-42 -> op1=-42
2291 * @note Identical implementation to vmovntps
2292 */
2293FNIEMOP_DEF(iemOp_vmovntpd_Mpd_Vpd)
2294{
2295 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPD, vmovntpd, Mpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2296 Assert(pVCpu->iem.s.uVexLength <= 1);
2297 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2298 if (IEM_IS_MODRM_MEM_MODE(bRm))
2299 {
2300 /*
2301 * memory, register.
2302 */
2303 if (pVCpu->iem.s.uVexLength == 0)
2304 {
2305 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2306 IEM_MC_LOCAL(RTUINT128U, uSrc);
2307 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2308
2309 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2310 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2311 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2312 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2313
2314 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2315 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2316
2317 IEM_MC_ADVANCE_RIP_AND_FINISH();
2318 IEM_MC_END();
2319 }
2320 else
2321 {
2322 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2323 IEM_MC_LOCAL(RTUINT256U, uSrc);
2324 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2325
2326 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2327 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2328 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2329 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2330
2331 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2332 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2333
2334 IEM_MC_ADVANCE_RIP_AND_FINISH();
2335 IEM_MC_END();
2336 }
2337 }
2338 /* The register, register encoding is invalid. */
2339 else
2340 IEMOP_RAISE_INVALID_OPCODE_RET();
2341}
2342
2343/**
2344 * @opmnemonic udvexf30f2b
2345 * @opcode 0x2b
2346 * @oppfx 0xf3
2347 * @opunused vex.modrm
2348 * @opcpuid avx
2349 * @optest ->
2350 * @opdone
2351 */
2352
2353/**
2354 * @opmnemonic udvexf20f2b
2355 * @opcode 0x2b
2356 * @oppfx 0xf2
2357 * @opunused vex.modrm
2358 * @opcpuid avx
2359 * @optest ->
2360 * @opdone
2361 */
2362
2363
2364/* Opcode VEX.0F 0x2c - invalid */
2365/* Opcode VEX.66.0F 0x2c - invalid */
2366/** Opcode VEX.F3.0F 0x2c - vcvttss2si Gy, Wss */
2367FNIEMOP_STUB(iemOp_vcvttss2si_Gy_Wss);
2368/** Opcode VEX.F2.0F 0x2c - vcvttsd2si Gy, Wsd */
2369FNIEMOP_STUB(iemOp_vcvttsd2si_Gy_Wsd);
2370
2371/* Opcode VEX.0F 0x2d - invalid */
2372/* Opcode VEX.66.0F 0x2d - invalid */
2373/** Opcode VEX.F3.0F 0x2d - vcvtss2si Gy, Wss */
2374FNIEMOP_STUB(iemOp_vcvtss2si_Gy_Wss);
2375/** Opcode VEX.F2.0F 0x2d - vcvtsd2si Gy, Wsd */
2376FNIEMOP_STUB(iemOp_vcvtsd2si_Gy_Wsd);
2377
2378
2379/**
2380 * @opcode 0x2e
2381 * @oppfx none
2382 * @opflmodify cf,pf,af,zf,sf,of
2383 * @opflclear af,sf,of
2384 */
2385FNIEMOP_DEF(iemOp_vucomiss_Vss_Wss)
2386{
2387 IEMOP_MNEMONIC2(VEX_RM, VUCOMISS, vucomiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2388 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2389 if (IEM_IS_MODRM_REG_MODE(bRm))
2390 {
2391 /*
2392 * Register, register.
2393 */
2394 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2395 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2396 IEM_MC_LOCAL(uint32_t, fEFlags);
2397 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2398 IEM_MC_ARG(RTFLOAT32U, uSrc1, 1);
2399 IEM_MC_ARG(RTFLOAT32U, uSrc2, 2);
2400 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2401 IEM_MC_PREPARE_AVX_USAGE();
2402 IEM_MC_FETCH_EFLAGS(fEFlags);
2403 IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
2404 IEM_MC_FETCH_XREG_R32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iDWord*/);
2405 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
2406 pEFlags, uSrc1, uSrc2);
2407 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2408 IEM_MC_COMMIT_EFLAGS(fEFlags);
2409
2410 IEM_MC_ADVANCE_RIP_AND_FINISH();
2411 IEM_MC_END();
2412 }
2413 else
2414 {
2415 /*
2416 * Register, memory.
2417 */
2418 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2419 IEM_MC_LOCAL(uint32_t, fEFlags);
2420 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2421 IEM_MC_ARG(RTFLOAT32U, uSrc1, 1);
2422 IEM_MC_ARG(RTFLOAT32U, uSrc2, 2);
2423 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2424
2425 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2426 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2427 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2428 IEM_MC_FETCH_MEM_R32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2429
2430 IEM_MC_PREPARE_AVX_USAGE();
2431 IEM_MC_FETCH_EFLAGS(fEFlags);
2432 IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
2433 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
2434 pEFlags, uSrc1, uSrc2);
2435 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2436 IEM_MC_COMMIT_EFLAGS(fEFlags);
2437
2438 IEM_MC_ADVANCE_RIP_AND_FINISH();
2439 IEM_MC_END();
2440 }
2441}
2442
2443
2444/**
2445 * @opcode 0x2e
2446 * @oppfx 0x66
2447 * @opflmodify cf,pf,af,zf,sf,of
2448 * @opflclear af,sf,of
2449 */
2450FNIEMOP_DEF(iemOp_vucomisd_Vsd_Wsd)
2451{
2452 IEMOP_MNEMONIC2(VEX_RM, VUCOMISD, vucomisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2453 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2454 if (IEM_IS_MODRM_REG_MODE(bRm))
2455 {
2456 /*
2457 * Register, register.
2458 */
2459 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2460 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2461 IEM_MC_LOCAL(uint32_t, fEFlags);
2462 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2463 IEM_MC_ARG(RTFLOAT64U, uSrc1, 1);
2464 IEM_MC_ARG(RTFLOAT64U, uSrc2, 2);
2465 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2466 IEM_MC_PREPARE_AVX_USAGE();
2467 IEM_MC_FETCH_EFLAGS(fEFlags);
2468 IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
2469 IEM_MC_FETCH_XREG_R64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iQWord*/);
2470 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
2471 pEFlags, uSrc1, uSrc2);
2472 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2473 IEM_MC_COMMIT_EFLAGS(fEFlags);
2474
2475 IEM_MC_ADVANCE_RIP_AND_FINISH();
2476 IEM_MC_END();
2477 }
2478 else
2479 {
2480 /*
2481 * Register, memory.
2482 */
2483 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2484 IEM_MC_LOCAL(uint32_t, fEFlags);
2485 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2486 IEM_MC_ARG(RTFLOAT64U, uSrc1, 1);
2487 IEM_MC_ARG(RTFLOAT64U, uSrc2, 2);
2488 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2489
2490 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2491 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2492 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2493 IEM_MC_FETCH_MEM_R64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2494
2495 IEM_MC_PREPARE_AVX_USAGE();
2496 IEM_MC_FETCH_EFLAGS(fEFlags);
2497 IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
2498 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
2499 pEFlags, uSrc1, uSrc2);
2500 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2501 IEM_MC_COMMIT_EFLAGS(fEFlags);
2502
2503 IEM_MC_ADVANCE_RIP_AND_FINISH();
2504 IEM_MC_END();
2505 }
2506}
2507
2508
2509/* Opcode VEX.F3.0F 0x2e - invalid */
2510/* Opcode VEX.F2.0F 0x2e - invalid */
2511
2512/**
2513 * @opcode 0x2f
2514 * @oppfx none
2515 * @opflmodify cf,pf,af,zf,sf,of
2516 * @opflclear af,sf,of
2517 */
2518FNIEMOP_DEF(iemOp_vcomiss_Vss_Wss)
2519{
2520 IEMOP_MNEMONIC2(VEX_RM, VCOMISS, vcomiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2521 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2522 if (IEM_IS_MODRM_REG_MODE(bRm))
2523 {
2524 /*
2525 * Register, register.
2526 */
2527 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2528 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2529 IEM_MC_LOCAL(uint32_t, fEFlags);
2530 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2531 IEM_MC_ARG(RTFLOAT32U, uSrc1, 1);
2532 IEM_MC_ARG(RTFLOAT32U, uSrc2, 2);
2533 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2534 IEM_MC_PREPARE_AVX_USAGE();
2535 IEM_MC_FETCH_EFLAGS(fEFlags);
2536 IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
2537 IEM_MC_FETCH_XREG_R32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iDWord*/);
2538 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
2539 pEFlags, uSrc1, uSrc2);
2540 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2541 IEM_MC_COMMIT_EFLAGS(fEFlags);
2542
2543 IEM_MC_ADVANCE_RIP_AND_FINISH();
2544 IEM_MC_END();
2545 }
2546 else
2547 {
2548 /*
2549 * Register, memory.
2550 */
2551 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2552 IEM_MC_LOCAL(uint32_t, fEFlags);
2553 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2554 IEM_MC_ARG(RTFLOAT32U, uSrc1, 1);
2555 IEM_MC_ARG(RTFLOAT32U, uSrc2, 2);
2556 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2557
2558 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2559 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2560 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2561 IEM_MC_FETCH_MEM_R32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2562
2563 IEM_MC_PREPARE_AVX_USAGE();
2564 IEM_MC_FETCH_EFLAGS(fEFlags);
2565 IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
2566 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
2567 pEFlags, uSrc1, uSrc2);
2568 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2569 IEM_MC_COMMIT_EFLAGS(fEFlags);
2570
2571 IEM_MC_ADVANCE_RIP_AND_FINISH();
2572 IEM_MC_END();
2573 }
2574}
2575
2576
2577/**
2578 * @opcode 0x2f
2579 * @oppfx 0x66
2580 * @opflmodify cf,pf,af,zf,sf,of
2581 * @opflclear af,sf,of
2582 */
2583FNIEMOP_DEF(iemOp_vcomisd_Vsd_Wsd)
2584{
2585 IEMOP_MNEMONIC2(VEX_RM, VCOMISD, vcomisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2586 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2587 if (IEM_IS_MODRM_REG_MODE(bRm))
2588 {
2589 /*
2590 * Register, register.
2591 */
2592 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2593 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2594 IEM_MC_LOCAL(uint32_t, fEFlags);
2595 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2596 IEM_MC_ARG(RTFLOAT64U, uSrc1, 1);
2597 IEM_MC_ARG(RTFLOAT64U, uSrc2, 2);
2598 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2599 IEM_MC_PREPARE_AVX_USAGE();
2600 IEM_MC_FETCH_EFLAGS(fEFlags);
2601 IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
2602 IEM_MC_FETCH_XREG_R64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iQWord*/);
2603 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
2604 pEFlags, uSrc1, uSrc2);
2605 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2606 IEM_MC_COMMIT_EFLAGS(fEFlags);
2607
2608 IEM_MC_ADVANCE_RIP_AND_FINISH();
2609 IEM_MC_END();
2610 }
2611 else
2612 {
2613 /*
2614 * Register, memory.
2615 */
2616 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2617 IEM_MC_LOCAL(uint32_t, fEFlags);
2618 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2619 IEM_MC_ARG(RTFLOAT64U, uSrc1, 1);
2620 IEM_MC_ARG(RTFLOAT64U, uSrc2, 2);
2621 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2622
2623 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2624 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2625 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2626 IEM_MC_FETCH_MEM_R64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2627
2628 IEM_MC_PREPARE_AVX_USAGE();
2629 IEM_MC_FETCH_EFLAGS(fEFlags);
2630 IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
2631 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
2632 pEFlags, uSrc1, uSrc2);
2633 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2634 IEM_MC_COMMIT_EFLAGS(fEFlags);
2635
2636 IEM_MC_ADVANCE_RIP_AND_FINISH();
2637 IEM_MC_END();
2638 }
2639}
2640
2641
2642/* Opcode VEX.F3.0F 0x2f - invalid */
2643/* Opcode VEX.F2.0F 0x2f - invalid */
2644
2645/* Opcode VEX.0F 0x30 - invalid */
2646/* Opcode VEX.0F 0x31 - invalid */
2647/* Opcode VEX.0F 0x32 - invalid */
2648/* Opcode VEX.0F 0x33 - invalid */
2649/* Opcode VEX.0F 0x34 - invalid */
2650/* Opcode VEX.0F 0x35 - invalid */
2651/* Opcode VEX.0F 0x36 - invalid */
2652/* Opcode VEX.0F 0x37 - invalid */
2653/* Opcode VEX.0F 0x38 - invalid */
2654/* Opcode VEX.0F 0x39 - invalid */
2655/* Opcode VEX.0F 0x3a - invalid */
2656/* Opcode VEX.0F 0x3b - invalid */
2657/* Opcode VEX.0F 0x3c - invalid */
2658/* Opcode VEX.0F 0x3d - invalid */
2659/* Opcode VEX.0F 0x3e - invalid */
2660/* Opcode VEX.0F 0x3f - invalid */
2661/* Opcode VEX.0F 0x40 - invalid */
2662/* Opcode VEX.0F 0x41 - invalid */
2663/* Opcode VEX.0F 0x42 - invalid */
2664/* Opcode VEX.0F 0x43 - invalid */
2665/* Opcode VEX.0F 0x44 - invalid */
2666/* Opcode VEX.0F 0x45 - invalid */
2667/* Opcode VEX.0F 0x46 - invalid */
2668/* Opcode VEX.0F 0x47 - invalid */
2669/* Opcode VEX.0F 0x48 - invalid */
2670/* Opcode VEX.0F 0x49 - invalid */
2671/* Opcode VEX.0F 0x4a - invalid */
2672/* Opcode VEX.0F 0x4b - invalid */
2673/* Opcode VEX.0F 0x4c - invalid */
2674/* Opcode VEX.0F 0x4d - invalid */
2675/* Opcode VEX.0F 0x4e - invalid */
2676/* Opcode VEX.0F 0x4f - invalid */
2677
2678
2679/** Opcode VEX.0F 0x50 - vmovmskps Gy, Ups */
2680FNIEMOP_DEF(iemOp_vmovmskps_Gy_Ups)
2681{
2682 IEMOP_MNEMONIC2(VEX_RM_REG, VMOVMSKPS, vmovmskps, Gd, Ux, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2683 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2684 if (IEM_IS_MODRM_REG_MODE(bRm))
2685 {
2686 /*
2687 * Register, register.
2688 */
2689 if (pVCpu->iem.s.uVexLength == 0)
2690 {
2691 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2692 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2693 IEM_MC_LOCAL(uint8_t, u8Dst);
2694 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2695 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
2696 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2697 IEM_MC_PREPARE_AVX_USAGE();
2698 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2699 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmovmskps_u128, iemAImpl_vmovmskps_u128_fallback),
2700 pu8Dst, puSrc);
2701 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2702 IEM_MC_ADVANCE_RIP_AND_FINISH();
2703 IEM_MC_END();
2704 }
2705 else
2706 {
2707 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2708 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
2709 IEM_MC_LOCAL(uint8_t, u8Dst);
2710 IEM_MC_LOCAL(RTUINT256U, uSrc);
2711 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2712 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
2713
2714 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2715 IEM_MC_PREPARE_AVX_USAGE();
2716 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2717 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vmovmskps_u256, iemAImpl_vmovmskps_u256_fallback),
2718 pu8Dst, puSrc);
2719 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2720 IEM_MC_ADVANCE_RIP_AND_FINISH();
2721 IEM_MC_END();
2722 }
2723 }
2724 /* No memory operand. */
2725 else
2726 IEMOP_RAISE_INVALID_OPCODE_RET();
2727}
2728
2729
2730/** Opcode VEX.66.0F 0x50 - vmovmskpd Gy,Upd */
2731FNIEMOP_DEF(iemOp_vmovmskpd_Gy_Upd)
2732{
2733 IEMOP_MNEMONIC2(VEX_RM_REG, VMOVMSKPD, vmovmskpd, Gd, Ux, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2734 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2735 if (IEM_IS_MODRM_REG_MODE(bRm))
2736 {
2737 /*
2738 * Register, register.
2739 */
2740 if (pVCpu->iem.s.uVexLength == 0)
2741 {
2742 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2743 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2744 IEM_MC_LOCAL(uint8_t, u8Dst);
2745 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2746 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
2747 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2748 IEM_MC_PREPARE_AVX_USAGE();
2749 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2750 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmovmskpd_u128, iemAImpl_vmovmskpd_u128_fallback),
2751 pu8Dst, puSrc);
2752 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2753 IEM_MC_ADVANCE_RIP_AND_FINISH();
2754 IEM_MC_END();
2755 }
2756 else
2757 {
2758 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2759 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
2760 IEM_MC_LOCAL(uint8_t, u8Dst);
2761 IEM_MC_LOCAL(RTUINT256U, uSrc);
2762 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2763 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
2764
2765 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2766 IEM_MC_PREPARE_AVX_USAGE();
2767 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2768 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vmovmskpd_u256, iemAImpl_vmovmskpd_u256_fallback),
2769 pu8Dst, puSrc);
2770 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2771 IEM_MC_ADVANCE_RIP_AND_FINISH();
2772 IEM_MC_END();
2773 }
2774 }
2775 /* No memory operand. */
2776 else
2777 IEMOP_RAISE_INVALID_OPCODE_RET();
2778}
2779
2780
2781/* Opcode VEX.F3.0F 0x50 - invalid */
2782/* Opcode VEX.F2.0F 0x50 - invalid */
2783
2784/** Opcode VEX.0F 0x51 - vsqrtps Vps, Wps */
2785FNIEMOP_STUB(iemOp_vsqrtps_Vps_Wps);
2786/** Opcode VEX.66.0F 0x51 - vsqrtpd Vpd, Wpd */
2787FNIEMOP_STUB(iemOp_vsqrtpd_Vpd_Wpd);
2788/** Opcode VEX.F3.0F 0x51 - vsqrtss Vss, Hss, Wss */
2789FNIEMOP_STUB(iemOp_vsqrtss_Vss_Hss_Wss);
2790/** Opcode VEX.F2.0F 0x51 - vsqrtsd Vsd, Hsd, Wsd */
2791FNIEMOP_STUB(iemOp_vsqrtsd_Vsd_Hsd_Wsd);
2792
2793/** Opcode VEX.0F 0x52 - vrsqrtps Vps, Wps */
2794FNIEMOP_STUB(iemOp_vrsqrtps_Vps_Wps);
2795/* Opcode VEX.66.0F 0x52 - invalid */
2796/** Opcode VEX.F3.0F 0x52 - vrsqrtss Vss, Hss, Wss */
2797FNIEMOP_STUB(iemOp_vrsqrtss_Vss_Hss_Wss);
2798/* Opcode VEX.F2.0F 0x52 - invalid */
2799
2800/** Opcode VEX.0F 0x53 - vrcpps Vps, Wps */
2801FNIEMOP_STUB(iemOp_vrcpps_Vps_Wps);
2802/* Opcode VEX.66.0F 0x53 - invalid */
2803/** Opcode VEX.F3.0F 0x53 - vrcpss Vss, Hss, Wss */
2804FNIEMOP_STUB(iemOp_vrcpss_Vss_Hss_Wss);
2805/* Opcode VEX.F2.0F 0x53 - invalid */
2806
2807
2808/** Opcode VEX.0F 0x54 - vandps Vps, Hps, Wps */
2809FNIEMOP_DEF(iemOp_vandps_Vps_Hps_Wps)
2810{
2811 IEMOP_MNEMONIC3(VEX_RVM, VANDPS, vandps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2812 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2813 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2814}
2815
2816
2817/** Opcode VEX.66.0F 0x54 - vandpd Vpd, Hpd, Wpd */
2818FNIEMOP_DEF(iemOp_vandpd_Vpd_Hpd_Wpd)
2819{
2820 IEMOP_MNEMONIC3(VEX_RVM, VANDPD, vandpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2821 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2822 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2823}
2824
2825
2826/* Opcode VEX.F3.0F 0x54 - invalid */
2827/* Opcode VEX.F2.0F 0x54 - invalid */
2828
2829
2830/** Opcode VEX.0F 0x55 - vandnps Vps, Hps, Wps */
2831FNIEMOP_DEF(iemOp_vandnps_Vps_Hps_Wps)
2832{
2833 IEMOP_MNEMONIC3(VEX_RVM, VANDNPS, vandnps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2834 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2835 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2836}
2837
2838
2839/** Opcode VEX.66.0F 0x55 - vandnpd Vpd, Hpd, Wpd */
2840FNIEMOP_DEF(iemOp_vandnpd_Vpd_Hpd_Wpd)
2841{
2842 IEMOP_MNEMONIC3(VEX_RVM, VANDNPD, vandnpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2843 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2844 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2845}
2846
2847
2848/* Opcode VEX.F3.0F 0x55 - invalid */
2849/* Opcode VEX.F2.0F 0x55 - invalid */
2850
2851/** Opcode VEX.0F 0x56 - vorps Vps, Hps, Wps */
2852FNIEMOP_DEF(iemOp_vorps_Vps_Hps_Wps)
2853{
2854 IEMOP_MNEMONIC3(VEX_RVM, VORPS, vorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2855 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2856 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2857}
2858
2859
2860/** Opcode VEX.66.0F 0x56 - vorpd Vpd, Hpd, Wpd */
2861FNIEMOP_DEF(iemOp_vorpd_Vpd_Hpd_Wpd)
2862{
2863 IEMOP_MNEMONIC3(VEX_RVM, VORPD, vorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2864 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2865 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2866}
2867
2868
2869/* Opcode VEX.F3.0F 0x56 - invalid */
2870/* Opcode VEX.F2.0F 0x56 - invalid */
2871
2872
2873/** Opcode VEX.0F 0x57 - vxorps Vps, Hps, Wps */
2874FNIEMOP_DEF(iemOp_vxorps_Vps_Hps_Wps)
2875{
2876 IEMOP_MNEMONIC3(VEX_RVM, VXORPS, vxorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2877 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2878 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2879}
2880
2881
2882/** Opcode VEX.66.0F 0x57 - vxorpd Vpd, Hpd, Wpd */
2883FNIEMOP_DEF(iemOp_vxorpd_Vpd_Hpd_Wpd)
2884{
2885 IEMOP_MNEMONIC3(VEX_RVM, VXORPD, vxorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2886 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2887 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2888}
2889
2890
2891/* Opcode VEX.F3.0F 0x57 - invalid */
2892/* Opcode VEX.F2.0F 0x57 - invalid */
2893
2894
2895/** Opcode VEX.0F 0x58 - vaddps Vps, Hps, Wps */
2896FNIEMOP_DEF(iemOp_vaddps_Vps_Hps_Wps)
2897{
2898 IEMOP_MNEMONIC3(VEX_RVM, VADDPS, vaddps, Vps, Hps, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2899 IEMOPMEDIAF3_INIT_VARS( vaddps);
2900 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
2901}
2902
2903
2904/** Opcode VEX.66.0F 0x58 - vaddpd Vpd, Hpd, Wpd */
2905FNIEMOP_DEF(iemOp_vaddpd_Vpd_Hpd_Wpd)
2906{
2907 IEMOP_MNEMONIC3(VEX_RVM, VADDPD, vaddpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2908 IEMOPMEDIAF3_INIT_VARS( vaddpd);
2909 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
2910}
2911
2912
2913/** Opcode VEX.F3.0F 0x58 - vaddss Vss, Hss, Wss */
2914FNIEMOP_DEF(iemOp_vaddss_Vss_Hss_Wss)
2915{
2916 IEMOP_MNEMONIC3(VEX_RVM, VADDSS, vaddss, Vps, Hps, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2917 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R32,
2918 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback));
2919}
2920
2921
2922/** Opcode VEX.F2.0F 0x58 - vaddsd Vsd, Hsd, Wsd */
2923FNIEMOP_STUB(iemOp_vaddsd_Vsd_Hsd_Wsd);
2924
2925/** Opcode VEX.0F 0x59 - vmulps Vps, Hps, Wps */
2926FNIEMOP_STUB(iemOp_vmulps_Vps_Hps_Wps);
2927/** Opcode VEX.66.0F 0x59 - vmulpd Vpd, Hpd, Wpd */
2928FNIEMOP_STUB(iemOp_vmulpd_Vpd_Hpd_Wpd);
2929/** Opcode VEX.F3.0F 0x59 - vmulss Vss, Hss, Wss */
2930FNIEMOP_STUB(iemOp_vmulss_Vss_Hss_Wss);
2931/** Opcode VEX.F2.0F 0x59 - vmulsd Vsd, Hsd, Wsd */
2932FNIEMOP_STUB(iemOp_vmulsd_Vsd_Hsd_Wsd);
2933
2934/** Opcode VEX.0F 0x5a - vcvtps2pd Vpd, Wps */
2935FNIEMOP_STUB(iemOp_vcvtps2pd_Vpd_Wps);
2936/** Opcode VEX.66.0F 0x5a - vcvtpd2ps Vps, Wpd */
2937FNIEMOP_STUB(iemOp_vcvtpd2ps_Vps_Wpd);
2938/** Opcode VEX.F3.0F 0x5a - vcvtss2sd Vsd, Hx, Wss */
2939FNIEMOP_STUB(iemOp_vcvtss2sd_Vsd_Hx_Wss);
2940/** Opcode VEX.F2.0F 0x5a - vcvtsd2ss Vss, Hx, Wsd */
2941FNIEMOP_STUB(iemOp_vcvtsd2ss_Vss_Hx_Wsd);
2942
2943/** Opcode VEX.0F 0x5b - vcvtdq2ps Vps, Wdq */
2944FNIEMOP_STUB(iemOp_vcvtdq2ps_Vps_Wdq);
2945/** Opcode VEX.66.0F 0x5b - vcvtps2dq Vdq, Wps */
2946FNIEMOP_STUB(iemOp_vcvtps2dq_Vdq_Wps);
2947/** Opcode VEX.F3.0F 0x5b - vcvttps2dq Vdq, Wps */
2948FNIEMOP_STUB(iemOp_vcvttps2dq_Vdq_Wps);
2949/* Opcode VEX.F2.0F 0x5b - invalid */
2950
2951
2952/** Opcode VEX.0F 0x5c - vsubps Vps, Hps, Wps */
2953FNIEMOP_DEF(iemOp_vsubps_Vps_Hps_Wps)
2954{
2955 IEMOP_MNEMONIC3(VEX_RVM, VSUBPS, vsubps, Vps, Hps, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2956 IEMOPMEDIAF3_INIT_VARS( vsubps);
2957 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
2958}
2959
2960
2961/** Opcode VEX.66.0F 0x5c - vsubpd Vpd, Hpd, Wpd */
2962FNIEMOP_STUB(iemOp_vsubpd_Vpd_Hpd_Wpd);
2963/** Opcode VEX.F3.0F 0x5c - vsubss Vss, Hss, Wss */
2964FNIEMOP_STUB(iemOp_vsubss_Vss_Hss_Wss);
2965/** Opcode VEX.F2.0F 0x5c - vsubsd Vsd, Hsd, Wsd */
2966FNIEMOP_STUB(iemOp_vsubsd_Vsd_Hsd_Wsd);
2967
2968/** Opcode VEX.0F 0x5d - vminps Vps, Hps, Wps */
2969FNIEMOP_STUB(iemOp_vminps_Vps_Hps_Wps);
2970/** Opcode VEX.66.0F 0x5d - vminpd Vpd, Hpd, Wpd */
2971FNIEMOP_STUB(iemOp_vminpd_Vpd_Hpd_Wpd);
2972/** Opcode VEX.F3.0F 0x5d - vminss Vss, Hss, Wss */
2973FNIEMOP_STUB(iemOp_vminss_Vss_Hss_Wss);
2974/** Opcode VEX.F2.0F 0x5d - vminsd Vsd, Hsd, Wsd */
2975FNIEMOP_STUB(iemOp_vminsd_Vsd_Hsd_Wsd);
2976
2977/** Opcode VEX.0F 0x5e - vdivps Vps, Hps, Wps */
2978FNIEMOP_STUB(iemOp_vdivps_Vps_Hps_Wps);
2979/** Opcode VEX.66.0F 0x5e - vdivpd Vpd, Hpd, Wpd */
2980FNIEMOP_STUB(iemOp_vdivpd_Vpd_Hpd_Wpd);
2981/** Opcode VEX.F3.0F 0x5e - vdivss Vss, Hss, Wss */
2982FNIEMOP_STUB(iemOp_vdivss_Vss_Hss_Wss);
2983/** Opcode VEX.F2.0F 0x5e - vdivsd Vsd, Hsd, Wsd */
2984FNIEMOP_STUB(iemOp_vdivsd_Vsd_Hsd_Wsd);
2985
2986/** Opcode VEX.0F 0x5f - vmaxps Vps, Hps, Wps */
2987FNIEMOP_STUB(iemOp_vmaxps_Vps_Hps_Wps);
2988/** Opcode VEX.66.0F 0x5f - vmaxpd Vpd, Hpd, Wpd */
2989FNIEMOP_STUB(iemOp_vmaxpd_Vpd_Hpd_Wpd);
2990/** Opcode VEX.F3.0F 0x5f - vmaxss Vss, Hss, Wss */
2991FNIEMOP_STUB(iemOp_vmaxss_Vss_Hss_Wss);
2992/** Opcode VEX.F2.0F 0x5f - vmaxsd Vsd, Hsd, Wsd */
2993FNIEMOP_STUB(iemOp_vmaxsd_Vsd_Hsd_Wsd);
2994
2995
2996/* Opcode VEX.0F 0x60 - invalid */
2997
2998
2999/** Opcode VEX.66.0F 0x60 - vpunpcklbw Vx, Hx, Wx */
3000FNIEMOP_DEF(iemOp_vpunpcklbw_Vx_Hx_Wx)
3001{
3002 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLBW, vpunpcklbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3003 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklbw);
3004 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3005}
3006
3007
3008/* Opcode VEX.F3.0F 0x60 - invalid */
3009
3010
3011/* Opcode VEX.0F 0x61 - invalid */
3012
3013
3014/** Opcode VEX.66.0F 0x61 - vpunpcklwd Vx, Hx, Wx */
3015FNIEMOP_DEF(iemOp_vpunpcklwd_Vx_Hx_Wx)
3016{
3017 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLWD, vpunpcklwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3018 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklwd);
3019 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3020}
3021
3022
3023/* Opcode VEX.F3.0F 0x61 - invalid */
3024
3025
3026/* Opcode VEX.0F 0x62 - invalid */
3027
3028/** Opcode VEX.66.0F 0x62 - vpunpckldq Vx, Hx, Wx */
3029FNIEMOP_DEF(iemOp_vpunpckldq_Vx_Hx_Wx)
3030{
3031 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLDQ, vpunpckldq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3032 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckldq);
3033 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3034}
3035
3036
3037/* Opcode VEX.F3.0F 0x62 - invalid */
3038
3039
3040
3041/* Opcode VEX.0F 0x63 - invalid */
3042
3043
3044/** Opcode VEX.66.0F 0x63 - vpacksswb Vx, Hx, Wx */
3045FNIEMOP_DEF(iemOp_vpacksswb_Vx_Hx_Wx)
3046{
3047 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSWB, vpacksswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3048 IEMOPMEDIAOPTF3_INIT_VARS( vpacksswb);
3049 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3050}
3051
3052
3053/* Opcode VEX.F3.0F 0x63 - invalid */
3054
3055/* Opcode VEX.0F 0x64 - invalid */
3056
3057
3058/** Opcode VEX.66.0F 0x64 - vpcmpgtb Vx, Hx, Wx */
3059FNIEMOP_DEF(iemOp_vpcmpgtb_Vx_Hx_Wx)
3060{
3061 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTB, vpcmpgtb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3062 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpgtb);
3063 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3064}
3065
3066
3067/* Opcode VEX.F3.0F 0x64 - invalid */
3068
3069/* Opcode VEX.0F 0x65 - invalid */
3070
3071
3072/** Opcode VEX.66.0F 0x65 - vpcmpgtw Vx, Hx, Wx */
3073FNIEMOP_DEF(iemOp_vpcmpgtw_Vx_Hx_Wx)
3074{
3075 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTW, vpcmpgtw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3076 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpgtw);
3077 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3078}
3079
3080
3081/* Opcode VEX.F3.0F 0x65 - invalid */
3082
3083/* Opcode VEX.0F 0x66 - invalid */
3084
3085
3086/** Opcode VEX.66.0F 0x66 - vpcmpgtd Vx, Hx, Wx */
3087FNIEMOP_DEF(iemOp_vpcmpgtd_Vx_Hx_Wx)
3088{
3089 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTD, vpcmpgtd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3090 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpgtd);
3091 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3092}
3093
3094
3095/* Opcode VEX.F3.0F 0x66 - invalid */
3096
3097/* Opcode VEX.0F 0x67 - invalid */
3098
3099
3100/** Opcode VEX.66.0F 0x67 - vpackuswb Vx, Hx, W */
3101FNIEMOP_DEF(iemOp_vpackuswb_Vx_Hx_W)
3102{
3103 IEMOP_MNEMONIC3(VEX_RVM, VPACKUSWB, vpackuswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3104 IEMOPMEDIAOPTF3_INIT_VARS( vpackuswb);
3105 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3106}
3107
3108
3109/* Opcode VEX.F3.0F 0x67 - invalid */
3110
3111
3112///**
3113// * Common worker for SSE2 instructions on the form:
3114// * pxxxx xmm1, xmm2/mem128
3115// *
3116// * The 2nd operand is the second half of a register, which in the memory case
3117// * means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
3118// * where it may read the full 128 bits or only the upper 64 bits.
3119// *
3120// * Exceptions type 4.
3121// */
3122//FNIEMOP_DEF_1(iemOpCommonSse_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
3123//{
3124// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3125// if (IEM_IS_MODRM_REG_MODE(bRm))
3126// {
3127// /*
3128// * Register, register.
3129// */
3130// IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3131// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
3132// IEM_MC_ARG(PRTUINT128U, pDst, 0);
3133// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
3134// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
3135// IEM_MC_PREPARE_SSE_USAGE();
3136// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3137// IEM_MC_REF_XREG_U128_CONST(pSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3138// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3139// IEM_MC_ADVANCE_RIP_AND_FINISH();
3140// IEM_MC_END();
3141// }
3142// else
3143// {
3144// /*
3145// * Register, memory.
3146// */
3147// IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3148// IEM_MC_ARG(PRTUINT128U, pDst, 0);
3149// IEM_MC_LOCAL(RTUINT128U, uSrc);
3150// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
3151// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3152//
3153// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3154// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
3155// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
3156// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */
3157//
3158// IEM_MC_PREPARE_SSE_USAGE();
3159// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3160// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3161//
3162// IEM_MC_ADVANCE_RIP_AND_FINISH();
3163// IEM_MC_END();
3164// }
3165// return VINF_SUCCESS;
3166//}
3167
3168
3169/* Opcode VEX.0F 0x68 - invalid */
3170
3171/** Opcode VEX.66.0F 0x68 - vpunpckhbw Vx, Hx, Wx */
3172FNIEMOP_DEF(iemOp_vpunpckhbw_Vx_Hx_Wx)
3173{
3174 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHBW, vpunpckhbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3175 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhbw);
3176 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3177}
3178
3179
3180/* Opcode VEX.F3.0F 0x68 - invalid */
3181
3182
3183/* Opcode VEX.0F 0x69 - invalid */
3184
3185
3186/** Opcode VEX.66.0F 0x69 - vpunpckhwd Vx, Hx, Wx */
3187FNIEMOP_DEF(iemOp_vpunpckhwd_Vx_Hx_Wx)
3188{
3189 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHWD, vpunpckhwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3190 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhwd);
3191 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3192}
3193
3194
3195/* Opcode VEX.F3.0F 0x69 - invalid */
3196
3197
3198/* Opcode VEX.0F 0x6a - invalid */
3199
3200
3201/** Opcode VEX.66.0F 0x6a - vpunpckhdq Vx, Hx, W */
3202FNIEMOP_DEF(iemOp_vpunpckhdq_Vx_Hx_W)
3203{
3204 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHDQ, vpunpckhdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3205 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhdq);
3206 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3207}
3208
3209
3210/* Opcode VEX.F3.0F 0x6a - invalid */
3211
3212
3213/* Opcode VEX.0F 0x6b - invalid */
3214
3215
3216/** Opcode VEX.66.0F 0x6b - vpackssdw Vx, Hx, Wx */
3217FNIEMOP_DEF(iemOp_vpackssdw_Vx_Hx_Wx)
3218{
3219 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSDW, vpackssdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3220 IEMOPMEDIAOPTF3_INIT_VARS( vpackssdw);
3221 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3222}
3223
3224
3225/* Opcode VEX.F3.0F 0x6b - invalid */
3226
3227
3228/* Opcode VEX.0F 0x6c - invalid */
3229
3230
3231/** Opcode VEX.66.0F 0x6c - vpunpcklqdq Vx, Hx, Wx */
3232FNIEMOP_DEF(iemOp_vpunpcklqdq_Vx_Hx_Wx)
3233{
3234 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLQDQ, vpunpcklqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3235 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklqdq);
3236 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3237}
3238
3239
3240/* Opcode VEX.F3.0F 0x6c - invalid */
3241/* Opcode VEX.F2.0F 0x6c - invalid */
3242
3243
3244/* Opcode VEX.0F 0x6d - invalid */
3245
3246
3247/** Opcode VEX.66.0F 0x6d - vpunpckhqdq Vx, Hx, W */
3248FNIEMOP_DEF(iemOp_vpunpckhqdq_Vx_Hx_W)
3249{
3250 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHQDQ, vpunpckhqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3251 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhqdq);
3252 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3253}
3254
3255
3256/* Opcode VEX.F3.0F 0x6d - invalid */
3257
3258
3259/* Opcode VEX.0F 0x6e - invalid */
3260
3261FNIEMOP_DEF(iemOp_vmovd_q_Vy_Ey)
3262{
3263 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3264 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3265 {
3266 /**
3267 * @opcode 0x6e
3268 * @opcodesub rex.w=1
3269 * @oppfx 0x66
3270 * @opcpuid avx
3271 * @opgroup og_avx_simdint_datamov
3272 * @opxcpttype 5
3273 * @optest 64-bit / op1=1 op2=2 -> op1=2
3274 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
3275 */
3276 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Eq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3277 if (IEM_IS_MODRM_REG_MODE(bRm))
3278 {
3279 /* XMM, greg64 */
3280 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3281 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3282 IEM_MC_LOCAL(uint64_t, u64Tmp);
3283
3284 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3285 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3286
3287 IEM_MC_FETCH_GREG_U64(u64Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
3288 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
3289
3290 IEM_MC_ADVANCE_RIP_AND_FINISH();
3291 IEM_MC_END();
3292 }
3293 else
3294 {
3295 /* XMM, [mem64] */
3296 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3297 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3298 IEM_MC_LOCAL(uint64_t, u64Tmp);
3299
3300 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3301 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3302 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3303 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3304
3305 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3306 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
3307
3308 IEM_MC_ADVANCE_RIP_AND_FINISH();
3309 IEM_MC_END();
3310 }
3311 }
3312 else
3313 {
3314 /**
3315 * @opdone
3316 * @opcode 0x6e
3317 * @opcodesub rex.w=0
3318 * @oppfx 0x66
3319 * @opcpuid avx
3320 * @opgroup og_avx_simdint_datamov
3321 * @opxcpttype 5
3322 * @opfunction iemOp_vmovd_q_Vy_Ey
3323 * @optest op1=1 op2=2 -> op1=2
3324 * @optest op1=0 op2=-42 -> op1=-42
3325 */
3326 IEMOP_MNEMONIC2(VEX_RM, VMOVD, vmovd, Vd_WO, Ed, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3327 if (IEM_IS_MODRM_REG_MODE(bRm))
3328 {
3329 /* XMM, greg32 */
3330 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3331 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3332 IEM_MC_LOCAL(uint32_t, u32Tmp);
3333
3334 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3335 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3336
3337 IEM_MC_FETCH_GREG_U32(u32Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
3338 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
3339
3340 IEM_MC_ADVANCE_RIP_AND_FINISH();
3341 IEM_MC_END();
3342 }
3343 else
3344 {
3345 /* XMM, [mem32] */
3346 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3347 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3348 IEM_MC_LOCAL(uint32_t, u32Tmp);
3349
3350 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3351 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3352 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3353 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3354
3355 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3356 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
3357
3358 IEM_MC_ADVANCE_RIP_AND_FINISH();
3359 IEM_MC_END();
3360 }
3361 }
3362}
3363
3364
3365/* Opcode VEX.F3.0F 0x6e - invalid */
3366
3367
3368/* Opcode VEX.0F 0x6f - invalid */
3369
3370/**
3371 * @opcode 0x6f
3372 * @oppfx 0x66
3373 * @opcpuid avx
3374 * @opgroup og_avx_simdint_datamove
3375 * @opxcpttype 1
3376 * @optest op1=1 op2=2 -> op1=2
3377 * @optest op1=0 op2=-42 -> op1=-42
3378 */
3379FNIEMOP_DEF(iemOp_vmovdqa_Vx_Wx)
3380{
3381 IEMOP_MNEMONIC2(VEX_RM, VMOVDQA, vmovdqa, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3382 Assert(pVCpu->iem.s.uVexLength <= 1);
3383 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3384 if (IEM_IS_MODRM_REG_MODE(bRm))
3385 {
3386 /*
3387 * Register, register.
3388 */
3389 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3390 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3391
3392 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3393 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3394 if (pVCpu->iem.s.uVexLength == 0)
3395 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3396 IEM_GET_MODRM_RM(pVCpu, bRm));
3397 else
3398 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3399 IEM_GET_MODRM_RM(pVCpu, bRm));
3400 IEM_MC_ADVANCE_RIP_AND_FINISH();
3401 IEM_MC_END();
3402 }
3403 else if (pVCpu->iem.s.uVexLength == 0)
3404 {
3405 /*
3406 * Register, memory128.
3407 */
3408 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3409 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3410 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3411
3412 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3413 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3414 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3415 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3416
3417 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3418 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
3419
3420 IEM_MC_ADVANCE_RIP_AND_FINISH();
3421 IEM_MC_END();
3422 }
3423 else
3424 {
3425 /*
3426 * Register, memory256.
3427 */
3428 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3429 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3430 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3431
3432 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3433 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3434 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3435 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3436
3437 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3438 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
3439
3440 IEM_MC_ADVANCE_RIP_AND_FINISH();
3441 IEM_MC_END();
3442 }
3443}
3444
3445/**
3446 * @opcode 0x6f
3447 * @oppfx 0xf3
3448 * @opcpuid avx
3449 * @opgroup og_avx_simdint_datamove
3450 * @opxcpttype 4UA
3451 * @optest op1=1 op2=2 -> op1=2
3452 * @optest op1=0 op2=-42 -> op1=-42
3453 */
3454FNIEMOP_DEF(iemOp_vmovdqu_Vx_Wx)
3455{
3456 IEMOP_MNEMONIC2(VEX_RM, VMOVDQU, vmovdqu, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3457 Assert(pVCpu->iem.s.uVexLength <= 1);
3458 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3459 if (IEM_IS_MODRM_REG_MODE(bRm))
3460 {
3461 /*
3462 * Register, register.
3463 */
3464 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3465 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3466
3467 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3468 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3469 if (pVCpu->iem.s.uVexLength == 0)
3470 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3471 IEM_GET_MODRM_RM(pVCpu, bRm));
3472 else
3473 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3474 IEM_GET_MODRM_RM(pVCpu, bRm));
3475 IEM_MC_ADVANCE_RIP_AND_FINISH();
3476 IEM_MC_END();
3477 }
3478 else if (pVCpu->iem.s.uVexLength == 0)
3479 {
3480 /*
3481 * Register, memory128.
3482 */
3483 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3484 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3485 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3486
3487 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3488 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3489 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3490 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3491
3492 IEM_MC_FETCH_MEM_U128_NO_AC(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3493 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
3494
3495 IEM_MC_ADVANCE_RIP_AND_FINISH();
3496 IEM_MC_END();
3497 }
3498 else
3499 {
3500 /*
3501 * Register, memory256.
3502 */
3503 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3504 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3505 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3506
3507 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3508 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3509 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3510 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3511
3512 IEM_MC_FETCH_MEM_U256_NO_AC(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3513 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
3514
3515 IEM_MC_ADVANCE_RIP_AND_FINISH();
3516 IEM_MC_END();
3517 }
3518}
3519
3520
3521/* Opcode VEX.0F 0x70 - invalid */
3522
3523
3524/**
3525 * Common worker for AVX/AVX2 instructions on the forms:
3526 * - vpxxx xmm0, xmm2/mem128, imm8
3527 * - vpxxx ymm0, ymm2/mem256, imm8
3528 *
3529 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
3530 */
3531FNIEMOP_DEF_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, PFNIEMAIMPLMEDIAPSHUFU128, pfnU128, PFNIEMAIMPLMEDIAPSHUFU256, pfnU256)
3532{
3533 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3534 if (IEM_IS_MODRM_REG_MODE(bRm))
3535 {
3536 /*
3537 * Register, register.
3538 */
3539 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3540 if (pVCpu->iem.s.uVexLength)
3541 {
3542 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3543 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3544 IEM_MC_LOCAL(RTUINT256U, uDst);
3545 IEM_MC_LOCAL(RTUINT256U, uSrc);
3546 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3547 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3548 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3549 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3550 IEM_MC_PREPARE_AVX_USAGE();
3551 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3552 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg);
3553 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3554 IEM_MC_ADVANCE_RIP_AND_FINISH();
3555 IEM_MC_END();
3556 }
3557 else
3558 {
3559 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3560 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3561 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3562 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
3563 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3564 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3565 IEM_MC_PREPARE_AVX_USAGE();
3566 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3567 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3568 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
3569 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3570 IEM_MC_ADVANCE_RIP_AND_FINISH();
3571 IEM_MC_END();
3572 }
3573 }
3574 else
3575 {
3576 /*
3577 * Register, memory.
3578 */
3579 if (pVCpu->iem.s.uVexLength)
3580 {
3581 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3582 IEM_MC_LOCAL(RTUINT256U, uDst);
3583 IEM_MC_LOCAL(RTUINT256U, uSrc);
3584 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3585 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3586 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3587
3588 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
3589 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3590 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3591 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3592 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3593 IEM_MC_PREPARE_AVX_USAGE();
3594
3595 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3596 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg);
3597 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3598
3599 IEM_MC_ADVANCE_RIP_AND_FINISH();
3600 IEM_MC_END();
3601 }
3602 else
3603 {
3604 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3605 IEM_MC_LOCAL(RTUINT128U, uSrc);
3606 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3607 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3608 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
3609
3610 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
3611 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3612 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3613 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3614 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3615 IEM_MC_PREPARE_AVX_USAGE();
3616
3617 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3618 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3619 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
3620 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3621
3622 IEM_MC_ADVANCE_RIP_AND_FINISH();
3623 IEM_MC_END();
3624 }
3625 }
3626}
3627
3628
3629/** Opcode VEX.66.0F 0x70 - vpshufd Vx, Wx, Ib */
3630FNIEMOP_DEF(iemOp_vpshufd_Vx_Wx_Ib)
3631{
3632 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFD, vpshufd, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3633 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufd_u128,
3634 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufd_u256, iemAImpl_vpshufd_u256_fallback));
3635
3636}
3637
3638
3639/** Opcode VEX.F3.0F 0x70 - vpshufhw Vx, Wx, Ib */
3640FNIEMOP_DEF(iemOp_vpshufhw_Vx_Wx_Ib)
3641{
3642 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFHW, vpshufhw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3643 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufhw_u128,
3644 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufhw_u256, iemAImpl_vpshufhw_u256_fallback));
3645
3646}
3647
3648
3649/** Opcode VEX.F2.0F 0x70 - vpshuflw Vx, Wx, Ib */
3650FNIEMOP_DEF(iemOp_vpshuflw_Vx_Wx_Ib)
3651{
3652 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFLW, vpshuflw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3653 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshuflw_u128,
3654 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshuflw_u256, iemAImpl_vpshuflw_u256_fallback));
3655}
3656
3657
3658/**
3659 * Common worker(s) for AVX/AVX2 instructions on the forms:
3660 * - vpxxx xmm0, xmm2, imm8
3661 * - vpxxx ymm0, ymm2, imm8
3662 *
3663 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
3664 */
3665FNIEMOP_DEF_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, uint8_t, bRm, PFNIEMAIMPLMEDIAPSHUFU128, pfnU128)
3666{
3667 if (IEM_IS_MODRM_REG_MODE(bRm))
3668 {
3669 /*
3670 * Register, register.
3671 */
3672 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3673 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3674 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
3675 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3676 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
3677 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3678 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3679 IEM_MC_PREPARE_AVX_USAGE();
3680 IEM_MC_REF_XREG_U128(puDst, IEM_GET_EFFECTIVE_VVVV(pVCpu));
3681 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3682 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
3683 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_EFFECTIVE_VVVV(pVCpu));
3684 IEM_MC_ADVANCE_RIP_AND_FINISH();
3685 IEM_MC_END();
3686 }
3687 /* No memory operand. */
3688 else
3689 IEMOP_RAISE_INVALID_OPCODE_RET();
3690}
3691
3692FNIEMOP_DEF_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, uint8_t, bRm, PFNIEMAIMPLMEDIAPSHUFU256, pfnU256)
3693{
3694 if (IEM_IS_MODRM_REG_MODE(bRm))
3695 {
3696 /*
3697 * Register, register.
3698 */
3699 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3700 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3701 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
3702 IEM_MC_LOCAL(RTUINT256U, uDst);
3703 IEM_MC_LOCAL(RTUINT256U, uSrc);
3704 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3705 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3706 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3707 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3708 IEM_MC_PREPARE_AVX_USAGE();
3709 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3710 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg);
3711 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_EFFECTIVE_VVVV(pVCpu), uDst);
3712 IEM_MC_ADVANCE_RIP_AND_FINISH();
3713 IEM_MC_END();
3714 }
3715 /* No memory operand. */
3716 else
3717 IEMOP_RAISE_INVALID_OPCODE_RET();
3718}
3719
3720
3721/* Opcode VEX.0F 0x71 11/2 - invalid. */
3722/** Opcode VEX.66.0F 0x71 11/2. */
3723FNIEMOP_DEF_1(iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, uint8_t, bRm)
3724{
3725 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLW, vpsrlw, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3726 if (pVCpu->iem.s.uVexLength)
3727 {
3728 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3729 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback));
3730 }
3731 else
3732 {
3733 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3734 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback));
3735 }
3736}
3737
3738
3739/* Opcode VEX.0F 0x71 11/4 - invalid */
3740/** Opcode VEX.66.0F 0x71 11/4. */
3741FNIEMOP_DEF_1(iemOp_VGrp12_vpsraw_Hx_Ux_Ib, uint8_t, bRm)
3742{
3743 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRAW, vpsraw, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3744 if (pVCpu->iem.s.uVexLength)
3745 {
3746 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3747 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback));
3748 }
3749 else
3750 {
3751 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3752 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback));
3753 }
3754}
3755
3756/* Opcode VEX.0F 0x71 11/6 - invalid */
3757
3758/** Opcode VEX.66.0F 0x71 11/6. */
3759FNIEMOP_DEF_1(iemOp_VGrp12_vpsllw_Hx_Ux_Ib, uint8_t, bRm)
3760{
3761 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSLLW, vpsllw, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3762 if (pVCpu->iem.s.uVexLength)
3763 {
3764 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3765 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback));
3766 }
3767 else
3768 {
3769 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3770 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback));
3771 }
3772}
3773
3774
3775/**
3776 * VEX Group 12 jump table for register variant.
3777 */
3778IEM_STATIC const PFNIEMOPRM g_apfnVexGroup12RegReg[] =
3779{
3780 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3781 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3782 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3783 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3784 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsraw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3785 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3786 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsllw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3787 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3788};
3789AssertCompile(RT_ELEMENTS(g_apfnVexGroup12RegReg) == 8*4);
3790
3791
3792/** Opcode VEX.0F 0x71. */
3793FNIEMOP_DEF(iemOp_VGrp12)
3794{
3795 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3796 if (IEM_IS_MODRM_REG_MODE(bRm))
3797 /* register, register */
3798 return FNIEMOP_CALL_1(g_apfnVexGroup12RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3799 + pVCpu->iem.s.idxPrefix], bRm);
3800 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3801}
3802
3803
3804/* Opcode VEX.0F 0x72 11/2 - invalid. */
3805/** Opcode VEX.66.0F 0x72 11/2. */
3806FNIEMOP_DEF_1(iemOp_VGrp13_vpsrld_Hx_Ux_Ib, uint8_t, bRm)
3807{
3808 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLD, vpsrld, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3809 if (pVCpu->iem.s.uVexLength)
3810 {
3811 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3812 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback));
3813 }
3814 else
3815 {
3816 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3817 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback));
3818 }
3819}
3820
3821
3822/* Opcode VEX.0F 0x72 11/4 - invalid. */
3823/** Opcode VEX.66.0F 0x72 11/4. */
3824FNIEMOP_DEF_1(iemOp_VGrp13_vpsrad_Hx_Ux_Ib, uint8_t, bRm)
3825{
3826 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRAD, vpsrad, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3827 if (pVCpu->iem.s.uVexLength)
3828 {
3829 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3830 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback));
3831 }
3832 else
3833 {
3834 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3835 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback));
3836 }
3837}
3838
3839/* Opcode VEX.0F 0x72 11/6 - invalid. */
3840
3841/** Opcode VEX.66.0F 0x72 11/6. */
3842FNIEMOP_DEF_1(iemOp_VGrp13_vpslld_Hx_Ux_Ib, uint8_t, bRm)
3843{
3844 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSLLD, vpslld, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3845 if (pVCpu->iem.s.uVexLength)
3846 {
3847 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3848 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback));
3849 }
3850 else
3851 {
3852 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3853 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback));
3854 }
3855}
3856
3857
3858/**
3859 * Group 13 jump table for register variant.
3860 */
3861IEM_STATIC const PFNIEMOPRM g_apfnVexGroup13RegReg[] =
3862{
3863 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3864 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3865 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3866 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3867 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrad_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3868 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3869 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpslld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3870 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3871};
3872AssertCompile(RT_ELEMENTS(g_apfnVexGroup13RegReg) == 8*4);
3873
3874/** Opcode VEX.0F 0x72. */
3875FNIEMOP_DEF(iemOp_VGrp13)
3876{
3877 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3878 if (IEM_IS_MODRM_REG_MODE(bRm))
3879 /* register, register */
3880 return FNIEMOP_CALL_1(g_apfnVexGroup13RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3881 + pVCpu->iem.s.idxPrefix], bRm);
3882 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3883}
3884
3885
3886/* Opcode VEX.0F 0x73 11/2 - invalid. */
3887/** Opcode VEX.66.0F 0x73 11/2. */
3888FNIEMOP_DEF_1(iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, uint8_t, bRm)
3889{
3890 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLQ, vpsrlq, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3891 if (pVCpu->iem.s.uVexLength)
3892 {
3893 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3894 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback));
3895 }
3896 else
3897 {
3898 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3899 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback));
3900 }
3901}
3902
3903
3904/** Opcode VEX.66.0F 0x73 11/3. */
3905FNIEMOP_DEF_1(iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, uint8_t, bRm)
3906{
3907 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLDQ, vpsrldq, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3908 if (pVCpu->iem.s.uVexLength)
3909 {
3910 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3911 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrldq_imm_u256, iemAImpl_vpsrldq_imm_u256_fallback));
3912 }
3913 else
3914 {
3915 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3916 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrldq_imm_u128, iemAImpl_vpsrldq_imm_u128_fallback));
3917 }
3918}
3919
3920/* Opcode VEX.0F 0x73 11/6 - invalid. */
3921
3922/** Opcode VEX.66.0F 0x73 11/6. */
3923FNIEMOP_DEF_1(iemOp_VGrp14_vpsllq_Hx_Ux_Ib, uint8_t, bRm)
3924{
3925 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSLLQ, vpsllq, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3926 if (pVCpu->iem.s.uVexLength)
3927 {
3928 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3929 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback));
3930 }
3931 else
3932 {
3933 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3934 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback));
3935 }
3936}
3937
3938/** Opcode VEX.66.0F 0x73 11/7. */
3939FNIEMOP_DEF_1(iemOp_VGrp14_vpslldq_Hx_Ux_Ib, uint8_t, bRm)
3940{
3941 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSLLDQ, vpslldq, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3942 if (pVCpu->iem.s.uVexLength)
3943 {
3944 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3945 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpslldq_imm_u256, iemAImpl_vpslldq_imm_u256_fallback));
3946 }
3947 else
3948 {
3949 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3950 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpslldq_imm_u128, iemAImpl_vpslldq_imm_u128_fallback));
3951 }
3952}
3953
3954/* Opcode VEX.0F 0x73 11/6 - invalid. */
3955
3956/**
3957 * Group 14 jump table for register variant.
3958 */
3959IEM_STATIC const PFNIEMOPRM g_apfnVexGroup14RegReg[] =
3960{
3961 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3962 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3963 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3964 /* /3 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3965 /* /4 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3966 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3967 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsllq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3968 /* /7 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpslldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3969};
3970AssertCompile(RT_ELEMENTS(g_apfnVexGroup14RegReg) == 8*4);
3971
3972
3973/** Opcode VEX.0F 0x73. */
3974FNIEMOP_DEF(iemOp_VGrp14)
3975{
3976 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3977 if (IEM_IS_MODRM_REG_MODE(bRm))
3978 /* register, register */
3979 return FNIEMOP_CALL_1(g_apfnVexGroup14RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3980 + pVCpu->iem.s.idxPrefix], bRm);
3981 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3982}
3983
3984
3985/* Opcode VEX.0F 0x74 - invalid */
3986
3987
3988/** Opcode VEX.66.0F 0x74 - vpcmpeqb Vx, Hx, Wx */
3989FNIEMOP_DEF(iemOp_vpcmpeqb_Vx_Hx_Wx)
3990{
3991 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQB, vpcmpeqb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3992 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpeqb);
3993 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3994}
3995
3996/* Opcode VEX.F3.0F 0x74 - invalid */
3997/* Opcode VEX.F2.0F 0x74 - invalid */
3998
3999
4000/* Opcode VEX.0F 0x75 - invalid */
4001
4002
4003/** Opcode VEX.66.0F 0x75 - vpcmpeqw Vx, Hx, Wx */
4004FNIEMOP_DEF(iemOp_vpcmpeqw_Vx_Hx_Wx)
4005{
4006 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQW, vpcmpeqw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4007 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpeqw);
4008 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4009}
4010
4011
4012/* Opcode VEX.F3.0F 0x75 - invalid */
4013/* Opcode VEX.F2.0F 0x75 - invalid */
4014
4015
4016/* Opcode VEX.0F 0x76 - invalid */
4017
4018
4019/** Opcode VEX.66.0F 0x76 - vpcmpeqd Vx, Hx, Wx */
4020FNIEMOP_DEF(iemOp_vpcmpeqd_Vx_Hx_Wx)
4021{
4022 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQD, vpcmpeqd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4023 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpeqd);
4024 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4025}
4026
4027
4028/* Opcode VEX.F3.0F 0x76 - invalid */
4029/* Opcode VEX.F2.0F 0x76 - invalid */
4030
4031
4032/** Opcode VEX.0F 0x77 - vzeroupperv vzeroallv */
4033FNIEMOP_DEF(iemOp_vzeroupperv__vzeroallv)
4034{
4035 Assert(pVCpu->iem.s.uVexLength <= 1);
4036 if (pVCpu->iem.s.uVexLength == 0)
4037 {
4038 /*
4039 * 128-bit: vzeroupper
4040 */
4041 IEMOP_MNEMONIC(vzeroupper, "vzeroupper");
4042 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4043
4044 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4045 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4046 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4047
4048 IEM_MC_CLEAR_YREG_128_UP(0);
4049 IEM_MC_CLEAR_YREG_128_UP(1);
4050 IEM_MC_CLEAR_YREG_128_UP(2);
4051 IEM_MC_CLEAR_YREG_128_UP(3);
4052 IEM_MC_CLEAR_YREG_128_UP(4);
4053 IEM_MC_CLEAR_YREG_128_UP(5);
4054 IEM_MC_CLEAR_YREG_128_UP(6);
4055 IEM_MC_CLEAR_YREG_128_UP(7);
4056
4057 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4058 {
4059 IEM_MC_CLEAR_YREG_128_UP( 8);
4060 IEM_MC_CLEAR_YREG_128_UP( 9);
4061 IEM_MC_CLEAR_YREG_128_UP(10);
4062 IEM_MC_CLEAR_YREG_128_UP(11);
4063 IEM_MC_CLEAR_YREG_128_UP(12);
4064 IEM_MC_CLEAR_YREG_128_UP(13);
4065 IEM_MC_CLEAR_YREG_128_UP(14);
4066 IEM_MC_CLEAR_YREG_128_UP(15);
4067 }
4068
4069 IEM_MC_ADVANCE_RIP_AND_FINISH();
4070 IEM_MC_END();
4071 }
4072 else
4073 {
4074 /*
4075 * 256-bit: vzeroall
4076 */
4077 IEMOP_MNEMONIC(vzeroall, "vzeroall");
4078 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4079
4080 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4081 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4082 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4083
4084 IEM_MC_LOCAL_CONST(uint32_t, uZero, 0);
4085 IEM_MC_STORE_YREG_U32_ZX_VLMAX(0, uZero);
4086 IEM_MC_STORE_YREG_U32_ZX_VLMAX(1, uZero);
4087 IEM_MC_STORE_YREG_U32_ZX_VLMAX(2, uZero);
4088 IEM_MC_STORE_YREG_U32_ZX_VLMAX(3, uZero);
4089 IEM_MC_STORE_YREG_U32_ZX_VLMAX(4, uZero);
4090 IEM_MC_STORE_YREG_U32_ZX_VLMAX(5, uZero);
4091 IEM_MC_STORE_YREG_U32_ZX_VLMAX(6, uZero);
4092 IEM_MC_STORE_YREG_U32_ZX_VLMAX(7, uZero);
4093
4094 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4095 {
4096 IEM_MC_STORE_YREG_U32_ZX_VLMAX( 8, uZero);
4097 IEM_MC_STORE_YREG_U32_ZX_VLMAX( 9, uZero);
4098 IEM_MC_STORE_YREG_U32_ZX_VLMAX(10, uZero);
4099 IEM_MC_STORE_YREG_U32_ZX_VLMAX(11, uZero);
4100 IEM_MC_STORE_YREG_U32_ZX_VLMAX(12, uZero);
4101 IEM_MC_STORE_YREG_U32_ZX_VLMAX(13, uZero);
4102 IEM_MC_STORE_YREG_U32_ZX_VLMAX(14, uZero);
4103 IEM_MC_STORE_YREG_U32_ZX_VLMAX(15, uZero);
4104 }
4105
4106 IEM_MC_ADVANCE_RIP_AND_FINISH();
4107 IEM_MC_END();
4108 }
4109}
4110
4111
4112/* Opcode VEX.66.0F 0x77 - invalid */
4113/* Opcode VEX.F3.0F 0x77 - invalid */
4114/* Opcode VEX.F2.0F 0x77 - invalid */
4115
4116/* Opcode VEX.0F 0x78 - invalid */
4117/* Opcode VEX.66.0F 0x78 - invalid */
4118/* Opcode VEX.F3.0F 0x78 - invalid */
4119/* Opcode VEX.F2.0F 0x78 - invalid */
4120
4121/* Opcode VEX.0F 0x79 - invalid */
4122/* Opcode VEX.66.0F 0x79 - invalid */
4123/* Opcode VEX.F3.0F 0x79 - invalid */
4124/* Opcode VEX.F2.0F 0x79 - invalid */
4125
4126/* Opcode VEX.0F 0x7a - invalid */
4127/* Opcode VEX.66.0F 0x7a - invalid */
4128/* Opcode VEX.F3.0F 0x7a - invalid */
4129/* Opcode VEX.F2.0F 0x7a - invalid */
4130
4131/* Opcode VEX.0F 0x7b - invalid */
4132/* Opcode VEX.66.0F 0x7b - invalid */
4133/* Opcode VEX.F3.0F 0x7b - invalid */
4134/* Opcode VEX.F2.0F 0x7b - invalid */
4135
4136/* Opcode VEX.0F 0x7c - invalid */
4137/** Opcode VEX.66.0F 0x7c - vhaddpd Vpd, Hpd, Wpd */
4138FNIEMOP_STUB(iemOp_vhaddpd_Vpd_Hpd_Wpd);
4139/* Opcode VEX.F3.0F 0x7c - invalid */
4140
4141
4142/** Opcode VEX.F2.0F 0x7c - vhaddps Vps, Hps, Wps */
4143FNIEMOP_DEF(iemOp_vhaddps_Vps_Hps_Wps)
4144{
4145 IEMOP_MNEMONIC3(VEX_RVM, VHADDPS, vhaddps, Vps, Hps, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4146 IEMOPMEDIAF3_INIT_VARS( vhaddps);
4147 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
4148}
4149
4150
4151/* Opcode VEX.0F 0x7d - invalid */
4152/** Opcode VEX.66.0F 0x7d - vhsubpd Vpd, Hpd, Wpd */
4153FNIEMOP_STUB(iemOp_vhsubpd_Vpd_Hpd_Wpd);
4154/* Opcode VEX.F3.0F 0x7d - invalid */
4155/** Opcode VEX.F2.0F 0x7d - vhsubps Vps, Hps, Wps */
4156FNIEMOP_STUB(iemOp_vhsubps_Vps_Hps_Wps);
4157
4158
4159/* Opcode VEX.0F 0x7e - invalid */
4160
4161FNIEMOP_DEF(iemOp_vmovd_q_Ey_Vy)
4162{
4163 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4164 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
4165 {
4166 /**
4167 * @opcode 0x7e
4168 * @opcodesub rex.w=1
4169 * @oppfx 0x66
4170 * @opcpuid avx
4171 * @opgroup og_avx_simdint_datamov
4172 * @opxcpttype 5
4173 * @optest 64-bit / op1=1 op2=2 -> op1=2
4174 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
4175 */
4176 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Eq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
4177 if (IEM_IS_MODRM_REG_MODE(bRm))
4178 {
4179 /* greg64, XMM */
4180 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
4181 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4182 IEM_MC_LOCAL(uint64_t, u64Tmp);
4183
4184 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4185 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4186
4187 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
4188 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Tmp);
4189
4190 IEM_MC_ADVANCE_RIP_AND_FINISH();
4191 IEM_MC_END();
4192 }
4193 else
4194 {
4195 /* [mem64], XMM */
4196 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
4197 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4198 IEM_MC_LOCAL(uint64_t, u64Tmp);
4199
4200 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4201 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4202 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4203 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4204
4205 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
4206 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
4207
4208 IEM_MC_ADVANCE_RIP_AND_FINISH();
4209 IEM_MC_END();
4210 }
4211 }
4212 else
4213 {
4214 /**
4215 * @opdone
4216 * @opcode 0x7e
4217 * @opcodesub rex.w=0
4218 * @oppfx 0x66
4219 * @opcpuid avx
4220 * @opgroup og_avx_simdint_datamov
4221 * @opxcpttype 5
4222 * @opfunction iemOp_vmovd_q_Vy_Ey
4223 * @optest op1=1 op2=2 -> op1=2
4224 * @optest op1=0 op2=-42 -> op1=-42
4225 */
4226 IEMOP_MNEMONIC2(VEX_MR, VMOVD, vmovd, Ed_WO, Vd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
4227 if (IEM_IS_MODRM_REG_MODE(bRm))
4228 {
4229 /* greg32, XMM */
4230 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4231 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4232 IEM_MC_LOCAL(uint32_t, u32Tmp);
4233
4234 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4235 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4236
4237 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4238 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Tmp);
4239
4240 IEM_MC_ADVANCE_RIP_AND_FINISH();
4241 IEM_MC_END();
4242 }
4243 else
4244 {
4245 /* [mem32], XMM */
4246 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4247 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4248 IEM_MC_LOCAL(uint32_t, u32Tmp);
4249
4250 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4251 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4252 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4253 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4254
4255 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4256 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
4257
4258 IEM_MC_ADVANCE_RIP_AND_FINISH();
4259 IEM_MC_END();
4260 }
4261 }
4262}
4263
4264
4265/**
4266 * @opcode 0x7e
4267 * @oppfx 0xf3
4268 * @opcpuid avx
4269 * @opgroup og_avx_pcksclr_datamove
4270 * @opxcpttype none
4271 * @optest op1=1 op2=2 -> op1=2
4272 * @optest op1=0 op2=-42 -> op1=-42
4273 */
4274FNIEMOP_DEF(iemOp_vmovq_Vq_Wq)
4275{
4276 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
4277 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4278 if (IEM_IS_MODRM_REG_MODE(bRm))
4279 {
4280 /*
4281 * Register, register.
4282 */
4283 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4284 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4285
4286 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4287 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4288
4289 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
4290 IEM_GET_MODRM_RM(pVCpu, bRm));
4291 IEM_MC_ADVANCE_RIP_AND_FINISH();
4292 IEM_MC_END();
4293 }
4294 else
4295 {
4296 /*
4297 * Memory, register.
4298 */
4299 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4300 IEM_MC_LOCAL(uint64_t, uSrc);
4301 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4302
4303 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4304 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4305 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4306 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4307
4308 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4309 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
4310
4311 IEM_MC_ADVANCE_RIP_AND_FINISH();
4312 IEM_MC_END();
4313 }
4314
4315}
4316/* Opcode VEX.F2.0F 0x7e - invalid */
4317
4318
4319/* Opcode VEX.0F 0x7f - invalid */
4320
4321/**
4322 * @opcode 0x7f
4323 * @oppfx 0x66
4324 * @opcpuid avx
4325 * @opgroup og_avx_simdint_datamove
4326 * @opxcpttype 1
4327 * @optest op1=1 op2=2 -> op1=2
4328 * @optest op1=0 op2=-42 -> op1=-42
4329 */
4330FNIEMOP_DEF(iemOp_vmovdqa_Wx_Vx)
4331{
4332 IEMOP_MNEMONIC2(VEX_MR, VMOVDQA, vmovdqa, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4333 Assert(pVCpu->iem.s.uVexLength <= 1);
4334 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4335 if (IEM_IS_MODRM_REG_MODE(bRm))
4336 {
4337 /*
4338 * Register, register.
4339 */
4340 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4341 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4342
4343 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4344 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4345 if (pVCpu->iem.s.uVexLength == 0)
4346 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4347 IEM_GET_MODRM_REG(pVCpu, bRm));
4348 else
4349 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4350 IEM_GET_MODRM_REG(pVCpu, bRm));
4351 IEM_MC_ADVANCE_RIP_AND_FINISH();
4352 IEM_MC_END();
4353 }
4354 else if (pVCpu->iem.s.uVexLength == 0)
4355 {
4356 /*
4357 * Register, memory128.
4358 */
4359 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4360 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4361 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4362
4363 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4364 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4365 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4366 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4367
4368 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
4369 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
4370
4371 IEM_MC_ADVANCE_RIP_AND_FINISH();
4372 IEM_MC_END();
4373 }
4374 else
4375 {
4376 /*
4377 * Register, memory256.
4378 */
4379 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4380 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
4381 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4382
4383 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4384 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4385 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4386 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4387
4388 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4389 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
4390
4391 IEM_MC_ADVANCE_RIP_AND_FINISH();
4392 IEM_MC_END();
4393 }
4394}
4395
4396
4397/**
4398 * @opcode 0x7f
4399 * @oppfx 0xf3
4400 * @opcpuid avx
4401 * @opgroup og_avx_simdint_datamove
4402 * @opxcpttype 4UA
4403 * @optest op1=1 op2=2 -> op1=2
4404 * @optest op1=0 op2=-42 -> op1=-42
4405 */
4406FNIEMOP_DEF(iemOp_vmovdqu_Wx_Vx)
4407{
4408 IEMOP_MNEMONIC2(VEX_MR, VMOVDQU, vmovdqu, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4409 Assert(pVCpu->iem.s.uVexLength <= 1);
4410 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4411 if (IEM_IS_MODRM_REG_MODE(bRm))
4412 {
4413 /*
4414 * Register, register.
4415 */
4416 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4417 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4418
4419 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4420 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4421 if (pVCpu->iem.s.uVexLength == 0)
4422 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4423 IEM_GET_MODRM_REG(pVCpu, bRm));
4424 else
4425 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4426 IEM_GET_MODRM_REG(pVCpu, bRm));
4427 IEM_MC_ADVANCE_RIP_AND_FINISH();
4428 IEM_MC_END();
4429 }
4430 else if (pVCpu->iem.s.uVexLength == 0)
4431 {
4432 /*
4433 * Register, memory128.
4434 */
4435 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4436 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4437 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4438
4439 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4440 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4441 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4442 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4443
4444 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
4445 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
4446
4447 IEM_MC_ADVANCE_RIP_AND_FINISH();
4448 IEM_MC_END();
4449 }
4450 else
4451 {
4452 /*
4453 * Register, memory256.
4454 */
4455 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4456 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
4457 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4458
4459 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4460 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4461 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4462 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4463
4464 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4465 IEM_MC_STORE_MEM_U256_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
4466
4467 IEM_MC_ADVANCE_RIP_AND_FINISH();
4468 IEM_MC_END();
4469 }
4470}
4471
4472/* Opcode VEX.F2.0F 0x7f - invalid */
4473
4474
4475/* Opcode VEX.0F 0x80 - invalid */
4476/* Opcode VEX.0F 0x81 - invalid */
4477/* Opcode VEX.0F 0x82 - invalid */
4478/* Opcode VEX.0F 0x83 - invalid */
4479/* Opcode VEX.0F 0x84 - invalid */
4480/* Opcode VEX.0F 0x85 - invalid */
4481/* Opcode VEX.0F 0x86 - invalid */
4482/* Opcode VEX.0F 0x87 - invalid */
4483/* Opcode VEX.0F 0x88 - invalid */
4484/* Opcode VEX.0F 0x89 - invalid */
4485/* Opcode VEX.0F 0x8a - invalid */
4486/* Opcode VEX.0F 0x8b - invalid */
4487/* Opcode VEX.0F 0x8c - invalid */
4488/* Opcode VEX.0F 0x8d - invalid */
4489/* Opcode VEX.0F 0x8e - invalid */
4490/* Opcode VEX.0F 0x8f - invalid */
4491/* Opcode VEX.0F 0x90 - invalid */
4492/* Opcode VEX.0F 0x91 - invalid */
4493/* Opcode VEX.0F 0x92 - invalid */
4494/* Opcode VEX.0F 0x93 - invalid */
4495/* Opcode VEX.0F 0x94 - invalid */
4496/* Opcode VEX.0F 0x95 - invalid */
4497/* Opcode VEX.0F 0x96 - invalid */
4498/* Opcode VEX.0F 0x97 - invalid */
4499/* Opcode VEX.0F 0x98 - invalid */
4500/* Opcode VEX.0F 0x99 - invalid */
4501/* Opcode VEX.0F 0x9a - invalid */
4502/* Opcode VEX.0F 0x9b - invalid */
4503/* Opcode VEX.0F 0x9c - invalid */
4504/* Opcode VEX.0F 0x9d - invalid */
4505/* Opcode VEX.0F 0x9e - invalid */
4506/* Opcode VEX.0F 0x9f - invalid */
4507/* Opcode VEX.0F 0xa0 - invalid */
4508/* Opcode VEX.0F 0xa1 - invalid */
4509/* Opcode VEX.0F 0xa2 - invalid */
4510/* Opcode VEX.0F 0xa3 - invalid */
4511/* Opcode VEX.0F 0xa4 - invalid */
4512/* Opcode VEX.0F 0xa5 - invalid */
4513/* Opcode VEX.0F 0xa6 - invalid */
4514/* Opcode VEX.0F 0xa7 - invalid */
4515/* Opcode VEX.0F 0xa8 - invalid */
4516/* Opcode VEX.0F 0xa9 - invalid */
4517/* Opcode VEX.0F 0xaa - invalid */
4518/* Opcode VEX.0F 0xab - invalid */
4519/* Opcode VEX.0F 0xac - invalid */
4520/* Opcode VEX.0F 0xad - invalid */
4521
4522
4523/* Opcode VEX.0F 0xae mem/0 - invalid. */
4524/* Opcode VEX.0F 0xae mem/1 - invalid. */
4525
4526/**
4527 * @ opmaps grp15
4528 * @ opcode !11/2
4529 * @ oppfx none
4530 * @ opcpuid sse
4531 * @ opgroup og_sse_mxcsrsm
4532 * @ opxcpttype 5
4533 * @ optest op1=0 -> mxcsr=0
4534 * @ optest op1=0x2083 -> mxcsr=0x2083
4535 * @ optest op1=0xfffffffe -> value.xcpt=0xd
4536 * @ optest op1=0x2083 cr0|=ts -> value.xcpt=0x7
4537 * @ optest op1=0x2083 cr0|=em -> value.xcpt=0x6
4538 * @ optest op1=0x2083 cr0|=mp -> mxcsr=0x2083
4539 * @ optest op1=0x2083 cr4&~=osfxsr -> value.xcpt=0x6
4540 * @ optest op1=0x2083 cr0|=ts,em -> value.xcpt=0x6
4541 * @ optest op1=0x2083 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
4542 * @ optest op1=0x2083 cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
4543 * @ optest op1=0x2083 cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
4544 */
4545FNIEMOP_STUB_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm);
4546//FNIEMOP_DEF_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm)
4547//{
4548// IEMOP_MNEMONIC1(M_MEM, VLDMXCSR, vldmxcsr, MdRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
4549// IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4550// IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
4551// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
4552// IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4553// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4554// IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
4555// IEM_MC_CALL_CIMPL_2(iemCImpl_ldmxcsr, iEffSeg, GCPtrEff);
4556// IEM_MC_END();
4557// return VINF_SUCCESS;
4558//}
4559
4560
4561/**
4562 * @opmaps vexgrp15
4563 * @opcode !11/3
4564 * @oppfx none
4565 * @opcpuid avx
4566 * @opgroup og_avx_mxcsrsm
4567 * @opxcpttype 5
4568 * @optest mxcsr=0 -> op1=0
4569 * @optest mxcsr=0x2083 -> op1=0x2083
4570 * @optest mxcsr=0x2084 cr0|=ts -> value.xcpt=0x7
4571 * @optest !amd / mxcsr=0x2085 cr0|=em -> op1=0x2085
4572 * @optest amd / mxcsr=0x2085 cr0|=em -> value.xcpt=0x6
4573 * @optest mxcsr=0x2086 cr0|=mp -> op1=0x2086
4574 * @optest mxcsr=0x2087 cr4&~=osfxsr -> op1=0x2087
4575 * @optest mxcsr=0x208f cr4&~=osxsave -> value.xcpt=0x6
4576 * @optest mxcsr=0x2087 cr4&~=osfxsr,osxsave -> value.xcpt=0x6
4577 * @optest !amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x7
4578 * @optest amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x6
4579 * @optest !amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> op1=0x2089
4580 * @optest amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
4581 * @optest !amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x7
4582 * @optest amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
4583 * @optest !amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x7
4584 * @optest amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
4585 * @optest !amd / mxcsr=0x208c xcr0&~=all_avx -> value.xcpt=0x6
4586 * @optest amd / mxcsr=0x208c xcr0&~=all_avx -> op1=0x208c
4587 * @optest !amd / mxcsr=0x208d xcr0&~=all_avx_sse -> value.xcpt=0x6
4588 * @optest amd / mxcsr=0x208d xcr0&~=all_avx_sse -> op1=0x208d
4589 * @optest !amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x6
4590 * @optest amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x7
4591 * @optest mxcsr=0x2082 cr0|=ts cr4&~=osxsave -> value.xcpt=0x6
4592 * @optest mxcsr=0x2081 xcr0&~=all_avx cr0|=ts cr4&~=osxsave
4593 * -> value.xcpt=0x6
4594 * @remarks AMD Jaguar CPU (f0x16,m0,s1) \#UD when CR0.EM is set. It also
4595 * doesn't seem to check XCR0[2:1] != 11b. This does not match the
4596 * APMv4 rev 3.17 page 509.
4597 * @todo Test this instruction on AMD Ryzen.
4598 */
4599FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr, uint8_t, bRm)
4600{
4601 IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
4602 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4603 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
4604 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
4605 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4606 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4607 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
4608 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_FPU, 0, iemCImpl_vstmxcsr, iEffSeg, GCPtrEff);
4609 IEM_MC_END();
4610}
4611
4612/* Opcode VEX.0F 0xae mem/4 - invalid. */
4613/* Opcode VEX.0F 0xae mem/5 - invalid. */
4614/* Opcode VEX.0F 0xae mem/6 - invalid. */
4615/* Opcode VEX.0F 0xae mem/7 - invalid. */
4616
4617/* Opcode VEX.0F 0xae 11b/0 - invalid. */
4618/* Opcode VEX.0F 0xae 11b/1 - invalid. */
4619/* Opcode VEX.0F 0xae 11b/2 - invalid. */
4620/* Opcode VEX.0F 0xae 11b/3 - invalid. */
4621/* Opcode VEX.0F 0xae 11b/4 - invalid. */
4622/* Opcode VEX.0F 0xae 11b/5 - invalid. */
4623/* Opcode VEX.0F 0xae 11b/6 - invalid. */
4624/* Opcode VEX.0F 0xae 11b/7 - invalid. */
4625
4626/**
4627 * Vex group 15 jump table for memory variant.
4628 */
4629IEM_STATIC const PFNIEMOPRM g_apfnVexGroup15MemReg[] =
4630{ /* pfx: none, 066h, 0f3h, 0f2h */
4631 /* /0 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4632 /* /1 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4633 /* /2 */ iemOp_VGrp15_vldmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4634 /* /3 */ iemOp_VGrp15_vstmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4635 /* /4 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4636 /* /5 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4637 /* /6 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4638 /* /7 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4639};
4640AssertCompile(RT_ELEMENTS(g_apfnVexGroup15MemReg) == 8*4);
4641
4642
4643/** Opcode vex. 0xae. */
4644FNIEMOP_DEF(iemOp_VGrp15)
4645{
4646 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4647 if (IEM_IS_MODRM_REG_MODE(bRm))
4648 /* register, register */
4649 return FNIEMOP_CALL_1(iemOp_InvalidWithRM, bRm);
4650
4651 /* memory, register */
4652 return FNIEMOP_CALL_1(g_apfnVexGroup15MemReg[ IEM_GET_MODRM_REG_8(bRm) * 4
4653 + pVCpu->iem.s.idxPrefix], bRm);
4654}
4655
4656
4657/* Opcode VEX.0F 0xaf - invalid. */
4658
4659/* Opcode VEX.0F 0xb0 - invalid. */
4660/* Opcode VEX.0F 0xb1 - invalid. */
4661/* Opcode VEX.0F 0xb2 - invalid. */
4662/* Opcode VEX.0F 0xb2 - invalid. */
4663/* Opcode VEX.0F 0xb3 - invalid. */
4664/* Opcode VEX.0F 0xb4 - invalid. */
4665/* Opcode VEX.0F 0xb5 - invalid. */
4666/* Opcode VEX.0F 0xb6 - invalid. */
4667/* Opcode VEX.0F 0xb7 - invalid. */
4668/* Opcode VEX.0F 0xb8 - invalid. */
4669/* Opcode VEX.0F 0xb9 - invalid. */
4670/* Opcode VEX.0F 0xba - invalid. */
4671/* Opcode VEX.0F 0xbb - invalid. */
4672/* Opcode VEX.0F 0xbc - invalid. */
4673/* Opcode VEX.0F 0xbd - invalid. */
4674/* Opcode VEX.0F 0xbe - invalid. */
4675/* Opcode VEX.0F 0xbf - invalid. */
4676
4677/* Opcode VEX.0F 0xc0 - invalid. */
4678/* Opcode VEX.66.0F 0xc0 - invalid. */
4679/* Opcode VEX.F3.0F 0xc0 - invalid. */
4680/* Opcode VEX.F2.0F 0xc0 - invalid. */
4681
4682/* Opcode VEX.0F 0xc1 - invalid. */
4683/* Opcode VEX.66.0F 0xc1 - invalid. */
4684/* Opcode VEX.F3.0F 0xc1 - invalid. */
4685/* Opcode VEX.F2.0F 0xc1 - invalid. */
4686
4687/** Opcode VEX.0F 0xc2 - vcmpps Vps,Hps,Wps,Ib */
4688FNIEMOP_STUB(iemOp_vcmpps_Vps_Hps_Wps_Ib);
4689/** Opcode VEX.66.0F 0xc2 - vcmppd Vpd,Hpd,Wpd,Ib */
4690FNIEMOP_STUB(iemOp_vcmppd_Vpd_Hpd_Wpd_Ib);
4691/** Opcode VEX.F3.0F 0xc2 - vcmpss Vss,Hss,Wss,Ib */
4692FNIEMOP_STUB(iemOp_vcmpss_Vss_Hss_Wss_Ib);
4693/** Opcode VEX.F2.0F 0xc2 - vcmpsd Vsd,Hsd,Wsd,Ib */
4694FNIEMOP_STUB(iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib);
4695
4696/* Opcode VEX.0F 0xc3 - invalid */
4697/* Opcode VEX.66.0F 0xc3 - invalid */
4698/* Opcode VEX.F3.0F 0xc3 - invalid */
4699/* Opcode VEX.F2.0F 0xc3 - invalid */
4700
4701/* Opcode VEX.0F 0xc4 - invalid */
4702
4703
4704/** Opcode VEX.66.0F 0xc4 - vpinsrw Vdq,Hdq,Ry/Mw,Ib */
4705FNIEMOP_DEF(iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib)
4706{
4707 /*IEMOP_MNEMONIC4(VEX_RMV, VPINSRW, vpinsrw, Vdq, Vdq, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);*/ /** @todo */
4708 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4709 if (IEM_IS_MODRM_REG_MODE(bRm))
4710 {
4711 /*
4712 * Register, register.
4713 */
4714 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4715 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4716 IEM_MC_LOCAL(RTUINT128U, uSrc1);
4717 IEM_MC_LOCAL(uint16_t, uValue);
4718
4719 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4720 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4721 IEM_MC_PREPARE_AVX_USAGE();
4722
4723 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
4724 IEM_MC_FETCH_GREG_U16(uValue, IEM_GET_MODRM_RM(pVCpu, bRm));
4725 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
4726 IEM_MC_STORE_XREG_U16( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7, uValue);
4727 IEM_MC_ADVANCE_RIP_AND_FINISH();
4728 IEM_MC_END();
4729 }
4730 else
4731 {
4732 /*
4733 * Register, memory.
4734 */
4735 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4736 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4737 IEM_MC_LOCAL(RTUINT128U, uSrc1);
4738 IEM_MC_LOCAL(uint16_t, uValue);
4739
4740 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
4741 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4742 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4743 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4744 IEM_MC_PREPARE_AVX_USAGE();
4745
4746 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
4747 IEM_MC_FETCH_MEM_U16(uValue, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4748 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
4749 IEM_MC_STORE_XREG_U16( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7, uValue);
4750 IEM_MC_ADVANCE_RIP_AND_FINISH();
4751 IEM_MC_END();
4752 }
4753}
4754
4755
4756/* Opcode VEX.F3.0F 0xc4 - invalid */
4757/* Opcode VEX.F2.0F 0xc4 - invalid */
4758
4759/* Opcode VEX.0F 0xc5 - invalid */
4760
4761
4762/** Opcode VEX.66.0F 0xc5 - vpextrw Gd, Udq, Ib */
4763FNIEMOP_DEF(iemOp_vpextrw_Gd_Udq_Ib)
4764{
4765 IEMOP_MNEMONIC3(VEX_RMI_REG, VPEXTRW, vpextrw, Gd, Ux, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
4766 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4767 if (IEM_IS_MODRM_REG_MODE(bRm))
4768 {
4769 /*
4770 * greg32, XMM, imm8.
4771 */
4772 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4773 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4774 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4775 IEM_MC_LOCAL(uint16_t, uValue);
4776 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4777 IEM_MC_PREPARE_AVX_USAGE();
4778 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_RM(pVCpu, bRm), bImm & 7);
4779 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uValue);
4780 IEM_MC_ADVANCE_RIP_AND_FINISH();
4781 IEM_MC_END();
4782 }
4783 /* No memory operand. */
4784 else
4785 IEMOP_RAISE_INVALID_OPCODE_RET();
4786}
4787
4788
4789/* Opcode VEX.F3.0F 0xc5 - invalid */
4790/* Opcode VEX.F2.0F 0xc5 - invalid */
4791
4792
4793#define VSHUFP_X(a_Instr) \
4794 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
4795 if (IEM_IS_MODRM_REG_MODE(bRm)) \
4796 { \
4797 /* \
4798 * Register, register. \
4799 */ \
4800 if (pVCpu->iem.s.uVexLength) \
4801 { \
4802 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4803 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
4804 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
4805 IEM_MC_LOCAL(RTUINT256U, uDst); \
4806 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
4807 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
4808 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
4809 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
4810 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
4811 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4812 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
4813 IEM_MC_PREPARE_AVX_USAGE(); \
4814 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4815 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
4816 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
4817 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4818 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
4819 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4820 IEM_MC_END(); \
4821 } \
4822 else \
4823 { \
4824 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4825 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
4826 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
4827 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
4828 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
4829 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2); \
4830 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4831 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
4832 IEM_MC_PREPARE_AVX_USAGE(); \
4833 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
4834 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4835 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
4836 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
4837 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4838 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
4839 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4840 IEM_MC_END(); \
4841 } \
4842 } \
4843 else \
4844 { \
4845 /* \
4846 * Register, memory. \
4847 */ \
4848 if (pVCpu->iem.s.uVexLength) \
4849 { \
4850 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
4851 IEM_MC_LOCAL(RTUINT256U, uDst); \
4852 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
4853 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
4854 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
4855 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
4856 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
4857 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
4858 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
4859 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4860 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4861 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
4862 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
4863 IEM_MC_PREPARE_AVX_USAGE(); \
4864 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
4865 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4866 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
4867 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4868 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
4869 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4870 IEM_MC_END(); \
4871 } \
4872 else \
4873 { \
4874 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
4875 IEM_MC_LOCAL(RTUINT128U, uSrc2); \
4876 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
4877 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
4878 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
4879 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2); \
4880 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
4881 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4882 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4883 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
4884 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
4885 IEM_MC_PREPARE_AVX_USAGE(); \
4886 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
4887 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
4888 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4889 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
4890 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4891 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
4892 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4893 IEM_MC_END(); \
4894 } \
4895 } \
4896 (void)0
4897
4898/** Opcode VEX.0F 0xc6 - vshufps Vps,Hps,Wps,Ib */
4899FNIEMOP_DEF(iemOp_vshufps_Vps_Hps_Wps_Ib)
4900{
4901 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPS, vshufps, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
4902 VSHUFP_X(vshufps);
4903}
4904
4905
4906/** Opcode VEX.66.0F 0xc6 - vshufpd Vpd,Hpd,Wpd,Ib */
4907FNIEMOP_DEF(iemOp_vshufpd_Vpd_Hpd_Wpd_Ib)
4908{
4909 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPD, vshufpd, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
4910 VSHUFP_X(vshufpd);
4911}
4912#undef VSHUFP_X
4913
4914
4915/* Opcode VEX.F3.0F 0xc6 - invalid */
4916/* Opcode VEX.F2.0F 0xc6 - invalid */
4917
4918/* Opcode VEX.0F 0xc7 - invalid */
4919/* Opcode VEX.66.0F 0xc7 - invalid */
4920/* Opcode VEX.F3.0F 0xc7 - invalid */
4921/* Opcode VEX.F2.0F 0xc7 - invalid */
4922
4923/* Opcode VEX.0F 0xc8 - invalid */
4924/* Opcode VEX.0F 0xc9 - invalid */
4925/* Opcode VEX.0F 0xca - invalid */
4926/* Opcode VEX.0F 0xcb - invalid */
4927/* Opcode VEX.0F 0xcc - invalid */
4928/* Opcode VEX.0F 0xcd - invalid */
4929/* Opcode VEX.0F 0xce - invalid */
4930/* Opcode VEX.0F 0xcf - invalid */
4931
4932
4933/* Opcode VEX.0F 0xd0 - invalid */
4934/** Opcode VEX.66.0F 0xd0 - vaddsubpd Vpd, Hpd, Wpd */
4935FNIEMOP_STUB(iemOp_vaddsubpd_Vpd_Hpd_Wpd);
4936/* Opcode VEX.F3.0F 0xd0 - invalid */
4937/** Opcode VEX.F2.0F 0xd0 - vaddsubps Vps, Hps, Wps */
4938FNIEMOP_STUB(iemOp_vaddsubps_Vps_Hps_Wps);
4939
4940/* Opcode VEX.0F 0xd1 - invalid */
4941/** Opcode VEX.66.0F 0xd1 - vpsrlw Vx, Hx, W */
4942FNIEMOP_DEF(iemOp_vpsrlw_Vx_Hx_W)
4943{
4944 IEMOP_MNEMONIC3(VEX_RVM, VPSRLW, vpsrlw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4945 IEMOPMEDIAOPTF3_INIT_VARS(vpsrlw);
4946 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4947}
4948
4949/* Opcode VEX.F3.0F 0xd1 - invalid */
4950/* Opcode VEX.F2.0F 0xd1 - invalid */
4951
4952/* Opcode VEX.0F 0xd2 - invalid */
4953/** Opcode VEX.66.0F 0xd2 - vpsrld Vx, Hx, Wx */
4954FNIEMOP_DEF(iemOp_vpsrld_Vx_Hx_Wx)
4955{
4956 IEMOP_MNEMONIC3(VEX_RVM, VPSRLD, vpsrld, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4957 IEMOPMEDIAOPTF3_INIT_VARS(vpsrld);
4958 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4959}
4960
4961/* Opcode VEX.F3.0F 0xd2 - invalid */
4962/* Opcode VEX.F2.0F 0xd2 - invalid */
4963
4964/* Opcode VEX.0F 0xd3 - invalid */
4965/** Opcode VEX.66.0F 0xd3 - vpsrlq Vx, Hx, Wx */
4966FNIEMOP_DEF(iemOp_vpsrlq_Vx_Hx_Wx)
4967{
4968 IEMOP_MNEMONIC3(VEX_RVM, VPSRLQ, vpsrlq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4969 IEMOPMEDIAOPTF3_INIT_VARS(vpsrlq);
4970 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4971}
4972
4973/* Opcode VEX.F3.0F 0xd3 - invalid */
4974/* Opcode VEX.F2.0F 0xd3 - invalid */
4975
4976/* Opcode VEX.0F 0xd4 - invalid */
4977
4978
4979/** Opcode VEX.66.0F 0xd4 - vpaddq Vx, Hx, W */
4980FNIEMOP_DEF(iemOp_vpaddq_Vx_Hx_Wx)
4981{
4982 IEMOP_MNEMONIC3(VEX_RVM, VPADDQ, vpaddq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4983 IEMOPMEDIAOPTF3_INIT_VARS( vpaddq);
4984 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4985}
4986
4987
4988/* Opcode VEX.F3.0F 0xd4 - invalid */
4989/* Opcode VEX.F2.0F 0xd4 - invalid */
4990
4991/* Opcode VEX.0F 0xd5 - invalid */
4992
4993
4994/** Opcode VEX.66.0F 0xd5 - vpmullw Vx, Hx, Wx */
4995FNIEMOP_DEF(iemOp_vpmullw_Vx_Hx_Wx)
4996{
4997 IEMOP_MNEMONIC3(VEX_RVM, VPMULLW, vpmullw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4998 IEMOPMEDIAOPTF3_INIT_VARS(vpmullw);
4999 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5000}
5001
5002
5003/* Opcode VEX.F3.0F 0xd5 - invalid */
5004/* Opcode VEX.F2.0F 0xd5 - invalid */
5005
5006/* Opcode VEX.0F 0xd6 - invalid */
5007
5008/**
5009 * @opcode 0xd6
5010 * @oppfx 0x66
5011 * @opcpuid avx
5012 * @opgroup og_avx_pcksclr_datamove
5013 * @opxcpttype none
5014 * @optest op1=-1 op2=2 -> op1=2
5015 * @optest op1=0 op2=-42 -> op1=-42
5016 */
5017FNIEMOP_DEF(iemOp_vmovq_Wq_Vq)
5018{
5019 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Wq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
5020 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5021 if (IEM_IS_MODRM_REG_MODE(bRm))
5022 {
5023 /*
5024 * Register, register.
5025 */
5026 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5027 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
5028
5029 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5030 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
5031
5032 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
5033 IEM_GET_MODRM_REG(pVCpu, bRm));
5034 IEM_MC_ADVANCE_RIP_AND_FINISH();
5035 IEM_MC_END();
5036 }
5037 else
5038 {
5039 /*
5040 * Memory, register.
5041 */
5042 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5043 IEM_MC_LOCAL(uint64_t, uSrc);
5044 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5045
5046 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5047 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
5048 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5049 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
5050
5051 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
5052 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
5053
5054 IEM_MC_ADVANCE_RIP_AND_FINISH();
5055 IEM_MC_END();
5056 }
5057}
5058
5059/* Opcode VEX.F3.0F 0xd6 - invalid */
5060/* Opcode VEX.F2.0F 0xd6 - invalid */
5061
5062
5063/* Opcode VEX.0F 0xd7 - invalid */
5064
5065/** Opcode VEX.66.0F 0xd7 - */
5066FNIEMOP_DEF(iemOp_vpmovmskb_Gd_Ux)
5067{
5068 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5069 /* Docs says register only. */
5070 if (IEM_IS_MODRM_REG_MODE(bRm)) /** @todo test that this is registers only. */
5071 {
5072 /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
5073 IEMOP_MNEMONIC2(VEX_RM_REG, VPMOVMSKB, vpmovmskb, Gd, Ux, DISOPTYPE_X86_SSE | DISOPTYPE_HARMLESS, 0);
5074 if (pVCpu->iem.s.uVexLength)
5075 {
5076 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5077 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
5078 IEM_MC_ARG(uint64_t *, puDst, 0);
5079 IEM_MC_LOCAL(RTUINT256U, uSrc);
5080 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
5081 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5082 IEM_MC_PREPARE_AVX_USAGE();
5083 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
5084 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
5085 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpmovmskb_u256,
5086 iemAImpl_vpmovmskb_u256_fallback), puDst, puSrc);
5087 IEM_MC_ADVANCE_RIP_AND_FINISH();
5088 IEM_MC_END();
5089 }
5090 else
5091 {
5092 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5093 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5094 IEM_MC_ARG(uint64_t *, puDst, 0);
5095 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
5096 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5097 IEM_MC_PREPARE_AVX_USAGE();
5098 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
5099 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
5100 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_pmovmskb_u128, puDst, puSrc);
5101 IEM_MC_ADVANCE_RIP_AND_FINISH();
5102 IEM_MC_END();
5103 }
5104 }
5105 else
5106 IEMOP_RAISE_INVALID_OPCODE_RET();
5107}
5108
5109
5110/* Opcode VEX.F3.0F 0xd7 - invalid */
5111/* Opcode VEX.F2.0F 0xd7 - invalid */
5112
5113
5114/* Opcode VEX.0F 0xd8 - invalid */
5115
5116/** Opcode VEX.66.0F 0xd8 - vpsubusb Vx, Hx, Wx */
5117FNIEMOP_DEF(iemOp_vpsubusb_Vx_Hx_Wx)
5118{
5119 IEMOP_MNEMONIC3(VEX_RVM, VPSUBUSB, vpsubusb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5120 IEMOPMEDIAOPTF3_INIT_VARS(vpsubusb);
5121 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5122}
5123
5124
5125/* Opcode VEX.F3.0F 0xd8 - invalid */
5126/* Opcode VEX.F2.0F 0xd8 - invalid */
5127
5128/* Opcode VEX.0F 0xd9 - invalid */
5129
5130
5131/** Opcode VEX.66.0F 0xd9 - vpsubusw Vx, Hx, Wx */
5132FNIEMOP_DEF(iemOp_vpsubusw_Vx_Hx_Wx)
5133{
5134 IEMOP_MNEMONIC3(VEX_RVM, VPSUBUSW, vpsubusw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5135 IEMOPMEDIAOPTF3_INIT_VARS(vpsubusw);
5136 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5137}
5138
5139
5140/* Opcode VEX.F3.0F 0xd9 - invalid */
5141/* Opcode VEX.F2.0F 0xd9 - invalid */
5142
5143/* Opcode VEX.0F 0xda - invalid */
5144
5145
5146/** Opcode VEX.66.0F 0xda - vpminub Vx, Hx, Wx */
5147FNIEMOP_DEF(iemOp_vpminub_Vx_Hx_Wx)
5148{
5149 IEMOP_MNEMONIC3(VEX_RVM, VPMINUB, vpminub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5150 IEMOPMEDIAOPTF3_INIT_VARS(vpminub);
5151 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5152}
5153
5154
5155/* Opcode VEX.F3.0F 0xda - invalid */
5156/* Opcode VEX.F2.0F 0xda - invalid */
5157
5158/* Opcode VEX.0F 0xdb - invalid */
5159
5160
5161/** Opcode VEX.66.0F 0xdb - vpand Vx, Hx, Wx */
5162FNIEMOP_DEF(iemOp_vpand_Vx_Hx_Wx)
5163{
5164 IEMOP_MNEMONIC3(VEX_RVM, VPAND, vpand, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5165 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
5166 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
5167}
5168
5169
5170/* Opcode VEX.F3.0F 0xdb - invalid */
5171/* Opcode VEX.F2.0F 0xdb - invalid */
5172
5173/* Opcode VEX.0F 0xdc - invalid */
5174
5175
5176/** Opcode VEX.66.0F 0xdc - vpaddusb Vx, Hx, Wx */
5177FNIEMOP_DEF(iemOp_vpaddusb_Vx_Hx_Wx)
5178{
5179 IEMOP_MNEMONIC3(VEX_RVM, VPADDUSB, vpaddusb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5180 IEMOPMEDIAOPTF3_INIT_VARS(vpaddusb);
5181 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5182}
5183
5184
5185/* Opcode VEX.F3.0F 0xdc - invalid */
5186/* Opcode VEX.F2.0F 0xdc - invalid */
5187
5188/* Opcode VEX.0F 0xdd - invalid */
5189
5190
5191/** Opcode VEX.66.0F 0xdd - vpaddusw Vx, Hx, Wx */
5192FNIEMOP_DEF(iemOp_vpaddusw_Vx_Hx_Wx)
5193{
5194 IEMOP_MNEMONIC3(VEX_RVM, VPADDUSW, vpaddusw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5195 IEMOPMEDIAOPTF3_INIT_VARS(vpaddusw);
5196 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5197}
5198
5199
5200/* Opcode VEX.F3.0F 0xdd - invalid */
5201/* Opcode VEX.F2.0F 0xdd - invalid */
5202
5203/* Opcode VEX.0F 0xde - invalid */
5204
5205
5206/** Opcode VEX.66.0F 0xde - vpmaxub Vx, Hx, Wx */
5207FNIEMOP_DEF(iemOp_vpmaxub_Vx_Hx_Wx)
5208{
5209 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUB, vpmaxub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5210 IEMOPMEDIAOPTF3_INIT_VARS(vpmaxub);
5211 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5212}
5213
5214
5215/* Opcode VEX.F3.0F 0xde - invalid */
5216/* Opcode VEX.F2.0F 0xde - invalid */
5217
5218/* Opcode VEX.0F 0xdf - invalid */
5219
5220
5221/** Opcode VEX.66.0F 0xdf - vpandn Vx, Hx, Wx */
5222FNIEMOP_DEF(iemOp_vpandn_Vx_Hx_Wx)
5223{
5224 IEMOP_MNEMONIC3(VEX_RVM, VPANDN, vpandn, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5225 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
5226 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
5227}
5228
5229
5230/* Opcode VEX.F3.0F 0xdf - invalid */
5231/* Opcode VEX.F2.0F 0xdf - invalid */
5232
5233/* Opcode VEX.0F 0xe0 - invalid */
5234
5235
5236/** Opcode VEX.66.0F 0xe0 - vpavgb Vx, Hx, Wx */
5237FNIEMOP_DEF(iemOp_vpavgb_Vx_Hx_Wx)
5238{
5239 IEMOP_MNEMONIC3(VEX_RVM, VPAVGB, vpavgb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5240 IEMOPMEDIAOPTF3_INIT_VARS(vpavgb);
5241 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5242}
5243
5244
5245/* Opcode VEX.F3.0F 0xe0 - invalid */
5246/* Opcode VEX.F2.0F 0xe0 - invalid */
5247
5248/* Opcode VEX.0F 0xe1 - invalid */
5249/** Opcode VEX.66.0F 0xe1 - vpsraw Vx, Hx, W */
5250FNIEMOP_DEF(iemOp_vpsraw_Vx_Hx_W)
5251{
5252 IEMOP_MNEMONIC3(VEX_RVM, VPSRAW, vpsraw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5253 IEMOPMEDIAOPTF3_INIT_VARS(vpsraw);
5254 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5255}
5256
5257/* Opcode VEX.F3.0F 0xe1 - invalid */
5258/* Opcode VEX.F2.0F 0xe1 - invalid */
5259
5260/* Opcode VEX.0F 0xe2 - invalid */
5261/** Opcode VEX.66.0F 0xe2 - vpsrad Vx, Hx, Wx */
5262FNIEMOP_DEF(iemOp_vpsrad_Vx_Hx_Wx)
5263{
5264 IEMOP_MNEMONIC3(VEX_RVM, VPSRAD, vpsrad, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5265 IEMOPMEDIAOPTF3_INIT_VARS(vpsrad);
5266 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5267}
5268
5269/* Opcode VEX.F3.0F 0xe2 - invalid */
5270/* Opcode VEX.F2.0F 0xe2 - invalid */
5271
5272/* Opcode VEX.0F 0xe3 - invalid */
5273
5274
5275/** Opcode VEX.66.0F 0xe3 - vpavgw Vx, Hx, Wx */
5276FNIEMOP_DEF(iemOp_vpavgw_Vx_Hx_Wx)
5277{
5278 IEMOP_MNEMONIC3(VEX_RVM, VPAVGW, vpavgw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5279 IEMOPMEDIAOPTF3_INIT_VARS(vpavgw);
5280 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5281}
5282
5283
5284/* Opcode VEX.F3.0F 0xe3 - invalid */
5285/* Opcode VEX.F2.0F 0xe3 - invalid */
5286
5287/* Opcode VEX.0F 0xe4 - invalid */
5288
5289
5290/** Opcode VEX.66.0F 0xe4 - vpmulhuw Vx, Hx, Wx */
5291FNIEMOP_DEF(iemOp_vpmulhuw_Vx_Hx_Wx)
5292{
5293 IEMOP_MNEMONIC3(VEX_RVM, VPMULHUW, vpmulhuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5294 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhuw);
5295 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5296}
5297
5298
5299/* Opcode VEX.F3.0F 0xe4 - invalid */
5300/* Opcode VEX.F2.0F 0xe4 - invalid */
5301
5302/* Opcode VEX.0F 0xe5 - invalid */
5303
5304
5305/** Opcode VEX.66.0F 0xe5 - vpmulhw Vx, Hx, Wx */
5306FNIEMOP_DEF(iemOp_vpmulhw_Vx_Hx_Wx)
5307{
5308 IEMOP_MNEMONIC3(VEX_RVM, VPMULHW, vpmulhw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5309 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhw);
5310 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5311}
5312
5313
5314/* Opcode VEX.F3.0F 0xe5 - invalid */
5315/* Opcode VEX.F2.0F 0xe5 - invalid */
5316
5317/* Opcode VEX.0F 0xe6 - invalid */
5318/** Opcode VEX.66.0F 0xe6 - vcvttpd2dq Vx, Wpd */
5319FNIEMOP_STUB(iemOp_vcvttpd2dq_Vx_Wpd);
5320/** Opcode VEX.F3.0F 0xe6 - vcvtdq2pd Vx, Wpd */
5321FNIEMOP_STUB(iemOp_vcvtdq2pd_Vx_Wpd);
5322/** Opcode VEX.F2.0F 0xe6 - vcvtpd2dq Vx, Wpd */
5323FNIEMOP_STUB(iemOp_vcvtpd2dq_Vx_Wpd);
5324
5325
5326/* Opcode VEX.0F 0xe7 - invalid */
5327
5328/**
5329 * @opcode 0xe7
5330 * @opcodesub !11 mr/reg
5331 * @oppfx 0x66
5332 * @opcpuid avx
5333 * @opgroup og_avx_cachect
5334 * @opxcpttype 1
5335 * @optest op1=-1 op2=2 -> op1=2
5336 * @optest op1=0 op2=-42 -> op1=-42
5337 */
5338FNIEMOP_DEF(iemOp_vmovntdq_Mx_Vx)
5339{
5340 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTDQ, vmovntdq, Mx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
5341 Assert(pVCpu->iem.s.uVexLength <= 1);
5342 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5343 if (IEM_IS_MODRM_MEM_MODE(bRm))
5344 {
5345 if (pVCpu->iem.s.uVexLength == 0)
5346 {
5347 /*
5348 * 128-bit: Memory, register.
5349 */
5350 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5351 IEM_MC_LOCAL(RTUINT128U, uSrc);
5352 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5353
5354 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5355 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5356 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5357 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
5358
5359 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
5360 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
5361
5362 IEM_MC_ADVANCE_RIP_AND_FINISH();
5363 IEM_MC_END();
5364 }
5365 else
5366 {
5367 /*
5368 * 256-bit: Memory, register.
5369 */
5370 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5371 IEM_MC_LOCAL(RTUINT256U, uSrc);
5372 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5373
5374 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5375 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5376 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5377 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
5378
5379 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
5380 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
5381
5382 IEM_MC_ADVANCE_RIP_AND_FINISH();
5383 IEM_MC_END();
5384 }
5385 }
5386 /**
5387 * @opdone
5388 * @opmnemonic udvex660fe7reg
5389 * @opcode 0xe7
5390 * @opcodesub 11 mr/reg
5391 * @oppfx 0x66
5392 * @opunused immediate
5393 * @opcpuid avx
5394 * @optest ->
5395 */
5396 else
5397 IEMOP_RAISE_INVALID_OPCODE_RET();
5398}
5399
5400/* Opcode VEX.F3.0F 0xe7 - invalid */
5401/* Opcode VEX.F2.0F 0xe7 - invalid */
5402
5403
5404/* Opcode VEX.0F 0xe8 - invalid */
5405
5406
5407/** Opcode VEX.66.0F 0xe8 - vpsubsb Vx, Hx, Wx */
5408FNIEMOP_DEF(iemOp_vpsubsb_Vx_Hx_Wx)
5409{
5410 IEMOP_MNEMONIC3(VEX_RVM, VPSUBSB, vpsubsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5411 IEMOPMEDIAOPTF3_INIT_VARS(vpsubsb);
5412 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5413}
5414
5415
5416/* Opcode VEX.F3.0F 0xe8 - invalid */
5417/* Opcode VEX.F2.0F 0xe8 - invalid */
5418
5419/* Opcode VEX.0F 0xe9 - invalid */
5420
5421
5422/** Opcode VEX.66.0F 0xe9 - vpsubsw Vx, Hx, Wx */
5423FNIEMOP_DEF(iemOp_vpsubsw_Vx_Hx_Wx)
5424{
5425 IEMOP_MNEMONIC3(VEX_RVM, VPSUBSW, vpsubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5426 IEMOPMEDIAOPTF3_INIT_VARS(vpsubsw);
5427 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5428}
5429
5430
5431/* Opcode VEX.F3.0F 0xe9 - invalid */
5432/* Opcode VEX.F2.0F 0xe9 - invalid */
5433
5434/* Opcode VEX.0F 0xea - invalid */
5435
5436
5437/** Opcode VEX.66.0F 0xea - vpminsw Vx, Hx, Wx */
5438FNIEMOP_DEF(iemOp_vpminsw_Vx_Hx_Wx)
5439{
5440 IEMOP_MNEMONIC3(VEX_RVM, VPMINSW, vpminsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5441 IEMOPMEDIAOPTF3_INIT_VARS(vpminsw);
5442 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5443}
5444
5445
5446/* Opcode VEX.F3.0F 0xea - invalid */
5447/* Opcode VEX.F2.0F 0xea - invalid */
5448
5449/* Opcode VEX.0F 0xeb - invalid */
5450
5451
5452/** Opcode VEX.66.0F 0xeb - vpor Vx, Hx, Wx */
5453FNIEMOP_DEF(iemOp_vpor_Vx_Hx_Wx)
5454{
5455 IEMOP_MNEMONIC3(VEX_RVM, VPOR, vpor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5456 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
5457 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
5458}
5459
5460
5461
5462/* Opcode VEX.F3.0F 0xeb - invalid */
5463/* Opcode VEX.F2.0F 0xeb - invalid */
5464
5465/* Opcode VEX.0F 0xec - invalid */
5466
5467
5468/** Opcode VEX.66.0F 0xec - vpaddsb Vx, Hx, Wx */
5469FNIEMOP_DEF(iemOp_vpaddsb_Vx_Hx_Wx)
5470{
5471 IEMOP_MNEMONIC3(VEX_RVM, VPADDSB, vpaddsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5472 IEMOPMEDIAOPTF3_INIT_VARS(vpaddsb);
5473 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5474}
5475
5476
5477/* Opcode VEX.F3.0F 0xec - invalid */
5478/* Opcode VEX.F2.0F 0xec - invalid */
5479
5480/* Opcode VEX.0F 0xed - invalid */
5481
5482
5483/** Opcode VEX.66.0F 0xed - vpaddsw Vx, Hx, Wx */
5484FNIEMOP_DEF(iemOp_vpaddsw_Vx_Hx_Wx)
5485{
5486 IEMOP_MNEMONIC3(VEX_RVM, VPADDSW, vpaddsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5487 IEMOPMEDIAOPTF3_INIT_VARS(vpaddsw);
5488 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5489}
5490
5491
5492/* Opcode VEX.F3.0F 0xed - invalid */
5493/* Opcode VEX.F2.0F 0xed - invalid */
5494
5495/* Opcode VEX.0F 0xee - invalid */
5496
5497
5498/** Opcode VEX.66.0F 0xee - vpmaxsw Vx, Hx, Wx */
5499FNIEMOP_DEF(iemOp_vpmaxsw_Vx_Hx_Wx)
5500{
5501 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSW, vpmaxsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5502 IEMOPMEDIAOPTF3_INIT_VARS(vpmaxsw);
5503 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5504}
5505
5506
5507/* Opcode VEX.F3.0F 0xee - invalid */
5508/* Opcode VEX.F2.0F 0xee - invalid */
5509
5510
5511/* Opcode VEX.0F 0xef - invalid */
5512
5513
5514/** Opcode VEX.66.0F 0xef - vpxor Vx, Hx, Wx */
5515FNIEMOP_DEF(iemOp_vpxor_Vx_Hx_Wx)
5516{
5517 IEMOP_MNEMONIC3(VEX_RVM, VPXOR, vpxor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5518 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
5519 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
5520}
5521
5522
5523/* Opcode VEX.F3.0F 0xef - invalid */
5524/* Opcode VEX.F2.0F 0xef - invalid */
5525
5526/* Opcode VEX.0F 0xf0 - invalid */
5527/* Opcode VEX.66.0F 0xf0 - invalid */
5528
5529
5530/** Opcode VEX.F2.0F 0xf0 - vlddqu Vx, Mx */
5531FNIEMOP_DEF(iemOp_vlddqu_Vx_Mx)
5532{
5533 IEMOP_MNEMONIC2(VEX_RM_MEM, VLDDQU, vlddqu, Vx_WO, Mx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
5534 Assert(pVCpu->iem.s.uVexLength <= 1);
5535 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5536 if (IEM_IS_MODRM_REG_MODE(bRm))
5537 {
5538 /*
5539 * Register, register - (not implemented, assuming it raises \#UD).
5540 */
5541 IEMOP_RAISE_INVALID_OPCODE_RET();
5542 }
5543 else if (pVCpu->iem.s.uVexLength == 0)
5544 {
5545 /*
5546 * Register, memory128.
5547 */
5548 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5549 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
5550 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5551
5552 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5553 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5554 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5555 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
5556
5557 IEM_MC_FETCH_MEM_U128_NO_AC(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
5558 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
5559
5560 IEM_MC_ADVANCE_RIP_AND_FINISH();
5561 IEM_MC_END();
5562 }
5563 else
5564 {
5565 /*
5566 * Register, memory256.
5567 */
5568 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5569 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
5570 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5571
5572 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5573 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5574 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5575 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
5576
5577 IEM_MC_FETCH_MEM_U256_NO_AC(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
5578 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
5579
5580 IEM_MC_ADVANCE_RIP_AND_FINISH();
5581 IEM_MC_END();
5582 }
5583}
5584
5585
5586/* Opcode VEX.0F 0xf1 - invalid */
5587/** Opcode VEX.66.0F 0xf1 - vpsllw Vx, Hx, W */
5588FNIEMOP_DEF(iemOp_vpsllw_Vx_Hx_W)
5589{
5590 IEMOP_MNEMONIC3(VEX_RVM, VPSLLW, vpsllw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5591 IEMOPMEDIAOPTF3_INIT_VARS(vpsllw);
5592 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5593}
5594
5595/* Opcode VEX.F2.0F 0xf1 - invalid */
5596
5597/* Opcode VEX.0F 0xf2 - invalid */
5598/** Opcode VEX.66.0F 0xf2 - vpslld Vx, Hx, Wx */
5599FNIEMOP_DEF(iemOp_vpslld_Vx_Hx_Wx)
5600{
5601 IEMOP_MNEMONIC3(VEX_RVM, VPSLLD, vpslld, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5602 IEMOPMEDIAOPTF3_INIT_VARS(vpslld);
5603 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5604}
5605/* Opcode VEX.F2.0F 0xf2 - invalid */
5606
5607/* Opcode VEX.0F 0xf3 - invalid */
5608/** Opcode VEX.66.0F 0xf3 - vpsllq Vx, Hx, Wx */
5609FNIEMOP_DEF(iemOp_vpsllq_Vx_Hx_Wx)
5610{
5611 IEMOP_MNEMONIC3(VEX_RVM, VPSLLQ, vpsllq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5612 IEMOPMEDIAOPTF3_INIT_VARS(vpsllq);
5613 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5614}
5615/* Opcode VEX.F2.0F 0xf3 - invalid */
5616
5617/* Opcode VEX.0F 0xf4 - invalid */
5618
5619
5620/** Opcode VEX.66.0F 0xf4 - vpmuludq Vx, Hx, W */
5621FNIEMOP_DEF(iemOp_vpmuludq_Vx_Hx_W)
5622{
5623 IEMOP_MNEMONIC3(VEX_RVM, VPMULUDQ, vpmuludq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5624 IEMOPMEDIAOPTF3_INIT_VARS(vpmuludq);
5625 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5626}
5627
5628
5629/* Opcode VEX.F2.0F 0xf4 - invalid */
5630
5631/* Opcode VEX.0F 0xf5 - invalid */
5632
5633
5634/** Opcode VEX.66.0F 0xf5 - vpmaddwd Vx, Hx, Wx */
5635FNIEMOP_DEF(iemOp_vpmaddwd_Vx_Hx_Wx)
5636{
5637 IEMOP_MNEMONIC3(VEX_RVM, VPMADDWD, vpmaddwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5638 IEMOPMEDIAOPTF3_INIT_VARS(vpmaddwd);
5639 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5640}
5641
5642
5643/* Opcode VEX.F2.0F 0xf5 - invalid */
5644
5645/* Opcode VEX.0F 0xf6 - invalid */
5646
5647
5648/** Opcode VEX.66.0F 0xf6 - vpsadbw Vx, Hx, Wx */
5649FNIEMOP_DEF(iemOp_vpsadbw_Vx_Hx_Wx)
5650{
5651 IEMOP_MNEMONIC3(VEX_RVM, VPSADBW, vpsadbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5652 IEMOPMEDIAOPTF3_INIT_VARS(vpsadbw);
5653 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5654}
5655
5656
5657/* Opcode VEX.F2.0F 0xf6 - invalid */
5658
5659/* Opcode VEX.0F 0xf7 - invalid */
5660
5661
5662/** Opcode VEX.66.0F 0xf7 - vmaskmovdqu Vdq, Udq */
5663FNIEMOP_DEF(iemOp_vmaskmovdqu_Vdq_Udq)
5664{
5665// IEMOP_MNEMONIC2(RM, VMASKMOVDQU, vmaskmovdqu, Vdq, Udq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES); /** @todo */
5666 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5667 if (IEM_IS_MODRM_REG_MODE(bRm))
5668 {
5669 /*
5670 * XMM, XMM, (implicit) [ ER]DI
5671 */
5672 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5673 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
5674 IEM_MC_LOCAL( uint64_t, u64EffAddr);
5675 IEM_MC_LOCAL( RTUINT128U, u128Mem);
5676 IEM_MC_ARG_LOCAL_REF(PRTUINT128U, pu128Mem, u128Mem, 0);
5677 IEM_MC_ARG( PCRTUINT128U, puSrc, 1);
5678 IEM_MC_ARG( PCRTUINT128U, puMsk, 2);
5679 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5680 IEM_MC_PREPARE_AVX_USAGE();
5681
5682 IEM_MC_FETCH_GREG_U64(u64EffAddr, X86_GREG_xDI);
5683 IEM_MC_FETCH_MEM_U128(u128Mem, pVCpu->iem.s.iEffSeg, u64EffAddr);
5684 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
5685 IEM_MC_REF_XREG_U128_CONST(puMsk, IEM_GET_MODRM_RM(pVCpu, bRm));
5686 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_maskmovdqu_u128, pu128Mem, puSrc, puMsk);
5687 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, u64EffAddr, u128Mem);
5688
5689 IEM_MC_ADVANCE_RIP_AND_FINISH();
5690 IEM_MC_END();
5691 }
5692 else
5693 {
5694 /* The memory, register encoding is invalid. */
5695 IEMOP_RAISE_INVALID_OPCODE_RET();
5696 }
5697}
5698
5699
5700/* Opcode VEX.F2.0F 0xf7 - invalid */
5701
5702/* Opcode VEX.0F 0xf8 - invalid */
5703
5704
5705/** Opcode VEX.66.0F 0xf8 - vpsubb Vx, Hx, W */
5706FNIEMOP_DEF(iemOp_vpsubb_Vx_Hx_Wx)
5707{
5708 IEMOP_MNEMONIC3(VEX_RVM, VPSUBB, vpsubb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5709 IEMOPMEDIAOPTF3_INIT_VARS( vpsubb);
5710 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5711}
5712
5713
5714/* Opcode VEX.F2.0F 0xf8 - invalid */
5715
5716/* Opcode VEX.0F 0xf9 - invalid */
5717
5718
5719/** Opcode VEX.66.0F 0xf9 - vpsubw Vx, Hx, Wx */
5720FNIEMOP_DEF(iemOp_vpsubw_Vx_Hx_Wx)
5721{
5722 IEMOP_MNEMONIC3(VEX_RVM, VPSUBW, vpsubw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5723 IEMOPMEDIAOPTF3_INIT_VARS( vpsubw);
5724 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5725}
5726
5727
5728/* Opcode VEX.F2.0F 0xf9 - invalid */
5729
5730/* Opcode VEX.0F 0xfa - invalid */
5731
5732
5733/** Opcode VEX.66.0F 0xfa - vpsubd Vx, Hx, Wx */
5734FNIEMOP_DEF(iemOp_vpsubd_Vx_Hx_Wx)
5735{
5736 IEMOP_MNEMONIC3(VEX_RVM, VPSUBD, vpsubd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5737 IEMOPMEDIAOPTF3_INIT_VARS( vpsubd);
5738 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5739}
5740
5741
5742/* Opcode VEX.F2.0F 0xfa - invalid */
5743
5744/* Opcode VEX.0F 0xfb - invalid */
5745
5746
5747/** Opcode VEX.66.0F 0xfb - vpsubq Vx, Hx, W */
5748FNIEMOP_DEF(iemOp_vpsubq_Vx_Hx_Wx)
5749{
5750 IEMOP_MNEMONIC3(VEX_RVM, VPSUBQ, vpsubq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5751 IEMOPMEDIAOPTF3_INIT_VARS( vpsubq);
5752 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5753}
5754
5755
5756/* Opcode VEX.F2.0F 0xfb - invalid */
5757
5758/* Opcode VEX.0F 0xfc - invalid */
5759
5760
5761/** Opcode VEX.66.0F 0xfc - vpaddb Vx, Hx, Wx */
5762FNIEMOP_DEF(iemOp_vpaddb_Vx_Hx_Wx)
5763{
5764 IEMOP_MNEMONIC3(VEX_RVM, VPADDB, vpaddb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5765 IEMOPMEDIAOPTF3_INIT_VARS( vpaddb);
5766 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5767}
5768
5769
5770/* Opcode VEX.F2.0F 0xfc - invalid */
5771
5772/* Opcode VEX.0F 0xfd - invalid */
5773
5774
5775/** Opcode VEX.66.0F 0xfd - vpaddw Vx, Hx, Wx */
5776FNIEMOP_DEF(iemOp_vpaddw_Vx_Hx_Wx)
5777{
5778 IEMOP_MNEMONIC3(VEX_RVM, VPADDW, vpaddw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5779 IEMOPMEDIAOPTF3_INIT_VARS( vpaddw);
5780 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5781}
5782
5783
5784/* Opcode VEX.F2.0F 0xfd - invalid */
5785
5786/* Opcode VEX.0F 0xfe - invalid */
5787
5788
5789/** Opcode VEX.66.0F 0xfe - vpaddd Vx, Hx, W */
5790FNIEMOP_DEF(iemOp_vpaddd_Vx_Hx_Wx)
5791{
5792 IEMOP_MNEMONIC3(VEX_RVM, VPADDD, vpaddd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5793 IEMOPMEDIAOPTF3_INIT_VARS( vpaddd);
5794 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5795}
5796
5797
5798/* Opcode VEX.F2.0F 0xfe - invalid */
5799
5800
5801/** Opcode **** 0x0f 0xff - UD0 */
5802FNIEMOP_DEF(iemOp_vud0)
5803{
5804/** @todo testcase: vud0 */
5805 IEMOP_MNEMONIC(vud0, "vud0");
5806 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
5807 {
5808 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
5809 if (IEM_IS_MODRM_MEM_MODE(bRm))
5810 IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(bRm);
5811 }
5812 IEMOP_HLP_DONE_DECODING();
5813 IEMOP_RAISE_INVALID_OPCODE_RET();
5814}
5815
5816
5817
5818/**
5819 * VEX opcode map \#1.
5820 *
5821 * @sa g_apfnTwoByteMap
5822 */
5823const PFNIEMOP g_apfnVexMap1[] =
5824{
5825 /* no prefix, 066h prefix f3h prefix, f2h prefix */
5826 /* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRM),
5827 /* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRM),
5828 /* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRM),
5829 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRM),
5830 /* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRM),
5831 /* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRM),
5832 /* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRM),
5833 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRM),
5834 /* 0x08 */ IEMOP_X4(iemOp_InvalidNeedRM),
5835 /* 0x09 */ IEMOP_X4(iemOp_InvalidNeedRM),
5836 /* 0x0a */ IEMOP_X4(iemOp_InvalidNeedRM),
5837 /* 0x0b */ IEMOP_X4(iemOp_vud2), /* ?? */
5838 /* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
5839 /* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
5840 /* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
5841 /* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
5842
5843 /* 0x10 */ iemOp_vmovups_Vps_Wps, iemOp_vmovupd_Vpd_Wpd, iemOp_vmovss_Vss_Hss_Wss, iemOp_vmovsd_Vsd_Hsd_Wsd,
5844 /* 0x11 */ iemOp_vmovups_Wps_Vps, iemOp_vmovupd_Wpd_Vpd, iemOp_vmovss_Wss_Hss_Vss, iemOp_vmovsd_Wsd_Hsd_Vsd,
5845 /* 0x12 */ iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx, iemOp_vmovddup_Vx_Wx,
5846 /* 0x13 */ iemOp_vmovlps_Mq_Vq, iemOp_vmovlpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5847 /* 0x14 */ iemOp_vunpcklps_Vx_Hx_Wx, iemOp_vunpcklpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5848 /* 0x15 */ iemOp_vunpckhps_Vx_Hx_Wx, iemOp_vunpckhpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5849 /* 0x16 */ iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq, iemOp_vmovhpd_Vdq_Hq_Mq, iemOp_vmovshdup_Vx_Wx, iemOp_InvalidNeedRM,
5850 /* 0x17 */ iemOp_vmovhps_Mq_Vq, iemOp_vmovhpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5851 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
5852 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
5853 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
5854 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
5855 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRM),
5856 /* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRM),
5857 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRM),
5858 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
5859
5860 /* 0x20 */ IEMOP_X4(iemOp_InvalidNeedRM),
5861 /* 0x21 */ IEMOP_X4(iemOp_InvalidNeedRM),
5862 /* 0x22 */ IEMOP_X4(iemOp_InvalidNeedRM),
5863 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRM),
5864 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRM),
5865 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRM),
5866 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
5867 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
5868 /* 0x28 */ iemOp_vmovaps_Vps_Wps, iemOp_vmovapd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5869 /* 0x29 */ iemOp_vmovaps_Wps_Vps, iemOp_vmovapd_Wpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5870 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtsi2ss_Vss_Hss_Ey, iemOp_vcvtsi2sd_Vsd_Hsd_Ey,
5871 /* 0x2b */ iemOp_vmovntps_Mps_Vps, iemOp_vmovntpd_Mpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5872 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvttss2si_Gy_Wss, iemOp_vcvttsd2si_Gy_Wsd,
5873 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtss2si_Gy_Wss, iemOp_vcvtsd2si_Gy_Wsd,
5874 /* 0x2e */ iemOp_vucomiss_Vss_Wss, iemOp_vucomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5875 /* 0x2f */ iemOp_vcomiss_Vss_Wss, iemOp_vcomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5876
5877 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRM),
5878 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRM),
5879 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRM),
5880 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRM),
5881 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRM),
5882 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRM),
5883 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
5884 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRM),
5885 /* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5886 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5887 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5888 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5889 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5890 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5891 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5892 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5893
5894 /* 0x40 */ IEMOP_X4(iemOp_InvalidNeedRM),
5895 /* 0x41 */ IEMOP_X4(iemOp_InvalidNeedRM),
5896 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
5897 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
5898 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
5899 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
5900 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
5901 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
5902 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
5903 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
5904 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
5905 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
5906 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
5907 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
5908 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
5909 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
5910
5911 /* 0x50 */ iemOp_vmovmskps_Gy_Ups, iemOp_vmovmskpd_Gy_Upd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5912 /* 0x51 */ iemOp_vsqrtps_Vps_Wps, iemOp_vsqrtpd_Vpd_Wpd, iemOp_vsqrtss_Vss_Hss_Wss, iemOp_vsqrtsd_Vsd_Hsd_Wsd,
5913 /* 0x52 */ iemOp_vrsqrtps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrsqrtss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
5914 /* 0x53 */ iemOp_vrcpps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrcpss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
5915 /* 0x54 */ iemOp_vandps_Vps_Hps_Wps, iemOp_vandpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5916 /* 0x55 */ iemOp_vandnps_Vps_Hps_Wps, iemOp_vandnpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5917 /* 0x56 */ iemOp_vorps_Vps_Hps_Wps, iemOp_vorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5918 /* 0x57 */ iemOp_vxorps_Vps_Hps_Wps, iemOp_vxorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5919 /* 0x58 */ iemOp_vaddps_Vps_Hps_Wps, iemOp_vaddpd_Vpd_Hpd_Wpd, iemOp_vaddss_Vss_Hss_Wss, iemOp_vaddsd_Vsd_Hsd_Wsd,
5920 /* 0x59 */ iemOp_vmulps_Vps_Hps_Wps, iemOp_vmulpd_Vpd_Hpd_Wpd, iemOp_vmulss_Vss_Hss_Wss, iemOp_vmulsd_Vsd_Hsd_Wsd,
5921 /* 0x5a */ iemOp_vcvtps2pd_Vpd_Wps, iemOp_vcvtpd2ps_Vps_Wpd, iemOp_vcvtss2sd_Vsd_Hx_Wss, iemOp_vcvtsd2ss_Vss_Hx_Wsd,
5922 /* 0x5b */ iemOp_vcvtdq2ps_Vps_Wdq, iemOp_vcvtps2dq_Vdq_Wps, iemOp_vcvttps2dq_Vdq_Wps, iemOp_InvalidNeedRM,
5923 /* 0x5c */ iemOp_vsubps_Vps_Hps_Wps, iemOp_vsubpd_Vpd_Hpd_Wpd, iemOp_vsubss_Vss_Hss_Wss, iemOp_vsubsd_Vsd_Hsd_Wsd,
5924 /* 0x5d */ iemOp_vminps_Vps_Hps_Wps, iemOp_vminpd_Vpd_Hpd_Wpd, iemOp_vminss_Vss_Hss_Wss, iemOp_vminsd_Vsd_Hsd_Wsd,
5925 /* 0x5e */ iemOp_vdivps_Vps_Hps_Wps, iemOp_vdivpd_Vpd_Hpd_Wpd, iemOp_vdivss_Vss_Hss_Wss, iemOp_vdivsd_Vsd_Hsd_Wsd,
5926 /* 0x5f */ iemOp_vmaxps_Vps_Hps_Wps, iemOp_vmaxpd_Vpd_Hpd_Wpd, iemOp_vmaxss_Vss_Hss_Wss, iemOp_vmaxsd_Vsd_Hsd_Wsd,
5927
5928 /* 0x60 */ iemOp_InvalidNeedRM, iemOp_vpunpcklbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5929 /* 0x61 */ iemOp_InvalidNeedRM, iemOp_vpunpcklwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5930 /* 0x62 */ iemOp_InvalidNeedRM, iemOp_vpunpckldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5931 /* 0x63 */ iemOp_InvalidNeedRM, iemOp_vpacksswb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5932 /* 0x64 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5933 /* 0x65 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5934 /* 0x66 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5935 /* 0x67 */ iemOp_InvalidNeedRM, iemOp_vpackuswb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5936 /* 0x68 */ iemOp_InvalidNeedRM, iemOp_vpunpckhbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5937 /* 0x69 */ iemOp_InvalidNeedRM, iemOp_vpunpckhwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5938 /* 0x6a */ iemOp_InvalidNeedRM, iemOp_vpunpckhdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5939 /* 0x6b */ iemOp_InvalidNeedRM, iemOp_vpackssdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5940 /* 0x6c */ iemOp_InvalidNeedRM, iemOp_vpunpcklqdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5941 /* 0x6d */ iemOp_InvalidNeedRM, iemOp_vpunpckhqdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5942 /* 0x6e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Vy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5943 /* 0x6f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Vx_Wx, iemOp_vmovdqu_Vx_Wx, iemOp_InvalidNeedRM,
5944
5945 /* 0x70 */ iemOp_InvalidNeedRM, iemOp_vpshufd_Vx_Wx_Ib, iemOp_vpshufhw_Vx_Wx_Ib, iemOp_vpshuflw_Vx_Wx_Ib,
5946 /* 0x71 */ iemOp_InvalidNeedRM, iemOp_VGrp12, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5947 /* 0x72 */ iemOp_InvalidNeedRM, iemOp_VGrp13, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5948 /* 0x73 */ iemOp_InvalidNeedRM, iemOp_VGrp14, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5949 /* 0x74 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5950 /* 0x75 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5951 /* 0x76 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5952 /* 0x77 */ iemOp_vzeroupperv__vzeroallv, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5953 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
5954 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
5955 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
5956 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
5957 /* 0x7c */ iemOp_InvalidNeedRM, iemOp_vhaddpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhaddps_Vps_Hps_Wps,
5958 /* 0x7d */ iemOp_InvalidNeedRM, iemOp_vhsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhsubps_Vps_Hps_Wps,
5959 /* 0x7e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Ey_Vy, iemOp_vmovq_Vq_Wq, iemOp_InvalidNeedRM,
5960 /* 0x7f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Wx_Vx, iemOp_vmovdqu_Wx_Vx, iemOp_InvalidNeedRM,
5961
5962 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
5963 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
5964 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
5965 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
5966 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
5967 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
5968 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
5969 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
5970 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
5971 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
5972 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
5973 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
5974 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
5975 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
5976 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
5977 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
5978
5979 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
5980 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
5981 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
5982 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
5983 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
5984 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
5985 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
5986 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
5987 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
5988 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
5989 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
5990 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
5991 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
5992 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
5993 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
5994 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
5995
5996 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
5997 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
5998 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
5999 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
6000 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
6001 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
6002 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
6003 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
6004 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
6005 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
6006 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
6007 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
6008 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
6009 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
6010 /* 0xae */ IEMOP_X4(iemOp_VGrp15),
6011 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
6012
6013 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
6014 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
6015 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
6016 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
6017 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
6018 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
6019 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
6020 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
6021 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
6022 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
6023 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
6024 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
6025 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
6026 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
6027 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
6028 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
6029
6030 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
6031 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
6032 /* 0xc2 */ iemOp_vcmpps_Vps_Hps_Wps_Ib, iemOp_vcmppd_Vpd_Hpd_Wpd_Ib, iemOp_vcmpss_Vss_Hss_Wss_Ib, iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib,
6033 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
6034 /* 0xc4 */ iemOp_InvalidNeedRM, iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
6035 /* 0xc5 */ iemOp_InvalidNeedRM, iemOp_vpextrw_Gd_Udq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
6036 /* 0xc6 */ iemOp_vshufps_Vps_Hps_Wps_Ib, iemOp_vshufpd_Vpd_Hpd_Wpd_Ib, iemOp_InvalidNeedRMImm8,iemOp_InvalidNeedRMImm8,
6037 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
6038 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
6039 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
6040 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
6041 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
6042 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
6043 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
6044 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
6045 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
6046
6047 /* 0xd0 */ iemOp_InvalidNeedRM, iemOp_vaddsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vaddsubps_Vps_Hps_Wps,
6048 /* 0xd1 */ iemOp_InvalidNeedRM, iemOp_vpsrlw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6049 /* 0xd2 */ iemOp_InvalidNeedRM, iemOp_vpsrld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6050 /* 0xd3 */ iemOp_InvalidNeedRM, iemOp_vpsrlq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6051 /* 0xd4 */ iemOp_InvalidNeedRM, iemOp_vpaddq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6052 /* 0xd5 */ iemOp_InvalidNeedRM, iemOp_vpmullw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6053 /* 0xd6 */ iemOp_InvalidNeedRM, iemOp_vmovq_Wq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6054 /* 0xd7 */ iemOp_InvalidNeedRM, iemOp_vpmovmskb_Gd_Ux, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6055 /* 0xd8 */ iemOp_InvalidNeedRM, iemOp_vpsubusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6056 /* 0xd9 */ iemOp_InvalidNeedRM, iemOp_vpsubusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6057 /* 0xda */ iemOp_InvalidNeedRM, iemOp_vpminub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6058 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vpand_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6059 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vpaddusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6060 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vpaddusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6061 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vpmaxub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6062 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vpandn_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6063
6064 /* 0xe0 */ iemOp_InvalidNeedRM, iemOp_vpavgb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6065 /* 0xe1 */ iemOp_InvalidNeedRM, iemOp_vpsraw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6066 /* 0xe2 */ iemOp_InvalidNeedRM, iemOp_vpsrad_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6067 /* 0xe3 */ iemOp_InvalidNeedRM, iemOp_vpavgw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6068 /* 0xe4 */ iemOp_InvalidNeedRM, iemOp_vpmulhuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6069 /* 0xe5 */ iemOp_InvalidNeedRM, iemOp_vpmulhw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6070 /* 0xe6 */ iemOp_InvalidNeedRM, iemOp_vcvttpd2dq_Vx_Wpd, iemOp_vcvtdq2pd_Vx_Wpd, iemOp_vcvtpd2dq_Vx_Wpd,
6071 /* 0xe7 */ iemOp_InvalidNeedRM, iemOp_vmovntdq_Mx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6072 /* 0xe8 */ iemOp_InvalidNeedRM, iemOp_vpsubsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6073 /* 0xe9 */ iemOp_InvalidNeedRM, iemOp_vpsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6074 /* 0xea */ iemOp_InvalidNeedRM, iemOp_vpminsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6075 /* 0xeb */ iemOp_InvalidNeedRM, iemOp_vpor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6076 /* 0xec */ iemOp_InvalidNeedRM, iemOp_vpaddsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6077 /* 0xed */ iemOp_InvalidNeedRM, iemOp_vpaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6078 /* 0xee */ iemOp_InvalidNeedRM, iemOp_vpmaxsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6079 /* 0xef */ iemOp_InvalidNeedRM, iemOp_vpxor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6080
6081 /* 0xf0 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vlddqu_Vx_Mx,
6082 /* 0xf1 */ iemOp_InvalidNeedRM, iemOp_vpsllw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6083 /* 0xf2 */ iemOp_InvalidNeedRM, iemOp_vpslld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6084 /* 0xf3 */ iemOp_InvalidNeedRM, iemOp_vpsllq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6085 /* 0xf4 */ iemOp_InvalidNeedRM, iemOp_vpmuludq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6086 /* 0xf5 */ iemOp_InvalidNeedRM, iemOp_vpmaddwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6087 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_vpsadbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6088 /* 0xf7 */ iemOp_InvalidNeedRM, iemOp_vmaskmovdqu_Vdq_Udq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6089 /* 0xf8 */ iemOp_InvalidNeedRM, iemOp_vpsubb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6090 /* 0xf9 */ iemOp_InvalidNeedRM, iemOp_vpsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6091 /* 0xfa */ iemOp_InvalidNeedRM, iemOp_vpsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6092 /* 0xfb */ iemOp_InvalidNeedRM, iemOp_vpsubq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6093 /* 0xfc */ iemOp_InvalidNeedRM, iemOp_vpaddb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6094 /* 0xfd */ iemOp_InvalidNeedRM, iemOp_vpaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6095 /* 0xfe */ iemOp_InvalidNeedRM, iemOp_vpaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6096 /* 0xff */ IEMOP_X4(iemOp_vud0) /* ?? */
6097};
6098AssertCompile(RT_ELEMENTS(g_apfnVexMap1) == 1024);
6099/** @} */
6100
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