VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h@ 105221

Last change on this file since 105221 was 105221, checked in by vboxsync, 9 months ago

VMM/IEM: Implement vmulss instruction emulation, bugref:9898
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1/* $Id: IEMAllInstVexMap1.cpp.h 105221 2024-07-09 09:16:35Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstTwoByte0f.cpp.h is a legacy mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 1
33 * @{
34 */
35
36/**
37 * Common worker for AVX2 instructions on the forms:
38 * - vpxxx xmm0, xmm1, xmm2/mem128
39 * - vpxxx ymm0, ymm1, ymm2/mem256
40 *
41 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
42 */
43FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, PCIEMOPMEDIAF3, pImpl)
44{
45 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
46 if (IEM_IS_MODRM_REG_MODE(bRm))
47 {
48 /*
49 * Register, register.
50 */
51 if (pVCpu->iem.s.uVexLength)
52 {
53 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
54 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
55 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
56 IEM_MC_PREPARE_AVX_USAGE();
57
58 IEM_MC_LOCAL(X86YMMREG, uSrc1);
59 IEM_MC_ARG_LOCAL_REF(PCX86YMMREG, puSrc1, uSrc1, 1);
60 IEM_MC_FETCH_YREG_YMM(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
61 IEM_MC_LOCAL(X86YMMREG, uSrc2);
62 IEM_MC_ARG_LOCAL_REF(PCX86YMMREG, puSrc2, uSrc2, 2);
63 IEM_MC_FETCH_YREG_YMM(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
64 IEM_MC_LOCAL(X86YMMREG, uDst);
65 IEM_MC_ARG_LOCAL_REF(PX86YMMREG, puDst, uDst, 0);
66 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
67 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
68 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
69 IEM_MC_ADVANCE_RIP_AND_FINISH();
70 IEM_MC_END();
71 }
72 else
73 {
74 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
75 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
76 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
77 IEM_MC_PREPARE_AVX_USAGE();
78
79 IEM_MC_LOCAL(X86XMMREG, uDst);
80 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
81 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
82 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
83 IEM_MC_ARG(PCX86XMMREG, puSrc2, 2);
84 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
85 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
86 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
87 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
88 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
89 IEM_MC_ADVANCE_RIP_AND_FINISH();
90 IEM_MC_END();
91 }
92 }
93 else
94 {
95 /*
96 * Register, memory.
97 */
98 if (pVCpu->iem.s.uVexLength)
99 {
100 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
101 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
102 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
103 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
104 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
105 IEM_MC_PREPARE_AVX_USAGE();
106
107 IEM_MC_LOCAL(X86YMMREG, uSrc2);
108 IEM_MC_ARG_LOCAL_REF(PCX86YMMREG, puSrc2, uSrc2, 2);
109 IEM_MC_FETCH_MEM_YMM_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
110 IEM_MC_LOCAL(X86YMMREG, uSrc1);
111 IEM_MC_ARG_LOCAL_REF(PCX86YMMREG, puSrc1, uSrc1, 1);
112 IEM_MC_FETCH_YREG_YMM(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
113 IEM_MC_LOCAL(X86YMMREG, uDst);
114 IEM_MC_ARG_LOCAL_REF(PX86YMMREG, puDst, uDst, 0);
115 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
116 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
117 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
118 IEM_MC_ADVANCE_RIP_AND_FINISH();
119 IEM_MC_END();
120 }
121 else
122 {
123 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
124 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
125 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
126 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
127 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
128 IEM_MC_PREPARE_AVX_USAGE();
129
130 IEM_MC_LOCAL(X86XMMREG, uDst);
131 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
132 IEM_MC_LOCAL(X86XMMREG, uSrc2);
133 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 2);
134 IEM_MC_FETCH_MEM_XMM_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
135 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
136 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
137
138 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
139 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
140 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
141 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
142 IEM_MC_ADVANCE_RIP_AND_FINISH();
143 IEM_MC_END();
144 }
145 }
146}
147
148
149/**
150 * Common worker for scalar AVX/AVX2 instructions on the forms (addss,subss,etc.):
151 * - vxxxss xmm0, xmm1, xmm2/mem32
152 *
153 * Exceptions type 4. AVX cpuid check for 128-bit operation.
154 * Ignores VEX.L, from SDM:
155 * Software should ensure VADDSS is encoded with VEX.L=0.
156 * Encoding VADDSS with VEX.L=1 may encounter unpredictable behavior
157 * across different processor generations.
158 */
159FNIEMOP_DEF_1(iemOpCommonAvx_Vx_Hx_R32, PFNIEMAIMPLFPAVXF3U128R32, pfnU128)
160{
161 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
162 if (IEM_IS_MODRM_REG_MODE(bRm))
163 {
164 /*
165 * Register, register.
166 */
167 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
168 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
169 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
170 IEM_MC_PREPARE_AVX_USAGE();
171
172 IEM_MC_LOCAL(X86XMMREG, uDst);
173 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
174 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
175 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
176 IEM_MC_ARG(PCRTFLOAT32U, pr32Src2, 2);
177 IEM_MC_REF_XREG_R32_CONST(pr32Src2, IEM_GET_MODRM_RM(pVCpu, bRm));
178 IEM_MC_CALL_AVX_AIMPL_3(pfnU128, puDst, puSrc1, pr32Src2);
179 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
180 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
181 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
182 IEM_MC_ADVANCE_RIP_AND_FINISH();
183 IEM_MC_END();
184 }
185 else
186 {
187 /*
188 * Register, memory.
189 */
190 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
191 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
192 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
193 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
194 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
195 IEM_MC_PREPARE_AVX_USAGE();
196
197 IEM_MC_LOCAL(RTFLOAT32U, r32Src2);
198 IEM_MC_ARG_LOCAL_REF(PCRTFLOAT32U, pr32Src2, r32Src2, 2);
199 IEM_MC_FETCH_MEM_R32(r32Src2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
200 IEM_MC_LOCAL(X86XMMREG, uDst);
201 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
202 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
203 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
204 IEM_MC_CALL_AVX_AIMPL_3(pfnU128, puDst, puSrc1, pr32Src2);
205 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
206 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
207 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
208 IEM_MC_ADVANCE_RIP_AND_FINISH();
209 IEM_MC_END();
210 }
211}
212
213
214/**
215 * Common worker for scalar AVX/AVX2 instructions on the forms (addsd,subsd,etc.):
216 * - vxxxsd xmm0, xmm1, xmm2/mem64
217 *
218 * Exceptions type 4. AVX cpuid check for 128-bit operation.
219 * Ignores VEX.L, from SDM:
220 * Software should ensure VADDSD is encoded with VEX.L=0.
221 * Encoding VADDSD with VEX.L=1 may encounter unpredictable behavior
222 * across different processor generations.
223 */
224FNIEMOP_DEF_1(iemOpCommonAvx_Vx_Hx_R64, PFNIEMAIMPLFPAVXF3U128R64, pfnU128)
225{
226 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
227 if (IEM_IS_MODRM_REG_MODE(bRm))
228 {
229 /*
230 * Register, register.
231 */
232 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
233 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
234 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
235 IEM_MC_PREPARE_AVX_USAGE();
236
237 IEM_MC_LOCAL(X86XMMREG, uDst);
238 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
239 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
240 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
241 IEM_MC_ARG(PCRTFLOAT64U, pr64Src2, 2);
242 IEM_MC_REF_XREG_R64_CONST(pr64Src2, IEM_GET_MODRM_RM(pVCpu, bRm));
243 IEM_MC_CALL_AVX_AIMPL_3(pfnU128, puDst, puSrc1, pr64Src2);
244 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
245 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
246 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
247 IEM_MC_ADVANCE_RIP_AND_FINISH();
248 IEM_MC_END();
249 }
250 else
251 {
252 /*
253 * Register, memory.
254 */
255 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
256 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
257 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
258 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
259 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
260 IEM_MC_PREPARE_AVX_USAGE();
261
262 IEM_MC_LOCAL(RTFLOAT64U, r64Src2);
263 IEM_MC_ARG_LOCAL_REF(PCRTFLOAT64U, pr64Src2, r64Src2, 2);
264 IEM_MC_FETCH_MEM_R64(r64Src2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
265 IEM_MC_LOCAL(X86XMMREG, uDst);
266 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
267 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
268 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
269 IEM_MC_CALL_AVX_AIMPL_3(pfnU128, puDst, puSrc1, pr64Src2);
270 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
271 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
272 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
273 IEM_MC_ADVANCE_RIP_AND_FINISH();
274 IEM_MC_END();
275 }
276}
277
278
279/**
280 * Common worker for AVX2 instructions on the forms:
281 * - vpxxx xmm0, xmm1, xmm2/mem128
282 * - vpxxx ymm0, ymm1, ymm2/mem256
283 *
284 * Takes function table for function w/o implicit state parameter.
285 *
286 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
287 */
288FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, PCIEMOPMEDIAOPTF3, pImpl)
289{
290 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
291 if (IEM_IS_MODRM_REG_MODE(bRm))
292 {
293 /*
294 * Register, register.
295 */
296 if (pVCpu->iem.s.uVexLength)
297 {
298 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
299 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
300 IEM_MC_LOCAL(RTUINT256U, uDst);
301 IEM_MC_LOCAL(RTUINT256U, uSrc1);
302 IEM_MC_LOCAL(RTUINT256U, uSrc2);
303 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
304 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
305 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
306 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
307 IEM_MC_PREPARE_AVX_USAGE();
308 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
309 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
310 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
311 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
312 IEM_MC_ADVANCE_RIP_AND_FINISH();
313 IEM_MC_END();
314 }
315 else
316 {
317 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
318 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
319 IEM_MC_ARG(PRTUINT128U, puDst, 0);
320 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
321 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
322 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
323 IEM_MC_PREPARE_AVX_USAGE();
324 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
325 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
326 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
327 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
328 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
329 IEM_MC_ADVANCE_RIP_AND_FINISH();
330 IEM_MC_END();
331 }
332 }
333 else
334 {
335 /*
336 * Register, memory.
337 */
338 if (pVCpu->iem.s.uVexLength)
339 {
340 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
341 IEM_MC_LOCAL(RTUINT256U, uDst);
342 IEM_MC_LOCAL(RTUINT256U, uSrc1);
343 IEM_MC_LOCAL(RTUINT256U, uSrc2);
344 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
345 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
346 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
347 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
348
349 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
350 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
351 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
352 IEM_MC_PREPARE_AVX_USAGE();
353
354 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
355 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
356 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
357 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
358
359 IEM_MC_ADVANCE_RIP_AND_FINISH();
360 IEM_MC_END();
361 }
362 else
363 {
364 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
365 IEM_MC_LOCAL(RTUINT128U, uSrc2);
366 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
367 IEM_MC_ARG(PRTUINT128U, puDst, 0);
368 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
369 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
370
371 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
372 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
373 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
374 IEM_MC_PREPARE_AVX_USAGE();
375
376 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
377 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
378 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
379 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
380 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
381
382 IEM_MC_ADVANCE_RIP_AND_FINISH();
383 IEM_MC_END();
384 }
385 }
386}
387
388
389/**
390 * Common worker for AVX2 instructions on the forms:
391 * - vpunpckhxx xmm0, xmm1, xmm2/mem128
392 * - vpunpckhxx ymm0, ymm1, ymm2/mem256
393 *
394 * The 128-bit memory version of this instruction may elect to skip fetching the
395 * lower 64 bits of the operand. We, however, do not.
396 *
397 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
398 */
399FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, PCIEMOPMEDIAOPTF3, pImpl)
400{
401 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
402}
403
404
405/**
406 * Common worker for AVX2 instructions on the forms:
407 * - vpunpcklxx xmm0, xmm1, xmm2/mem128
408 * - vpunpcklxx ymm0, ymm1, ymm2/mem256
409 *
410 * The 128-bit memory version of this instruction may elect to skip fetching the
411 * higher 64 bits of the operand. We, however, do not.
412 *
413 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
414 */
415FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, PCIEMOPMEDIAOPTF3, pImpl)
416{
417 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
418}
419
420
421/**
422 * Common worker for AVX2 instructions on the forms:
423 * - vpxxx xmm0, xmm1/mem128
424 * - vpxxx ymm0, ymm1/mem256
425 *
426 * Takes function table for function w/o implicit state parameter.
427 *
428 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
429 */
430FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, PCIEMOPMEDIAOPTF2, pImpl)
431{
432 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
433 if (IEM_IS_MODRM_REG_MODE(bRm))
434 {
435 /*
436 * Register, register.
437 */
438 if (pVCpu->iem.s.uVexLength)
439 {
440 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
441 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
442 IEM_MC_LOCAL(RTUINT256U, uDst);
443 IEM_MC_LOCAL(RTUINT256U, uSrc);
444 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
445 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
446 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
447 IEM_MC_PREPARE_AVX_USAGE();
448 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
449 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
450 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
451 IEM_MC_ADVANCE_RIP_AND_FINISH();
452 IEM_MC_END();
453 }
454 else
455 {
456 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
457 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
458 IEM_MC_ARG(PRTUINT128U, puDst, 0);
459 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
460 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
461 IEM_MC_PREPARE_AVX_USAGE();
462 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
463 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
464 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
465 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
466 IEM_MC_ADVANCE_RIP_AND_FINISH();
467 IEM_MC_END();
468 }
469 }
470 else
471 {
472 /*
473 * Register, memory.
474 */
475 if (pVCpu->iem.s.uVexLength)
476 {
477 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
478 IEM_MC_LOCAL(RTUINT256U, uDst);
479 IEM_MC_LOCAL(RTUINT256U, uSrc);
480 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
481 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
482 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
483
484 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
485 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
486 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
487 IEM_MC_PREPARE_AVX_USAGE();
488
489 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
490 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
491 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
492
493 IEM_MC_ADVANCE_RIP_AND_FINISH();
494 IEM_MC_END();
495 }
496 else
497 {
498 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
499 IEM_MC_LOCAL(RTUINT128U, uSrc);
500 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
501 IEM_MC_ARG(PRTUINT128U, puDst, 0);
502 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
503
504 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
505 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
506 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
507 IEM_MC_PREPARE_AVX_USAGE();
508
509 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
510 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
511 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
512 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
513
514 IEM_MC_ADVANCE_RIP_AND_FINISH();
515 IEM_MC_END();
516 }
517 }
518}
519
520
521/* Opcode VEX.0F 0x00 - invalid */
522/* Opcode VEX.0F 0x01 - invalid */
523/* Opcode VEX.0F 0x02 - invalid */
524/* Opcode VEX.0F 0x03 - invalid */
525/* Opcode VEX.0F 0x04 - invalid */
526/* Opcode VEX.0F 0x05 - invalid */
527/* Opcode VEX.0F 0x06 - invalid */
528/* Opcode VEX.0F 0x07 - invalid */
529/* Opcode VEX.0F 0x08 - invalid */
530/* Opcode VEX.0F 0x09 - invalid */
531/* Opcode VEX.0F 0x0a - invalid */
532
533/** Opcode VEX.0F 0x0b. */
534FNIEMOP_DEF(iemOp_vud2)
535{
536 IEMOP_MNEMONIC(vud2, "vud2");
537 IEMOP_RAISE_INVALID_OPCODE_RET();
538}
539
540/* Opcode VEX.0F 0x0c - invalid */
541/* Opcode VEX.0F 0x0d - invalid */
542/* Opcode VEX.0F 0x0e - invalid */
543/* Opcode VEX.0F 0x0f - invalid */
544
545
546/**
547 * @opcode 0x10
548 * @oppfx none
549 * @opcpuid avx
550 * @opgroup og_avx_simdfp_datamove
551 * @opxcpttype 4UA
552 * @optest op1=1 op2=2 -> op1=2
553 * @optest op1=0 op2=-22 -> op1=-22
554 */
555FNIEMOP_DEF(iemOp_vmovups_Vps_Wps)
556{
557 IEMOP_MNEMONIC2(VEX_RM, VMOVUPS, vmovups, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
558 Assert(pVCpu->iem.s.uVexLength <= 1);
559 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
560 if (IEM_IS_MODRM_REG_MODE(bRm))
561 {
562 /*
563 * Register, register.
564 */
565 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
566 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
567 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
568 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
569 if (pVCpu->iem.s.uVexLength == 0)
570 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
571 IEM_GET_MODRM_RM(pVCpu, bRm));
572 else
573 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
574 IEM_GET_MODRM_RM(pVCpu, bRm));
575 IEM_MC_ADVANCE_RIP_AND_FINISH();
576 IEM_MC_END();
577 }
578 else if (pVCpu->iem.s.uVexLength == 0)
579 {
580 /*
581 * 128-bit: Register, Memory
582 */
583 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
584 IEM_MC_LOCAL(RTUINT128U, uSrc);
585 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
586
587 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
588 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
589 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
590 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
591
592 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
593 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
594
595 IEM_MC_ADVANCE_RIP_AND_FINISH();
596 IEM_MC_END();
597 }
598 else
599 {
600 /*
601 * 256-bit: Register, Memory
602 */
603 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
604 IEM_MC_LOCAL(RTUINT256U, uSrc);
605 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
606
607 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
608 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
609 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
610 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
611
612 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
613 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
614
615 IEM_MC_ADVANCE_RIP_AND_FINISH();
616 IEM_MC_END();
617 }
618}
619
620
621/**
622 * @opcode 0x10
623 * @oppfx 0x66
624 * @opcpuid avx
625 * @opgroup og_avx_simdfp_datamove
626 * @opxcpttype 4UA
627 * @optest op1=1 op2=2 -> op1=2
628 * @optest op1=0 op2=-22 -> op1=-22
629 */
630FNIEMOP_DEF(iemOp_vmovupd_Vpd_Wpd)
631{
632 IEMOP_MNEMONIC2(VEX_RM, VMOVUPD, vmovupd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
633 Assert(pVCpu->iem.s.uVexLength <= 1);
634 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
635 if (IEM_IS_MODRM_REG_MODE(bRm))
636 {
637 /*
638 * Register, register.
639 */
640 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
641 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
642 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
643 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
644 if (pVCpu->iem.s.uVexLength == 0)
645 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
646 IEM_GET_MODRM_RM(pVCpu, bRm));
647 else
648 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
649 IEM_GET_MODRM_RM(pVCpu, bRm));
650 IEM_MC_ADVANCE_RIP_AND_FINISH();
651 IEM_MC_END();
652 }
653 else if (pVCpu->iem.s.uVexLength == 0)
654 {
655 /*
656 * 128-bit: Memory, register.
657 */
658 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
659 IEM_MC_LOCAL(RTUINT128U, uSrc);
660 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
661
662 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
663 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
664 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
665 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
666
667 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
668 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
669
670 IEM_MC_ADVANCE_RIP_AND_FINISH();
671 IEM_MC_END();
672 }
673 else
674 {
675 /*
676 * 256-bit: Memory, register.
677 */
678 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
679 IEM_MC_LOCAL(RTUINT256U, uSrc);
680 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
681
682 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
683 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
684 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
685 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
686
687 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
688 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
689
690 IEM_MC_ADVANCE_RIP_AND_FINISH();
691 IEM_MC_END();
692 }
693}
694
695
696FNIEMOP_DEF(iemOp_vmovss_Vss_Hss_Wss)
697{
698 Assert(pVCpu->iem.s.uVexLength <= 1);
699 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
700 if (IEM_IS_MODRM_REG_MODE(bRm))
701 {
702 /**
703 * @opcode 0x10
704 * @oppfx 0xf3
705 * @opcodesub 11 mr/reg
706 * @opcpuid avx
707 * @opgroup og_avx_simdfp_datamerge
708 * @opxcpttype 5
709 * @optest op1=1 op2=0 op3=2 -> op1=2
710 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
711 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
712 * @optest op1=3 op2=-2 op3=0x77 -> op1=-8589934473
713 * @note HssHi refers to bits 127:32.
714 */
715 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
716 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
717 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
718 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
719 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
720 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
721 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
722 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
723 IEM_MC_ADVANCE_RIP_AND_FINISH();
724 IEM_MC_END();
725 }
726 else
727 {
728 /**
729 * @opdone
730 * @opcode 0x10
731 * @oppfx 0xf3
732 * @opcodesub !11 mr/reg
733 * @opcpuid avx
734 * @opgroup og_avx_simdfp_datamove
735 * @opxcpttype 5
736 * @opfunction iemOp_vmovss_Vss_Hss_Wss
737 * @optest op1=1 op2=2 -> op1=2
738 * @optest op1=0 op2=-22 -> op1=-22
739 */
740 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSS, vmovss, VssZx_WO, Md, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
741 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
742 IEM_MC_LOCAL(uint32_t, uSrc);
743 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
744
745 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
746 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
747 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
748 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
749
750 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
751 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
752
753 IEM_MC_ADVANCE_RIP_AND_FINISH();
754 IEM_MC_END();
755 }
756}
757
758
759FNIEMOP_DEF(iemOp_vmovsd_Vsd_Hsd_Wsd)
760{
761 Assert(pVCpu->iem.s.uVexLength <= 1);
762 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
763 if (IEM_IS_MODRM_REG_MODE(bRm))
764 {
765 /**
766 * @opcode 0x10
767 * @oppfx 0xf2
768 * @opcodesub 11 mr/reg
769 * @opcpuid avx
770 * @opgroup og_avx_simdfp_datamerge
771 * @opxcpttype 5
772 * @optest op1=1 op2=0 op3=2 -> op1=2
773 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
774 * @optest op1=3 op2=-1 op3=0x77 ->
775 * op1=0xffffffffffffffff0000000000000077
776 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x420000000000000077
777 */
778 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
779 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
780 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
781
782 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
783 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
784 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
785 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
786 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
787 IEM_MC_ADVANCE_RIP_AND_FINISH();
788 IEM_MC_END();
789 }
790 else
791 {
792 /**
793 * @opdone
794 * @opcode 0x10
795 * @oppfx 0xf2
796 * @opcodesub !11 mr/reg
797 * @opcpuid avx
798 * @opgroup og_avx_simdfp_datamove
799 * @opxcpttype 5
800 * @opfunction iemOp_vmovsd_Vsd_Hsd_Wsd
801 * @optest op1=1 op2=2 -> op1=2
802 * @optest op1=0 op2=-22 -> op1=-22
803 */
804 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSD, vmovsd, VsdZx_WO, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
805 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
806 IEM_MC_LOCAL(uint64_t, uSrc);
807 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
808
809 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
810 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
811 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
812 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
813
814 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
815 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
816
817 IEM_MC_ADVANCE_RIP_AND_FINISH();
818 IEM_MC_END();
819 }
820}
821
822
823/**
824 * @opcode 0x11
825 * @oppfx none
826 * @opcpuid avx
827 * @opgroup og_avx_simdfp_datamove
828 * @opxcpttype 4UA
829 * @optest op1=1 op2=2 -> op1=2
830 * @optest op1=0 op2=-22 -> op1=-22
831 */
832FNIEMOP_DEF(iemOp_vmovups_Wps_Vps)
833{
834 IEMOP_MNEMONIC2(VEX_MR, VMOVUPS, vmovups, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
835 Assert(pVCpu->iem.s.uVexLength <= 1);
836 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
837 if (IEM_IS_MODRM_REG_MODE(bRm))
838 {
839 /*
840 * Register, register.
841 */
842 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
843 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
844 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
845 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
846 if (pVCpu->iem.s.uVexLength == 0)
847 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
848 IEM_GET_MODRM_REG(pVCpu, bRm));
849 else
850 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
851 IEM_GET_MODRM_REG(pVCpu, bRm));
852 IEM_MC_ADVANCE_RIP_AND_FINISH();
853 IEM_MC_END();
854 }
855 else if (pVCpu->iem.s.uVexLength == 0)
856 {
857 /*
858 * 128-bit: Memory, register.
859 */
860 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
861 IEM_MC_LOCAL(RTUINT128U, uSrc);
862 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
863
864 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
865 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
866 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
867 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
868
869 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
870 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
871
872 IEM_MC_ADVANCE_RIP_AND_FINISH();
873 IEM_MC_END();
874 }
875 else
876 {
877 /*
878 * 256-bit: Memory, register.
879 */
880 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
881 IEM_MC_LOCAL(RTUINT256U, uSrc);
882 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
883
884 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
885 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
886 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
887 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
888
889 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
890 IEM_MC_STORE_MEM_U256_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
891
892 IEM_MC_ADVANCE_RIP_AND_FINISH();
893 IEM_MC_END();
894 }
895}
896
897
898/**
899 * @opcode 0x11
900 * @oppfx 0x66
901 * @opcpuid avx
902 * @opgroup og_avx_simdfp_datamove
903 * @opxcpttype 4UA
904 * @optest op1=1 op2=2 -> op1=2
905 * @optest op1=0 op2=-22 -> op1=-22
906 */
907FNIEMOP_DEF(iemOp_vmovupd_Wpd_Vpd)
908{
909 IEMOP_MNEMONIC2(VEX_MR, VMOVUPD, vmovupd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
910 Assert(pVCpu->iem.s.uVexLength <= 1);
911 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
912 if (IEM_IS_MODRM_REG_MODE(bRm))
913 {
914 /*
915 * Register, register.
916 */
917 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
918 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
919 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
920 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
921 if (pVCpu->iem.s.uVexLength == 0)
922 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
923 IEM_GET_MODRM_REG(pVCpu, bRm));
924 else
925 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
926 IEM_GET_MODRM_REG(pVCpu, bRm));
927 IEM_MC_ADVANCE_RIP_AND_FINISH();
928 IEM_MC_END();
929 }
930 else if (pVCpu->iem.s.uVexLength == 0)
931 {
932 /*
933 * 128-bit: Memory, register.
934 */
935 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
936 IEM_MC_LOCAL(RTUINT128U, uSrc);
937 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
938
939 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
940 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
941 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
942 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
943
944 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
945 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
946
947 IEM_MC_ADVANCE_RIP_AND_FINISH();
948 IEM_MC_END();
949 }
950 else
951 {
952 /*
953 * 256-bit: Memory, register.
954 */
955 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
956 IEM_MC_LOCAL(RTUINT256U, uSrc);
957 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
958
959 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
960 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
961 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
962 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
963
964 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
965 IEM_MC_STORE_MEM_U256_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
966
967 IEM_MC_ADVANCE_RIP_AND_FINISH();
968 IEM_MC_END();
969 }
970}
971
972
973FNIEMOP_DEF(iemOp_vmovss_Wss_Hss_Vss)
974{
975 Assert(pVCpu->iem.s.uVexLength <= 1);
976 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
977 if (IEM_IS_MODRM_REG_MODE(bRm))
978 {
979 /**
980 * @opcode 0x11
981 * @oppfx 0xf3
982 * @opcodesub 11 mr/reg
983 * @opcpuid avx
984 * @opgroup og_avx_simdfp_datamerge
985 * @opxcpttype 5
986 * @optest op1=1 op2=0 op3=2 -> op1=2
987 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
988 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
989 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x4200000077
990 */
991 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
992 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
993 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
994
995 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
996 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
997 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
998 IEM_GET_MODRM_REG(pVCpu, bRm),
999 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
1000 IEM_MC_ADVANCE_RIP_AND_FINISH();
1001 IEM_MC_END();
1002 }
1003 else
1004 {
1005 /**
1006 * @opdone
1007 * @opcode 0x11
1008 * @oppfx 0xf3
1009 * @opcodesub !11 mr/reg
1010 * @opcpuid avx
1011 * @opgroup og_avx_simdfp_datamove
1012 * @opxcpttype 5
1013 * @opfunction iemOp_vmovss_Vss_Hss_Wss
1014 * @optest op1=1 op2=2 -> op1=2
1015 * @optest op1=0 op2=-22 -> op1=-22
1016 */
1017 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
1018 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1019 IEM_MC_LOCAL(uint32_t, uSrc);
1020 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1021
1022 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1023 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1024 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1025 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1026
1027 IEM_MC_FETCH_YREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1028 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1029
1030 IEM_MC_ADVANCE_RIP_AND_FINISH();
1031 IEM_MC_END();
1032 }
1033}
1034
1035
1036FNIEMOP_DEF(iemOp_vmovsd_Wsd_Hsd_Vsd)
1037{
1038 Assert(pVCpu->iem.s.uVexLength <= 1);
1039 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1040 if (IEM_IS_MODRM_REG_MODE(bRm))
1041 {
1042 /**
1043 * @opcode 0x11
1044 * @oppfx 0xf2
1045 * @opcodesub 11 mr/reg
1046 * @opcpuid avx
1047 * @opgroup og_avx_simdfp_datamerge
1048 * @opxcpttype 5
1049 * @optest op1=1 op2=0 op3=2 -> op1=2
1050 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
1051 * @optest op1=3 op2=-1 op3=0x77 ->
1052 * op1=0xffffffffffffffff0000000000000077
1053 * @optest op2=0x42 op3=0x77 -> op1=0x420000000000000077
1054 */
1055 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
1056 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1057 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
1058
1059 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1060 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1061 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
1062 IEM_GET_MODRM_REG(pVCpu, bRm),
1063 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
1064 IEM_MC_ADVANCE_RIP_AND_FINISH();
1065 IEM_MC_END();
1066 }
1067 else
1068 {
1069 /**
1070 * @opdone
1071 * @opcode 0x11
1072 * @oppfx 0xf2
1073 * @opcodesub !11 mr/reg
1074 * @opcpuid avx
1075 * @opgroup og_avx_simdfp_datamove
1076 * @opxcpttype 5
1077 * @opfunction iemOp_vmovsd_Wsd_Hsd_Vsd
1078 * @optest op1=1 op2=2 -> op1=2
1079 * @optest op1=0 op2=-22 -> op1=-22
1080 */
1081 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSD, vmovsd, Mq_WO, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
1082 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1083 IEM_MC_LOCAL(uint64_t, uSrc);
1084 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1085
1086 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1087 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1088 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1089 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1090
1091 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
1092 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1093
1094 IEM_MC_ADVANCE_RIP_AND_FINISH();
1095 IEM_MC_END();
1096 }
1097}
1098
1099
1100FNIEMOP_DEF(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps)
1101{
1102 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1103 if (IEM_IS_MODRM_REG_MODE(bRm))
1104 {
1105 /**
1106 * @opcode 0x12
1107 * @opcodesub 11 mr/reg
1108 * @oppfx none
1109 * @opcpuid avx
1110 * @opgroup og_avx_simdfp_datamerge
1111 * @opxcpttype 7LZ
1112 * @optest op2=0x2200220122022203
1113 * op3=0x3304330533063307
1114 * -> op1=0x22002201220222033304330533063307
1115 * @optest op2=-1 op3=-42 -> op1=-42
1116 * @note op3 and op2 are only the 8-byte high XMM register halfs.
1117 */
1118 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1119 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1120 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1121
1122 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1123 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1124 IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1125 IEM_GET_MODRM_RM(pVCpu, bRm),
1126 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1127
1128 IEM_MC_ADVANCE_RIP_AND_FINISH();
1129 IEM_MC_END();
1130 }
1131 else
1132 {
1133 /**
1134 * @opdone
1135 * @opcode 0x12
1136 * @opcodesub !11 mr/reg
1137 * @oppfx none
1138 * @opcpuid avx
1139 * @opgroup og_avx_simdfp_datamove
1140 * @opxcpttype 5LZ
1141 * @opfunction iemOp_vmovlps_Vq_Hq_Mq__vmovhlps
1142 * @optest op1=1 op2=0 op3=0 -> op1=0
1143 * @optest op1=0 op2=-1 op3=-1 -> op1=-1
1144 * @optest op1=1 op2=2 op3=3 -> op1=0x20000000000000003
1145 * @optest op2=-1 op3=0x42 -> op1=0xffffffffffffffff0000000000000042
1146 */
1147 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPS, vmovlps, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1148
1149 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1150 IEM_MC_LOCAL(uint64_t, uSrc);
1151 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1152
1153 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1154 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1155 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1156 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1157
1158 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1159 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1160 uSrc,
1161 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1162
1163 IEM_MC_ADVANCE_RIP_AND_FINISH();
1164 IEM_MC_END();
1165 }
1166}
1167
1168
1169/**
1170 * @opcode 0x12
1171 * @opcodesub !11 mr/reg
1172 * @oppfx 0x66
1173 * @opcpuid avx
1174 * @opgroup og_avx_pcksclr_datamerge
1175 * @opxcpttype 5LZ
1176 * @optest op2=0 op3=2 -> op1=2
1177 * @optest op2=0x22 op3=0x33 -> op1=0x220000000000000033
1178 * @optest op2=0xfffffff0fffffff1 op3=0xeeeeeee8eeeeeee9
1179 * -> op1=0xfffffff0fffffff1eeeeeee8eeeeeee9
1180 */
1181FNIEMOP_DEF(iemOp_vmovlpd_Vq_Hq_Mq)
1182{
1183 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1184 if (IEM_IS_MODRM_MEM_MODE(bRm))
1185 {
1186 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPD, vmovlpd, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1187
1188 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1189 IEM_MC_LOCAL(uint64_t, uSrc);
1190 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1191
1192 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1193 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1194 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1195 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1196
1197 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1198 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1199 uSrc,
1200 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1201
1202 IEM_MC_ADVANCE_RIP_AND_FINISH();
1203 IEM_MC_END();
1204 }
1205
1206 /**
1207 * @opdone
1208 * @opmnemonic udvex660f12m3
1209 * @opcode 0x12
1210 * @opcodesub 11 mr/reg
1211 * @oppfx 0x66
1212 * @opunused immediate
1213 * @opcpuid avx
1214 * @optest ->
1215 */
1216 else
1217 IEMOP_RAISE_INVALID_OPCODE_RET();
1218}
1219
1220
1221/**
1222 * @opcode 0x12
1223 * @oppfx 0xf3
1224 * @opcpuid avx
1225 * @opgroup og_avx_pcksclr_datamove
1226 * @opxcpttype 4
1227 * @optest vex.l==0 / op1=-1 op2=0xdddddddd00000002eeeeeeee00000001
1228 * -> op1=0x00000002000000020000000100000001
1229 * @optest vex.l==1 /
1230 * op2=0xbbbbbbbb00000004cccccccc00000003dddddddd00000002eeeeeeee00000001
1231 * -> op1=0x0000000400000004000000030000000300000002000000020000000100000001
1232 */
1233FNIEMOP_DEF(iemOp_vmovsldup_Vx_Wx)
1234{
1235 IEMOP_MNEMONIC2(VEX_RM, VMOVSLDUP, vmovsldup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1236 Assert(pVCpu->iem.s.uVexLength <= 1);
1237 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1238 if (IEM_IS_MODRM_REG_MODE(bRm))
1239 {
1240 /*
1241 * Register, register.
1242 */
1243 if (pVCpu->iem.s.uVexLength == 0)
1244 {
1245 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1246 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1247 IEM_MC_LOCAL(RTUINT128U, uSrc);
1248
1249 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1250 IEM_MC_PREPARE_AVX_USAGE();
1251
1252 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1253 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1254 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1255 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1256 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1257 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1258
1259 IEM_MC_ADVANCE_RIP_AND_FINISH();
1260 IEM_MC_END();
1261 }
1262 else
1263 {
1264 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1265 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1266 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1267 IEM_MC_PREPARE_AVX_USAGE();
1268
1269 IEM_MC_LOCAL(RTUINT256U, uSrc);
1270 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1271 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1272 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1273 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1274 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1275 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 4);
1276 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 4);
1277 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 6);
1278 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 6);
1279 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1280
1281 IEM_MC_ADVANCE_RIP_AND_FINISH();
1282 IEM_MC_END();
1283 }
1284 }
1285 else
1286 {
1287 /*
1288 * Register, memory.
1289 */
1290 if (pVCpu->iem.s.uVexLength == 0)
1291 {
1292 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1293 IEM_MC_LOCAL(RTUINT128U, uSrc);
1294 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1295
1296 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1297 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1298 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1299 IEM_MC_PREPARE_AVX_USAGE();
1300
1301 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1302 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1303 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1304 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1305 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1306 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1307
1308 IEM_MC_ADVANCE_RIP_AND_FINISH();
1309 IEM_MC_END();
1310 }
1311 else
1312 {
1313 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1314 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1315 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1316 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1317 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1318 IEM_MC_PREPARE_AVX_USAGE();
1319
1320 IEM_MC_LOCAL(RTUINT256U, uSrc);
1321 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1322
1323 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1324 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1325 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1326 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1327 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 4);
1328 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 4);
1329 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 6);
1330 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 6);
1331 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1332
1333 IEM_MC_ADVANCE_RIP_AND_FINISH();
1334 IEM_MC_END();
1335 }
1336 }
1337}
1338
1339
1340/**
1341 * @opcode 0x12
1342 * @oppfx 0xf2
1343 * @opcpuid avx
1344 * @opgroup og_avx_pcksclr_datamove
1345 * @opxcpttype 5
1346 * @optest vex.l==0 / op2=0xddddddddeeeeeeee2222222211111111
1347 * -> op1=0x22222222111111112222222211111111
1348 * @optest vex.l==1 / op2=0xbbbbbbbbcccccccc4444444433333333ddddddddeeeeeeee2222222211111111
1349 * -> op1=0x4444444433333333444444443333333322222222111111112222222211111111
1350 */
1351FNIEMOP_DEF(iemOp_vmovddup_Vx_Wx)
1352{
1353 IEMOP_MNEMONIC2(VEX_RM, VMOVDDUP, vmovddup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1354 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1355 if (IEM_IS_MODRM_REG_MODE(bRm))
1356 {
1357 /*
1358 * Register, register.
1359 */
1360 if (pVCpu->iem.s.uVexLength == 0)
1361 {
1362 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1363 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1364 IEM_MC_LOCAL(uint64_t, uSrc);
1365
1366 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1367 IEM_MC_PREPARE_AVX_USAGE();
1368
1369 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /* a_iQword*/);
1370 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc);
1371 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc);
1372 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1373
1374 IEM_MC_ADVANCE_RIP_AND_FINISH();
1375 IEM_MC_END();
1376 }
1377 else
1378 {
1379 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1380 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1381 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1382 IEM_MC_PREPARE_AVX_USAGE();
1383
1384 IEM_MC_LOCAL(uint64_t, uSrc1);
1385 IEM_MC_LOCAL(uint64_t, uSrc2);
1386 IEM_MC_FETCH_YREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /* a_iQword*/);
1387 IEM_MC_FETCH_YREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 2 /* a_iQword*/);
1388
1389 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc1);
1390 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc1);
1391 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 2 /* a_iQword*/, uSrc2);
1392 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 3 /* a_iQword*/, uSrc2);
1393 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1394
1395 IEM_MC_ADVANCE_RIP_AND_FINISH();
1396 IEM_MC_END();
1397 }
1398 }
1399 else
1400 {
1401 /*
1402 * Register, memory.
1403 */
1404 if (pVCpu->iem.s.uVexLength == 0)
1405 {
1406 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1407 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1408 IEM_MC_LOCAL(uint64_t, uSrc);
1409
1410 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1411 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1412 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1413 IEM_MC_PREPARE_AVX_USAGE();
1414
1415 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1416 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc);
1417 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc);
1418 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1419
1420 IEM_MC_ADVANCE_RIP_AND_FINISH();
1421 IEM_MC_END();
1422 }
1423 else
1424 {
1425 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1426 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1427
1428 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1429 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1430 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1431 IEM_MC_PREPARE_AVX_USAGE();
1432
1433 IEM_MC_LOCAL(RTUINT256U, uSrc);
1434 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1435
1436 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQwDst*/, uSrc, 0 /*a_iQwSrc*/);
1437 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /*a_iQwDst*/, uSrc, 0 /*a_iQwSrc*/);
1438 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2 /*a_iQwDst*/, uSrc, 2 /*a_iQwSrc*/);
1439 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3 /*a_iQwDst*/, uSrc, 2 /*a_iQwSrc*/);
1440 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1441
1442 IEM_MC_ADVANCE_RIP_AND_FINISH();
1443 IEM_MC_END();
1444 }
1445 }
1446}
1447
1448
1449/**
1450 * @opcode 0x13
1451 * @opcodesub !11 mr/reg
1452 * @oppfx none
1453 * @opcpuid avx
1454 * @opgroup og_avx_simdfp_datamove
1455 * @opxcpttype 5
1456 * @optest op1=1 op2=2 -> op1=2
1457 * @optest op1=0 op2=-42 -> op1=-42
1458 */
1459FNIEMOP_DEF(iemOp_vmovlps_Mq_Vq)
1460{
1461 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1462 if (IEM_IS_MODRM_MEM_MODE(bRm))
1463 {
1464 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPS, vmovlps, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1465
1466 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1467 IEM_MC_LOCAL(uint64_t, uSrc);
1468 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1469
1470 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1471 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1472 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1473 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1474
1475 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
1476 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1477
1478 IEM_MC_ADVANCE_RIP_AND_FINISH();
1479 IEM_MC_END();
1480 }
1481
1482 /**
1483 * @opdone
1484 * @opmnemonic udvex0f13m3
1485 * @opcode 0x13
1486 * @opcodesub 11 mr/reg
1487 * @oppfx none
1488 * @opunused immediate
1489 * @opcpuid avx
1490 * @optest ->
1491 */
1492 else
1493 IEMOP_RAISE_INVALID_OPCODE_RET();
1494}
1495
1496
1497/**
1498 * @opcode 0x13
1499 * @opcodesub !11 mr/reg
1500 * @oppfx 0x66
1501 * @opcpuid avx
1502 * @opgroup og_avx_pcksclr_datamove
1503 * @opxcpttype 5
1504 * @optest op1=1 op2=2 -> op1=2
1505 * @optest op1=0 op2=-42 -> op1=-42
1506 */
1507FNIEMOP_DEF(iemOp_vmovlpd_Mq_Vq)
1508{
1509 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1510 if (IEM_IS_MODRM_MEM_MODE(bRm))
1511 {
1512 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPD, vmovlpd, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1513 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1514 IEM_MC_LOCAL(uint64_t, uSrc);
1515 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1516
1517 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1518 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1519 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1520 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1521
1522 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
1523 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1524
1525 IEM_MC_ADVANCE_RIP_AND_FINISH();
1526 IEM_MC_END();
1527 }
1528
1529 /**
1530 * @opdone
1531 * @opmnemonic udvex660f13m3
1532 * @opcode 0x13
1533 * @opcodesub 11 mr/reg
1534 * @oppfx 0x66
1535 * @opunused immediate
1536 * @opcpuid avx
1537 * @optest ->
1538 */
1539 else
1540 IEMOP_RAISE_INVALID_OPCODE_RET();
1541}
1542
1543/* Opcode VEX.F3.0F 0x13 - invalid */
1544/* Opcode VEX.F2.0F 0x13 - invalid */
1545
1546/** Opcode VEX.0F 0x14 - vunpcklps Vx, Hx, Wx*/
1547FNIEMOP_DEF(iemOp_vunpcklps_Vx_Hx_Wx)
1548{
1549 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPS, vunpcklps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1550 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklps);
1551 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1552}
1553
1554
1555/** Opcode VEX.66.0F 0x14 - vunpcklpd Vx,Hx,Wx */
1556FNIEMOP_DEF(iemOp_vunpcklpd_Vx_Hx_Wx)
1557{
1558 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPD, vunpcklpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1559 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklpd);
1560 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1561}
1562
1563
1564/* Opcode VEX.F3.0F 0x14 - invalid */
1565/* Opcode VEX.F2.0F 0x14 - invalid */
1566
1567
1568/** Opcode VEX.0F 0x15 - vunpckhps Vx, Hx, Wx */
1569FNIEMOP_DEF(iemOp_vunpckhps_Vx_Hx_Wx)
1570{
1571 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPS, vunpckhps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1572 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhps);
1573 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1574}
1575
1576
1577/** Opcode VEX.66.0F 0x15 - vunpckhpd Vx,Hx,Wx */
1578FNIEMOP_DEF(iemOp_vunpckhpd_Vx_Hx_Wx)
1579{
1580 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPD, vunpckhpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1581 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhpd);
1582 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1583}
1584
1585
1586/* Opcode VEX.F3.0F 0x15 - invalid */
1587/* Opcode VEX.F2.0F 0x15 - invalid */
1588
1589
1590FNIEMOP_DEF(iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq)
1591{
1592 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1593 if (IEM_IS_MODRM_REG_MODE(bRm))
1594 {
1595 /**
1596 * @opcode 0x16
1597 * @opcodesub 11 mr/reg
1598 * @oppfx none
1599 * @opcpuid avx
1600 * @opgroup og_avx_simdfp_datamerge
1601 * @opxcpttype 7LZ
1602 */
1603 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVLHPS, vmovlhps, Vq_WO, Hq, Uq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1604
1605 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1606 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1607
1608 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1609 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1610 IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1611 IEM_GET_MODRM_RM(pVCpu, bRm),
1612 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1613
1614 IEM_MC_ADVANCE_RIP_AND_FINISH();
1615 IEM_MC_END();
1616 }
1617 else
1618 {
1619 /**
1620 * @opdone
1621 * @opcode 0x16
1622 * @opcodesub !11 mr/reg
1623 * @oppfx none
1624 * @opcpuid avx
1625 * @opgroup og_avx_simdfp_datamove
1626 * @opxcpttype 5LZ
1627 * @opfunction iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq
1628 */
1629 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPS, vmovhps, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1630
1631 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1632 IEM_MC_LOCAL(uint64_t, uSrc);
1633 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1634
1635 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1636 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1637 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1638 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1639
1640 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1641 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1642 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1643 uSrc);
1644
1645 IEM_MC_ADVANCE_RIP_AND_FINISH();
1646 IEM_MC_END();
1647 }
1648}
1649
1650
1651/**
1652 * @opcode 0x16
1653 * @opcodesub !11 mr/reg
1654 * @oppfx 0x66
1655 * @opcpuid avx
1656 * @opgroup og_avx_pcksclr_datamerge
1657 * @opxcpttype 5LZ
1658 */
1659FNIEMOP_DEF(iemOp_vmovhpd_Vdq_Hq_Mq)
1660{
1661 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1662 if (IEM_IS_MODRM_MEM_MODE(bRm))
1663 {
1664 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPD, vmovhpd, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1665
1666 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1667 IEM_MC_LOCAL(uint64_t, uSrc);
1668 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1669
1670 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1671 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1672 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1673 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1674
1675 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1676 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1677 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1678 uSrc);
1679
1680 IEM_MC_ADVANCE_RIP_AND_FINISH();
1681 IEM_MC_END();
1682 }
1683
1684 /**
1685 * @opdone
1686 * @opmnemonic udvex660f16m3
1687 * @opcode 0x12
1688 * @opcodesub 11 mr/reg
1689 * @oppfx 0x66
1690 * @opunused immediate
1691 * @opcpuid avx
1692 * @optest ->
1693 */
1694 else
1695 IEMOP_RAISE_INVALID_OPCODE_RET();
1696}
1697
1698
1699/** Opcode VEX.F3.0F 0x16 - vmovshdup Vx, Wx */
1700/**
1701 * @opcode 0x16
1702 * @oppfx 0xf3
1703 * @opcpuid avx
1704 * @opgroup og_avx_pcksclr_datamove
1705 * @opxcpttype 4
1706 */
1707FNIEMOP_DEF(iemOp_vmovshdup_Vx_Wx)
1708{
1709 IEMOP_MNEMONIC2(VEX_RM, VMOVSHDUP, vmovshdup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1710 Assert(pVCpu->iem.s.uVexLength <= 1);
1711 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1712 if (IEM_IS_MODRM_REG_MODE(bRm))
1713 {
1714 /*
1715 * Register, register.
1716 */
1717 if (pVCpu->iem.s.uVexLength == 0)
1718 {
1719 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1720 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1721 IEM_MC_LOCAL(RTUINT128U, uSrc);
1722
1723 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1724 IEM_MC_PREPARE_AVX_USAGE();
1725
1726 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1727 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1728 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1729 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1730 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1731 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1732
1733 IEM_MC_ADVANCE_RIP_AND_FINISH();
1734 IEM_MC_END();
1735 }
1736 else
1737 {
1738 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1739 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1740 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1741 IEM_MC_PREPARE_AVX_USAGE();
1742
1743 IEM_MC_LOCAL(RTUINT256U, uSrc);
1744 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1745 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1746 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1747 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1748 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1749 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 5);
1750 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 5);
1751 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 7);
1752 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 7);
1753 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1754
1755 IEM_MC_ADVANCE_RIP_AND_FINISH();
1756 IEM_MC_END();
1757 }
1758 }
1759 else
1760 {
1761 /*
1762 * Register, memory.
1763 */
1764 if (pVCpu->iem.s.uVexLength == 0)
1765 {
1766 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1767 IEM_MC_LOCAL(RTUINT128U, uSrc);
1768 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1769
1770 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1771 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1772 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1773 IEM_MC_PREPARE_AVX_USAGE();
1774
1775 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1776 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1777 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1778 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1779 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1780 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1781
1782 IEM_MC_ADVANCE_RIP_AND_FINISH();
1783 IEM_MC_END();
1784 }
1785 else
1786 {
1787 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1788 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1789 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1790 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1791 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1792 IEM_MC_PREPARE_AVX_USAGE();
1793
1794 IEM_MC_LOCAL(RTUINT256U, uSrc);
1795 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1796
1797 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1798 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1799 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1800 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1801 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 5);
1802 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 5);
1803 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 7);
1804 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 7);
1805 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1806
1807 IEM_MC_ADVANCE_RIP_AND_FINISH();
1808 IEM_MC_END();
1809 }
1810 }
1811}
1812
1813
1814/* Opcode VEX.F2.0F 0x16 - invalid */
1815
1816
1817/**
1818 * @opcode 0x17
1819 * @opcodesub !11 mr/reg
1820 * @oppfx none
1821 * @opcpuid avx
1822 * @opgroup og_avx_simdfp_datamove
1823 * @opxcpttype 5
1824 */
1825FNIEMOP_DEF(iemOp_vmovhps_Mq_Vq)
1826{
1827 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1828 if (IEM_IS_MODRM_MEM_MODE(bRm))
1829 {
1830 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPS, vmovhps, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1831
1832 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1833 IEM_MC_LOCAL(uint64_t, uSrc);
1834 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1835
1836 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1837 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1838 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1839 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1840
1841 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 1 /*a_iQWord*/);
1842 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1843
1844 IEM_MC_ADVANCE_RIP_AND_FINISH();
1845 IEM_MC_END();
1846 }
1847
1848 /**
1849 * @opdone
1850 * @opmnemonic udvex0f17m3
1851 * @opcode 0x17
1852 * @opcodesub 11 mr/reg
1853 * @oppfx none
1854 * @opunused immediate
1855 * @opcpuid avx
1856 * @optest ->
1857 */
1858 else
1859 IEMOP_RAISE_INVALID_OPCODE_RET();
1860}
1861
1862
1863/**
1864 * @opcode 0x17
1865 * @opcodesub !11 mr/reg
1866 * @oppfx 0x66
1867 * @opcpuid avx
1868 * @opgroup og_avx_pcksclr_datamove
1869 * @opxcpttype 5
1870 */
1871FNIEMOP_DEF(iemOp_vmovhpd_Mq_Vq)
1872{
1873 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1874 if (IEM_IS_MODRM_MEM_MODE(bRm))
1875 {
1876 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPD, vmovhpd, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1877
1878 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1879 IEM_MC_LOCAL(uint64_t, uSrc);
1880 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1881
1882 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1883 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1884 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1885 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1886
1887 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 1 /*a_iQWord*/);
1888 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1889
1890 IEM_MC_ADVANCE_RIP_AND_FINISH();
1891 IEM_MC_END();
1892 }
1893
1894 /**
1895 * @opdone
1896 * @opmnemonic udvex660f17m3
1897 * @opcode 0x17
1898 * @opcodesub 11 mr/reg
1899 * @oppfx 0x66
1900 * @opunused immediate
1901 * @opcpuid avx
1902 * @optest ->
1903 */
1904 else
1905 IEMOP_RAISE_INVALID_OPCODE_RET();
1906}
1907
1908
1909/* Opcode VEX.F3.0F 0x17 - invalid */
1910/* Opcode VEX.F2.0F 0x17 - invalid */
1911
1912
1913/* Opcode VEX.0F 0x18 - invalid */
1914/* Opcode VEX.0F 0x19 - invalid */
1915/* Opcode VEX.0F 0x1a - invalid */
1916/* Opcode VEX.0F 0x1b - invalid */
1917/* Opcode VEX.0F 0x1c - invalid */
1918/* Opcode VEX.0F 0x1d - invalid */
1919/* Opcode VEX.0F 0x1e - invalid */
1920/* Opcode VEX.0F 0x1f - invalid */
1921
1922/* Opcode VEX.0F 0x20 - invalid */
1923/* Opcode VEX.0F 0x21 - invalid */
1924/* Opcode VEX.0F 0x22 - invalid */
1925/* Opcode VEX.0F 0x23 - invalid */
1926/* Opcode VEX.0F 0x24 - invalid */
1927/* Opcode VEX.0F 0x25 - invalid */
1928/* Opcode VEX.0F 0x26 - invalid */
1929/* Opcode VEX.0F 0x27 - invalid */
1930
1931/**
1932 * @opcode 0x28
1933 * @oppfx none
1934 * @opcpuid avx
1935 * @opgroup og_avx_pcksclr_datamove
1936 * @opxcpttype 1
1937 * @optest op1=1 op2=2 -> op1=2
1938 * @optest op1=0 op2=-42 -> op1=-42
1939 * @note Almost identical to vmovapd.
1940 */
1941FNIEMOP_DEF(iemOp_vmovaps_Vps_Wps)
1942{
1943 IEMOP_MNEMONIC2(VEX_RM, VMOVAPS, vmovaps, Vps_WO, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1944 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1945 Assert(pVCpu->iem.s.uVexLength <= 1);
1946 if (IEM_IS_MODRM_REG_MODE(bRm))
1947 {
1948 /*
1949 * Register, register.
1950 */
1951 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1952 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1953
1954 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1955 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1956 if (pVCpu->iem.s.uVexLength == 0)
1957 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1958 IEM_GET_MODRM_RM(pVCpu, bRm));
1959 else
1960 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1961 IEM_GET_MODRM_RM(pVCpu, bRm));
1962 IEM_MC_ADVANCE_RIP_AND_FINISH();
1963 IEM_MC_END();
1964 }
1965 else
1966 {
1967 /*
1968 * Register, memory.
1969 */
1970 if (pVCpu->iem.s.uVexLength == 0)
1971 {
1972 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1973 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1974 IEM_MC_LOCAL(RTUINT128U, uSrc);
1975
1976 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1977 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1978 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1979 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1980
1981 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1982 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1983
1984 IEM_MC_ADVANCE_RIP_AND_FINISH();
1985 IEM_MC_END();
1986 }
1987 else
1988 {
1989 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1990 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1991 IEM_MC_LOCAL(RTUINT256U, uSrc);
1992
1993 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1994 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1995 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1996 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1997
1998 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1999 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
2000
2001 IEM_MC_ADVANCE_RIP_AND_FINISH();
2002 IEM_MC_END();
2003 }
2004 }
2005}
2006
2007
2008/**
2009 * @opcode 0x28
2010 * @oppfx 66
2011 * @opcpuid avx
2012 * @opgroup og_avx_pcksclr_datamove
2013 * @opxcpttype 1
2014 * @optest op1=1 op2=2 -> op1=2
2015 * @optest op1=0 op2=-42 -> op1=-42
2016 * @note Almost identical to vmovaps
2017 */
2018FNIEMOP_DEF(iemOp_vmovapd_Vpd_Wpd)
2019{
2020 IEMOP_MNEMONIC2(VEX_RM, VMOVAPD, vmovapd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2021 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2022 Assert(pVCpu->iem.s.uVexLength <= 1);
2023 if (IEM_IS_MODRM_REG_MODE(bRm))
2024 {
2025 /*
2026 * Register, register.
2027 */
2028 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2029 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2030
2031 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2032 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2033 if (pVCpu->iem.s.uVexLength == 0)
2034 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
2035 IEM_GET_MODRM_RM(pVCpu, bRm));
2036 else
2037 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
2038 IEM_GET_MODRM_RM(pVCpu, bRm));
2039 IEM_MC_ADVANCE_RIP_AND_FINISH();
2040 IEM_MC_END();
2041 }
2042 else
2043 {
2044 /*
2045 * Register, memory.
2046 */
2047 if (pVCpu->iem.s.uVexLength == 0)
2048 {
2049 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2050 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2051 IEM_MC_LOCAL(RTUINT128U, uSrc);
2052
2053 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2054 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2055 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2056 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2057
2058 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2059 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
2060
2061 IEM_MC_ADVANCE_RIP_AND_FINISH();
2062 IEM_MC_END();
2063 }
2064 else
2065 {
2066 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2067 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2068 IEM_MC_LOCAL(RTUINT256U, uSrc);
2069
2070 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2071 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2072 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2073 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2074
2075 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2076 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
2077
2078 IEM_MC_ADVANCE_RIP_AND_FINISH();
2079 IEM_MC_END();
2080 }
2081 }
2082}
2083
2084/**
2085 * @opmnemonic udvexf30f28
2086 * @opcode 0x28
2087 * @oppfx 0xf3
2088 * @opunused vex.modrm
2089 * @opcpuid avx
2090 * @optest ->
2091 * @opdone
2092 */
2093
2094/**
2095 * @opmnemonic udvexf20f28
2096 * @opcode 0x28
2097 * @oppfx 0xf2
2098 * @opunused vex.modrm
2099 * @opcpuid avx
2100 * @optest ->
2101 * @opdone
2102 */
2103
2104/**
2105 * @opcode 0x29
2106 * @oppfx none
2107 * @opcpuid avx
2108 * @opgroup og_avx_pcksclr_datamove
2109 * @opxcpttype 1
2110 * @optest op1=1 op2=2 -> op1=2
2111 * @optest op1=0 op2=-42 -> op1=-42
2112 * @note Almost identical to vmovapd.
2113 */
2114FNIEMOP_DEF(iemOp_vmovaps_Wps_Vps)
2115{
2116 IEMOP_MNEMONIC2(VEX_MR, VMOVAPS, vmovaps, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2117 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2118 Assert(pVCpu->iem.s.uVexLength <= 1);
2119 if (IEM_IS_MODRM_REG_MODE(bRm))
2120 {
2121 /*
2122 * Register, register.
2123 */
2124 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2125 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2126
2127 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2128 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2129 if (pVCpu->iem.s.uVexLength == 0)
2130 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2131 IEM_GET_MODRM_REG(pVCpu, bRm));
2132 else
2133 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2134 IEM_GET_MODRM_REG(pVCpu, bRm));
2135 IEM_MC_ADVANCE_RIP_AND_FINISH();
2136 IEM_MC_END();
2137 }
2138 else
2139 {
2140 /*
2141 * Register, memory.
2142 */
2143 if (pVCpu->iem.s.uVexLength == 0)
2144 {
2145 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2146 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2147 IEM_MC_LOCAL(RTUINT128U, uSrc);
2148
2149 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2150 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2151 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2152 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2153
2154 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
2155 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2156
2157 IEM_MC_ADVANCE_RIP_AND_FINISH();
2158 IEM_MC_END();
2159 }
2160 else
2161 {
2162 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2163 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2164 IEM_MC_LOCAL(RTUINT256U, uSrc);
2165
2166 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2167 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2168 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2169 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2170
2171 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2172 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2173
2174 IEM_MC_ADVANCE_RIP_AND_FINISH();
2175 IEM_MC_END();
2176 }
2177 }
2178}
2179
2180/**
2181 * @opcode 0x29
2182 * @oppfx 66
2183 * @opcpuid avx
2184 * @opgroup og_avx_pcksclr_datamove
2185 * @opxcpttype 1
2186 * @optest op1=1 op2=2 -> op1=2
2187 * @optest op1=0 op2=-42 -> op1=-42
2188 * @note Almost identical to vmovaps
2189 */
2190FNIEMOP_DEF(iemOp_vmovapd_Wpd_Vpd)
2191{
2192 IEMOP_MNEMONIC2(VEX_MR, VMOVAPD, vmovapd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2193 Assert(pVCpu->iem.s.uVexLength <= 1);
2194 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2195 if (IEM_IS_MODRM_REG_MODE(bRm))
2196 {
2197 /*
2198 * Register, register.
2199 */
2200 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2201 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2202
2203 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2204 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2205 if (pVCpu->iem.s.uVexLength == 0)
2206 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2207 IEM_GET_MODRM_REG(pVCpu, bRm));
2208 else
2209 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2210 IEM_GET_MODRM_REG(pVCpu, bRm));
2211 IEM_MC_ADVANCE_RIP_AND_FINISH();
2212 IEM_MC_END();
2213 }
2214 else
2215 {
2216 /*
2217 * Register, memory.
2218 */
2219 if (pVCpu->iem.s.uVexLength == 0)
2220 {
2221 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2222 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2223 IEM_MC_LOCAL(RTUINT128U, uSrc);
2224
2225 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2226 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2227 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2228 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2229
2230 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
2231 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2232
2233 IEM_MC_ADVANCE_RIP_AND_FINISH();
2234 IEM_MC_END();
2235 }
2236 else
2237 {
2238 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2239 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2240 IEM_MC_LOCAL(RTUINT256U, uSrc);
2241
2242 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2243 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2244 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2245 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2246
2247 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2248 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2249
2250 IEM_MC_ADVANCE_RIP_AND_FINISH();
2251 IEM_MC_END();
2252 }
2253 }
2254}
2255
2256
2257/**
2258 * @opmnemonic udvexf30f29
2259 * @opcode 0x29
2260 * @oppfx 0xf3
2261 * @opunused vex.modrm
2262 * @opcpuid avx
2263 * @optest ->
2264 * @opdone
2265 */
2266
2267/**
2268 * @opmnemonic udvexf20f29
2269 * @opcode 0x29
2270 * @oppfx 0xf2
2271 * @opunused vex.modrm
2272 * @opcpuid avx
2273 * @optest ->
2274 * @opdone
2275 */
2276
2277
2278/** Opcode VEX.0F 0x2a - invalid */
2279/** Opcode VEX.66.0F 0x2a - invalid */
2280/** Opcode VEX.F3.0F 0x2a - vcvtsi2ss Vss, Hss, Ey */
2281FNIEMOP_STUB(iemOp_vcvtsi2ss_Vss_Hss_Ey);
2282/** Opcode VEX.F2.0F 0x2a - vcvtsi2sd Vsd, Hsd, Ey */
2283FNIEMOP_STUB(iemOp_vcvtsi2sd_Vsd_Hsd_Ey);
2284
2285
2286/**
2287 * @opcode 0x2b
2288 * @opcodesub !11 mr/reg
2289 * @oppfx none
2290 * @opcpuid avx
2291 * @opgroup og_avx_cachect
2292 * @opxcpttype 1
2293 * @optest op1=1 op2=2 -> op1=2
2294 * @optest op1=0 op2=-42 -> op1=-42
2295 * @note Identical implementation to vmovntpd
2296 */
2297FNIEMOP_DEF(iemOp_vmovntps_Mps_Vps)
2298{
2299 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPS, vmovntps, Mps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2300 Assert(pVCpu->iem.s.uVexLength <= 1);
2301 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2302 if (IEM_IS_MODRM_MEM_MODE(bRm))
2303 {
2304 /*
2305 * memory, register.
2306 */
2307 if (pVCpu->iem.s.uVexLength == 0)
2308 {
2309 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2310 IEM_MC_LOCAL(RTUINT128U, uSrc);
2311 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2312
2313 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2314 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2315 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2316 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2317
2318 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2319 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2320
2321 IEM_MC_ADVANCE_RIP_AND_FINISH();
2322 IEM_MC_END();
2323 }
2324 else
2325 {
2326 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2327 IEM_MC_LOCAL(RTUINT256U, uSrc);
2328 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2329
2330 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2331 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2332 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2333 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2334
2335 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2336 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2337
2338 IEM_MC_ADVANCE_RIP_AND_FINISH();
2339 IEM_MC_END();
2340 }
2341 }
2342 /* The register, register encoding is invalid. */
2343 else
2344 IEMOP_RAISE_INVALID_OPCODE_RET();
2345}
2346
2347/**
2348 * @opcode 0x2b
2349 * @opcodesub !11 mr/reg
2350 * @oppfx 0x66
2351 * @opcpuid avx
2352 * @opgroup og_avx_cachect
2353 * @opxcpttype 1
2354 * @optest op1=1 op2=2 -> op1=2
2355 * @optest op1=0 op2=-42 -> op1=-42
2356 * @note Identical implementation to vmovntps
2357 */
2358FNIEMOP_DEF(iemOp_vmovntpd_Mpd_Vpd)
2359{
2360 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPD, vmovntpd, Mpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2361 Assert(pVCpu->iem.s.uVexLength <= 1);
2362 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2363 if (IEM_IS_MODRM_MEM_MODE(bRm))
2364 {
2365 /*
2366 * memory, register.
2367 */
2368 if (pVCpu->iem.s.uVexLength == 0)
2369 {
2370 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2371 IEM_MC_LOCAL(RTUINT128U, uSrc);
2372 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2373
2374 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2375 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2376 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2377 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2378
2379 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2380 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2381
2382 IEM_MC_ADVANCE_RIP_AND_FINISH();
2383 IEM_MC_END();
2384 }
2385 else
2386 {
2387 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2388 IEM_MC_LOCAL(RTUINT256U, uSrc);
2389 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2390
2391 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2392 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2393 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2394 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2395
2396 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2397 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2398
2399 IEM_MC_ADVANCE_RIP_AND_FINISH();
2400 IEM_MC_END();
2401 }
2402 }
2403 /* The register, register encoding is invalid. */
2404 else
2405 IEMOP_RAISE_INVALID_OPCODE_RET();
2406}
2407
2408/**
2409 * @opmnemonic udvexf30f2b
2410 * @opcode 0x2b
2411 * @oppfx 0xf3
2412 * @opunused vex.modrm
2413 * @opcpuid avx
2414 * @optest ->
2415 * @opdone
2416 */
2417
2418/**
2419 * @opmnemonic udvexf20f2b
2420 * @opcode 0x2b
2421 * @oppfx 0xf2
2422 * @opunused vex.modrm
2423 * @opcpuid avx
2424 * @optest ->
2425 * @opdone
2426 */
2427
2428
2429/* Opcode VEX.0F 0x2c - invalid */
2430/* Opcode VEX.66.0F 0x2c - invalid */
2431/** Opcode VEX.F3.0F 0x2c - vcvttss2si Gy, Wss */
2432FNIEMOP_STUB(iemOp_vcvttss2si_Gy_Wss);
2433/** Opcode VEX.F2.0F 0x2c - vcvttsd2si Gy, Wsd */
2434FNIEMOP_STUB(iemOp_vcvttsd2si_Gy_Wsd);
2435
2436/* Opcode VEX.0F 0x2d - invalid */
2437/* Opcode VEX.66.0F 0x2d - invalid */
2438/** Opcode VEX.F3.0F 0x2d - vcvtss2si Gy, Wss */
2439FNIEMOP_STUB(iemOp_vcvtss2si_Gy_Wss);
2440/** Opcode VEX.F2.0F 0x2d - vcvtsd2si Gy, Wsd */
2441FNIEMOP_STUB(iemOp_vcvtsd2si_Gy_Wsd);
2442
2443
2444/**
2445 * @opcode 0x2e
2446 * @oppfx none
2447 * @opflmodify cf,pf,af,zf,sf,of
2448 * @opflclear af,sf,of
2449 */
2450FNIEMOP_DEF(iemOp_vucomiss_Vss_Wss)
2451{
2452 IEMOP_MNEMONIC2(VEX_RM, VUCOMISS, vucomiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2453 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2454 if (IEM_IS_MODRM_REG_MODE(bRm))
2455 {
2456 /*
2457 * Register, register.
2458 */
2459 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2460 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2461 IEM_MC_LOCAL(uint32_t, fEFlags);
2462 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2463 IEM_MC_ARG(RTFLOAT32U, uSrc1, 1);
2464 IEM_MC_ARG(RTFLOAT32U, uSrc2, 2);
2465 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2466 IEM_MC_PREPARE_AVX_USAGE();
2467 IEM_MC_FETCH_EFLAGS(fEFlags);
2468 IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
2469 IEM_MC_FETCH_XREG_R32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iDWord*/);
2470 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
2471 pEFlags, uSrc1, uSrc2);
2472 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2473 IEM_MC_COMMIT_EFLAGS(fEFlags);
2474
2475 IEM_MC_ADVANCE_RIP_AND_FINISH();
2476 IEM_MC_END();
2477 }
2478 else
2479 {
2480 /*
2481 * Register, memory.
2482 */
2483 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2484 IEM_MC_LOCAL(uint32_t, fEFlags);
2485 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2486 IEM_MC_ARG(RTFLOAT32U, uSrc1, 1);
2487 IEM_MC_ARG(RTFLOAT32U, uSrc2, 2);
2488 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2489
2490 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2491 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2492 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2493 IEM_MC_FETCH_MEM_R32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2494
2495 IEM_MC_PREPARE_AVX_USAGE();
2496 IEM_MC_FETCH_EFLAGS(fEFlags);
2497 IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
2498 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
2499 pEFlags, uSrc1, uSrc2);
2500 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2501 IEM_MC_COMMIT_EFLAGS(fEFlags);
2502
2503 IEM_MC_ADVANCE_RIP_AND_FINISH();
2504 IEM_MC_END();
2505 }
2506}
2507
2508
2509/**
2510 * @opcode 0x2e
2511 * @oppfx 0x66
2512 * @opflmodify cf,pf,af,zf,sf,of
2513 * @opflclear af,sf,of
2514 */
2515FNIEMOP_DEF(iemOp_vucomisd_Vsd_Wsd)
2516{
2517 IEMOP_MNEMONIC2(VEX_RM, VUCOMISD, vucomisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2518 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2519 if (IEM_IS_MODRM_REG_MODE(bRm))
2520 {
2521 /*
2522 * Register, register.
2523 */
2524 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2525 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2526 IEM_MC_LOCAL(uint32_t, fEFlags);
2527 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2528 IEM_MC_ARG(RTFLOAT64U, uSrc1, 1);
2529 IEM_MC_ARG(RTFLOAT64U, uSrc2, 2);
2530 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2531 IEM_MC_PREPARE_AVX_USAGE();
2532 IEM_MC_FETCH_EFLAGS(fEFlags);
2533 IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
2534 IEM_MC_FETCH_XREG_R64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iQWord*/);
2535 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
2536 pEFlags, uSrc1, uSrc2);
2537 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2538 IEM_MC_COMMIT_EFLAGS(fEFlags);
2539
2540 IEM_MC_ADVANCE_RIP_AND_FINISH();
2541 IEM_MC_END();
2542 }
2543 else
2544 {
2545 /*
2546 * Register, memory.
2547 */
2548 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2549 IEM_MC_LOCAL(uint32_t, fEFlags);
2550 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2551 IEM_MC_ARG(RTFLOAT64U, uSrc1, 1);
2552 IEM_MC_ARG(RTFLOAT64U, uSrc2, 2);
2553 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2554
2555 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2556 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2557 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2558 IEM_MC_FETCH_MEM_R64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2559
2560 IEM_MC_PREPARE_AVX_USAGE();
2561 IEM_MC_FETCH_EFLAGS(fEFlags);
2562 IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
2563 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
2564 pEFlags, uSrc1, uSrc2);
2565 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2566 IEM_MC_COMMIT_EFLAGS(fEFlags);
2567
2568 IEM_MC_ADVANCE_RIP_AND_FINISH();
2569 IEM_MC_END();
2570 }
2571}
2572
2573
2574/* Opcode VEX.F3.0F 0x2e - invalid */
2575/* Opcode VEX.F2.0F 0x2e - invalid */
2576
2577/**
2578 * @opcode 0x2f
2579 * @oppfx none
2580 * @opflmodify cf,pf,af,zf,sf,of
2581 * @opflclear af,sf,of
2582 */
2583FNIEMOP_DEF(iemOp_vcomiss_Vss_Wss)
2584{
2585 IEMOP_MNEMONIC2(VEX_RM, VCOMISS, vcomiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2586 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2587 if (IEM_IS_MODRM_REG_MODE(bRm))
2588 {
2589 /*
2590 * Register, register.
2591 */
2592 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2593 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2594 IEM_MC_LOCAL(uint32_t, fEFlags);
2595 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2596 IEM_MC_ARG(RTFLOAT32U, uSrc1, 1);
2597 IEM_MC_ARG(RTFLOAT32U, uSrc2, 2);
2598 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2599 IEM_MC_PREPARE_AVX_USAGE();
2600 IEM_MC_FETCH_EFLAGS(fEFlags);
2601 IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
2602 IEM_MC_FETCH_XREG_R32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iDWord*/);
2603 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
2604 pEFlags, uSrc1, uSrc2);
2605 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2606 IEM_MC_COMMIT_EFLAGS(fEFlags);
2607
2608 IEM_MC_ADVANCE_RIP_AND_FINISH();
2609 IEM_MC_END();
2610 }
2611 else
2612 {
2613 /*
2614 * Register, memory.
2615 */
2616 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2617 IEM_MC_LOCAL(uint32_t, fEFlags);
2618 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2619 IEM_MC_ARG(RTFLOAT32U, uSrc1, 1);
2620 IEM_MC_ARG(RTFLOAT32U, uSrc2, 2);
2621 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2622
2623 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2624 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2625 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2626 IEM_MC_FETCH_MEM_R32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2627
2628 IEM_MC_PREPARE_AVX_USAGE();
2629 IEM_MC_FETCH_EFLAGS(fEFlags);
2630 IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
2631 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
2632 pEFlags, uSrc1, uSrc2);
2633 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2634 IEM_MC_COMMIT_EFLAGS(fEFlags);
2635
2636 IEM_MC_ADVANCE_RIP_AND_FINISH();
2637 IEM_MC_END();
2638 }
2639}
2640
2641
2642/**
2643 * @opcode 0x2f
2644 * @oppfx 0x66
2645 * @opflmodify cf,pf,af,zf,sf,of
2646 * @opflclear af,sf,of
2647 */
2648FNIEMOP_DEF(iemOp_vcomisd_Vsd_Wsd)
2649{
2650 IEMOP_MNEMONIC2(VEX_RM, VCOMISD, vcomisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2651 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2652 if (IEM_IS_MODRM_REG_MODE(bRm))
2653 {
2654 /*
2655 * Register, register.
2656 */
2657 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2658 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2659 IEM_MC_LOCAL(uint32_t, fEFlags);
2660 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2661 IEM_MC_ARG(RTFLOAT64U, uSrc1, 1);
2662 IEM_MC_ARG(RTFLOAT64U, uSrc2, 2);
2663 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2664 IEM_MC_PREPARE_AVX_USAGE();
2665 IEM_MC_FETCH_EFLAGS(fEFlags);
2666 IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
2667 IEM_MC_FETCH_XREG_R64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iQWord*/);
2668 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
2669 pEFlags, uSrc1, uSrc2);
2670 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2671 IEM_MC_COMMIT_EFLAGS(fEFlags);
2672
2673 IEM_MC_ADVANCE_RIP_AND_FINISH();
2674 IEM_MC_END();
2675 }
2676 else
2677 {
2678 /*
2679 * Register, memory.
2680 */
2681 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2682 IEM_MC_LOCAL(uint32_t, fEFlags);
2683 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2684 IEM_MC_ARG(RTFLOAT64U, uSrc1, 1);
2685 IEM_MC_ARG(RTFLOAT64U, uSrc2, 2);
2686 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2687
2688 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2689 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2690 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2691 IEM_MC_FETCH_MEM_R64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2692
2693 IEM_MC_PREPARE_AVX_USAGE();
2694 IEM_MC_FETCH_EFLAGS(fEFlags);
2695 IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
2696 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
2697 pEFlags, uSrc1, uSrc2);
2698 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2699 IEM_MC_COMMIT_EFLAGS(fEFlags);
2700
2701 IEM_MC_ADVANCE_RIP_AND_FINISH();
2702 IEM_MC_END();
2703 }
2704}
2705
2706
2707/* Opcode VEX.F3.0F 0x2f - invalid */
2708/* Opcode VEX.F2.0F 0x2f - invalid */
2709
2710/* Opcode VEX.0F 0x30 - invalid */
2711/* Opcode VEX.0F 0x31 - invalid */
2712/* Opcode VEX.0F 0x32 - invalid */
2713/* Opcode VEX.0F 0x33 - invalid */
2714/* Opcode VEX.0F 0x34 - invalid */
2715/* Opcode VEX.0F 0x35 - invalid */
2716/* Opcode VEX.0F 0x36 - invalid */
2717/* Opcode VEX.0F 0x37 - invalid */
2718/* Opcode VEX.0F 0x38 - invalid */
2719/* Opcode VEX.0F 0x39 - invalid */
2720/* Opcode VEX.0F 0x3a - invalid */
2721/* Opcode VEX.0F 0x3b - invalid */
2722/* Opcode VEX.0F 0x3c - invalid */
2723/* Opcode VEX.0F 0x3d - invalid */
2724/* Opcode VEX.0F 0x3e - invalid */
2725/* Opcode VEX.0F 0x3f - invalid */
2726/* Opcode VEX.0F 0x40 - invalid */
2727/* Opcode VEX.0F 0x41 - invalid */
2728/* Opcode VEX.0F 0x42 - invalid */
2729/* Opcode VEX.0F 0x43 - invalid */
2730/* Opcode VEX.0F 0x44 - invalid */
2731/* Opcode VEX.0F 0x45 - invalid */
2732/* Opcode VEX.0F 0x46 - invalid */
2733/* Opcode VEX.0F 0x47 - invalid */
2734/* Opcode VEX.0F 0x48 - invalid */
2735/* Opcode VEX.0F 0x49 - invalid */
2736/* Opcode VEX.0F 0x4a - invalid */
2737/* Opcode VEX.0F 0x4b - invalid */
2738/* Opcode VEX.0F 0x4c - invalid */
2739/* Opcode VEX.0F 0x4d - invalid */
2740/* Opcode VEX.0F 0x4e - invalid */
2741/* Opcode VEX.0F 0x4f - invalid */
2742
2743
2744/** Opcode VEX.0F 0x50 - vmovmskps Gy, Ups */
2745FNIEMOP_DEF(iemOp_vmovmskps_Gy_Ups)
2746{
2747 IEMOP_MNEMONIC2(VEX_RM_REG, VMOVMSKPS, vmovmskps, Gd, Ux, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2748 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2749 if (IEM_IS_MODRM_REG_MODE(bRm))
2750 {
2751 /*
2752 * Register, register.
2753 */
2754 if (pVCpu->iem.s.uVexLength == 0)
2755 {
2756 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2757 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2758 IEM_MC_LOCAL(uint8_t, u8Dst);
2759 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2760 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
2761 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2762 IEM_MC_PREPARE_AVX_USAGE();
2763 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2764 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmovmskps_u128, iemAImpl_vmovmskps_u128_fallback),
2765 pu8Dst, puSrc);
2766 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2767 IEM_MC_ADVANCE_RIP_AND_FINISH();
2768 IEM_MC_END();
2769 }
2770 else
2771 {
2772 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2773 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
2774 IEM_MC_LOCAL(uint8_t, u8Dst);
2775 IEM_MC_LOCAL(RTUINT256U, uSrc);
2776 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2777 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
2778
2779 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2780 IEM_MC_PREPARE_AVX_USAGE();
2781 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2782 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vmovmskps_u256, iemAImpl_vmovmskps_u256_fallback),
2783 pu8Dst, puSrc);
2784 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2785 IEM_MC_ADVANCE_RIP_AND_FINISH();
2786 IEM_MC_END();
2787 }
2788 }
2789 /* No memory operand. */
2790 else
2791 IEMOP_RAISE_INVALID_OPCODE_RET();
2792}
2793
2794
2795/** Opcode VEX.66.0F 0x50 - vmovmskpd Gy,Upd */
2796FNIEMOP_DEF(iemOp_vmovmskpd_Gy_Upd)
2797{
2798 IEMOP_MNEMONIC2(VEX_RM_REG, VMOVMSKPD, vmovmskpd, Gd, Ux, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2799 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2800 if (IEM_IS_MODRM_REG_MODE(bRm))
2801 {
2802 /*
2803 * Register, register.
2804 */
2805 if (pVCpu->iem.s.uVexLength == 0)
2806 {
2807 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2808 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2809 IEM_MC_LOCAL(uint8_t, u8Dst);
2810 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2811 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
2812 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2813 IEM_MC_PREPARE_AVX_USAGE();
2814 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2815 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmovmskpd_u128, iemAImpl_vmovmskpd_u128_fallback),
2816 pu8Dst, puSrc);
2817 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2818 IEM_MC_ADVANCE_RIP_AND_FINISH();
2819 IEM_MC_END();
2820 }
2821 else
2822 {
2823 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2824 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
2825 IEM_MC_LOCAL(uint8_t, u8Dst);
2826 IEM_MC_LOCAL(RTUINT256U, uSrc);
2827 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2828 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
2829
2830 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2831 IEM_MC_PREPARE_AVX_USAGE();
2832 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2833 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vmovmskpd_u256, iemAImpl_vmovmskpd_u256_fallback),
2834 pu8Dst, puSrc);
2835 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2836 IEM_MC_ADVANCE_RIP_AND_FINISH();
2837 IEM_MC_END();
2838 }
2839 }
2840 /* No memory operand. */
2841 else
2842 IEMOP_RAISE_INVALID_OPCODE_RET();
2843}
2844
2845
2846/* Opcode VEX.F3.0F 0x50 - invalid */
2847/* Opcode VEX.F2.0F 0x50 - invalid */
2848
2849/** Opcode VEX.0F 0x51 - vsqrtps Vps, Wps */
2850FNIEMOP_STUB(iemOp_vsqrtps_Vps_Wps);
2851/** Opcode VEX.66.0F 0x51 - vsqrtpd Vpd, Wpd */
2852FNIEMOP_STUB(iemOp_vsqrtpd_Vpd_Wpd);
2853/** Opcode VEX.F3.0F 0x51 - vsqrtss Vss, Hss, Wss */
2854FNIEMOP_STUB(iemOp_vsqrtss_Vss_Hss_Wss);
2855/** Opcode VEX.F2.0F 0x51 - vsqrtsd Vsd, Hsd, Wsd */
2856FNIEMOP_STUB(iemOp_vsqrtsd_Vsd_Hsd_Wsd);
2857
2858/** Opcode VEX.0F 0x52 - vrsqrtps Vps, Wps */
2859FNIEMOP_STUB(iemOp_vrsqrtps_Vps_Wps);
2860/* Opcode VEX.66.0F 0x52 - invalid */
2861/** Opcode VEX.F3.0F 0x52 - vrsqrtss Vss, Hss, Wss */
2862FNIEMOP_STUB(iemOp_vrsqrtss_Vss_Hss_Wss);
2863/* Opcode VEX.F2.0F 0x52 - invalid */
2864
2865/** Opcode VEX.0F 0x53 - vrcpps Vps, Wps */
2866FNIEMOP_STUB(iemOp_vrcpps_Vps_Wps);
2867/* Opcode VEX.66.0F 0x53 - invalid */
2868/** Opcode VEX.F3.0F 0x53 - vrcpss Vss, Hss, Wss */
2869FNIEMOP_STUB(iemOp_vrcpss_Vss_Hss_Wss);
2870/* Opcode VEX.F2.0F 0x53 - invalid */
2871
2872
2873/** Opcode VEX.0F 0x54 - vandps Vps, Hps, Wps */
2874FNIEMOP_DEF(iemOp_vandps_Vps_Hps_Wps)
2875{
2876 IEMOP_MNEMONIC3(VEX_RVM, VANDPS, vandps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2877 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2878 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2879}
2880
2881
2882/** Opcode VEX.66.0F 0x54 - vandpd Vpd, Hpd, Wpd */
2883FNIEMOP_DEF(iemOp_vandpd_Vpd_Hpd_Wpd)
2884{
2885 IEMOP_MNEMONIC3(VEX_RVM, VANDPD, vandpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2886 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2887 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2888}
2889
2890
2891/* Opcode VEX.F3.0F 0x54 - invalid */
2892/* Opcode VEX.F2.0F 0x54 - invalid */
2893
2894
2895/** Opcode VEX.0F 0x55 - vandnps Vps, Hps, Wps */
2896FNIEMOP_DEF(iemOp_vandnps_Vps_Hps_Wps)
2897{
2898 IEMOP_MNEMONIC3(VEX_RVM, VANDNPS, vandnps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2899 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2900 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2901}
2902
2903
2904/** Opcode VEX.66.0F 0x55 - vandnpd Vpd, Hpd, Wpd */
2905FNIEMOP_DEF(iemOp_vandnpd_Vpd_Hpd_Wpd)
2906{
2907 IEMOP_MNEMONIC3(VEX_RVM, VANDNPD, vandnpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2908 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2909 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2910}
2911
2912
2913/* Opcode VEX.F3.0F 0x55 - invalid */
2914/* Opcode VEX.F2.0F 0x55 - invalid */
2915
2916/** Opcode VEX.0F 0x56 - vorps Vps, Hps, Wps */
2917FNIEMOP_DEF(iemOp_vorps_Vps_Hps_Wps)
2918{
2919 IEMOP_MNEMONIC3(VEX_RVM, VORPS, vorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2920 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2921 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2922}
2923
2924
2925/** Opcode VEX.66.0F 0x56 - vorpd Vpd, Hpd, Wpd */
2926FNIEMOP_DEF(iemOp_vorpd_Vpd_Hpd_Wpd)
2927{
2928 IEMOP_MNEMONIC3(VEX_RVM, VORPD, vorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2929 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2930 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2931}
2932
2933
2934/* Opcode VEX.F3.0F 0x56 - invalid */
2935/* Opcode VEX.F2.0F 0x56 - invalid */
2936
2937
2938/** Opcode VEX.0F 0x57 - vxorps Vps, Hps, Wps */
2939FNIEMOP_DEF(iemOp_vxorps_Vps_Hps_Wps)
2940{
2941 IEMOP_MNEMONIC3(VEX_RVM, VXORPS, vxorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2942 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2943 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2944}
2945
2946
2947/** Opcode VEX.66.0F 0x57 - vxorpd Vpd, Hpd, Wpd */
2948FNIEMOP_DEF(iemOp_vxorpd_Vpd_Hpd_Wpd)
2949{
2950 IEMOP_MNEMONIC3(VEX_RVM, VXORPD, vxorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2951 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2952 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2953}
2954
2955
2956/* Opcode VEX.F3.0F 0x57 - invalid */
2957/* Opcode VEX.F2.0F 0x57 - invalid */
2958
2959
2960/** Opcode VEX.0F 0x58 - vaddps Vps, Hps, Wps */
2961FNIEMOP_DEF(iemOp_vaddps_Vps_Hps_Wps)
2962{
2963 IEMOP_MNEMONIC3(VEX_RVM, VADDPS, vaddps, Vps, Hps, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2964 IEMOPMEDIAF3_INIT_VARS( vaddps);
2965 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
2966}
2967
2968
2969/** Opcode VEX.66.0F 0x58 - vaddpd Vpd, Hpd, Wpd */
2970FNIEMOP_DEF(iemOp_vaddpd_Vpd_Hpd_Wpd)
2971{
2972 IEMOP_MNEMONIC3(VEX_RVM, VADDPD, vaddpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2973 IEMOPMEDIAF3_INIT_VARS( vaddpd);
2974 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
2975}
2976
2977
2978/** Opcode VEX.F3.0F 0x58 - vaddss Vss, Hss, Wss */
2979FNIEMOP_DEF(iemOp_vaddss_Vss_Hss_Wss)
2980{
2981 IEMOP_MNEMONIC3(VEX_RVM, VADDSS, vaddss, Vps, Hps, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2982 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R32,
2983 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback));
2984}
2985
2986
2987/** Opcode VEX.F2.0F 0x58 - vaddsd Vsd, Hsd, Wsd */
2988FNIEMOP_DEF(iemOp_vaddsd_Vsd_Hsd_Wsd)
2989{
2990 IEMOP_MNEMONIC3(VEX_RVM, VADDSD, vaddsd, Vpd, Hpd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2991 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R64,
2992 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback));
2993}
2994
2995
2996/** Opcode VEX.0F 0x59 - vmulps Vps, Hps, Wps */
2997FNIEMOP_DEF(iemOp_vmulps_Vps_Hps_Wps)
2998{
2999 IEMOP_MNEMONIC3(VEX_RVM, VMULPS, vmulps, Vps, Hps, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3000 IEMOPMEDIAF3_INIT_VARS( vmulps);
3001 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
3002}
3003
3004
3005/** Opcode VEX.66.0F 0x59 - vmulpd Vpd, Hpd, Wpd */
3006FNIEMOP_DEF(iemOp_vmulpd_Vpd_Hpd_Wpd)
3007{
3008 IEMOP_MNEMONIC3(VEX_RVM, VMULPD, vmulpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3009 IEMOPMEDIAF3_INIT_VARS( vmulpd);
3010 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
3011}
3012
3013
3014/** Opcode VEX.F3.0F 0x59 - vmulss Vss, Hss, Wss */
3015FNIEMOP_DEF(iemOp_vmulss_Vss_Hss_Wss)
3016{
3017 IEMOP_MNEMONIC3(VEX_RVM, VMULSS, vmulss, Vps, Hps, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3018 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R32,
3019 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback));
3020}
3021
3022
3023/** Opcode VEX.F2.0F 0x59 - vmulsd Vsd, Hsd, Wsd */
3024FNIEMOP_STUB(iemOp_vmulsd_Vsd_Hsd_Wsd);
3025
3026/** Opcode VEX.0F 0x5a - vcvtps2pd Vpd, Wps */
3027FNIEMOP_STUB(iemOp_vcvtps2pd_Vpd_Wps);
3028/** Opcode VEX.66.0F 0x5a - vcvtpd2ps Vps, Wpd */
3029FNIEMOP_STUB(iemOp_vcvtpd2ps_Vps_Wpd);
3030/** Opcode VEX.F3.0F 0x5a - vcvtss2sd Vsd, Hx, Wss */
3031FNIEMOP_STUB(iemOp_vcvtss2sd_Vsd_Hx_Wss);
3032/** Opcode VEX.F2.0F 0x5a - vcvtsd2ss Vss, Hx, Wsd */
3033FNIEMOP_STUB(iemOp_vcvtsd2ss_Vss_Hx_Wsd);
3034
3035/** Opcode VEX.0F 0x5b - vcvtdq2ps Vps, Wdq */
3036FNIEMOP_STUB(iemOp_vcvtdq2ps_Vps_Wdq);
3037/** Opcode VEX.66.0F 0x5b - vcvtps2dq Vdq, Wps */
3038FNIEMOP_STUB(iemOp_vcvtps2dq_Vdq_Wps);
3039/** Opcode VEX.F3.0F 0x5b - vcvttps2dq Vdq, Wps */
3040FNIEMOP_STUB(iemOp_vcvttps2dq_Vdq_Wps);
3041/* Opcode VEX.F2.0F 0x5b - invalid */
3042
3043
3044/** Opcode VEX.0F 0x5c - vsubps Vps, Hps, Wps */
3045FNIEMOP_DEF(iemOp_vsubps_Vps_Hps_Wps)
3046{
3047 IEMOP_MNEMONIC3(VEX_RVM, VSUBPS, vsubps, Vps, Hps, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3048 IEMOPMEDIAF3_INIT_VARS( vsubps);
3049 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
3050}
3051
3052
3053/** Opcode VEX.66.0F 0x5c - vsubpd Vpd, Hpd, Wpd */
3054FNIEMOP_DEF(iemOp_vsubpd_Vpd_Hpd_Wpd)
3055{
3056 IEMOP_MNEMONIC3(VEX_RVM, VSUBPD, vsubpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3057 IEMOPMEDIAF3_INIT_VARS( vsubpd);
3058 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
3059}
3060
3061
3062/** Opcode VEX.F3.0F 0x5c - vsubss Vss, Hss, Wss */
3063FNIEMOP_DEF(iemOp_vsubss_Vss_Hss_Wss)
3064{
3065 IEMOP_MNEMONIC3(VEX_RVM, VSUBSS, vsubss, Vps, Hps, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3066 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R32,
3067 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback));
3068}
3069
3070
3071/** Opcode VEX.F2.0F 0x5c - vsubsd Vsd, Hsd, Wsd */
3072FNIEMOP_STUB(iemOp_vsubsd_Vsd_Hsd_Wsd);
3073
3074/** Opcode VEX.0F 0x5d - vminps Vps, Hps, Wps */
3075FNIEMOP_STUB(iemOp_vminps_Vps_Hps_Wps);
3076/** Opcode VEX.66.0F 0x5d - vminpd Vpd, Hpd, Wpd */
3077FNIEMOP_STUB(iemOp_vminpd_Vpd_Hpd_Wpd);
3078/** Opcode VEX.F3.0F 0x5d - vminss Vss, Hss, Wss */
3079FNIEMOP_STUB(iemOp_vminss_Vss_Hss_Wss);
3080/** Opcode VEX.F2.0F 0x5d - vminsd Vsd, Hsd, Wsd */
3081FNIEMOP_STUB(iemOp_vminsd_Vsd_Hsd_Wsd);
3082
3083/** Opcode VEX.0F 0x5e - vdivps Vps, Hps, Wps */
3084FNIEMOP_STUB(iemOp_vdivps_Vps_Hps_Wps);
3085/** Opcode VEX.66.0F 0x5e - vdivpd Vpd, Hpd, Wpd */
3086FNIEMOP_STUB(iemOp_vdivpd_Vpd_Hpd_Wpd);
3087/** Opcode VEX.F3.0F 0x5e - vdivss Vss, Hss, Wss */
3088FNIEMOP_STUB(iemOp_vdivss_Vss_Hss_Wss);
3089/** Opcode VEX.F2.0F 0x5e - vdivsd Vsd, Hsd, Wsd */
3090FNIEMOP_STUB(iemOp_vdivsd_Vsd_Hsd_Wsd);
3091
3092/** Opcode VEX.0F 0x5f - vmaxps Vps, Hps, Wps */
3093FNIEMOP_STUB(iemOp_vmaxps_Vps_Hps_Wps);
3094/** Opcode VEX.66.0F 0x5f - vmaxpd Vpd, Hpd, Wpd */
3095FNIEMOP_STUB(iemOp_vmaxpd_Vpd_Hpd_Wpd);
3096/** Opcode VEX.F3.0F 0x5f - vmaxss Vss, Hss, Wss */
3097FNIEMOP_STUB(iemOp_vmaxss_Vss_Hss_Wss);
3098/** Opcode VEX.F2.0F 0x5f - vmaxsd Vsd, Hsd, Wsd */
3099FNIEMOP_STUB(iemOp_vmaxsd_Vsd_Hsd_Wsd);
3100
3101
3102/* Opcode VEX.0F 0x60 - invalid */
3103
3104
3105/** Opcode VEX.66.0F 0x60 - vpunpcklbw Vx, Hx, Wx */
3106FNIEMOP_DEF(iemOp_vpunpcklbw_Vx_Hx_Wx)
3107{
3108 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLBW, vpunpcklbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3109 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklbw);
3110 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3111}
3112
3113
3114/* Opcode VEX.F3.0F 0x60 - invalid */
3115
3116
3117/* Opcode VEX.0F 0x61 - invalid */
3118
3119
3120/** Opcode VEX.66.0F 0x61 - vpunpcklwd Vx, Hx, Wx */
3121FNIEMOP_DEF(iemOp_vpunpcklwd_Vx_Hx_Wx)
3122{
3123 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLWD, vpunpcklwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3124 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklwd);
3125 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3126}
3127
3128
3129/* Opcode VEX.F3.0F 0x61 - invalid */
3130
3131
3132/* Opcode VEX.0F 0x62 - invalid */
3133
3134/** Opcode VEX.66.0F 0x62 - vpunpckldq Vx, Hx, Wx */
3135FNIEMOP_DEF(iemOp_vpunpckldq_Vx_Hx_Wx)
3136{
3137 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLDQ, vpunpckldq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3138 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckldq);
3139 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3140}
3141
3142
3143/* Opcode VEX.F3.0F 0x62 - invalid */
3144
3145
3146
3147/* Opcode VEX.0F 0x63 - invalid */
3148
3149
3150/** Opcode VEX.66.0F 0x63 - vpacksswb Vx, Hx, Wx */
3151FNIEMOP_DEF(iemOp_vpacksswb_Vx_Hx_Wx)
3152{
3153 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSWB, vpacksswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3154 IEMOPMEDIAOPTF3_INIT_VARS( vpacksswb);
3155 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3156}
3157
3158
3159/* Opcode VEX.F3.0F 0x63 - invalid */
3160
3161/* Opcode VEX.0F 0x64 - invalid */
3162
3163
3164/** Opcode VEX.66.0F 0x64 - vpcmpgtb Vx, Hx, Wx */
3165FNIEMOP_DEF(iemOp_vpcmpgtb_Vx_Hx_Wx)
3166{
3167 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTB, vpcmpgtb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3168 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpgtb);
3169 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3170}
3171
3172
3173/* Opcode VEX.F3.0F 0x64 - invalid */
3174
3175/* Opcode VEX.0F 0x65 - invalid */
3176
3177
3178/** Opcode VEX.66.0F 0x65 - vpcmpgtw Vx, Hx, Wx */
3179FNIEMOP_DEF(iemOp_vpcmpgtw_Vx_Hx_Wx)
3180{
3181 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTW, vpcmpgtw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3182 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpgtw);
3183 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3184}
3185
3186
3187/* Opcode VEX.F3.0F 0x65 - invalid */
3188
3189/* Opcode VEX.0F 0x66 - invalid */
3190
3191
3192/** Opcode VEX.66.0F 0x66 - vpcmpgtd Vx, Hx, Wx */
3193FNIEMOP_DEF(iemOp_vpcmpgtd_Vx_Hx_Wx)
3194{
3195 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTD, vpcmpgtd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3196 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpgtd);
3197 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3198}
3199
3200
3201/* Opcode VEX.F3.0F 0x66 - invalid */
3202
3203/* Opcode VEX.0F 0x67 - invalid */
3204
3205
3206/** Opcode VEX.66.0F 0x67 - vpackuswb Vx, Hx, W */
3207FNIEMOP_DEF(iemOp_vpackuswb_Vx_Hx_W)
3208{
3209 IEMOP_MNEMONIC3(VEX_RVM, VPACKUSWB, vpackuswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3210 IEMOPMEDIAOPTF3_INIT_VARS( vpackuswb);
3211 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3212}
3213
3214
3215/* Opcode VEX.F3.0F 0x67 - invalid */
3216
3217
3218///**
3219// * Common worker for SSE2 instructions on the form:
3220// * pxxxx xmm1, xmm2/mem128
3221// *
3222// * The 2nd operand is the second half of a register, which in the memory case
3223// * means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
3224// * where it may read the full 128 bits or only the upper 64 bits.
3225// *
3226// * Exceptions type 4.
3227// */
3228//FNIEMOP_DEF_1(iemOpCommonSse_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
3229//{
3230// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3231// if (IEM_IS_MODRM_REG_MODE(bRm))
3232// {
3233// /*
3234// * Register, register.
3235// */
3236// IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3237// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
3238// IEM_MC_ARG(PRTUINT128U, pDst, 0);
3239// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
3240// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
3241// IEM_MC_PREPARE_SSE_USAGE();
3242// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3243// IEM_MC_REF_XREG_U128_CONST(pSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3244// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3245// IEM_MC_ADVANCE_RIP_AND_FINISH();
3246// IEM_MC_END();
3247// }
3248// else
3249// {
3250// /*
3251// * Register, memory.
3252// */
3253// IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3254// IEM_MC_ARG(PRTUINT128U, pDst, 0);
3255// IEM_MC_LOCAL(RTUINT128U, uSrc);
3256// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
3257// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3258//
3259// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3260// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
3261// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
3262// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */
3263//
3264// IEM_MC_PREPARE_SSE_USAGE();
3265// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3266// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3267//
3268// IEM_MC_ADVANCE_RIP_AND_FINISH();
3269// IEM_MC_END();
3270// }
3271// return VINF_SUCCESS;
3272//}
3273
3274
3275/* Opcode VEX.0F 0x68 - invalid */
3276
3277/** Opcode VEX.66.0F 0x68 - vpunpckhbw Vx, Hx, Wx */
3278FNIEMOP_DEF(iemOp_vpunpckhbw_Vx_Hx_Wx)
3279{
3280 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHBW, vpunpckhbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3281 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhbw);
3282 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3283}
3284
3285
3286/* Opcode VEX.F3.0F 0x68 - invalid */
3287
3288
3289/* Opcode VEX.0F 0x69 - invalid */
3290
3291
3292/** Opcode VEX.66.0F 0x69 - vpunpckhwd Vx, Hx, Wx */
3293FNIEMOP_DEF(iemOp_vpunpckhwd_Vx_Hx_Wx)
3294{
3295 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHWD, vpunpckhwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3296 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhwd);
3297 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3298}
3299
3300
3301/* Opcode VEX.F3.0F 0x69 - invalid */
3302
3303
3304/* Opcode VEX.0F 0x6a - invalid */
3305
3306
3307/** Opcode VEX.66.0F 0x6a - vpunpckhdq Vx, Hx, W */
3308FNIEMOP_DEF(iemOp_vpunpckhdq_Vx_Hx_W)
3309{
3310 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHDQ, vpunpckhdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3311 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhdq);
3312 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3313}
3314
3315
3316/* Opcode VEX.F3.0F 0x6a - invalid */
3317
3318
3319/* Opcode VEX.0F 0x6b - invalid */
3320
3321
3322/** Opcode VEX.66.0F 0x6b - vpackssdw Vx, Hx, Wx */
3323FNIEMOP_DEF(iemOp_vpackssdw_Vx_Hx_Wx)
3324{
3325 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSDW, vpackssdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3326 IEMOPMEDIAOPTF3_INIT_VARS( vpackssdw);
3327 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3328}
3329
3330
3331/* Opcode VEX.F3.0F 0x6b - invalid */
3332
3333
3334/* Opcode VEX.0F 0x6c - invalid */
3335
3336
3337/** Opcode VEX.66.0F 0x6c - vpunpcklqdq Vx, Hx, Wx */
3338FNIEMOP_DEF(iemOp_vpunpcklqdq_Vx_Hx_Wx)
3339{
3340 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLQDQ, vpunpcklqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3341 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklqdq);
3342 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3343}
3344
3345
3346/* Opcode VEX.F3.0F 0x6c - invalid */
3347/* Opcode VEX.F2.0F 0x6c - invalid */
3348
3349
3350/* Opcode VEX.0F 0x6d - invalid */
3351
3352
3353/** Opcode VEX.66.0F 0x6d - vpunpckhqdq Vx, Hx, W */
3354FNIEMOP_DEF(iemOp_vpunpckhqdq_Vx_Hx_W)
3355{
3356 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHQDQ, vpunpckhqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3357 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhqdq);
3358 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3359}
3360
3361
3362/* Opcode VEX.F3.0F 0x6d - invalid */
3363
3364
3365/* Opcode VEX.0F 0x6e - invalid */
3366
3367FNIEMOP_DEF(iemOp_vmovd_q_Vy_Ey)
3368{
3369 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3370 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3371 {
3372 /**
3373 * @opcode 0x6e
3374 * @opcodesub rex.w=1
3375 * @oppfx 0x66
3376 * @opcpuid avx
3377 * @opgroup og_avx_simdint_datamov
3378 * @opxcpttype 5
3379 * @optest 64-bit / op1=1 op2=2 -> op1=2
3380 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
3381 */
3382 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Eq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3383 if (IEM_IS_MODRM_REG_MODE(bRm))
3384 {
3385 /* XMM, greg64 */
3386 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3387 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3388 IEM_MC_LOCAL(uint64_t, u64Tmp);
3389
3390 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3391 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3392
3393 IEM_MC_FETCH_GREG_U64(u64Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
3394 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
3395
3396 IEM_MC_ADVANCE_RIP_AND_FINISH();
3397 IEM_MC_END();
3398 }
3399 else
3400 {
3401 /* XMM, [mem64] */
3402 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3403 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3404 IEM_MC_LOCAL(uint64_t, u64Tmp);
3405
3406 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3407 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3408 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3409 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3410
3411 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3412 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
3413
3414 IEM_MC_ADVANCE_RIP_AND_FINISH();
3415 IEM_MC_END();
3416 }
3417 }
3418 else
3419 {
3420 /**
3421 * @opdone
3422 * @opcode 0x6e
3423 * @opcodesub rex.w=0
3424 * @oppfx 0x66
3425 * @opcpuid avx
3426 * @opgroup og_avx_simdint_datamov
3427 * @opxcpttype 5
3428 * @opfunction iemOp_vmovd_q_Vy_Ey
3429 * @optest op1=1 op2=2 -> op1=2
3430 * @optest op1=0 op2=-42 -> op1=-42
3431 */
3432 IEMOP_MNEMONIC2(VEX_RM, VMOVD, vmovd, Vd_WO, Ed, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3433 if (IEM_IS_MODRM_REG_MODE(bRm))
3434 {
3435 /* XMM, greg32 */
3436 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3437 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3438 IEM_MC_LOCAL(uint32_t, u32Tmp);
3439
3440 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3441 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3442
3443 IEM_MC_FETCH_GREG_U32(u32Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
3444 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
3445
3446 IEM_MC_ADVANCE_RIP_AND_FINISH();
3447 IEM_MC_END();
3448 }
3449 else
3450 {
3451 /* XMM, [mem32] */
3452 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3453 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3454 IEM_MC_LOCAL(uint32_t, u32Tmp);
3455
3456 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3457 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3458 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3459 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3460
3461 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3462 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
3463
3464 IEM_MC_ADVANCE_RIP_AND_FINISH();
3465 IEM_MC_END();
3466 }
3467 }
3468}
3469
3470
3471/* Opcode VEX.F3.0F 0x6e - invalid */
3472
3473
3474/* Opcode VEX.0F 0x6f - invalid */
3475
3476/**
3477 * @opcode 0x6f
3478 * @oppfx 0x66
3479 * @opcpuid avx
3480 * @opgroup og_avx_simdint_datamove
3481 * @opxcpttype 1
3482 * @optest op1=1 op2=2 -> op1=2
3483 * @optest op1=0 op2=-42 -> op1=-42
3484 */
3485FNIEMOP_DEF(iemOp_vmovdqa_Vx_Wx)
3486{
3487 IEMOP_MNEMONIC2(VEX_RM, VMOVDQA, vmovdqa, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3488 Assert(pVCpu->iem.s.uVexLength <= 1);
3489 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3490 if (IEM_IS_MODRM_REG_MODE(bRm))
3491 {
3492 /*
3493 * Register, register.
3494 */
3495 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3496 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3497
3498 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3499 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3500 if (pVCpu->iem.s.uVexLength == 0)
3501 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3502 IEM_GET_MODRM_RM(pVCpu, bRm));
3503 else
3504 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3505 IEM_GET_MODRM_RM(pVCpu, bRm));
3506 IEM_MC_ADVANCE_RIP_AND_FINISH();
3507 IEM_MC_END();
3508 }
3509 else if (pVCpu->iem.s.uVexLength == 0)
3510 {
3511 /*
3512 * Register, memory128.
3513 */
3514 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3515 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3516 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3517
3518 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3519 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3520 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3521 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3522
3523 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3524 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
3525
3526 IEM_MC_ADVANCE_RIP_AND_FINISH();
3527 IEM_MC_END();
3528 }
3529 else
3530 {
3531 /*
3532 * Register, memory256.
3533 */
3534 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3535 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3536 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3537
3538 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3539 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3540 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3541 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3542
3543 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3544 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
3545
3546 IEM_MC_ADVANCE_RIP_AND_FINISH();
3547 IEM_MC_END();
3548 }
3549}
3550
3551/**
3552 * @opcode 0x6f
3553 * @oppfx 0xf3
3554 * @opcpuid avx
3555 * @opgroup og_avx_simdint_datamove
3556 * @opxcpttype 4UA
3557 * @optest op1=1 op2=2 -> op1=2
3558 * @optest op1=0 op2=-42 -> op1=-42
3559 */
3560FNIEMOP_DEF(iemOp_vmovdqu_Vx_Wx)
3561{
3562 IEMOP_MNEMONIC2(VEX_RM, VMOVDQU, vmovdqu, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3563 Assert(pVCpu->iem.s.uVexLength <= 1);
3564 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3565 if (IEM_IS_MODRM_REG_MODE(bRm))
3566 {
3567 /*
3568 * Register, register.
3569 */
3570 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3571 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3572
3573 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3574 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3575 if (pVCpu->iem.s.uVexLength == 0)
3576 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3577 IEM_GET_MODRM_RM(pVCpu, bRm));
3578 else
3579 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3580 IEM_GET_MODRM_RM(pVCpu, bRm));
3581 IEM_MC_ADVANCE_RIP_AND_FINISH();
3582 IEM_MC_END();
3583 }
3584 else if (pVCpu->iem.s.uVexLength == 0)
3585 {
3586 /*
3587 * Register, memory128.
3588 */
3589 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3590 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3591 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3592
3593 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3594 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3595 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3596 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3597
3598 IEM_MC_FETCH_MEM_U128_NO_AC(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3599 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
3600
3601 IEM_MC_ADVANCE_RIP_AND_FINISH();
3602 IEM_MC_END();
3603 }
3604 else
3605 {
3606 /*
3607 * Register, memory256.
3608 */
3609 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3610 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3611 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3612
3613 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3614 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3615 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3616 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3617
3618 IEM_MC_FETCH_MEM_U256_NO_AC(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3619 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
3620
3621 IEM_MC_ADVANCE_RIP_AND_FINISH();
3622 IEM_MC_END();
3623 }
3624}
3625
3626
3627/* Opcode VEX.0F 0x70 - invalid */
3628
3629
3630/**
3631 * Common worker for AVX/AVX2 instructions on the forms:
3632 * - vpxxx xmm0, xmm2/mem128, imm8
3633 * - vpxxx ymm0, ymm2/mem256, imm8
3634 *
3635 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
3636 */
3637FNIEMOP_DEF_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, PFNIEMAIMPLMEDIAPSHUFU128, pfnU128, PFNIEMAIMPLMEDIAPSHUFU256, pfnU256)
3638{
3639 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3640 if (IEM_IS_MODRM_REG_MODE(bRm))
3641 {
3642 /*
3643 * Register, register.
3644 */
3645 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3646 if (pVCpu->iem.s.uVexLength)
3647 {
3648 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3649 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3650 IEM_MC_LOCAL(RTUINT256U, uDst);
3651 IEM_MC_LOCAL(RTUINT256U, uSrc);
3652 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3653 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3654 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3655 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3656 IEM_MC_PREPARE_AVX_USAGE();
3657 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3658 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg);
3659 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3660 IEM_MC_ADVANCE_RIP_AND_FINISH();
3661 IEM_MC_END();
3662 }
3663 else
3664 {
3665 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3666 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3667 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3668 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
3669 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3670 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3671 IEM_MC_PREPARE_AVX_USAGE();
3672 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3673 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3674 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
3675 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3676 IEM_MC_ADVANCE_RIP_AND_FINISH();
3677 IEM_MC_END();
3678 }
3679 }
3680 else
3681 {
3682 /*
3683 * Register, memory.
3684 */
3685 if (pVCpu->iem.s.uVexLength)
3686 {
3687 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3688 IEM_MC_LOCAL(RTUINT256U, uDst);
3689 IEM_MC_LOCAL(RTUINT256U, uSrc);
3690 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3691 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3692 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3693
3694 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
3695 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3696 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3697 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3698 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3699 IEM_MC_PREPARE_AVX_USAGE();
3700
3701 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3702 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg);
3703 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3704
3705 IEM_MC_ADVANCE_RIP_AND_FINISH();
3706 IEM_MC_END();
3707 }
3708 else
3709 {
3710 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3711 IEM_MC_LOCAL(RTUINT128U, uSrc);
3712 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3713 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3714 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
3715
3716 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
3717 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3718 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3719 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3720 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3721 IEM_MC_PREPARE_AVX_USAGE();
3722
3723 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3724 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3725 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
3726 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3727
3728 IEM_MC_ADVANCE_RIP_AND_FINISH();
3729 IEM_MC_END();
3730 }
3731 }
3732}
3733
3734
3735/** Opcode VEX.66.0F 0x70 - vpshufd Vx, Wx, Ib */
3736FNIEMOP_DEF(iemOp_vpshufd_Vx_Wx_Ib)
3737{
3738 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFD, vpshufd, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3739 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufd_u128,
3740 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufd_u256, iemAImpl_vpshufd_u256_fallback));
3741
3742}
3743
3744
3745/** Opcode VEX.F3.0F 0x70 - vpshufhw Vx, Wx, Ib */
3746FNIEMOP_DEF(iemOp_vpshufhw_Vx_Wx_Ib)
3747{
3748 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFHW, vpshufhw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3749 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufhw_u128,
3750 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufhw_u256, iemAImpl_vpshufhw_u256_fallback));
3751
3752}
3753
3754
3755/** Opcode VEX.F2.0F 0x70 - vpshuflw Vx, Wx, Ib */
3756FNIEMOP_DEF(iemOp_vpshuflw_Vx_Wx_Ib)
3757{
3758 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFLW, vpshuflw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3759 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshuflw_u128,
3760 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshuflw_u256, iemAImpl_vpshuflw_u256_fallback));
3761}
3762
3763
3764/**
3765 * Common worker(s) for AVX/AVX2 instructions on the forms:
3766 * - vpxxx xmm0, xmm2, imm8
3767 * - vpxxx ymm0, ymm2, imm8
3768 *
3769 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
3770 */
3771FNIEMOP_DEF_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, uint8_t, bRm, PFNIEMAIMPLMEDIAPSHUFU128, pfnU128)
3772{
3773 if (IEM_IS_MODRM_REG_MODE(bRm))
3774 {
3775 /*
3776 * Register, register.
3777 */
3778 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3779 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3780 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
3781 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3782 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
3783 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3784 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3785 IEM_MC_PREPARE_AVX_USAGE();
3786 IEM_MC_REF_XREG_U128(puDst, IEM_GET_EFFECTIVE_VVVV(pVCpu));
3787 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3788 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
3789 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_EFFECTIVE_VVVV(pVCpu));
3790 IEM_MC_ADVANCE_RIP_AND_FINISH();
3791 IEM_MC_END();
3792 }
3793 /* No memory operand. */
3794 else
3795 IEMOP_RAISE_INVALID_OPCODE_RET();
3796}
3797
3798FNIEMOP_DEF_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, uint8_t, bRm, PFNIEMAIMPLMEDIAPSHUFU256, pfnU256)
3799{
3800 if (IEM_IS_MODRM_REG_MODE(bRm))
3801 {
3802 /*
3803 * Register, register.
3804 */
3805 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3806 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3807 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
3808 IEM_MC_LOCAL(RTUINT256U, uDst);
3809 IEM_MC_LOCAL(RTUINT256U, uSrc);
3810 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3811 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3812 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3813 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3814 IEM_MC_PREPARE_AVX_USAGE();
3815 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3816 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg);
3817 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_EFFECTIVE_VVVV(pVCpu), uDst);
3818 IEM_MC_ADVANCE_RIP_AND_FINISH();
3819 IEM_MC_END();
3820 }
3821 /* No memory operand. */
3822 else
3823 IEMOP_RAISE_INVALID_OPCODE_RET();
3824}
3825
3826
3827/* Opcode VEX.0F 0x71 11/2 - invalid. */
3828/** Opcode VEX.66.0F 0x71 11/2. */
3829FNIEMOP_DEF_1(iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, uint8_t, bRm)
3830{
3831 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLW, vpsrlw, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3832 if (pVCpu->iem.s.uVexLength)
3833 {
3834 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3835 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback));
3836 }
3837 else
3838 {
3839 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3840 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback));
3841 }
3842}
3843
3844
3845/* Opcode VEX.0F 0x71 11/4 - invalid */
3846/** Opcode VEX.66.0F 0x71 11/4. */
3847FNIEMOP_DEF_1(iemOp_VGrp12_vpsraw_Hx_Ux_Ib, uint8_t, bRm)
3848{
3849 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRAW, vpsraw, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3850 if (pVCpu->iem.s.uVexLength)
3851 {
3852 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3853 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback));
3854 }
3855 else
3856 {
3857 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3858 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback));
3859 }
3860}
3861
3862/* Opcode VEX.0F 0x71 11/6 - invalid */
3863
3864/** Opcode VEX.66.0F 0x71 11/6. */
3865FNIEMOP_DEF_1(iemOp_VGrp12_vpsllw_Hx_Ux_Ib, uint8_t, bRm)
3866{
3867 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSLLW, vpsllw, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3868 if (pVCpu->iem.s.uVexLength)
3869 {
3870 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3871 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback));
3872 }
3873 else
3874 {
3875 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3876 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback));
3877 }
3878}
3879
3880
3881/**
3882 * VEX Group 12 jump table for register variant.
3883 */
3884IEM_STATIC const PFNIEMOPRM g_apfnVexGroup12RegReg[] =
3885{
3886 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3887 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3888 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3889 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3890 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsraw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3891 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3892 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsllw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3893 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3894};
3895AssertCompile(RT_ELEMENTS(g_apfnVexGroup12RegReg) == 8*4);
3896
3897
3898/** Opcode VEX.0F 0x71. */
3899FNIEMOP_DEF(iemOp_VGrp12)
3900{
3901 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3902 if (IEM_IS_MODRM_REG_MODE(bRm))
3903 /* register, register */
3904 return FNIEMOP_CALL_1(g_apfnVexGroup12RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3905 + pVCpu->iem.s.idxPrefix], bRm);
3906 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3907}
3908
3909
3910/* Opcode VEX.0F 0x72 11/2 - invalid. */
3911/** Opcode VEX.66.0F 0x72 11/2. */
3912FNIEMOP_DEF_1(iemOp_VGrp13_vpsrld_Hx_Ux_Ib, uint8_t, bRm)
3913{
3914 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLD, vpsrld, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3915 if (pVCpu->iem.s.uVexLength)
3916 {
3917 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3918 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback));
3919 }
3920 else
3921 {
3922 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3923 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback));
3924 }
3925}
3926
3927
3928/* Opcode VEX.0F 0x72 11/4 - invalid. */
3929/** Opcode VEX.66.0F 0x72 11/4. */
3930FNIEMOP_DEF_1(iemOp_VGrp13_vpsrad_Hx_Ux_Ib, uint8_t, bRm)
3931{
3932 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRAD, vpsrad, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3933 if (pVCpu->iem.s.uVexLength)
3934 {
3935 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3936 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback));
3937 }
3938 else
3939 {
3940 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3941 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback));
3942 }
3943}
3944
3945/* Opcode VEX.0F 0x72 11/6 - invalid. */
3946
3947/** Opcode VEX.66.0F 0x72 11/6. */
3948FNIEMOP_DEF_1(iemOp_VGrp13_vpslld_Hx_Ux_Ib, uint8_t, bRm)
3949{
3950 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSLLD, vpslld, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3951 if (pVCpu->iem.s.uVexLength)
3952 {
3953 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3954 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback));
3955 }
3956 else
3957 {
3958 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3959 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback));
3960 }
3961}
3962
3963
3964/**
3965 * Group 13 jump table for register variant.
3966 */
3967IEM_STATIC const PFNIEMOPRM g_apfnVexGroup13RegReg[] =
3968{
3969 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3970 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3971 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3972 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3973 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrad_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3974 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3975 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpslld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3976 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3977};
3978AssertCompile(RT_ELEMENTS(g_apfnVexGroup13RegReg) == 8*4);
3979
3980/** Opcode VEX.0F 0x72. */
3981FNIEMOP_DEF(iemOp_VGrp13)
3982{
3983 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3984 if (IEM_IS_MODRM_REG_MODE(bRm))
3985 /* register, register */
3986 return FNIEMOP_CALL_1(g_apfnVexGroup13RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3987 + pVCpu->iem.s.idxPrefix], bRm);
3988 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3989}
3990
3991
3992/* Opcode VEX.0F 0x73 11/2 - invalid. */
3993/** Opcode VEX.66.0F 0x73 11/2. */
3994FNIEMOP_DEF_1(iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, uint8_t, bRm)
3995{
3996 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLQ, vpsrlq, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3997 if (pVCpu->iem.s.uVexLength)
3998 {
3999 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
4000 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback));
4001 }
4002 else
4003 {
4004 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
4005 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback));
4006 }
4007}
4008
4009
4010/** Opcode VEX.66.0F 0x73 11/3. */
4011FNIEMOP_DEF_1(iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, uint8_t, bRm)
4012{
4013 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLDQ, vpsrldq, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4014 if (pVCpu->iem.s.uVexLength)
4015 {
4016 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
4017 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrldq_imm_u256, iemAImpl_vpsrldq_imm_u256_fallback));
4018 }
4019 else
4020 {
4021 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
4022 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrldq_imm_u128, iemAImpl_vpsrldq_imm_u128_fallback));
4023 }
4024}
4025
4026/* Opcode VEX.0F 0x73 11/6 - invalid. */
4027
4028/** Opcode VEX.66.0F 0x73 11/6. */
4029FNIEMOP_DEF_1(iemOp_VGrp14_vpsllq_Hx_Ux_Ib, uint8_t, bRm)
4030{
4031 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSLLQ, vpsllq, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4032 if (pVCpu->iem.s.uVexLength)
4033 {
4034 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
4035 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback));
4036 }
4037 else
4038 {
4039 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
4040 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback));
4041 }
4042}
4043
4044/** Opcode VEX.66.0F 0x73 11/7. */
4045FNIEMOP_DEF_1(iemOp_VGrp14_vpslldq_Hx_Ux_Ib, uint8_t, bRm)
4046{
4047 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSLLDQ, vpslldq, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4048 if (pVCpu->iem.s.uVexLength)
4049 {
4050 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
4051 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpslldq_imm_u256, iemAImpl_vpslldq_imm_u256_fallback));
4052 }
4053 else
4054 {
4055 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
4056 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpslldq_imm_u128, iemAImpl_vpslldq_imm_u128_fallback));
4057 }
4058}
4059
4060/* Opcode VEX.0F 0x73 11/6 - invalid. */
4061
4062/**
4063 * Group 14 jump table for register variant.
4064 */
4065IEM_STATIC const PFNIEMOPRM g_apfnVexGroup14RegReg[] =
4066{
4067 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4068 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4069 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4070 /* /3 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4071 /* /4 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4072 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4073 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsllq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4074 /* /7 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpslldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4075};
4076AssertCompile(RT_ELEMENTS(g_apfnVexGroup14RegReg) == 8*4);
4077
4078
4079/** Opcode VEX.0F 0x73. */
4080FNIEMOP_DEF(iemOp_VGrp14)
4081{
4082 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4083 if (IEM_IS_MODRM_REG_MODE(bRm))
4084 /* register, register */
4085 return FNIEMOP_CALL_1(g_apfnVexGroup14RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
4086 + pVCpu->iem.s.idxPrefix], bRm);
4087 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
4088}
4089
4090
4091/* Opcode VEX.0F 0x74 - invalid */
4092
4093
4094/** Opcode VEX.66.0F 0x74 - vpcmpeqb Vx, Hx, Wx */
4095FNIEMOP_DEF(iemOp_vpcmpeqb_Vx_Hx_Wx)
4096{
4097 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQB, vpcmpeqb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4098 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpeqb);
4099 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4100}
4101
4102/* Opcode VEX.F3.0F 0x74 - invalid */
4103/* Opcode VEX.F2.0F 0x74 - invalid */
4104
4105
4106/* Opcode VEX.0F 0x75 - invalid */
4107
4108
4109/** Opcode VEX.66.0F 0x75 - vpcmpeqw Vx, Hx, Wx */
4110FNIEMOP_DEF(iemOp_vpcmpeqw_Vx_Hx_Wx)
4111{
4112 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQW, vpcmpeqw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4113 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpeqw);
4114 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4115}
4116
4117
4118/* Opcode VEX.F3.0F 0x75 - invalid */
4119/* Opcode VEX.F2.0F 0x75 - invalid */
4120
4121
4122/* Opcode VEX.0F 0x76 - invalid */
4123
4124
4125/** Opcode VEX.66.0F 0x76 - vpcmpeqd Vx, Hx, Wx */
4126FNIEMOP_DEF(iemOp_vpcmpeqd_Vx_Hx_Wx)
4127{
4128 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQD, vpcmpeqd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4129 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpeqd);
4130 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4131}
4132
4133
4134/* Opcode VEX.F3.0F 0x76 - invalid */
4135/* Opcode VEX.F2.0F 0x76 - invalid */
4136
4137
4138/** Opcode VEX.0F 0x77 - vzeroupperv vzeroallv */
4139FNIEMOP_DEF(iemOp_vzeroupperv__vzeroallv)
4140{
4141 Assert(pVCpu->iem.s.uVexLength <= 1);
4142 if (pVCpu->iem.s.uVexLength == 0)
4143 {
4144 /*
4145 * 128-bit: vzeroupper
4146 */
4147 IEMOP_MNEMONIC(vzeroupper, "vzeroupper");
4148 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4149
4150 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4151 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4152 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4153
4154 IEM_MC_CLEAR_YREG_128_UP(0);
4155 IEM_MC_CLEAR_YREG_128_UP(1);
4156 IEM_MC_CLEAR_YREG_128_UP(2);
4157 IEM_MC_CLEAR_YREG_128_UP(3);
4158 IEM_MC_CLEAR_YREG_128_UP(4);
4159 IEM_MC_CLEAR_YREG_128_UP(5);
4160 IEM_MC_CLEAR_YREG_128_UP(6);
4161 IEM_MC_CLEAR_YREG_128_UP(7);
4162
4163 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4164 {
4165 IEM_MC_CLEAR_YREG_128_UP( 8);
4166 IEM_MC_CLEAR_YREG_128_UP( 9);
4167 IEM_MC_CLEAR_YREG_128_UP(10);
4168 IEM_MC_CLEAR_YREG_128_UP(11);
4169 IEM_MC_CLEAR_YREG_128_UP(12);
4170 IEM_MC_CLEAR_YREG_128_UP(13);
4171 IEM_MC_CLEAR_YREG_128_UP(14);
4172 IEM_MC_CLEAR_YREG_128_UP(15);
4173 }
4174
4175 IEM_MC_ADVANCE_RIP_AND_FINISH();
4176 IEM_MC_END();
4177 }
4178 else
4179 {
4180 /*
4181 * 256-bit: vzeroall
4182 */
4183 IEMOP_MNEMONIC(vzeroall, "vzeroall");
4184 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4185
4186 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4187 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4188 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4189
4190 IEM_MC_LOCAL_CONST(uint32_t, uZero, 0);
4191 IEM_MC_STORE_YREG_U32_ZX_VLMAX(0, uZero);
4192 IEM_MC_STORE_YREG_U32_ZX_VLMAX(1, uZero);
4193 IEM_MC_STORE_YREG_U32_ZX_VLMAX(2, uZero);
4194 IEM_MC_STORE_YREG_U32_ZX_VLMAX(3, uZero);
4195 IEM_MC_STORE_YREG_U32_ZX_VLMAX(4, uZero);
4196 IEM_MC_STORE_YREG_U32_ZX_VLMAX(5, uZero);
4197 IEM_MC_STORE_YREG_U32_ZX_VLMAX(6, uZero);
4198 IEM_MC_STORE_YREG_U32_ZX_VLMAX(7, uZero);
4199
4200 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4201 {
4202 IEM_MC_STORE_YREG_U32_ZX_VLMAX( 8, uZero);
4203 IEM_MC_STORE_YREG_U32_ZX_VLMAX( 9, uZero);
4204 IEM_MC_STORE_YREG_U32_ZX_VLMAX(10, uZero);
4205 IEM_MC_STORE_YREG_U32_ZX_VLMAX(11, uZero);
4206 IEM_MC_STORE_YREG_U32_ZX_VLMAX(12, uZero);
4207 IEM_MC_STORE_YREG_U32_ZX_VLMAX(13, uZero);
4208 IEM_MC_STORE_YREG_U32_ZX_VLMAX(14, uZero);
4209 IEM_MC_STORE_YREG_U32_ZX_VLMAX(15, uZero);
4210 }
4211
4212 IEM_MC_ADVANCE_RIP_AND_FINISH();
4213 IEM_MC_END();
4214 }
4215}
4216
4217
4218/* Opcode VEX.66.0F 0x77 - invalid */
4219/* Opcode VEX.F3.0F 0x77 - invalid */
4220/* Opcode VEX.F2.0F 0x77 - invalid */
4221
4222/* Opcode VEX.0F 0x78 - invalid */
4223/* Opcode VEX.66.0F 0x78 - invalid */
4224/* Opcode VEX.F3.0F 0x78 - invalid */
4225/* Opcode VEX.F2.0F 0x78 - invalid */
4226
4227/* Opcode VEX.0F 0x79 - invalid */
4228/* Opcode VEX.66.0F 0x79 - invalid */
4229/* Opcode VEX.F3.0F 0x79 - invalid */
4230/* Opcode VEX.F2.0F 0x79 - invalid */
4231
4232/* Opcode VEX.0F 0x7a - invalid */
4233/* Opcode VEX.66.0F 0x7a - invalid */
4234/* Opcode VEX.F3.0F 0x7a - invalid */
4235/* Opcode VEX.F2.0F 0x7a - invalid */
4236
4237/* Opcode VEX.0F 0x7b - invalid */
4238/* Opcode VEX.66.0F 0x7b - invalid */
4239/* Opcode VEX.F3.0F 0x7b - invalid */
4240/* Opcode VEX.F2.0F 0x7b - invalid */
4241
4242/* Opcode VEX.0F 0x7c - invalid */
4243/** Opcode VEX.66.0F 0x7c - vhaddpd Vpd, Hpd, Wpd */
4244FNIEMOP_STUB(iemOp_vhaddpd_Vpd_Hpd_Wpd);
4245/* Opcode VEX.F3.0F 0x7c - invalid */
4246
4247
4248/** Opcode VEX.F2.0F 0x7c - vhaddps Vps, Hps, Wps */
4249FNIEMOP_DEF(iemOp_vhaddps_Vps_Hps_Wps)
4250{
4251 IEMOP_MNEMONIC3(VEX_RVM, VHADDPS, vhaddps, Vps, Hps, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4252 IEMOPMEDIAF3_INIT_VARS( vhaddps);
4253 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
4254}
4255
4256
4257/* Opcode VEX.0F 0x7d - invalid */
4258/** Opcode VEX.66.0F 0x7d - vhsubpd Vpd, Hpd, Wpd */
4259FNIEMOP_STUB(iemOp_vhsubpd_Vpd_Hpd_Wpd);
4260/* Opcode VEX.F3.0F 0x7d - invalid */
4261/** Opcode VEX.F2.0F 0x7d - vhsubps Vps, Hps, Wps */
4262FNIEMOP_STUB(iemOp_vhsubps_Vps_Hps_Wps);
4263
4264
4265/* Opcode VEX.0F 0x7e - invalid */
4266
4267FNIEMOP_DEF(iemOp_vmovd_q_Ey_Vy)
4268{
4269 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4270 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
4271 {
4272 /**
4273 * @opcode 0x7e
4274 * @opcodesub rex.w=1
4275 * @oppfx 0x66
4276 * @opcpuid avx
4277 * @opgroup og_avx_simdint_datamov
4278 * @opxcpttype 5
4279 * @optest 64-bit / op1=1 op2=2 -> op1=2
4280 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
4281 */
4282 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Eq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
4283 if (IEM_IS_MODRM_REG_MODE(bRm))
4284 {
4285 /* greg64, XMM */
4286 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
4287 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4288 IEM_MC_LOCAL(uint64_t, u64Tmp);
4289
4290 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4291 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4292
4293 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
4294 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Tmp);
4295
4296 IEM_MC_ADVANCE_RIP_AND_FINISH();
4297 IEM_MC_END();
4298 }
4299 else
4300 {
4301 /* [mem64], XMM */
4302 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
4303 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4304 IEM_MC_LOCAL(uint64_t, u64Tmp);
4305
4306 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4307 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4308 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4309 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4310
4311 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
4312 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
4313
4314 IEM_MC_ADVANCE_RIP_AND_FINISH();
4315 IEM_MC_END();
4316 }
4317 }
4318 else
4319 {
4320 /**
4321 * @opdone
4322 * @opcode 0x7e
4323 * @opcodesub rex.w=0
4324 * @oppfx 0x66
4325 * @opcpuid avx
4326 * @opgroup og_avx_simdint_datamov
4327 * @opxcpttype 5
4328 * @opfunction iemOp_vmovd_q_Vy_Ey
4329 * @optest op1=1 op2=2 -> op1=2
4330 * @optest op1=0 op2=-42 -> op1=-42
4331 */
4332 IEMOP_MNEMONIC2(VEX_MR, VMOVD, vmovd, Ed_WO, Vd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
4333 if (IEM_IS_MODRM_REG_MODE(bRm))
4334 {
4335 /* greg32, XMM */
4336 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4337 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4338 IEM_MC_LOCAL(uint32_t, u32Tmp);
4339
4340 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4341 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4342
4343 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4344 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Tmp);
4345
4346 IEM_MC_ADVANCE_RIP_AND_FINISH();
4347 IEM_MC_END();
4348 }
4349 else
4350 {
4351 /* [mem32], XMM */
4352 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4353 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4354 IEM_MC_LOCAL(uint32_t, u32Tmp);
4355
4356 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4357 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4358 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4359 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4360
4361 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4362 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
4363
4364 IEM_MC_ADVANCE_RIP_AND_FINISH();
4365 IEM_MC_END();
4366 }
4367 }
4368}
4369
4370
4371/**
4372 * @opcode 0x7e
4373 * @oppfx 0xf3
4374 * @opcpuid avx
4375 * @opgroup og_avx_pcksclr_datamove
4376 * @opxcpttype none
4377 * @optest op1=1 op2=2 -> op1=2
4378 * @optest op1=0 op2=-42 -> op1=-42
4379 */
4380FNIEMOP_DEF(iemOp_vmovq_Vq_Wq)
4381{
4382 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
4383 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4384 if (IEM_IS_MODRM_REG_MODE(bRm))
4385 {
4386 /*
4387 * Register, register.
4388 */
4389 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4390 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4391
4392 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4393 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4394
4395 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
4396 IEM_GET_MODRM_RM(pVCpu, bRm));
4397 IEM_MC_ADVANCE_RIP_AND_FINISH();
4398 IEM_MC_END();
4399 }
4400 else
4401 {
4402 /*
4403 * Memory, register.
4404 */
4405 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4406 IEM_MC_LOCAL(uint64_t, uSrc);
4407 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4408
4409 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4410 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4411 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4412 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4413
4414 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4415 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
4416
4417 IEM_MC_ADVANCE_RIP_AND_FINISH();
4418 IEM_MC_END();
4419 }
4420
4421}
4422/* Opcode VEX.F2.0F 0x7e - invalid */
4423
4424
4425/* Opcode VEX.0F 0x7f - invalid */
4426
4427/**
4428 * @opcode 0x7f
4429 * @oppfx 0x66
4430 * @opcpuid avx
4431 * @opgroup og_avx_simdint_datamove
4432 * @opxcpttype 1
4433 * @optest op1=1 op2=2 -> op1=2
4434 * @optest op1=0 op2=-42 -> op1=-42
4435 */
4436FNIEMOP_DEF(iemOp_vmovdqa_Wx_Vx)
4437{
4438 IEMOP_MNEMONIC2(VEX_MR, VMOVDQA, vmovdqa, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4439 Assert(pVCpu->iem.s.uVexLength <= 1);
4440 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4441 if (IEM_IS_MODRM_REG_MODE(bRm))
4442 {
4443 /*
4444 * Register, register.
4445 */
4446 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4447 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4448
4449 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4450 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4451 if (pVCpu->iem.s.uVexLength == 0)
4452 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4453 IEM_GET_MODRM_REG(pVCpu, bRm));
4454 else
4455 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4456 IEM_GET_MODRM_REG(pVCpu, bRm));
4457 IEM_MC_ADVANCE_RIP_AND_FINISH();
4458 IEM_MC_END();
4459 }
4460 else if (pVCpu->iem.s.uVexLength == 0)
4461 {
4462 /*
4463 * Register, memory128.
4464 */
4465 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4466 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4467 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4468
4469 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4470 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4471 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4472 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4473
4474 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
4475 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
4476
4477 IEM_MC_ADVANCE_RIP_AND_FINISH();
4478 IEM_MC_END();
4479 }
4480 else
4481 {
4482 /*
4483 * Register, memory256.
4484 */
4485 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4486 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
4487 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4488
4489 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4490 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4491 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4492 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4493
4494 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4495 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
4496
4497 IEM_MC_ADVANCE_RIP_AND_FINISH();
4498 IEM_MC_END();
4499 }
4500}
4501
4502
4503/**
4504 * @opcode 0x7f
4505 * @oppfx 0xf3
4506 * @opcpuid avx
4507 * @opgroup og_avx_simdint_datamove
4508 * @opxcpttype 4UA
4509 * @optest op1=1 op2=2 -> op1=2
4510 * @optest op1=0 op2=-42 -> op1=-42
4511 */
4512FNIEMOP_DEF(iemOp_vmovdqu_Wx_Vx)
4513{
4514 IEMOP_MNEMONIC2(VEX_MR, VMOVDQU, vmovdqu, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4515 Assert(pVCpu->iem.s.uVexLength <= 1);
4516 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4517 if (IEM_IS_MODRM_REG_MODE(bRm))
4518 {
4519 /*
4520 * Register, register.
4521 */
4522 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4523 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4524
4525 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4526 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4527 if (pVCpu->iem.s.uVexLength == 0)
4528 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4529 IEM_GET_MODRM_REG(pVCpu, bRm));
4530 else
4531 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4532 IEM_GET_MODRM_REG(pVCpu, bRm));
4533 IEM_MC_ADVANCE_RIP_AND_FINISH();
4534 IEM_MC_END();
4535 }
4536 else if (pVCpu->iem.s.uVexLength == 0)
4537 {
4538 /*
4539 * Register, memory128.
4540 */
4541 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4542 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4543 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4544
4545 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4546 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4547 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4548 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4549
4550 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
4551 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
4552
4553 IEM_MC_ADVANCE_RIP_AND_FINISH();
4554 IEM_MC_END();
4555 }
4556 else
4557 {
4558 /*
4559 * Register, memory256.
4560 */
4561 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4562 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
4563 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4564
4565 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4566 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4567 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4568 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4569
4570 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4571 IEM_MC_STORE_MEM_U256_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
4572
4573 IEM_MC_ADVANCE_RIP_AND_FINISH();
4574 IEM_MC_END();
4575 }
4576}
4577
4578/* Opcode VEX.F2.0F 0x7f - invalid */
4579
4580
4581/* Opcode VEX.0F 0x80 - invalid */
4582/* Opcode VEX.0F 0x81 - invalid */
4583/* Opcode VEX.0F 0x82 - invalid */
4584/* Opcode VEX.0F 0x83 - invalid */
4585/* Opcode VEX.0F 0x84 - invalid */
4586/* Opcode VEX.0F 0x85 - invalid */
4587/* Opcode VEX.0F 0x86 - invalid */
4588/* Opcode VEX.0F 0x87 - invalid */
4589/* Opcode VEX.0F 0x88 - invalid */
4590/* Opcode VEX.0F 0x89 - invalid */
4591/* Opcode VEX.0F 0x8a - invalid */
4592/* Opcode VEX.0F 0x8b - invalid */
4593/* Opcode VEX.0F 0x8c - invalid */
4594/* Opcode VEX.0F 0x8d - invalid */
4595/* Opcode VEX.0F 0x8e - invalid */
4596/* Opcode VEX.0F 0x8f - invalid */
4597/* Opcode VEX.0F 0x90 - invalid */
4598/* Opcode VEX.0F 0x91 - invalid */
4599/* Opcode VEX.0F 0x92 - invalid */
4600/* Opcode VEX.0F 0x93 - invalid */
4601/* Opcode VEX.0F 0x94 - invalid */
4602/* Opcode VEX.0F 0x95 - invalid */
4603/* Opcode VEX.0F 0x96 - invalid */
4604/* Opcode VEX.0F 0x97 - invalid */
4605/* Opcode VEX.0F 0x98 - invalid */
4606/* Opcode VEX.0F 0x99 - invalid */
4607/* Opcode VEX.0F 0x9a - invalid */
4608/* Opcode VEX.0F 0x9b - invalid */
4609/* Opcode VEX.0F 0x9c - invalid */
4610/* Opcode VEX.0F 0x9d - invalid */
4611/* Opcode VEX.0F 0x9e - invalid */
4612/* Opcode VEX.0F 0x9f - invalid */
4613/* Opcode VEX.0F 0xa0 - invalid */
4614/* Opcode VEX.0F 0xa1 - invalid */
4615/* Opcode VEX.0F 0xa2 - invalid */
4616/* Opcode VEX.0F 0xa3 - invalid */
4617/* Opcode VEX.0F 0xa4 - invalid */
4618/* Opcode VEX.0F 0xa5 - invalid */
4619/* Opcode VEX.0F 0xa6 - invalid */
4620/* Opcode VEX.0F 0xa7 - invalid */
4621/* Opcode VEX.0F 0xa8 - invalid */
4622/* Opcode VEX.0F 0xa9 - invalid */
4623/* Opcode VEX.0F 0xaa - invalid */
4624/* Opcode VEX.0F 0xab - invalid */
4625/* Opcode VEX.0F 0xac - invalid */
4626/* Opcode VEX.0F 0xad - invalid */
4627
4628
4629/* Opcode VEX.0F 0xae mem/0 - invalid. */
4630/* Opcode VEX.0F 0xae mem/1 - invalid. */
4631
4632/**
4633 * @ opmaps grp15
4634 * @ opcode !11/2
4635 * @ oppfx none
4636 * @ opcpuid sse
4637 * @ opgroup og_sse_mxcsrsm
4638 * @ opxcpttype 5
4639 * @ optest op1=0 -> mxcsr=0
4640 * @ optest op1=0x2083 -> mxcsr=0x2083
4641 * @ optest op1=0xfffffffe -> value.xcpt=0xd
4642 * @ optest op1=0x2083 cr0|=ts -> value.xcpt=0x7
4643 * @ optest op1=0x2083 cr0|=em -> value.xcpt=0x6
4644 * @ optest op1=0x2083 cr0|=mp -> mxcsr=0x2083
4645 * @ optest op1=0x2083 cr4&~=osfxsr -> value.xcpt=0x6
4646 * @ optest op1=0x2083 cr0|=ts,em -> value.xcpt=0x6
4647 * @ optest op1=0x2083 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
4648 * @ optest op1=0x2083 cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
4649 * @ optest op1=0x2083 cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
4650 */
4651FNIEMOP_STUB_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm);
4652//FNIEMOP_DEF_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm)
4653//{
4654// IEMOP_MNEMONIC1(M_MEM, VLDMXCSR, vldmxcsr, MdRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
4655// IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4656// IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
4657// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
4658// IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4659// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4660// IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
4661// IEM_MC_CALL_CIMPL_2(iemCImpl_ldmxcsr, iEffSeg, GCPtrEff);
4662// IEM_MC_END();
4663// return VINF_SUCCESS;
4664//}
4665
4666
4667/**
4668 * @opmaps vexgrp15
4669 * @opcode !11/3
4670 * @oppfx none
4671 * @opcpuid avx
4672 * @opgroup og_avx_mxcsrsm
4673 * @opxcpttype 5
4674 * @optest mxcsr=0 -> op1=0
4675 * @optest mxcsr=0x2083 -> op1=0x2083
4676 * @optest mxcsr=0x2084 cr0|=ts -> value.xcpt=0x7
4677 * @optest !amd / mxcsr=0x2085 cr0|=em -> op1=0x2085
4678 * @optest amd / mxcsr=0x2085 cr0|=em -> value.xcpt=0x6
4679 * @optest mxcsr=0x2086 cr0|=mp -> op1=0x2086
4680 * @optest mxcsr=0x2087 cr4&~=osfxsr -> op1=0x2087
4681 * @optest mxcsr=0x208f cr4&~=osxsave -> value.xcpt=0x6
4682 * @optest mxcsr=0x2087 cr4&~=osfxsr,osxsave -> value.xcpt=0x6
4683 * @optest !amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x7
4684 * @optest amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x6
4685 * @optest !amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> op1=0x2089
4686 * @optest amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
4687 * @optest !amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x7
4688 * @optest amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
4689 * @optest !amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x7
4690 * @optest amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
4691 * @optest !amd / mxcsr=0x208c xcr0&~=all_avx -> value.xcpt=0x6
4692 * @optest amd / mxcsr=0x208c xcr0&~=all_avx -> op1=0x208c
4693 * @optest !amd / mxcsr=0x208d xcr0&~=all_avx_sse -> value.xcpt=0x6
4694 * @optest amd / mxcsr=0x208d xcr0&~=all_avx_sse -> op1=0x208d
4695 * @optest !amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x6
4696 * @optest amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x7
4697 * @optest mxcsr=0x2082 cr0|=ts cr4&~=osxsave -> value.xcpt=0x6
4698 * @optest mxcsr=0x2081 xcr0&~=all_avx cr0|=ts cr4&~=osxsave
4699 * -> value.xcpt=0x6
4700 * @remarks AMD Jaguar CPU (f0x16,m0,s1) \#UD when CR0.EM is set. It also
4701 * doesn't seem to check XCR0[2:1] != 11b. This does not match the
4702 * APMv4 rev 3.17 page 509.
4703 * @todo Test this instruction on AMD Ryzen.
4704 */
4705FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr, uint8_t, bRm)
4706{
4707 IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
4708 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4709 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
4710 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
4711 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4712 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4713 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
4714 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_FPU, 0, iemCImpl_vstmxcsr, iEffSeg, GCPtrEff);
4715 IEM_MC_END();
4716}
4717
4718/* Opcode VEX.0F 0xae mem/4 - invalid. */
4719/* Opcode VEX.0F 0xae mem/5 - invalid. */
4720/* Opcode VEX.0F 0xae mem/6 - invalid. */
4721/* Opcode VEX.0F 0xae mem/7 - invalid. */
4722
4723/* Opcode VEX.0F 0xae 11b/0 - invalid. */
4724/* Opcode VEX.0F 0xae 11b/1 - invalid. */
4725/* Opcode VEX.0F 0xae 11b/2 - invalid. */
4726/* Opcode VEX.0F 0xae 11b/3 - invalid. */
4727/* Opcode VEX.0F 0xae 11b/4 - invalid. */
4728/* Opcode VEX.0F 0xae 11b/5 - invalid. */
4729/* Opcode VEX.0F 0xae 11b/6 - invalid. */
4730/* Opcode VEX.0F 0xae 11b/7 - invalid. */
4731
4732/**
4733 * Vex group 15 jump table for memory variant.
4734 */
4735IEM_STATIC const PFNIEMOPRM g_apfnVexGroup15MemReg[] =
4736{ /* pfx: none, 066h, 0f3h, 0f2h */
4737 /* /0 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4738 /* /1 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4739 /* /2 */ iemOp_VGrp15_vldmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4740 /* /3 */ iemOp_VGrp15_vstmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4741 /* /4 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4742 /* /5 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4743 /* /6 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4744 /* /7 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4745};
4746AssertCompile(RT_ELEMENTS(g_apfnVexGroup15MemReg) == 8*4);
4747
4748
4749/** Opcode vex. 0xae. */
4750FNIEMOP_DEF(iemOp_VGrp15)
4751{
4752 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4753 if (IEM_IS_MODRM_REG_MODE(bRm))
4754 /* register, register */
4755 return FNIEMOP_CALL_1(iemOp_InvalidWithRM, bRm);
4756
4757 /* memory, register */
4758 return FNIEMOP_CALL_1(g_apfnVexGroup15MemReg[ IEM_GET_MODRM_REG_8(bRm) * 4
4759 + pVCpu->iem.s.idxPrefix], bRm);
4760}
4761
4762
4763/* Opcode VEX.0F 0xaf - invalid. */
4764
4765/* Opcode VEX.0F 0xb0 - invalid. */
4766/* Opcode VEX.0F 0xb1 - invalid. */
4767/* Opcode VEX.0F 0xb2 - invalid. */
4768/* Opcode VEX.0F 0xb2 - invalid. */
4769/* Opcode VEX.0F 0xb3 - invalid. */
4770/* Opcode VEX.0F 0xb4 - invalid. */
4771/* Opcode VEX.0F 0xb5 - invalid. */
4772/* Opcode VEX.0F 0xb6 - invalid. */
4773/* Opcode VEX.0F 0xb7 - invalid. */
4774/* Opcode VEX.0F 0xb8 - invalid. */
4775/* Opcode VEX.0F 0xb9 - invalid. */
4776/* Opcode VEX.0F 0xba - invalid. */
4777/* Opcode VEX.0F 0xbb - invalid. */
4778/* Opcode VEX.0F 0xbc - invalid. */
4779/* Opcode VEX.0F 0xbd - invalid. */
4780/* Opcode VEX.0F 0xbe - invalid. */
4781/* Opcode VEX.0F 0xbf - invalid. */
4782
4783/* Opcode VEX.0F 0xc0 - invalid. */
4784/* Opcode VEX.66.0F 0xc0 - invalid. */
4785/* Opcode VEX.F3.0F 0xc0 - invalid. */
4786/* Opcode VEX.F2.0F 0xc0 - invalid. */
4787
4788/* Opcode VEX.0F 0xc1 - invalid. */
4789/* Opcode VEX.66.0F 0xc1 - invalid. */
4790/* Opcode VEX.F3.0F 0xc1 - invalid. */
4791/* Opcode VEX.F2.0F 0xc1 - invalid. */
4792
4793/** Opcode VEX.0F 0xc2 - vcmpps Vps,Hps,Wps,Ib */
4794FNIEMOP_STUB(iemOp_vcmpps_Vps_Hps_Wps_Ib);
4795/** Opcode VEX.66.0F 0xc2 - vcmppd Vpd,Hpd,Wpd,Ib */
4796FNIEMOP_STUB(iemOp_vcmppd_Vpd_Hpd_Wpd_Ib);
4797/** Opcode VEX.F3.0F 0xc2 - vcmpss Vss,Hss,Wss,Ib */
4798FNIEMOP_STUB(iemOp_vcmpss_Vss_Hss_Wss_Ib);
4799/** Opcode VEX.F2.0F 0xc2 - vcmpsd Vsd,Hsd,Wsd,Ib */
4800FNIEMOP_STUB(iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib);
4801
4802/* Opcode VEX.0F 0xc3 - invalid */
4803/* Opcode VEX.66.0F 0xc3 - invalid */
4804/* Opcode VEX.F3.0F 0xc3 - invalid */
4805/* Opcode VEX.F2.0F 0xc3 - invalid */
4806
4807/* Opcode VEX.0F 0xc4 - invalid */
4808
4809
4810/** Opcode VEX.66.0F 0xc4 - vpinsrw Vdq,Hdq,Ry/Mw,Ib */
4811FNIEMOP_DEF(iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib)
4812{
4813 /*IEMOP_MNEMONIC4(VEX_RMV, VPINSRW, vpinsrw, Vdq, Vdq, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);*/ /** @todo */
4814 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4815 if (IEM_IS_MODRM_REG_MODE(bRm))
4816 {
4817 /*
4818 * Register, register.
4819 */
4820 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4821 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4822 IEM_MC_LOCAL(RTUINT128U, uSrc1);
4823 IEM_MC_LOCAL(uint16_t, uValue);
4824
4825 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4826 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4827 IEM_MC_PREPARE_AVX_USAGE();
4828
4829 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
4830 IEM_MC_FETCH_GREG_U16(uValue, IEM_GET_MODRM_RM(pVCpu, bRm));
4831 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
4832 IEM_MC_STORE_XREG_U16( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7, uValue);
4833 IEM_MC_ADVANCE_RIP_AND_FINISH();
4834 IEM_MC_END();
4835 }
4836 else
4837 {
4838 /*
4839 * Register, memory.
4840 */
4841 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4842 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4843 IEM_MC_LOCAL(RTUINT128U, uSrc1);
4844 IEM_MC_LOCAL(uint16_t, uValue);
4845
4846 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
4847 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4848 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4849 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4850 IEM_MC_PREPARE_AVX_USAGE();
4851
4852 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
4853 IEM_MC_FETCH_MEM_U16(uValue, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4854 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
4855 IEM_MC_STORE_XREG_U16( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7, uValue);
4856 IEM_MC_ADVANCE_RIP_AND_FINISH();
4857 IEM_MC_END();
4858 }
4859}
4860
4861
4862/* Opcode VEX.F3.0F 0xc4 - invalid */
4863/* Opcode VEX.F2.0F 0xc4 - invalid */
4864
4865/* Opcode VEX.0F 0xc5 - invalid */
4866
4867
4868/** Opcode VEX.66.0F 0xc5 - vpextrw Gd, Udq, Ib */
4869FNIEMOP_DEF(iemOp_vpextrw_Gd_Udq_Ib)
4870{
4871 IEMOP_MNEMONIC3(VEX_RMI_REG, VPEXTRW, vpextrw, Gd, Ux, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
4872 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4873 if (IEM_IS_MODRM_REG_MODE(bRm))
4874 {
4875 /*
4876 * greg32, XMM, imm8.
4877 */
4878 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4879 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4880 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4881 IEM_MC_LOCAL(uint16_t, uValue);
4882 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4883 IEM_MC_PREPARE_AVX_USAGE();
4884 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_RM(pVCpu, bRm), bImm & 7);
4885 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uValue);
4886 IEM_MC_ADVANCE_RIP_AND_FINISH();
4887 IEM_MC_END();
4888 }
4889 /* No memory operand. */
4890 else
4891 IEMOP_RAISE_INVALID_OPCODE_RET();
4892}
4893
4894
4895/* Opcode VEX.F3.0F 0xc5 - invalid */
4896/* Opcode VEX.F2.0F 0xc5 - invalid */
4897
4898
4899#define VSHUFP_X(a_Instr) \
4900 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
4901 if (IEM_IS_MODRM_REG_MODE(bRm)) \
4902 { \
4903 /* \
4904 * Register, register. \
4905 */ \
4906 if (pVCpu->iem.s.uVexLength) \
4907 { \
4908 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4909 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
4910 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
4911 IEM_MC_LOCAL(RTUINT256U, uDst); \
4912 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
4913 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
4914 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
4915 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
4916 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
4917 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4918 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
4919 IEM_MC_PREPARE_AVX_USAGE(); \
4920 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4921 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
4922 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
4923 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4924 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
4925 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4926 IEM_MC_END(); \
4927 } \
4928 else \
4929 { \
4930 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4931 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
4932 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
4933 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
4934 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
4935 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2); \
4936 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4937 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
4938 IEM_MC_PREPARE_AVX_USAGE(); \
4939 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
4940 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4941 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
4942 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
4943 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4944 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
4945 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4946 IEM_MC_END(); \
4947 } \
4948 } \
4949 else \
4950 { \
4951 /* \
4952 * Register, memory. \
4953 */ \
4954 if (pVCpu->iem.s.uVexLength) \
4955 { \
4956 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
4957 IEM_MC_LOCAL(RTUINT256U, uDst); \
4958 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
4959 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
4960 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
4961 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
4962 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
4963 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
4964 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
4965 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4966 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4967 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
4968 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
4969 IEM_MC_PREPARE_AVX_USAGE(); \
4970 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
4971 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4972 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
4973 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4974 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
4975 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4976 IEM_MC_END(); \
4977 } \
4978 else \
4979 { \
4980 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
4981 IEM_MC_LOCAL(RTUINT128U, uSrc2); \
4982 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
4983 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
4984 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
4985 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2); \
4986 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
4987 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4988 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4989 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
4990 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
4991 IEM_MC_PREPARE_AVX_USAGE(); \
4992 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
4993 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
4994 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4995 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
4996 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4997 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
4998 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4999 IEM_MC_END(); \
5000 } \
5001 } \
5002 (void)0
5003
5004/** Opcode VEX.0F 0xc6 - vshufps Vps,Hps,Wps,Ib */
5005FNIEMOP_DEF(iemOp_vshufps_Vps_Hps_Wps_Ib)
5006{
5007 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPS, vshufps, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
5008 VSHUFP_X(vshufps);
5009}
5010
5011
5012/** Opcode VEX.66.0F 0xc6 - vshufpd Vpd,Hpd,Wpd,Ib */
5013FNIEMOP_DEF(iemOp_vshufpd_Vpd_Hpd_Wpd_Ib)
5014{
5015 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPD, vshufpd, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
5016 VSHUFP_X(vshufpd);
5017}
5018#undef VSHUFP_X
5019
5020
5021/* Opcode VEX.F3.0F 0xc6 - invalid */
5022/* Opcode VEX.F2.0F 0xc6 - invalid */
5023
5024/* Opcode VEX.0F 0xc7 - invalid */
5025/* Opcode VEX.66.0F 0xc7 - invalid */
5026/* Opcode VEX.F3.0F 0xc7 - invalid */
5027/* Opcode VEX.F2.0F 0xc7 - invalid */
5028
5029/* Opcode VEX.0F 0xc8 - invalid */
5030/* Opcode VEX.0F 0xc9 - invalid */
5031/* Opcode VEX.0F 0xca - invalid */
5032/* Opcode VEX.0F 0xcb - invalid */
5033/* Opcode VEX.0F 0xcc - invalid */
5034/* Opcode VEX.0F 0xcd - invalid */
5035/* Opcode VEX.0F 0xce - invalid */
5036/* Opcode VEX.0F 0xcf - invalid */
5037
5038
5039/* Opcode VEX.0F 0xd0 - invalid */
5040/** Opcode VEX.66.0F 0xd0 - vaddsubpd Vpd, Hpd, Wpd */
5041FNIEMOP_STUB(iemOp_vaddsubpd_Vpd_Hpd_Wpd);
5042/* Opcode VEX.F3.0F 0xd0 - invalid */
5043/** Opcode VEX.F2.0F 0xd0 - vaddsubps Vps, Hps, Wps */
5044FNIEMOP_STUB(iemOp_vaddsubps_Vps_Hps_Wps);
5045
5046/* Opcode VEX.0F 0xd1 - invalid */
5047/** Opcode VEX.66.0F 0xd1 - vpsrlw Vx, Hx, W */
5048FNIEMOP_DEF(iemOp_vpsrlw_Vx_Hx_W)
5049{
5050 IEMOP_MNEMONIC3(VEX_RVM, VPSRLW, vpsrlw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5051 IEMOPMEDIAOPTF3_INIT_VARS(vpsrlw);
5052 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5053}
5054
5055/* Opcode VEX.F3.0F 0xd1 - invalid */
5056/* Opcode VEX.F2.0F 0xd1 - invalid */
5057
5058/* Opcode VEX.0F 0xd2 - invalid */
5059/** Opcode VEX.66.0F 0xd2 - vpsrld Vx, Hx, Wx */
5060FNIEMOP_DEF(iemOp_vpsrld_Vx_Hx_Wx)
5061{
5062 IEMOP_MNEMONIC3(VEX_RVM, VPSRLD, vpsrld, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5063 IEMOPMEDIAOPTF3_INIT_VARS(vpsrld);
5064 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5065}
5066
5067/* Opcode VEX.F3.0F 0xd2 - invalid */
5068/* Opcode VEX.F2.0F 0xd2 - invalid */
5069
5070/* Opcode VEX.0F 0xd3 - invalid */
5071/** Opcode VEX.66.0F 0xd3 - vpsrlq Vx, Hx, Wx */
5072FNIEMOP_DEF(iemOp_vpsrlq_Vx_Hx_Wx)
5073{
5074 IEMOP_MNEMONIC3(VEX_RVM, VPSRLQ, vpsrlq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5075 IEMOPMEDIAOPTF3_INIT_VARS(vpsrlq);
5076 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5077}
5078
5079/* Opcode VEX.F3.0F 0xd3 - invalid */
5080/* Opcode VEX.F2.0F 0xd3 - invalid */
5081
5082/* Opcode VEX.0F 0xd4 - invalid */
5083
5084
5085/** Opcode VEX.66.0F 0xd4 - vpaddq Vx, Hx, W */
5086FNIEMOP_DEF(iemOp_vpaddq_Vx_Hx_Wx)
5087{
5088 IEMOP_MNEMONIC3(VEX_RVM, VPADDQ, vpaddq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5089 IEMOPMEDIAOPTF3_INIT_VARS( vpaddq);
5090 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5091}
5092
5093
5094/* Opcode VEX.F3.0F 0xd4 - invalid */
5095/* Opcode VEX.F2.0F 0xd4 - invalid */
5096
5097/* Opcode VEX.0F 0xd5 - invalid */
5098
5099
5100/** Opcode VEX.66.0F 0xd5 - vpmullw Vx, Hx, Wx */
5101FNIEMOP_DEF(iemOp_vpmullw_Vx_Hx_Wx)
5102{
5103 IEMOP_MNEMONIC3(VEX_RVM, VPMULLW, vpmullw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5104 IEMOPMEDIAOPTF3_INIT_VARS(vpmullw);
5105 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5106}
5107
5108
5109/* Opcode VEX.F3.0F 0xd5 - invalid */
5110/* Opcode VEX.F2.0F 0xd5 - invalid */
5111
5112/* Opcode VEX.0F 0xd6 - invalid */
5113
5114/**
5115 * @opcode 0xd6
5116 * @oppfx 0x66
5117 * @opcpuid avx
5118 * @opgroup og_avx_pcksclr_datamove
5119 * @opxcpttype none
5120 * @optest op1=-1 op2=2 -> op1=2
5121 * @optest op1=0 op2=-42 -> op1=-42
5122 */
5123FNIEMOP_DEF(iemOp_vmovq_Wq_Vq)
5124{
5125 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Wq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
5126 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5127 if (IEM_IS_MODRM_REG_MODE(bRm))
5128 {
5129 /*
5130 * Register, register.
5131 */
5132 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5133 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
5134
5135 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5136 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
5137
5138 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
5139 IEM_GET_MODRM_REG(pVCpu, bRm));
5140 IEM_MC_ADVANCE_RIP_AND_FINISH();
5141 IEM_MC_END();
5142 }
5143 else
5144 {
5145 /*
5146 * Memory, register.
5147 */
5148 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5149 IEM_MC_LOCAL(uint64_t, uSrc);
5150 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5151
5152 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5153 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
5154 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5155 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
5156
5157 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
5158 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
5159
5160 IEM_MC_ADVANCE_RIP_AND_FINISH();
5161 IEM_MC_END();
5162 }
5163}
5164
5165/* Opcode VEX.F3.0F 0xd6 - invalid */
5166/* Opcode VEX.F2.0F 0xd6 - invalid */
5167
5168
5169/* Opcode VEX.0F 0xd7 - invalid */
5170
5171/** Opcode VEX.66.0F 0xd7 - */
5172FNIEMOP_DEF(iemOp_vpmovmskb_Gd_Ux)
5173{
5174 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5175 /* Docs says register only. */
5176 if (IEM_IS_MODRM_REG_MODE(bRm)) /** @todo test that this is registers only. */
5177 {
5178 /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
5179 IEMOP_MNEMONIC2(VEX_RM_REG, VPMOVMSKB, vpmovmskb, Gd, Ux, DISOPTYPE_X86_SSE | DISOPTYPE_HARMLESS, 0);
5180 if (pVCpu->iem.s.uVexLength)
5181 {
5182 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5183 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
5184 IEM_MC_ARG(uint64_t *, puDst, 0);
5185 IEM_MC_LOCAL(RTUINT256U, uSrc);
5186 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
5187 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5188 IEM_MC_PREPARE_AVX_USAGE();
5189 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
5190 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
5191 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpmovmskb_u256,
5192 iemAImpl_vpmovmskb_u256_fallback), puDst, puSrc);
5193 IEM_MC_ADVANCE_RIP_AND_FINISH();
5194 IEM_MC_END();
5195 }
5196 else
5197 {
5198 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5199 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5200 IEM_MC_ARG(uint64_t *, puDst, 0);
5201 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
5202 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5203 IEM_MC_PREPARE_AVX_USAGE();
5204 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
5205 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
5206 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_pmovmskb_u128, puDst, puSrc);
5207 IEM_MC_ADVANCE_RIP_AND_FINISH();
5208 IEM_MC_END();
5209 }
5210 }
5211 else
5212 IEMOP_RAISE_INVALID_OPCODE_RET();
5213}
5214
5215
5216/* Opcode VEX.F3.0F 0xd7 - invalid */
5217/* Opcode VEX.F2.0F 0xd7 - invalid */
5218
5219
5220/* Opcode VEX.0F 0xd8 - invalid */
5221
5222/** Opcode VEX.66.0F 0xd8 - vpsubusb Vx, Hx, Wx */
5223FNIEMOP_DEF(iemOp_vpsubusb_Vx_Hx_Wx)
5224{
5225 IEMOP_MNEMONIC3(VEX_RVM, VPSUBUSB, vpsubusb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5226 IEMOPMEDIAOPTF3_INIT_VARS(vpsubusb);
5227 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5228}
5229
5230
5231/* Opcode VEX.F3.0F 0xd8 - invalid */
5232/* Opcode VEX.F2.0F 0xd8 - invalid */
5233
5234/* Opcode VEX.0F 0xd9 - invalid */
5235
5236
5237/** Opcode VEX.66.0F 0xd9 - vpsubusw Vx, Hx, Wx */
5238FNIEMOP_DEF(iemOp_vpsubusw_Vx_Hx_Wx)
5239{
5240 IEMOP_MNEMONIC3(VEX_RVM, VPSUBUSW, vpsubusw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5241 IEMOPMEDIAOPTF3_INIT_VARS(vpsubusw);
5242 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5243}
5244
5245
5246/* Opcode VEX.F3.0F 0xd9 - invalid */
5247/* Opcode VEX.F2.0F 0xd9 - invalid */
5248
5249/* Opcode VEX.0F 0xda - invalid */
5250
5251
5252/** Opcode VEX.66.0F 0xda - vpminub Vx, Hx, Wx */
5253FNIEMOP_DEF(iemOp_vpminub_Vx_Hx_Wx)
5254{
5255 IEMOP_MNEMONIC3(VEX_RVM, VPMINUB, vpminub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5256 IEMOPMEDIAOPTF3_INIT_VARS(vpminub);
5257 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5258}
5259
5260
5261/* Opcode VEX.F3.0F 0xda - invalid */
5262/* Opcode VEX.F2.0F 0xda - invalid */
5263
5264/* Opcode VEX.0F 0xdb - invalid */
5265
5266
5267/** Opcode VEX.66.0F 0xdb - vpand Vx, Hx, Wx */
5268FNIEMOP_DEF(iemOp_vpand_Vx_Hx_Wx)
5269{
5270 IEMOP_MNEMONIC3(VEX_RVM, VPAND, vpand, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5271 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
5272 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
5273}
5274
5275
5276/* Opcode VEX.F3.0F 0xdb - invalid */
5277/* Opcode VEX.F2.0F 0xdb - invalid */
5278
5279/* Opcode VEX.0F 0xdc - invalid */
5280
5281
5282/** Opcode VEX.66.0F 0xdc - vpaddusb Vx, Hx, Wx */
5283FNIEMOP_DEF(iemOp_vpaddusb_Vx_Hx_Wx)
5284{
5285 IEMOP_MNEMONIC3(VEX_RVM, VPADDUSB, vpaddusb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5286 IEMOPMEDIAOPTF3_INIT_VARS(vpaddusb);
5287 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5288}
5289
5290
5291/* Opcode VEX.F3.0F 0xdc - invalid */
5292/* Opcode VEX.F2.0F 0xdc - invalid */
5293
5294/* Opcode VEX.0F 0xdd - invalid */
5295
5296
5297/** Opcode VEX.66.0F 0xdd - vpaddusw Vx, Hx, Wx */
5298FNIEMOP_DEF(iemOp_vpaddusw_Vx_Hx_Wx)
5299{
5300 IEMOP_MNEMONIC3(VEX_RVM, VPADDUSW, vpaddusw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5301 IEMOPMEDIAOPTF3_INIT_VARS(vpaddusw);
5302 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5303}
5304
5305
5306/* Opcode VEX.F3.0F 0xdd - invalid */
5307/* Opcode VEX.F2.0F 0xdd - invalid */
5308
5309/* Opcode VEX.0F 0xde - invalid */
5310
5311
5312/** Opcode VEX.66.0F 0xde - vpmaxub Vx, Hx, Wx */
5313FNIEMOP_DEF(iemOp_vpmaxub_Vx_Hx_Wx)
5314{
5315 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUB, vpmaxub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5316 IEMOPMEDIAOPTF3_INIT_VARS(vpmaxub);
5317 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5318}
5319
5320
5321/* Opcode VEX.F3.0F 0xde - invalid */
5322/* Opcode VEX.F2.0F 0xde - invalid */
5323
5324/* Opcode VEX.0F 0xdf - invalid */
5325
5326
5327/** Opcode VEX.66.0F 0xdf - vpandn Vx, Hx, Wx */
5328FNIEMOP_DEF(iemOp_vpandn_Vx_Hx_Wx)
5329{
5330 IEMOP_MNEMONIC3(VEX_RVM, VPANDN, vpandn, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5331 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
5332 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
5333}
5334
5335
5336/* Opcode VEX.F3.0F 0xdf - invalid */
5337/* Opcode VEX.F2.0F 0xdf - invalid */
5338
5339/* Opcode VEX.0F 0xe0 - invalid */
5340
5341
5342/** Opcode VEX.66.0F 0xe0 - vpavgb Vx, Hx, Wx */
5343FNIEMOP_DEF(iemOp_vpavgb_Vx_Hx_Wx)
5344{
5345 IEMOP_MNEMONIC3(VEX_RVM, VPAVGB, vpavgb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5346 IEMOPMEDIAOPTF3_INIT_VARS(vpavgb);
5347 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5348}
5349
5350
5351/* Opcode VEX.F3.0F 0xe0 - invalid */
5352/* Opcode VEX.F2.0F 0xe0 - invalid */
5353
5354/* Opcode VEX.0F 0xe1 - invalid */
5355/** Opcode VEX.66.0F 0xe1 - vpsraw Vx, Hx, W */
5356FNIEMOP_DEF(iemOp_vpsraw_Vx_Hx_W)
5357{
5358 IEMOP_MNEMONIC3(VEX_RVM, VPSRAW, vpsraw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5359 IEMOPMEDIAOPTF3_INIT_VARS(vpsraw);
5360 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5361}
5362
5363/* Opcode VEX.F3.0F 0xe1 - invalid */
5364/* Opcode VEX.F2.0F 0xe1 - invalid */
5365
5366/* Opcode VEX.0F 0xe2 - invalid */
5367/** Opcode VEX.66.0F 0xe2 - vpsrad Vx, Hx, Wx */
5368FNIEMOP_DEF(iemOp_vpsrad_Vx_Hx_Wx)
5369{
5370 IEMOP_MNEMONIC3(VEX_RVM, VPSRAD, vpsrad, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5371 IEMOPMEDIAOPTF3_INIT_VARS(vpsrad);
5372 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5373}
5374
5375/* Opcode VEX.F3.0F 0xe2 - invalid */
5376/* Opcode VEX.F2.0F 0xe2 - invalid */
5377
5378/* Opcode VEX.0F 0xe3 - invalid */
5379
5380
5381/** Opcode VEX.66.0F 0xe3 - vpavgw Vx, Hx, Wx */
5382FNIEMOP_DEF(iemOp_vpavgw_Vx_Hx_Wx)
5383{
5384 IEMOP_MNEMONIC3(VEX_RVM, VPAVGW, vpavgw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5385 IEMOPMEDIAOPTF3_INIT_VARS(vpavgw);
5386 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5387}
5388
5389
5390/* Opcode VEX.F3.0F 0xe3 - invalid */
5391/* Opcode VEX.F2.0F 0xe3 - invalid */
5392
5393/* Opcode VEX.0F 0xe4 - invalid */
5394
5395
5396/** Opcode VEX.66.0F 0xe4 - vpmulhuw Vx, Hx, Wx */
5397FNIEMOP_DEF(iemOp_vpmulhuw_Vx_Hx_Wx)
5398{
5399 IEMOP_MNEMONIC3(VEX_RVM, VPMULHUW, vpmulhuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5400 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhuw);
5401 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5402}
5403
5404
5405/* Opcode VEX.F3.0F 0xe4 - invalid */
5406/* Opcode VEX.F2.0F 0xe4 - invalid */
5407
5408/* Opcode VEX.0F 0xe5 - invalid */
5409
5410
5411/** Opcode VEX.66.0F 0xe5 - vpmulhw Vx, Hx, Wx */
5412FNIEMOP_DEF(iemOp_vpmulhw_Vx_Hx_Wx)
5413{
5414 IEMOP_MNEMONIC3(VEX_RVM, VPMULHW, vpmulhw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5415 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhw);
5416 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5417}
5418
5419
5420/* Opcode VEX.F3.0F 0xe5 - invalid */
5421/* Opcode VEX.F2.0F 0xe5 - invalid */
5422
5423/* Opcode VEX.0F 0xe6 - invalid */
5424/** Opcode VEX.66.0F 0xe6 - vcvttpd2dq Vx, Wpd */
5425FNIEMOP_STUB(iemOp_vcvttpd2dq_Vx_Wpd);
5426/** Opcode VEX.F3.0F 0xe6 - vcvtdq2pd Vx, Wpd */
5427FNIEMOP_STUB(iemOp_vcvtdq2pd_Vx_Wpd);
5428/** Opcode VEX.F2.0F 0xe6 - vcvtpd2dq Vx, Wpd */
5429FNIEMOP_STUB(iemOp_vcvtpd2dq_Vx_Wpd);
5430
5431
5432/* Opcode VEX.0F 0xe7 - invalid */
5433
5434/**
5435 * @opcode 0xe7
5436 * @opcodesub !11 mr/reg
5437 * @oppfx 0x66
5438 * @opcpuid avx
5439 * @opgroup og_avx_cachect
5440 * @opxcpttype 1
5441 * @optest op1=-1 op2=2 -> op1=2
5442 * @optest op1=0 op2=-42 -> op1=-42
5443 */
5444FNIEMOP_DEF(iemOp_vmovntdq_Mx_Vx)
5445{
5446 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTDQ, vmovntdq, Mx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
5447 Assert(pVCpu->iem.s.uVexLength <= 1);
5448 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5449 if (IEM_IS_MODRM_MEM_MODE(bRm))
5450 {
5451 if (pVCpu->iem.s.uVexLength == 0)
5452 {
5453 /*
5454 * 128-bit: Memory, register.
5455 */
5456 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5457 IEM_MC_LOCAL(RTUINT128U, uSrc);
5458 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5459
5460 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5461 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5462 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5463 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
5464
5465 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
5466 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
5467
5468 IEM_MC_ADVANCE_RIP_AND_FINISH();
5469 IEM_MC_END();
5470 }
5471 else
5472 {
5473 /*
5474 * 256-bit: Memory, register.
5475 */
5476 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5477 IEM_MC_LOCAL(RTUINT256U, uSrc);
5478 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5479
5480 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5481 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5482 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5483 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
5484
5485 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
5486 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
5487
5488 IEM_MC_ADVANCE_RIP_AND_FINISH();
5489 IEM_MC_END();
5490 }
5491 }
5492 /**
5493 * @opdone
5494 * @opmnemonic udvex660fe7reg
5495 * @opcode 0xe7
5496 * @opcodesub 11 mr/reg
5497 * @oppfx 0x66
5498 * @opunused immediate
5499 * @opcpuid avx
5500 * @optest ->
5501 */
5502 else
5503 IEMOP_RAISE_INVALID_OPCODE_RET();
5504}
5505
5506/* Opcode VEX.F3.0F 0xe7 - invalid */
5507/* Opcode VEX.F2.0F 0xe7 - invalid */
5508
5509
5510/* Opcode VEX.0F 0xe8 - invalid */
5511
5512
5513/** Opcode VEX.66.0F 0xe8 - vpsubsb Vx, Hx, Wx */
5514FNIEMOP_DEF(iemOp_vpsubsb_Vx_Hx_Wx)
5515{
5516 IEMOP_MNEMONIC3(VEX_RVM, VPSUBSB, vpsubsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5517 IEMOPMEDIAOPTF3_INIT_VARS(vpsubsb);
5518 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5519}
5520
5521
5522/* Opcode VEX.F3.0F 0xe8 - invalid */
5523/* Opcode VEX.F2.0F 0xe8 - invalid */
5524
5525/* Opcode VEX.0F 0xe9 - invalid */
5526
5527
5528/** Opcode VEX.66.0F 0xe9 - vpsubsw Vx, Hx, Wx */
5529FNIEMOP_DEF(iemOp_vpsubsw_Vx_Hx_Wx)
5530{
5531 IEMOP_MNEMONIC3(VEX_RVM, VPSUBSW, vpsubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5532 IEMOPMEDIAOPTF3_INIT_VARS(vpsubsw);
5533 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5534}
5535
5536
5537/* Opcode VEX.F3.0F 0xe9 - invalid */
5538/* Opcode VEX.F2.0F 0xe9 - invalid */
5539
5540/* Opcode VEX.0F 0xea - invalid */
5541
5542
5543/** Opcode VEX.66.0F 0xea - vpminsw Vx, Hx, Wx */
5544FNIEMOP_DEF(iemOp_vpminsw_Vx_Hx_Wx)
5545{
5546 IEMOP_MNEMONIC3(VEX_RVM, VPMINSW, vpminsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5547 IEMOPMEDIAOPTF3_INIT_VARS(vpminsw);
5548 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5549}
5550
5551
5552/* Opcode VEX.F3.0F 0xea - invalid */
5553/* Opcode VEX.F2.0F 0xea - invalid */
5554
5555/* Opcode VEX.0F 0xeb - invalid */
5556
5557
5558/** Opcode VEX.66.0F 0xeb - vpor Vx, Hx, Wx */
5559FNIEMOP_DEF(iemOp_vpor_Vx_Hx_Wx)
5560{
5561 IEMOP_MNEMONIC3(VEX_RVM, VPOR, vpor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5562 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
5563 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
5564}
5565
5566
5567
5568/* Opcode VEX.F3.0F 0xeb - invalid */
5569/* Opcode VEX.F2.0F 0xeb - invalid */
5570
5571/* Opcode VEX.0F 0xec - invalid */
5572
5573
5574/** Opcode VEX.66.0F 0xec - vpaddsb Vx, Hx, Wx */
5575FNIEMOP_DEF(iemOp_vpaddsb_Vx_Hx_Wx)
5576{
5577 IEMOP_MNEMONIC3(VEX_RVM, VPADDSB, vpaddsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5578 IEMOPMEDIAOPTF3_INIT_VARS(vpaddsb);
5579 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5580}
5581
5582
5583/* Opcode VEX.F3.0F 0xec - invalid */
5584/* Opcode VEX.F2.0F 0xec - invalid */
5585
5586/* Opcode VEX.0F 0xed - invalid */
5587
5588
5589/** Opcode VEX.66.0F 0xed - vpaddsw Vx, Hx, Wx */
5590FNIEMOP_DEF(iemOp_vpaddsw_Vx_Hx_Wx)
5591{
5592 IEMOP_MNEMONIC3(VEX_RVM, VPADDSW, vpaddsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5593 IEMOPMEDIAOPTF3_INIT_VARS(vpaddsw);
5594 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5595}
5596
5597
5598/* Opcode VEX.F3.0F 0xed - invalid */
5599/* Opcode VEX.F2.0F 0xed - invalid */
5600
5601/* Opcode VEX.0F 0xee - invalid */
5602
5603
5604/** Opcode VEX.66.0F 0xee - vpmaxsw Vx, Hx, Wx */
5605FNIEMOP_DEF(iemOp_vpmaxsw_Vx_Hx_Wx)
5606{
5607 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSW, vpmaxsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5608 IEMOPMEDIAOPTF3_INIT_VARS(vpmaxsw);
5609 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5610}
5611
5612
5613/* Opcode VEX.F3.0F 0xee - invalid */
5614/* Opcode VEX.F2.0F 0xee - invalid */
5615
5616
5617/* Opcode VEX.0F 0xef - invalid */
5618
5619
5620/** Opcode VEX.66.0F 0xef - vpxor Vx, Hx, Wx */
5621FNIEMOP_DEF(iemOp_vpxor_Vx_Hx_Wx)
5622{
5623 IEMOP_MNEMONIC3(VEX_RVM, VPXOR, vpxor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5624 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
5625 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
5626}
5627
5628
5629/* Opcode VEX.F3.0F 0xef - invalid */
5630/* Opcode VEX.F2.0F 0xef - invalid */
5631
5632/* Opcode VEX.0F 0xf0 - invalid */
5633/* Opcode VEX.66.0F 0xf0 - invalid */
5634
5635
5636/** Opcode VEX.F2.0F 0xf0 - vlddqu Vx, Mx */
5637FNIEMOP_DEF(iemOp_vlddqu_Vx_Mx)
5638{
5639 IEMOP_MNEMONIC2(VEX_RM_MEM, VLDDQU, vlddqu, Vx_WO, Mx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
5640 Assert(pVCpu->iem.s.uVexLength <= 1);
5641 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5642 if (IEM_IS_MODRM_REG_MODE(bRm))
5643 {
5644 /*
5645 * Register, register - (not implemented, assuming it raises \#UD).
5646 */
5647 IEMOP_RAISE_INVALID_OPCODE_RET();
5648 }
5649 else if (pVCpu->iem.s.uVexLength == 0)
5650 {
5651 /*
5652 * Register, memory128.
5653 */
5654 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5655 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
5656 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5657
5658 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5659 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5660 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5661 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
5662
5663 IEM_MC_FETCH_MEM_U128_NO_AC(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
5664 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
5665
5666 IEM_MC_ADVANCE_RIP_AND_FINISH();
5667 IEM_MC_END();
5668 }
5669 else
5670 {
5671 /*
5672 * Register, memory256.
5673 */
5674 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5675 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
5676 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5677
5678 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5679 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5680 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5681 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
5682
5683 IEM_MC_FETCH_MEM_U256_NO_AC(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
5684 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
5685
5686 IEM_MC_ADVANCE_RIP_AND_FINISH();
5687 IEM_MC_END();
5688 }
5689}
5690
5691
5692/* Opcode VEX.0F 0xf1 - invalid */
5693/** Opcode VEX.66.0F 0xf1 - vpsllw Vx, Hx, W */
5694FNIEMOP_DEF(iemOp_vpsllw_Vx_Hx_W)
5695{
5696 IEMOP_MNEMONIC3(VEX_RVM, VPSLLW, vpsllw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5697 IEMOPMEDIAOPTF3_INIT_VARS(vpsllw);
5698 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5699}
5700
5701/* Opcode VEX.F2.0F 0xf1 - invalid */
5702
5703/* Opcode VEX.0F 0xf2 - invalid */
5704/** Opcode VEX.66.0F 0xf2 - vpslld Vx, Hx, Wx */
5705FNIEMOP_DEF(iemOp_vpslld_Vx_Hx_Wx)
5706{
5707 IEMOP_MNEMONIC3(VEX_RVM, VPSLLD, vpslld, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5708 IEMOPMEDIAOPTF3_INIT_VARS(vpslld);
5709 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5710}
5711/* Opcode VEX.F2.0F 0xf2 - invalid */
5712
5713/* Opcode VEX.0F 0xf3 - invalid */
5714/** Opcode VEX.66.0F 0xf3 - vpsllq Vx, Hx, Wx */
5715FNIEMOP_DEF(iemOp_vpsllq_Vx_Hx_Wx)
5716{
5717 IEMOP_MNEMONIC3(VEX_RVM, VPSLLQ, vpsllq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5718 IEMOPMEDIAOPTF3_INIT_VARS(vpsllq);
5719 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5720}
5721/* Opcode VEX.F2.0F 0xf3 - invalid */
5722
5723/* Opcode VEX.0F 0xf4 - invalid */
5724
5725
5726/** Opcode VEX.66.0F 0xf4 - vpmuludq Vx, Hx, W */
5727FNIEMOP_DEF(iemOp_vpmuludq_Vx_Hx_W)
5728{
5729 IEMOP_MNEMONIC3(VEX_RVM, VPMULUDQ, vpmuludq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5730 IEMOPMEDIAOPTF3_INIT_VARS(vpmuludq);
5731 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5732}
5733
5734
5735/* Opcode VEX.F2.0F 0xf4 - invalid */
5736
5737/* Opcode VEX.0F 0xf5 - invalid */
5738
5739
5740/** Opcode VEX.66.0F 0xf5 - vpmaddwd Vx, Hx, Wx */
5741FNIEMOP_DEF(iemOp_vpmaddwd_Vx_Hx_Wx)
5742{
5743 IEMOP_MNEMONIC3(VEX_RVM, VPMADDWD, vpmaddwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5744 IEMOPMEDIAOPTF3_INIT_VARS(vpmaddwd);
5745 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5746}
5747
5748
5749/* Opcode VEX.F2.0F 0xf5 - invalid */
5750
5751/* Opcode VEX.0F 0xf6 - invalid */
5752
5753
5754/** Opcode VEX.66.0F 0xf6 - vpsadbw Vx, Hx, Wx */
5755FNIEMOP_DEF(iemOp_vpsadbw_Vx_Hx_Wx)
5756{
5757 IEMOP_MNEMONIC3(VEX_RVM, VPSADBW, vpsadbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5758 IEMOPMEDIAOPTF3_INIT_VARS(vpsadbw);
5759 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5760}
5761
5762
5763/* Opcode VEX.F2.0F 0xf6 - invalid */
5764
5765/* Opcode VEX.0F 0xf7 - invalid */
5766
5767
5768/** Opcode VEX.66.0F 0xf7 - vmaskmovdqu Vdq, Udq */
5769FNIEMOP_DEF(iemOp_vmaskmovdqu_Vdq_Udq)
5770{
5771// IEMOP_MNEMONIC2(RM, VMASKMOVDQU, vmaskmovdqu, Vdq, Udq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES); /** @todo */
5772 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5773 if (IEM_IS_MODRM_REG_MODE(bRm))
5774 {
5775 /*
5776 * XMM, XMM, (implicit) [ ER]DI
5777 */
5778 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5779 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
5780 IEM_MC_LOCAL( uint64_t, u64EffAddr);
5781 IEM_MC_LOCAL( RTUINT128U, u128Mem);
5782 IEM_MC_ARG_LOCAL_REF(PRTUINT128U, pu128Mem, u128Mem, 0);
5783 IEM_MC_ARG( PCRTUINT128U, puSrc, 1);
5784 IEM_MC_ARG( PCRTUINT128U, puMsk, 2);
5785 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5786 IEM_MC_PREPARE_AVX_USAGE();
5787
5788 IEM_MC_FETCH_GREG_U64(u64EffAddr, X86_GREG_xDI);
5789 IEM_MC_FETCH_MEM_U128(u128Mem, pVCpu->iem.s.iEffSeg, u64EffAddr);
5790 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
5791 IEM_MC_REF_XREG_U128_CONST(puMsk, IEM_GET_MODRM_RM(pVCpu, bRm));
5792 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_maskmovdqu_u128, pu128Mem, puSrc, puMsk);
5793 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, u64EffAddr, u128Mem);
5794
5795 IEM_MC_ADVANCE_RIP_AND_FINISH();
5796 IEM_MC_END();
5797 }
5798 else
5799 {
5800 /* The memory, register encoding is invalid. */
5801 IEMOP_RAISE_INVALID_OPCODE_RET();
5802 }
5803}
5804
5805
5806/* Opcode VEX.F2.0F 0xf7 - invalid */
5807
5808/* Opcode VEX.0F 0xf8 - invalid */
5809
5810
5811/** Opcode VEX.66.0F 0xf8 - vpsubb Vx, Hx, W */
5812FNIEMOP_DEF(iemOp_vpsubb_Vx_Hx_Wx)
5813{
5814 IEMOP_MNEMONIC3(VEX_RVM, VPSUBB, vpsubb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5815 IEMOPMEDIAOPTF3_INIT_VARS( vpsubb);
5816 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5817}
5818
5819
5820/* Opcode VEX.F2.0F 0xf8 - invalid */
5821
5822/* Opcode VEX.0F 0xf9 - invalid */
5823
5824
5825/** Opcode VEX.66.0F 0xf9 - vpsubw Vx, Hx, Wx */
5826FNIEMOP_DEF(iemOp_vpsubw_Vx_Hx_Wx)
5827{
5828 IEMOP_MNEMONIC3(VEX_RVM, VPSUBW, vpsubw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5829 IEMOPMEDIAOPTF3_INIT_VARS( vpsubw);
5830 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5831}
5832
5833
5834/* Opcode VEX.F2.0F 0xf9 - invalid */
5835
5836/* Opcode VEX.0F 0xfa - invalid */
5837
5838
5839/** Opcode VEX.66.0F 0xfa - vpsubd Vx, Hx, Wx */
5840FNIEMOP_DEF(iemOp_vpsubd_Vx_Hx_Wx)
5841{
5842 IEMOP_MNEMONIC3(VEX_RVM, VPSUBD, vpsubd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5843 IEMOPMEDIAOPTF3_INIT_VARS( vpsubd);
5844 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5845}
5846
5847
5848/* Opcode VEX.F2.0F 0xfa - invalid */
5849
5850/* Opcode VEX.0F 0xfb - invalid */
5851
5852
5853/** Opcode VEX.66.0F 0xfb - vpsubq Vx, Hx, W */
5854FNIEMOP_DEF(iemOp_vpsubq_Vx_Hx_Wx)
5855{
5856 IEMOP_MNEMONIC3(VEX_RVM, VPSUBQ, vpsubq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5857 IEMOPMEDIAOPTF3_INIT_VARS( vpsubq);
5858 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5859}
5860
5861
5862/* Opcode VEX.F2.0F 0xfb - invalid */
5863
5864/* Opcode VEX.0F 0xfc - invalid */
5865
5866
5867/** Opcode VEX.66.0F 0xfc - vpaddb Vx, Hx, Wx */
5868FNIEMOP_DEF(iemOp_vpaddb_Vx_Hx_Wx)
5869{
5870 IEMOP_MNEMONIC3(VEX_RVM, VPADDB, vpaddb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5871 IEMOPMEDIAOPTF3_INIT_VARS( vpaddb);
5872 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5873}
5874
5875
5876/* Opcode VEX.F2.0F 0xfc - invalid */
5877
5878/* Opcode VEX.0F 0xfd - invalid */
5879
5880
5881/** Opcode VEX.66.0F 0xfd - vpaddw Vx, Hx, Wx */
5882FNIEMOP_DEF(iemOp_vpaddw_Vx_Hx_Wx)
5883{
5884 IEMOP_MNEMONIC3(VEX_RVM, VPADDW, vpaddw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5885 IEMOPMEDIAOPTF3_INIT_VARS( vpaddw);
5886 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5887}
5888
5889
5890/* Opcode VEX.F2.0F 0xfd - invalid */
5891
5892/* Opcode VEX.0F 0xfe - invalid */
5893
5894
5895/** Opcode VEX.66.0F 0xfe - vpaddd Vx, Hx, W */
5896FNIEMOP_DEF(iemOp_vpaddd_Vx_Hx_Wx)
5897{
5898 IEMOP_MNEMONIC3(VEX_RVM, VPADDD, vpaddd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5899 IEMOPMEDIAOPTF3_INIT_VARS( vpaddd);
5900 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5901}
5902
5903
5904/* Opcode VEX.F2.0F 0xfe - invalid */
5905
5906
5907/** Opcode **** 0x0f 0xff - UD0 */
5908FNIEMOP_DEF(iemOp_vud0)
5909{
5910/** @todo testcase: vud0 */
5911 IEMOP_MNEMONIC(vud0, "vud0");
5912 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
5913 {
5914 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
5915 if (IEM_IS_MODRM_MEM_MODE(bRm))
5916 IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(bRm);
5917 }
5918 IEMOP_HLP_DONE_DECODING();
5919 IEMOP_RAISE_INVALID_OPCODE_RET();
5920}
5921
5922
5923
5924/**
5925 * VEX opcode map \#1.
5926 *
5927 * @sa g_apfnTwoByteMap
5928 */
5929const PFNIEMOP g_apfnVexMap1[] =
5930{
5931 /* no prefix, 066h prefix f3h prefix, f2h prefix */
5932 /* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRM),
5933 /* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRM),
5934 /* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRM),
5935 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRM),
5936 /* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRM),
5937 /* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRM),
5938 /* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRM),
5939 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRM),
5940 /* 0x08 */ IEMOP_X4(iemOp_InvalidNeedRM),
5941 /* 0x09 */ IEMOP_X4(iemOp_InvalidNeedRM),
5942 /* 0x0a */ IEMOP_X4(iemOp_InvalidNeedRM),
5943 /* 0x0b */ IEMOP_X4(iemOp_vud2), /* ?? */
5944 /* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
5945 /* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
5946 /* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
5947 /* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
5948
5949 /* 0x10 */ iemOp_vmovups_Vps_Wps, iemOp_vmovupd_Vpd_Wpd, iemOp_vmovss_Vss_Hss_Wss, iemOp_vmovsd_Vsd_Hsd_Wsd,
5950 /* 0x11 */ iemOp_vmovups_Wps_Vps, iemOp_vmovupd_Wpd_Vpd, iemOp_vmovss_Wss_Hss_Vss, iemOp_vmovsd_Wsd_Hsd_Vsd,
5951 /* 0x12 */ iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx, iemOp_vmovddup_Vx_Wx,
5952 /* 0x13 */ iemOp_vmovlps_Mq_Vq, iemOp_vmovlpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5953 /* 0x14 */ iemOp_vunpcklps_Vx_Hx_Wx, iemOp_vunpcklpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5954 /* 0x15 */ iemOp_vunpckhps_Vx_Hx_Wx, iemOp_vunpckhpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5955 /* 0x16 */ iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq, iemOp_vmovhpd_Vdq_Hq_Mq, iemOp_vmovshdup_Vx_Wx, iemOp_InvalidNeedRM,
5956 /* 0x17 */ iemOp_vmovhps_Mq_Vq, iemOp_vmovhpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5957 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
5958 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
5959 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
5960 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
5961 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRM),
5962 /* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRM),
5963 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRM),
5964 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
5965
5966 /* 0x20 */ IEMOP_X4(iemOp_InvalidNeedRM),
5967 /* 0x21 */ IEMOP_X4(iemOp_InvalidNeedRM),
5968 /* 0x22 */ IEMOP_X4(iemOp_InvalidNeedRM),
5969 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRM),
5970 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRM),
5971 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRM),
5972 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
5973 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
5974 /* 0x28 */ iemOp_vmovaps_Vps_Wps, iemOp_vmovapd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5975 /* 0x29 */ iemOp_vmovaps_Wps_Vps, iemOp_vmovapd_Wpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5976 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtsi2ss_Vss_Hss_Ey, iemOp_vcvtsi2sd_Vsd_Hsd_Ey,
5977 /* 0x2b */ iemOp_vmovntps_Mps_Vps, iemOp_vmovntpd_Mpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5978 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvttss2si_Gy_Wss, iemOp_vcvttsd2si_Gy_Wsd,
5979 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtss2si_Gy_Wss, iemOp_vcvtsd2si_Gy_Wsd,
5980 /* 0x2e */ iemOp_vucomiss_Vss_Wss, iemOp_vucomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5981 /* 0x2f */ iemOp_vcomiss_Vss_Wss, iemOp_vcomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
5982
5983 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRM),
5984 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRM),
5985 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRM),
5986 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRM),
5987 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRM),
5988 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRM),
5989 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
5990 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRM),
5991 /* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5992 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5993 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5994 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5995 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5996 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5997 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5998 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
5999
6000 /* 0x40 */ IEMOP_X4(iemOp_InvalidNeedRM),
6001 /* 0x41 */ IEMOP_X4(iemOp_InvalidNeedRM),
6002 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
6003 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
6004 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
6005 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
6006 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
6007 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
6008 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
6009 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
6010 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
6011 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
6012 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
6013 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
6014 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
6015 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
6016
6017 /* 0x50 */ iemOp_vmovmskps_Gy_Ups, iemOp_vmovmskpd_Gy_Upd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6018 /* 0x51 */ iemOp_vsqrtps_Vps_Wps, iemOp_vsqrtpd_Vpd_Wpd, iemOp_vsqrtss_Vss_Hss_Wss, iemOp_vsqrtsd_Vsd_Hsd_Wsd,
6019 /* 0x52 */ iemOp_vrsqrtps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrsqrtss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
6020 /* 0x53 */ iemOp_vrcpps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrcpss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
6021 /* 0x54 */ iemOp_vandps_Vps_Hps_Wps, iemOp_vandpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6022 /* 0x55 */ iemOp_vandnps_Vps_Hps_Wps, iemOp_vandnpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6023 /* 0x56 */ iemOp_vorps_Vps_Hps_Wps, iemOp_vorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6024 /* 0x57 */ iemOp_vxorps_Vps_Hps_Wps, iemOp_vxorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6025 /* 0x58 */ iemOp_vaddps_Vps_Hps_Wps, iemOp_vaddpd_Vpd_Hpd_Wpd, iemOp_vaddss_Vss_Hss_Wss, iemOp_vaddsd_Vsd_Hsd_Wsd,
6026 /* 0x59 */ iemOp_vmulps_Vps_Hps_Wps, iemOp_vmulpd_Vpd_Hpd_Wpd, iemOp_vmulss_Vss_Hss_Wss, iemOp_vmulsd_Vsd_Hsd_Wsd,
6027 /* 0x5a */ iemOp_vcvtps2pd_Vpd_Wps, iemOp_vcvtpd2ps_Vps_Wpd, iemOp_vcvtss2sd_Vsd_Hx_Wss, iemOp_vcvtsd2ss_Vss_Hx_Wsd,
6028 /* 0x5b */ iemOp_vcvtdq2ps_Vps_Wdq, iemOp_vcvtps2dq_Vdq_Wps, iemOp_vcvttps2dq_Vdq_Wps, iemOp_InvalidNeedRM,
6029 /* 0x5c */ iemOp_vsubps_Vps_Hps_Wps, iemOp_vsubpd_Vpd_Hpd_Wpd, iemOp_vsubss_Vss_Hss_Wss, iemOp_vsubsd_Vsd_Hsd_Wsd,
6030 /* 0x5d */ iemOp_vminps_Vps_Hps_Wps, iemOp_vminpd_Vpd_Hpd_Wpd, iemOp_vminss_Vss_Hss_Wss, iemOp_vminsd_Vsd_Hsd_Wsd,
6031 /* 0x5e */ iemOp_vdivps_Vps_Hps_Wps, iemOp_vdivpd_Vpd_Hpd_Wpd, iemOp_vdivss_Vss_Hss_Wss, iemOp_vdivsd_Vsd_Hsd_Wsd,
6032 /* 0x5f */ iemOp_vmaxps_Vps_Hps_Wps, iemOp_vmaxpd_Vpd_Hpd_Wpd, iemOp_vmaxss_Vss_Hss_Wss, iemOp_vmaxsd_Vsd_Hsd_Wsd,
6033
6034 /* 0x60 */ iemOp_InvalidNeedRM, iemOp_vpunpcklbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6035 /* 0x61 */ iemOp_InvalidNeedRM, iemOp_vpunpcklwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6036 /* 0x62 */ iemOp_InvalidNeedRM, iemOp_vpunpckldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6037 /* 0x63 */ iemOp_InvalidNeedRM, iemOp_vpacksswb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6038 /* 0x64 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6039 /* 0x65 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6040 /* 0x66 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6041 /* 0x67 */ iemOp_InvalidNeedRM, iemOp_vpackuswb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6042 /* 0x68 */ iemOp_InvalidNeedRM, iemOp_vpunpckhbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6043 /* 0x69 */ iemOp_InvalidNeedRM, iemOp_vpunpckhwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6044 /* 0x6a */ iemOp_InvalidNeedRM, iemOp_vpunpckhdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6045 /* 0x6b */ iemOp_InvalidNeedRM, iemOp_vpackssdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6046 /* 0x6c */ iemOp_InvalidNeedRM, iemOp_vpunpcklqdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6047 /* 0x6d */ iemOp_InvalidNeedRM, iemOp_vpunpckhqdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6048 /* 0x6e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Vy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6049 /* 0x6f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Vx_Wx, iemOp_vmovdqu_Vx_Wx, iemOp_InvalidNeedRM,
6050
6051 /* 0x70 */ iemOp_InvalidNeedRM, iemOp_vpshufd_Vx_Wx_Ib, iemOp_vpshufhw_Vx_Wx_Ib, iemOp_vpshuflw_Vx_Wx_Ib,
6052 /* 0x71 */ iemOp_InvalidNeedRM, iemOp_VGrp12, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6053 /* 0x72 */ iemOp_InvalidNeedRM, iemOp_VGrp13, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6054 /* 0x73 */ iemOp_InvalidNeedRM, iemOp_VGrp14, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6055 /* 0x74 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6056 /* 0x75 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6057 /* 0x76 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6058 /* 0x77 */ iemOp_vzeroupperv__vzeroallv, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6059 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
6060 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
6061 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
6062 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
6063 /* 0x7c */ iemOp_InvalidNeedRM, iemOp_vhaddpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhaddps_Vps_Hps_Wps,
6064 /* 0x7d */ iemOp_InvalidNeedRM, iemOp_vhsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhsubps_Vps_Hps_Wps,
6065 /* 0x7e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Ey_Vy, iemOp_vmovq_Vq_Wq, iemOp_InvalidNeedRM,
6066 /* 0x7f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Wx_Vx, iemOp_vmovdqu_Wx_Vx, iemOp_InvalidNeedRM,
6067
6068 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
6069 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
6070 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
6071 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
6072 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
6073 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
6074 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
6075 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
6076 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
6077 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
6078 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
6079 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
6080 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
6081 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
6082 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
6083 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
6084
6085 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
6086 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
6087 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
6088 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
6089 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
6090 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
6091 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
6092 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
6093 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
6094 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
6095 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
6096 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
6097 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
6098 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
6099 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
6100 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
6101
6102 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
6103 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
6104 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
6105 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
6106 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
6107 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
6108 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
6109 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
6110 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
6111 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
6112 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
6113 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
6114 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
6115 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
6116 /* 0xae */ IEMOP_X4(iemOp_VGrp15),
6117 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
6118
6119 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
6120 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
6121 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
6122 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
6123 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
6124 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
6125 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
6126 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
6127 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
6128 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
6129 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
6130 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
6131 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
6132 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
6133 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
6134 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
6135
6136 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
6137 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
6138 /* 0xc2 */ iemOp_vcmpps_Vps_Hps_Wps_Ib, iemOp_vcmppd_Vpd_Hpd_Wpd_Ib, iemOp_vcmpss_Vss_Hss_Wss_Ib, iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib,
6139 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
6140 /* 0xc4 */ iemOp_InvalidNeedRM, iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
6141 /* 0xc5 */ iemOp_InvalidNeedRM, iemOp_vpextrw_Gd_Udq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
6142 /* 0xc6 */ iemOp_vshufps_Vps_Hps_Wps_Ib, iemOp_vshufpd_Vpd_Hpd_Wpd_Ib, iemOp_InvalidNeedRMImm8,iemOp_InvalidNeedRMImm8,
6143 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
6144 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
6145 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
6146 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
6147 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
6148 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
6149 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
6150 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
6151 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
6152
6153 /* 0xd0 */ iemOp_InvalidNeedRM, iemOp_vaddsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vaddsubps_Vps_Hps_Wps,
6154 /* 0xd1 */ iemOp_InvalidNeedRM, iemOp_vpsrlw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6155 /* 0xd2 */ iemOp_InvalidNeedRM, iemOp_vpsrld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6156 /* 0xd3 */ iemOp_InvalidNeedRM, iemOp_vpsrlq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6157 /* 0xd4 */ iemOp_InvalidNeedRM, iemOp_vpaddq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6158 /* 0xd5 */ iemOp_InvalidNeedRM, iemOp_vpmullw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6159 /* 0xd6 */ iemOp_InvalidNeedRM, iemOp_vmovq_Wq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6160 /* 0xd7 */ iemOp_InvalidNeedRM, iemOp_vpmovmskb_Gd_Ux, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6161 /* 0xd8 */ iemOp_InvalidNeedRM, iemOp_vpsubusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6162 /* 0xd9 */ iemOp_InvalidNeedRM, iemOp_vpsubusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6163 /* 0xda */ iemOp_InvalidNeedRM, iemOp_vpminub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6164 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vpand_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6165 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vpaddusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6166 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vpaddusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6167 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vpmaxub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6168 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vpandn_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6169
6170 /* 0xe0 */ iemOp_InvalidNeedRM, iemOp_vpavgb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6171 /* 0xe1 */ iemOp_InvalidNeedRM, iemOp_vpsraw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6172 /* 0xe2 */ iemOp_InvalidNeedRM, iemOp_vpsrad_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6173 /* 0xe3 */ iemOp_InvalidNeedRM, iemOp_vpavgw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6174 /* 0xe4 */ iemOp_InvalidNeedRM, iemOp_vpmulhuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6175 /* 0xe5 */ iemOp_InvalidNeedRM, iemOp_vpmulhw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6176 /* 0xe6 */ iemOp_InvalidNeedRM, iemOp_vcvttpd2dq_Vx_Wpd, iemOp_vcvtdq2pd_Vx_Wpd, iemOp_vcvtpd2dq_Vx_Wpd,
6177 /* 0xe7 */ iemOp_InvalidNeedRM, iemOp_vmovntdq_Mx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6178 /* 0xe8 */ iemOp_InvalidNeedRM, iemOp_vpsubsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6179 /* 0xe9 */ iemOp_InvalidNeedRM, iemOp_vpsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6180 /* 0xea */ iemOp_InvalidNeedRM, iemOp_vpminsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6181 /* 0xeb */ iemOp_InvalidNeedRM, iemOp_vpor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6182 /* 0xec */ iemOp_InvalidNeedRM, iemOp_vpaddsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6183 /* 0xed */ iemOp_InvalidNeedRM, iemOp_vpaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6184 /* 0xee */ iemOp_InvalidNeedRM, iemOp_vpmaxsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6185 /* 0xef */ iemOp_InvalidNeedRM, iemOp_vpxor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6186
6187 /* 0xf0 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vlddqu_Vx_Mx,
6188 /* 0xf1 */ iemOp_InvalidNeedRM, iemOp_vpsllw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6189 /* 0xf2 */ iemOp_InvalidNeedRM, iemOp_vpslld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6190 /* 0xf3 */ iemOp_InvalidNeedRM, iemOp_vpsllq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6191 /* 0xf4 */ iemOp_InvalidNeedRM, iemOp_vpmuludq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6192 /* 0xf5 */ iemOp_InvalidNeedRM, iemOp_vpmaddwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6193 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_vpsadbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6194 /* 0xf7 */ iemOp_InvalidNeedRM, iemOp_vmaskmovdqu_Vdq_Udq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6195 /* 0xf8 */ iemOp_InvalidNeedRM, iemOp_vpsubb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6196 /* 0xf9 */ iemOp_InvalidNeedRM, iemOp_vpsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6197 /* 0xfa */ iemOp_InvalidNeedRM, iemOp_vpsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6198 /* 0xfb */ iemOp_InvalidNeedRM, iemOp_vpsubq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6199 /* 0xfc */ iemOp_InvalidNeedRM, iemOp_vpaddb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6200 /* 0xfd */ iemOp_InvalidNeedRM, iemOp_vpaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6201 /* 0xfe */ iemOp_InvalidNeedRM, iemOp_vpaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6202 /* 0xff */ IEMOP_X4(iemOp_vud0) /* ?? */
6203};
6204AssertCompile(RT_ELEMENTS(g_apfnVexMap1) == 1024);
6205/** @} */
6206
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