VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h@ 105228

Last change on this file since 105228 was 105228, checked in by vboxsync, 9 months ago

VMM/IEM: Implement vdiv{ps,pd,ss,sd} instruction emulations, bugref:9898
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1/* $Id: IEMAllInstVexMap1.cpp.h 105228 2024-07-09 10:20:02Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstTwoByte0f.cpp.h is a legacy mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 1
33 * @{
34 */
35
36/**
37 * Common worker for AVX2 instructions on the forms:
38 * - vpxxx xmm0, xmm1, xmm2/mem128
39 * - vpxxx ymm0, ymm1, ymm2/mem256
40 *
41 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
42 */
43FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, PCIEMOPMEDIAF3, pImpl)
44{
45 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
46 if (IEM_IS_MODRM_REG_MODE(bRm))
47 {
48 /*
49 * Register, register.
50 */
51 if (pVCpu->iem.s.uVexLength)
52 {
53 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
54 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
55 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
56 IEM_MC_PREPARE_AVX_USAGE();
57
58 IEM_MC_LOCAL(X86YMMREG, uSrc1);
59 IEM_MC_ARG_LOCAL_REF(PCX86YMMREG, puSrc1, uSrc1, 1);
60 IEM_MC_FETCH_YREG_YMM(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
61 IEM_MC_LOCAL(X86YMMREG, uSrc2);
62 IEM_MC_ARG_LOCAL_REF(PCX86YMMREG, puSrc2, uSrc2, 2);
63 IEM_MC_FETCH_YREG_YMM(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
64 IEM_MC_LOCAL(X86YMMREG, uDst);
65 IEM_MC_ARG_LOCAL_REF(PX86YMMREG, puDst, uDst, 0);
66 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
67 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
68 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
69 IEM_MC_ADVANCE_RIP_AND_FINISH();
70 IEM_MC_END();
71 }
72 else
73 {
74 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
75 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
76 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
77 IEM_MC_PREPARE_AVX_USAGE();
78
79 IEM_MC_LOCAL(X86XMMREG, uDst);
80 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
81 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
82 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
83 IEM_MC_ARG(PCX86XMMREG, puSrc2, 2);
84 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
85 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
86 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
87 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
88 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
89 IEM_MC_ADVANCE_RIP_AND_FINISH();
90 IEM_MC_END();
91 }
92 }
93 else
94 {
95 /*
96 * Register, memory.
97 */
98 if (pVCpu->iem.s.uVexLength)
99 {
100 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
101 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
102 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
103 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
104 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
105 IEM_MC_PREPARE_AVX_USAGE();
106
107 IEM_MC_LOCAL(X86YMMREG, uSrc2);
108 IEM_MC_ARG_LOCAL_REF(PCX86YMMREG, puSrc2, uSrc2, 2);
109 IEM_MC_FETCH_MEM_YMM_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
110 IEM_MC_LOCAL(X86YMMREG, uSrc1);
111 IEM_MC_ARG_LOCAL_REF(PCX86YMMREG, puSrc1, uSrc1, 1);
112 IEM_MC_FETCH_YREG_YMM(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
113 IEM_MC_LOCAL(X86YMMREG, uDst);
114 IEM_MC_ARG_LOCAL_REF(PX86YMMREG, puDst, uDst, 0);
115 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
116 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
117 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
118 IEM_MC_ADVANCE_RIP_AND_FINISH();
119 IEM_MC_END();
120 }
121 else
122 {
123 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
124 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
125 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
126 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
127 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
128 IEM_MC_PREPARE_AVX_USAGE();
129
130 IEM_MC_LOCAL(X86XMMREG, uDst);
131 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
132 IEM_MC_LOCAL(X86XMMREG, uSrc2);
133 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 2);
134 IEM_MC_FETCH_MEM_XMM_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
135 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
136 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
137
138 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
139 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
140 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
141 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
142 IEM_MC_ADVANCE_RIP_AND_FINISH();
143 IEM_MC_END();
144 }
145 }
146}
147
148
149/**
150 * Common worker for scalar AVX/AVX2 instructions on the forms (addss,subss,etc.):
151 * - vxxxss xmm0, xmm1, xmm2/mem32
152 *
153 * Exceptions type 4. AVX cpuid check for 128-bit operation.
154 * Ignores VEX.L, from SDM:
155 * Software should ensure VADDSS is encoded with VEX.L=0.
156 * Encoding VADDSS with VEX.L=1 may encounter unpredictable behavior
157 * across different processor generations.
158 */
159FNIEMOP_DEF_1(iemOpCommonAvx_Vx_Hx_R32, PFNIEMAIMPLFPAVXF3U128R32, pfnU128)
160{
161 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
162 if (IEM_IS_MODRM_REG_MODE(bRm))
163 {
164 /*
165 * Register, register.
166 */
167 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
168 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
169 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
170 IEM_MC_PREPARE_AVX_USAGE();
171
172 IEM_MC_LOCAL(X86XMMREG, uDst);
173 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
174 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
175 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
176 IEM_MC_ARG(PCRTFLOAT32U, pr32Src2, 2);
177 IEM_MC_REF_XREG_R32_CONST(pr32Src2, IEM_GET_MODRM_RM(pVCpu, bRm));
178 IEM_MC_CALL_AVX_AIMPL_3(pfnU128, puDst, puSrc1, pr32Src2);
179 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
180 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
181 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
182 IEM_MC_ADVANCE_RIP_AND_FINISH();
183 IEM_MC_END();
184 }
185 else
186 {
187 /*
188 * Register, memory.
189 */
190 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
191 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
192 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
193 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
194 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
195 IEM_MC_PREPARE_AVX_USAGE();
196
197 IEM_MC_LOCAL(RTFLOAT32U, r32Src2);
198 IEM_MC_ARG_LOCAL_REF(PCRTFLOAT32U, pr32Src2, r32Src2, 2);
199 IEM_MC_FETCH_MEM_R32(r32Src2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
200 IEM_MC_LOCAL(X86XMMREG, uDst);
201 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
202 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
203 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
204 IEM_MC_CALL_AVX_AIMPL_3(pfnU128, puDst, puSrc1, pr32Src2);
205 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
206 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
207 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
208 IEM_MC_ADVANCE_RIP_AND_FINISH();
209 IEM_MC_END();
210 }
211}
212
213
214/**
215 * Common worker for scalar AVX/AVX2 instructions on the forms (addsd,subsd,etc.):
216 * - vxxxsd xmm0, xmm1, xmm2/mem64
217 *
218 * Exceptions type 4. AVX cpuid check for 128-bit operation.
219 * Ignores VEX.L, from SDM:
220 * Software should ensure VADDSD is encoded with VEX.L=0.
221 * Encoding VADDSD with VEX.L=1 may encounter unpredictable behavior
222 * across different processor generations.
223 */
224FNIEMOP_DEF_1(iemOpCommonAvx_Vx_Hx_R64, PFNIEMAIMPLFPAVXF3U128R64, pfnU128)
225{
226 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
227 if (IEM_IS_MODRM_REG_MODE(bRm))
228 {
229 /*
230 * Register, register.
231 */
232 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
233 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
234 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
235 IEM_MC_PREPARE_AVX_USAGE();
236
237 IEM_MC_LOCAL(X86XMMREG, uDst);
238 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
239 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
240 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
241 IEM_MC_ARG(PCRTFLOAT64U, pr64Src2, 2);
242 IEM_MC_REF_XREG_R64_CONST(pr64Src2, IEM_GET_MODRM_RM(pVCpu, bRm));
243 IEM_MC_CALL_AVX_AIMPL_3(pfnU128, puDst, puSrc1, pr64Src2);
244 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
245 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
246 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
247 IEM_MC_ADVANCE_RIP_AND_FINISH();
248 IEM_MC_END();
249 }
250 else
251 {
252 /*
253 * Register, memory.
254 */
255 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
256 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
257 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
258 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
259 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
260 IEM_MC_PREPARE_AVX_USAGE();
261
262 IEM_MC_LOCAL(RTFLOAT64U, r64Src2);
263 IEM_MC_ARG_LOCAL_REF(PCRTFLOAT64U, pr64Src2, r64Src2, 2);
264 IEM_MC_FETCH_MEM_R64(r64Src2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
265 IEM_MC_LOCAL(X86XMMREG, uDst);
266 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, puDst, uDst, 0);
267 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1);
268 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
269 IEM_MC_CALL_AVX_AIMPL_3(pfnU128, puDst, puSrc1, pr64Src2);
270 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
271 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
272 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
273 IEM_MC_ADVANCE_RIP_AND_FINISH();
274 IEM_MC_END();
275 }
276}
277
278
279/**
280 * Common worker for AVX2 instructions on the forms:
281 * - vpxxx xmm0, xmm1, xmm2/mem128
282 * - vpxxx ymm0, ymm1, ymm2/mem256
283 *
284 * Takes function table for function w/o implicit state parameter.
285 *
286 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
287 */
288FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, PCIEMOPMEDIAOPTF3, pImpl)
289{
290 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
291 if (IEM_IS_MODRM_REG_MODE(bRm))
292 {
293 /*
294 * Register, register.
295 */
296 if (pVCpu->iem.s.uVexLength)
297 {
298 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
299 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
300 IEM_MC_LOCAL(RTUINT256U, uDst);
301 IEM_MC_LOCAL(RTUINT256U, uSrc1);
302 IEM_MC_LOCAL(RTUINT256U, uSrc2);
303 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
304 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
305 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
306 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
307 IEM_MC_PREPARE_AVX_USAGE();
308 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
309 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
310 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
311 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
312 IEM_MC_ADVANCE_RIP_AND_FINISH();
313 IEM_MC_END();
314 }
315 else
316 {
317 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
318 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
319 IEM_MC_ARG(PRTUINT128U, puDst, 0);
320 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
321 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
322 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
323 IEM_MC_PREPARE_AVX_USAGE();
324 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
325 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
326 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
327 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
328 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
329 IEM_MC_ADVANCE_RIP_AND_FINISH();
330 IEM_MC_END();
331 }
332 }
333 else
334 {
335 /*
336 * Register, memory.
337 */
338 if (pVCpu->iem.s.uVexLength)
339 {
340 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
341 IEM_MC_LOCAL(RTUINT256U, uDst);
342 IEM_MC_LOCAL(RTUINT256U, uSrc1);
343 IEM_MC_LOCAL(RTUINT256U, uSrc2);
344 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
345 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
346 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
347 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
348
349 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
350 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
351 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
352 IEM_MC_PREPARE_AVX_USAGE();
353
354 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
355 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
356 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2);
357 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
358
359 IEM_MC_ADVANCE_RIP_AND_FINISH();
360 IEM_MC_END();
361 }
362 else
363 {
364 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
365 IEM_MC_LOCAL(RTUINT128U, uSrc2);
366 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
367 IEM_MC_ARG(PRTUINT128U, puDst, 0);
368 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
369 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
370
371 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
372 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
373 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
374 IEM_MC_PREPARE_AVX_USAGE();
375
376 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
377 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
378 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
379 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2);
380 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
381
382 IEM_MC_ADVANCE_RIP_AND_FINISH();
383 IEM_MC_END();
384 }
385 }
386}
387
388
389/**
390 * Common worker for AVX2 instructions on the forms:
391 * - vpunpckhxx xmm0, xmm1, xmm2/mem128
392 * - vpunpckhxx ymm0, ymm1, ymm2/mem256
393 *
394 * The 128-bit memory version of this instruction may elect to skip fetching the
395 * lower 64 bits of the operand. We, however, do not.
396 *
397 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
398 */
399FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, PCIEMOPMEDIAOPTF3, pImpl)
400{
401 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
402}
403
404
405/**
406 * Common worker for AVX2 instructions on the forms:
407 * - vpunpcklxx xmm0, xmm1, xmm2/mem128
408 * - vpunpcklxx ymm0, ymm1, ymm2/mem256
409 *
410 * The 128-bit memory version of this instruction may elect to skip fetching the
411 * higher 64 bits of the operand. We, however, do not.
412 *
413 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
414 */
415FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, PCIEMOPMEDIAOPTF3, pImpl)
416{
417 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, pImpl);
418}
419
420
421/**
422 * Common worker for AVX2 instructions on the forms:
423 * - vpxxx xmm0, xmm1/mem128
424 * - vpxxx ymm0, ymm1/mem256
425 *
426 * Takes function table for function w/o implicit state parameter.
427 *
428 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
429 */
430FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, PCIEMOPMEDIAOPTF2, pImpl)
431{
432 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
433 if (IEM_IS_MODRM_REG_MODE(bRm))
434 {
435 /*
436 * Register, register.
437 */
438 if (pVCpu->iem.s.uVexLength)
439 {
440 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
441 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
442 IEM_MC_LOCAL(RTUINT256U, uDst);
443 IEM_MC_LOCAL(RTUINT256U, uSrc);
444 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
445 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
446 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
447 IEM_MC_PREPARE_AVX_USAGE();
448 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
449 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
450 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
451 IEM_MC_ADVANCE_RIP_AND_FINISH();
452 IEM_MC_END();
453 }
454 else
455 {
456 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
457 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
458 IEM_MC_ARG(PRTUINT128U, puDst, 0);
459 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
460 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
461 IEM_MC_PREPARE_AVX_USAGE();
462 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
463 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
464 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
465 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
466 IEM_MC_ADVANCE_RIP_AND_FINISH();
467 IEM_MC_END();
468 }
469 }
470 else
471 {
472 /*
473 * Register, memory.
474 */
475 if (pVCpu->iem.s.uVexLength)
476 {
477 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
478 IEM_MC_LOCAL(RTUINT256U, uDst);
479 IEM_MC_LOCAL(RTUINT256U, uSrc);
480 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
481 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
482 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
483
484 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
485 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
486 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
487 IEM_MC_PREPARE_AVX_USAGE();
488
489 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
490 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc);
491 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
492
493 IEM_MC_ADVANCE_RIP_AND_FINISH();
494 IEM_MC_END();
495 }
496 else
497 {
498 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
499 IEM_MC_LOCAL(RTUINT128U, uSrc);
500 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
501 IEM_MC_ARG(PRTUINT128U, puDst, 0);
502 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
503
504 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
505 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
506 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
507 IEM_MC_PREPARE_AVX_USAGE();
508
509 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
510 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
511 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc);
512 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
513
514 IEM_MC_ADVANCE_RIP_AND_FINISH();
515 IEM_MC_END();
516 }
517 }
518}
519
520
521/* Opcode VEX.0F 0x00 - invalid */
522/* Opcode VEX.0F 0x01 - invalid */
523/* Opcode VEX.0F 0x02 - invalid */
524/* Opcode VEX.0F 0x03 - invalid */
525/* Opcode VEX.0F 0x04 - invalid */
526/* Opcode VEX.0F 0x05 - invalid */
527/* Opcode VEX.0F 0x06 - invalid */
528/* Opcode VEX.0F 0x07 - invalid */
529/* Opcode VEX.0F 0x08 - invalid */
530/* Opcode VEX.0F 0x09 - invalid */
531/* Opcode VEX.0F 0x0a - invalid */
532
533/** Opcode VEX.0F 0x0b. */
534FNIEMOP_DEF(iemOp_vud2)
535{
536 IEMOP_MNEMONIC(vud2, "vud2");
537 IEMOP_RAISE_INVALID_OPCODE_RET();
538}
539
540/* Opcode VEX.0F 0x0c - invalid */
541/* Opcode VEX.0F 0x0d - invalid */
542/* Opcode VEX.0F 0x0e - invalid */
543/* Opcode VEX.0F 0x0f - invalid */
544
545
546/**
547 * @opcode 0x10
548 * @oppfx none
549 * @opcpuid avx
550 * @opgroup og_avx_simdfp_datamove
551 * @opxcpttype 4UA
552 * @optest op1=1 op2=2 -> op1=2
553 * @optest op1=0 op2=-22 -> op1=-22
554 */
555FNIEMOP_DEF(iemOp_vmovups_Vps_Wps)
556{
557 IEMOP_MNEMONIC2(VEX_RM, VMOVUPS, vmovups, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
558 Assert(pVCpu->iem.s.uVexLength <= 1);
559 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
560 if (IEM_IS_MODRM_REG_MODE(bRm))
561 {
562 /*
563 * Register, register.
564 */
565 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
566 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
567 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
568 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
569 if (pVCpu->iem.s.uVexLength == 0)
570 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
571 IEM_GET_MODRM_RM(pVCpu, bRm));
572 else
573 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
574 IEM_GET_MODRM_RM(pVCpu, bRm));
575 IEM_MC_ADVANCE_RIP_AND_FINISH();
576 IEM_MC_END();
577 }
578 else if (pVCpu->iem.s.uVexLength == 0)
579 {
580 /*
581 * 128-bit: Register, Memory
582 */
583 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
584 IEM_MC_LOCAL(RTUINT128U, uSrc);
585 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
586
587 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
588 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
589 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
590 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
591
592 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
593 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
594
595 IEM_MC_ADVANCE_RIP_AND_FINISH();
596 IEM_MC_END();
597 }
598 else
599 {
600 /*
601 * 256-bit: Register, Memory
602 */
603 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
604 IEM_MC_LOCAL(RTUINT256U, uSrc);
605 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
606
607 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
608 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
609 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
610 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
611
612 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
613 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
614
615 IEM_MC_ADVANCE_RIP_AND_FINISH();
616 IEM_MC_END();
617 }
618}
619
620
621/**
622 * @opcode 0x10
623 * @oppfx 0x66
624 * @opcpuid avx
625 * @opgroup og_avx_simdfp_datamove
626 * @opxcpttype 4UA
627 * @optest op1=1 op2=2 -> op1=2
628 * @optest op1=0 op2=-22 -> op1=-22
629 */
630FNIEMOP_DEF(iemOp_vmovupd_Vpd_Wpd)
631{
632 IEMOP_MNEMONIC2(VEX_RM, VMOVUPD, vmovupd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
633 Assert(pVCpu->iem.s.uVexLength <= 1);
634 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
635 if (IEM_IS_MODRM_REG_MODE(bRm))
636 {
637 /*
638 * Register, register.
639 */
640 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
641 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
642 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
643 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
644 if (pVCpu->iem.s.uVexLength == 0)
645 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
646 IEM_GET_MODRM_RM(pVCpu, bRm));
647 else
648 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
649 IEM_GET_MODRM_RM(pVCpu, bRm));
650 IEM_MC_ADVANCE_RIP_AND_FINISH();
651 IEM_MC_END();
652 }
653 else if (pVCpu->iem.s.uVexLength == 0)
654 {
655 /*
656 * 128-bit: Memory, register.
657 */
658 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
659 IEM_MC_LOCAL(RTUINT128U, uSrc);
660 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
661
662 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
663 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
664 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
665 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
666
667 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
668 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
669
670 IEM_MC_ADVANCE_RIP_AND_FINISH();
671 IEM_MC_END();
672 }
673 else
674 {
675 /*
676 * 256-bit: Memory, register.
677 */
678 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
679 IEM_MC_LOCAL(RTUINT256U, uSrc);
680 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
681
682 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
683 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
684 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
685 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
686
687 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
688 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
689
690 IEM_MC_ADVANCE_RIP_AND_FINISH();
691 IEM_MC_END();
692 }
693}
694
695
696FNIEMOP_DEF(iemOp_vmovss_Vss_Hss_Wss)
697{
698 Assert(pVCpu->iem.s.uVexLength <= 1);
699 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
700 if (IEM_IS_MODRM_REG_MODE(bRm))
701 {
702 /**
703 * @opcode 0x10
704 * @oppfx 0xf3
705 * @opcodesub 11 mr/reg
706 * @opcpuid avx
707 * @opgroup og_avx_simdfp_datamerge
708 * @opxcpttype 5
709 * @optest op1=1 op2=0 op3=2 -> op1=2
710 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
711 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
712 * @optest op1=3 op2=-2 op3=0x77 -> op1=-8589934473
713 * @note HssHi refers to bits 127:32.
714 */
715 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
716 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
717 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
718 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
719 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
720 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
721 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
722 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
723 IEM_MC_ADVANCE_RIP_AND_FINISH();
724 IEM_MC_END();
725 }
726 else
727 {
728 /**
729 * @opdone
730 * @opcode 0x10
731 * @oppfx 0xf3
732 * @opcodesub !11 mr/reg
733 * @opcpuid avx
734 * @opgroup og_avx_simdfp_datamove
735 * @opxcpttype 5
736 * @opfunction iemOp_vmovss_Vss_Hss_Wss
737 * @optest op1=1 op2=2 -> op1=2
738 * @optest op1=0 op2=-22 -> op1=-22
739 */
740 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSS, vmovss, VssZx_WO, Md, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
741 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
742 IEM_MC_LOCAL(uint32_t, uSrc);
743 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
744
745 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
746 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
747 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
748 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
749
750 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
751 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
752
753 IEM_MC_ADVANCE_RIP_AND_FINISH();
754 IEM_MC_END();
755 }
756}
757
758
759FNIEMOP_DEF(iemOp_vmovsd_Vsd_Hsd_Wsd)
760{
761 Assert(pVCpu->iem.s.uVexLength <= 1);
762 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
763 if (IEM_IS_MODRM_REG_MODE(bRm))
764 {
765 /**
766 * @opcode 0x10
767 * @oppfx 0xf2
768 * @opcodesub 11 mr/reg
769 * @opcpuid avx
770 * @opgroup og_avx_simdfp_datamerge
771 * @opxcpttype 5
772 * @optest op1=1 op2=0 op3=2 -> op1=2
773 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
774 * @optest op1=3 op2=-1 op3=0x77 ->
775 * op1=0xffffffffffffffff0000000000000077
776 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x420000000000000077
777 */
778 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
779 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
780 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
781
782 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
783 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
784 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
785 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
786 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
787 IEM_MC_ADVANCE_RIP_AND_FINISH();
788 IEM_MC_END();
789 }
790 else
791 {
792 /**
793 * @opdone
794 * @opcode 0x10
795 * @oppfx 0xf2
796 * @opcodesub !11 mr/reg
797 * @opcpuid avx
798 * @opgroup og_avx_simdfp_datamove
799 * @opxcpttype 5
800 * @opfunction iemOp_vmovsd_Vsd_Hsd_Wsd
801 * @optest op1=1 op2=2 -> op1=2
802 * @optest op1=0 op2=-22 -> op1=-22
803 */
804 IEMOP_MNEMONIC2(VEX_RM_MEM, VMOVSD, vmovsd, VsdZx_WO, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
805 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
806 IEM_MC_LOCAL(uint64_t, uSrc);
807 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
808
809 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
810 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
811 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
812 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
813
814 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
815 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
816
817 IEM_MC_ADVANCE_RIP_AND_FINISH();
818 IEM_MC_END();
819 }
820}
821
822
823/**
824 * @opcode 0x11
825 * @oppfx none
826 * @opcpuid avx
827 * @opgroup og_avx_simdfp_datamove
828 * @opxcpttype 4UA
829 * @optest op1=1 op2=2 -> op1=2
830 * @optest op1=0 op2=-22 -> op1=-22
831 */
832FNIEMOP_DEF(iemOp_vmovups_Wps_Vps)
833{
834 IEMOP_MNEMONIC2(VEX_MR, VMOVUPS, vmovups, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
835 Assert(pVCpu->iem.s.uVexLength <= 1);
836 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
837 if (IEM_IS_MODRM_REG_MODE(bRm))
838 {
839 /*
840 * Register, register.
841 */
842 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
843 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
844 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
845 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
846 if (pVCpu->iem.s.uVexLength == 0)
847 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
848 IEM_GET_MODRM_REG(pVCpu, bRm));
849 else
850 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
851 IEM_GET_MODRM_REG(pVCpu, bRm));
852 IEM_MC_ADVANCE_RIP_AND_FINISH();
853 IEM_MC_END();
854 }
855 else if (pVCpu->iem.s.uVexLength == 0)
856 {
857 /*
858 * 128-bit: Memory, register.
859 */
860 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
861 IEM_MC_LOCAL(RTUINT128U, uSrc);
862 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
863
864 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
865 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
866 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
867 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
868
869 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
870 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
871
872 IEM_MC_ADVANCE_RIP_AND_FINISH();
873 IEM_MC_END();
874 }
875 else
876 {
877 /*
878 * 256-bit: Memory, register.
879 */
880 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
881 IEM_MC_LOCAL(RTUINT256U, uSrc);
882 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
883
884 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
885 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
886 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
887 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
888
889 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
890 IEM_MC_STORE_MEM_U256_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
891
892 IEM_MC_ADVANCE_RIP_AND_FINISH();
893 IEM_MC_END();
894 }
895}
896
897
898/**
899 * @opcode 0x11
900 * @oppfx 0x66
901 * @opcpuid avx
902 * @opgroup og_avx_simdfp_datamove
903 * @opxcpttype 4UA
904 * @optest op1=1 op2=2 -> op1=2
905 * @optest op1=0 op2=-22 -> op1=-22
906 */
907FNIEMOP_DEF(iemOp_vmovupd_Wpd_Vpd)
908{
909 IEMOP_MNEMONIC2(VEX_MR, VMOVUPD, vmovupd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
910 Assert(pVCpu->iem.s.uVexLength <= 1);
911 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
912 if (IEM_IS_MODRM_REG_MODE(bRm))
913 {
914 /*
915 * Register, register.
916 */
917 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
918 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
919 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
920 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
921 if (pVCpu->iem.s.uVexLength == 0)
922 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
923 IEM_GET_MODRM_REG(pVCpu, bRm));
924 else
925 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
926 IEM_GET_MODRM_REG(pVCpu, bRm));
927 IEM_MC_ADVANCE_RIP_AND_FINISH();
928 IEM_MC_END();
929 }
930 else if (pVCpu->iem.s.uVexLength == 0)
931 {
932 /*
933 * 128-bit: Memory, register.
934 */
935 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
936 IEM_MC_LOCAL(RTUINT128U, uSrc);
937 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
938
939 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
940 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
941 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
942 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
943
944 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
945 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
946
947 IEM_MC_ADVANCE_RIP_AND_FINISH();
948 IEM_MC_END();
949 }
950 else
951 {
952 /*
953 * 256-bit: Memory, register.
954 */
955 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
956 IEM_MC_LOCAL(RTUINT256U, uSrc);
957 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
958
959 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
960 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
961 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
962 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
963
964 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
965 IEM_MC_STORE_MEM_U256_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
966
967 IEM_MC_ADVANCE_RIP_AND_FINISH();
968 IEM_MC_END();
969 }
970}
971
972
973FNIEMOP_DEF(iemOp_vmovss_Wss_Hss_Vss)
974{
975 Assert(pVCpu->iem.s.uVexLength <= 1);
976 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
977 if (IEM_IS_MODRM_REG_MODE(bRm))
978 {
979 /**
980 * @opcode 0x11
981 * @oppfx 0xf3
982 * @opcodesub 11 mr/reg
983 * @opcpuid avx
984 * @opgroup og_avx_simdfp_datamerge
985 * @opxcpttype 5
986 * @optest op1=1 op2=0 op3=2 -> op1=2
987 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
988 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
989 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x4200000077
990 */
991 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
992 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
993 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
994
995 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
996 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
997 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/,
998 IEM_GET_MODRM_REG(pVCpu, bRm),
999 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
1000 IEM_MC_ADVANCE_RIP_AND_FINISH();
1001 IEM_MC_END();
1002 }
1003 else
1004 {
1005 /**
1006 * @opdone
1007 * @opcode 0x11
1008 * @oppfx 0xf3
1009 * @opcodesub !11 mr/reg
1010 * @opcpuid avx
1011 * @opgroup og_avx_simdfp_datamove
1012 * @opxcpttype 5
1013 * @opfunction iemOp_vmovss_Vss_Hss_Wss
1014 * @optest op1=1 op2=2 -> op1=2
1015 * @optest op1=0 op2=-22 -> op1=-22
1016 */
1017 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
1018 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1019 IEM_MC_LOCAL(uint32_t, uSrc);
1020 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1021
1022 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1023 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1024 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1025 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1026
1027 IEM_MC_FETCH_YREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
1028 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1029
1030 IEM_MC_ADVANCE_RIP_AND_FINISH();
1031 IEM_MC_END();
1032 }
1033}
1034
1035
1036FNIEMOP_DEF(iemOp_vmovsd_Wsd_Hsd_Vsd)
1037{
1038 Assert(pVCpu->iem.s.uVexLength <= 1);
1039 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1040 if (IEM_IS_MODRM_REG_MODE(bRm))
1041 {
1042 /**
1043 * @opcode 0x11
1044 * @oppfx 0xf2
1045 * @opcodesub 11 mr/reg
1046 * @opcpuid avx
1047 * @opgroup og_avx_simdfp_datamerge
1048 * @opxcpttype 5
1049 * @optest op1=1 op2=0 op3=2 -> op1=2
1050 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
1051 * @optest op1=3 op2=-1 op3=0x77 ->
1052 * op1=0xffffffffffffffff0000000000000077
1053 * @optest op2=0x42 op3=0x77 -> op1=0x420000000000000077
1054 */
1055 IEMOP_MNEMONIC3(VEX_MVR_REG, VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
1056 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1057 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
1058
1059 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1060 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1061 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
1062 IEM_GET_MODRM_REG(pVCpu, bRm),
1063 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
1064 IEM_MC_ADVANCE_RIP_AND_FINISH();
1065 IEM_MC_END();
1066 }
1067 else
1068 {
1069 /**
1070 * @opdone
1071 * @opcode 0x11
1072 * @oppfx 0xf2
1073 * @opcodesub !11 mr/reg
1074 * @opcpuid avx
1075 * @opgroup og_avx_simdfp_datamove
1076 * @opxcpttype 5
1077 * @opfunction iemOp_vmovsd_Wsd_Hsd_Vsd
1078 * @optest op1=1 op2=2 -> op1=2
1079 * @optest op1=0 op2=-22 -> op1=-22
1080 */
1081 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVSD, vmovsd, Mq_WO, Vsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_IGNORED);
1082 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1083 IEM_MC_LOCAL(uint64_t, uSrc);
1084 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1085
1086 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1087 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1088 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1089 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1090
1091 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
1092 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1093
1094 IEM_MC_ADVANCE_RIP_AND_FINISH();
1095 IEM_MC_END();
1096 }
1097}
1098
1099
1100FNIEMOP_DEF(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps)
1101{
1102 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1103 if (IEM_IS_MODRM_REG_MODE(bRm))
1104 {
1105 /**
1106 * @opcode 0x12
1107 * @opcodesub 11 mr/reg
1108 * @oppfx none
1109 * @opcpuid avx
1110 * @opgroup og_avx_simdfp_datamerge
1111 * @opxcpttype 7LZ
1112 * @optest op2=0x2200220122022203
1113 * op3=0x3304330533063307
1114 * -> op1=0x22002201220222033304330533063307
1115 * @optest op2=-1 op3=-42 -> op1=-42
1116 * @note op3 and op2 are only the 8-byte high XMM register halfs.
1117 */
1118 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1119 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1120 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1121
1122 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1123 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1124 IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1125 IEM_GET_MODRM_RM(pVCpu, bRm),
1126 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1127
1128 IEM_MC_ADVANCE_RIP_AND_FINISH();
1129 IEM_MC_END();
1130 }
1131 else
1132 {
1133 /**
1134 * @opdone
1135 * @opcode 0x12
1136 * @opcodesub !11 mr/reg
1137 * @oppfx none
1138 * @opcpuid avx
1139 * @opgroup og_avx_simdfp_datamove
1140 * @opxcpttype 5LZ
1141 * @opfunction iemOp_vmovlps_Vq_Hq_Mq__vmovhlps
1142 * @optest op1=1 op2=0 op3=0 -> op1=0
1143 * @optest op1=0 op2=-1 op3=-1 -> op1=-1
1144 * @optest op1=1 op2=2 op3=3 -> op1=0x20000000000000003
1145 * @optest op2=-1 op3=0x42 -> op1=0xffffffffffffffff0000000000000042
1146 */
1147 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPS, vmovlps, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1148
1149 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1150 IEM_MC_LOCAL(uint64_t, uSrc);
1151 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1152
1153 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1154 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1155 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1156 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1157
1158 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1159 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1160 uSrc,
1161 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1162
1163 IEM_MC_ADVANCE_RIP_AND_FINISH();
1164 IEM_MC_END();
1165 }
1166}
1167
1168
1169/**
1170 * @opcode 0x12
1171 * @opcodesub !11 mr/reg
1172 * @oppfx 0x66
1173 * @opcpuid avx
1174 * @opgroup og_avx_pcksclr_datamerge
1175 * @opxcpttype 5LZ
1176 * @optest op2=0 op3=2 -> op1=2
1177 * @optest op2=0x22 op3=0x33 -> op1=0x220000000000000033
1178 * @optest op2=0xfffffff0fffffff1 op3=0xeeeeeee8eeeeeee9
1179 * -> op1=0xfffffff0fffffff1eeeeeee8eeeeeee9
1180 */
1181FNIEMOP_DEF(iemOp_vmovlpd_Vq_Hq_Mq)
1182{
1183 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1184 if (IEM_IS_MODRM_MEM_MODE(bRm))
1185 {
1186 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPD, vmovlpd, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1187
1188 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1189 IEM_MC_LOCAL(uint64_t, uSrc);
1190 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1191
1192 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1193 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1194 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1195 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1196
1197 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1198 IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1199 uSrc,
1200 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1201
1202 IEM_MC_ADVANCE_RIP_AND_FINISH();
1203 IEM_MC_END();
1204 }
1205
1206 /**
1207 * @opdone
1208 * @opmnemonic udvex660f12m3
1209 * @opcode 0x12
1210 * @opcodesub 11 mr/reg
1211 * @oppfx 0x66
1212 * @opunused immediate
1213 * @opcpuid avx
1214 * @optest ->
1215 */
1216 else
1217 IEMOP_RAISE_INVALID_OPCODE_RET();
1218}
1219
1220
1221/**
1222 * @opcode 0x12
1223 * @oppfx 0xf3
1224 * @opcpuid avx
1225 * @opgroup og_avx_pcksclr_datamove
1226 * @opxcpttype 4
1227 * @optest vex.l==0 / op1=-1 op2=0xdddddddd00000002eeeeeeee00000001
1228 * -> op1=0x00000002000000020000000100000001
1229 * @optest vex.l==1 /
1230 * op2=0xbbbbbbbb00000004cccccccc00000003dddddddd00000002eeeeeeee00000001
1231 * -> op1=0x0000000400000004000000030000000300000002000000020000000100000001
1232 */
1233FNIEMOP_DEF(iemOp_vmovsldup_Vx_Wx)
1234{
1235 IEMOP_MNEMONIC2(VEX_RM, VMOVSLDUP, vmovsldup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1236 Assert(pVCpu->iem.s.uVexLength <= 1);
1237 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1238 if (IEM_IS_MODRM_REG_MODE(bRm))
1239 {
1240 /*
1241 * Register, register.
1242 */
1243 if (pVCpu->iem.s.uVexLength == 0)
1244 {
1245 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1246 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1247 IEM_MC_LOCAL(RTUINT128U, uSrc);
1248
1249 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1250 IEM_MC_PREPARE_AVX_USAGE();
1251
1252 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1253 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1254 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1255 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1256 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1257 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1258
1259 IEM_MC_ADVANCE_RIP_AND_FINISH();
1260 IEM_MC_END();
1261 }
1262 else
1263 {
1264 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1265 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1266 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1267 IEM_MC_PREPARE_AVX_USAGE();
1268
1269 IEM_MC_LOCAL(RTUINT256U, uSrc);
1270 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1271 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1272 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1273 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1274 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1275 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 4);
1276 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 4);
1277 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 6);
1278 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 6);
1279 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1280
1281 IEM_MC_ADVANCE_RIP_AND_FINISH();
1282 IEM_MC_END();
1283 }
1284 }
1285 else
1286 {
1287 /*
1288 * Register, memory.
1289 */
1290 if (pVCpu->iem.s.uVexLength == 0)
1291 {
1292 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1293 IEM_MC_LOCAL(RTUINT128U, uSrc);
1294 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1295
1296 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1297 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1298 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1299 IEM_MC_PREPARE_AVX_USAGE();
1300
1301 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1302 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1303 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1304 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1305 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1306 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1307
1308 IEM_MC_ADVANCE_RIP_AND_FINISH();
1309 IEM_MC_END();
1310 }
1311 else
1312 {
1313 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1314 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1315 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1316 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1317 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1318 IEM_MC_PREPARE_AVX_USAGE();
1319
1320 IEM_MC_LOCAL(RTUINT256U, uSrc);
1321 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1322
1323 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 0);
1324 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 0);
1325 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 2);
1326 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2);
1327 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 4);
1328 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 4);
1329 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 6);
1330 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 6);
1331 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1332
1333 IEM_MC_ADVANCE_RIP_AND_FINISH();
1334 IEM_MC_END();
1335 }
1336 }
1337}
1338
1339
1340/**
1341 * @opcode 0x12
1342 * @oppfx 0xf2
1343 * @opcpuid avx
1344 * @opgroup og_avx_pcksclr_datamove
1345 * @opxcpttype 5
1346 * @optest vex.l==0 / op2=0xddddddddeeeeeeee2222222211111111
1347 * -> op1=0x22222222111111112222222211111111
1348 * @optest vex.l==1 / op2=0xbbbbbbbbcccccccc4444444433333333ddddddddeeeeeeee2222222211111111
1349 * -> op1=0x4444444433333333444444443333333322222222111111112222222211111111
1350 */
1351FNIEMOP_DEF(iemOp_vmovddup_Vx_Wx)
1352{
1353 IEMOP_MNEMONIC2(VEX_RM, VMOVDDUP, vmovddup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1354 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1355 if (IEM_IS_MODRM_REG_MODE(bRm))
1356 {
1357 /*
1358 * Register, register.
1359 */
1360 if (pVCpu->iem.s.uVexLength == 0)
1361 {
1362 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1363 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1364 IEM_MC_LOCAL(uint64_t, uSrc);
1365
1366 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1367 IEM_MC_PREPARE_AVX_USAGE();
1368
1369 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /* a_iQword*/);
1370 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc);
1371 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc);
1372 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1373
1374 IEM_MC_ADVANCE_RIP_AND_FINISH();
1375 IEM_MC_END();
1376 }
1377 else
1378 {
1379 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1380 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1381 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1382 IEM_MC_PREPARE_AVX_USAGE();
1383
1384 IEM_MC_LOCAL(uint64_t, uSrc1);
1385 IEM_MC_LOCAL(uint64_t, uSrc2);
1386 IEM_MC_FETCH_YREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /* a_iQword*/);
1387 IEM_MC_FETCH_YREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 2 /* a_iQword*/);
1388
1389 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc1);
1390 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc1);
1391 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 2 /* a_iQword*/, uSrc2);
1392 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 3 /* a_iQword*/, uSrc2);
1393 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1394
1395 IEM_MC_ADVANCE_RIP_AND_FINISH();
1396 IEM_MC_END();
1397 }
1398 }
1399 else
1400 {
1401 /*
1402 * Register, memory.
1403 */
1404 if (pVCpu->iem.s.uVexLength == 0)
1405 {
1406 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1407 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1408 IEM_MC_LOCAL(uint64_t, uSrc);
1409
1410 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1411 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1412 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1413 IEM_MC_PREPARE_AVX_USAGE();
1414
1415 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1416 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc);
1417 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc);
1418 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1419
1420 IEM_MC_ADVANCE_RIP_AND_FINISH();
1421 IEM_MC_END();
1422 }
1423 else
1424 {
1425 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1426 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1427
1428 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1429 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1430 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1431 IEM_MC_PREPARE_AVX_USAGE();
1432
1433 IEM_MC_LOCAL(RTUINT256U, uSrc);
1434 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1435
1436 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQwDst*/, uSrc, 0 /*a_iQwSrc*/);
1437 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /*a_iQwDst*/, uSrc, 0 /*a_iQwSrc*/);
1438 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2 /*a_iQwDst*/, uSrc, 2 /*a_iQwSrc*/);
1439 IEM_MC_STORE_YREG_U64_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3 /*a_iQwDst*/, uSrc, 2 /*a_iQwSrc*/);
1440 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1441
1442 IEM_MC_ADVANCE_RIP_AND_FINISH();
1443 IEM_MC_END();
1444 }
1445 }
1446}
1447
1448
1449/**
1450 * @opcode 0x13
1451 * @opcodesub !11 mr/reg
1452 * @oppfx none
1453 * @opcpuid avx
1454 * @opgroup og_avx_simdfp_datamove
1455 * @opxcpttype 5
1456 * @optest op1=1 op2=2 -> op1=2
1457 * @optest op1=0 op2=-42 -> op1=-42
1458 */
1459FNIEMOP_DEF(iemOp_vmovlps_Mq_Vq)
1460{
1461 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1462 if (IEM_IS_MODRM_MEM_MODE(bRm))
1463 {
1464 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPS, vmovlps, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1465
1466 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1467 IEM_MC_LOCAL(uint64_t, uSrc);
1468 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1469
1470 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1471 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1472 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1473 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1474
1475 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
1476 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1477
1478 IEM_MC_ADVANCE_RIP_AND_FINISH();
1479 IEM_MC_END();
1480 }
1481
1482 /**
1483 * @opdone
1484 * @opmnemonic udvex0f13m3
1485 * @opcode 0x13
1486 * @opcodesub 11 mr/reg
1487 * @oppfx none
1488 * @opunused immediate
1489 * @opcpuid avx
1490 * @optest ->
1491 */
1492 else
1493 IEMOP_RAISE_INVALID_OPCODE_RET();
1494}
1495
1496
1497/**
1498 * @opcode 0x13
1499 * @opcodesub !11 mr/reg
1500 * @oppfx 0x66
1501 * @opcpuid avx
1502 * @opgroup og_avx_pcksclr_datamove
1503 * @opxcpttype 5
1504 * @optest op1=1 op2=2 -> op1=2
1505 * @optest op1=0 op2=-42 -> op1=-42
1506 */
1507FNIEMOP_DEF(iemOp_vmovlpd_Mq_Vq)
1508{
1509 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1510 if (IEM_IS_MODRM_MEM_MODE(bRm))
1511 {
1512 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPD, vmovlpd, Mq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1513 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1514 IEM_MC_LOCAL(uint64_t, uSrc);
1515 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1516
1517 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1518 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1519 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1520 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1521
1522 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
1523 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1524
1525 IEM_MC_ADVANCE_RIP_AND_FINISH();
1526 IEM_MC_END();
1527 }
1528
1529 /**
1530 * @opdone
1531 * @opmnemonic udvex660f13m3
1532 * @opcode 0x13
1533 * @opcodesub 11 mr/reg
1534 * @oppfx 0x66
1535 * @opunused immediate
1536 * @opcpuid avx
1537 * @optest ->
1538 */
1539 else
1540 IEMOP_RAISE_INVALID_OPCODE_RET();
1541}
1542
1543/* Opcode VEX.F3.0F 0x13 - invalid */
1544/* Opcode VEX.F2.0F 0x13 - invalid */
1545
1546/** Opcode VEX.0F 0x14 - vunpcklps Vx, Hx, Wx*/
1547FNIEMOP_DEF(iemOp_vunpcklps_Vx_Hx_Wx)
1548{
1549 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPS, vunpcklps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1550 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklps);
1551 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1552}
1553
1554
1555/** Opcode VEX.66.0F 0x14 - vunpcklpd Vx,Hx,Wx */
1556FNIEMOP_DEF(iemOp_vunpcklpd_Vx_Hx_Wx)
1557{
1558 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKLPD, vunpcklpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1559 IEMOPMEDIAOPTF3_INIT_VARS( vunpcklpd);
1560 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1561}
1562
1563
1564/* Opcode VEX.F3.0F 0x14 - invalid */
1565/* Opcode VEX.F2.0F 0x14 - invalid */
1566
1567
1568/** Opcode VEX.0F 0x15 - vunpckhps Vx, Hx, Wx */
1569FNIEMOP_DEF(iemOp_vunpckhps_Vx_Hx_Wx)
1570{
1571 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPS, vunpckhps, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1572 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhps);
1573 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1574}
1575
1576
1577/** Opcode VEX.66.0F 0x15 - vunpckhpd Vx,Hx,Wx */
1578FNIEMOP_DEF(iemOp_vunpckhpd_Vx_Hx_Wx)
1579{
1580 IEMOP_MNEMONIC3(VEX_RVM, VUNPCKHPD, vunpckhpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
1581 IEMOPMEDIAOPTF3_INIT_VARS( vunpckhpd);
1582 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1583}
1584
1585
1586/* Opcode VEX.F3.0F 0x15 - invalid */
1587/* Opcode VEX.F2.0F 0x15 - invalid */
1588
1589
1590FNIEMOP_DEF(iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq)
1591{
1592 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1593 if (IEM_IS_MODRM_REG_MODE(bRm))
1594 {
1595 /**
1596 * @opcode 0x16
1597 * @opcodesub 11 mr/reg
1598 * @oppfx none
1599 * @opcpuid avx
1600 * @opgroup og_avx_simdfp_datamerge
1601 * @opxcpttype 7LZ
1602 */
1603 IEMOP_MNEMONIC3(VEX_RVM_REG, VMOVLHPS, vmovlhps, Vq_WO, Hq, Uq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1604
1605 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1606 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1607
1608 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1609 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1610 IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1611 IEM_GET_MODRM_RM(pVCpu, bRm),
1612 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
1613
1614 IEM_MC_ADVANCE_RIP_AND_FINISH();
1615 IEM_MC_END();
1616 }
1617 else
1618 {
1619 /**
1620 * @opdone
1621 * @opcode 0x16
1622 * @opcodesub !11 mr/reg
1623 * @oppfx none
1624 * @opcpuid avx
1625 * @opgroup og_avx_simdfp_datamove
1626 * @opxcpttype 5LZ
1627 * @opfunction iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq
1628 */
1629 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPS, vmovhps, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1630
1631 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1632 IEM_MC_LOCAL(uint64_t, uSrc);
1633 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1634
1635 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1636 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1637 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1638 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1639
1640 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1641 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1642 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1643 uSrc);
1644
1645 IEM_MC_ADVANCE_RIP_AND_FINISH();
1646 IEM_MC_END();
1647 }
1648}
1649
1650
1651/**
1652 * @opcode 0x16
1653 * @opcodesub !11 mr/reg
1654 * @oppfx 0x66
1655 * @opcpuid avx
1656 * @opgroup og_avx_pcksclr_datamerge
1657 * @opxcpttype 5LZ
1658 */
1659FNIEMOP_DEF(iemOp_vmovhpd_Vdq_Hq_Mq)
1660{
1661 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1662 if (IEM_IS_MODRM_MEM_MODE(bRm))
1663 {
1664 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVHPD, vmovhpd, Vq_WO, Hq, Mq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1665
1666 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1667 IEM_MC_LOCAL(uint64_t, uSrc);
1668 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1669
1670 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1671 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1672 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1673 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1674
1675 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1676 IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1677 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/,
1678 uSrc);
1679
1680 IEM_MC_ADVANCE_RIP_AND_FINISH();
1681 IEM_MC_END();
1682 }
1683
1684 /**
1685 * @opdone
1686 * @opmnemonic udvex660f16m3
1687 * @opcode 0x12
1688 * @opcodesub 11 mr/reg
1689 * @oppfx 0x66
1690 * @opunused immediate
1691 * @opcpuid avx
1692 * @optest ->
1693 */
1694 else
1695 IEMOP_RAISE_INVALID_OPCODE_RET();
1696}
1697
1698
1699/** Opcode VEX.F3.0F 0x16 - vmovshdup Vx, Wx */
1700/**
1701 * @opcode 0x16
1702 * @oppfx 0xf3
1703 * @opcpuid avx
1704 * @opgroup og_avx_pcksclr_datamove
1705 * @opxcpttype 4
1706 */
1707FNIEMOP_DEF(iemOp_vmovshdup_Vx_Wx)
1708{
1709 IEMOP_MNEMONIC2(VEX_RM, VMOVSHDUP, vmovshdup, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1710 Assert(pVCpu->iem.s.uVexLength <= 1);
1711 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1712 if (IEM_IS_MODRM_REG_MODE(bRm))
1713 {
1714 /*
1715 * Register, register.
1716 */
1717 if (pVCpu->iem.s.uVexLength == 0)
1718 {
1719 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1720 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1721 IEM_MC_LOCAL(RTUINT128U, uSrc);
1722
1723 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1724 IEM_MC_PREPARE_AVX_USAGE();
1725
1726 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1727 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1728 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1729 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1730 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1731 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1732
1733 IEM_MC_ADVANCE_RIP_AND_FINISH();
1734 IEM_MC_END();
1735 }
1736 else
1737 {
1738 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1739 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1740 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1741 IEM_MC_PREPARE_AVX_USAGE();
1742
1743 IEM_MC_LOCAL(RTUINT256U, uSrc);
1744 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1745 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1746 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1747 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1748 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1749 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 5);
1750 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 5);
1751 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 7);
1752 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 7);
1753 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1754
1755 IEM_MC_ADVANCE_RIP_AND_FINISH();
1756 IEM_MC_END();
1757 }
1758 }
1759 else
1760 {
1761 /*
1762 * Register, memory.
1763 */
1764 if (pVCpu->iem.s.uVexLength == 0)
1765 {
1766 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1767 IEM_MC_LOCAL(RTUINT128U, uSrc);
1768 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1769
1770 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1771 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1772 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1773 IEM_MC_PREPARE_AVX_USAGE();
1774
1775 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1776 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1777 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1778 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1779 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1780 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1781
1782 IEM_MC_ADVANCE_RIP_AND_FINISH();
1783 IEM_MC_END();
1784 }
1785 else
1786 {
1787 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1788 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1789 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1790 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1791 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1792 IEM_MC_PREPARE_AVX_USAGE();
1793
1794 IEM_MC_LOCAL(RTUINT256U, uSrc);
1795 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1796
1797 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc, 1);
1798 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc, 1);
1799 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc, 3);
1800 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3);
1801 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 4, uSrc, 5);
1802 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 5, uSrc, 5);
1803 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 6, uSrc, 7);
1804 IEM_MC_STORE_YREG_U32_U256(IEM_GET_MODRM_REG(pVCpu, bRm), 7, uSrc, 7);
1805 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
1806
1807 IEM_MC_ADVANCE_RIP_AND_FINISH();
1808 IEM_MC_END();
1809 }
1810 }
1811}
1812
1813
1814/* Opcode VEX.F2.0F 0x16 - invalid */
1815
1816
1817/**
1818 * @opcode 0x17
1819 * @opcodesub !11 mr/reg
1820 * @oppfx none
1821 * @opcpuid avx
1822 * @opgroup og_avx_simdfp_datamove
1823 * @opxcpttype 5
1824 */
1825FNIEMOP_DEF(iemOp_vmovhps_Mq_Vq)
1826{
1827 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1828 if (IEM_IS_MODRM_MEM_MODE(bRm))
1829 {
1830 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPS, vmovhps, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1831
1832 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1833 IEM_MC_LOCAL(uint64_t, uSrc);
1834 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1835
1836 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1837 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1838 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1839 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1840
1841 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 1 /*a_iQWord*/);
1842 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1843
1844 IEM_MC_ADVANCE_RIP_AND_FINISH();
1845 IEM_MC_END();
1846 }
1847
1848 /**
1849 * @opdone
1850 * @opmnemonic udvex0f17m3
1851 * @opcode 0x17
1852 * @opcodesub 11 mr/reg
1853 * @oppfx none
1854 * @opunused immediate
1855 * @opcpuid avx
1856 * @optest ->
1857 */
1858 else
1859 IEMOP_RAISE_INVALID_OPCODE_RET();
1860}
1861
1862
1863/**
1864 * @opcode 0x17
1865 * @opcodesub !11 mr/reg
1866 * @oppfx 0x66
1867 * @opcpuid avx
1868 * @opgroup og_avx_pcksclr_datamove
1869 * @opxcpttype 5
1870 */
1871FNIEMOP_DEF(iemOp_vmovhpd_Mq_Vq)
1872{
1873 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1874 if (IEM_IS_MODRM_MEM_MODE(bRm))
1875 {
1876 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVHPD, vmovhpd, Mq_WO, VqHi, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1877
1878 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1879 IEM_MC_LOCAL(uint64_t, uSrc);
1880 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1881
1882 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1883 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
1884 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1885 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1886
1887 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 1 /*a_iQWord*/);
1888 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1889
1890 IEM_MC_ADVANCE_RIP_AND_FINISH();
1891 IEM_MC_END();
1892 }
1893
1894 /**
1895 * @opdone
1896 * @opmnemonic udvex660f17m3
1897 * @opcode 0x17
1898 * @opcodesub 11 mr/reg
1899 * @oppfx 0x66
1900 * @opunused immediate
1901 * @opcpuid avx
1902 * @optest ->
1903 */
1904 else
1905 IEMOP_RAISE_INVALID_OPCODE_RET();
1906}
1907
1908
1909/* Opcode VEX.F3.0F 0x17 - invalid */
1910/* Opcode VEX.F2.0F 0x17 - invalid */
1911
1912
1913/* Opcode VEX.0F 0x18 - invalid */
1914/* Opcode VEX.0F 0x19 - invalid */
1915/* Opcode VEX.0F 0x1a - invalid */
1916/* Opcode VEX.0F 0x1b - invalid */
1917/* Opcode VEX.0F 0x1c - invalid */
1918/* Opcode VEX.0F 0x1d - invalid */
1919/* Opcode VEX.0F 0x1e - invalid */
1920/* Opcode VEX.0F 0x1f - invalid */
1921
1922/* Opcode VEX.0F 0x20 - invalid */
1923/* Opcode VEX.0F 0x21 - invalid */
1924/* Opcode VEX.0F 0x22 - invalid */
1925/* Opcode VEX.0F 0x23 - invalid */
1926/* Opcode VEX.0F 0x24 - invalid */
1927/* Opcode VEX.0F 0x25 - invalid */
1928/* Opcode VEX.0F 0x26 - invalid */
1929/* Opcode VEX.0F 0x27 - invalid */
1930
1931/**
1932 * @opcode 0x28
1933 * @oppfx none
1934 * @opcpuid avx
1935 * @opgroup og_avx_pcksclr_datamove
1936 * @opxcpttype 1
1937 * @optest op1=1 op2=2 -> op1=2
1938 * @optest op1=0 op2=-42 -> op1=-42
1939 * @note Almost identical to vmovapd.
1940 */
1941FNIEMOP_DEF(iemOp_vmovaps_Vps_Wps)
1942{
1943 IEMOP_MNEMONIC2(VEX_RM, VMOVAPS, vmovaps, Vps_WO, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
1944 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1945 Assert(pVCpu->iem.s.uVexLength <= 1);
1946 if (IEM_IS_MODRM_REG_MODE(bRm))
1947 {
1948 /*
1949 * Register, register.
1950 */
1951 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1952 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1953
1954 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1955 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1956 if (pVCpu->iem.s.uVexLength == 0)
1957 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1958 IEM_GET_MODRM_RM(pVCpu, bRm));
1959 else
1960 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
1961 IEM_GET_MODRM_RM(pVCpu, bRm));
1962 IEM_MC_ADVANCE_RIP_AND_FINISH();
1963 IEM_MC_END();
1964 }
1965 else
1966 {
1967 /*
1968 * Register, memory.
1969 */
1970 if (pVCpu->iem.s.uVexLength == 0)
1971 {
1972 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1973 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1974 IEM_MC_LOCAL(RTUINT128U, uSrc);
1975
1976 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1977 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1978 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1979 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1980
1981 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1982 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1983
1984 IEM_MC_ADVANCE_RIP_AND_FINISH();
1985 IEM_MC_END();
1986 }
1987 else
1988 {
1989 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1990 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1991 IEM_MC_LOCAL(RTUINT256U, uSrc);
1992
1993 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1994 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
1995 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1996 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1997
1998 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1999 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
2000
2001 IEM_MC_ADVANCE_RIP_AND_FINISH();
2002 IEM_MC_END();
2003 }
2004 }
2005}
2006
2007
2008/**
2009 * @opcode 0x28
2010 * @oppfx 66
2011 * @opcpuid avx
2012 * @opgroup og_avx_pcksclr_datamove
2013 * @opxcpttype 1
2014 * @optest op1=1 op2=2 -> op1=2
2015 * @optest op1=0 op2=-42 -> op1=-42
2016 * @note Almost identical to vmovaps
2017 */
2018FNIEMOP_DEF(iemOp_vmovapd_Vpd_Wpd)
2019{
2020 IEMOP_MNEMONIC2(VEX_RM, VMOVAPD, vmovapd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2021 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2022 Assert(pVCpu->iem.s.uVexLength <= 1);
2023 if (IEM_IS_MODRM_REG_MODE(bRm))
2024 {
2025 /*
2026 * Register, register.
2027 */
2028 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2029 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2030
2031 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2032 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2033 if (pVCpu->iem.s.uVexLength == 0)
2034 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
2035 IEM_GET_MODRM_RM(pVCpu, bRm));
2036 else
2037 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
2038 IEM_GET_MODRM_RM(pVCpu, bRm));
2039 IEM_MC_ADVANCE_RIP_AND_FINISH();
2040 IEM_MC_END();
2041 }
2042 else
2043 {
2044 /*
2045 * Register, memory.
2046 */
2047 if (pVCpu->iem.s.uVexLength == 0)
2048 {
2049 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2050 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2051 IEM_MC_LOCAL(RTUINT128U, uSrc);
2052
2053 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2054 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2055 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2056 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2057
2058 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2059 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
2060
2061 IEM_MC_ADVANCE_RIP_AND_FINISH();
2062 IEM_MC_END();
2063 }
2064 else
2065 {
2066 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2067 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2068 IEM_MC_LOCAL(RTUINT256U, uSrc);
2069
2070 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2071 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2072 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2073 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2074
2075 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2076 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
2077
2078 IEM_MC_ADVANCE_RIP_AND_FINISH();
2079 IEM_MC_END();
2080 }
2081 }
2082}
2083
2084/**
2085 * @opmnemonic udvexf30f28
2086 * @opcode 0x28
2087 * @oppfx 0xf3
2088 * @opunused vex.modrm
2089 * @opcpuid avx
2090 * @optest ->
2091 * @opdone
2092 */
2093
2094/**
2095 * @opmnemonic udvexf20f28
2096 * @opcode 0x28
2097 * @oppfx 0xf2
2098 * @opunused vex.modrm
2099 * @opcpuid avx
2100 * @optest ->
2101 * @opdone
2102 */
2103
2104/**
2105 * @opcode 0x29
2106 * @oppfx none
2107 * @opcpuid avx
2108 * @opgroup og_avx_pcksclr_datamove
2109 * @opxcpttype 1
2110 * @optest op1=1 op2=2 -> op1=2
2111 * @optest op1=0 op2=-42 -> op1=-42
2112 * @note Almost identical to vmovapd.
2113 */
2114FNIEMOP_DEF(iemOp_vmovaps_Wps_Vps)
2115{
2116 IEMOP_MNEMONIC2(VEX_MR, VMOVAPS, vmovaps, Wps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2117 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2118 Assert(pVCpu->iem.s.uVexLength <= 1);
2119 if (IEM_IS_MODRM_REG_MODE(bRm))
2120 {
2121 /*
2122 * Register, register.
2123 */
2124 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2125 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2126
2127 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2128 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2129 if (pVCpu->iem.s.uVexLength == 0)
2130 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2131 IEM_GET_MODRM_REG(pVCpu, bRm));
2132 else
2133 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2134 IEM_GET_MODRM_REG(pVCpu, bRm));
2135 IEM_MC_ADVANCE_RIP_AND_FINISH();
2136 IEM_MC_END();
2137 }
2138 else
2139 {
2140 /*
2141 * Register, memory.
2142 */
2143 if (pVCpu->iem.s.uVexLength == 0)
2144 {
2145 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2146 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2147 IEM_MC_LOCAL(RTUINT128U, uSrc);
2148
2149 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2150 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2151 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2152 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2153
2154 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
2155 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2156
2157 IEM_MC_ADVANCE_RIP_AND_FINISH();
2158 IEM_MC_END();
2159 }
2160 else
2161 {
2162 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2163 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2164 IEM_MC_LOCAL(RTUINT256U, uSrc);
2165
2166 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2167 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2168 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2169 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2170
2171 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2172 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2173
2174 IEM_MC_ADVANCE_RIP_AND_FINISH();
2175 IEM_MC_END();
2176 }
2177 }
2178}
2179
2180/**
2181 * @opcode 0x29
2182 * @oppfx 66
2183 * @opcpuid avx
2184 * @opgroup og_avx_pcksclr_datamove
2185 * @opxcpttype 1
2186 * @optest op1=1 op2=2 -> op1=2
2187 * @optest op1=0 op2=-42 -> op1=-42
2188 * @note Almost identical to vmovaps
2189 */
2190FNIEMOP_DEF(iemOp_vmovapd_Wpd_Vpd)
2191{
2192 IEMOP_MNEMONIC2(VEX_MR, VMOVAPD, vmovapd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2193 Assert(pVCpu->iem.s.uVexLength <= 1);
2194 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2195 if (IEM_IS_MODRM_REG_MODE(bRm))
2196 {
2197 /*
2198 * Register, register.
2199 */
2200 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2201 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2202
2203 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2204 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2205 if (pVCpu->iem.s.uVexLength == 0)
2206 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2207 IEM_GET_MODRM_REG(pVCpu, bRm));
2208 else
2209 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
2210 IEM_GET_MODRM_REG(pVCpu, bRm));
2211 IEM_MC_ADVANCE_RIP_AND_FINISH();
2212 IEM_MC_END();
2213 }
2214 else
2215 {
2216 /*
2217 * Register, memory.
2218 */
2219 if (pVCpu->iem.s.uVexLength == 0)
2220 {
2221 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2222 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2223 IEM_MC_LOCAL(RTUINT128U, uSrc);
2224
2225 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2226 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2227 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2228 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2229
2230 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
2231 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2232
2233 IEM_MC_ADVANCE_RIP_AND_FINISH();
2234 IEM_MC_END();
2235 }
2236 else
2237 {
2238 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2239 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2240 IEM_MC_LOCAL(RTUINT256U, uSrc);
2241
2242 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2243 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2244 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2245 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
2246
2247 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2248 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2249
2250 IEM_MC_ADVANCE_RIP_AND_FINISH();
2251 IEM_MC_END();
2252 }
2253 }
2254}
2255
2256
2257/**
2258 * @opmnemonic udvexf30f29
2259 * @opcode 0x29
2260 * @oppfx 0xf3
2261 * @opunused vex.modrm
2262 * @opcpuid avx
2263 * @optest ->
2264 * @opdone
2265 */
2266
2267/**
2268 * @opmnemonic udvexf20f29
2269 * @opcode 0x29
2270 * @oppfx 0xf2
2271 * @opunused vex.modrm
2272 * @opcpuid avx
2273 * @optest ->
2274 * @opdone
2275 */
2276
2277
2278/** Opcode VEX.0F 0x2a - invalid */
2279/** Opcode VEX.66.0F 0x2a - invalid */
2280/** Opcode VEX.F3.0F 0x2a - vcvtsi2ss Vss, Hss, Ey */
2281FNIEMOP_STUB(iemOp_vcvtsi2ss_Vss_Hss_Ey);
2282/** Opcode VEX.F2.0F 0x2a - vcvtsi2sd Vsd, Hsd, Ey */
2283FNIEMOP_STUB(iemOp_vcvtsi2sd_Vsd_Hsd_Ey);
2284
2285
2286/**
2287 * @opcode 0x2b
2288 * @opcodesub !11 mr/reg
2289 * @oppfx none
2290 * @opcpuid avx
2291 * @opgroup og_avx_cachect
2292 * @opxcpttype 1
2293 * @optest op1=1 op2=2 -> op1=2
2294 * @optest op1=0 op2=-42 -> op1=-42
2295 * @note Identical implementation to vmovntpd
2296 */
2297FNIEMOP_DEF(iemOp_vmovntps_Mps_Vps)
2298{
2299 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPS, vmovntps, Mps_WO, Vps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2300 Assert(pVCpu->iem.s.uVexLength <= 1);
2301 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2302 if (IEM_IS_MODRM_MEM_MODE(bRm))
2303 {
2304 /*
2305 * memory, register.
2306 */
2307 if (pVCpu->iem.s.uVexLength == 0)
2308 {
2309 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2310 IEM_MC_LOCAL(RTUINT128U, uSrc);
2311 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2312
2313 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2314 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2315 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2316 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2317
2318 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2319 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2320
2321 IEM_MC_ADVANCE_RIP_AND_FINISH();
2322 IEM_MC_END();
2323 }
2324 else
2325 {
2326 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2327 IEM_MC_LOCAL(RTUINT256U, uSrc);
2328 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2329
2330 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2331 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2332 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2333 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2334
2335 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2336 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2337
2338 IEM_MC_ADVANCE_RIP_AND_FINISH();
2339 IEM_MC_END();
2340 }
2341 }
2342 /* The register, register encoding is invalid. */
2343 else
2344 IEMOP_RAISE_INVALID_OPCODE_RET();
2345}
2346
2347/**
2348 * @opcode 0x2b
2349 * @opcodesub !11 mr/reg
2350 * @oppfx 0x66
2351 * @opcpuid avx
2352 * @opgroup og_avx_cachect
2353 * @opxcpttype 1
2354 * @optest op1=1 op2=2 -> op1=2
2355 * @optest op1=0 op2=-42 -> op1=-42
2356 * @note Identical implementation to vmovntps
2357 */
2358FNIEMOP_DEF(iemOp_vmovntpd_Mpd_Vpd)
2359{
2360 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPD, vmovntpd, Mpd_WO, Vpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
2361 Assert(pVCpu->iem.s.uVexLength <= 1);
2362 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2363 if (IEM_IS_MODRM_MEM_MODE(bRm))
2364 {
2365 /*
2366 * memory, register.
2367 */
2368 if (pVCpu->iem.s.uVexLength == 0)
2369 {
2370 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2371 IEM_MC_LOCAL(RTUINT128U, uSrc);
2372 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2373
2374 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2375 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2376 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2377 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2378
2379 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2380 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2381
2382 IEM_MC_ADVANCE_RIP_AND_FINISH();
2383 IEM_MC_END();
2384 }
2385 else
2386 {
2387 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2388 IEM_MC_LOCAL(RTUINT256U, uSrc);
2389 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2390
2391 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2392 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
2393 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2394 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2395
2396 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
2397 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2398
2399 IEM_MC_ADVANCE_RIP_AND_FINISH();
2400 IEM_MC_END();
2401 }
2402 }
2403 /* The register, register encoding is invalid. */
2404 else
2405 IEMOP_RAISE_INVALID_OPCODE_RET();
2406}
2407
2408/**
2409 * @opmnemonic udvexf30f2b
2410 * @opcode 0x2b
2411 * @oppfx 0xf3
2412 * @opunused vex.modrm
2413 * @opcpuid avx
2414 * @optest ->
2415 * @opdone
2416 */
2417
2418/**
2419 * @opmnemonic udvexf20f2b
2420 * @opcode 0x2b
2421 * @oppfx 0xf2
2422 * @opunused vex.modrm
2423 * @opcpuid avx
2424 * @optest ->
2425 * @opdone
2426 */
2427
2428
2429/* Opcode VEX.0F 0x2c - invalid */
2430/* Opcode VEX.66.0F 0x2c - invalid */
2431/** Opcode VEX.F3.0F 0x2c - vcvttss2si Gy, Wss */
2432FNIEMOP_STUB(iemOp_vcvttss2si_Gy_Wss);
2433/** Opcode VEX.F2.0F 0x2c - vcvttsd2si Gy, Wsd */
2434FNIEMOP_STUB(iemOp_vcvttsd2si_Gy_Wsd);
2435
2436/* Opcode VEX.0F 0x2d - invalid */
2437/* Opcode VEX.66.0F 0x2d - invalid */
2438/** Opcode VEX.F3.0F 0x2d - vcvtss2si Gy, Wss */
2439FNIEMOP_STUB(iemOp_vcvtss2si_Gy_Wss);
2440/** Opcode VEX.F2.0F 0x2d - vcvtsd2si Gy, Wsd */
2441FNIEMOP_STUB(iemOp_vcvtsd2si_Gy_Wsd);
2442
2443
2444/**
2445 * @opcode 0x2e
2446 * @oppfx none
2447 * @opflmodify cf,pf,af,zf,sf,of
2448 * @opflclear af,sf,of
2449 */
2450FNIEMOP_DEF(iemOp_vucomiss_Vss_Wss)
2451{
2452 IEMOP_MNEMONIC2(VEX_RM, VUCOMISS, vucomiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2453 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2454 if (IEM_IS_MODRM_REG_MODE(bRm))
2455 {
2456 /*
2457 * Register, register.
2458 */
2459 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2460 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2461 IEM_MC_LOCAL(uint32_t, fEFlags);
2462 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2463 IEM_MC_ARG(RTFLOAT32U, uSrc1, 1);
2464 IEM_MC_ARG(RTFLOAT32U, uSrc2, 2);
2465 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2466 IEM_MC_PREPARE_AVX_USAGE();
2467 IEM_MC_FETCH_EFLAGS(fEFlags);
2468 IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
2469 IEM_MC_FETCH_XREG_R32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iDWord*/);
2470 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
2471 pEFlags, uSrc1, uSrc2);
2472 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2473 IEM_MC_COMMIT_EFLAGS(fEFlags);
2474
2475 IEM_MC_ADVANCE_RIP_AND_FINISH();
2476 IEM_MC_END();
2477 }
2478 else
2479 {
2480 /*
2481 * Register, memory.
2482 */
2483 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2484 IEM_MC_LOCAL(uint32_t, fEFlags);
2485 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2486 IEM_MC_ARG(RTFLOAT32U, uSrc1, 1);
2487 IEM_MC_ARG(RTFLOAT32U, uSrc2, 2);
2488 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2489
2490 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2491 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2492 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2493 IEM_MC_FETCH_MEM_R32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2494
2495 IEM_MC_PREPARE_AVX_USAGE();
2496 IEM_MC_FETCH_EFLAGS(fEFlags);
2497 IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
2498 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
2499 pEFlags, uSrc1, uSrc2);
2500 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2501 IEM_MC_COMMIT_EFLAGS(fEFlags);
2502
2503 IEM_MC_ADVANCE_RIP_AND_FINISH();
2504 IEM_MC_END();
2505 }
2506}
2507
2508
2509/**
2510 * @opcode 0x2e
2511 * @oppfx 0x66
2512 * @opflmodify cf,pf,af,zf,sf,of
2513 * @opflclear af,sf,of
2514 */
2515FNIEMOP_DEF(iemOp_vucomisd_Vsd_Wsd)
2516{
2517 IEMOP_MNEMONIC2(VEX_RM, VUCOMISD, vucomisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2518 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2519 if (IEM_IS_MODRM_REG_MODE(bRm))
2520 {
2521 /*
2522 * Register, register.
2523 */
2524 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2525 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2526 IEM_MC_LOCAL(uint32_t, fEFlags);
2527 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2528 IEM_MC_ARG(RTFLOAT64U, uSrc1, 1);
2529 IEM_MC_ARG(RTFLOAT64U, uSrc2, 2);
2530 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2531 IEM_MC_PREPARE_AVX_USAGE();
2532 IEM_MC_FETCH_EFLAGS(fEFlags);
2533 IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
2534 IEM_MC_FETCH_XREG_R64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iQWord*/);
2535 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
2536 pEFlags, uSrc1, uSrc2);
2537 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2538 IEM_MC_COMMIT_EFLAGS(fEFlags);
2539
2540 IEM_MC_ADVANCE_RIP_AND_FINISH();
2541 IEM_MC_END();
2542 }
2543 else
2544 {
2545 /*
2546 * Register, memory.
2547 */
2548 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2549 IEM_MC_LOCAL(uint32_t, fEFlags);
2550 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2551 IEM_MC_ARG(RTFLOAT64U, uSrc1, 1);
2552 IEM_MC_ARG(RTFLOAT64U, uSrc2, 2);
2553 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2554
2555 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2556 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2557 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2558 IEM_MC_FETCH_MEM_R64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2559
2560 IEM_MC_PREPARE_AVX_USAGE();
2561 IEM_MC_FETCH_EFLAGS(fEFlags);
2562 IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
2563 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
2564 pEFlags, uSrc1, uSrc2);
2565 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2566 IEM_MC_COMMIT_EFLAGS(fEFlags);
2567
2568 IEM_MC_ADVANCE_RIP_AND_FINISH();
2569 IEM_MC_END();
2570 }
2571}
2572
2573
2574/* Opcode VEX.F3.0F 0x2e - invalid */
2575/* Opcode VEX.F2.0F 0x2e - invalid */
2576
2577/**
2578 * @opcode 0x2f
2579 * @oppfx none
2580 * @opflmodify cf,pf,af,zf,sf,of
2581 * @opflclear af,sf,of
2582 */
2583FNIEMOP_DEF(iemOp_vcomiss_Vss_Wss)
2584{
2585 IEMOP_MNEMONIC2(VEX_RM, VCOMISS, vcomiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2586 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2587 if (IEM_IS_MODRM_REG_MODE(bRm))
2588 {
2589 /*
2590 * Register, register.
2591 */
2592 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2593 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2594 IEM_MC_LOCAL(uint32_t, fEFlags);
2595 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2596 IEM_MC_ARG(RTFLOAT32U, uSrc1, 1);
2597 IEM_MC_ARG(RTFLOAT32U, uSrc2, 2);
2598 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2599 IEM_MC_PREPARE_AVX_USAGE();
2600 IEM_MC_FETCH_EFLAGS(fEFlags);
2601 IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
2602 IEM_MC_FETCH_XREG_R32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iDWord*/);
2603 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
2604 pEFlags, uSrc1, uSrc2);
2605 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2606 IEM_MC_COMMIT_EFLAGS(fEFlags);
2607
2608 IEM_MC_ADVANCE_RIP_AND_FINISH();
2609 IEM_MC_END();
2610 }
2611 else
2612 {
2613 /*
2614 * Register, memory.
2615 */
2616 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2617 IEM_MC_LOCAL(uint32_t, fEFlags);
2618 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2619 IEM_MC_ARG(RTFLOAT32U, uSrc1, 1);
2620 IEM_MC_ARG(RTFLOAT32U, uSrc2, 2);
2621 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2622
2623 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2624 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2625 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2626 IEM_MC_FETCH_MEM_R32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2627
2628 IEM_MC_PREPARE_AVX_USAGE();
2629 IEM_MC_FETCH_EFLAGS(fEFlags);
2630 IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
2631 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
2632 pEFlags, uSrc1, uSrc2);
2633 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2634 IEM_MC_COMMIT_EFLAGS(fEFlags);
2635
2636 IEM_MC_ADVANCE_RIP_AND_FINISH();
2637 IEM_MC_END();
2638 }
2639}
2640
2641
2642/**
2643 * @opcode 0x2f
2644 * @oppfx 0x66
2645 * @opflmodify cf,pf,af,zf,sf,of
2646 * @opflclear af,sf,of
2647 */
2648FNIEMOP_DEF(iemOp_vcomisd_Vsd_Wsd)
2649{
2650 IEMOP_MNEMONIC2(VEX_RM, VCOMISD, vcomisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
2651 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2652 if (IEM_IS_MODRM_REG_MODE(bRm))
2653 {
2654 /*
2655 * Register, register.
2656 */
2657 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2658 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2659 IEM_MC_LOCAL(uint32_t, fEFlags);
2660 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2661 IEM_MC_ARG(RTFLOAT64U, uSrc1, 1);
2662 IEM_MC_ARG(RTFLOAT64U, uSrc2, 2);
2663 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2664 IEM_MC_PREPARE_AVX_USAGE();
2665 IEM_MC_FETCH_EFLAGS(fEFlags);
2666 IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
2667 IEM_MC_FETCH_XREG_R64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iQWord*/);
2668 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
2669 pEFlags, uSrc1, uSrc2);
2670 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2671 IEM_MC_COMMIT_EFLAGS(fEFlags);
2672
2673 IEM_MC_ADVANCE_RIP_AND_FINISH();
2674 IEM_MC_END();
2675 }
2676 else
2677 {
2678 /*
2679 * Register, memory.
2680 */
2681 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2682 IEM_MC_LOCAL(uint32_t, fEFlags);
2683 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0);
2684 IEM_MC_ARG(RTFLOAT64U, uSrc1, 1);
2685 IEM_MC_ARG(RTFLOAT64U, uSrc2, 2);
2686 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2687
2688 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2689 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
2690 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2691 IEM_MC_FETCH_MEM_R64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2692
2693 IEM_MC_PREPARE_AVX_USAGE();
2694 IEM_MC_FETCH_EFLAGS(fEFlags);
2695 IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
2696 IEM_MC_CALL_AVX_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
2697 pEFlags, uSrc1, uSrc2);
2698 IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
2699 IEM_MC_COMMIT_EFLAGS(fEFlags);
2700
2701 IEM_MC_ADVANCE_RIP_AND_FINISH();
2702 IEM_MC_END();
2703 }
2704}
2705
2706
2707/* Opcode VEX.F3.0F 0x2f - invalid */
2708/* Opcode VEX.F2.0F 0x2f - invalid */
2709
2710/* Opcode VEX.0F 0x30 - invalid */
2711/* Opcode VEX.0F 0x31 - invalid */
2712/* Opcode VEX.0F 0x32 - invalid */
2713/* Opcode VEX.0F 0x33 - invalid */
2714/* Opcode VEX.0F 0x34 - invalid */
2715/* Opcode VEX.0F 0x35 - invalid */
2716/* Opcode VEX.0F 0x36 - invalid */
2717/* Opcode VEX.0F 0x37 - invalid */
2718/* Opcode VEX.0F 0x38 - invalid */
2719/* Opcode VEX.0F 0x39 - invalid */
2720/* Opcode VEX.0F 0x3a - invalid */
2721/* Opcode VEX.0F 0x3b - invalid */
2722/* Opcode VEX.0F 0x3c - invalid */
2723/* Opcode VEX.0F 0x3d - invalid */
2724/* Opcode VEX.0F 0x3e - invalid */
2725/* Opcode VEX.0F 0x3f - invalid */
2726/* Opcode VEX.0F 0x40 - invalid */
2727/* Opcode VEX.0F 0x41 - invalid */
2728/* Opcode VEX.0F 0x42 - invalid */
2729/* Opcode VEX.0F 0x43 - invalid */
2730/* Opcode VEX.0F 0x44 - invalid */
2731/* Opcode VEX.0F 0x45 - invalid */
2732/* Opcode VEX.0F 0x46 - invalid */
2733/* Opcode VEX.0F 0x47 - invalid */
2734/* Opcode VEX.0F 0x48 - invalid */
2735/* Opcode VEX.0F 0x49 - invalid */
2736/* Opcode VEX.0F 0x4a - invalid */
2737/* Opcode VEX.0F 0x4b - invalid */
2738/* Opcode VEX.0F 0x4c - invalid */
2739/* Opcode VEX.0F 0x4d - invalid */
2740/* Opcode VEX.0F 0x4e - invalid */
2741/* Opcode VEX.0F 0x4f - invalid */
2742
2743
2744/** Opcode VEX.0F 0x50 - vmovmskps Gy, Ups */
2745FNIEMOP_DEF(iemOp_vmovmskps_Gy_Ups)
2746{
2747 IEMOP_MNEMONIC2(VEX_RM_REG, VMOVMSKPS, vmovmskps, Gd, Ux, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2748 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2749 if (IEM_IS_MODRM_REG_MODE(bRm))
2750 {
2751 /*
2752 * Register, register.
2753 */
2754 if (pVCpu->iem.s.uVexLength == 0)
2755 {
2756 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2757 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2758 IEM_MC_LOCAL(uint8_t, u8Dst);
2759 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2760 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
2761 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2762 IEM_MC_PREPARE_AVX_USAGE();
2763 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2764 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmovmskps_u128, iemAImpl_vmovmskps_u128_fallback),
2765 pu8Dst, puSrc);
2766 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2767 IEM_MC_ADVANCE_RIP_AND_FINISH();
2768 IEM_MC_END();
2769 }
2770 else
2771 {
2772 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2773 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
2774 IEM_MC_LOCAL(uint8_t, u8Dst);
2775 IEM_MC_LOCAL(RTUINT256U, uSrc);
2776 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2777 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
2778
2779 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2780 IEM_MC_PREPARE_AVX_USAGE();
2781 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2782 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vmovmskps_u256, iemAImpl_vmovmskps_u256_fallback),
2783 pu8Dst, puSrc);
2784 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2785 IEM_MC_ADVANCE_RIP_AND_FINISH();
2786 IEM_MC_END();
2787 }
2788 }
2789 /* No memory operand. */
2790 else
2791 IEMOP_RAISE_INVALID_OPCODE_RET();
2792}
2793
2794
2795/** Opcode VEX.66.0F 0x50 - vmovmskpd Gy,Upd */
2796FNIEMOP_DEF(iemOp_vmovmskpd_Gy_Upd)
2797{
2798 IEMOP_MNEMONIC2(VEX_RM_REG, VMOVMSKPD, vmovmskpd, Gd, Ux, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2799 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2800 if (IEM_IS_MODRM_REG_MODE(bRm))
2801 {
2802 /*
2803 * Register, register.
2804 */
2805 if (pVCpu->iem.s.uVexLength == 0)
2806 {
2807 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2808 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
2809 IEM_MC_LOCAL(uint8_t, u8Dst);
2810 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2811 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
2812 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2813 IEM_MC_PREPARE_AVX_USAGE();
2814 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2815 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmovmskpd_u128, iemAImpl_vmovmskpd_u128_fallback),
2816 pu8Dst, puSrc);
2817 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2818 IEM_MC_ADVANCE_RIP_AND_FINISH();
2819 IEM_MC_END();
2820 }
2821 else
2822 {
2823 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2824 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
2825 IEM_MC_LOCAL(uint8_t, u8Dst);
2826 IEM_MC_LOCAL(RTUINT256U, uSrc);
2827 IEM_MC_ARG_LOCAL_REF(uint8_t *, pu8Dst, u8Dst, 0);
2828 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
2829
2830 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2831 IEM_MC_PREPARE_AVX_USAGE();
2832 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
2833 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vmovmskpd_u256, iemAImpl_vmovmskpd_u256_fallback),
2834 pu8Dst, puSrc);
2835 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst);
2836 IEM_MC_ADVANCE_RIP_AND_FINISH();
2837 IEM_MC_END();
2838 }
2839 }
2840 /* No memory operand. */
2841 else
2842 IEMOP_RAISE_INVALID_OPCODE_RET();
2843}
2844
2845
2846/* Opcode VEX.F3.0F 0x50 - invalid */
2847/* Opcode VEX.F2.0F 0x50 - invalid */
2848
2849/** Opcode VEX.0F 0x51 - vsqrtps Vps, Wps */
2850FNIEMOP_STUB(iemOp_vsqrtps_Vps_Wps);
2851/** Opcode VEX.66.0F 0x51 - vsqrtpd Vpd, Wpd */
2852FNIEMOP_STUB(iemOp_vsqrtpd_Vpd_Wpd);
2853/** Opcode VEX.F3.0F 0x51 - vsqrtss Vss, Hss, Wss */
2854FNIEMOP_STUB(iemOp_vsqrtss_Vss_Hss_Wss);
2855/** Opcode VEX.F2.0F 0x51 - vsqrtsd Vsd, Hsd, Wsd */
2856FNIEMOP_STUB(iemOp_vsqrtsd_Vsd_Hsd_Wsd);
2857
2858/** Opcode VEX.0F 0x52 - vrsqrtps Vps, Wps */
2859FNIEMOP_STUB(iemOp_vrsqrtps_Vps_Wps);
2860/* Opcode VEX.66.0F 0x52 - invalid */
2861/** Opcode VEX.F3.0F 0x52 - vrsqrtss Vss, Hss, Wss */
2862FNIEMOP_STUB(iemOp_vrsqrtss_Vss_Hss_Wss);
2863/* Opcode VEX.F2.0F 0x52 - invalid */
2864
2865/** Opcode VEX.0F 0x53 - vrcpps Vps, Wps */
2866FNIEMOP_STUB(iemOp_vrcpps_Vps_Wps);
2867/* Opcode VEX.66.0F 0x53 - invalid */
2868/** Opcode VEX.F3.0F 0x53 - vrcpss Vss, Hss, Wss */
2869FNIEMOP_STUB(iemOp_vrcpss_Vss_Hss_Wss);
2870/* Opcode VEX.F2.0F 0x53 - invalid */
2871
2872
2873/** Opcode VEX.0F 0x54 - vandps Vps, Hps, Wps */
2874FNIEMOP_DEF(iemOp_vandps_Vps_Hps_Wps)
2875{
2876 IEMOP_MNEMONIC3(VEX_RVM, VANDPS, vandps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2877 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2878 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2879}
2880
2881
2882/** Opcode VEX.66.0F 0x54 - vandpd Vpd, Hpd, Wpd */
2883FNIEMOP_DEF(iemOp_vandpd_Vpd_Hpd_Wpd)
2884{
2885 IEMOP_MNEMONIC3(VEX_RVM, VANDPD, vandpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2886 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2887 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
2888}
2889
2890
2891/* Opcode VEX.F3.0F 0x54 - invalid */
2892/* Opcode VEX.F2.0F 0x54 - invalid */
2893
2894
2895/** Opcode VEX.0F 0x55 - vandnps Vps, Hps, Wps */
2896FNIEMOP_DEF(iemOp_vandnps_Vps_Hps_Wps)
2897{
2898 IEMOP_MNEMONIC3(VEX_RVM, VANDNPS, vandnps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2899 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2900 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2901}
2902
2903
2904/** Opcode VEX.66.0F 0x55 - vandnpd Vpd, Hpd, Wpd */
2905FNIEMOP_DEF(iemOp_vandnpd_Vpd_Hpd_Wpd)
2906{
2907 IEMOP_MNEMONIC3(VEX_RVM, VANDNPD, vandnpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2908 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2909 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
2910}
2911
2912
2913/* Opcode VEX.F3.0F 0x55 - invalid */
2914/* Opcode VEX.F2.0F 0x55 - invalid */
2915
2916/** Opcode VEX.0F 0x56 - vorps Vps, Hps, Wps */
2917FNIEMOP_DEF(iemOp_vorps_Vps_Hps_Wps)
2918{
2919 IEMOP_MNEMONIC3(VEX_RVM, VORPS, vorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2920 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2921 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2922}
2923
2924
2925/** Opcode VEX.66.0F 0x56 - vorpd Vpd, Hpd, Wpd */
2926FNIEMOP_DEF(iemOp_vorpd_Vpd_Hpd_Wpd)
2927{
2928 IEMOP_MNEMONIC3(VEX_RVM, VORPD, vorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2929 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2930 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
2931}
2932
2933
2934/* Opcode VEX.F3.0F 0x56 - invalid */
2935/* Opcode VEX.F2.0F 0x56 - invalid */
2936
2937
2938/** Opcode VEX.0F 0x57 - vxorps Vps, Hps, Wps */
2939FNIEMOP_DEF(iemOp_vxorps_Vps_Hps_Wps)
2940{
2941 IEMOP_MNEMONIC3(VEX_RVM, VXORPS, vxorps, Vps, Hps, Wps, DISOPTYPE_HARMLESS, 0);
2942 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2943 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2944}
2945
2946
2947/** Opcode VEX.66.0F 0x57 - vxorpd Vpd, Hpd, Wpd */
2948FNIEMOP_DEF(iemOp_vxorpd_Vpd_Hpd_Wpd)
2949{
2950 IEMOP_MNEMONIC3(VEX_RVM, VXORPD, vxorpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS, 0);
2951 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
2952 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
2953}
2954
2955
2956/* Opcode VEX.F3.0F 0x57 - invalid */
2957/* Opcode VEX.F2.0F 0x57 - invalid */
2958
2959
2960/** Opcode VEX.0F 0x58 - vaddps Vps, Hps, Wps */
2961FNIEMOP_DEF(iemOp_vaddps_Vps_Hps_Wps)
2962{
2963 IEMOP_MNEMONIC3(VEX_RVM, VADDPS, vaddps, Vps, Hps, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2964 IEMOPMEDIAF3_INIT_VARS( vaddps);
2965 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
2966}
2967
2968
2969/** Opcode VEX.66.0F 0x58 - vaddpd Vpd, Hpd, Wpd */
2970FNIEMOP_DEF(iemOp_vaddpd_Vpd_Hpd_Wpd)
2971{
2972 IEMOP_MNEMONIC3(VEX_RVM, VADDPD, vaddpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2973 IEMOPMEDIAF3_INIT_VARS( vaddpd);
2974 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
2975}
2976
2977
2978/** Opcode VEX.F3.0F 0x58 - vaddss Vss, Hss, Wss */
2979FNIEMOP_DEF(iemOp_vaddss_Vss_Hss_Wss)
2980{
2981 IEMOP_MNEMONIC3(VEX_RVM, VADDSS, vaddss, Vps, Hps, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2982 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R32,
2983 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback));
2984}
2985
2986
2987/** Opcode VEX.F2.0F 0x58 - vaddsd Vsd, Hsd, Wsd */
2988FNIEMOP_DEF(iemOp_vaddsd_Vsd_Hsd_Wsd)
2989{
2990 IEMOP_MNEMONIC3(VEX_RVM, VADDSD, vaddsd, Vpd, Hpd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
2991 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R64,
2992 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback));
2993}
2994
2995
2996/** Opcode VEX.0F 0x59 - vmulps Vps, Hps, Wps */
2997FNIEMOP_DEF(iemOp_vmulps_Vps_Hps_Wps)
2998{
2999 IEMOP_MNEMONIC3(VEX_RVM, VMULPS, vmulps, Vps, Hps, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3000 IEMOPMEDIAF3_INIT_VARS( vmulps);
3001 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
3002}
3003
3004
3005/** Opcode VEX.66.0F 0x59 - vmulpd Vpd, Hpd, Wpd */
3006FNIEMOP_DEF(iemOp_vmulpd_Vpd_Hpd_Wpd)
3007{
3008 IEMOP_MNEMONIC3(VEX_RVM, VMULPD, vmulpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3009 IEMOPMEDIAF3_INIT_VARS( vmulpd);
3010 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
3011}
3012
3013
3014/** Opcode VEX.F3.0F 0x59 - vmulss Vss, Hss, Wss */
3015FNIEMOP_DEF(iemOp_vmulss_Vss_Hss_Wss)
3016{
3017 IEMOP_MNEMONIC3(VEX_RVM, VMULSS, vmulss, Vps, Hps, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3018 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R32,
3019 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback));
3020}
3021
3022
3023/** Opcode VEX.F2.0F 0x59 - vmulsd Vsd, Hsd, Wsd */
3024FNIEMOP_DEF(iemOp_vmulsd_Vsd_Hsd_Wsd)
3025{
3026 IEMOP_MNEMONIC3(VEX_RVM, VMULSD, vmulsd, Vpd, Hpd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3027 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R64,
3028 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback));
3029}
3030
3031
3032/** Opcode VEX.0F 0x5a - vcvtps2pd Vpd, Wps */
3033FNIEMOP_STUB(iemOp_vcvtps2pd_Vpd_Wps);
3034/** Opcode VEX.66.0F 0x5a - vcvtpd2ps Vps, Wpd */
3035FNIEMOP_STUB(iemOp_vcvtpd2ps_Vps_Wpd);
3036/** Opcode VEX.F3.0F 0x5a - vcvtss2sd Vsd, Hx, Wss */
3037FNIEMOP_STUB(iemOp_vcvtss2sd_Vsd_Hx_Wss);
3038/** Opcode VEX.F2.0F 0x5a - vcvtsd2ss Vss, Hx, Wsd */
3039FNIEMOP_STUB(iemOp_vcvtsd2ss_Vss_Hx_Wsd);
3040
3041/** Opcode VEX.0F 0x5b - vcvtdq2ps Vps, Wdq */
3042FNIEMOP_STUB(iemOp_vcvtdq2ps_Vps_Wdq);
3043/** Opcode VEX.66.0F 0x5b - vcvtps2dq Vdq, Wps */
3044FNIEMOP_STUB(iemOp_vcvtps2dq_Vdq_Wps);
3045/** Opcode VEX.F3.0F 0x5b - vcvttps2dq Vdq, Wps */
3046FNIEMOP_STUB(iemOp_vcvttps2dq_Vdq_Wps);
3047/* Opcode VEX.F2.0F 0x5b - invalid */
3048
3049
3050/** Opcode VEX.0F 0x5c - vsubps Vps, Hps, Wps */
3051FNIEMOP_DEF(iemOp_vsubps_Vps_Hps_Wps)
3052{
3053 IEMOP_MNEMONIC3(VEX_RVM, VSUBPS, vsubps, Vps, Hps, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3054 IEMOPMEDIAF3_INIT_VARS( vsubps);
3055 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
3056}
3057
3058
3059/** Opcode VEX.66.0F 0x5c - vsubpd Vpd, Hpd, Wpd */
3060FNIEMOP_DEF(iemOp_vsubpd_Vpd_Hpd_Wpd)
3061{
3062 IEMOP_MNEMONIC3(VEX_RVM, VSUBPD, vsubpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3063 IEMOPMEDIAF3_INIT_VARS( vsubpd);
3064 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
3065}
3066
3067
3068/** Opcode VEX.F3.0F 0x5c - vsubss Vss, Hss, Wss */
3069FNIEMOP_DEF(iemOp_vsubss_Vss_Hss_Wss)
3070{
3071 IEMOP_MNEMONIC3(VEX_RVM, VSUBSS, vsubss, Vps, Hps, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3072 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R32,
3073 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback));
3074}
3075
3076
3077/** Opcode VEX.F2.0F 0x5c - vsubsd Vsd, Hsd, Wsd */
3078FNIEMOP_DEF(iemOp_vsubsd_Vsd_Hsd_Wsd)
3079{
3080 IEMOP_MNEMONIC3(VEX_RVM, VSUBSD, vsubsd, Vpd, Hpd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3081 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R64,
3082 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback));
3083}
3084
3085
3086/** Opcode VEX.0F 0x5d - vminps Vps, Hps, Wps */
3087FNIEMOP_DEF(iemOp_vminps_Vps_Hps_Wps)
3088{
3089 IEMOP_MNEMONIC3(VEX_RVM, VMINPS, vminps, Vps, Hps, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3090 IEMOPMEDIAF3_INIT_VARS( vminps);
3091 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
3092}
3093
3094
3095/** Opcode VEX.66.0F 0x5d - vminpd Vpd, Hpd, Wpd */
3096FNIEMOP_DEF(iemOp_vminpd_Vpd_Hpd_Wpd)
3097{
3098 IEMOP_MNEMONIC3(VEX_RVM, VMINPD, vminpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3099 IEMOPMEDIAF3_INIT_VARS( vminpd);
3100 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
3101}
3102
3103
3104/** Opcode VEX.F3.0F 0x5d - vminss Vss, Hss, Wss */
3105FNIEMOP_DEF(iemOp_vminss_Vss_Hss_Wss)
3106{
3107 IEMOP_MNEMONIC3(VEX_RVM, VMINSS, vminss, Vps, Hps, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3108 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R32,
3109 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback));
3110}
3111
3112
3113/** Opcode VEX.F2.0F 0x5d - vminsd Vsd, Hsd, Wsd */
3114FNIEMOP_DEF(iemOp_vminsd_Vsd_Hsd_Wsd)
3115{
3116 IEMOP_MNEMONIC3(VEX_RVM, VMINSD, vminsd, Vpd, Hpd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3117 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R64,
3118 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback));
3119}
3120
3121
3122/** Opcode VEX.0F 0x5e - vdivps Vps, Hps, Wps */
3123FNIEMOP_DEF(iemOp_vdivps_Vps_Hps_Wps)
3124{
3125 IEMOP_MNEMONIC3(VEX_RVM, VDIVPS, vdivps, Vps, Hps, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3126 IEMOPMEDIAF3_INIT_VARS( vdivps);
3127 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
3128}
3129
3130
3131/** Opcode VEX.66.0F 0x5e - vdivpd Vpd, Hpd, Wpd */
3132FNIEMOP_DEF(iemOp_vdivpd_Vpd_Hpd_Wpd)
3133{
3134 IEMOP_MNEMONIC3(VEX_RVM, VDIVPD, vdivpd, Vpd, Hpd, Wpd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3135 IEMOPMEDIAF3_INIT_VARS( vdivpd);
3136 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
3137}
3138
3139
3140/** Opcode VEX.F3.0F 0x5e - vdivss Vss, Hss, Wss */
3141FNIEMOP_DEF(iemOp_vdivss_Vss_Hss_Wss)
3142{
3143 IEMOP_MNEMONIC3(VEX_RVM, VDIVSS, vdivss, Vps, Hps, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3144 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R32,
3145 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback));
3146}
3147
3148
3149/** Opcode VEX.F2.0F 0x5e - vdivsd Vsd, Hsd, Wsd */
3150FNIEMOP_DEF(iemOp_vdivsd_Vsd_Hsd_Wsd)
3151{
3152 IEMOP_MNEMONIC3(VEX_RVM, VDIVSD, vdivsd, Vpd, Hpd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3153 return FNIEMOP_CALL_1(iemOpCommonAvx_Vx_Hx_R64,
3154 IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback));
3155}
3156
3157
3158/** Opcode VEX.0F 0x5f - vmaxps Vps, Hps, Wps */
3159FNIEMOP_STUB(iemOp_vmaxps_Vps_Hps_Wps);
3160/** Opcode VEX.66.0F 0x5f - vmaxpd Vpd, Hpd, Wpd */
3161FNIEMOP_STUB(iemOp_vmaxpd_Vpd_Hpd_Wpd);
3162/** Opcode VEX.F3.0F 0x5f - vmaxss Vss, Hss, Wss */
3163FNIEMOP_STUB(iemOp_vmaxss_Vss_Hss_Wss);
3164/** Opcode VEX.F2.0F 0x5f - vmaxsd Vsd, Hsd, Wsd */
3165FNIEMOP_STUB(iemOp_vmaxsd_Vsd_Hsd_Wsd);
3166
3167
3168/* Opcode VEX.0F 0x60 - invalid */
3169
3170
3171/** Opcode VEX.66.0F 0x60 - vpunpcklbw Vx, Hx, Wx */
3172FNIEMOP_DEF(iemOp_vpunpcklbw_Vx_Hx_Wx)
3173{
3174 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLBW, vpunpcklbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3175 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklbw);
3176 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3177}
3178
3179
3180/* Opcode VEX.F3.0F 0x60 - invalid */
3181
3182
3183/* Opcode VEX.0F 0x61 - invalid */
3184
3185
3186/** Opcode VEX.66.0F 0x61 - vpunpcklwd Vx, Hx, Wx */
3187FNIEMOP_DEF(iemOp_vpunpcklwd_Vx_Hx_Wx)
3188{
3189 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLWD, vpunpcklwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3190 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklwd);
3191 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3192}
3193
3194
3195/* Opcode VEX.F3.0F 0x61 - invalid */
3196
3197
3198/* Opcode VEX.0F 0x62 - invalid */
3199
3200/** Opcode VEX.66.0F 0x62 - vpunpckldq Vx, Hx, Wx */
3201FNIEMOP_DEF(iemOp_vpunpckldq_Vx_Hx_Wx)
3202{
3203 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLDQ, vpunpckldq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3204 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckldq);
3205 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3206}
3207
3208
3209/* Opcode VEX.F3.0F 0x62 - invalid */
3210
3211
3212
3213/* Opcode VEX.0F 0x63 - invalid */
3214
3215
3216/** Opcode VEX.66.0F 0x63 - vpacksswb Vx, Hx, Wx */
3217FNIEMOP_DEF(iemOp_vpacksswb_Vx_Hx_Wx)
3218{
3219 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSWB, vpacksswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3220 IEMOPMEDIAOPTF3_INIT_VARS( vpacksswb);
3221 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3222}
3223
3224
3225/* Opcode VEX.F3.0F 0x63 - invalid */
3226
3227/* Opcode VEX.0F 0x64 - invalid */
3228
3229
3230/** Opcode VEX.66.0F 0x64 - vpcmpgtb Vx, Hx, Wx */
3231FNIEMOP_DEF(iemOp_vpcmpgtb_Vx_Hx_Wx)
3232{
3233 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTB, vpcmpgtb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3234 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpgtb);
3235 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3236}
3237
3238
3239/* Opcode VEX.F3.0F 0x64 - invalid */
3240
3241/* Opcode VEX.0F 0x65 - invalid */
3242
3243
3244/** Opcode VEX.66.0F 0x65 - vpcmpgtw Vx, Hx, Wx */
3245FNIEMOP_DEF(iemOp_vpcmpgtw_Vx_Hx_Wx)
3246{
3247 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTW, vpcmpgtw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3248 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpgtw);
3249 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3250}
3251
3252
3253/* Opcode VEX.F3.0F 0x65 - invalid */
3254
3255/* Opcode VEX.0F 0x66 - invalid */
3256
3257
3258/** Opcode VEX.66.0F 0x66 - vpcmpgtd Vx, Hx, Wx */
3259FNIEMOP_DEF(iemOp_vpcmpgtd_Vx_Hx_Wx)
3260{
3261 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTD, vpcmpgtd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
3262 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpgtd);
3263 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3264}
3265
3266
3267/* Opcode VEX.F3.0F 0x66 - invalid */
3268
3269/* Opcode VEX.0F 0x67 - invalid */
3270
3271
3272/** Opcode VEX.66.0F 0x67 - vpackuswb Vx, Hx, W */
3273FNIEMOP_DEF(iemOp_vpackuswb_Vx_Hx_W)
3274{
3275 IEMOP_MNEMONIC3(VEX_RVM, VPACKUSWB, vpackuswb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3276 IEMOPMEDIAOPTF3_INIT_VARS( vpackuswb);
3277 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3278}
3279
3280
3281/* Opcode VEX.F3.0F 0x67 - invalid */
3282
3283
3284///**
3285// * Common worker for SSE2 instructions on the form:
3286// * pxxxx xmm1, xmm2/mem128
3287// *
3288// * The 2nd operand is the second half of a register, which in the memory case
3289// * means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
3290// * where it may read the full 128 bits or only the upper 64 bits.
3291// *
3292// * Exceptions type 4.
3293// */
3294//FNIEMOP_DEF_1(iemOpCommonSse_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
3295//{
3296// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3297// if (IEM_IS_MODRM_REG_MODE(bRm))
3298// {
3299// /*
3300// * Register, register.
3301// */
3302// IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3303// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
3304// IEM_MC_ARG(PRTUINT128U, pDst, 0);
3305// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
3306// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
3307// IEM_MC_PREPARE_SSE_USAGE();
3308// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3309// IEM_MC_REF_XREG_U128_CONST(pSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3310// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3311// IEM_MC_ADVANCE_RIP_AND_FINISH();
3312// IEM_MC_END();
3313// }
3314// else
3315// {
3316// /*
3317// * Register, memory.
3318// */
3319// IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3320// IEM_MC_ARG(PRTUINT128U, pDst, 0);
3321// IEM_MC_LOCAL(RTUINT128U, uSrc);
3322// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
3323// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3324//
3325// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3326// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
3327// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
3328// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */
3329//
3330// IEM_MC_PREPARE_SSE_USAGE();
3331// IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3332// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3333//
3334// IEM_MC_ADVANCE_RIP_AND_FINISH();
3335// IEM_MC_END();
3336// }
3337// return VINF_SUCCESS;
3338//}
3339
3340
3341/* Opcode VEX.0F 0x68 - invalid */
3342
3343/** Opcode VEX.66.0F 0x68 - vpunpckhbw Vx, Hx, Wx */
3344FNIEMOP_DEF(iemOp_vpunpckhbw_Vx_Hx_Wx)
3345{
3346 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHBW, vpunpckhbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3347 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhbw);
3348 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3349}
3350
3351
3352/* Opcode VEX.F3.0F 0x68 - invalid */
3353
3354
3355/* Opcode VEX.0F 0x69 - invalid */
3356
3357
3358/** Opcode VEX.66.0F 0x69 - vpunpckhwd Vx, Hx, Wx */
3359FNIEMOP_DEF(iemOp_vpunpckhwd_Vx_Hx_Wx)
3360{
3361 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHWD, vpunpckhwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3362 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhwd);
3363 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3364}
3365
3366
3367/* Opcode VEX.F3.0F 0x69 - invalid */
3368
3369
3370/* Opcode VEX.0F 0x6a - invalid */
3371
3372
3373/** Opcode VEX.66.0F 0x6a - vpunpckhdq Vx, Hx, W */
3374FNIEMOP_DEF(iemOp_vpunpckhdq_Vx_Hx_W)
3375{
3376 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHDQ, vpunpckhdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3377 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhdq);
3378 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3379}
3380
3381
3382/* Opcode VEX.F3.0F 0x6a - invalid */
3383
3384
3385/* Opcode VEX.0F 0x6b - invalid */
3386
3387
3388/** Opcode VEX.66.0F 0x6b - vpackssdw Vx, Hx, Wx */
3389FNIEMOP_DEF(iemOp_vpackssdw_Vx_Hx_Wx)
3390{
3391 IEMOP_MNEMONIC3(VEX_RVM, VPACKSSDW, vpackssdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3392 IEMOPMEDIAOPTF3_INIT_VARS( vpackssdw);
3393 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3394}
3395
3396
3397/* Opcode VEX.F3.0F 0x6b - invalid */
3398
3399
3400/* Opcode VEX.0F 0x6c - invalid */
3401
3402
3403/** Opcode VEX.66.0F 0x6c - vpunpcklqdq Vx, Hx, Wx */
3404FNIEMOP_DEF(iemOp_vpunpcklqdq_Vx_Hx_Wx)
3405{
3406 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKLQDQ, vpunpcklqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3407 IEMOPMEDIAOPTF3_INIT_VARS( vpunpcklqdq);
3408 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_LowSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3409}
3410
3411
3412/* Opcode VEX.F3.0F 0x6c - invalid */
3413/* Opcode VEX.F2.0F 0x6c - invalid */
3414
3415
3416/* Opcode VEX.0F 0x6d - invalid */
3417
3418
3419/** Opcode VEX.66.0F 0x6d - vpunpckhqdq Vx, Hx, W */
3420FNIEMOP_DEF(iemOp_vpunpckhqdq_Vx_Hx_W)
3421{
3422 IEMOP_MNEMONIC3(VEX_RVM, VPUNPCKHQDQ, vpunpckhqdq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3423 IEMOPMEDIAOPTF3_INIT_VARS( vpunpckhqdq);
3424 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_HighSrc, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
3425}
3426
3427
3428/* Opcode VEX.F3.0F 0x6d - invalid */
3429
3430
3431/* Opcode VEX.0F 0x6e - invalid */
3432
3433FNIEMOP_DEF(iemOp_vmovd_q_Vy_Ey)
3434{
3435 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3436 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3437 {
3438 /**
3439 * @opcode 0x6e
3440 * @opcodesub rex.w=1
3441 * @oppfx 0x66
3442 * @opcpuid avx
3443 * @opgroup og_avx_simdint_datamov
3444 * @opxcpttype 5
3445 * @optest 64-bit / op1=1 op2=2 -> op1=2
3446 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
3447 */
3448 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Eq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3449 if (IEM_IS_MODRM_REG_MODE(bRm))
3450 {
3451 /* XMM, greg64 */
3452 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3453 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3454 IEM_MC_LOCAL(uint64_t, u64Tmp);
3455
3456 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3457 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3458
3459 IEM_MC_FETCH_GREG_U64(u64Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
3460 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
3461
3462 IEM_MC_ADVANCE_RIP_AND_FINISH();
3463 IEM_MC_END();
3464 }
3465 else
3466 {
3467 /* XMM, [mem64] */
3468 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3469 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3470 IEM_MC_LOCAL(uint64_t, u64Tmp);
3471
3472 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3473 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3474 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3475 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3476
3477 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3478 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
3479
3480 IEM_MC_ADVANCE_RIP_AND_FINISH();
3481 IEM_MC_END();
3482 }
3483 }
3484 else
3485 {
3486 /**
3487 * @opdone
3488 * @opcode 0x6e
3489 * @opcodesub rex.w=0
3490 * @oppfx 0x66
3491 * @opcpuid avx
3492 * @opgroup og_avx_simdint_datamov
3493 * @opxcpttype 5
3494 * @opfunction iemOp_vmovd_q_Vy_Ey
3495 * @optest op1=1 op2=2 -> op1=2
3496 * @optest op1=0 op2=-42 -> op1=-42
3497 */
3498 IEMOP_MNEMONIC2(VEX_RM, VMOVD, vmovd, Vd_WO, Ed, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
3499 if (IEM_IS_MODRM_REG_MODE(bRm))
3500 {
3501 /* XMM, greg32 */
3502 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3503 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3504 IEM_MC_LOCAL(uint32_t, u32Tmp);
3505
3506 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3507 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3508
3509 IEM_MC_FETCH_GREG_U32(u32Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
3510 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
3511
3512 IEM_MC_ADVANCE_RIP_AND_FINISH();
3513 IEM_MC_END();
3514 }
3515 else
3516 {
3517 /* XMM, [mem32] */
3518 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3519 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3520 IEM_MC_LOCAL(uint32_t, u32Tmp);
3521
3522 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3523 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
3524 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3525 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3526
3527 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3528 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
3529
3530 IEM_MC_ADVANCE_RIP_AND_FINISH();
3531 IEM_MC_END();
3532 }
3533 }
3534}
3535
3536
3537/* Opcode VEX.F3.0F 0x6e - invalid */
3538
3539
3540/* Opcode VEX.0F 0x6f - invalid */
3541
3542/**
3543 * @opcode 0x6f
3544 * @oppfx 0x66
3545 * @opcpuid avx
3546 * @opgroup og_avx_simdint_datamove
3547 * @opxcpttype 1
3548 * @optest op1=1 op2=2 -> op1=2
3549 * @optest op1=0 op2=-42 -> op1=-42
3550 */
3551FNIEMOP_DEF(iemOp_vmovdqa_Vx_Wx)
3552{
3553 IEMOP_MNEMONIC2(VEX_RM, VMOVDQA, vmovdqa, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3554 Assert(pVCpu->iem.s.uVexLength <= 1);
3555 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3556 if (IEM_IS_MODRM_REG_MODE(bRm))
3557 {
3558 /*
3559 * Register, register.
3560 */
3561 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3562 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3563
3564 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3565 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3566 if (pVCpu->iem.s.uVexLength == 0)
3567 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3568 IEM_GET_MODRM_RM(pVCpu, bRm));
3569 else
3570 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3571 IEM_GET_MODRM_RM(pVCpu, bRm));
3572 IEM_MC_ADVANCE_RIP_AND_FINISH();
3573 IEM_MC_END();
3574 }
3575 else if (pVCpu->iem.s.uVexLength == 0)
3576 {
3577 /*
3578 * Register, memory128.
3579 */
3580 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3581 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3582 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3583
3584 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3585 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3586 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3587 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3588
3589 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3590 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
3591
3592 IEM_MC_ADVANCE_RIP_AND_FINISH();
3593 IEM_MC_END();
3594 }
3595 else
3596 {
3597 /*
3598 * Register, memory256.
3599 */
3600 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3601 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3602 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3603
3604 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3605 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3606 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3607 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3608
3609 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3610 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
3611
3612 IEM_MC_ADVANCE_RIP_AND_FINISH();
3613 IEM_MC_END();
3614 }
3615}
3616
3617/**
3618 * @opcode 0x6f
3619 * @oppfx 0xf3
3620 * @opcpuid avx
3621 * @opgroup og_avx_simdint_datamove
3622 * @opxcpttype 4UA
3623 * @optest op1=1 op2=2 -> op1=2
3624 * @optest op1=0 op2=-42 -> op1=-42
3625 */
3626FNIEMOP_DEF(iemOp_vmovdqu_Vx_Wx)
3627{
3628 IEMOP_MNEMONIC2(VEX_RM, VMOVDQU, vmovdqu, Vx_WO, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
3629 Assert(pVCpu->iem.s.uVexLength <= 1);
3630 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3631 if (IEM_IS_MODRM_REG_MODE(bRm))
3632 {
3633 /*
3634 * Register, register.
3635 */
3636 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3637 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3638
3639 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3640 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3641 if (pVCpu->iem.s.uVexLength == 0)
3642 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3643 IEM_GET_MODRM_RM(pVCpu, bRm));
3644 else
3645 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
3646 IEM_GET_MODRM_RM(pVCpu, bRm));
3647 IEM_MC_ADVANCE_RIP_AND_FINISH();
3648 IEM_MC_END();
3649 }
3650 else if (pVCpu->iem.s.uVexLength == 0)
3651 {
3652 /*
3653 * Register, memory128.
3654 */
3655 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3656 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3657 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3658
3659 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3660 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3661 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3662 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3663
3664 IEM_MC_FETCH_MEM_U128_NO_AC(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3665 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
3666
3667 IEM_MC_ADVANCE_RIP_AND_FINISH();
3668 IEM_MC_END();
3669 }
3670 else
3671 {
3672 /*
3673 * Register, memory256.
3674 */
3675 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3676 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
3677 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3678
3679 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3680 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3681 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3682 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
3683
3684 IEM_MC_FETCH_MEM_U256_NO_AC(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3685 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
3686
3687 IEM_MC_ADVANCE_RIP_AND_FINISH();
3688 IEM_MC_END();
3689 }
3690}
3691
3692
3693/* Opcode VEX.0F 0x70 - invalid */
3694
3695
3696/**
3697 * Common worker for AVX/AVX2 instructions on the forms:
3698 * - vpxxx xmm0, xmm2/mem128, imm8
3699 * - vpxxx ymm0, ymm2/mem256, imm8
3700 *
3701 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
3702 */
3703FNIEMOP_DEF_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, PFNIEMAIMPLMEDIAPSHUFU128, pfnU128, PFNIEMAIMPLMEDIAPSHUFU256, pfnU256)
3704{
3705 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3706 if (IEM_IS_MODRM_REG_MODE(bRm))
3707 {
3708 /*
3709 * Register, register.
3710 */
3711 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3712 if (pVCpu->iem.s.uVexLength)
3713 {
3714 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3715 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3716 IEM_MC_LOCAL(RTUINT256U, uDst);
3717 IEM_MC_LOCAL(RTUINT256U, uSrc);
3718 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3719 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3720 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3721 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3722 IEM_MC_PREPARE_AVX_USAGE();
3723 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3724 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg);
3725 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3726 IEM_MC_ADVANCE_RIP_AND_FINISH();
3727 IEM_MC_END();
3728 }
3729 else
3730 {
3731 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3732 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3733 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3734 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
3735 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3736 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3737 IEM_MC_PREPARE_AVX_USAGE();
3738 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3739 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3740 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
3741 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3742 IEM_MC_ADVANCE_RIP_AND_FINISH();
3743 IEM_MC_END();
3744 }
3745 }
3746 else
3747 {
3748 /*
3749 * Register, memory.
3750 */
3751 if (pVCpu->iem.s.uVexLength)
3752 {
3753 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3754 IEM_MC_LOCAL(RTUINT256U, uDst);
3755 IEM_MC_LOCAL(RTUINT256U, uSrc);
3756 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3757 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3758 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3759
3760 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
3761 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3762 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
3763 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3764 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3765 IEM_MC_PREPARE_AVX_USAGE();
3766
3767 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3768 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg);
3769 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
3770
3771 IEM_MC_ADVANCE_RIP_AND_FINISH();
3772 IEM_MC_END();
3773 }
3774 else
3775 {
3776 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3777 IEM_MC_LOCAL(RTUINT128U, uSrc);
3778 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3779 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3780 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
3781
3782 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
3783 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3784 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
3785 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3786 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3787 IEM_MC_PREPARE_AVX_USAGE();
3788
3789 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3790 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
3791 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
3792 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
3793
3794 IEM_MC_ADVANCE_RIP_AND_FINISH();
3795 IEM_MC_END();
3796 }
3797 }
3798}
3799
3800
3801/** Opcode VEX.66.0F 0x70 - vpshufd Vx, Wx, Ib */
3802FNIEMOP_DEF(iemOp_vpshufd_Vx_Wx_Ib)
3803{
3804 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFD, vpshufd, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3805 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufd_u128,
3806 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufd_u256, iemAImpl_vpshufd_u256_fallback));
3807
3808}
3809
3810
3811/** Opcode VEX.F3.0F 0x70 - vpshufhw Vx, Wx, Ib */
3812FNIEMOP_DEF(iemOp_vpshufhw_Vx_Wx_Ib)
3813{
3814 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFHW, vpshufhw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3815 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshufhw_u128,
3816 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshufhw_u256, iemAImpl_vpshufhw_u256_fallback));
3817
3818}
3819
3820
3821/** Opcode VEX.F2.0F 0x70 - vpshuflw Vx, Wx, Ib */
3822FNIEMOP_DEF(iemOp_vpshuflw_Vx_Wx_Ib)
3823{
3824 IEMOP_MNEMONIC3(VEX_RMI, VPSHUFLW, vpshuflw, Vx, Wx, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3825 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_vpshufXX_Vx_Wx_Ib, iemAImpl_pshuflw_u128,
3826 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpshuflw_u256, iemAImpl_vpshuflw_u256_fallback));
3827}
3828
3829
3830/**
3831 * Common worker(s) for AVX/AVX2 instructions on the forms:
3832 * - vpxxx xmm0, xmm2, imm8
3833 * - vpxxx ymm0, ymm2, imm8
3834 *
3835 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
3836 */
3837FNIEMOP_DEF_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, uint8_t, bRm, PFNIEMAIMPLMEDIAPSHUFU128, pfnU128)
3838{
3839 if (IEM_IS_MODRM_REG_MODE(bRm))
3840 {
3841 /*
3842 * Register, register.
3843 */
3844 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3845 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3846 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
3847 IEM_MC_ARG(PRTUINT128U, puDst, 0);
3848 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
3849 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3850 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3851 IEM_MC_PREPARE_AVX_USAGE();
3852 IEM_MC_REF_XREG_U128(puDst, IEM_GET_EFFECTIVE_VVVV(pVCpu));
3853 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3854 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
3855 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_EFFECTIVE_VVVV(pVCpu));
3856 IEM_MC_ADVANCE_RIP_AND_FINISH();
3857 IEM_MC_END();
3858 }
3859 /* No memory operand. */
3860 else
3861 IEMOP_RAISE_INVALID_OPCODE_RET();
3862}
3863
3864FNIEMOP_DEF_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, uint8_t, bRm, PFNIEMAIMPLMEDIAPSHUFU256, pfnU256)
3865{
3866 if (IEM_IS_MODRM_REG_MODE(bRm))
3867 {
3868 /*
3869 * Register, register.
3870 */
3871 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
3872 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
3873 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
3874 IEM_MC_LOCAL(RTUINT256U, uDst);
3875 IEM_MC_LOCAL(RTUINT256U, uSrc);
3876 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
3877 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
3878 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
3879 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
3880 IEM_MC_PREPARE_AVX_USAGE();
3881 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
3882 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg);
3883 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_EFFECTIVE_VVVV(pVCpu), uDst);
3884 IEM_MC_ADVANCE_RIP_AND_FINISH();
3885 IEM_MC_END();
3886 }
3887 /* No memory operand. */
3888 else
3889 IEMOP_RAISE_INVALID_OPCODE_RET();
3890}
3891
3892
3893/* Opcode VEX.0F 0x71 11/2 - invalid. */
3894/** Opcode VEX.66.0F 0x71 11/2. */
3895FNIEMOP_DEF_1(iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, uint8_t, bRm)
3896{
3897 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLW, vpsrlw, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3898 if (pVCpu->iem.s.uVexLength)
3899 {
3900 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3901 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback));
3902 }
3903 else
3904 {
3905 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3906 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback));
3907 }
3908}
3909
3910
3911/* Opcode VEX.0F 0x71 11/4 - invalid */
3912/** Opcode VEX.66.0F 0x71 11/4. */
3913FNIEMOP_DEF_1(iemOp_VGrp12_vpsraw_Hx_Ux_Ib, uint8_t, bRm)
3914{
3915 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRAW, vpsraw, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3916 if (pVCpu->iem.s.uVexLength)
3917 {
3918 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3919 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback));
3920 }
3921 else
3922 {
3923 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3924 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback));
3925 }
3926}
3927
3928/* Opcode VEX.0F 0x71 11/6 - invalid */
3929
3930/** Opcode VEX.66.0F 0x71 11/6. */
3931FNIEMOP_DEF_1(iemOp_VGrp12_vpsllw_Hx_Ux_Ib, uint8_t, bRm)
3932{
3933 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSLLW, vpsllw, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3934 if (pVCpu->iem.s.uVexLength)
3935 {
3936 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3937 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback));
3938 }
3939 else
3940 {
3941 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3942 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback));
3943 }
3944}
3945
3946
3947/**
3948 * VEX Group 12 jump table for register variant.
3949 */
3950IEM_STATIC const PFNIEMOPRM g_apfnVexGroup12RegReg[] =
3951{
3952 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3953 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3954 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3955 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3956 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsraw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3957 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3958 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsllw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3959 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3960};
3961AssertCompile(RT_ELEMENTS(g_apfnVexGroup12RegReg) == 8*4);
3962
3963
3964/** Opcode VEX.0F 0x71. */
3965FNIEMOP_DEF(iemOp_VGrp12)
3966{
3967 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3968 if (IEM_IS_MODRM_REG_MODE(bRm))
3969 /* register, register */
3970 return FNIEMOP_CALL_1(g_apfnVexGroup12RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
3971 + pVCpu->iem.s.idxPrefix], bRm);
3972 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3973}
3974
3975
3976/* Opcode VEX.0F 0x72 11/2 - invalid. */
3977/** Opcode VEX.66.0F 0x72 11/2. */
3978FNIEMOP_DEF_1(iemOp_VGrp13_vpsrld_Hx_Ux_Ib, uint8_t, bRm)
3979{
3980 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLD, vpsrld, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3981 if (pVCpu->iem.s.uVexLength)
3982 {
3983 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
3984 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback));
3985 }
3986 else
3987 {
3988 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
3989 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback));
3990 }
3991}
3992
3993
3994/* Opcode VEX.0F 0x72 11/4 - invalid. */
3995/** Opcode VEX.66.0F 0x72 11/4. */
3996FNIEMOP_DEF_1(iemOp_VGrp13_vpsrad_Hx_Ux_Ib, uint8_t, bRm)
3997{
3998 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRAD, vpsrad, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
3999 if (pVCpu->iem.s.uVexLength)
4000 {
4001 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
4002 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback));
4003 }
4004 else
4005 {
4006 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
4007 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback));
4008 }
4009}
4010
4011/* Opcode VEX.0F 0x72 11/6 - invalid. */
4012
4013/** Opcode VEX.66.0F 0x72 11/6. */
4014FNIEMOP_DEF_1(iemOp_VGrp13_vpslld_Hx_Ux_Ib, uint8_t, bRm)
4015{
4016 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSLLD, vpslld, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4017 if (pVCpu->iem.s.uVexLength)
4018 {
4019 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
4020 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback));
4021 }
4022 else
4023 {
4024 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
4025 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback));
4026 }
4027}
4028
4029
4030/**
4031 * Group 13 jump table for register variant.
4032 */
4033IEM_STATIC const PFNIEMOPRM g_apfnVexGroup13RegReg[] =
4034{
4035 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4036 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4037 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4038 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4039 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrad_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4040 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4041 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpslld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4042 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
4043};
4044AssertCompile(RT_ELEMENTS(g_apfnVexGroup13RegReg) == 8*4);
4045
4046/** Opcode VEX.0F 0x72. */
4047FNIEMOP_DEF(iemOp_VGrp13)
4048{
4049 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4050 if (IEM_IS_MODRM_REG_MODE(bRm))
4051 /* register, register */
4052 return FNIEMOP_CALL_1(g_apfnVexGroup13RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
4053 + pVCpu->iem.s.idxPrefix], bRm);
4054 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
4055}
4056
4057
4058/* Opcode VEX.0F 0x73 11/2 - invalid. */
4059/** Opcode VEX.66.0F 0x73 11/2. */
4060FNIEMOP_DEF_1(iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, uint8_t, bRm)
4061{
4062 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLQ, vpsrlq, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4063 if (pVCpu->iem.s.uVexLength)
4064 {
4065 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
4066 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback));
4067 }
4068 else
4069 {
4070 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
4071 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback));
4072 }
4073}
4074
4075
4076/** Opcode VEX.66.0F 0x73 11/3. */
4077FNIEMOP_DEF_1(iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, uint8_t, bRm)
4078{
4079 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLDQ, vpsrldq, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4080 if (pVCpu->iem.s.uVexLength)
4081 {
4082 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
4083 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrldq_imm_u256, iemAImpl_vpsrldq_imm_u256_fallback));
4084 }
4085 else
4086 {
4087 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
4088 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrldq_imm_u128, iemAImpl_vpsrldq_imm_u128_fallback));
4089 }
4090}
4091
4092/* Opcode VEX.0F 0x73 11/6 - invalid. */
4093
4094/** Opcode VEX.66.0F 0x73 11/6. */
4095FNIEMOP_DEF_1(iemOp_VGrp14_vpsllq_Hx_Ux_Ib, uint8_t, bRm)
4096{
4097 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSLLQ, vpsllq, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4098 if (pVCpu->iem.s.uVexLength)
4099 {
4100 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
4101 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback));
4102 }
4103 else
4104 {
4105 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
4106 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback));
4107 }
4108}
4109
4110/** Opcode VEX.66.0F 0x73 11/7. */
4111FNIEMOP_DEF_1(iemOp_VGrp14_vpslldq_Hx_Ux_Ib, uint8_t, bRm)
4112{
4113 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSLLDQ, vpslldq, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4114 if (pVCpu->iem.s.uVexLength)
4115 {
4116 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
4117 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpslldq_imm_u256, iemAImpl_vpslldq_imm_u256_fallback));
4118 }
4119 else
4120 {
4121 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
4122 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpslldq_imm_u128, iemAImpl_vpslldq_imm_u128_fallback));
4123 }
4124}
4125
4126/* Opcode VEX.0F 0x73 11/6 - invalid. */
4127
4128/**
4129 * Group 14 jump table for register variant.
4130 */
4131IEM_STATIC const PFNIEMOPRM g_apfnVexGroup14RegReg[] =
4132{
4133 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4134 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4135 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4136 /* /3 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4137 /* /4 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4138 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
4139 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsllq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4140 /* /7 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpslldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
4141};
4142AssertCompile(RT_ELEMENTS(g_apfnVexGroup14RegReg) == 8*4);
4143
4144
4145/** Opcode VEX.0F 0x73. */
4146FNIEMOP_DEF(iemOp_VGrp14)
4147{
4148 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4149 if (IEM_IS_MODRM_REG_MODE(bRm))
4150 /* register, register */
4151 return FNIEMOP_CALL_1(g_apfnVexGroup14RegReg[ IEM_GET_MODRM_REG_8(bRm) * 4
4152 + pVCpu->iem.s.idxPrefix], bRm);
4153 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
4154}
4155
4156
4157/* Opcode VEX.0F 0x74 - invalid */
4158
4159
4160/** Opcode VEX.66.0F 0x74 - vpcmpeqb Vx, Hx, Wx */
4161FNIEMOP_DEF(iemOp_vpcmpeqb_Vx_Hx_Wx)
4162{
4163 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQB, vpcmpeqb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4164 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpeqb);
4165 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4166}
4167
4168/* Opcode VEX.F3.0F 0x74 - invalid */
4169/* Opcode VEX.F2.0F 0x74 - invalid */
4170
4171
4172/* Opcode VEX.0F 0x75 - invalid */
4173
4174
4175/** Opcode VEX.66.0F 0x75 - vpcmpeqw Vx, Hx, Wx */
4176FNIEMOP_DEF(iemOp_vpcmpeqw_Vx_Hx_Wx)
4177{
4178 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQW, vpcmpeqw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4179 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpeqw);
4180 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4181}
4182
4183
4184/* Opcode VEX.F3.0F 0x75 - invalid */
4185/* Opcode VEX.F2.0F 0x75 - invalid */
4186
4187
4188/* Opcode VEX.0F 0x76 - invalid */
4189
4190
4191/** Opcode VEX.66.0F 0x76 - vpcmpeqd Vx, Hx, Wx */
4192FNIEMOP_DEF(iemOp_vpcmpeqd_Vx_Hx_Wx)
4193{
4194 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQD, vpcmpeqd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
4195 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpeqd);
4196 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
4197}
4198
4199
4200/* Opcode VEX.F3.0F 0x76 - invalid */
4201/* Opcode VEX.F2.0F 0x76 - invalid */
4202
4203
4204/** Opcode VEX.0F 0x77 - vzeroupperv vzeroallv */
4205FNIEMOP_DEF(iemOp_vzeroupperv__vzeroallv)
4206{
4207 Assert(pVCpu->iem.s.uVexLength <= 1);
4208 if (pVCpu->iem.s.uVexLength == 0)
4209 {
4210 /*
4211 * 128-bit: vzeroupper
4212 */
4213 IEMOP_MNEMONIC(vzeroupper, "vzeroupper");
4214 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4215
4216 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4217 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4218 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4219
4220 IEM_MC_CLEAR_YREG_128_UP(0);
4221 IEM_MC_CLEAR_YREG_128_UP(1);
4222 IEM_MC_CLEAR_YREG_128_UP(2);
4223 IEM_MC_CLEAR_YREG_128_UP(3);
4224 IEM_MC_CLEAR_YREG_128_UP(4);
4225 IEM_MC_CLEAR_YREG_128_UP(5);
4226 IEM_MC_CLEAR_YREG_128_UP(6);
4227 IEM_MC_CLEAR_YREG_128_UP(7);
4228
4229 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4230 {
4231 IEM_MC_CLEAR_YREG_128_UP( 8);
4232 IEM_MC_CLEAR_YREG_128_UP( 9);
4233 IEM_MC_CLEAR_YREG_128_UP(10);
4234 IEM_MC_CLEAR_YREG_128_UP(11);
4235 IEM_MC_CLEAR_YREG_128_UP(12);
4236 IEM_MC_CLEAR_YREG_128_UP(13);
4237 IEM_MC_CLEAR_YREG_128_UP(14);
4238 IEM_MC_CLEAR_YREG_128_UP(15);
4239 }
4240
4241 IEM_MC_ADVANCE_RIP_AND_FINISH();
4242 IEM_MC_END();
4243 }
4244 else
4245 {
4246 /*
4247 * 256-bit: vzeroall
4248 */
4249 IEMOP_MNEMONIC(vzeroall, "vzeroall");
4250 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4251
4252 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4253 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4254 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4255
4256 IEM_MC_LOCAL_CONST(uint32_t, uZero, 0);
4257 IEM_MC_STORE_YREG_U32_ZX_VLMAX(0, uZero);
4258 IEM_MC_STORE_YREG_U32_ZX_VLMAX(1, uZero);
4259 IEM_MC_STORE_YREG_U32_ZX_VLMAX(2, uZero);
4260 IEM_MC_STORE_YREG_U32_ZX_VLMAX(3, uZero);
4261 IEM_MC_STORE_YREG_U32_ZX_VLMAX(4, uZero);
4262 IEM_MC_STORE_YREG_U32_ZX_VLMAX(5, uZero);
4263 IEM_MC_STORE_YREG_U32_ZX_VLMAX(6, uZero);
4264 IEM_MC_STORE_YREG_U32_ZX_VLMAX(7, uZero);
4265
4266 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4267 {
4268 IEM_MC_STORE_YREG_U32_ZX_VLMAX( 8, uZero);
4269 IEM_MC_STORE_YREG_U32_ZX_VLMAX( 9, uZero);
4270 IEM_MC_STORE_YREG_U32_ZX_VLMAX(10, uZero);
4271 IEM_MC_STORE_YREG_U32_ZX_VLMAX(11, uZero);
4272 IEM_MC_STORE_YREG_U32_ZX_VLMAX(12, uZero);
4273 IEM_MC_STORE_YREG_U32_ZX_VLMAX(13, uZero);
4274 IEM_MC_STORE_YREG_U32_ZX_VLMAX(14, uZero);
4275 IEM_MC_STORE_YREG_U32_ZX_VLMAX(15, uZero);
4276 }
4277
4278 IEM_MC_ADVANCE_RIP_AND_FINISH();
4279 IEM_MC_END();
4280 }
4281}
4282
4283
4284/* Opcode VEX.66.0F 0x77 - invalid */
4285/* Opcode VEX.F3.0F 0x77 - invalid */
4286/* Opcode VEX.F2.0F 0x77 - invalid */
4287
4288/* Opcode VEX.0F 0x78 - invalid */
4289/* Opcode VEX.66.0F 0x78 - invalid */
4290/* Opcode VEX.F3.0F 0x78 - invalid */
4291/* Opcode VEX.F2.0F 0x78 - invalid */
4292
4293/* Opcode VEX.0F 0x79 - invalid */
4294/* Opcode VEX.66.0F 0x79 - invalid */
4295/* Opcode VEX.F3.0F 0x79 - invalid */
4296/* Opcode VEX.F2.0F 0x79 - invalid */
4297
4298/* Opcode VEX.0F 0x7a - invalid */
4299/* Opcode VEX.66.0F 0x7a - invalid */
4300/* Opcode VEX.F3.0F 0x7a - invalid */
4301/* Opcode VEX.F2.0F 0x7a - invalid */
4302
4303/* Opcode VEX.0F 0x7b - invalid */
4304/* Opcode VEX.66.0F 0x7b - invalid */
4305/* Opcode VEX.F3.0F 0x7b - invalid */
4306/* Opcode VEX.F2.0F 0x7b - invalid */
4307
4308/* Opcode VEX.0F 0x7c - invalid */
4309/** Opcode VEX.66.0F 0x7c - vhaddpd Vpd, Hpd, Wpd */
4310FNIEMOP_STUB(iemOp_vhaddpd_Vpd_Hpd_Wpd);
4311/* Opcode VEX.F3.0F 0x7c - invalid */
4312
4313
4314/** Opcode VEX.F2.0F 0x7c - vhaddps Vps, Hps, Wps */
4315FNIEMOP_DEF(iemOp_vhaddps_Vps_Hps_Wps)
4316{
4317 IEMOP_MNEMONIC3(VEX_RVM, VHADDPS, vhaddps, Vps, Hps, Wps, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
4318 IEMOPMEDIAF3_INIT_VARS( vhaddps);
4319 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
4320}
4321
4322
4323/* Opcode VEX.0F 0x7d - invalid */
4324/** Opcode VEX.66.0F 0x7d - vhsubpd Vpd, Hpd, Wpd */
4325FNIEMOP_STUB(iemOp_vhsubpd_Vpd_Hpd_Wpd);
4326/* Opcode VEX.F3.0F 0x7d - invalid */
4327/** Opcode VEX.F2.0F 0x7d - vhsubps Vps, Hps, Wps */
4328FNIEMOP_STUB(iemOp_vhsubps_Vps_Hps_Wps);
4329
4330
4331/* Opcode VEX.0F 0x7e - invalid */
4332
4333FNIEMOP_DEF(iemOp_vmovd_q_Ey_Vy)
4334{
4335 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4336 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
4337 {
4338 /**
4339 * @opcode 0x7e
4340 * @opcodesub rex.w=1
4341 * @oppfx 0x66
4342 * @opcpuid avx
4343 * @opgroup og_avx_simdint_datamov
4344 * @opxcpttype 5
4345 * @optest 64-bit / op1=1 op2=2 -> op1=2
4346 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
4347 */
4348 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Eq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
4349 if (IEM_IS_MODRM_REG_MODE(bRm))
4350 {
4351 /* greg64, XMM */
4352 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
4353 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4354 IEM_MC_LOCAL(uint64_t, u64Tmp);
4355
4356 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4357 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4358
4359 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
4360 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Tmp);
4361
4362 IEM_MC_ADVANCE_RIP_AND_FINISH();
4363 IEM_MC_END();
4364 }
4365 else
4366 {
4367 /* [mem64], XMM */
4368 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
4369 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4370 IEM_MC_LOCAL(uint64_t, u64Tmp);
4371
4372 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4373 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4374 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4375 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4376
4377 IEM_MC_FETCH_YREG_U64(u64Tmp, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
4378 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
4379
4380 IEM_MC_ADVANCE_RIP_AND_FINISH();
4381 IEM_MC_END();
4382 }
4383 }
4384 else
4385 {
4386 /**
4387 * @opdone
4388 * @opcode 0x7e
4389 * @opcodesub rex.w=0
4390 * @oppfx 0x66
4391 * @opcpuid avx
4392 * @opgroup og_avx_simdint_datamov
4393 * @opxcpttype 5
4394 * @opfunction iemOp_vmovd_q_Vy_Ey
4395 * @optest op1=1 op2=2 -> op1=2
4396 * @optest op1=0 op2=-42 -> op1=-42
4397 */
4398 IEMOP_MNEMONIC2(VEX_MR, VMOVD, vmovd, Ed_WO, Vd, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_VEX_L_ZERO);
4399 if (IEM_IS_MODRM_REG_MODE(bRm))
4400 {
4401 /* greg32, XMM */
4402 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4403 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4404 IEM_MC_LOCAL(uint32_t, u32Tmp);
4405
4406 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4407 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4408
4409 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4410 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Tmp);
4411
4412 IEM_MC_ADVANCE_RIP_AND_FINISH();
4413 IEM_MC_END();
4414 }
4415 else
4416 {
4417 /* [mem32], XMM */
4418 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4419 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4420 IEM_MC_LOCAL(uint32_t, u32Tmp);
4421
4422 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4423 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4424 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4425 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4426
4427 IEM_MC_FETCH_YREG_U32(u32Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4428 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
4429
4430 IEM_MC_ADVANCE_RIP_AND_FINISH();
4431 IEM_MC_END();
4432 }
4433 }
4434}
4435
4436
4437/**
4438 * @opcode 0x7e
4439 * @oppfx 0xf3
4440 * @opcpuid avx
4441 * @opgroup og_avx_pcksclr_datamove
4442 * @opxcpttype none
4443 * @optest op1=1 op2=2 -> op1=2
4444 * @optest op1=0 op2=-42 -> op1=-42
4445 */
4446FNIEMOP_DEF(iemOp_vmovq_Vq_Wq)
4447{
4448 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
4449 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4450 if (IEM_IS_MODRM_REG_MODE(bRm))
4451 {
4452 /*
4453 * Register, register.
4454 */
4455 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4456 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4457
4458 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4459 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4460
4461 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm),
4462 IEM_GET_MODRM_RM(pVCpu, bRm));
4463 IEM_MC_ADVANCE_RIP_AND_FINISH();
4464 IEM_MC_END();
4465 }
4466 else
4467 {
4468 /*
4469 * Memory, register.
4470 */
4471 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4472 IEM_MC_LOCAL(uint64_t, uSrc);
4473 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4474
4475 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4476 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4477 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4478 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4479
4480 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4481 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
4482
4483 IEM_MC_ADVANCE_RIP_AND_FINISH();
4484 IEM_MC_END();
4485 }
4486
4487}
4488/* Opcode VEX.F2.0F 0x7e - invalid */
4489
4490
4491/* Opcode VEX.0F 0x7f - invalid */
4492
4493/**
4494 * @opcode 0x7f
4495 * @oppfx 0x66
4496 * @opcpuid avx
4497 * @opgroup og_avx_simdint_datamove
4498 * @opxcpttype 1
4499 * @optest op1=1 op2=2 -> op1=2
4500 * @optest op1=0 op2=-42 -> op1=-42
4501 */
4502FNIEMOP_DEF(iemOp_vmovdqa_Wx_Vx)
4503{
4504 IEMOP_MNEMONIC2(VEX_MR, VMOVDQA, vmovdqa, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4505 Assert(pVCpu->iem.s.uVexLength <= 1);
4506 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4507 if (IEM_IS_MODRM_REG_MODE(bRm))
4508 {
4509 /*
4510 * Register, register.
4511 */
4512 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4513 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4514
4515 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4516 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4517 if (pVCpu->iem.s.uVexLength == 0)
4518 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4519 IEM_GET_MODRM_REG(pVCpu, bRm));
4520 else
4521 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4522 IEM_GET_MODRM_REG(pVCpu, bRm));
4523 IEM_MC_ADVANCE_RIP_AND_FINISH();
4524 IEM_MC_END();
4525 }
4526 else if (pVCpu->iem.s.uVexLength == 0)
4527 {
4528 /*
4529 * Register, memory128.
4530 */
4531 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4532 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4533 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4534
4535 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4536 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4537 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4538 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4539
4540 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
4541 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
4542
4543 IEM_MC_ADVANCE_RIP_AND_FINISH();
4544 IEM_MC_END();
4545 }
4546 else
4547 {
4548 /*
4549 * Register, memory256.
4550 */
4551 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4552 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
4553 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4554
4555 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4556 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4557 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4558 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4559
4560 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4561 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
4562
4563 IEM_MC_ADVANCE_RIP_AND_FINISH();
4564 IEM_MC_END();
4565 }
4566}
4567
4568
4569/**
4570 * @opcode 0x7f
4571 * @oppfx 0xf3
4572 * @opcpuid avx
4573 * @opgroup og_avx_simdint_datamove
4574 * @opxcpttype 4UA
4575 * @optest op1=1 op2=2 -> op1=2
4576 * @optest op1=0 op2=-42 -> op1=-42
4577 */
4578FNIEMOP_DEF(iemOp_vmovdqu_Wx_Vx)
4579{
4580 IEMOP_MNEMONIC2(VEX_MR, VMOVDQU, vmovdqu, Wx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
4581 Assert(pVCpu->iem.s.uVexLength <= 1);
4582 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4583 if (IEM_IS_MODRM_REG_MODE(bRm))
4584 {
4585 /*
4586 * Register, register.
4587 */
4588 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4589 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4590
4591 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4592 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
4593 if (pVCpu->iem.s.uVexLength == 0)
4594 IEM_MC_COPY_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4595 IEM_GET_MODRM_REG(pVCpu, bRm));
4596 else
4597 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
4598 IEM_GET_MODRM_REG(pVCpu, bRm));
4599 IEM_MC_ADVANCE_RIP_AND_FINISH();
4600 IEM_MC_END();
4601 }
4602 else if (pVCpu->iem.s.uVexLength == 0)
4603 {
4604 /*
4605 * Register, memory128.
4606 */
4607 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4608 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
4609 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4610
4611 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4612 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4613 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4614 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4615
4616 IEM_MC_FETCH_YREG_U128(u128Tmp, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
4617 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
4618
4619 IEM_MC_ADVANCE_RIP_AND_FINISH();
4620 IEM_MC_END();
4621 }
4622 else
4623 {
4624 /*
4625 * Register, memory256.
4626 */
4627 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4628 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
4629 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4630
4631 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
4632 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
4633 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4634 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
4635
4636 IEM_MC_FETCH_YREG_U256(u256Tmp, IEM_GET_MODRM_REG(pVCpu, bRm));
4637 IEM_MC_STORE_MEM_U256_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp);
4638
4639 IEM_MC_ADVANCE_RIP_AND_FINISH();
4640 IEM_MC_END();
4641 }
4642}
4643
4644/* Opcode VEX.F2.0F 0x7f - invalid */
4645
4646
4647/* Opcode VEX.0F 0x80 - invalid */
4648/* Opcode VEX.0F 0x81 - invalid */
4649/* Opcode VEX.0F 0x82 - invalid */
4650/* Opcode VEX.0F 0x83 - invalid */
4651/* Opcode VEX.0F 0x84 - invalid */
4652/* Opcode VEX.0F 0x85 - invalid */
4653/* Opcode VEX.0F 0x86 - invalid */
4654/* Opcode VEX.0F 0x87 - invalid */
4655/* Opcode VEX.0F 0x88 - invalid */
4656/* Opcode VEX.0F 0x89 - invalid */
4657/* Opcode VEX.0F 0x8a - invalid */
4658/* Opcode VEX.0F 0x8b - invalid */
4659/* Opcode VEX.0F 0x8c - invalid */
4660/* Opcode VEX.0F 0x8d - invalid */
4661/* Opcode VEX.0F 0x8e - invalid */
4662/* Opcode VEX.0F 0x8f - invalid */
4663/* Opcode VEX.0F 0x90 - invalid */
4664/* Opcode VEX.0F 0x91 - invalid */
4665/* Opcode VEX.0F 0x92 - invalid */
4666/* Opcode VEX.0F 0x93 - invalid */
4667/* Opcode VEX.0F 0x94 - invalid */
4668/* Opcode VEX.0F 0x95 - invalid */
4669/* Opcode VEX.0F 0x96 - invalid */
4670/* Opcode VEX.0F 0x97 - invalid */
4671/* Opcode VEX.0F 0x98 - invalid */
4672/* Opcode VEX.0F 0x99 - invalid */
4673/* Opcode VEX.0F 0x9a - invalid */
4674/* Opcode VEX.0F 0x9b - invalid */
4675/* Opcode VEX.0F 0x9c - invalid */
4676/* Opcode VEX.0F 0x9d - invalid */
4677/* Opcode VEX.0F 0x9e - invalid */
4678/* Opcode VEX.0F 0x9f - invalid */
4679/* Opcode VEX.0F 0xa0 - invalid */
4680/* Opcode VEX.0F 0xa1 - invalid */
4681/* Opcode VEX.0F 0xa2 - invalid */
4682/* Opcode VEX.0F 0xa3 - invalid */
4683/* Opcode VEX.0F 0xa4 - invalid */
4684/* Opcode VEX.0F 0xa5 - invalid */
4685/* Opcode VEX.0F 0xa6 - invalid */
4686/* Opcode VEX.0F 0xa7 - invalid */
4687/* Opcode VEX.0F 0xa8 - invalid */
4688/* Opcode VEX.0F 0xa9 - invalid */
4689/* Opcode VEX.0F 0xaa - invalid */
4690/* Opcode VEX.0F 0xab - invalid */
4691/* Opcode VEX.0F 0xac - invalid */
4692/* Opcode VEX.0F 0xad - invalid */
4693
4694
4695/* Opcode VEX.0F 0xae mem/0 - invalid. */
4696/* Opcode VEX.0F 0xae mem/1 - invalid. */
4697
4698/**
4699 * @ opmaps grp15
4700 * @ opcode !11/2
4701 * @ oppfx none
4702 * @ opcpuid sse
4703 * @ opgroup og_sse_mxcsrsm
4704 * @ opxcpttype 5
4705 * @ optest op1=0 -> mxcsr=0
4706 * @ optest op1=0x2083 -> mxcsr=0x2083
4707 * @ optest op1=0xfffffffe -> value.xcpt=0xd
4708 * @ optest op1=0x2083 cr0|=ts -> value.xcpt=0x7
4709 * @ optest op1=0x2083 cr0|=em -> value.xcpt=0x6
4710 * @ optest op1=0x2083 cr0|=mp -> mxcsr=0x2083
4711 * @ optest op1=0x2083 cr4&~=osfxsr -> value.xcpt=0x6
4712 * @ optest op1=0x2083 cr0|=ts,em -> value.xcpt=0x6
4713 * @ optest op1=0x2083 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
4714 * @ optest op1=0x2083 cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
4715 * @ optest op1=0x2083 cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
4716 */
4717FNIEMOP_STUB_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm);
4718//FNIEMOP_DEF_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm)
4719//{
4720// IEMOP_MNEMONIC1(M_MEM, VLDMXCSR, vldmxcsr, MdRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
4721// IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4722// IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
4723// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
4724// IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4725// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4726// IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
4727// IEM_MC_CALL_CIMPL_2(iemCImpl_ldmxcsr, iEffSeg, GCPtrEff);
4728// IEM_MC_END();
4729// return VINF_SUCCESS;
4730//}
4731
4732
4733/**
4734 * @opmaps vexgrp15
4735 * @opcode !11/3
4736 * @oppfx none
4737 * @opcpuid avx
4738 * @opgroup og_avx_mxcsrsm
4739 * @opxcpttype 5
4740 * @optest mxcsr=0 -> op1=0
4741 * @optest mxcsr=0x2083 -> op1=0x2083
4742 * @optest mxcsr=0x2084 cr0|=ts -> value.xcpt=0x7
4743 * @optest !amd / mxcsr=0x2085 cr0|=em -> op1=0x2085
4744 * @optest amd / mxcsr=0x2085 cr0|=em -> value.xcpt=0x6
4745 * @optest mxcsr=0x2086 cr0|=mp -> op1=0x2086
4746 * @optest mxcsr=0x2087 cr4&~=osfxsr -> op1=0x2087
4747 * @optest mxcsr=0x208f cr4&~=osxsave -> value.xcpt=0x6
4748 * @optest mxcsr=0x2087 cr4&~=osfxsr,osxsave -> value.xcpt=0x6
4749 * @optest !amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x7
4750 * @optest amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x6
4751 * @optest !amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> op1=0x2089
4752 * @optest amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
4753 * @optest !amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x7
4754 * @optest amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
4755 * @optest !amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x7
4756 * @optest amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
4757 * @optest !amd / mxcsr=0x208c xcr0&~=all_avx -> value.xcpt=0x6
4758 * @optest amd / mxcsr=0x208c xcr0&~=all_avx -> op1=0x208c
4759 * @optest !amd / mxcsr=0x208d xcr0&~=all_avx_sse -> value.xcpt=0x6
4760 * @optest amd / mxcsr=0x208d xcr0&~=all_avx_sse -> op1=0x208d
4761 * @optest !amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x6
4762 * @optest amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x7
4763 * @optest mxcsr=0x2082 cr0|=ts cr4&~=osxsave -> value.xcpt=0x6
4764 * @optest mxcsr=0x2081 xcr0&~=all_avx cr0|=ts cr4&~=osxsave
4765 * -> value.xcpt=0x6
4766 * @remarks AMD Jaguar CPU (f0x16,m0,s1) \#UD when CR0.EM is set. It also
4767 * doesn't seem to check XCR0[2:1] != 11b. This does not match the
4768 * APMv4 rev 3.17 page 509.
4769 * @todo Test this instruction on AMD Ryzen.
4770 */
4771FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr, uint8_t, bRm)
4772{
4773 IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
4774 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4775 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
4776 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
4777 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
4778 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
4779 IEM_MC_ARG_CONST(uint8_t, iEffSeg, /*=*/ pVCpu->iem.s.iEffSeg, 0);
4780 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_FPU, 0, iemCImpl_vstmxcsr, iEffSeg, GCPtrEff);
4781 IEM_MC_END();
4782}
4783
4784/* Opcode VEX.0F 0xae mem/4 - invalid. */
4785/* Opcode VEX.0F 0xae mem/5 - invalid. */
4786/* Opcode VEX.0F 0xae mem/6 - invalid. */
4787/* Opcode VEX.0F 0xae mem/7 - invalid. */
4788
4789/* Opcode VEX.0F 0xae 11b/0 - invalid. */
4790/* Opcode VEX.0F 0xae 11b/1 - invalid. */
4791/* Opcode VEX.0F 0xae 11b/2 - invalid. */
4792/* Opcode VEX.0F 0xae 11b/3 - invalid. */
4793/* Opcode VEX.0F 0xae 11b/4 - invalid. */
4794/* Opcode VEX.0F 0xae 11b/5 - invalid. */
4795/* Opcode VEX.0F 0xae 11b/6 - invalid. */
4796/* Opcode VEX.0F 0xae 11b/7 - invalid. */
4797
4798/**
4799 * Vex group 15 jump table for memory variant.
4800 */
4801IEM_STATIC const PFNIEMOPRM g_apfnVexGroup15MemReg[] =
4802{ /* pfx: none, 066h, 0f3h, 0f2h */
4803 /* /0 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4804 /* /1 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4805 /* /2 */ iemOp_VGrp15_vldmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4806 /* /3 */ iemOp_VGrp15_vstmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4807 /* /4 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4808 /* /5 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4809 /* /6 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4810 /* /7 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
4811};
4812AssertCompile(RT_ELEMENTS(g_apfnVexGroup15MemReg) == 8*4);
4813
4814
4815/** Opcode vex. 0xae. */
4816FNIEMOP_DEF(iemOp_VGrp15)
4817{
4818 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4819 if (IEM_IS_MODRM_REG_MODE(bRm))
4820 /* register, register */
4821 return FNIEMOP_CALL_1(iemOp_InvalidWithRM, bRm);
4822
4823 /* memory, register */
4824 return FNIEMOP_CALL_1(g_apfnVexGroup15MemReg[ IEM_GET_MODRM_REG_8(bRm) * 4
4825 + pVCpu->iem.s.idxPrefix], bRm);
4826}
4827
4828
4829/* Opcode VEX.0F 0xaf - invalid. */
4830
4831/* Opcode VEX.0F 0xb0 - invalid. */
4832/* Opcode VEX.0F 0xb1 - invalid. */
4833/* Opcode VEX.0F 0xb2 - invalid. */
4834/* Opcode VEX.0F 0xb2 - invalid. */
4835/* Opcode VEX.0F 0xb3 - invalid. */
4836/* Opcode VEX.0F 0xb4 - invalid. */
4837/* Opcode VEX.0F 0xb5 - invalid. */
4838/* Opcode VEX.0F 0xb6 - invalid. */
4839/* Opcode VEX.0F 0xb7 - invalid. */
4840/* Opcode VEX.0F 0xb8 - invalid. */
4841/* Opcode VEX.0F 0xb9 - invalid. */
4842/* Opcode VEX.0F 0xba - invalid. */
4843/* Opcode VEX.0F 0xbb - invalid. */
4844/* Opcode VEX.0F 0xbc - invalid. */
4845/* Opcode VEX.0F 0xbd - invalid. */
4846/* Opcode VEX.0F 0xbe - invalid. */
4847/* Opcode VEX.0F 0xbf - invalid. */
4848
4849/* Opcode VEX.0F 0xc0 - invalid. */
4850/* Opcode VEX.66.0F 0xc0 - invalid. */
4851/* Opcode VEX.F3.0F 0xc0 - invalid. */
4852/* Opcode VEX.F2.0F 0xc0 - invalid. */
4853
4854/* Opcode VEX.0F 0xc1 - invalid. */
4855/* Opcode VEX.66.0F 0xc1 - invalid. */
4856/* Opcode VEX.F3.0F 0xc1 - invalid. */
4857/* Opcode VEX.F2.0F 0xc1 - invalid. */
4858
4859/** Opcode VEX.0F 0xc2 - vcmpps Vps,Hps,Wps,Ib */
4860FNIEMOP_STUB(iemOp_vcmpps_Vps_Hps_Wps_Ib);
4861/** Opcode VEX.66.0F 0xc2 - vcmppd Vpd,Hpd,Wpd,Ib */
4862FNIEMOP_STUB(iemOp_vcmppd_Vpd_Hpd_Wpd_Ib);
4863/** Opcode VEX.F3.0F 0xc2 - vcmpss Vss,Hss,Wss,Ib */
4864FNIEMOP_STUB(iemOp_vcmpss_Vss_Hss_Wss_Ib);
4865/** Opcode VEX.F2.0F 0xc2 - vcmpsd Vsd,Hsd,Wsd,Ib */
4866FNIEMOP_STUB(iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib);
4867
4868/* Opcode VEX.0F 0xc3 - invalid */
4869/* Opcode VEX.66.0F 0xc3 - invalid */
4870/* Opcode VEX.F3.0F 0xc3 - invalid */
4871/* Opcode VEX.F2.0F 0xc3 - invalid */
4872
4873/* Opcode VEX.0F 0xc4 - invalid */
4874
4875
4876/** Opcode VEX.66.0F 0xc4 - vpinsrw Vdq,Hdq,Ry/Mw,Ib */
4877FNIEMOP_DEF(iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib)
4878{
4879 /*IEMOP_MNEMONIC4(VEX_RMV, VPINSRW, vpinsrw, Vdq, Vdq, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);*/ /** @todo */
4880 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4881 if (IEM_IS_MODRM_REG_MODE(bRm))
4882 {
4883 /*
4884 * Register, register.
4885 */
4886 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4887 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4888 IEM_MC_LOCAL(RTUINT128U, uSrc1);
4889 IEM_MC_LOCAL(uint16_t, uValue);
4890
4891 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4892 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4893 IEM_MC_PREPARE_AVX_USAGE();
4894
4895 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
4896 IEM_MC_FETCH_GREG_U16(uValue, IEM_GET_MODRM_RM(pVCpu, bRm));
4897 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
4898 IEM_MC_STORE_XREG_U16( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7, uValue);
4899 IEM_MC_ADVANCE_RIP_AND_FINISH();
4900 IEM_MC_END();
4901 }
4902 else
4903 {
4904 /*
4905 * Register, memory.
4906 */
4907 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4908 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
4909 IEM_MC_LOCAL(RTUINT128U, uSrc1);
4910 IEM_MC_LOCAL(uint16_t, uValue);
4911
4912 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
4913 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4914 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4915 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4916 IEM_MC_PREPARE_AVX_USAGE();
4917
4918 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
4919 IEM_MC_FETCH_MEM_U16(uValue, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
4920 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
4921 IEM_MC_STORE_XREG_U16( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7, uValue);
4922 IEM_MC_ADVANCE_RIP_AND_FINISH();
4923 IEM_MC_END();
4924 }
4925}
4926
4927
4928/* Opcode VEX.F3.0F 0xc4 - invalid */
4929/* Opcode VEX.F2.0F 0xc4 - invalid */
4930
4931/* Opcode VEX.0F 0xc5 - invalid */
4932
4933
4934/** Opcode VEX.66.0F 0xc5 - vpextrw Gd, Udq, Ib */
4935FNIEMOP_DEF(iemOp_vpextrw_Gd_Udq_Ib)
4936{
4937 IEMOP_MNEMONIC3(VEX_RMI_REG, VPEXTRW, vpextrw, Gd, Ux, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
4938 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4939 if (IEM_IS_MODRM_REG_MODE(bRm))
4940 {
4941 /*
4942 * greg32, XMM, imm8.
4943 */
4944 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
4945 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
4946 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
4947 IEM_MC_LOCAL(uint16_t, uValue);
4948 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
4949 IEM_MC_PREPARE_AVX_USAGE();
4950 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_RM(pVCpu, bRm), bImm & 7);
4951 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uValue);
4952 IEM_MC_ADVANCE_RIP_AND_FINISH();
4953 IEM_MC_END();
4954 }
4955 /* No memory operand. */
4956 else
4957 IEMOP_RAISE_INVALID_OPCODE_RET();
4958}
4959
4960
4961/* Opcode VEX.F3.0F 0xc5 - invalid */
4962/* Opcode VEX.F2.0F 0xc5 - invalid */
4963
4964
4965#define VSHUFP_X(a_Instr) \
4966 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
4967 if (IEM_IS_MODRM_REG_MODE(bRm)) \
4968 { \
4969 /* \
4970 * Register, register. \
4971 */ \
4972 if (pVCpu->iem.s.uVexLength) \
4973 { \
4974 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4975 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
4976 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
4977 IEM_MC_LOCAL(RTUINT256U, uDst); \
4978 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
4979 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
4980 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
4981 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
4982 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
4983 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
4984 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
4985 IEM_MC_PREPARE_AVX_USAGE(); \
4986 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
4987 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
4988 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
4989 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bImmArg); \
4990 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
4991 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
4992 IEM_MC_END(); \
4993 } \
4994 else \
4995 { \
4996 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
4997 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
4998 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
4999 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
5000 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
5001 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2); \
5002 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
5003 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
5004 IEM_MC_PREPARE_AVX_USAGE(); \
5005 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
5006 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
5007 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
5008 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
5009 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bImmArg); \
5010 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
5011 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
5012 IEM_MC_END(); \
5013 } \
5014 } \
5015 else \
5016 { \
5017 /* \
5018 * Register, memory. \
5019 */ \
5020 if (pVCpu->iem.s.uVexLength) \
5021 { \
5022 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
5023 IEM_MC_LOCAL(RTUINT256U, uDst); \
5024 IEM_MC_LOCAL(RTUINT256U, uSrc1); \
5025 IEM_MC_LOCAL(RTUINT256U, uSrc2); \
5026 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
5027 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
5028 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1); \
5029 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2); \
5030 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
5031 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
5032 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
5033 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2); \
5034 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
5035 IEM_MC_PREPARE_AVX_USAGE(); \
5036 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
5037 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
5038 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
5039 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bImmArg); \
5040 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
5041 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
5042 IEM_MC_END(); \
5043 } \
5044 else \
5045 { \
5046 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
5047 IEM_MC_LOCAL(RTUINT128U, uSrc2); \
5048 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
5049 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
5050 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1); \
5051 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2); \
5052 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
5053 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); \
5054 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); \
5055 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); \
5056 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
5057 IEM_MC_PREPARE_AVX_USAGE(); \
5058 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
5059 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
5060 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
5061 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
5062 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bImmArg); \
5063 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
5064 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
5065 IEM_MC_END(); \
5066 } \
5067 } \
5068 (void)0
5069
5070/** Opcode VEX.0F 0xc6 - vshufps Vps,Hps,Wps,Ib */
5071FNIEMOP_DEF(iemOp_vshufps_Vps_Hps_Wps_Ib)
5072{
5073 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPS, vshufps, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
5074 VSHUFP_X(vshufps);
5075}
5076
5077
5078/** Opcode VEX.66.0F 0xc6 - vshufpd Vpd,Hpd,Wpd,Ib */
5079FNIEMOP_DEF(iemOp_vshufpd_Vpd_Hpd_Wpd_Ib)
5080{
5081 IEMOP_MNEMONIC4(VEX_RMI, VSHUFPD, vshufpd, Vpd, Hpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_SKIP_PYTHON); /** @todo */
5082 VSHUFP_X(vshufpd);
5083}
5084#undef VSHUFP_X
5085
5086
5087/* Opcode VEX.F3.0F 0xc6 - invalid */
5088/* Opcode VEX.F2.0F 0xc6 - invalid */
5089
5090/* Opcode VEX.0F 0xc7 - invalid */
5091/* Opcode VEX.66.0F 0xc7 - invalid */
5092/* Opcode VEX.F3.0F 0xc7 - invalid */
5093/* Opcode VEX.F2.0F 0xc7 - invalid */
5094
5095/* Opcode VEX.0F 0xc8 - invalid */
5096/* Opcode VEX.0F 0xc9 - invalid */
5097/* Opcode VEX.0F 0xca - invalid */
5098/* Opcode VEX.0F 0xcb - invalid */
5099/* Opcode VEX.0F 0xcc - invalid */
5100/* Opcode VEX.0F 0xcd - invalid */
5101/* Opcode VEX.0F 0xce - invalid */
5102/* Opcode VEX.0F 0xcf - invalid */
5103
5104
5105/* Opcode VEX.0F 0xd0 - invalid */
5106/** Opcode VEX.66.0F 0xd0 - vaddsubpd Vpd, Hpd, Wpd */
5107FNIEMOP_STUB(iemOp_vaddsubpd_Vpd_Hpd_Wpd);
5108/* Opcode VEX.F3.0F 0xd0 - invalid */
5109/** Opcode VEX.F2.0F 0xd0 - vaddsubps Vps, Hps, Wps */
5110FNIEMOP_STUB(iemOp_vaddsubps_Vps_Hps_Wps);
5111
5112/* Opcode VEX.0F 0xd1 - invalid */
5113/** Opcode VEX.66.0F 0xd1 - vpsrlw Vx, Hx, W */
5114FNIEMOP_DEF(iemOp_vpsrlw_Vx_Hx_W)
5115{
5116 IEMOP_MNEMONIC3(VEX_RVM, VPSRLW, vpsrlw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5117 IEMOPMEDIAOPTF3_INIT_VARS(vpsrlw);
5118 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5119}
5120
5121/* Opcode VEX.F3.0F 0xd1 - invalid */
5122/* Opcode VEX.F2.0F 0xd1 - invalid */
5123
5124/* Opcode VEX.0F 0xd2 - invalid */
5125/** Opcode VEX.66.0F 0xd2 - vpsrld Vx, Hx, Wx */
5126FNIEMOP_DEF(iemOp_vpsrld_Vx_Hx_Wx)
5127{
5128 IEMOP_MNEMONIC3(VEX_RVM, VPSRLD, vpsrld, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5129 IEMOPMEDIAOPTF3_INIT_VARS(vpsrld);
5130 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5131}
5132
5133/* Opcode VEX.F3.0F 0xd2 - invalid */
5134/* Opcode VEX.F2.0F 0xd2 - invalid */
5135
5136/* Opcode VEX.0F 0xd3 - invalid */
5137/** Opcode VEX.66.0F 0xd3 - vpsrlq Vx, Hx, Wx */
5138FNIEMOP_DEF(iemOp_vpsrlq_Vx_Hx_Wx)
5139{
5140 IEMOP_MNEMONIC3(VEX_RVM, VPSRLQ, vpsrlq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5141 IEMOPMEDIAOPTF3_INIT_VARS(vpsrlq);
5142 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5143}
5144
5145/* Opcode VEX.F3.0F 0xd3 - invalid */
5146/* Opcode VEX.F2.0F 0xd3 - invalid */
5147
5148/* Opcode VEX.0F 0xd4 - invalid */
5149
5150
5151/** Opcode VEX.66.0F 0xd4 - vpaddq Vx, Hx, W */
5152FNIEMOP_DEF(iemOp_vpaddq_Vx_Hx_Wx)
5153{
5154 IEMOP_MNEMONIC3(VEX_RVM, VPADDQ, vpaddq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5155 IEMOPMEDIAOPTF3_INIT_VARS( vpaddq);
5156 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5157}
5158
5159
5160/* Opcode VEX.F3.0F 0xd4 - invalid */
5161/* Opcode VEX.F2.0F 0xd4 - invalid */
5162
5163/* Opcode VEX.0F 0xd5 - invalid */
5164
5165
5166/** Opcode VEX.66.0F 0xd5 - vpmullw Vx, Hx, Wx */
5167FNIEMOP_DEF(iemOp_vpmullw_Vx_Hx_Wx)
5168{
5169 IEMOP_MNEMONIC3(VEX_RVM, VPMULLW, vpmullw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5170 IEMOPMEDIAOPTF3_INIT_VARS(vpmullw);
5171 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5172}
5173
5174
5175/* Opcode VEX.F3.0F 0xd5 - invalid */
5176/* Opcode VEX.F2.0F 0xd5 - invalid */
5177
5178/* Opcode VEX.0F 0xd6 - invalid */
5179
5180/**
5181 * @opcode 0xd6
5182 * @oppfx 0x66
5183 * @opcpuid avx
5184 * @opgroup og_avx_pcksclr_datamove
5185 * @opxcpttype none
5186 * @optest op1=-1 op2=2 -> op1=2
5187 * @optest op1=0 op2=-42 -> op1=-42
5188 */
5189FNIEMOP_DEF(iemOp_vmovq_Wq_Vq)
5190{
5191 IEMOP_MNEMONIC2(VEX_MR, VMOVQ, vmovq, Wq_WO, Vq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
5192 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5193 if (IEM_IS_MODRM_REG_MODE(bRm))
5194 {
5195 /*
5196 * Register, register.
5197 */
5198 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5199 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
5200
5201 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5202 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
5203
5204 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm),
5205 IEM_GET_MODRM_REG(pVCpu, bRm));
5206 IEM_MC_ADVANCE_RIP_AND_FINISH();
5207 IEM_MC_END();
5208 }
5209 else
5210 {
5211 /*
5212 * Memory, register.
5213 */
5214 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5215 IEM_MC_LOCAL(uint64_t, uSrc);
5216 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5217
5218 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5219 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
5220 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5221 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
5222
5223 IEM_MC_FETCH_YREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
5224 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
5225
5226 IEM_MC_ADVANCE_RIP_AND_FINISH();
5227 IEM_MC_END();
5228 }
5229}
5230
5231/* Opcode VEX.F3.0F 0xd6 - invalid */
5232/* Opcode VEX.F2.0F 0xd6 - invalid */
5233
5234
5235/* Opcode VEX.0F 0xd7 - invalid */
5236
5237/** Opcode VEX.66.0F 0xd7 - */
5238FNIEMOP_DEF(iemOp_vpmovmskb_Gd_Ux)
5239{
5240 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5241 /* Docs says register only. */
5242 if (IEM_IS_MODRM_REG_MODE(bRm)) /** @todo test that this is registers only. */
5243 {
5244 /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
5245 IEMOP_MNEMONIC2(VEX_RM_REG, VPMOVMSKB, vpmovmskb, Gd, Ux, DISOPTYPE_X86_SSE | DISOPTYPE_HARMLESS, 0);
5246 if (pVCpu->iem.s.uVexLength)
5247 {
5248 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5249 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
5250 IEM_MC_ARG(uint64_t *, puDst, 0);
5251 IEM_MC_LOCAL(RTUINT256U, uSrc);
5252 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
5253 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5254 IEM_MC_PREPARE_AVX_USAGE();
5255 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
5256 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
5257 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpmovmskb_u256,
5258 iemAImpl_vpmovmskb_u256_fallback), puDst, puSrc);
5259 IEM_MC_ADVANCE_RIP_AND_FINISH();
5260 IEM_MC_END();
5261 }
5262 else
5263 {
5264 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5265 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5266 IEM_MC_ARG(uint64_t *, puDst, 0);
5267 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
5268 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5269 IEM_MC_PREPARE_AVX_USAGE();
5270 IEM_MC_REF_GREG_U64(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
5271 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
5272 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_pmovmskb_u128, puDst, puSrc);
5273 IEM_MC_ADVANCE_RIP_AND_FINISH();
5274 IEM_MC_END();
5275 }
5276 }
5277 else
5278 IEMOP_RAISE_INVALID_OPCODE_RET();
5279}
5280
5281
5282/* Opcode VEX.F3.0F 0xd7 - invalid */
5283/* Opcode VEX.F2.0F 0xd7 - invalid */
5284
5285
5286/* Opcode VEX.0F 0xd8 - invalid */
5287
5288/** Opcode VEX.66.0F 0xd8 - vpsubusb Vx, Hx, Wx */
5289FNIEMOP_DEF(iemOp_vpsubusb_Vx_Hx_Wx)
5290{
5291 IEMOP_MNEMONIC3(VEX_RVM, VPSUBUSB, vpsubusb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5292 IEMOPMEDIAOPTF3_INIT_VARS(vpsubusb);
5293 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5294}
5295
5296
5297/* Opcode VEX.F3.0F 0xd8 - invalid */
5298/* Opcode VEX.F2.0F 0xd8 - invalid */
5299
5300/* Opcode VEX.0F 0xd9 - invalid */
5301
5302
5303/** Opcode VEX.66.0F 0xd9 - vpsubusw Vx, Hx, Wx */
5304FNIEMOP_DEF(iemOp_vpsubusw_Vx_Hx_Wx)
5305{
5306 IEMOP_MNEMONIC3(VEX_RVM, VPSUBUSW, vpsubusw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5307 IEMOPMEDIAOPTF3_INIT_VARS(vpsubusw);
5308 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5309}
5310
5311
5312/* Opcode VEX.F3.0F 0xd9 - invalid */
5313/* Opcode VEX.F2.0F 0xd9 - invalid */
5314
5315/* Opcode VEX.0F 0xda - invalid */
5316
5317
5318/** Opcode VEX.66.0F 0xda - vpminub Vx, Hx, Wx */
5319FNIEMOP_DEF(iemOp_vpminub_Vx_Hx_Wx)
5320{
5321 IEMOP_MNEMONIC3(VEX_RVM, VPMINUB, vpminub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5322 IEMOPMEDIAOPTF3_INIT_VARS(vpminub);
5323 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5324}
5325
5326
5327/* Opcode VEX.F3.0F 0xda - invalid */
5328/* Opcode VEX.F2.0F 0xda - invalid */
5329
5330/* Opcode VEX.0F 0xdb - invalid */
5331
5332
5333/** Opcode VEX.66.0F 0xdb - vpand Vx, Hx, Wx */
5334FNIEMOP_DEF(iemOp_vpand_Vx_Hx_Wx)
5335{
5336 IEMOP_MNEMONIC3(VEX_RVM, VPAND, vpand, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5337 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
5338 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpand, &g_iemAImpl_vpand_fallback));
5339}
5340
5341
5342/* Opcode VEX.F3.0F 0xdb - invalid */
5343/* Opcode VEX.F2.0F 0xdb - invalid */
5344
5345/* Opcode VEX.0F 0xdc - invalid */
5346
5347
5348/** Opcode VEX.66.0F 0xdc - vpaddusb Vx, Hx, Wx */
5349FNIEMOP_DEF(iemOp_vpaddusb_Vx_Hx_Wx)
5350{
5351 IEMOP_MNEMONIC3(VEX_RVM, VPADDUSB, vpaddusb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5352 IEMOPMEDIAOPTF3_INIT_VARS(vpaddusb);
5353 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5354}
5355
5356
5357/* Opcode VEX.F3.0F 0xdc - invalid */
5358/* Opcode VEX.F2.0F 0xdc - invalid */
5359
5360/* Opcode VEX.0F 0xdd - invalid */
5361
5362
5363/** Opcode VEX.66.0F 0xdd - vpaddusw Vx, Hx, Wx */
5364FNIEMOP_DEF(iemOp_vpaddusw_Vx_Hx_Wx)
5365{
5366 IEMOP_MNEMONIC3(VEX_RVM, VPADDUSW, vpaddusw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5367 IEMOPMEDIAOPTF3_INIT_VARS(vpaddusw);
5368 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5369}
5370
5371
5372/* Opcode VEX.F3.0F 0xdd - invalid */
5373/* Opcode VEX.F2.0F 0xdd - invalid */
5374
5375/* Opcode VEX.0F 0xde - invalid */
5376
5377
5378/** Opcode VEX.66.0F 0xde - vpmaxub Vx, Hx, Wx */
5379FNIEMOP_DEF(iemOp_vpmaxub_Vx_Hx_Wx)
5380{
5381 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUB, vpmaxub, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5382 IEMOPMEDIAOPTF3_INIT_VARS(vpmaxub);
5383 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5384}
5385
5386
5387/* Opcode VEX.F3.0F 0xde - invalid */
5388/* Opcode VEX.F2.0F 0xde - invalid */
5389
5390/* Opcode VEX.0F 0xdf - invalid */
5391
5392
5393/** Opcode VEX.66.0F 0xdf - vpandn Vx, Hx, Wx */
5394FNIEMOP_DEF(iemOp_vpandn_Vx_Hx_Wx)
5395{
5396 IEMOP_MNEMONIC3(VEX_RVM, VPANDN, vpandn, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5397 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
5398 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpandn, &g_iemAImpl_vpandn_fallback));
5399}
5400
5401
5402/* Opcode VEX.F3.0F 0xdf - invalid */
5403/* Opcode VEX.F2.0F 0xdf - invalid */
5404
5405/* Opcode VEX.0F 0xe0 - invalid */
5406
5407
5408/** Opcode VEX.66.0F 0xe0 - vpavgb Vx, Hx, Wx */
5409FNIEMOP_DEF(iemOp_vpavgb_Vx_Hx_Wx)
5410{
5411 IEMOP_MNEMONIC3(VEX_RVM, VPAVGB, vpavgb, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5412 IEMOPMEDIAOPTF3_INIT_VARS(vpavgb);
5413 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5414}
5415
5416
5417/* Opcode VEX.F3.0F 0xe0 - invalid */
5418/* Opcode VEX.F2.0F 0xe0 - invalid */
5419
5420/* Opcode VEX.0F 0xe1 - invalid */
5421/** Opcode VEX.66.0F 0xe1 - vpsraw Vx, Hx, W */
5422FNIEMOP_DEF(iemOp_vpsraw_Vx_Hx_W)
5423{
5424 IEMOP_MNEMONIC3(VEX_RVM, VPSRAW, vpsraw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5425 IEMOPMEDIAOPTF3_INIT_VARS(vpsraw);
5426 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5427}
5428
5429/* Opcode VEX.F3.0F 0xe1 - invalid */
5430/* Opcode VEX.F2.0F 0xe1 - invalid */
5431
5432/* Opcode VEX.0F 0xe2 - invalid */
5433/** Opcode VEX.66.0F 0xe2 - vpsrad Vx, Hx, Wx */
5434FNIEMOP_DEF(iemOp_vpsrad_Vx_Hx_Wx)
5435{
5436 IEMOP_MNEMONIC3(VEX_RVM, VPSRAD, vpsrad, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5437 IEMOPMEDIAOPTF3_INIT_VARS(vpsrad);
5438 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5439}
5440
5441/* Opcode VEX.F3.0F 0xe2 - invalid */
5442/* Opcode VEX.F2.0F 0xe2 - invalid */
5443
5444/* Opcode VEX.0F 0xe3 - invalid */
5445
5446
5447/** Opcode VEX.66.0F 0xe3 - vpavgw Vx, Hx, Wx */
5448FNIEMOP_DEF(iemOp_vpavgw_Vx_Hx_Wx)
5449{
5450 IEMOP_MNEMONIC3(VEX_RVM, VPAVGW, vpavgw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5451 IEMOPMEDIAOPTF3_INIT_VARS(vpavgw);
5452 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5453}
5454
5455
5456/* Opcode VEX.F3.0F 0xe3 - invalid */
5457/* Opcode VEX.F2.0F 0xe3 - invalid */
5458
5459/* Opcode VEX.0F 0xe4 - invalid */
5460
5461
5462/** Opcode VEX.66.0F 0xe4 - vpmulhuw Vx, Hx, Wx */
5463FNIEMOP_DEF(iemOp_vpmulhuw_Vx_Hx_Wx)
5464{
5465 IEMOP_MNEMONIC3(VEX_RVM, VPMULHUW, vpmulhuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5466 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhuw);
5467 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5468}
5469
5470
5471/* Opcode VEX.F3.0F 0xe4 - invalid */
5472/* Opcode VEX.F2.0F 0xe4 - invalid */
5473
5474/* Opcode VEX.0F 0xe5 - invalid */
5475
5476
5477/** Opcode VEX.66.0F 0xe5 - vpmulhw Vx, Hx, Wx */
5478FNIEMOP_DEF(iemOp_vpmulhw_Vx_Hx_Wx)
5479{
5480 IEMOP_MNEMONIC3(VEX_RVM, VPMULHW, vpmulhw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5481 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhw);
5482 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5483}
5484
5485
5486/* Opcode VEX.F3.0F 0xe5 - invalid */
5487/* Opcode VEX.F2.0F 0xe5 - invalid */
5488
5489/* Opcode VEX.0F 0xe6 - invalid */
5490/** Opcode VEX.66.0F 0xe6 - vcvttpd2dq Vx, Wpd */
5491FNIEMOP_STUB(iemOp_vcvttpd2dq_Vx_Wpd);
5492/** Opcode VEX.F3.0F 0xe6 - vcvtdq2pd Vx, Wpd */
5493FNIEMOP_STUB(iemOp_vcvtdq2pd_Vx_Wpd);
5494/** Opcode VEX.F2.0F 0xe6 - vcvtpd2dq Vx, Wpd */
5495FNIEMOP_STUB(iemOp_vcvtpd2dq_Vx_Wpd);
5496
5497
5498/* Opcode VEX.0F 0xe7 - invalid */
5499
5500/**
5501 * @opcode 0xe7
5502 * @opcodesub !11 mr/reg
5503 * @oppfx 0x66
5504 * @opcpuid avx
5505 * @opgroup og_avx_cachect
5506 * @opxcpttype 1
5507 * @optest op1=-1 op2=2 -> op1=2
5508 * @optest op1=0 op2=-42 -> op1=-42
5509 */
5510FNIEMOP_DEF(iemOp_vmovntdq_Mx_Vx)
5511{
5512 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTDQ, vmovntdq, Mx_WO, Vx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
5513 Assert(pVCpu->iem.s.uVexLength <= 1);
5514 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5515 if (IEM_IS_MODRM_MEM_MODE(bRm))
5516 {
5517 if (pVCpu->iem.s.uVexLength == 0)
5518 {
5519 /*
5520 * 128-bit: Memory, register.
5521 */
5522 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5523 IEM_MC_LOCAL(RTUINT128U, uSrc);
5524 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5525
5526 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5527 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5528 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5529 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
5530
5531 IEM_MC_FETCH_YREG_U128(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDQWord*/);
5532 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
5533
5534 IEM_MC_ADVANCE_RIP_AND_FINISH();
5535 IEM_MC_END();
5536 }
5537 else
5538 {
5539 /*
5540 * 256-bit: Memory, register.
5541 */
5542 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5543 IEM_MC_LOCAL(RTUINT256U, uSrc);
5544 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5545
5546 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5547 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5548 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5549 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
5550
5551 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
5552 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
5553
5554 IEM_MC_ADVANCE_RIP_AND_FINISH();
5555 IEM_MC_END();
5556 }
5557 }
5558 /**
5559 * @opdone
5560 * @opmnemonic udvex660fe7reg
5561 * @opcode 0xe7
5562 * @opcodesub 11 mr/reg
5563 * @oppfx 0x66
5564 * @opunused immediate
5565 * @opcpuid avx
5566 * @optest ->
5567 */
5568 else
5569 IEMOP_RAISE_INVALID_OPCODE_RET();
5570}
5571
5572/* Opcode VEX.F3.0F 0xe7 - invalid */
5573/* Opcode VEX.F2.0F 0xe7 - invalid */
5574
5575
5576/* Opcode VEX.0F 0xe8 - invalid */
5577
5578
5579/** Opcode VEX.66.0F 0xe8 - vpsubsb Vx, Hx, Wx */
5580FNIEMOP_DEF(iemOp_vpsubsb_Vx_Hx_Wx)
5581{
5582 IEMOP_MNEMONIC3(VEX_RVM, VPSUBSB, vpsubsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5583 IEMOPMEDIAOPTF3_INIT_VARS(vpsubsb);
5584 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5585}
5586
5587
5588/* Opcode VEX.F3.0F 0xe8 - invalid */
5589/* Opcode VEX.F2.0F 0xe8 - invalid */
5590
5591/* Opcode VEX.0F 0xe9 - invalid */
5592
5593
5594/** Opcode VEX.66.0F 0xe9 - vpsubsw Vx, Hx, Wx */
5595FNIEMOP_DEF(iemOp_vpsubsw_Vx_Hx_Wx)
5596{
5597 IEMOP_MNEMONIC3(VEX_RVM, VPSUBSW, vpsubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5598 IEMOPMEDIAOPTF3_INIT_VARS(vpsubsw);
5599 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5600}
5601
5602
5603/* Opcode VEX.F3.0F 0xe9 - invalid */
5604/* Opcode VEX.F2.0F 0xe9 - invalid */
5605
5606/* Opcode VEX.0F 0xea - invalid */
5607
5608
5609/** Opcode VEX.66.0F 0xea - vpminsw Vx, Hx, Wx */
5610FNIEMOP_DEF(iemOp_vpminsw_Vx_Hx_Wx)
5611{
5612 IEMOP_MNEMONIC3(VEX_RVM, VPMINSW, vpminsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5613 IEMOPMEDIAOPTF3_INIT_VARS(vpminsw);
5614 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5615}
5616
5617
5618/* Opcode VEX.F3.0F 0xea - invalid */
5619/* Opcode VEX.F2.0F 0xea - invalid */
5620
5621/* Opcode VEX.0F 0xeb - invalid */
5622
5623
5624/** Opcode VEX.66.0F 0xeb - vpor Vx, Hx, Wx */
5625FNIEMOP_DEF(iemOp_vpor_Vx_Hx_Wx)
5626{
5627 IEMOP_MNEMONIC3(VEX_RVM, VPOR, vpor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5628 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
5629 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpor, &g_iemAImpl_vpor_fallback));
5630}
5631
5632
5633
5634/* Opcode VEX.F3.0F 0xeb - invalid */
5635/* Opcode VEX.F2.0F 0xeb - invalid */
5636
5637/* Opcode VEX.0F 0xec - invalid */
5638
5639
5640/** Opcode VEX.66.0F 0xec - vpaddsb Vx, Hx, Wx */
5641FNIEMOP_DEF(iemOp_vpaddsb_Vx_Hx_Wx)
5642{
5643 IEMOP_MNEMONIC3(VEX_RVM, VPADDSB, vpaddsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5644 IEMOPMEDIAOPTF3_INIT_VARS(vpaddsb);
5645 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5646}
5647
5648
5649/* Opcode VEX.F3.0F 0xec - invalid */
5650/* Opcode VEX.F2.0F 0xec - invalid */
5651
5652/* Opcode VEX.0F 0xed - invalid */
5653
5654
5655/** Opcode VEX.66.0F 0xed - vpaddsw Vx, Hx, Wx */
5656FNIEMOP_DEF(iemOp_vpaddsw_Vx_Hx_Wx)
5657{
5658 IEMOP_MNEMONIC3(VEX_RVM, VPADDSW, vpaddsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5659 IEMOPMEDIAOPTF3_INIT_VARS(vpaddsw);
5660 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5661}
5662
5663
5664/* Opcode VEX.F3.0F 0xed - invalid */
5665/* Opcode VEX.F2.0F 0xed - invalid */
5666
5667/* Opcode VEX.0F 0xee - invalid */
5668
5669
5670/** Opcode VEX.66.0F 0xee - vpmaxsw Vx, Hx, Wx */
5671FNIEMOP_DEF(iemOp_vpmaxsw_Vx_Hx_Wx)
5672{
5673 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSW, vpmaxsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5674 IEMOPMEDIAOPTF3_INIT_VARS(vpmaxsw);
5675 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5676}
5677
5678
5679/* Opcode VEX.F3.0F 0xee - invalid */
5680/* Opcode VEX.F2.0F 0xee - invalid */
5681
5682
5683/* Opcode VEX.0F 0xef - invalid */
5684
5685
5686/** Opcode VEX.66.0F 0xef - vpxor Vx, Hx, Wx */
5687FNIEMOP_DEF(iemOp_vpxor_Vx_Hx_Wx)
5688{
5689 IEMOP_MNEMONIC3(VEX_RVM, VPXOR, vpxor, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5690 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt,
5691 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &g_iemAImpl_vpxor, &g_iemAImpl_vpxor_fallback));
5692}
5693
5694
5695/* Opcode VEX.F3.0F 0xef - invalid */
5696/* Opcode VEX.F2.0F 0xef - invalid */
5697
5698/* Opcode VEX.0F 0xf0 - invalid */
5699/* Opcode VEX.66.0F 0xf0 - invalid */
5700
5701
5702/** Opcode VEX.F2.0F 0xf0 - vlddqu Vx, Mx */
5703FNIEMOP_DEF(iemOp_vlddqu_Vx_Mx)
5704{
5705 IEMOP_MNEMONIC2(VEX_RM_MEM, VLDDQU, vlddqu, Vx_WO, Mx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
5706 Assert(pVCpu->iem.s.uVexLength <= 1);
5707 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5708 if (IEM_IS_MODRM_REG_MODE(bRm))
5709 {
5710 /*
5711 * Register, register - (not implemented, assuming it raises \#UD).
5712 */
5713 IEMOP_RAISE_INVALID_OPCODE_RET();
5714 }
5715 else if (pVCpu->iem.s.uVexLength == 0)
5716 {
5717 /*
5718 * Register, memory128.
5719 */
5720 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5721 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
5722 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5723
5724 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5725 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5726 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5727 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
5728
5729 IEM_MC_FETCH_MEM_U128_NO_AC(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
5730 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
5731
5732 IEM_MC_ADVANCE_RIP_AND_FINISH();
5733 IEM_MC_END();
5734 }
5735 else
5736 {
5737 /*
5738 * Register, memory256.
5739 */
5740 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5741 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
5742 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
5743
5744 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
5745 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
5746 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5747 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
5748
5749 IEM_MC_FETCH_MEM_U256_NO_AC(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
5750 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
5751
5752 IEM_MC_ADVANCE_RIP_AND_FINISH();
5753 IEM_MC_END();
5754 }
5755}
5756
5757
5758/* Opcode VEX.0F 0xf1 - invalid */
5759/** Opcode VEX.66.0F 0xf1 - vpsllw Vx, Hx, W */
5760FNIEMOP_DEF(iemOp_vpsllw_Vx_Hx_W)
5761{
5762 IEMOP_MNEMONIC3(VEX_RVM, VPSLLW, vpsllw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5763 IEMOPMEDIAOPTF3_INIT_VARS(vpsllw);
5764 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5765}
5766
5767/* Opcode VEX.F2.0F 0xf1 - invalid */
5768
5769/* Opcode VEX.0F 0xf2 - invalid */
5770/** Opcode VEX.66.0F 0xf2 - vpslld Vx, Hx, Wx */
5771FNIEMOP_DEF(iemOp_vpslld_Vx_Hx_Wx)
5772{
5773 IEMOP_MNEMONIC3(VEX_RVM, VPSLLD, vpslld, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5774 IEMOPMEDIAOPTF3_INIT_VARS(vpslld);
5775 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5776}
5777/* Opcode VEX.F2.0F 0xf2 - invalid */
5778
5779/* Opcode VEX.0F 0xf3 - invalid */
5780/** Opcode VEX.66.0F 0xf3 - vpsllq Vx, Hx, Wx */
5781FNIEMOP_DEF(iemOp_vpsllq_Vx_Hx_Wx)
5782{
5783 IEMOP_MNEMONIC3(VEX_RVM, VPSLLQ, vpsllq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
5784 IEMOPMEDIAOPTF3_INIT_VARS(vpsllq);
5785 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5786}
5787/* Opcode VEX.F2.0F 0xf3 - invalid */
5788
5789/* Opcode VEX.0F 0xf4 - invalid */
5790
5791
5792/** Opcode VEX.66.0F 0xf4 - vpmuludq Vx, Hx, W */
5793FNIEMOP_DEF(iemOp_vpmuludq_Vx_Hx_W)
5794{
5795 IEMOP_MNEMONIC3(VEX_RVM, VPMULUDQ, vpmuludq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5796 IEMOPMEDIAOPTF3_INIT_VARS(vpmuludq);
5797 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5798}
5799
5800
5801/* Opcode VEX.F2.0F 0xf4 - invalid */
5802
5803/* Opcode VEX.0F 0xf5 - invalid */
5804
5805
5806/** Opcode VEX.66.0F 0xf5 - vpmaddwd Vx, Hx, Wx */
5807FNIEMOP_DEF(iemOp_vpmaddwd_Vx_Hx_Wx)
5808{
5809 IEMOP_MNEMONIC3(VEX_RVM, VPMADDWD, vpmaddwd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5810 IEMOPMEDIAOPTF3_INIT_VARS(vpmaddwd);
5811 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5812}
5813
5814
5815/* Opcode VEX.F2.0F 0xf5 - invalid */
5816
5817/* Opcode VEX.0F 0xf6 - invalid */
5818
5819
5820/** Opcode VEX.66.0F 0xf6 - vpsadbw Vx, Hx, Wx */
5821FNIEMOP_DEF(iemOp_vpsadbw_Vx_Hx_Wx)
5822{
5823 IEMOP_MNEMONIC3(VEX_RVM, VPSADBW, vpsadbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5824 IEMOPMEDIAOPTF3_INIT_VARS(vpsadbw);
5825 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5826}
5827
5828
5829/* Opcode VEX.F2.0F 0xf6 - invalid */
5830
5831/* Opcode VEX.0F 0xf7 - invalid */
5832
5833
5834/** Opcode VEX.66.0F 0xf7 - vmaskmovdqu Vdq, Udq */
5835FNIEMOP_DEF(iemOp_vmaskmovdqu_Vdq_Udq)
5836{
5837// IEMOP_MNEMONIC2(RM, VMASKMOVDQU, vmaskmovdqu, Vdq, Udq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES); /** @todo */
5838 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5839 if (IEM_IS_MODRM_REG_MODE(bRm))
5840 {
5841 /*
5842 * XMM, XMM, (implicit) [ ER]DI
5843 */
5844 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
5845 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
5846 IEM_MC_LOCAL( uint64_t, u64EffAddr);
5847 IEM_MC_LOCAL( RTUINT128U, u128Mem);
5848 IEM_MC_ARG_LOCAL_REF(PRTUINT128U, pu128Mem, u128Mem, 0);
5849 IEM_MC_ARG( PCRTUINT128U, puSrc, 1);
5850 IEM_MC_ARG( PCRTUINT128U, puMsk, 2);
5851 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
5852 IEM_MC_PREPARE_AVX_USAGE();
5853
5854 IEM_MC_FETCH_GREG_U64(u64EffAddr, X86_GREG_xDI);
5855 IEM_MC_FETCH_MEM_U128(u128Mem, pVCpu->iem.s.iEffSeg, u64EffAddr);
5856 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
5857 IEM_MC_REF_XREG_U128_CONST(puMsk, IEM_GET_MODRM_RM(pVCpu, bRm));
5858 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_maskmovdqu_u128, pu128Mem, puSrc, puMsk);
5859 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, u64EffAddr, u128Mem);
5860
5861 IEM_MC_ADVANCE_RIP_AND_FINISH();
5862 IEM_MC_END();
5863 }
5864 else
5865 {
5866 /* The memory, register encoding is invalid. */
5867 IEMOP_RAISE_INVALID_OPCODE_RET();
5868 }
5869}
5870
5871
5872/* Opcode VEX.F2.0F 0xf7 - invalid */
5873
5874/* Opcode VEX.0F 0xf8 - invalid */
5875
5876
5877/** Opcode VEX.66.0F 0xf8 - vpsubb Vx, Hx, W */
5878FNIEMOP_DEF(iemOp_vpsubb_Vx_Hx_Wx)
5879{
5880 IEMOP_MNEMONIC3(VEX_RVM, VPSUBB, vpsubb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5881 IEMOPMEDIAOPTF3_INIT_VARS( vpsubb);
5882 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5883}
5884
5885
5886/* Opcode VEX.F2.0F 0xf8 - invalid */
5887
5888/* Opcode VEX.0F 0xf9 - invalid */
5889
5890
5891/** Opcode VEX.66.0F 0xf9 - vpsubw Vx, Hx, Wx */
5892FNIEMOP_DEF(iemOp_vpsubw_Vx_Hx_Wx)
5893{
5894 IEMOP_MNEMONIC3(VEX_RVM, VPSUBW, vpsubw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5895 IEMOPMEDIAOPTF3_INIT_VARS( vpsubw);
5896 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5897}
5898
5899
5900/* Opcode VEX.F2.0F 0xf9 - invalid */
5901
5902/* Opcode VEX.0F 0xfa - invalid */
5903
5904
5905/** Opcode VEX.66.0F 0xfa - vpsubd Vx, Hx, Wx */
5906FNIEMOP_DEF(iemOp_vpsubd_Vx_Hx_Wx)
5907{
5908 IEMOP_MNEMONIC3(VEX_RVM, VPSUBD, vpsubd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5909 IEMOPMEDIAOPTF3_INIT_VARS( vpsubd);
5910 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5911}
5912
5913
5914/* Opcode VEX.F2.0F 0xfa - invalid */
5915
5916/* Opcode VEX.0F 0xfb - invalid */
5917
5918
5919/** Opcode VEX.66.0F 0xfb - vpsubq Vx, Hx, W */
5920FNIEMOP_DEF(iemOp_vpsubq_Vx_Hx_Wx)
5921{
5922 IEMOP_MNEMONIC3(VEX_RVM, VPSUBQ, vpsubq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5923 IEMOPMEDIAOPTF3_INIT_VARS( vpsubq);
5924 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5925}
5926
5927
5928/* Opcode VEX.F2.0F 0xfb - invalid */
5929
5930/* Opcode VEX.0F 0xfc - invalid */
5931
5932
5933/** Opcode VEX.66.0F 0xfc - vpaddb Vx, Hx, Wx */
5934FNIEMOP_DEF(iemOp_vpaddb_Vx_Hx_Wx)
5935{
5936 IEMOP_MNEMONIC3(VEX_RVM, VPADDB, vpaddb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5937 IEMOPMEDIAOPTF3_INIT_VARS( vpaddb);
5938 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5939}
5940
5941
5942/* Opcode VEX.F2.0F 0xfc - invalid */
5943
5944/* Opcode VEX.0F 0xfd - invalid */
5945
5946
5947/** Opcode VEX.66.0F 0xfd - vpaddw Vx, Hx, Wx */
5948FNIEMOP_DEF(iemOp_vpaddw_Vx_Hx_Wx)
5949{
5950 IEMOP_MNEMONIC3(VEX_RVM, VPADDW, vpaddw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5951 IEMOPMEDIAOPTF3_INIT_VARS( vpaddw);
5952 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5953}
5954
5955
5956/* Opcode VEX.F2.0F 0xfd - invalid */
5957
5958/* Opcode VEX.0F 0xfe - invalid */
5959
5960
5961/** Opcode VEX.66.0F 0xfe - vpaddd Vx, Hx, W */
5962FNIEMOP_DEF(iemOp_vpaddd_Vx_Hx_Wx)
5963{
5964 IEMOP_MNEMONIC3(VEX_RVM, VPADDD, vpaddd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
5965 IEMOPMEDIAOPTF3_INIT_VARS( vpaddd);
5966 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
5967}
5968
5969
5970/* Opcode VEX.F2.0F 0xfe - invalid */
5971
5972
5973/** Opcode **** 0x0f 0xff - UD0 */
5974FNIEMOP_DEF(iemOp_vud0)
5975{
5976/** @todo testcase: vud0 */
5977 IEMOP_MNEMONIC(vud0, "vud0");
5978 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
5979 {
5980 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
5981 if (IEM_IS_MODRM_MEM_MODE(bRm))
5982 IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(bRm);
5983 }
5984 IEMOP_HLP_DONE_DECODING();
5985 IEMOP_RAISE_INVALID_OPCODE_RET();
5986}
5987
5988
5989
5990/**
5991 * VEX opcode map \#1.
5992 *
5993 * @sa g_apfnTwoByteMap
5994 */
5995const PFNIEMOP g_apfnVexMap1[] =
5996{
5997 /* no prefix, 066h prefix f3h prefix, f2h prefix */
5998 /* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRM),
5999 /* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRM),
6000 /* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRM),
6001 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRM),
6002 /* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRM),
6003 /* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRM),
6004 /* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRM),
6005 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRM),
6006 /* 0x08 */ IEMOP_X4(iemOp_InvalidNeedRM),
6007 /* 0x09 */ IEMOP_X4(iemOp_InvalidNeedRM),
6008 /* 0x0a */ IEMOP_X4(iemOp_InvalidNeedRM),
6009 /* 0x0b */ IEMOP_X4(iemOp_vud2), /* ?? */
6010 /* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
6011 /* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
6012 /* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
6013 /* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
6014
6015 /* 0x10 */ iemOp_vmovups_Vps_Wps, iemOp_vmovupd_Vpd_Wpd, iemOp_vmovss_Vss_Hss_Wss, iemOp_vmovsd_Vsd_Hsd_Wsd,
6016 /* 0x11 */ iemOp_vmovups_Wps_Vps, iemOp_vmovupd_Wpd_Vpd, iemOp_vmovss_Wss_Hss_Vss, iemOp_vmovsd_Wsd_Hsd_Vsd,
6017 /* 0x12 */ iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx, iemOp_vmovddup_Vx_Wx,
6018 /* 0x13 */ iemOp_vmovlps_Mq_Vq, iemOp_vmovlpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6019 /* 0x14 */ iemOp_vunpcklps_Vx_Hx_Wx, iemOp_vunpcklpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6020 /* 0x15 */ iemOp_vunpckhps_Vx_Hx_Wx, iemOp_vunpckhpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6021 /* 0x16 */ iemOp_vmovhps_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq, iemOp_vmovhpd_Vdq_Hq_Mq, iemOp_vmovshdup_Vx_Wx, iemOp_InvalidNeedRM,
6022 /* 0x17 */ iemOp_vmovhps_Mq_Vq, iemOp_vmovhpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6023 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
6024 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
6025 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
6026 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
6027 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRM),
6028 /* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRM),
6029 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRM),
6030 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
6031
6032 /* 0x20 */ IEMOP_X4(iemOp_InvalidNeedRM),
6033 /* 0x21 */ IEMOP_X4(iemOp_InvalidNeedRM),
6034 /* 0x22 */ IEMOP_X4(iemOp_InvalidNeedRM),
6035 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRM),
6036 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRM),
6037 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRM),
6038 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
6039 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
6040 /* 0x28 */ iemOp_vmovaps_Vps_Wps, iemOp_vmovapd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6041 /* 0x29 */ iemOp_vmovaps_Wps_Vps, iemOp_vmovapd_Wpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6042 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtsi2ss_Vss_Hss_Ey, iemOp_vcvtsi2sd_Vsd_Hsd_Ey,
6043 /* 0x2b */ iemOp_vmovntps_Mps_Vps, iemOp_vmovntpd_Mpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6044 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvttss2si_Gy_Wss, iemOp_vcvttsd2si_Gy_Wsd,
6045 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtss2si_Gy_Wss, iemOp_vcvtsd2si_Gy_Wsd,
6046 /* 0x2e */ iemOp_vucomiss_Vss_Wss, iemOp_vucomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6047 /* 0x2f */ iemOp_vcomiss_Vss_Wss, iemOp_vcomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6048
6049 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRM),
6050 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRM),
6051 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRM),
6052 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRM),
6053 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRM),
6054 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRM),
6055 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
6056 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRM),
6057 /* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
6058 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
6059 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
6060 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
6061 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
6062 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
6063 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
6064 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
6065
6066 /* 0x40 */ IEMOP_X4(iemOp_InvalidNeedRM),
6067 /* 0x41 */ IEMOP_X4(iemOp_InvalidNeedRM),
6068 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
6069 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
6070 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
6071 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
6072 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
6073 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
6074 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
6075 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
6076 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
6077 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
6078 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
6079 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
6080 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
6081 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
6082
6083 /* 0x50 */ iemOp_vmovmskps_Gy_Ups, iemOp_vmovmskpd_Gy_Upd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6084 /* 0x51 */ iemOp_vsqrtps_Vps_Wps, iemOp_vsqrtpd_Vpd_Wpd, iemOp_vsqrtss_Vss_Hss_Wss, iemOp_vsqrtsd_Vsd_Hsd_Wsd,
6085 /* 0x52 */ iemOp_vrsqrtps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrsqrtss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
6086 /* 0x53 */ iemOp_vrcpps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrcpss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
6087 /* 0x54 */ iemOp_vandps_Vps_Hps_Wps, iemOp_vandpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6088 /* 0x55 */ iemOp_vandnps_Vps_Hps_Wps, iemOp_vandnpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6089 /* 0x56 */ iemOp_vorps_Vps_Hps_Wps, iemOp_vorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6090 /* 0x57 */ iemOp_vxorps_Vps_Hps_Wps, iemOp_vxorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6091 /* 0x58 */ iemOp_vaddps_Vps_Hps_Wps, iemOp_vaddpd_Vpd_Hpd_Wpd, iemOp_vaddss_Vss_Hss_Wss, iemOp_vaddsd_Vsd_Hsd_Wsd,
6092 /* 0x59 */ iemOp_vmulps_Vps_Hps_Wps, iemOp_vmulpd_Vpd_Hpd_Wpd, iemOp_vmulss_Vss_Hss_Wss, iemOp_vmulsd_Vsd_Hsd_Wsd,
6093 /* 0x5a */ iemOp_vcvtps2pd_Vpd_Wps, iemOp_vcvtpd2ps_Vps_Wpd, iemOp_vcvtss2sd_Vsd_Hx_Wss, iemOp_vcvtsd2ss_Vss_Hx_Wsd,
6094 /* 0x5b */ iemOp_vcvtdq2ps_Vps_Wdq, iemOp_vcvtps2dq_Vdq_Wps, iemOp_vcvttps2dq_Vdq_Wps, iemOp_InvalidNeedRM,
6095 /* 0x5c */ iemOp_vsubps_Vps_Hps_Wps, iemOp_vsubpd_Vpd_Hpd_Wpd, iemOp_vsubss_Vss_Hss_Wss, iemOp_vsubsd_Vsd_Hsd_Wsd,
6096 /* 0x5d */ iemOp_vminps_Vps_Hps_Wps, iemOp_vminpd_Vpd_Hpd_Wpd, iemOp_vminss_Vss_Hss_Wss, iemOp_vminsd_Vsd_Hsd_Wsd,
6097 /* 0x5e */ iemOp_vdivps_Vps_Hps_Wps, iemOp_vdivpd_Vpd_Hpd_Wpd, iemOp_vdivss_Vss_Hss_Wss, iemOp_vdivsd_Vsd_Hsd_Wsd,
6098 /* 0x5f */ iemOp_vmaxps_Vps_Hps_Wps, iemOp_vmaxpd_Vpd_Hpd_Wpd, iemOp_vmaxss_Vss_Hss_Wss, iemOp_vmaxsd_Vsd_Hsd_Wsd,
6099
6100 /* 0x60 */ iemOp_InvalidNeedRM, iemOp_vpunpcklbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6101 /* 0x61 */ iemOp_InvalidNeedRM, iemOp_vpunpcklwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6102 /* 0x62 */ iemOp_InvalidNeedRM, iemOp_vpunpckldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6103 /* 0x63 */ iemOp_InvalidNeedRM, iemOp_vpacksswb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6104 /* 0x64 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6105 /* 0x65 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6106 /* 0x66 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6107 /* 0x67 */ iemOp_InvalidNeedRM, iemOp_vpackuswb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6108 /* 0x68 */ iemOp_InvalidNeedRM, iemOp_vpunpckhbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6109 /* 0x69 */ iemOp_InvalidNeedRM, iemOp_vpunpckhwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6110 /* 0x6a */ iemOp_InvalidNeedRM, iemOp_vpunpckhdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6111 /* 0x6b */ iemOp_InvalidNeedRM, iemOp_vpackssdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6112 /* 0x6c */ iemOp_InvalidNeedRM, iemOp_vpunpcklqdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6113 /* 0x6d */ iemOp_InvalidNeedRM, iemOp_vpunpckhqdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6114 /* 0x6e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Vy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6115 /* 0x6f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Vx_Wx, iemOp_vmovdqu_Vx_Wx, iemOp_InvalidNeedRM,
6116
6117 /* 0x70 */ iemOp_InvalidNeedRM, iemOp_vpshufd_Vx_Wx_Ib, iemOp_vpshufhw_Vx_Wx_Ib, iemOp_vpshuflw_Vx_Wx_Ib,
6118 /* 0x71 */ iemOp_InvalidNeedRM, iemOp_VGrp12, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6119 /* 0x72 */ iemOp_InvalidNeedRM, iemOp_VGrp13, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6120 /* 0x73 */ iemOp_InvalidNeedRM, iemOp_VGrp14, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6121 /* 0x74 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6122 /* 0x75 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6123 /* 0x76 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6124 /* 0x77 */ iemOp_vzeroupperv__vzeroallv, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6125 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
6126 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
6127 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
6128 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
6129 /* 0x7c */ iemOp_InvalidNeedRM, iemOp_vhaddpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhaddps_Vps_Hps_Wps,
6130 /* 0x7d */ iemOp_InvalidNeedRM, iemOp_vhsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhsubps_Vps_Hps_Wps,
6131 /* 0x7e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Ey_Vy, iemOp_vmovq_Vq_Wq, iemOp_InvalidNeedRM,
6132 /* 0x7f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Wx_Vx, iemOp_vmovdqu_Wx_Vx, iemOp_InvalidNeedRM,
6133
6134 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
6135 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
6136 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
6137 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
6138 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
6139 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
6140 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
6141 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
6142 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
6143 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
6144 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
6145 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
6146 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
6147 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
6148 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
6149 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
6150
6151 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
6152 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
6153 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
6154 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
6155 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
6156 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
6157 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
6158 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
6159 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
6160 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
6161 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
6162 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
6163 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
6164 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
6165 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
6166 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
6167
6168 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
6169 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
6170 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
6171 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
6172 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
6173 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
6174 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
6175 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
6176 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
6177 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
6178 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
6179 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
6180 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
6181 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
6182 /* 0xae */ IEMOP_X4(iemOp_VGrp15),
6183 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
6184
6185 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
6186 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
6187 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
6188 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
6189 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
6190 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
6191 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
6192 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
6193 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
6194 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
6195 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
6196 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
6197 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
6198 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
6199 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
6200 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
6201
6202 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
6203 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
6204 /* 0xc2 */ iemOp_vcmpps_Vps_Hps_Wps_Ib, iemOp_vcmppd_Vpd_Hpd_Wpd_Ib, iemOp_vcmpss_Vss_Hss_Wss_Ib, iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib,
6205 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
6206 /* 0xc4 */ iemOp_InvalidNeedRM, iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
6207 /* 0xc5 */ iemOp_InvalidNeedRM, iemOp_vpextrw_Gd_Udq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
6208 /* 0xc6 */ iemOp_vshufps_Vps_Hps_Wps_Ib, iemOp_vshufpd_Vpd_Hpd_Wpd_Ib, iemOp_InvalidNeedRMImm8,iemOp_InvalidNeedRMImm8,
6209 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
6210 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
6211 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
6212 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
6213 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
6214 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
6215 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
6216 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
6217 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
6218
6219 /* 0xd0 */ iemOp_InvalidNeedRM, iemOp_vaddsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vaddsubps_Vps_Hps_Wps,
6220 /* 0xd1 */ iemOp_InvalidNeedRM, iemOp_vpsrlw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6221 /* 0xd2 */ iemOp_InvalidNeedRM, iemOp_vpsrld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6222 /* 0xd3 */ iemOp_InvalidNeedRM, iemOp_vpsrlq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6223 /* 0xd4 */ iemOp_InvalidNeedRM, iemOp_vpaddq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6224 /* 0xd5 */ iemOp_InvalidNeedRM, iemOp_vpmullw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6225 /* 0xd6 */ iemOp_InvalidNeedRM, iemOp_vmovq_Wq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6226 /* 0xd7 */ iemOp_InvalidNeedRM, iemOp_vpmovmskb_Gd_Ux, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6227 /* 0xd8 */ iemOp_InvalidNeedRM, iemOp_vpsubusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6228 /* 0xd9 */ iemOp_InvalidNeedRM, iemOp_vpsubusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6229 /* 0xda */ iemOp_InvalidNeedRM, iemOp_vpminub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6230 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vpand_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6231 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vpaddusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6232 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vpaddusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6233 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vpmaxub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6234 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vpandn_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6235
6236 /* 0xe0 */ iemOp_InvalidNeedRM, iemOp_vpavgb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6237 /* 0xe1 */ iemOp_InvalidNeedRM, iemOp_vpsraw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6238 /* 0xe2 */ iemOp_InvalidNeedRM, iemOp_vpsrad_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6239 /* 0xe3 */ iemOp_InvalidNeedRM, iemOp_vpavgw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6240 /* 0xe4 */ iemOp_InvalidNeedRM, iemOp_vpmulhuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6241 /* 0xe5 */ iemOp_InvalidNeedRM, iemOp_vpmulhw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6242 /* 0xe6 */ iemOp_InvalidNeedRM, iemOp_vcvttpd2dq_Vx_Wpd, iemOp_vcvtdq2pd_Vx_Wpd, iemOp_vcvtpd2dq_Vx_Wpd,
6243 /* 0xe7 */ iemOp_InvalidNeedRM, iemOp_vmovntdq_Mx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6244 /* 0xe8 */ iemOp_InvalidNeedRM, iemOp_vpsubsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6245 /* 0xe9 */ iemOp_InvalidNeedRM, iemOp_vpsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6246 /* 0xea */ iemOp_InvalidNeedRM, iemOp_vpminsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6247 /* 0xeb */ iemOp_InvalidNeedRM, iemOp_vpor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6248 /* 0xec */ iemOp_InvalidNeedRM, iemOp_vpaddsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6249 /* 0xed */ iemOp_InvalidNeedRM, iemOp_vpaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6250 /* 0xee */ iemOp_InvalidNeedRM, iemOp_vpmaxsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6251 /* 0xef */ iemOp_InvalidNeedRM, iemOp_vpxor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6252
6253 /* 0xf0 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vlddqu_Vx_Mx,
6254 /* 0xf1 */ iemOp_InvalidNeedRM, iemOp_vpsllw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6255 /* 0xf2 */ iemOp_InvalidNeedRM, iemOp_vpslld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6256 /* 0xf3 */ iemOp_InvalidNeedRM, iemOp_vpsllq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6257 /* 0xf4 */ iemOp_InvalidNeedRM, iemOp_vpmuludq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6258 /* 0xf5 */ iemOp_InvalidNeedRM, iemOp_vpmaddwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6259 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_vpsadbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6260 /* 0xf7 */ iemOp_InvalidNeedRM, iemOp_vmaskmovdqu_Vdq_Udq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6261 /* 0xf8 */ iemOp_InvalidNeedRM, iemOp_vpsubb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6262 /* 0xf9 */ iemOp_InvalidNeedRM, iemOp_vpsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6263 /* 0xfa */ iemOp_InvalidNeedRM, iemOp_vpsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6264 /* 0xfb */ iemOp_InvalidNeedRM, iemOp_vpsubq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6265 /* 0xfc */ iemOp_InvalidNeedRM, iemOp_vpaddb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6266 /* 0xfd */ iemOp_InvalidNeedRM, iemOp_vpaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6267 /* 0xfe */ iemOp_InvalidNeedRM, iemOp_vpaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
6268 /* 0xff */ IEMOP_X4(iemOp_vud0) /* ?? */
6269};
6270AssertCompile(RT_ELEMENTS(g_apfnVexMap1) == 1024);
6271/** @} */
6272
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