IEMAllInstVexMap2.cpp.h@ 103836

Last change on this file since 103836 was 103735, checked in by vboxsync, 9 months ago
VMM/IEM: Implement vpsrlv[dq], vpsravd, vpsllv[dq] instruction dispatch & emulation, bugref:9898
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1	/* $Id: IEMAllInstVexMap2.cpp.h 103735 2024-03-08 05:15:24Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation.
4	*
5	* @remarks IEMAllInstThree0f38.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
11	*
12	* This file is part of VirtualBox base platform packages, as
13	* available from https://www.virtualbox.org.
14	*
15	* This program is free software; you can redistribute it and/or
16	* modify it under the terms of the GNU General Public License
17	* as published by the Free Software Foundation, in version 3 of the
18	* License.
19	*
20	* This program is distributed in the hope that it will be useful, but
21	* WITHOUT ANY WARRANTY; without even the implied warranty of
22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23	* General Public License for more details.
24	*
25	* You should have received a copy of the GNU General Public License
26	* along with this program; if not, see <https://www.gnu.org/licenses>.
27	*
28	* SPDX-License-Identifier: GPL-3.0-only
29	*/
30
31
32	/** @name VEX Opcode Map 2
33	* @{
34	*/
35
36	/* Opcode VEX.0F38 0x00 - invalid. */
37
38
39	/** Opcode VEX.66.0F38 0x00. */
40	FNIEMOP_DEF(iemOp_vpshufb_Vx_Hx_Wx)
41	{
42	IEMOP_MNEMONIC3(VEX_RVM, VPSHUFB, vpshufb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
43	IEMOPMEDIAF3_INIT_VARS(vpshufb);
44	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
45	}
46
47
48	/* Opcode VEX.0F38 0x01 - invalid. */
49
50
51	/** Opcode VEX.66.0F38 0x01. */
52	FNIEMOP_DEF(iemOp_vphaddw_Vx_Hx_Wx)
53	{
54	IEMOP_MNEMONIC3(VEX_RVM, VPHADDW, vphaddw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
55	IEMOPMEDIAOPTF3_INIT_VARS(vphaddw);
56	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
57	}
58
59
60	/* Opcode VEX.0F38 0x02 - invalid. */
61
62
63	/** Opcode VEX.66.0F38 0x02. */
64	FNIEMOP_DEF(iemOp_vphaddd_Vx_Hx_Wx)
65	{
66	IEMOP_MNEMONIC3(VEX_RVM, VPHADDD, vphaddd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
67	IEMOPMEDIAOPTF3_INIT_VARS(vphaddd);
68	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
69	}
70
71
72	/* Opcode VEX.0F38 0x03 - invalid. */
73
74
75	/** Opcode VEX.66.0F38 0x03. */
76	FNIEMOP_DEF(iemOp_vphaddsw_Vx_Hx_Wx)
77	{
78	IEMOP_MNEMONIC3(VEX_RVM, VPHADDSW, vphaddsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
79	IEMOPMEDIAOPTF3_INIT_VARS(vphaddsw);
80	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
81	}
82
83
84	/* Opcode VEX.0F38 0x04 - invalid. */
85
86
87	/** Opcode VEX.66.0F38 0x04. */
88	FNIEMOP_DEF(iemOp_vpmaddubsw_Vx_Hx_Wx)
89	{
90	IEMOP_MNEMONIC3(VEX_RVM, VPMADDUBSW, vpmaddubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
91	IEMOPMEDIAOPTF3_INIT_VARS(vpmaddubsw);
92	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
93	}
94
95
96	/* Opcode VEX.0F38 0x05 - invalid. */
97
98
99	/** Opcode VEX.66.0F38 0x05. */
100	FNIEMOP_DEF(iemOp_vphsubw_Vx_Hx_Wx)
101	{
102	IEMOP_MNEMONIC3(VEX_RVM, VPHSUBW, vphsubw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
103	IEMOPMEDIAOPTF3_INIT_VARS(vphsubw);
104	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
105	}
106
107
108	/* Opcode VEX.0F38 0x06 - invalid. */
109
110
111	/** Opcode VEX.66.0F38 0x06. */
112	FNIEMOP_DEF(iemOp_vphsubd_Vx_Hx_Wx)
113	{
114	IEMOP_MNEMONIC3(VEX_RVM, VPHSUBD, vphsubd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
115	IEMOPMEDIAOPTF3_INIT_VARS(vphsubd);
116	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
117	}
118
119
120	/* Opcode VEX.0F38 0x07 - invalid. */
121
122
123	/** Opcode VEX.66.0F38 0x07. */
124	FNIEMOP_DEF(iemOp_vphsubsw_Vx_Hx_Wx)
125	{
126	IEMOP_MNEMONIC3(VEX_RVM, VPHSUBSW, vphsubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
127	IEMOPMEDIAOPTF3_INIT_VARS(vphsubsw);
128	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
129	}
130
131
132	/* Opcode VEX.0F38 0x08 - invalid. */
133
134
135	/** Opcode VEX.66.0F38 0x08. */
136	FNIEMOP_DEF(iemOp_vpsignb_Vx_Hx_Wx)
137	{
138	IEMOP_MNEMONIC3(VEX_RVM, VPSIGNB, vpsignb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
139	IEMOPMEDIAOPTF3_INIT_VARS(vpsignb);
140	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
141	}
142
143
144	/* Opcode VEX.0F38 0x09 - invalid. */
145
146
147	/** Opcode VEX.66.0F38 0x09. */
148	FNIEMOP_DEF(iemOp_vpsignw_Vx_Hx_Wx)
149	{
150	IEMOP_MNEMONIC3(VEX_RVM, VPSIGNW, vpsignw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
151	IEMOPMEDIAOPTF3_INIT_VARS(vpsignw);
152	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
153	}
154
155
156	/* Opcode VEX.0F38 0x0a - invalid. */
157
158
159	/** Opcode VEX.66.0F38 0x0a. */
160	FNIEMOP_DEF(iemOp_vpsignd_Vx_Hx_Wx)
161	{
162	IEMOP_MNEMONIC3(VEX_RVM, VPSIGND, vpsignd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
163	IEMOPMEDIAOPTF3_INIT_VARS(vpsignd);
164	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
165	}
166
167
168	/* Opcode VEX.0F38 0x0b - invalid. */
169
170
171	/** Opcode VEX.66.0F38 0x0b. */
172	FNIEMOP_DEF(iemOp_vpmulhrsw_Vx_Hx_Wx)
173	{
174	IEMOP_MNEMONIC3(VEX_RVM, VPMULHRSW, vpmulhrsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
175	IEMOPMEDIAOPTF3_INIT_VARS(vpmulhrsw);
176	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
177	}
178
179
180	/* Opcode VEX.0F38 0x0c - invalid. */
181
182
183	/** Opcode VEX.66.0F38 0x0c.
184	* AVX,AVX */
185	FNIEMOP_DEF(iemOp_vpermilps_Vx_Hx_Wx)
186	{
187	IEMOP_MNEMONIC3(VEX_RVM, VPERMILPS, vpermilps, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
188	IEMOPMEDIAOPTF3_INIT_VARS(vpermilps);
189	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
190	}
191
192
193	/* Opcode VEX.0F38 0x0d - invalid. */
194
195
196	/** Opcode VEX.66.0F38 0x0d.
197	* AVX,AVX */
198	FNIEMOP_DEF(iemOp_vpermilpd_Vx_Hx_Wx)
199	{
200	IEMOP_MNEMONIC3(VEX_RVM, VPERMILPD, vpermilpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
201	IEMOPMEDIAOPTF3_INIT_VARS(vpermilpd);
202	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
203	}
204
205
206	/* Opcode VEX.0F38 0x0e - invalid. */
207	/** Opcode VEX.66.0F38 0x0e. */
208	FNIEMOP_STUB(iemOp_vtestps_Vx_Wx);
209	/* Opcode VEX.0F38 0x0f - invalid. */
210	/** Opcode VEX.66.0F38 0x0f. */
211	FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx);
212
213
214	/* Opcode VEX.0F38 0x10 - invalid */
215	/* Opcode VEX.66.0F38 0x10 - invalid (legacy only). */
216	/* Opcode VEX.0F38 0x11 - invalid */
217	/* Opcode VEX.66.0F38 0x11 - invalid */
218	/* Opcode VEX.0F38 0x12 - invalid */
219	/* Opcode VEX.66.0F38 0x12 - invalid */
220	/* Opcode VEX.0F38 0x13 - invalid */
221	/* Opcode VEX.66.0F38 0x13 - invalid (vex only). */
222	/* Opcode VEX.0F38 0x14 - invalid */
223	/* Opcode VEX.66.0F38 0x14 - invalid (legacy only). */
224	/* Opcode VEX.0F38 0x15 - invalid */
225	/* Opcode VEX.66.0F38 0x15 - invalid (legacy only). */
226	/* Opcode VEX.0F38 0x16 - invalid */
227	/** Opcode VEX.66.0F38 0x16. */
228	FNIEMOP_STUB(iemOp_vpermps_Vqq_Hqq_Wqq);
229	/* Opcode VEX.0F38 0x17 - invalid */
230
231
232	/**
233	* @opcode 0x17
234	* @oppfx 0x66
235	* @opflmodify cf,pf,af,zf,sf,of
236	* @opflclear pf,af,sf,of
237	*/
238	FNIEMOP_DEF(iemOp_vptest_Vx_Wx)
239	{
240	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
241	if (IEM_IS_MODRM_REG_MODE(bRm))
242	{
243	/*
244	* Register, register.
245	*/
246	if (pVCpu->iem.s.uVexLength)
247	{
248	IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
249	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
250	IEM_MC_LOCAL(RTUINT256U, uSrc1);
251	IEM_MC_LOCAL(RTUINT256U, uSrc2);
252	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
253	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
254	IEM_MC_ARG(uint32_t *, pEFlags, 2);
255	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
256	IEM_MC_PREPARE_AVX_USAGE();
257	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
258	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
259	IEM_MC_REF_EFLAGS(pEFlags);
260	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
261	puSrc1, puSrc2, pEFlags);
262	IEM_MC_ADVANCE_RIP_AND_FINISH();
263	IEM_MC_END();
264	}
265	else
266	{
267	IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
268	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
269	IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
270	IEM_MC_ARG(PCRTUINT128U, puSrc2, 1);
271	IEM_MC_ARG(uint32_t *, pEFlags, 2);
272	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
273	IEM_MC_PREPARE_AVX_USAGE();
274	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
275	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
276	IEM_MC_REF_EFLAGS(pEFlags);
277	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
278	IEM_MC_ADVANCE_RIP_AND_FINISH();
279	IEM_MC_END();
280	}
281	}
282	else
283	{
284	/*
285	* Register, memory.
286	*/
287	if (pVCpu->iem.s.uVexLength)
288	{
289	IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
290	IEM_MC_LOCAL(RTUINT256U, uSrc1);
291	IEM_MC_LOCAL(RTUINT256U, uSrc2);
292	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
293	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
294	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
295	IEM_MC_ARG(uint32_t *, pEFlags, 2);
296
297	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
298	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
299	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
300	IEM_MC_PREPARE_AVX_USAGE();
301
302	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
303	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
304	IEM_MC_REF_EFLAGS(pEFlags);
305	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
306	puSrc1, puSrc2, pEFlags);
307
308	IEM_MC_ADVANCE_RIP_AND_FINISH();
309	IEM_MC_END();
310	}
311	else
312	{
313	IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
314	IEM_MC_LOCAL(RTUINT128U, uSrc2);
315	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
316	IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
317	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1);
318	IEM_MC_ARG(uint32_t *, pEFlags, 2);
319
320	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
321	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
322	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
323	IEM_MC_PREPARE_AVX_USAGE();
324
325	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
326	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
327	IEM_MC_REF_EFLAGS(pEFlags);
328	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
329
330	IEM_MC_ADVANCE_RIP_AND_FINISH();
331	IEM_MC_END();
332	}
333	}
334	}
335
336
337	/* Opcode VEX.0F38 0x18 - invalid */
338
339
340	/** Opcode VEX.66.0F38 0x18. */
341	FNIEMOP_DEF(iemOp_vbroadcastss_Vx_Wd)
342	{
343	IEMOP_MNEMONIC2(VEX_RM, VBROADCASTSS, vbroadcastss, Vx, Wx, DISOPTYPE_HARMLESS, 0);
344	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
345	if (IEM_IS_MODRM_REG_MODE(bRm))
346	{
347	/*
348	* Register, register.
349	*/
350	if (pVCpu->iem.s.uVexLength)
351	{
352	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
353	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
354	IEM_MC_LOCAL(uint32_t, uSrc);
355
356	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
357	IEM_MC_PREPARE_AVX_USAGE();
358
359	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
360	IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
361
362	IEM_MC_ADVANCE_RIP_AND_FINISH();
363	IEM_MC_END();
364	}
365	else
366	{
367	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
368	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
369	IEM_MC_LOCAL(uint32_t, uSrc);
370
371	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
372	IEM_MC_PREPARE_AVX_USAGE();
373	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
374	IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
375
376	IEM_MC_ADVANCE_RIP_AND_FINISH();
377	IEM_MC_END();
378	}
379	}
380	else
381	{
382	/*
383	* Register, memory.
384	*/
385	if (pVCpu->iem.s.uVexLength)
386	{
387	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
388	IEM_MC_LOCAL(uint32_t, uSrc);
389	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
390
391	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
392	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
393	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
394	IEM_MC_PREPARE_AVX_USAGE();
395
396	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
397	IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
398
399	IEM_MC_ADVANCE_RIP_AND_FINISH();
400	IEM_MC_END();
401	}
402	else
403	{
404	IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
405	IEM_MC_LOCAL(uint32_t, uSrc);
406	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
407
408	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
409	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
410	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
411	IEM_MC_PREPARE_AVX_USAGE();
412
413	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
414	IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
415
416	IEM_MC_ADVANCE_RIP_AND_FINISH();
417	IEM_MC_END();
418	}
419	}
420	}
421
422
423	/* Opcode VEX.0F38 0x19 - invalid */
424
425
426	/** Opcode VEX.66.0F38 0x19. */
427	FNIEMOP_DEF(iemOp_vbroadcastsd_Vqq_Wq)
428	{
429	IEMOP_MNEMONIC2(VEX_RM, VBROADCASTSD, vbroadcastsd, Vx, Wx, DISOPTYPE_HARMLESS, 0);
430	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
431	if (IEM_IS_MODRM_REG_MODE(bRm))
432	{
433	/*
434	* Register, register.
435	*/
436	if (pVCpu->iem.s.uVexLength)
437	{
438	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
439	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
440	IEM_MC_LOCAL(uint64_t, uSrc);
441
442	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
443	IEM_MC_PREPARE_AVX_USAGE();
444
445	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
446	IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
447
448	IEM_MC_ADVANCE_RIP_AND_FINISH();
449	IEM_MC_END();
450	}
451	else
452	{
453	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
454	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
455	IEM_MC_LOCAL(uint64_t, uSrc);
456
457	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
458	IEM_MC_PREPARE_AVX_USAGE();
459	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
460	IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
461
462	IEM_MC_ADVANCE_RIP_AND_FINISH();
463	IEM_MC_END();
464	}
465	}
466	else
467	{
468	/*
469	* Register, memory.
470	*/
471	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
472	IEM_MC_LOCAL(uint64_t, uSrc);
473	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
474
475	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
476	IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx);
477	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
478	IEM_MC_PREPARE_AVX_USAGE();
479
480	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
481	IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
482
483	IEM_MC_ADVANCE_RIP_AND_FINISH();
484	IEM_MC_END();
485	}
486	}
487
488
489	/* Opcode VEX.0F38 0x1a - invalid */
490
491
492	/** Opcode VEX.66.0F38 0x1a. */
493	FNIEMOP_DEF(iemOp_vbroadcastf128_Vqq_Mdq)
494	{
495	IEMOP_MNEMONIC2(VEX_RM, VBROADCASTF128, vbroadcastf128, Vx, Wx, DISOPTYPE_HARMLESS, 0);
496	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
497	if (IEM_IS_MODRM_REG_MODE(bRm))
498	{
499	/*
500	* No register, register.
501	*/
502	IEMOP_RAISE_INVALID_OPCODE_RET();
503	}
504	else
505	{
506	/*
507	* Register, memory.
508	*/
509	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
510	IEM_MC_LOCAL(RTUINT128U, uSrc);
511	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
512
513	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
514	IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx);
515	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
516	IEM_MC_PREPARE_AVX_USAGE();
517
518	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
519	IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
520
521	IEM_MC_ADVANCE_RIP_AND_FINISH();
522	IEM_MC_END();
523	}
524	}
525
526
527	/* Opcode VEX.0F38 0x1b - invalid */
528	/* Opcode VEX.66.0F38 0x1b - invalid */
529	/* Opcode VEX.0F38 0x1c - invalid. */
530
531
532	/** Opcode VEX.66.0F38 0x1c. */
533	FNIEMOP_DEF(iemOp_vpabsb_Vx_Wx)
534	{
535	IEMOP_MNEMONIC2(VEX_RM, VPABSB, vpabsb, Vx, Wx, DISOPTYPE_HARMLESS, 0);
536	IEMOPMEDIAOPTF2_INIT_VARS(vpabsb);
537	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
538	}
539
540
541	/* Opcode VEX.0F38 0x1d - invalid. */
542
543
544	/** Opcode VEX.66.0F38 0x1d. */
545	FNIEMOP_DEF(iemOp_vpabsw_Vx_Wx)
546	{
547	IEMOP_MNEMONIC2(VEX_RM, VPABSW, vpabsw, Vx, Wx, DISOPTYPE_HARMLESS, 0);
548	IEMOPMEDIAOPTF2_INIT_VARS(vpabsw);
549	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
550	}
551
552	/* Opcode VEX.0F38 0x1e - invalid. */
553
554
555	/** Opcode VEX.66.0F38 0x1e. */
556	FNIEMOP_DEF(iemOp_vpabsd_Vx_Wx)
557	{
558	IEMOP_MNEMONIC2(VEX_RM, VPABSD, vpabsd, Vx, Wx, DISOPTYPE_HARMLESS, 0);
559	IEMOPMEDIAOPTF2_INIT_VARS(vpabsd);
560	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
561	}
562
563
564	/* Opcode VEX.0F38 0x1f - invalid */
565	/* Opcode VEX.66.0F38 0x1f - invalid */
566
567
568	/** Body for the vpmov{s,z}x* instructions. */
569	#define IEMOP_BODY_VPMOV_S_Z(a_Instr, a_SrcWidth, a_VexLengthMemFetch) \
570	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
571	if (IEM_IS_MODRM_REG_MODE(bRm)) \
572	{ \
573	/* \
574	* Register, register. \
575	*/ \
576	if (pVCpu->iem.s.uVexLength) \
577	{ \
578	IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER, 0); \
579	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2); \
580	IEM_MC_LOCAL(RTUINT256U, uDst); \
581	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
582	IEM_MC_ARG(PCRTUINT128U, puSrc, 1); \
583	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
584	IEM_MC_PREPARE_AVX_USAGE(); \
585	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
586	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
587	iemAImpl_ ## a_Instr ## _u256_fallback), \
588	puDst, puSrc); \
589	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
590	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
591	IEM_MC_END(); \
592	} \
593	else \
594	{ \
595	IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
596	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx); \
597	IEM_MC_ARG(PRTUINT128U, puDst, 0); \
598	IEM_MC_ARG(uint64_t, uSrc, 1); \
599	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
600	IEM_MC_PREPARE_AVX_USAGE(); \
601	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /* a_iQword*/); \
602	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
603	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
604	iemAImpl_## a_Instr ## _u128_fallback), \
605	puDst, uSrc); \
606	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
607	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
608	IEM_MC_END(); \
609	} \
610	} \
611	else \
612	{ \
613	/* \
614	* Register, memory. \
615	*/ \
616	if (pVCpu->iem.s.uVexLength) \
617	{ \
618	IEM_MC_BEGIN(2, 3, IEM_MC_F_NOT_286_OR_OLDER, 0); \
619	IEM_MC_LOCAL(RTUINT256U, uDst); \
620	IEM_MC_LOCAL(RTUINT128U, uSrc); \
621	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
622	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
623	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1); \
624	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
625	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2); \
626	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
627	IEM_MC_PREPARE_AVX_USAGE(); \
628	a_VexLengthMemFetch(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
629	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
630	iemAImpl_ ## a_Instr ## _u256_fallback), \
631	puDst, puSrc); \
632	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
633	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
634	IEM_MC_END(); \
635	} \
636	else \
637	{ \
638	IEM_MC_BEGIN(2, 1, IEM_MC_F_NOT_286_OR_OLDER, 0); \
639	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
640	IEM_MC_ARG(PRTUINT128U, puDst, 0); \
641	IEM_MC_ARG(uint ## a_SrcWidth ##_t, uSrc, 1); \
642	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
643	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx); \
644	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
645	IEM_MC_PREPARE_AVX_USAGE(); \
646	IEM_MC_FETCH_MEM_U ## a_SrcWidth (uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
647	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
648	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
649	iemAImpl_ ## a_Instr ## _u128_fallback), \
650	puDst, uSrc); \
651	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
652	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
653	IEM_MC_END(); \
654	} \
655	} \
656	(void)0
657
658	/** Opcode VEX.66.0F38 0x20. */
659	FNIEMOP_DEF(iemOp_vpmovsxbw_Vx_UxMq)
660	{
661	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
662	IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBW, vpmovsxbw, Vx, Wq, DISOPTYPE_HARMLESS, 0);
663	IEMOP_BODY_VPMOV_S_Z(vpmovsxbw, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
664	}
665
666
667	/** Opcode VEX.66.0F38 0x21. */
668	FNIEMOP_DEF(iemOp_vpmovsxbd_Vx_UxMd)
669	{
670	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
671	IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBD, vpmovsxbd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
672	IEMOP_BODY_VPMOV_S_Z(vpmovsxbd, 32, IEM_MC_FETCH_MEM_U128);
673	}
674
675
676	/** Opcode VEX.66.0F38 0x22. */
677	FNIEMOP_DEF(iemOp_vpmovsxbq_Vx_UxMw)
678	{
679	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
680	IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBQ, vpmovsxbq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
681	IEMOP_BODY_VPMOV_S_Z(vpmovsxbq, 16, IEM_MC_FETCH_MEM_U128);
682	}
683
684
685	/** Opcode VEX.66.0F38 0x23. */
686	FNIEMOP_DEF(iemOp_vpmovsxwd_Vx_UxMq)
687	{
688	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
689	IEMOP_MNEMONIC2(VEX_RM, VPMOVSXWD, vpmovsxwd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
690	IEMOP_BODY_VPMOV_S_Z(vpmovsxwd, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
691	}
692
693
694	/** Opcode VEX.66.0F38 0x24. */
695	FNIEMOP_DEF(iemOp_vpmovsxwq_Vx_UxMd)
696	{
697	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
698	IEMOP_MNEMONIC2(VEX_RM, VPMOVSXWQ, vpmovsxwq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
699	IEMOP_BODY_VPMOV_S_Z(vpmovsxwq, 32, IEM_MC_FETCH_MEM_U128);
700	}
701
702
703	/** Opcode VEX.66.0F38 0x25. */
704	FNIEMOP_DEF(iemOp_vpmovsxdq_Vx_UxMq)
705	{
706	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
707	IEMOP_MNEMONIC2(VEX_RM, VPMOVSXDQ, vpmovsxdq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
708	IEMOP_BODY_VPMOV_S_Z(vpmovsxdq, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
709	}
710
711
712	/* Opcode VEX.66.0F38 0x26 - invalid */
713	/* Opcode VEX.66.0F38 0x27 - invalid */
714
715
716	/** Opcode VEX.66.0F38 0x28. */
717	FNIEMOP_DEF(iemOp_vpmuldq_Vx_Hx_Wx)
718	{
719	IEMOP_MNEMONIC3(VEX_RVM, VPMULDQ, vpmuldq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
720	IEMOPMEDIAOPTF3_INIT_VARS(vpmuldq);
721	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
722	}
723
724
725	/** Opcode VEX.66.0F38 0x29. */
726	FNIEMOP_DEF(iemOp_vpcmpeqq_Vx_Hx_Wx)
727	{
728	IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQQ, vpcmpeqq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
729	IEMOPMEDIAF3_INIT_VARS(vpcmpeqq);
730	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
731	}
732
733
734	FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
735	{
736	Assert(pVCpu->iem.s.uVexLength <= 1);
737	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
738	if (IEM_IS_MODRM_MEM_MODE(bRm))
739	{
740	if (pVCpu->iem.s.uVexLength == 0)
741	{
742	/**
743	* @opcode 0x2a
744	* @opcodesub !11 mr/reg vex.l=0
745	* @oppfx 0x66
746	* @opcpuid avx
747	* @opgroup og_avx_cachect
748	* @opxcpttype 1
749	* @optest op1=-1 op2=2 -> op1=2
750	* @optest op1=0 op2=-42 -> op1=-42
751	*/
752	/* 128-bit: Memory, register. */
753	IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
754	DISOPTYPE_HARMLESS \| DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
755	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
756	IEM_MC_LOCAL(RTUINT128U, uSrc);
757	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
758
759	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
760	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
761	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
762	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
763
764	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
765	IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
766
767	IEM_MC_ADVANCE_RIP_AND_FINISH();
768	IEM_MC_END();
769	}
770	else
771	{
772	/**
773	* @opdone
774	* @opcode 0x2a
775	* @opcodesub !11 mr/reg vex.l=1
776	* @oppfx 0x66
777	* @opcpuid avx2
778	* @opgroup og_avx2_cachect
779	* @opxcpttype 1
780	* @optest op1=-1 op2=2 -> op1=2
781	* @optest op1=0 op2=-42 -> op1=-42
782	*/
783	/* 256-bit: Memory, register. */
784	IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
785	DISOPTYPE_HARMLESS \| DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
786	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
787	IEM_MC_LOCAL(RTUINT256U, uSrc);
788	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
789
790	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
791	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
792	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
793	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
794
795	IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
796	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
797
798	IEM_MC_ADVANCE_RIP_AND_FINISH();
799	IEM_MC_END();
800	}
801	}
802
803	/**
804	* @opdone
805	* @opmnemonic udvex660f382arg
806	* @opcode 0x2a
807	* @opcodesub 11 mr/reg
808	* @oppfx 0x66
809	* @opunused immediate
810	* @opcpuid avx
811	* @optest ->
812	*/
813	else
814	IEMOP_RAISE_INVALID_OPCODE_RET();
815	}
816
817
818	/** Opcode VEX.66.0F38 0x2b. */
819	FNIEMOP_DEF(iemOp_vpackusdw_Vx_Hx_Wx)
820	{
821	IEMOP_MNEMONIC3(VEX_RVM, VPACKUSDW, vpackusdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_AVX, 0);
822	IEMOPMEDIAOPTF3_INIT_VARS( vpackusdw);
823	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
824	}
825
826
827	/** Opcode VEX.66.0F38 0x2c. */
828	FNIEMOP_STUB(iemOp_vmaskmovps_Vx_Hx_Mx);
829	/** Opcode VEX.66.0F38 0x2d. */
830	FNIEMOP_STUB(iemOp_vmaskmovpd_Vx_Hx_Mx);
831	/** Opcode VEX.66.0F38 0x2e. */
832	FNIEMOP_STUB(iemOp_vmaskmovps_Mx_Hx_Vx);
833	/** Opcode VEX.66.0F38 0x2f. */
834	FNIEMOP_STUB(iemOp_vmaskmovpd_Mx_Hx_Vx);
835
836
837	/** Opcode VEX.66.0F38 0x30. */
838	FNIEMOP_DEF(iemOp_vpmovzxbw_Vx_UxMq)
839	{
840	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
841	IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBW, vpmovzxbw, Vx, Wq, DISOPTYPE_HARMLESS, 0);
842	IEMOP_BODY_VPMOV_S_Z(vpmovzxbw, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
843	}
844
845
846	/** Opcode VEX.66.0F38 0x31. */
847	FNIEMOP_DEF(iemOp_vpmovzxbd_Vx_UxMd)
848	{
849	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
850	IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBD, vpmovzxbd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
851	IEMOP_BODY_VPMOV_S_Z(vpmovzxbd, 32, IEM_MC_FETCH_MEM_U128);
852	}
853
854
855	/** Opcode VEX.66.0F38 0x32. */
856	FNIEMOP_DEF(iemOp_vpmovzxbq_Vx_UxMw)
857	{
858	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
859	IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBQ, vpmovzxbq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
860	IEMOP_BODY_VPMOV_S_Z(vpmovzxbq, 16, IEM_MC_FETCH_MEM_U128);
861	}
862
863
864	/** Opcode VEX.66.0F38 0x33. */
865	FNIEMOP_DEF(iemOp_vpmovzxwd_Vx_UxMq)
866	{
867	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
868	IEMOP_MNEMONIC2(VEX_RM, VPMOVZXWD, vpmovzxwd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
869	IEMOP_BODY_VPMOV_S_Z(vpmovzxwd, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
870	}
871
872
873	/** Opcode VEX.66.0F38 0x34. */
874	FNIEMOP_DEF(iemOp_vpmovzxwq_Vx_UxMd)
875	{
876	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
877	IEMOP_MNEMONIC2(VEX_RM, VPMOVZXWQ, vpmovzxwq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
878	IEMOP_BODY_VPMOV_S_Z(vpmovzxwq, 32, IEM_MC_FETCH_MEM_U128);
879	}
880
881
882	/** Opcode VEX.66.0F38 0x35. */
883	FNIEMOP_DEF(iemOp_vpmovzxdq_Vx_UxMq)
884	{
885	/** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
886	IEMOP_MNEMONIC2(VEX_RM, VPMOVZXDQ, vpmovzxdq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
887	IEMOP_BODY_VPMOV_S_Z(vpmovzxdq, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
888	}
889
890
891	/* Opcode VEX.66.0F38 0x36. */
892	FNIEMOP_STUB(iemOp_vpermd_Vqq_Hqq_Wqq);
893
894
895	/** Opcode VEX.66.0F38 0x37. */
896	FNIEMOP_DEF(iemOp_vpcmpgtq_Vx_Hx_Wx)
897	{
898	IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTQ, vpcmpgtq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
899	IEMOPMEDIAF3_INIT_VARS(vpcmpgtq);
900	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
901	}
902
903
904	/** Opcode VEX.66.0F38 0x38. */
905	FNIEMOP_DEF(iemOp_vpminsb_Vx_Hx_Wx)
906	{
907	IEMOP_MNEMONIC3(VEX_RVM, VPMINSB, vpminsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
908	IEMOPMEDIAF3_INIT_VARS(vpminsb);
909	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
910	}
911
912
913	/** Opcode VEX.66.0F38 0x39. */
914	FNIEMOP_DEF(iemOp_vpminsd_Vx_Hx_Wx)
915	{
916	IEMOP_MNEMONIC3(VEX_RVM, VPMINSD, vpminsd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
917	IEMOPMEDIAF3_INIT_VARS(vpminsd);
918	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
919	}
920
921
922	/** Opcode VEX.66.0F38 0x3a. */
923	FNIEMOP_DEF(iemOp_vpminuw_Vx_Hx_Wx)
924	{
925	IEMOP_MNEMONIC3(VEX_RVM, VPMINUW, vpminuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
926	IEMOPMEDIAF3_INIT_VARS(vpminuw);
927	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
928	}
929
930
931	/** Opcode VEX.66.0F38 0x3b. */
932	FNIEMOP_DEF(iemOp_vpminud_Vx_Hx_Wx)
933	{
934	IEMOP_MNEMONIC3(VEX_RVM, VPMINUD, vpminud, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
935	IEMOPMEDIAF3_INIT_VARS(vpminud);
936	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
937	}
938
939
940	/** Opcode VEX.66.0F38 0x3c. */
941	FNIEMOP_DEF(iemOp_vpmaxsb_Vx_Hx_Wx)
942	{
943	IEMOP_MNEMONIC3(VEX_RVM, VPMAXSB, vpmaxsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
944	IEMOPMEDIAF3_INIT_VARS(vpmaxsb);
945	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
946	}
947
948
949	/** Opcode VEX.66.0F38 0x3d. */
950	FNIEMOP_DEF(iemOp_vpmaxsd_Vx_Hx_Wx)
951	{
952	IEMOP_MNEMONIC3(VEX_RVM, VPMAXSD, vpmaxsd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
953	IEMOPMEDIAF3_INIT_VARS(vpmaxsd);
954	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
955	}
956
957
958	/** Opcode VEX.66.0F38 0x3e. */
959	FNIEMOP_DEF(iemOp_vpmaxuw_Vx_Hx_Wx)
960	{
961	IEMOP_MNEMONIC3(VEX_RVM, VPMAXUW, vpmaxuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
962	IEMOPMEDIAF3_INIT_VARS(vpmaxuw);
963	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
964	}
965
966
967	/** Opcode VEX.66.0F38 0x3f. */
968	FNIEMOP_DEF(iemOp_vpmaxud_Vx_Hx_Wx)
969	{
970	IEMOP_MNEMONIC3(VEX_RVM, VPMAXUD, vpmaxud, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
971	IEMOPMEDIAF3_INIT_VARS(vpmaxud);
972	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
973	}
974
975
976	/** Opcode VEX.66.0F38 0x40. */
977	FNIEMOP_DEF(iemOp_vpmulld_Vx_Hx_Wx)
978	{
979	IEMOP_MNEMONIC3(VEX_RVM, VPMULLD, vpmulld, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
980	IEMOPMEDIAOPTF3_INIT_VARS(vpmulld);
981	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
982	}
983
984
985	/** Opcode VEX.66.0F38 0x41. */
986	FNIEMOP_DEF(iemOp_vphminposuw_Vdq_Wdq)
987	{
988	IEMOP_MNEMONIC2(VEX_RM, VPHMINPOSUW, vphminposuw, Vdq, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
989	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
990	if (IEM_IS_MODRM_REG_MODE(bRm))
991	{
992	/*
993	* Register, register.
994	*/
995	IEM_MC_BEGIN(2, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
996	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
997	IEM_MC_ARG(PRTUINT128U, puDst, 0);
998	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
999	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1000	IEM_MC_PREPARE_AVX_USAGE();
1001	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1002	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1003	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback),
1004	puDst, puSrc);
1005	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1006	IEM_MC_ADVANCE_RIP_AND_FINISH();
1007	IEM_MC_END();
1008	}
1009	else
1010	{
1011	/*
1012	* Register, memory.
1013	*/
1014	IEM_MC_BEGIN(2, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1015	IEM_MC_LOCAL(RTUINT128U, uSrc);
1016	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1017	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1018	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1019
1020	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1021	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1022	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1023	IEM_MC_PREPARE_AVX_USAGE();
1024
1025	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1026	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1027	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback),
1028	puDst, puSrc);
1029	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1030
1031	IEM_MC_ADVANCE_RIP_AND_FINISH();
1032	IEM_MC_END();
1033	}
1034	}
1035
1036
1037	/* Opcode VEX.66.0F38 0x42 - invalid. */
1038	/* Opcode VEX.66.0F38 0x43 - invalid. */
1039	/* Opcode VEX.66.0F38 0x44 - invalid. */
1040
1041
1042	/** Opcode VEX.66.0F38 0x45. */
1043	FNIEMOP_DEF(iemOp_vpsrlvd_q_Vx_Hx_Wx)
1044	{
1045	IEMOP_MNEMONIC3(VEX_RVM, VPSRLVD, vpsrlvd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1046
1047	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1048	{
1049	IEMOPMEDIAOPTF3_INIT_VARS(vpsrlvq);
1050	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1051	}
1052	else
1053	{
1054	IEMOPMEDIAOPTF3_INIT_VARS(vpsrlvd);
1055	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1056	}
1057	}
1058
1059
1060	/** Opcode VEX.66.0F38 0x46. */
1061	FNIEMOP_DEF(iemOp_vpsravd_Vx_Hx_Wx)
1062	{
1063	IEMOP_MNEMONIC3(VEX_RVM, VPSRAVD, vpsravd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1064	IEMOPMEDIAOPTF3_INIT_VARS(vpsravd);
1065	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1066	}
1067
1068
1069	/** Opcode VEX.66.0F38 0x47. */
1070	FNIEMOP_DEF(iemOp_vpsllvd_q_Vx_Hx_Wx)
1071	{
1072	IEMOP_MNEMONIC3(VEX_RVM, VPSLLVD, vpsllvd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1073
1074	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1075	{
1076	IEMOPMEDIAOPTF3_INIT_VARS(vpsllvq);
1077	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1078	}
1079	else
1080	{
1081	IEMOPMEDIAOPTF3_INIT_VARS(vpsllvd);
1082	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1083	}
1084	}
1085
1086
1087	/* Opcode VEX.66.0F38 0x48 - invalid. */
1088	/* Opcode VEX.66.0F38 0x49 - invalid. */
1089	/* Opcode VEX.66.0F38 0x4a - invalid. */
1090	/* Opcode VEX.66.0F38 0x4b - invalid. */
1091	/* Opcode VEX.66.0F38 0x4c - invalid. */
1092	/* Opcode VEX.66.0F38 0x4d - invalid. */
1093	/* Opcode VEX.66.0F38 0x4e - invalid. */
1094	/* Opcode VEX.66.0F38 0x4f - invalid. */
1095
1096	/* Opcode VEX.66.0F38 0x50 - invalid. */
1097	/* Opcode VEX.66.0F38 0x51 - invalid. */
1098	/* Opcode VEX.66.0F38 0x52 - invalid. */
1099	/* Opcode VEX.66.0F38 0x53 - invalid. */
1100	/* Opcode VEX.66.0F38 0x54 - invalid. */
1101	/* Opcode VEX.66.0F38 0x55 - invalid. */
1102	/* Opcode VEX.66.0F38 0x56 - invalid. */
1103	/* Opcode VEX.66.0F38 0x57 - invalid. */
1104
1105
1106	/** Opcode VEX.66.0F38 0x58. */
1107	FNIEMOP_DEF(iemOp_vpbroadcastd_Vx_Wx)
1108	{
1109	IEMOP_MNEMONIC2(VEX_RM, VPBROADCASTD, vpbroadcastd, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1110	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1111	if (IEM_IS_MODRM_REG_MODE(bRm))
1112	{
1113	/*
1114	* Register, register.
1115	*/
1116	if (pVCpu->iem.s.uVexLength)
1117	{
1118	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1119	IEM_MC_LOCAL(uint32_t, uSrc);
1120
1121	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1122	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1123	IEM_MC_PREPARE_AVX_USAGE();
1124
1125	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1126	IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1127
1128	IEM_MC_ADVANCE_RIP_AND_FINISH();
1129	IEM_MC_END();
1130	}
1131	else
1132	{
1133	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1134	IEM_MC_LOCAL(uint32_t, uSrc);
1135
1136	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1137	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1138	IEM_MC_PREPARE_AVX_USAGE();
1139	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1140	IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1141
1142	IEM_MC_ADVANCE_RIP_AND_FINISH();
1143	IEM_MC_END();
1144	}
1145	}
1146	else
1147	{
1148	/*
1149	* Register, memory.
1150	*/
1151	if (pVCpu->iem.s.uVexLength)
1152	{
1153	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1154	IEM_MC_LOCAL(uint32_t, uSrc);
1155	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1156
1157	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1158	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1159	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1160	IEM_MC_PREPARE_AVX_USAGE();
1161
1162	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1163	IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1164
1165	IEM_MC_ADVANCE_RIP_AND_FINISH();
1166	IEM_MC_END();
1167	}
1168	else
1169	{
1170	IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
1171	IEM_MC_LOCAL(uint32_t, uSrc);
1172	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1173
1174	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1175	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1176	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1177	IEM_MC_PREPARE_AVX_USAGE();
1178
1179	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1180	IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1181
1182	IEM_MC_ADVANCE_RIP_AND_FINISH();
1183	IEM_MC_END();
1184	}
1185	}
1186	}
1187
1188
1189	/** Opcode VEX.66.0F38 0x59. */
1190	FNIEMOP_DEF(iemOp_vpbroadcastq_Vx_Wx)
1191	{
1192	IEMOP_MNEMONIC2(VEX_RM, VPBROADCASTQ, vpbroadcastq, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1193	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1194	if (IEM_IS_MODRM_REG_MODE(bRm))
1195	{
1196	/*
1197	* Register, register.
1198	*/
1199	if (pVCpu->iem.s.uVexLength)
1200	{
1201	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1202	IEM_MC_LOCAL(uint64_t, uSrc);
1203
1204	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1205	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1206	IEM_MC_PREPARE_AVX_USAGE();
1207
1208	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1209	IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1210
1211	IEM_MC_ADVANCE_RIP_AND_FINISH();
1212	IEM_MC_END();
1213	}
1214	else
1215	{
1216	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1217	IEM_MC_LOCAL(uint64_t, uSrc);
1218
1219	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1220	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1221	IEM_MC_PREPARE_AVX_USAGE();
1222	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1223	IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1224
1225	IEM_MC_ADVANCE_RIP_AND_FINISH();
1226	IEM_MC_END();
1227	}
1228	}
1229	else
1230	{
1231	/*
1232	* Register, memory.
1233	*/
1234	if (pVCpu->iem.s.uVexLength)
1235	{
1236	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1237	IEM_MC_LOCAL(uint64_t, uSrc);
1238	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1239
1240	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1241	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1242	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1243	IEM_MC_PREPARE_AVX_USAGE();
1244
1245	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1246	IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1247
1248	IEM_MC_ADVANCE_RIP_AND_FINISH();
1249	IEM_MC_END();
1250	}
1251	else
1252	{
1253	IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
1254	IEM_MC_LOCAL(uint64_t, uSrc);
1255	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1256
1257	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1258	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1259	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1260	IEM_MC_PREPARE_AVX_USAGE();
1261
1262	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1263	IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1264
1265	IEM_MC_ADVANCE_RIP_AND_FINISH();
1266	IEM_MC_END();
1267	}
1268	}
1269	}
1270
1271
1272	/** Opcode VEX.66.0F38 0x5a. */
1273	FNIEMOP_DEF(iemOp_vbroadcasti128_Vqq_Mdq)
1274	{
1275	IEMOP_MNEMONIC2(VEX_RM, VBROADCASTI128, vbroadcasti128, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1276	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1277	if (IEM_IS_MODRM_REG_MODE(bRm))
1278	{
1279	/*
1280	* No register, register.
1281	*/
1282	IEMOP_RAISE_INVALID_OPCODE_RET();
1283	}
1284	else
1285	{
1286	/*
1287	* Register, memory.
1288	*/
1289	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1290	IEM_MC_LOCAL(RTUINT128U, uSrc);
1291	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1292
1293	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1294	IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx);
1295	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1296	IEM_MC_PREPARE_AVX_USAGE();
1297
1298	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1299	IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1300
1301	IEM_MC_ADVANCE_RIP_AND_FINISH();
1302	IEM_MC_END();
1303	}
1304	}
1305
1306
1307	/* Opcode VEX.66.0F38 0x5b - invalid. */
1308	/* Opcode VEX.66.0F38 0x5c - invalid. */
1309	/* Opcode VEX.66.0F38 0x5d - invalid. */
1310	/* Opcode VEX.66.0F38 0x5e - invalid. */
1311	/* Opcode VEX.66.0F38 0x5f - invalid. */
1312
1313	/* Opcode VEX.66.0F38 0x60 - invalid. */
1314	/* Opcode VEX.66.0F38 0x61 - invalid. */
1315	/* Opcode VEX.66.0F38 0x62 - invalid. */
1316	/* Opcode VEX.66.0F38 0x63 - invalid. */
1317	/* Opcode VEX.66.0F38 0x64 - invalid. */
1318	/* Opcode VEX.66.0F38 0x65 - invalid. */
1319	/* Opcode VEX.66.0F38 0x66 - invalid. */
1320	/* Opcode VEX.66.0F38 0x67 - invalid. */
1321	/* Opcode VEX.66.0F38 0x68 - invalid. */
1322	/* Opcode VEX.66.0F38 0x69 - invalid. */
1323	/* Opcode VEX.66.0F38 0x6a - invalid. */
1324	/* Opcode VEX.66.0F38 0x6b - invalid. */
1325	/* Opcode VEX.66.0F38 0x6c - invalid. */
1326	/* Opcode VEX.66.0F38 0x6d - invalid. */
1327	/* Opcode VEX.66.0F38 0x6e - invalid. */
1328	/* Opcode VEX.66.0F38 0x6f - invalid. */
1329
1330	/* Opcode VEX.66.0F38 0x70 - invalid. */
1331	/* Opcode VEX.66.0F38 0x71 - invalid. */
1332	/* Opcode VEX.66.0F38 0x72 - invalid. */
1333	/* Opcode VEX.66.0F38 0x73 - invalid. */
1334	/* Opcode VEX.66.0F38 0x74 - invalid. */
1335	/* Opcode VEX.66.0F38 0x75 - invalid. */
1336	/* Opcode VEX.66.0F38 0x76 - invalid. */
1337	/* Opcode VEX.66.0F38 0x77 - invalid. */
1338
1339
1340	/** Opcode VEX.66.0F38 0x78. */
1341	FNIEMOP_DEF(iemOp_vpbroadcastb_Vx_Wx)
1342	{
1343	IEMOP_MNEMONIC2(VEX_RM, VPBROADCASTB, vpbroadcastb, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1344	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1345	if (IEM_IS_MODRM_REG_MODE(bRm))
1346	{
1347	/*
1348	* Register, register.
1349	*/
1350	if (pVCpu->iem.s.uVexLength)
1351	{
1352	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1353	IEM_MC_LOCAL(uint8_t, uSrc);
1354
1355	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1356	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1357	IEM_MC_PREPARE_AVX_USAGE();
1358
1359	IEM_MC_FETCH_XREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1360	IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1361
1362	IEM_MC_ADVANCE_RIP_AND_FINISH();
1363	IEM_MC_END();
1364	}
1365	else
1366	{
1367	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1368	IEM_MC_LOCAL(uint8_t, uSrc);
1369
1370	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1371	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1372	IEM_MC_PREPARE_AVX_USAGE();
1373	IEM_MC_FETCH_XREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1374	IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1375
1376	IEM_MC_ADVANCE_RIP_AND_FINISH();
1377	IEM_MC_END();
1378	}
1379	}
1380	else
1381	{
1382	/*
1383	* Register, memory.
1384	*/
1385	if (pVCpu->iem.s.uVexLength)
1386	{
1387	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1388	IEM_MC_LOCAL(uint8_t, uSrc);
1389	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1390
1391	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1392	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1393	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1394	IEM_MC_PREPARE_AVX_USAGE();
1395
1396	IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1397	IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1398
1399	IEM_MC_ADVANCE_RIP_AND_FINISH();
1400	IEM_MC_END();
1401	}
1402	else
1403	{
1404	IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
1405	IEM_MC_LOCAL(uint8_t, uSrc);
1406	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1407
1408	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1409	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1410	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1411	IEM_MC_PREPARE_AVX_USAGE();
1412
1413	IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1414	IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1415
1416	IEM_MC_ADVANCE_RIP_AND_FINISH();
1417	IEM_MC_END();
1418	}
1419	}
1420	}
1421
1422
1423	/** Opcode VEX.66.0F38 0x79. */
1424	FNIEMOP_DEF(iemOp_vpbroadcastw_Vx_Wx)
1425	{
1426	IEMOP_MNEMONIC2(VEX_RM, VPBROADCASTW, vpbroadcastw, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1427	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1428	if (IEM_IS_MODRM_REG_MODE(bRm))
1429	{
1430	/*
1431	* Register, register.
1432	*/
1433	if (pVCpu->iem.s.uVexLength)
1434	{
1435	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1436	IEM_MC_LOCAL(uint16_t, uSrc);
1437
1438	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1439	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1440	IEM_MC_PREPARE_AVX_USAGE();
1441
1442	IEM_MC_FETCH_XREG_U16(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1443	IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1444
1445	IEM_MC_ADVANCE_RIP_AND_FINISH();
1446	IEM_MC_END();
1447	}
1448	else
1449	{
1450	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1451	IEM_MC_LOCAL(uint16_t, uSrc);
1452
1453	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1454	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1455	IEM_MC_PREPARE_AVX_USAGE();
1456	IEM_MC_FETCH_XREG_U16(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1457	IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1458
1459	IEM_MC_ADVANCE_RIP_AND_FINISH();
1460	IEM_MC_END();
1461	}
1462	}
1463	else
1464	{
1465	/*
1466	* Register, memory.
1467	*/
1468	if (pVCpu->iem.s.uVexLength)
1469	{
1470	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1471	IEM_MC_LOCAL(uint16_t, uSrc);
1472	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1473
1474	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1475	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1476	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1477	IEM_MC_PREPARE_AVX_USAGE();
1478
1479	IEM_MC_FETCH_MEM_U16(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1480	IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1481
1482	IEM_MC_ADVANCE_RIP_AND_FINISH();
1483	IEM_MC_END();
1484	}
1485	else
1486	{
1487	IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
1488	IEM_MC_LOCAL(uint16_t, uSrc);
1489	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1490
1491	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1492	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1493	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1494	IEM_MC_PREPARE_AVX_USAGE();
1495
1496	IEM_MC_FETCH_MEM_U16(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1497	IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1498
1499	IEM_MC_ADVANCE_RIP_AND_FINISH();
1500	IEM_MC_END();
1501	}
1502	}
1503	}
1504
1505
1506	/* Opcode VEX.66.0F38 0x7a - invalid. */
1507	/* Opcode VEX.66.0F38 0x7b - invalid. */
1508	/* Opcode VEX.66.0F38 0x7c - invalid. */
1509	/* Opcode VEX.66.0F38 0x7d - invalid. */
1510	/* Opcode VEX.66.0F38 0x7e - invalid. */
1511	/* Opcode VEX.66.0F38 0x7f - invalid. */
1512
1513	/* Opcode VEX.66.0F38 0x80 - invalid (legacy only). */
1514	/* Opcode VEX.66.0F38 0x81 - invalid (legacy only). */
1515	/* Opcode VEX.66.0F38 0x82 - invalid (legacy only). */
1516	/* Opcode VEX.66.0F38 0x83 - invalid. */
1517	/* Opcode VEX.66.0F38 0x84 - invalid. */
1518	/* Opcode VEX.66.0F38 0x85 - invalid. */
1519	/* Opcode VEX.66.0F38 0x86 - invalid. */
1520	/* Opcode VEX.66.0F38 0x87 - invalid. */
1521	/* Opcode VEX.66.0F38 0x88 - invalid. */
1522	/* Opcode VEX.66.0F38 0x89 - invalid. */
1523	/* Opcode VEX.66.0F38 0x8a - invalid. */
1524	/* Opcode VEX.66.0F38 0x8b - invalid. */
1525	/** Opcode VEX.66.0F38 0x8c. */
1526	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Vx_Hx_Mx);
1527	/* Opcode VEX.66.0F38 0x8d - invalid. */
1528	/** Opcode VEX.66.0F38 0x8e. */
1529	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Mx_Vx_Hx);
1530	/* Opcode VEX.66.0F38 0x8f - invalid. */
1531
1532	/** Opcode VEX.66.0F38 0x90 (vex only). */
1533	FNIEMOP_STUB(iemOp_vgatherdd_q_Vx_Hx_Wx);
1534	/** Opcode VEX.66.0F38 0x91 (vex only). */
1535	FNIEMOP_STUB(iemOp_vgatherqd_q_Vx_Hx_Wx);
1536	/** Opcode VEX.66.0F38 0x92 (vex only). */
1537	FNIEMOP_STUB(iemOp_vgatherdps_d_Vx_Hx_Wx);
1538	/** Opcode VEX.66.0F38 0x93 (vex only). */
1539	FNIEMOP_STUB(iemOp_vgatherqps_d_Vx_Hx_Wx);
1540	/* Opcode VEX.66.0F38 0x94 - invalid. */
1541	/* Opcode VEX.66.0F38 0x95 - invalid. */
1542	/** Opcode VEX.66.0F38 0x96 (vex only). */
1543	FNIEMOP_STUB(iemOp_vfmaddsub132ps_q_Vx_Hx_Wx);
1544	/** Opcode VEX.66.0F38 0x97 (vex only). */
1545	FNIEMOP_STUB(iemOp_vfmsubadd132ps_d_Vx_Hx_Wx);
1546	/** Opcode VEX.66.0F38 0x98 (vex only). */
1547	FNIEMOP_STUB(iemOp_vfmadd132ps_d_Vx_Hx_Wx);
1548	/** Opcode VEX.66.0F38 0x99 (vex only). */
1549	FNIEMOP_STUB(iemOp_vfmadd132ss_d_Vx_Hx_Wx);
1550	/** Opcode VEX.66.0F38 0x9a (vex only). */
1551	FNIEMOP_STUB(iemOp_vfmsub132ps_d_Vx_Hx_Wx);
1552	/** Opcode VEX.66.0F38 0x9b (vex only). */
1553	FNIEMOP_STUB(iemOp_vfmsub132ss_d_Vx_Hx_Wx);
1554	/** Opcode VEX.66.0F38 0x9c (vex only). */
1555	FNIEMOP_STUB(iemOp_vfnmadd132ps_d_Vx_Hx_Wx);
1556	/** Opcode VEX.66.0F38 0x9d (vex only). */
1557	FNIEMOP_STUB(iemOp_vfnmadd132ss_d_Vx_Hx_Wx);
1558	/** Opcode VEX.66.0F38 0x9e (vex only). */
1559	FNIEMOP_STUB(iemOp_vfnmsub132ps_d_Vx_Hx_Wx);
1560	/** Opcode VEX.66.0F38 0x9f (vex only). */
1561	FNIEMOP_STUB(iemOp_vfnmsub132ss_d_Vx_Hx_Wx);
1562
1563	/* Opcode VEX.66.0F38 0xa0 - invalid. */
1564	/* Opcode VEX.66.0F38 0xa1 - invalid. */
1565	/* Opcode VEX.66.0F38 0xa2 - invalid. */
1566	/* Opcode VEX.66.0F38 0xa3 - invalid. */
1567	/* Opcode VEX.66.0F38 0xa4 - invalid. */
1568	/* Opcode VEX.66.0F38 0xa5 - invalid. */
1569	/** Opcode VEX.66.0F38 0xa6 (vex only). */
1570	FNIEMOP_STUB(iemOp_vfmaddsub213ps_d_Vx_Hx_Wx);
1571	/** Opcode VEX.66.0F38 0xa7 (vex only). */
1572	FNIEMOP_STUB(iemOp_vfmsubadd213ps_d_Vx_Hx_Wx);
1573	/** Opcode VEX.66.0F38 0xa8 (vex only). */
1574	FNIEMOP_STUB(iemOp_vfmadd213ps_d_Vx_Hx_Wx);
1575	/** Opcode VEX.66.0F38 0xa9 (vex only). */
1576	FNIEMOP_STUB(iemOp_vfmadd213ss_d_Vx_Hx_Wx);
1577	/** Opcode VEX.66.0F38 0xaa (vex only). */
1578	FNIEMOP_STUB(iemOp_vfmsub213ps_d_Vx_Hx_Wx);
1579	/** Opcode VEX.66.0F38 0xab (vex only). */
1580	FNIEMOP_STUB(iemOp_vfmsub213ss_d_Vx_Hx_Wx);
1581	/** Opcode VEX.66.0F38 0xac (vex only). */
1582	FNIEMOP_STUB(iemOp_vfnmadd213ps_d_Vx_Hx_Wx);
1583	/** Opcode VEX.66.0F38 0xad (vex only). */
1584	FNIEMOP_STUB(iemOp_vfnmadd213ss_d_Vx_Hx_Wx);
1585	/** Opcode VEX.66.0F38 0xae (vex only). */
1586	FNIEMOP_STUB(iemOp_vfnmsub213ps_d_Vx_Hx_Wx);
1587	/** Opcode VEX.66.0F38 0xaf (vex only). */
1588	FNIEMOP_STUB(iemOp_vfnmsub213ss_d_Vx_Hx_Wx);
1589
1590	/* Opcode VEX.66.0F38 0xb0 - invalid. */
1591	/* Opcode VEX.66.0F38 0xb1 - invalid. */
1592	/* Opcode VEX.66.0F38 0xb2 - invalid. */
1593	/* Opcode VEX.66.0F38 0xb3 - invalid. */
1594	/* Opcode VEX.66.0F38 0xb4 - invalid. */
1595	/* Opcode VEX.66.0F38 0xb5 - invalid. */
1596	/** Opcode VEX.66.0F38 0xb6 (vex only). */
1597	FNIEMOP_STUB(iemOp_vfmaddsub231ps_d_Vx_Hx_Wx);
1598	/** Opcode VEX.66.0F38 0xb7 (vex only). */
1599	FNIEMOP_STUB(iemOp_vfmsubadd231ps_d_Vx_Hx_Wx);
1600	/** Opcode VEX.66.0F38 0xb8 (vex only). */
1601	FNIEMOP_STUB(iemOp_vfmadd231ps_d_Vx_Hx_Wx);
1602	/** Opcode VEX.66.0F38 0xb9 (vex only). */
1603	FNIEMOP_STUB(iemOp_vfmadd231ss_d_Vx_Hx_Wx);
1604	/** Opcode VEX.66.0F38 0xba (vex only). */
1605	FNIEMOP_STUB(iemOp_vfmsub231ps_d_Vx_Hx_Wx);
1606	/** Opcode VEX.66.0F38 0xbb (vex only). */
1607	FNIEMOP_STUB(iemOp_vfmsub231ss_d_Vx_Hx_Wx);
1608	/** Opcode VEX.66.0F38 0xbc (vex only). */
1609	FNIEMOP_STUB(iemOp_vfnmadd231ps_d_Vx_Hx_Wx);
1610	/** Opcode VEX.66.0F38 0xbd (vex only). */
1611	FNIEMOP_STUB(iemOp_vfnmadd231ss_d_Vx_Hx_Wx);
1612	/** Opcode VEX.66.0F38 0xbe (vex only). */
1613	FNIEMOP_STUB(iemOp_vfnmsub231ps_d_Vx_Hx_Wx);
1614	/** Opcode VEX.66.0F38 0xbf (vex only). */
1615	FNIEMOP_STUB(iemOp_vfnmsub231ss_d_Vx_Hx_Wx);
1616
1617	/* Opcode VEX.0F38 0xc0 - invalid. */
1618	/* Opcode VEX.66.0F38 0xc0 - invalid. */
1619	/* Opcode VEX.0F38 0xc1 - invalid. */
1620	/* Opcode VEX.66.0F38 0xc1 - invalid. */
1621	/* Opcode VEX.0F38 0xc2 - invalid. */
1622	/* Opcode VEX.66.0F38 0xc2 - invalid. */
1623	/* Opcode VEX.0F38 0xc3 - invalid. */
1624	/* Opcode VEX.66.0F38 0xc3 - invalid. */
1625	/* Opcode VEX.0F38 0xc4 - invalid. */
1626	/* Opcode VEX.66.0F38 0xc4 - invalid. */
1627	/* Opcode VEX.0F38 0xc5 - invalid. */
1628	/* Opcode VEX.66.0F38 0xc5 - invalid. */
1629	/* Opcode VEX.0F38 0xc6 - invalid. */
1630	/* Opcode VEX.66.0F38 0xc6 - invalid. */
1631	/* Opcode VEX.0F38 0xc7 - invalid. */
1632	/* Opcode VEX.66.0F38 0xc7 - invalid. */
1633	/* Opcode VEX.0F38 0xc8 - invalid. */
1634	/* Opcode VEX.66.0F38 0xc8 - invalid. */
1635	/* Opcode VEX.0F38 0xc9 - invalid. */
1636	/* Opcode VEX.66.0F38 0xc9 - invalid. */
1637	/* Opcode VEX.0F38 0xca. */
1638	/* Opcode VEX.66.0F38 0xca - invalid. */
1639	/* Opcode VEX.0F38 0xcb - invalid. */
1640	/* Opcode VEX.66.0F38 0xcb - invalid. */
1641	/* Opcode VEX.0F38 0xcc - invalid. */
1642	/* Opcode VEX.66.0F38 0xcc - invalid. */
1643	/* Opcode VEX.0F38 0xcd - invalid. */
1644	/* Opcode VEX.66.0F38 0xcd - invalid. */
1645	/* Opcode VEX.0F38 0xce - invalid. */
1646	/* Opcode VEX.66.0F38 0xce - invalid. */
1647	/* Opcode VEX.0F38 0xcf - invalid. */
1648	/* Opcode VEX.66.0F38 0xcf - invalid. */
1649
1650	/* Opcode VEX.66.0F38 0xd0 - invalid. */
1651	/* Opcode VEX.66.0F38 0xd1 - invalid. */
1652	/* Opcode VEX.66.0F38 0xd2 - invalid. */
1653	/* Opcode VEX.66.0F38 0xd3 - invalid. */
1654	/* Opcode VEX.66.0F38 0xd4 - invalid. */
1655	/* Opcode VEX.66.0F38 0xd5 - invalid. */
1656	/* Opcode VEX.66.0F38 0xd6 - invalid. */
1657	/* Opcode VEX.66.0F38 0xd7 - invalid. */
1658	/* Opcode VEX.66.0F38 0xd8 - invalid. */
1659	/* Opcode VEX.66.0F38 0xd9 - invalid. */
1660	/* Opcode VEX.66.0F38 0xda - invalid. */
1661	/** Opcode VEX.66.0F38 0xdb. */
1662	FNIEMOP_STUB(iemOp_vaesimc_Vdq_Wdq);
1663	/** Opcode VEX.66.0F38 0xdc. */
1664	FNIEMOP_STUB(iemOp_vaesenc_Vdq_Wdq);
1665	/** Opcode VEX.66.0F38 0xdd. */
1666	FNIEMOP_STUB(iemOp_vaesenclast_Vdq_Wdq);
1667	/** Opcode VEX.66.0F38 0xde. */
1668	FNIEMOP_STUB(iemOp_vaesdec_Vdq_Wdq);
1669	/** Opcode VEX.66.0F38 0xdf. */
1670	FNIEMOP_STUB(iemOp_vaesdeclast_Vdq_Wdq);
1671
1672	/* Opcode VEX.66.0F38 0xe0 - invalid. */
1673	/* Opcode VEX.66.0F38 0xe1 - invalid. */
1674	/* Opcode VEX.66.0F38 0xe2 - invalid. */
1675	/* Opcode VEX.66.0F38 0xe3 - invalid. */
1676	/* Opcode VEX.66.0F38 0xe4 - invalid. */
1677	/* Opcode VEX.66.0F38 0xe5 - invalid. */
1678	/* Opcode VEX.66.0F38 0xe6 - invalid. */
1679	/* Opcode VEX.66.0F38 0xe7 - invalid. */
1680	/* Opcode VEX.66.0F38 0xe8 - invalid. */
1681	/* Opcode VEX.66.0F38 0xe9 - invalid. */
1682	/* Opcode VEX.66.0F38 0xea - invalid. */
1683	/* Opcode VEX.66.0F38 0xeb - invalid. */
1684	/* Opcode VEX.66.0F38 0xec - invalid. */
1685	/* Opcode VEX.66.0F38 0xed - invalid. */
1686	/* Opcode VEX.66.0F38 0xee - invalid. */
1687	/* Opcode VEX.66.0F38 0xef - invalid. */
1688
1689
1690	/* Opcode VEX.0F38 0xf0 - invalid (legacy only). */
1691	/* Opcode VEX.66.0F38 0xf0 - invalid (legacy only). */
1692	/* Opcode VEX.F3.0F38 0xf0 - invalid. */
1693	/* Opcode VEX.F2.0F38 0xf0 - invalid (legacy only). */
1694
1695	/* Opcode VEX.0F38 0xf1 - invalid (legacy only). */
1696	/* Opcode VEX.66.0F38 0xf1 - invalid (legacy only). */
1697	/* Opcode VEX.F3.0F38 0xf1 - invalid. */
1698	/* Opcode VEX.F2.0F38 0xf1 - invalid (legacy only). */
1699
1700	/**
1701	* @opcode 0xf2
1702	* @oppfx none
1703	* @opflmodify cf,pf,af,zf,sf,of
1704	* @opflclear cf,of
1705	* @opflundef pf,af
1706	* @note VEX only
1707	*/
1708	FNIEMOP_DEF(iemOp_andn_Gy_By_Ey)
1709	{
1710	IEMOP_MNEMONIC3(VEX_RVM, ANDN, andn, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1711	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF);
1712	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1713	if (IEM_IS_MODRM_REG_MODE(bRm))
1714	{
1715	/*
1716	* Register, register.
1717	*/
1718	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1719	{
1720	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1721	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
1722	IEM_MC_ARG(uint64_t *, pDst, 0);
1723	IEM_MC_ARG(uint64_t, uSrc1, 1);
1724	IEM_MC_ARG(uint64_t, uSrc2, 2);
1725	IEM_MC_ARG(uint32_t *, pEFlags, 3);
1726	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1727	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1728	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1729	IEM_MC_REF_EFLAGS(pEFlags);
1730	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
1731	pDst, uSrc1, uSrc2, pEFlags);
1732	IEM_MC_ADVANCE_RIP_AND_FINISH();
1733	IEM_MC_END();
1734	}
1735	else
1736	{
1737	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1738	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
1739	IEM_MC_ARG(uint32_t *, pDst, 0);
1740	IEM_MC_ARG(uint32_t, uSrc1, 1);
1741	IEM_MC_ARG(uint32_t, uSrc2, 2);
1742	IEM_MC_ARG(uint32_t *, pEFlags, 3);
1743	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1744	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1745	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1746	IEM_MC_REF_EFLAGS(pEFlags);
1747	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
1748	pDst, uSrc1, uSrc2, pEFlags);
1749	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1750	IEM_MC_ADVANCE_RIP_AND_FINISH();
1751	IEM_MC_END();
1752	}
1753	}
1754	else
1755	{
1756	/*
1757	* Register, memory.
1758	*/
1759	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1760	{
1761	IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1762	IEM_MC_ARG(uint64_t *, pDst, 0);
1763	IEM_MC_ARG(uint64_t, uSrc1, 1);
1764	IEM_MC_ARG(uint64_t, uSrc2, 2);
1765	IEM_MC_ARG(uint32_t *, pEFlags, 3);
1766	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1767	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1768	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
1769	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1770	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1771	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1772	IEM_MC_REF_EFLAGS(pEFlags);
1773	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
1774	pDst, uSrc1, uSrc2, pEFlags);
1775	IEM_MC_ADVANCE_RIP_AND_FINISH();
1776	IEM_MC_END();
1777	}
1778	else
1779	{
1780	IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1781	IEM_MC_ARG(uint32_t *, pDst, 0);
1782	IEM_MC_ARG(uint32_t, uSrc1, 1);
1783	IEM_MC_ARG(uint32_t, uSrc2, 2);
1784	IEM_MC_ARG(uint32_t *, pEFlags, 3);
1785	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1786	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1787	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
1788	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1789	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1790	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1791	IEM_MC_REF_EFLAGS(pEFlags);
1792	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
1793	pDst, uSrc1, uSrc2, pEFlags);
1794	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1795	IEM_MC_ADVANCE_RIP_AND_FINISH();
1796	IEM_MC_END();
1797	}
1798	}
1799	}
1800
1801	/* Opcode VEX.66.0F38 0xf2 - invalid. */
1802	/* Opcode VEX.F3.0F38 0xf2 - invalid. */
1803	/* Opcode VEX.F2.0F38 0xf2 - invalid. */
1804
1805
1806	/* Opcode VEX.0F38 0xf3 - invalid. */
1807	/* Opcode VEX.66.0F38 0xf3 - invalid. */
1808
1809	/* Opcode VEX.F3.0F38 0xf3 /0 - invalid. */
1810
1811	/** Body for the vex group 17 instructions. */
1812	#define IEMOP_BODY_By_Ey(a_Instr) \
1813	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF); \
1814	if (IEM_IS_MODRM_REG_MODE(bRm)) \
1815	{ \
1816	/* \
1817	* Register, register. \
1818	*/ \
1819	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1820	{ \
1821	IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
1822	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
1823	IEM_MC_ARG(uint64_t *, pDst, 0); \
1824	IEM_MC_ARG(uint64_t, uSrc, 1); \
1825	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1826	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1827	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1828	IEM_MC_REF_EFLAGS(pEFlags); \
1829	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
1830	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
1831	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1832	IEM_MC_END(); \
1833	} \
1834	else \
1835	{ \
1836	IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
1837	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
1838	IEM_MC_ARG(uint32_t *, pDst, 0); \
1839	IEM_MC_ARG(uint32_t, uSrc, 1); \
1840	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1841	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1842	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1843	IEM_MC_REF_EFLAGS(pEFlags); \
1844	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
1845	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
1846	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1847	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1848	IEM_MC_END(); \
1849	} \
1850	} \
1851	else \
1852	{ \
1853	/* \
1854	* Register, memory. \
1855	*/ \
1856	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1857	{ \
1858	IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0); \
1859	IEM_MC_ARG(uint64_t *, pDst, 0); \
1860	IEM_MC_ARG(uint64_t, uSrc, 1); \
1861	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1862	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1863	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1864	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
1865	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1866	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1867	IEM_MC_REF_EFLAGS(pEFlags); \
1868	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
1869	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
1870	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1871	IEM_MC_END(); \
1872	} \
1873	else \
1874	{ \
1875	IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0); \
1876	IEM_MC_ARG(uint32_t *, pDst, 0); \
1877	IEM_MC_ARG(uint32_t, uSrc, 1); \
1878	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1879	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1880	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1881	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
1882	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1883	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1884	IEM_MC_REF_EFLAGS(pEFlags); \
1885	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
1886	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
1887	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1888	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1889	IEM_MC_END(); \
1890	} \
1891	} \
1892	(void)0
1893
1894
1895	/**
1896	* @opmaps vexgrp17
1897	* @opcode /1
1898	* @opflmodify cf,pf,af,zf,sf,of
1899	* @opflclear of
1900	* @opflundef pf,af
1901	*/
1902	FNIEMOP_DEF_1(iemOp_VGrp17_blsr_By_Ey, uint8_t, bRm)
1903	{
1904	IEMOP_MNEMONIC2(VEX_VM, BLSR, blsr, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1905	IEMOP_BODY_By_Ey(blsr);
1906	}
1907
1908
1909	/**
1910	* @opmaps vexgrp17
1911	* @opcode /2
1912	* @opflmodify cf,pf,af,zf,sf,of
1913	* @opflclear zf,of
1914	* @opflundef pf,af
1915	*/
1916	FNIEMOP_DEF_1(iemOp_VGrp17_blsmsk_By_Ey, uint8_t, bRm)
1917	{
1918	IEMOP_MNEMONIC2(VEX_VM, BLSMSK, blsmsk, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1919	IEMOP_BODY_By_Ey(blsmsk);
1920	}
1921
1922
1923	/**
1924	* @opmaps vexgrp17
1925	* @opcode /3
1926	* @opflmodify cf,pf,af,zf,sf,of
1927	* @opflclear of
1928	* @opflundef pf,af
1929	*/
1930	FNIEMOP_DEF_1(iemOp_VGrp17_blsi_By_Ey, uint8_t, bRm)
1931	{
1932	IEMOP_MNEMONIC2(VEX_VM, BLSI, blsi, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1933	IEMOP_BODY_By_Ey(blsi);
1934	}
1935
1936
1937	/* Opcode VEX.F3.0F38 0xf3 /4 - invalid. */
1938	/* Opcode VEX.F3.0F38 0xf3 /5 - invalid. */
1939	/* Opcode VEX.F3.0F38 0xf3 /6 - invalid. */
1940	/* Opcode VEX.F3.0F38 0xf3 /7 - invalid. */
1941
1942	/**
1943	* Group 17 jump table for the VEX.F3 variant.
1944	*/
1945	IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =
1946	{
1947	/* /0 */ iemOp_InvalidWithRM,
1948	/* /1 */ iemOp_VGrp17_blsr_By_Ey,
1949	/* /2 */ iemOp_VGrp17_blsmsk_By_Ey,
1950	/* /3 */ iemOp_VGrp17_blsi_By_Ey,
1951	/* /4 */ iemOp_InvalidWithRM,
1952	/* /5 */ iemOp_InvalidWithRM,
1953	/* /6 */ iemOp_InvalidWithRM,
1954	/* /7 */ iemOp_InvalidWithRM
1955	};
1956	AssertCompile(RT_ELEMENTS(g_apfnVexGroup17_f3) == 8);
1957
1958	/** Opcode VEX.F3.0F38 0xf3 - invalid (vex only - group 17). */
1959	FNIEMOP_DEF(iemOp_VGrp17_f3)
1960	{
1961	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1962	return FNIEMOP_CALL_1(g_apfnVexGroup17_f3[IEM_GET_MODRM_REG_8(bRm)], bRm);
1963	}
1964
1965	/* Opcode VEX.F2.0F38 0xf3 - invalid (vex only - group 17). */
1966
1967
1968	/* Opcode VEX.0F38 0xf4 - invalid. */
1969	/* Opcode VEX.66.0F38 0xf4 - invalid. */
1970	/* Opcode VEX.F3.0F38 0xf4 - invalid. */
1971	/* Opcode VEX.F2.0F38 0xf4 - invalid. */
1972
1973	/** Body for BZHI, BEXTR, ++; assumes VEX.L must be 0. */
1974	#define IEMOP_BODY_Gy_Ey_By(a_Instr, a_fFeatureMember, a_fUndefFlags) \
1975	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
1976	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1977	if (IEM_IS_MODRM_REG_MODE(bRm)) \
1978	{ \
1979	/* \
1980	* Register, register. \
1981	*/ \
1982	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1983	{ \
1984	IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT, 0); \
1985	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
1986	IEM_MC_ARG(uint64_t *, pDst, 0); \
1987	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1988	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1989	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1990	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1991	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1992	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1993	IEM_MC_REF_EFLAGS(pEFlags); \
1994	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1995	iemAImpl_ ## a_Instr ## _u64_fallback), \
1996	pDst, uSrc1, uSrc2, pEFlags); \
1997	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1998	IEM_MC_END(); \
1999	} \
2000	else \
2001	{ \
2002	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
2003	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2004	IEM_MC_ARG(uint32_t *, pDst, 0); \
2005	IEM_MC_ARG(uint32_t, uSrc1, 1); \
2006	IEM_MC_ARG(uint32_t, uSrc2, 2); \
2007	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
2008	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2009	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2010	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2011	IEM_MC_REF_EFLAGS(pEFlags); \
2012	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
2013	iemAImpl_ ## a_Instr ## _u32_fallback), \
2014	pDst, uSrc1, uSrc2, pEFlags); \
2015	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2016	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2017	IEM_MC_END(); \
2018	} \
2019	} \
2020	else \
2021	{ \
2022	/* \
2023	* Register, memory. \
2024	*/ \
2025	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2026	{ \
2027	IEM_MC_BEGIN(4, 1, IEM_MC_F_64BIT, 0); \
2028	IEM_MC_ARG(uint64_t *, pDst, 0); \
2029	IEM_MC_ARG(uint64_t, uSrc1, 1); \
2030	IEM_MC_ARG(uint64_t, uSrc2, 2); \
2031	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
2032	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2033	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2034	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2035	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2036	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2037	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2038	IEM_MC_REF_EFLAGS(pEFlags); \
2039	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
2040	iemAImpl_ ## a_Instr ## _u64_fallback), \
2041	pDst, uSrc1, uSrc2, pEFlags); \
2042	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2043	IEM_MC_END(); \
2044	} \
2045	else \
2046	{ \
2047	IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0); \
2048	IEM_MC_ARG(uint32_t *, pDst, 0); \
2049	IEM_MC_ARG(uint32_t, uSrc1, 1); \
2050	IEM_MC_ARG(uint32_t, uSrc2, 2); \
2051	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
2052	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2053	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2054	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2055	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2056	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2057	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2058	IEM_MC_REF_EFLAGS(pEFlags); \
2059	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
2060	iemAImpl_ ## a_Instr ## _u32_fallback), \
2061	pDst, uSrc1, uSrc2, pEFlags); \
2062	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2063	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2064	IEM_MC_END(); \
2065	} \
2066	} \
2067	(void)0
2068
2069	/** Body for SARX, SHLX, SHRX; assumes VEX.L must be 0. */
2070	#define IEMOP_BODY_Gy_Ey_By_NoEflags(a_Instr, a_fFeatureMember) \
2071	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
2072	if (IEM_IS_MODRM_REG_MODE(bRm)) \
2073	{ \
2074	/* \
2075	* Register, register. \
2076	*/ \
2077	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2078	{ \
2079	IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
2080	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2081	IEM_MC_ARG(uint64_t *, pDst, 0); \
2082	IEM_MC_ARG(uint64_t, uSrc1, 1); \
2083	IEM_MC_ARG(uint64_t, uSrc2, 2); \
2084	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2085	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2086	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2087	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
2088	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
2089	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2090	IEM_MC_END(); \
2091	} \
2092	else \
2093	{ \
2094	IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
2095	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2096	IEM_MC_ARG(uint32_t *, pDst, 0); \
2097	IEM_MC_ARG(uint32_t, uSrc1, 1); \
2098	IEM_MC_ARG(uint32_t, uSrc2, 2); \
2099	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2100	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2101	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2102	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
2103	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
2104	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2105	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2106	IEM_MC_END(); \
2107	} \
2108	} \
2109	else \
2110	{ \
2111	/* \
2112	* Register, memory. \
2113	*/ \
2114	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2115	{ \
2116	IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0); \
2117	IEM_MC_ARG(uint64_t *, pDst, 0); \
2118	IEM_MC_ARG(uint64_t, uSrc1, 1); \
2119	IEM_MC_ARG(uint64_t, uSrc2, 2); \
2120	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2121	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2122	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2123	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2124	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2125	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2126	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
2127	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
2128	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2129	IEM_MC_END(); \
2130	} \
2131	else \
2132	{ \
2133	IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0); \
2134	IEM_MC_ARG(uint32_t *, pDst, 0); \
2135	IEM_MC_ARG(uint32_t, uSrc1, 1); \
2136	IEM_MC_ARG(uint32_t, uSrc2, 2); \
2137	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2138	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2139	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2140	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2141	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2142	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2143	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
2144	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
2145	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2146	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2147	IEM_MC_END(); \
2148	} \
2149	} \
2150	(void)0
2151
2152	/**
2153	* @opcode 0xf5
2154	* @oppfx none
2155	* @opflmodify cf,pf,af,zf,sf,of
2156	* @opflclear of
2157	* @opflundef pf,af
2158	* @note VEX only
2159	*/
2160	FNIEMOP_DEF(iemOp_bzhi_Gy_Ey_By)
2161	{
2162	IEMOP_MNEMONIC3(VEX_RMV, BZHI, bzhi, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2163	IEMOP_BODY_Gy_Ey_By(bzhi, fBmi2, X86_EFL_AF \| X86_EFL_PF);
2164	}
2165
2166	/* Opcode VEX.66.0F38 0xf5 - invalid. */
2167
2168	/** Body for PDEP and PEXT (similar to ANDN, except no EFLAGS). */
2169	#define IEMOP_BODY_Gy_By_Ey_NoEflags(a_Instr, a_fFeatureMember) \
2170	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
2171	if (IEM_IS_MODRM_REG_MODE(bRm)) \
2172	{ \
2173	/* \
2174	* Register, register. \
2175	*/ \
2176	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2177	{ \
2178	IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0); \
2179	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2180	IEM_MC_ARG(uint64_t *, pDst, 0); \
2181	IEM_MC_ARG(uint64_t, uSrc1, 1); \
2182	IEM_MC_ARG(uint64_t, uSrc2, 2); \
2183	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2184	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2185	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2186	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
2187	iemAImpl_ ## a_Instr ## _u64, \
2188	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
2189	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2190	IEM_MC_END(); \
2191	} \
2192	else \
2193	{ \
2194	IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0); \
2195	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2196	IEM_MC_ARG(uint32_t *, pDst, 0); \
2197	IEM_MC_ARG(uint32_t, uSrc1, 1); \
2198	IEM_MC_ARG(uint32_t, uSrc2, 2); \
2199	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2200	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2201	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2202	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
2203	iemAImpl_ ## a_Instr ## _u32, \
2204	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
2205	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2206	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2207	IEM_MC_END(); \
2208	} \
2209	} \
2210	else \
2211	{ \
2212	/* \
2213	* Register, memory. \
2214	*/ \
2215	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2216	{ \
2217	IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0); \
2218	IEM_MC_ARG(uint64_t *, pDst, 0); \
2219	IEM_MC_ARG(uint64_t, uSrc1, 1); \
2220	IEM_MC_ARG(uint64_t, uSrc2, 2); \
2221	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2222	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2223	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2224	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2225	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2226	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2227	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
2228	iemAImpl_ ## a_Instr ## _u64, \
2229	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
2230	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2231	IEM_MC_END(); \
2232	} \
2233	else \
2234	{ \
2235	IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0); \
2236	IEM_MC_ARG(uint32_t *, pDst, 0); \
2237	IEM_MC_ARG(uint32_t, uSrc1, 1); \
2238	IEM_MC_ARG(uint32_t, uSrc2, 2); \
2239	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2240	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2241	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2242	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2243	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2244	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2245	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
2246	iemAImpl_ ## a_Instr ## _u32, \
2247	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
2248	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2249	IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2250	IEM_MC_END(); \
2251	} \
2252	} \
2253	(void)0
2254
2255
2256	/** Opcode VEX.F3.0F38 0xf5 (vex only). */
2257	FNIEMOP_DEF(iemOp_pext_Gy_By_Ey)
2258	{
2259	IEMOP_MNEMONIC3(VEX_RVM, PEXT, pext, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2260	IEMOP_BODY_Gy_By_Ey_NoEflags(pext, fBmi2);
2261	}
2262
2263
2264	/** Opcode VEX.F2.0F38 0xf5 (vex only). */
2265	FNIEMOP_DEF(iemOp_pdep_Gy_By_Ey)
2266	{
2267	IEMOP_MNEMONIC3(VEX_RVM, PDEP, pdep, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2268	IEMOP_BODY_Gy_By_Ey_NoEflags(pdep, fBmi2);
2269	}
2270
2271
2272	/* Opcode VEX.0F38 0xf6 - invalid. */
2273	/* Opcode VEX.66.0F38 0xf6 - invalid (legacy only). */
2274	/* Opcode VEX.F3.0F38 0xf6 - invalid (legacy only). */
2275
2276
2277	/**
2278	* @opcode 0xf6
2279	* @oppfx 0xf2
2280	* @opflclass unchanged
2281	*/
2282	FNIEMOP_DEF(iemOp_mulx_By_Gy_rDX_Ey)
2283	{
2284	IEMOP_MNEMONIC4(VEX_RVM, MULX, mulx, Gy, By, Ey, rDX, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2285	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2286	if (IEM_IS_MODRM_REG_MODE(bRm))
2287	{
2288	/*
2289	* Register, register.
2290	*/
2291	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2292	{
2293	IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT, 0);
2294	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
2295	IEM_MC_ARG(uint64_t *, pDst1, 0);
2296	IEM_MC_ARG(uint64_t *, pDst2, 1);
2297	IEM_MC_ARG(uint64_t, uSrc1, 2);
2298	IEM_MC_ARG(uint64_t, uSrc2, 3);
2299	IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
2300	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2301	IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
2302	IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
2303	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
2304	pDst1, pDst2, uSrc1, uSrc2);
2305	IEM_MC_ADVANCE_RIP_AND_FINISH();
2306	IEM_MC_END();
2307	}
2308	else
2309	{
2310	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
2311	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
2312	IEM_MC_ARG(uint32_t *, pDst1, 0);
2313	IEM_MC_ARG(uint32_t *, pDst2, 1);
2314	IEM_MC_ARG(uint32_t, uSrc1, 2);
2315	IEM_MC_ARG(uint32_t, uSrc2, 3);
2316	IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
2317	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2318	IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
2319	IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
2320	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
2321	pDst1, pDst2, uSrc1, uSrc2);
2322	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu));
2323	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
2324	IEM_MC_ADVANCE_RIP_AND_FINISH();
2325	IEM_MC_END();
2326	}
2327	}
2328	else
2329	{
2330	/*
2331	* Register, memory.
2332	*/
2333	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2334	{
2335	IEM_MC_BEGIN(4, 1, IEM_MC_F_64BIT, 0);
2336	IEM_MC_ARG(uint64_t *, pDst1, 0);
2337	IEM_MC_ARG(uint64_t *, pDst2, 1);
2338	IEM_MC_ARG(uint64_t, uSrc1, 2);
2339	IEM_MC_ARG(uint64_t, uSrc2, 3);
2340	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2341	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2342	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
2343	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2344	IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
2345	IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
2346	IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
2347	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
2348	pDst1, pDst2, uSrc1, uSrc2);
2349	IEM_MC_ADVANCE_RIP_AND_FINISH();
2350	IEM_MC_END();
2351	}
2352	else
2353	{
2354	IEM_MC_BEGIN(4, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
2355	IEM_MC_ARG(uint32_t *, pDst1, 0);
2356	IEM_MC_ARG(uint32_t *, pDst2, 1);
2357	IEM_MC_ARG(uint32_t, uSrc1, 2);
2358	IEM_MC_ARG(uint32_t, uSrc2, 3);
2359	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2360	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2361	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
2362	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2363	IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
2364	IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
2365	IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
2366	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
2367	pDst1, pDst2, uSrc1, uSrc2);
2368	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu));
2369	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
2370	IEM_MC_ADVANCE_RIP_AND_FINISH();
2371	IEM_MC_END();
2372	}
2373	}
2374	}
2375
2376
2377	/**
2378	* @opcode 0xf7
2379	* @oppfx none
2380	* @opflmodify cf,pf,af,zf,sf,of
2381	* @opflclear cf,of
2382	* @opflundef pf,af,sf
2383	*/
2384	FNIEMOP_DEF(iemOp_bextr_Gy_Ey_By)
2385	{
2386	IEMOP_MNEMONIC3(VEX_RMV, BEXTR, bextr, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2387	IEMOP_BODY_Gy_Ey_By(bextr, fBmi1, X86_EFL_SF \| X86_EFL_AF \| X86_EFL_PF);
2388	}
2389
2390
2391	/**
2392	* @opcode 0xf7
2393	* @oppfx 0x66
2394	* @opflclass unchanged
2395	*/
2396	FNIEMOP_DEF(iemOp_shlx_Gy_Ey_By)
2397	{
2398	IEMOP_MNEMONIC3(VEX_RMV, SHLX, shlx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2399	IEMOP_BODY_Gy_Ey_By_NoEflags(shlx, fBmi2);
2400	}
2401
2402
2403	/**
2404	* @opcode 0xf7
2405	* @oppfx 0xf3
2406	* @opflclass unchanged
2407	*/
2408	FNIEMOP_DEF(iemOp_sarx_Gy_Ey_By)
2409	{
2410	IEMOP_MNEMONIC3(VEX_RMV, SARX, sarx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2411	IEMOP_BODY_Gy_Ey_By_NoEflags(sarx, fBmi2);
2412	}
2413
2414
2415	/**
2416	* @opcode 0xf7
2417	* @oppfx 0xf2
2418	* @opflclass unchanged
2419	*/
2420	FNIEMOP_DEF(iemOp_shrx_Gy_Ey_By)
2421	{
2422	IEMOP_MNEMONIC3(VEX_RMV, SHRX, shrx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2423	IEMOP_BODY_Gy_Ey_By_NoEflags(shrx, fBmi2);
2424	}
2425
2426	/* Opcode VEX.0F38 0xf8 - invalid. */
2427	/* Opcode VEX.66.0F38 0xf8 - invalid. */
2428	/* Opcode VEX.F3.0F38 0xf8 - invalid. */
2429	/* Opcode VEX.F2.0F38 0xf8 - invalid. */
2430
2431	/* Opcode VEX.0F38 0xf9 - invalid. */
2432	/* Opcode VEX.66.0F38 0xf9 - invalid. */
2433	/* Opcode VEX.F3.0F38 0xf9 - invalid. */
2434	/* Opcode VEX.F2.0F38 0xf9 - invalid. */
2435
2436	/* Opcode VEX.0F38 0xfa - invalid. */
2437	/* Opcode VEX.66.0F38 0xfa - invalid. */
2438	/* Opcode VEX.F3.0F38 0xfa - invalid. */
2439	/* Opcode VEX.F2.0F38 0xfa - invalid. */
2440
2441	/* Opcode VEX.0F38 0xfb - invalid. */
2442	/* Opcode VEX.66.0F38 0xfb - invalid. */
2443	/* Opcode VEX.F3.0F38 0xfb - invalid. */
2444	/* Opcode VEX.F2.0F38 0xfb - invalid. */
2445
2446	/* Opcode VEX.0F38 0xfc - invalid. */
2447	/* Opcode VEX.66.0F38 0xfc - invalid. */
2448	/* Opcode VEX.F3.0F38 0xfc - invalid. */
2449	/* Opcode VEX.F2.0F38 0xfc - invalid. */
2450
2451	/* Opcode VEX.0F38 0xfd - invalid. */
2452	/* Opcode VEX.66.0F38 0xfd - invalid. */
2453	/* Opcode VEX.F3.0F38 0xfd - invalid. */
2454	/* Opcode VEX.F2.0F38 0xfd - invalid. */
2455
2456	/* Opcode VEX.0F38 0xfe - invalid. */
2457	/* Opcode VEX.66.0F38 0xfe - invalid. */
2458	/* Opcode VEX.F3.0F38 0xfe - invalid. */
2459	/* Opcode VEX.F2.0F38 0xfe - invalid. */
2460
2461	/* Opcode VEX.0F38 0xff - invalid. */
2462	/* Opcode VEX.66.0F38 0xff - invalid. */
2463	/* Opcode VEX.F3.0F38 0xff - invalid. */
2464	/* Opcode VEX.F2.0F38 0xff - invalid. */
2465
2466
2467	/**
2468	* VEX opcode map \#2.
2469	*
2470	* @sa g_apfnThreeByte0f38
2471	*/
2472	const PFNIEMOP g_apfnVexMap2[] =
2473	{
2474	/* no prefix, 066h prefix f3h prefix, f2h prefix */
2475	/* 0x00 */ iemOp_InvalidNeedRM, iemOp_vpshufb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2476	/* 0x01 */ iemOp_InvalidNeedRM, iemOp_vphaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2477	/* 0x02 */ iemOp_InvalidNeedRM, iemOp_vphaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2478	/* 0x03 */ iemOp_InvalidNeedRM, iemOp_vphaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2479	/* 0x04 */ iemOp_InvalidNeedRM, iemOp_vpmaddubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2480	/* 0x05 */ iemOp_InvalidNeedRM, iemOp_vphsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2481	/* 0x06 */ iemOp_InvalidNeedRM, iemOp_vphsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2482	/* 0x07 */ iemOp_InvalidNeedRM, iemOp_vphsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2483	/* 0x08 */ iemOp_InvalidNeedRM, iemOp_vpsignb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2484	/* 0x09 */ iemOp_InvalidNeedRM, iemOp_vpsignw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2485	/* 0x0a */ iemOp_InvalidNeedRM, iemOp_vpsignd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2486	/* 0x0b */ iemOp_InvalidNeedRM, iemOp_vpmulhrsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2487	/* 0x0c */ iemOp_InvalidNeedRM, iemOp_vpermilps_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2488	/* 0x0d */ iemOp_InvalidNeedRM, iemOp_vpermilpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2489	/* 0x0e */ iemOp_InvalidNeedRM, iemOp_vtestps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2490	/* 0x0f */ iemOp_InvalidNeedRM, iemOp_vtestpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2491
2492	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRM),
2493	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
2494	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
2495	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
2496	/* 0x14 */ IEMOP_X4(iemOp_InvalidNeedRM),
2497	/* 0x15 */ IEMOP_X4(iemOp_InvalidNeedRM),
2498	/* 0x16 */ iemOp_InvalidNeedRM, iemOp_vpermps_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2499	/* 0x17 */ iemOp_InvalidNeedRM, iemOp_vptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2500	/* 0x18 */ iemOp_InvalidNeedRM, iemOp_vbroadcastss_Vx_Wd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2501	/* 0x19 */ iemOp_InvalidNeedRM, iemOp_vbroadcastsd_Vqq_Wq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2502	/* 0x1a */ iemOp_InvalidNeedRM, iemOp_vbroadcastf128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2503	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
2504	/* 0x1c */ iemOp_InvalidNeedRM, iemOp_vpabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2505	/* 0x1d */ iemOp_InvalidNeedRM, iemOp_vpabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2506	/* 0x1e */ iemOp_InvalidNeedRM, iemOp_vpabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2507	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
2508
2509	/* 0x20 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2510	/* 0x21 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2511	/* 0x22 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2512	/* 0x23 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2513	/* 0x24 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2514	/* 0x25 */ iemOp_InvalidNeedRM, iemOp_vpmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2515	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
2516	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
2517	/* 0x28 */ iemOp_InvalidNeedRM, iemOp_vpmuldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2518	/* 0x29 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2519	/* 0x2a */ iemOp_InvalidNeedRM, iemOp_vmovntdqa_Vx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2520	/* 0x2b */ iemOp_InvalidNeedRM, iemOp_vpackusdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2521	/* 0x2c */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2522	/* 0x2d */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2523	/* 0x2e */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2524	/* 0x2f */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2525
2526	/* 0x30 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2527	/* 0x31 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2528	/* 0x32 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2529	/* 0x33 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2530	/* 0x34 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2531	/* 0x35 */ iemOp_InvalidNeedRM, iemOp_vpmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2532	/* 0x36 */ iemOp_InvalidNeedRM, iemOp_vpermd_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2533	/* 0x37 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2534	/* 0x38 */ iemOp_InvalidNeedRM, iemOp_vpminsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2535	/* 0x39 */ iemOp_InvalidNeedRM, iemOp_vpminsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2536	/* 0x3a */ iemOp_InvalidNeedRM, iemOp_vpminuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2537	/* 0x3b */ iemOp_InvalidNeedRM, iemOp_vpminud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2538	/* 0x3c */ iemOp_InvalidNeedRM, iemOp_vpmaxsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2539	/* 0x3d */ iemOp_InvalidNeedRM, iemOp_vpmaxsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2540	/* 0x3e */ iemOp_InvalidNeedRM, iemOp_vpmaxuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2541	/* 0x3f */ iemOp_InvalidNeedRM, iemOp_vpmaxud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2542
2543	/* 0x40 */ iemOp_InvalidNeedRM, iemOp_vpmulld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2544	/* 0x41 */ iemOp_InvalidNeedRM, iemOp_vphminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2545	/* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
2546	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
2547	/* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
2548	/* 0x45 */ iemOp_InvalidNeedRM, iemOp_vpsrlvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2549	/* 0x46 */ iemOp_InvalidNeedRM, iemOp_vpsravd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2550	/* 0x47 */ iemOp_InvalidNeedRM, iemOp_vpsllvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2551	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
2552	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
2553	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
2554	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
2555	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
2556	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
2557	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
2558	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
2559
2560	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
2561	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
2562	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
2563	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
2564	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
2565	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
2566	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
2567	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
2568	/* 0x58 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2569	/* 0x59 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2570	/* 0x5a */ iemOp_InvalidNeedRM, iemOp_vbroadcasti128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2571	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
2572	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
2573	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
2574	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
2575	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
2576
2577	/* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
2578	/* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
2579	/* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
2580	/* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
2581	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
2582	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
2583	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
2584	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
2585	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
2586	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
2587	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
2588	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
2589	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
2590	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
2591	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
2592	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
2593
2594	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
2595	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
2596	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
2597	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
2598	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
2599	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
2600	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
2601	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
2602	/* 0x78 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2603	/* 0x79 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2604	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
2605	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
2606	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
2607	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
2608	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
2609	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
2610
2611	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
2612	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
2613	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
2614	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
2615	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
2616	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
2617	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
2618	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
2619	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
2620	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
2621	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
2622	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
2623	/* 0x8c */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2624	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
2625	/* 0x8e */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Mx_Vx_Hx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2626	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
2627
2628	/* 0x90 */ iemOp_InvalidNeedRM, iemOp_vgatherdd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2629	/* 0x91 */ iemOp_InvalidNeedRM, iemOp_vgatherqd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2630	/* 0x92 */ iemOp_InvalidNeedRM, iemOp_vgatherdps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2631	/* 0x93 */ iemOp_InvalidNeedRM, iemOp_vgatherqps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2632	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
2633	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
2634	/* 0x96 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub132ps_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2635	/* 0x97 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2636	/* 0x98 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2637	/* 0x99 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2638	/* 0x9a */ iemOp_InvalidNeedRM, iemOp_vfmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2639	/* 0x9b */ iemOp_InvalidNeedRM, iemOp_vfmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2640	/* 0x9c */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2641	/* 0x9d */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2642	/* 0x9e */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2643	/* 0x9f */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2644
2645	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2646	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2647	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2648	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2649	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2650	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2651	/* 0xa6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2652	/* 0xa7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2653	/* 0xa8 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2654	/* 0xa9 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2655	/* 0xaa */ iemOp_InvalidNeedRM, iemOp_vfmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2656	/* 0xab */ iemOp_InvalidNeedRM, iemOp_vfmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2657	/* 0xac */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2658	/* 0xad */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2659	/* 0xae */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2660	/* 0xaf */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2661
2662	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2663	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2664	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2665	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2666	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2667	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2668	/* 0xb6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2669	/* 0xb7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2670	/* 0xb8 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2671	/* 0xb9 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2672	/* 0xba */ iemOp_InvalidNeedRM, iemOp_vfmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2673	/* 0xbb */ iemOp_InvalidNeedRM, iemOp_vfmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2674	/* 0xbc */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2675	/* 0xbd */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2676	/* 0xbe */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2677	/* 0xbf */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2678
2679	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2680	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2681	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2682	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2683	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2684	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2685	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2686	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2687	/* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2688	/* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2689	/* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
2690	/* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
2691	/* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
2692	/* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
2693	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
2694	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
2695
2696	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2697	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2698	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2699	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2700	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2701	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2702	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2703	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2704	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2705	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2706	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
2707	/* 0xdb */ iemOp_InvalidNeedRM, iemOp_vaesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2708	/* 0xdc */ iemOp_InvalidNeedRM, iemOp_vaesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2709	/* 0xdd */ iemOp_InvalidNeedRM, iemOp_vaesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2710	/* 0xde */ iemOp_InvalidNeedRM, iemOp_vaesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2711	/* 0xdf */ iemOp_InvalidNeedRM, iemOp_vaesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2712
2713	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2714	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2715	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2716	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2717	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2718	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2719	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2720	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2721	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2722	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2723	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
2724	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
2725	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
2726	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
2727	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
2728	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
2729
2730	/* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2731	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2732	/* 0xf2 */ iemOp_andn_Gy_By_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2733	/* 0xf3 */ iemOp_VGrp17_f3, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2734	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2735	/* 0xf5 */ iemOp_bzhi_Gy_Ey_By, iemOp_InvalidNeedRM, iemOp_pext_Gy_By_Ey, iemOp_pdep_Gy_By_Ey,
2736	/* 0xf6 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_mulx_By_Gy_rDX_Ey,
2737	/* 0xf7 */ iemOp_bextr_Gy_Ey_By, iemOp_shlx_Gy_Ey_By, iemOp_sarx_Gy_Ey_By, iemOp_shrx_Gy_Ey_By,
2738	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2739	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2740	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
2741	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
2742	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
2743	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
2744	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
2745	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
2746	};
2747	AssertCompile(RT_ELEMENTS(g_apfnVexMap2) == 1024);
2748
2749	/** @} */
2750

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap2.cpp.h@ 103836

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