VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap2.cpp.h@ 104192

Last change on this file since 104192 was 104192, checked in by vboxsync, 11 months ago

VMM/IEM: Fix one more incorrect (missing) instruction name / decoding, bugref:9898
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File size: 111.4 KB
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1/* $Id: IEMAllInstVexMap2.cpp.h 104192 2024-04-05 13:38:14Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstThree0f38.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 2
33 * @{
34 */
35
36/* Opcode VEX.0F38 0x00 - invalid. */
37
38
39/** Opcode VEX.66.0F38 0x00. */
40FNIEMOP_DEF(iemOp_vpshufb_Vx_Hx_Wx)
41{
42 IEMOP_MNEMONIC3(VEX_RVM, VPSHUFB, vpshufb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
43 IEMOPMEDIAOPTF3_INIT_VARS( vpshufb);
44 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
45}
46
47
48/* Opcode VEX.0F38 0x01 - invalid. */
49
50
51/** Opcode VEX.66.0F38 0x01. */
52FNIEMOP_DEF(iemOp_vphaddw_Vx_Hx_Wx)
53{
54 IEMOP_MNEMONIC3(VEX_RVM, VPHADDW, vphaddw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
55 IEMOPMEDIAOPTF3_INIT_VARS(vphaddw);
56 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
57}
58
59
60/* Opcode VEX.0F38 0x02 - invalid. */
61
62
63/** Opcode VEX.66.0F38 0x02. */
64FNIEMOP_DEF(iemOp_vphaddd_Vx_Hx_Wx)
65{
66 IEMOP_MNEMONIC3(VEX_RVM, VPHADDD, vphaddd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
67 IEMOPMEDIAOPTF3_INIT_VARS(vphaddd);
68 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
69}
70
71
72/* Opcode VEX.0F38 0x03 - invalid. */
73
74
75/** Opcode VEX.66.0F38 0x03. */
76FNIEMOP_DEF(iemOp_vphaddsw_Vx_Hx_Wx)
77{
78 IEMOP_MNEMONIC3(VEX_RVM, VPHADDSW, vphaddsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
79 IEMOPMEDIAOPTF3_INIT_VARS(vphaddsw);
80 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
81}
82
83
84/* Opcode VEX.0F38 0x04 - invalid. */
85
86
87/** Opcode VEX.66.0F38 0x04. */
88FNIEMOP_DEF(iemOp_vpmaddubsw_Vx_Hx_Wx)
89{
90 IEMOP_MNEMONIC3(VEX_RVM, VPMADDUBSW, vpmaddubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
91 IEMOPMEDIAOPTF3_INIT_VARS(vpmaddubsw);
92 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
93}
94
95
96/* Opcode VEX.0F38 0x05 - invalid. */
97
98
99/** Opcode VEX.66.0F38 0x05. */
100FNIEMOP_DEF(iemOp_vphsubw_Vx_Hx_Wx)
101{
102 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBW, vphsubw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
103 IEMOPMEDIAOPTF3_INIT_VARS(vphsubw);
104 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
105}
106
107
108/* Opcode VEX.0F38 0x06 - invalid. */
109
110
111/** Opcode VEX.66.0F38 0x06. */
112FNIEMOP_DEF(iemOp_vphsubd_Vx_Hx_Wx)
113{
114 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBD, vphsubd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
115 IEMOPMEDIAOPTF3_INIT_VARS(vphsubd);
116 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
117}
118
119
120/* Opcode VEX.0F38 0x07 - invalid. */
121
122
123/** Opcode VEX.66.0F38 0x07. */
124FNIEMOP_DEF(iemOp_vphsubsw_Vx_Hx_Wx)
125{
126 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBSW, vphsubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
127 IEMOPMEDIAOPTF3_INIT_VARS(vphsubsw);
128 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
129}
130
131
132/* Opcode VEX.0F38 0x08 - invalid. */
133
134
135/** Opcode VEX.66.0F38 0x08. */
136FNIEMOP_DEF(iemOp_vpsignb_Vx_Hx_Wx)
137{
138 IEMOP_MNEMONIC3(VEX_RVM, VPSIGNB, vpsignb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
139 IEMOPMEDIAOPTF3_INIT_VARS(vpsignb);
140 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
141}
142
143
144/* Opcode VEX.0F38 0x09 - invalid. */
145
146
147/** Opcode VEX.66.0F38 0x09. */
148FNIEMOP_DEF(iemOp_vpsignw_Vx_Hx_Wx)
149{
150 IEMOP_MNEMONIC3(VEX_RVM, VPSIGNW, vpsignw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
151 IEMOPMEDIAOPTF3_INIT_VARS(vpsignw);
152 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
153}
154
155
156/* Opcode VEX.0F38 0x0a - invalid. */
157
158
159/** Opcode VEX.66.0F38 0x0a. */
160FNIEMOP_DEF(iemOp_vpsignd_Vx_Hx_Wx)
161{
162 IEMOP_MNEMONIC3(VEX_RVM, VPSIGND, vpsignd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
163 IEMOPMEDIAOPTF3_INIT_VARS(vpsignd);
164 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
165}
166
167
168/* Opcode VEX.0F38 0x0b - invalid. */
169
170
171/** Opcode VEX.66.0F38 0x0b. */
172FNIEMOP_DEF(iemOp_vpmulhrsw_Vx_Hx_Wx)
173{
174 IEMOP_MNEMONIC3(VEX_RVM, VPMULHRSW, vpmulhrsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
175 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhrsw);
176 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
177}
178
179
180/* Opcode VEX.0F38 0x0c - invalid. */
181
182
183/** Opcode VEX.66.0F38 0x0c.
184 * AVX,AVX */
185FNIEMOP_DEF(iemOp_vpermilps_Vx_Hx_Wx)
186{
187 IEMOP_MNEMONIC3(VEX_RVM, VPERMILPS, vpermilps, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
188 IEMOPMEDIAOPTF3_INIT_VARS(vpermilps);
189 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
190}
191
192
193/* Opcode VEX.0F38 0x0d - invalid. */
194
195
196/** Opcode VEX.66.0F38 0x0d.
197 * AVX,AVX */
198FNIEMOP_DEF(iemOp_vpermilpd_Vx_Hx_Wx)
199{
200 IEMOP_MNEMONIC3(VEX_RVM, VPERMILPD, vpermilpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
201 IEMOPMEDIAOPTF3_INIT_VARS(vpermilpd);
202 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
203}
204
205
206/* Opcode VEX.0F38 0x0e - invalid. */
207/** Opcode VEX.66.0F38 0x0e. */
208FNIEMOP_STUB(iemOp_vtestps_Vx_Wx);
209/* Opcode VEX.0F38 0x0f - invalid. */
210/** Opcode VEX.66.0F38 0x0f. */
211FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx);
212
213
214/* Opcode VEX.0F38 0x10 - invalid */
215/* Opcode VEX.66.0F38 0x10 - invalid (legacy only). */
216/* Opcode VEX.0F38 0x11 - invalid */
217/* Opcode VEX.66.0F38 0x11 - invalid */
218/* Opcode VEX.0F38 0x12 - invalid */
219/* Opcode VEX.66.0F38 0x12 - invalid */
220/* Opcode VEX.0F38 0x13 - invalid */
221/* Opcode VEX.66.0F38 0x13 (vex only). */
222FNIEMOP_STUB(iemOp_vcvtph2ps_Vx_Wx);
223/* Opcode VEX.0F38 0x14 - invalid */
224/* Opcode VEX.66.0F38 0x14 - invalid (legacy only). */
225/* Opcode VEX.0F38 0x15 - invalid */
226/* Opcode VEX.66.0F38 0x15 - invalid (legacy only). */
227/* Opcode VEX.0F38 0x16 - invalid */
228/** Opcode VEX.66.0F38 0x16. */
229FNIEMOP_STUB(iemOp_vpermps_Vqq_Hqq_Wqq);
230/* Opcode VEX.0F38 0x17 - invalid */
231
232
233/**
234 * @opcode 0x17
235 * @oppfx 0x66
236 * @opflmodify cf,pf,af,zf,sf,of
237 * @opflclear pf,af,sf,of
238 */
239FNIEMOP_DEF(iemOp_vptest_Vx_Wx)
240{
241 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
242 if (IEM_IS_MODRM_REG_MODE(bRm))
243 {
244 /*
245 * Register, register.
246 */
247 if (pVCpu->iem.s.uVexLength)
248 {
249 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
250 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
251 IEM_MC_LOCAL(RTUINT256U, uSrc1);
252 IEM_MC_LOCAL(RTUINT256U, uSrc2);
253 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
254 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
255 IEM_MC_ARG(uint32_t *, pEFlags, 2);
256 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
257 IEM_MC_PREPARE_AVX_USAGE();
258 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
259 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
260 IEM_MC_REF_EFLAGS(pEFlags);
261 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
262 puSrc1, puSrc2, pEFlags);
263 IEM_MC_ADVANCE_RIP_AND_FINISH();
264 IEM_MC_END();
265 }
266 else
267 {
268 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
269 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
270 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
271 IEM_MC_ARG(PCRTUINT128U, puSrc2, 1);
272 IEM_MC_ARG(uint32_t *, pEFlags, 2);
273 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
274 IEM_MC_PREPARE_AVX_USAGE();
275 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
276 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
277 IEM_MC_REF_EFLAGS(pEFlags);
278 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
279 IEM_MC_ADVANCE_RIP_AND_FINISH();
280 IEM_MC_END();
281 }
282 }
283 else
284 {
285 /*
286 * Register, memory.
287 */
288 if (pVCpu->iem.s.uVexLength)
289 {
290 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
291 IEM_MC_LOCAL(RTUINT256U, uSrc1);
292 IEM_MC_LOCAL(RTUINT256U, uSrc2);
293 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
294 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
295 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
296 IEM_MC_ARG(uint32_t *, pEFlags, 2);
297
298 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
299 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
300 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
301 IEM_MC_PREPARE_AVX_USAGE();
302
303 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
304 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
305 IEM_MC_REF_EFLAGS(pEFlags);
306 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
307 puSrc1, puSrc2, pEFlags);
308
309 IEM_MC_ADVANCE_RIP_AND_FINISH();
310 IEM_MC_END();
311 }
312 else
313 {
314 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
315 IEM_MC_LOCAL(RTUINT128U, uSrc2);
316 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
317 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
318 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1);
319 IEM_MC_ARG(uint32_t *, pEFlags, 2);
320
321 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
322 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
323 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
324 IEM_MC_PREPARE_AVX_USAGE();
325
326 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
327 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
328 IEM_MC_REF_EFLAGS(pEFlags);
329 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
330
331 IEM_MC_ADVANCE_RIP_AND_FINISH();
332 IEM_MC_END();
333 }
334 }
335}
336
337
338/* Opcode VEX.0F38 0x18 - invalid */
339
340
341/** Opcode VEX.66.0F38 0x18. */
342FNIEMOP_DEF(iemOp_vbroadcastss_Vx_Wd)
343{
344 IEMOP_MNEMONIC2(VEX_RM, VBROADCASTSS, vbroadcastss, Vx, Wx, DISOPTYPE_HARMLESS, 0);
345 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
346 if (IEM_IS_MODRM_REG_MODE(bRm))
347 {
348 /*
349 * Register, register.
350 */
351 if (pVCpu->iem.s.uVexLength)
352 {
353 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
354 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
355 IEM_MC_LOCAL(uint32_t, uSrc);
356
357 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
358 IEM_MC_PREPARE_AVX_USAGE();
359
360 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
361 IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
362
363 IEM_MC_ADVANCE_RIP_AND_FINISH();
364 IEM_MC_END();
365 }
366 else
367 {
368 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
369 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
370 IEM_MC_LOCAL(uint32_t, uSrc);
371
372 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
373 IEM_MC_PREPARE_AVX_USAGE();
374 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
375 IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
376
377 IEM_MC_ADVANCE_RIP_AND_FINISH();
378 IEM_MC_END();
379 }
380 }
381 else
382 {
383 /*
384 * Register, memory.
385 */
386 if (pVCpu->iem.s.uVexLength)
387 {
388 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
389 IEM_MC_LOCAL(uint32_t, uSrc);
390 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
391
392 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
393 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
394 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
395 IEM_MC_PREPARE_AVX_USAGE();
396
397 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
398 IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
399
400 IEM_MC_ADVANCE_RIP_AND_FINISH();
401 IEM_MC_END();
402 }
403 else
404 {
405 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
406 IEM_MC_LOCAL(uint32_t, uSrc);
407 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
408
409 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
410 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
411 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
412 IEM_MC_PREPARE_AVX_USAGE();
413
414 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
415 IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
416
417 IEM_MC_ADVANCE_RIP_AND_FINISH();
418 IEM_MC_END();
419 }
420 }
421}
422
423
424/* Opcode VEX.0F38 0x19 - invalid */
425
426
427/** Opcode VEX.66.0F38 0x19. */
428FNIEMOP_DEF(iemOp_vbroadcastsd_Vqq_Wq)
429{
430 IEMOP_MNEMONIC2(VEX_RM, VBROADCASTSD, vbroadcastsd, Vx, Wx, DISOPTYPE_HARMLESS, 0);
431 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
432 if (IEM_IS_MODRM_REG_MODE(bRm))
433 {
434 /*
435 * Register, register.
436 */
437 if (pVCpu->iem.s.uVexLength)
438 {
439 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
440 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
441 IEM_MC_LOCAL(uint64_t, uSrc);
442
443 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
444 IEM_MC_PREPARE_AVX_USAGE();
445
446 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
447 IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
448
449 IEM_MC_ADVANCE_RIP_AND_FINISH();
450 IEM_MC_END();
451 }
452 else
453 {
454 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
455 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
456 IEM_MC_LOCAL(uint64_t, uSrc);
457
458 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
459 IEM_MC_PREPARE_AVX_USAGE();
460 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
461 IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
462
463 IEM_MC_ADVANCE_RIP_AND_FINISH();
464 IEM_MC_END();
465 }
466 }
467 else
468 {
469 /*
470 * Register, memory.
471 */
472 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
473 IEM_MC_LOCAL(uint64_t, uSrc);
474 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
475
476 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
477 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx);
478 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
479 IEM_MC_PREPARE_AVX_USAGE();
480
481 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
482 IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
483
484 IEM_MC_ADVANCE_RIP_AND_FINISH();
485 IEM_MC_END();
486 }
487}
488
489
490/* Opcode VEX.0F38 0x1a - invalid */
491
492
493/** Opcode VEX.66.0F38 0x1a. */
494FNIEMOP_DEF(iemOp_vbroadcastf128_Vqq_Mdq)
495{
496 IEMOP_MNEMONIC2(VEX_RM, VBROADCASTF128, vbroadcastf128, Vx, Wx, DISOPTYPE_HARMLESS, 0);
497 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
498 if (IEM_IS_MODRM_REG_MODE(bRm))
499 {
500 /*
501 * No register, register.
502 */
503 IEMOP_RAISE_INVALID_OPCODE_RET();
504 }
505 else
506 {
507 /*
508 * Register, memory.
509 */
510 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
511 IEM_MC_LOCAL(RTUINT128U, uSrc);
512 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
513
514 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
515 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx);
516 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
517 IEM_MC_PREPARE_AVX_USAGE();
518
519 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
520 IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
521
522 IEM_MC_ADVANCE_RIP_AND_FINISH();
523 IEM_MC_END();
524 }
525}
526
527
528/* Opcode VEX.0F38 0x1b - invalid */
529/* Opcode VEX.66.0F38 0x1b - invalid */
530/* Opcode VEX.0F38 0x1c - invalid. */
531
532
533/** Opcode VEX.66.0F38 0x1c. */
534FNIEMOP_DEF(iemOp_vpabsb_Vx_Wx)
535{
536 IEMOP_MNEMONIC2(VEX_RM, VPABSB, vpabsb, Vx, Wx, DISOPTYPE_HARMLESS, 0);
537 IEMOPMEDIAOPTF2_INIT_VARS(vpabsb);
538 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
539}
540
541
542/* Opcode VEX.0F38 0x1d - invalid. */
543
544
545/** Opcode VEX.66.0F38 0x1d. */
546FNIEMOP_DEF(iemOp_vpabsw_Vx_Wx)
547{
548 IEMOP_MNEMONIC2(VEX_RM, VPABSW, vpabsw, Vx, Wx, DISOPTYPE_HARMLESS, 0);
549 IEMOPMEDIAOPTF2_INIT_VARS(vpabsw);
550 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
551}
552
553/* Opcode VEX.0F38 0x1e - invalid. */
554
555
556/** Opcode VEX.66.0F38 0x1e. */
557FNIEMOP_DEF(iemOp_vpabsd_Vx_Wx)
558{
559 IEMOP_MNEMONIC2(VEX_RM, VPABSD, vpabsd, Vx, Wx, DISOPTYPE_HARMLESS, 0);
560 IEMOPMEDIAOPTF2_INIT_VARS(vpabsd);
561 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
562}
563
564
565/* Opcode VEX.0F38 0x1f - invalid */
566/* Opcode VEX.66.0F38 0x1f - invalid */
567
568
569/** Body for the vpmov{s,z}x* instructions. */
570#define IEMOP_BODY_VPMOV_S_Z(a_Instr, a_SrcWidth, a_VexLengthMemFetch) \
571 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
572 if (IEM_IS_MODRM_REG_MODE(bRm)) \
573 { \
574 /* \
575 * Register, register. \
576 */ \
577 if (pVCpu->iem.s.uVexLength) \
578 { \
579 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
580 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2); \
581 IEM_MC_LOCAL(RTUINT256U, uDst); \
582 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
583 IEM_MC_ARG(PCRTUINT128U, puSrc, 1); \
584 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
585 IEM_MC_PREPARE_AVX_USAGE(); \
586 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
587 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
588 iemAImpl_ ## a_Instr ## _u256_fallback), \
589 puDst, puSrc); \
590 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
591 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
592 IEM_MC_END(); \
593 } \
594 else \
595 { \
596 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
597 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx); \
598 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
599 IEM_MC_ARG(uint ## a_SrcWidth ##_t, uSrc, 1); \
600 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
601 IEM_MC_PREPARE_AVX_USAGE(); \
602 IEM_MC_FETCH_XREG_U ## a_SrcWidth (uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0); \
603 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
604 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
605 iemAImpl_## a_Instr ## _u128_fallback), \
606 puDst, uSrc); \
607 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
608 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
609 IEM_MC_END(); \
610 } \
611 } \
612 else \
613 { \
614 /* \
615 * Register, memory. \
616 */ \
617 if (pVCpu->iem.s.uVexLength) \
618 { \
619 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
620 IEM_MC_LOCAL(RTUINT256U, uDst); \
621 IEM_MC_LOCAL(RTUINT128U, uSrc); \
622 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
623 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
624 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1); \
625 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
626 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2); \
627 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
628 IEM_MC_PREPARE_AVX_USAGE(); \
629 a_VexLengthMemFetch(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
630 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
631 iemAImpl_ ## a_Instr ## _u256_fallback), \
632 puDst, puSrc); \
633 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
634 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
635 IEM_MC_END(); \
636 } \
637 else \
638 { \
639 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
640 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
641 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
642 IEM_MC_ARG(uint ## a_SrcWidth ##_t, uSrc, 1); \
643 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
644 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx); \
645 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
646 IEM_MC_PREPARE_AVX_USAGE(); \
647 IEM_MC_FETCH_MEM_U ## a_SrcWidth (uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
648 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
649 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
650 iemAImpl_ ## a_Instr ## _u128_fallback), \
651 puDst, uSrc); \
652 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
653 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
654 IEM_MC_END(); \
655 } \
656 } \
657 (void)0
658
659/** Opcode VEX.66.0F38 0x20. */
660FNIEMOP_DEF(iemOp_vpmovsxbw_Vx_UxMq)
661{
662 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
663 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBW, vpmovsxbw, Vx, Wq, DISOPTYPE_HARMLESS, 0);
664 IEMOP_BODY_VPMOV_S_Z(vpmovsxbw, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
665}
666
667
668/** Opcode VEX.66.0F38 0x21. */
669FNIEMOP_DEF(iemOp_vpmovsxbd_Vx_UxMd)
670{
671 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
672 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBD, vpmovsxbd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
673 IEMOP_BODY_VPMOV_S_Z(vpmovsxbd, 32, IEM_MC_FETCH_MEM_U128);
674}
675
676
677/** Opcode VEX.66.0F38 0x22. */
678FNIEMOP_DEF(iemOp_vpmovsxbq_Vx_UxMw)
679{
680 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
681 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBQ, vpmovsxbq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
682 IEMOP_BODY_VPMOV_S_Z(vpmovsxbq, 16, IEM_MC_FETCH_MEM_U128);
683}
684
685
686/** Opcode VEX.66.0F38 0x23. */
687FNIEMOP_DEF(iemOp_vpmovsxwd_Vx_UxMq)
688{
689 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
690 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXWD, vpmovsxwd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
691 IEMOP_BODY_VPMOV_S_Z(vpmovsxwd, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
692}
693
694
695/** Opcode VEX.66.0F38 0x24. */
696FNIEMOP_DEF(iemOp_vpmovsxwq_Vx_UxMd)
697{
698 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
699 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXWQ, vpmovsxwq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
700 IEMOP_BODY_VPMOV_S_Z(vpmovsxwq, 32, IEM_MC_FETCH_MEM_U128);
701}
702
703
704/** Opcode VEX.66.0F38 0x25. */
705FNIEMOP_DEF(iemOp_vpmovsxdq_Vx_UxMq)
706{
707 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
708 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXDQ, vpmovsxdq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
709 IEMOP_BODY_VPMOV_S_Z(vpmovsxdq, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
710}
711
712
713/* Opcode VEX.66.0F38 0x26 - invalid */
714/* Opcode VEX.66.0F38 0x27 - invalid */
715
716
717/** Opcode VEX.66.0F38 0x28. */
718FNIEMOP_DEF(iemOp_vpmuldq_Vx_Hx_Wx)
719{
720 IEMOP_MNEMONIC3(VEX_RVM, VPMULDQ, vpmuldq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
721 IEMOPMEDIAOPTF3_INIT_VARS(vpmuldq);
722 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
723}
724
725
726/** Opcode VEX.66.0F38 0x29. */
727FNIEMOP_DEF(iemOp_vpcmpeqq_Vx_Hx_Wx)
728{
729 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQQ, vpcmpeqq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
730 IEMOPMEDIAOPTF3_INIT_VARS(vpcmpeqq);
731 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
732}
733
734
735FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
736{
737 Assert(pVCpu->iem.s.uVexLength <= 1);
738 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
739 if (IEM_IS_MODRM_MEM_MODE(bRm))
740 {
741 if (pVCpu->iem.s.uVexLength == 0)
742 {
743 /**
744 * @opcode 0x2a
745 * @opcodesub !11 mr/reg vex.l=0
746 * @oppfx 0x66
747 * @opcpuid avx
748 * @opgroup og_avx_cachect
749 * @opxcpttype 1
750 * @optest op1=-1 op2=2 -> op1=2
751 * @optest op1=0 op2=-42 -> op1=-42
752 */
753 /* 128-bit: Memory, register. */
754 IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
755 DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
756 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
757 IEM_MC_LOCAL(RTUINT128U, uSrc);
758 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
759
760 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
761 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
762 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
763 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
764
765 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
766 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
767
768 IEM_MC_ADVANCE_RIP_AND_FINISH();
769 IEM_MC_END();
770 }
771 else
772 {
773 /**
774 * @opdone
775 * @opcode 0x2a
776 * @opcodesub !11 mr/reg vex.l=1
777 * @oppfx 0x66
778 * @opcpuid avx2
779 * @opgroup og_avx2_cachect
780 * @opxcpttype 1
781 * @optest op1=-1 op2=2 -> op1=2
782 * @optest op1=0 op2=-42 -> op1=-42
783 */
784 /* 256-bit: Memory, register. */
785 IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
786 DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
787 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
788 IEM_MC_LOCAL(RTUINT256U, uSrc);
789 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
790
791 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
792 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
793 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
794 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
795
796 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
797 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
798
799 IEM_MC_ADVANCE_RIP_AND_FINISH();
800 IEM_MC_END();
801 }
802 }
803
804 /**
805 * @opdone
806 * @opmnemonic udvex660f382arg
807 * @opcode 0x2a
808 * @opcodesub 11 mr/reg
809 * @oppfx 0x66
810 * @opunused immediate
811 * @opcpuid avx
812 * @optest ->
813 */
814 else
815 IEMOP_RAISE_INVALID_OPCODE_RET();
816}
817
818
819/** Opcode VEX.66.0F38 0x2b. */
820FNIEMOP_DEF(iemOp_vpackusdw_Vx_Hx_Wx)
821{
822 IEMOP_MNEMONIC3(VEX_RVM, VPACKUSDW, vpackusdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
823 IEMOPMEDIAOPTF3_INIT_VARS( vpackusdw);
824 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
825}
826
827
828/** Opcode VEX.66.0F38 0x2c. */
829FNIEMOP_STUB(iemOp_vmaskmovps_Vx_Hx_Mx);
830/** Opcode VEX.66.0F38 0x2d. */
831FNIEMOP_STUB(iemOp_vmaskmovpd_Vx_Hx_Mx);
832/** Opcode VEX.66.0F38 0x2e. */
833FNIEMOP_STUB(iemOp_vmaskmovps_Mx_Hx_Vx);
834/** Opcode VEX.66.0F38 0x2f. */
835FNIEMOP_STUB(iemOp_vmaskmovpd_Mx_Hx_Vx);
836
837
838/** Opcode VEX.66.0F38 0x30. */
839FNIEMOP_DEF(iemOp_vpmovzxbw_Vx_UxMq)
840{
841 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
842 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBW, vpmovzxbw, Vx, Wq, DISOPTYPE_HARMLESS, 0);
843 IEMOP_BODY_VPMOV_S_Z(vpmovzxbw, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
844}
845
846
847/** Opcode VEX.66.0F38 0x31. */
848FNIEMOP_DEF(iemOp_vpmovzxbd_Vx_UxMd)
849{
850 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
851 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBD, vpmovzxbd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
852 IEMOP_BODY_VPMOV_S_Z(vpmovzxbd, 32, IEM_MC_FETCH_MEM_U128);
853}
854
855
856/** Opcode VEX.66.0F38 0x32. */
857FNIEMOP_DEF(iemOp_vpmovzxbq_Vx_UxMw)
858{
859 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
860 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBQ, vpmovzxbq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
861 IEMOP_BODY_VPMOV_S_Z(vpmovzxbq, 16, IEM_MC_FETCH_MEM_U128);
862}
863
864
865/** Opcode VEX.66.0F38 0x33. */
866FNIEMOP_DEF(iemOp_vpmovzxwd_Vx_UxMq)
867{
868 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
869 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXWD, vpmovzxwd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
870 IEMOP_BODY_VPMOV_S_Z(vpmovzxwd, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
871}
872
873
874/** Opcode VEX.66.0F38 0x34. */
875FNIEMOP_DEF(iemOp_vpmovzxwq_Vx_UxMd)
876{
877 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
878 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXWQ, vpmovzxwq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
879 IEMOP_BODY_VPMOV_S_Z(vpmovzxwq, 32, IEM_MC_FETCH_MEM_U128);
880}
881
882
883/** Opcode VEX.66.0F38 0x35. */
884FNIEMOP_DEF(iemOp_vpmovzxdq_Vx_UxMq)
885{
886 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
887 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXDQ, vpmovzxdq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
888 IEMOP_BODY_VPMOV_S_Z(vpmovzxdq, 64, IEM_MC_FETCH_MEM_U128_NO_AC);
889}
890
891
892/* Opcode VEX.66.0F38 0x36. */
893FNIEMOP_STUB(iemOp_vpermd_Vqq_Hqq_Wqq);
894
895
896/** Opcode VEX.66.0F38 0x37. */
897FNIEMOP_DEF(iemOp_vpcmpgtq_Vx_Hx_Wx)
898{
899 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTQ, vpcmpgtq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
900 IEMOPMEDIAOPTF3_INIT_VARS( vpcmpgtq);
901 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
902}
903
904
905/** Opcode VEX.66.0F38 0x38. */
906FNIEMOP_DEF(iemOp_vpminsb_Vx_Hx_Wx)
907{
908 IEMOP_MNEMONIC3(VEX_RVM, VPMINSB, vpminsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
909 IEMOPMEDIAOPTF3_INIT_VARS( vpminsb);
910 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
911}
912
913
914/** Opcode VEX.66.0F38 0x39. */
915FNIEMOP_DEF(iemOp_vpminsd_Vx_Hx_Wx)
916{
917 IEMOP_MNEMONIC3(VEX_RVM, VPMINSD, vpminsd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
918 IEMOPMEDIAOPTF3_INIT_VARS( vpminsd);
919 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
920}
921
922
923/** Opcode VEX.66.0F38 0x3a. */
924FNIEMOP_DEF(iemOp_vpminuw_Vx_Hx_Wx)
925{
926 IEMOP_MNEMONIC3(VEX_RVM, VPMINUW, vpminuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
927 IEMOPMEDIAOPTF3_INIT_VARS( vpminuw);
928 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
929}
930
931
932/** Opcode VEX.66.0F38 0x3b. */
933FNIEMOP_DEF(iemOp_vpminud_Vx_Hx_Wx)
934{
935 IEMOP_MNEMONIC3(VEX_RVM, VPMINUD, vpminud, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
936 IEMOPMEDIAOPTF3_INIT_VARS( vpminud);
937 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
938}
939
940
941/** Opcode VEX.66.0F38 0x3c. */
942FNIEMOP_DEF(iemOp_vpmaxsb_Vx_Hx_Wx)
943{
944 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSB, vpmaxsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
945 IEMOPMEDIAOPTF3_INIT_VARS( vpmaxsb);
946 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
947}
948
949
950/** Opcode VEX.66.0F38 0x3d. */
951FNIEMOP_DEF(iemOp_vpmaxsd_Vx_Hx_Wx)
952{
953 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSD, vpmaxsd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
954 IEMOPMEDIAOPTF3_INIT_VARS( vpmaxsd);
955 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
956}
957
958
959/** Opcode VEX.66.0F38 0x3e. */
960FNIEMOP_DEF(iemOp_vpmaxuw_Vx_Hx_Wx)
961{
962 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUW, vpmaxuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
963 IEMOPMEDIAOPTF3_INIT_VARS( vpmaxuw);
964 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
965}
966
967
968/** Opcode VEX.66.0F38 0x3f. */
969FNIEMOP_DEF(iemOp_vpmaxud_Vx_Hx_Wx)
970{
971 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUD, vpmaxud, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
972 IEMOPMEDIAOPTF3_INIT_VARS( vpmaxud);
973 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
974}
975
976
977/** Opcode VEX.66.0F38 0x40. */
978FNIEMOP_DEF(iemOp_vpmulld_Vx_Hx_Wx)
979{
980 IEMOP_MNEMONIC3(VEX_RVM, VPMULLD, vpmulld, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
981 IEMOPMEDIAOPTF3_INIT_VARS(vpmulld);
982 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
983}
984
985
986/** Opcode VEX.66.0F38 0x41. */
987FNIEMOP_DEF(iemOp_vphminposuw_Vdq_Wdq)
988{
989 IEMOP_MNEMONIC2(VEX_RM, VPHMINPOSUW, vphminposuw, Vdq, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
990 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
991 if (IEM_IS_MODRM_REG_MODE(bRm))
992 {
993 /*
994 * Register, register.
995 */
996 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
997 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
998 IEM_MC_ARG(PRTUINT128U, puDst, 0);
999 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1000 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1001 IEM_MC_PREPARE_AVX_USAGE();
1002 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1003 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1004 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback),
1005 puDst, puSrc);
1006 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1007 IEM_MC_ADVANCE_RIP_AND_FINISH();
1008 IEM_MC_END();
1009 }
1010 else
1011 {
1012 /*
1013 * Register, memory.
1014 */
1015 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1016 IEM_MC_LOCAL(RTUINT128U, uSrc);
1017 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1018 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1019 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1020
1021 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1022 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1023 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1024 IEM_MC_PREPARE_AVX_USAGE();
1025
1026 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1027 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1028 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback),
1029 puDst, puSrc);
1030 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1031
1032 IEM_MC_ADVANCE_RIP_AND_FINISH();
1033 IEM_MC_END();
1034 }
1035}
1036
1037
1038/* Opcode VEX.66.0F38 0x42 - invalid. */
1039/* Opcode VEX.66.0F38 0x43 - invalid. */
1040/* Opcode VEX.66.0F38 0x44 - invalid. */
1041
1042
1043/** Opcode VEX.66.0F38 0x45. */
1044FNIEMOP_DEF(iemOp_vpsrlvd_q_Vx_Hx_Wx)
1045{
1046 IEMOP_MNEMONIC3(VEX_RVM, VPSRLVD, vpsrlvd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1047
1048 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1049 {
1050 IEMOPMEDIAOPTF3_INIT_VARS(vpsrlvq);
1051 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1052 }
1053 else
1054 {
1055 IEMOPMEDIAOPTF3_INIT_VARS(vpsrlvd);
1056 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1057 }
1058}
1059
1060
1061/** Opcode VEX.66.0F38 0x46. */
1062FNIEMOP_DEF(iemOp_vpsravd_Vx_Hx_Wx)
1063{
1064 IEMOP_MNEMONIC3(VEX_RVM, VPSRAVD, vpsravd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1065 IEMOPMEDIAOPTF3_INIT_VARS(vpsravd);
1066 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1067}
1068
1069
1070/** Opcode VEX.66.0F38 0x47. */
1071FNIEMOP_DEF(iemOp_vpsllvd_q_Vx_Hx_Wx)
1072{
1073 IEMOP_MNEMONIC3(VEX_RVM, VPSLLVD, vpsllvd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
1074
1075 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1076 {
1077 IEMOPMEDIAOPTF3_INIT_VARS(vpsllvq);
1078 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1079 }
1080 else
1081 {
1082 IEMOPMEDIAOPTF3_INIT_VARS(vpsllvd);
1083 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1084 }
1085}
1086
1087
1088/* Opcode VEX.66.0F38 0x48 - invalid. */
1089/* Opcode VEX.66.0F38 0x49 - invalid. */
1090/* Opcode VEX.66.0F38 0x4a - invalid. */
1091/* Opcode VEX.66.0F38 0x4b - invalid. */
1092/* Opcode VEX.66.0F38 0x4c - invalid. */
1093/* Opcode VEX.66.0F38 0x4d - invalid. */
1094/* Opcode VEX.66.0F38 0x4e - invalid. */
1095/* Opcode VEX.66.0F38 0x4f - invalid. */
1096
1097/* Opcode VEX.66.0F38 0x50 - invalid. */
1098/* Opcode VEX.66.0F38 0x51 - invalid. */
1099/* Opcode VEX.66.0F38 0x52 - invalid. */
1100/* Opcode VEX.66.0F38 0x53 - invalid. */
1101/* Opcode VEX.66.0F38 0x54 - invalid. */
1102/* Opcode VEX.66.0F38 0x55 - invalid. */
1103/* Opcode VEX.66.0F38 0x56 - invalid. */
1104/* Opcode VEX.66.0F38 0x57 - invalid. */
1105
1106
1107/** Opcode VEX.66.0F38 0x58. */
1108FNIEMOP_DEF(iemOp_vpbroadcastd_Vx_Wx)
1109{
1110 IEMOP_MNEMONIC2(VEX_RM, VPBROADCASTD, vpbroadcastd, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1111 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1112 if (IEM_IS_MODRM_REG_MODE(bRm))
1113 {
1114 /*
1115 * Register, register.
1116 */
1117 if (pVCpu->iem.s.uVexLength)
1118 {
1119 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1120 IEM_MC_LOCAL(uint32_t, uSrc);
1121
1122 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1123 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1124 IEM_MC_PREPARE_AVX_USAGE();
1125
1126 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1127 IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1128
1129 IEM_MC_ADVANCE_RIP_AND_FINISH();
1130 IEM_MC_END();
1131 }
1132 else
1133 {
1134 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1135 IEM_MC_LOCAL(uint32_t, uSrc);
1136
1137 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1138 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1139 IEM_MC_PREPARE_AVX_USAGE();
1140 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1141 IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1142
1143 IEM_MC_ADVANCE_RIP_AND_FINISH();
1144 IEM_MC_END();
1145 }
1146 }
1147 else
1148 {
1149 /*
1150 * Register, memory.
1151 */
1152 if (pVCpu->iem.s.uVexLength)
1153 {
1154 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1155 IEM_MC_LOCAL(uint32_t, uSrc);
1156 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1157
1158 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1159 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1160 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1161 IEM_MC_PREPARE_AVX_USAGE();
1162
1163 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1164 IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1165
1166 IEM_MC_ADVANCE_RIP_AND_FINISH();
1167 IEM_MC_END();
1168 }
1169 else
1170 {
1171 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1172 IEM_MC_LOCAL(uint32_t, uSrc);
1173 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1174
1175 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1176 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1177 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1178 IEM_MC_PREPARE_AVX_USAGE();
1179
1180 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1181 IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1182
1183 IEM_MC_ADVANCE_RIP_AND_FINISH();
1184 IEM_MC_END();
1185 }
1186 }
1187}
1188
1189
1190/** Opcode VEX.66.0F38 0x59. */
1191FNIEMOP_DEF(iemOp_vpbroadcastq_Vx_Wx)
1192{
1193 IEMOP_MNEMONIC2(VEX_RM, VPBROADCASTQ, vpbroadcastq, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1194 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1195 if (IEM_IS_MODRM_REG_MODE(bRm))
1196 {
1197 /*
1198 * Register, register.
1199 */
1200 if (pVCpu->iem.s.uVexLength)
1201 {
1202 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1203 IEM_MC_LOCAL(uint64_t, uSrc);
1204
1205 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1206 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1207 IEM_MC_PREPARE_AVX_USAGE();
1208
1209 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1210 IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1211
1212 IEM_MC_ADVANCE_RIP_AND_FINISH();
1213 IEM_MC_END();
1214 }
1215 else
1216 {
1217 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1218 IEM_MC_LOCAL(uint64_t, uSrc);
1219
1220 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1221 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1222 IEM_MC_PREPARE_AVX_USAGE();
1223 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1224 IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1225
1226 IEM_MC_ADVANCE_RIP_AND_FINISH();
1227 IEM_MC_END();
1228 }
1229 }
1230 else
1231 {
1232 /*
1233 * Register, memory.
1234 */
1235 if (pVCpu->iem.s.uVexLength)
1236 {
1237 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1238 IEM_MC_LOCAL(uint64_t, uSrc);
1239 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1240
1241 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1242 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1243 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1244 IEM_MC_PREPARE_AVX_USAGE();
1245
1246 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1247 IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1248
1249 IEM_MC_ADVANCE_RIP_AND_FINISH();
1250 IEM_MC_END();
1251 }
1252 else
1253 {
1254 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1255 IEM_MC_LOCAL(uint64_t, uSrc);
1256 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1257
1258 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1259 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1260 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1261 IEM_MC_PREPARE_AVX_USAGE();
1262
1263 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1264 IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1265
1266 IEM_MC_ADVANCE_RIP_AND_FINISH();
1267 IEM_MC_END();
1268 }
1269 }
1270}
1271
1272
1273/** Opcode VEX.66.0F38 0x5a. */
1274FNIEMOP_DEF(iemOp_vbroadcasti128_Vqq_Mdq)
1275{
1276 IEMOP_MNEMONIC2(VEX_RM, VBROADCASTI128, vbroadcasti128, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1277 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1278 if (IEM_IS_MODRM_REG_MODE(bRm))
1279 {
1280 /*
1281 * No register, register.
1282 */
1283 IEMOP_RAISE_INVALID_OPCODE_RET();
1284 }
1285 else
1286 {
1287 /*
1288 * Register, memory.
1289 */
1290 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1291 IEM_MC_LOCAL(RTUINT128U, uSrc);
1292 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1293
1294 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1295 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx);
1296 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1297 IEM_MC_PREPARE_AVX_USAGE();
1298
1299 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1300 IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1301
1302 IEM_MC_ADVANCE_RIP_AND_FINISH();
1303 IEM_MC_END();
1304 }
1305}
1306
1307
1308/* Opcode VEX.66.0F38 0x5b - invalid. */
1309/* Opcode VEX.66.0F38 0x5c - invalid. */
1310/* Opcode VEX.66.0F38 0x5d - invalid. */
1311/* Opcode VEX.66.0F38 0x5e - invalid. */
1312/* Opcode VEX.66.0F38 0x5f - invalid. */
1313
1314/* Opcode VEX.66.0F38 0x60 - invalid. */
1315/* Opcode VEX.66.0F38 0x61 - invalid. */
1316/* Opcode VEX.66.0F38 0x62 - invalid. */
1317/* Opcode VEX.66.0F38 0x63 - invalid. */
1318/* Opcode VEX.66.0F38 0x64 - invalid. */
1319/* Opcode VEX.66.0F38 0x65 - invalid. */
1320/* Opcode VEX.66.0F38 0x66 - invalid. */
1321/* Opcode VEX.66.0F38 0x67 - invalid. */
1322/* Opcode VEX.66.0F38 0x68 - invalid. */
1323/* Opcode VEX.66.0F38 0x69 - invalid. */
1324/* Opcode VEX.66.0F38 0x6a - invalid. */
1325/* Opcode VEX.66.0F38 0x6b - invalid. */
1326/* Opcode VEX.66.0F38 0x6c - invalid. */
1327/* Opcode VEX.66.0F38 0x6d - invalid. */
1328/* Opcode VEX.66.0F38 0x6e - invalid. */
1329/* Opcode VEX.66.0F38 0x6f - invalid. */
1330
1331/* Opcode VEX.66.0F38 0x70 - invalid. */
1332/* Opcode VEX.66.0F38 0x71 - invalid. */
1333/* Opcode VEX.66.0F38 0x72 - invalid. */
1334/* Opcode VEX.66.0F38 0x73 - invalid. */
1335/* Opcode VEX.66.0F38 0x74 - invalid. */
1336/* Opcode VEX.66.0F38 0x75 - invalid. */
1337/* Opcode VEX.66.0F38 0x76 - invalid. */
1338/* Opcode VEX.66.0F38 0x77 - invalid. */
1339
1340
1341/** Opcode VEX.66.0F38 0x78. */
1342FNIEMOP_DEF(iemOp_vpbroadcastb_Vx_Wx)
1343{
1344 IEMOP_MNEMONIC2(VEX_RM, VPBROADCASTB, vpbroadcastb, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1345 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1346 if (IEM_IS_MODRM_REG_MODE(bRm))
1347 {
1348 /*
1349 * Register, register.
1350 */
1351 if (pVCpu->iem.s.uVexLength)
1352 {
1353 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1354 IEM_MC_LOCAL(uint8_t, uSrc);
1355
1356 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1357 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1358 IEM_MC_PREPARE_AVX_USAGE();
1359
1360 IEM_MC_FETCH_XREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1361 IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1362
1363 IEM_MC_ADVANCE_RIP_AND_FINISH();
1364 IEM_MC_END();
1365 }
1366 else
1367 {
1368 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1369 IEM_MC_LOCAL(uint8_t, uSrc);
1370
1371 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1372 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1373 IEM_MC_PREPARE_AVX_USAGE();
1374 IEM_MC_FETCH_XREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1375 IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1376
1377 IEM_MC_ADVANCE_RIP_AND_FINISH();
1378 IEM_MC_END();
1379 }
1380 }
1381 else
1382 {
1383 /*
1384 * Register, memory.
1385 */
1386 if (pVCpu->iem.s.uVexLength)
1387 {
1388 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1389 IEM_MC_LOCAL(uint8_t, uSrc);
1390 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1391
1392 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1393 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1394 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1395 IEM_MC_PREPARE_AVX_USAGE();
1396
1397 IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1398 IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1399
1400 IEM_MC_ADVANCE_RIP_AND_FINISH();
1401 IEM_MC_END();
1402 }
1403 else
1404 {
1405 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1406 IEM_MC_LOCAL(uint8_t, uSrc);
1407 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1408
1409 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1410 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1411 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1412 IEM_MC_PREPARE_AVX_USAGE();
1413
1414 IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1415 IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1416
1417 IEM_MC_ADVANCE_RIP_AND_FINISH();
1418 IEM_MC_END();
1419 }
1420 }
1421}
1422
1423
1424/** Opcode VEX.66.0F38 0x79. */
1425FNIEMOP_DEF(iemOp_vpbroadcastw_Vx_Wx)
1426{
1427 IEMOP_MNEMONIC2(VEX_RM, VPBROADCASTW, vpbroadcastw, Vx, Wx, DISOPTYPE_HARMLESS, 0);
1428 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1429 if (IEM_IS_MODRM_REG_MODE(bRm))
1430 {
1431 /*
1432 * Register, register.
1433 */
1434 if (pVCpu->iem.s.uVexLength)
1435 {
1436 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1437 IEM_MC_LOCAL(uint16_t, uSrc);
1438
1439 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1440 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1441 IEM_MC_PREPARE_AVX_USAGE();
1442
1443 IEM_MC_FETCH_XREG_U16(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1444 IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1445
1446 IEM_MC_ADVANCE_RIP_AND_FINISH();
1447 IEM_MC_END();
1448 }
1449 else
1450 {
1451 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1452 IEM_MC_LOCAL(uint16_t, uSrc);
1453
1454 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1455 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1456 IEM_MC_PREPARE_AVX_USAGE();
1457 IEM_MC_FETCH_XREG_U16(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
1458 IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1459
1460 IEM_MC_ADVANCE_RIP_AND_FINISH();
1461 IEM_MC_END();
1462 }
1463 }
1464 else
1465 {
1466 /*
1467 * Register, memory.
1468 */
1469 if (pVCpu->iem.s.uVexLength)
1470 {
1471 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1472 IEM_MC_LOCAL(uint16_t, uSrc);
1473 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1474
1475 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1476 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1477 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1478 IEM_MC_PREPARE_AVX_USAGE();
1479
1480 IEM_MC_FETCH_MEM_U16(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1481 IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1482
1483 IEM_MC_ADVANCE_RIP_AND_FINISH();
1484 IEM_MC_END();
1485 }
1486 else
1487 {
1488 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1489 IEM_MC_LOCAL(uint16_t, uSrc);
1490 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1491
1492 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1493 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
1494 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1495 IEM_MC_PREPARE_AVX_USAGE();
1496
1497 IEM_MC_FETCH_MEM_U16(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1498 IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1499
1500 IEM_MC_ADVANCE_RIP_AND_FINISH();
1501 IEM_MC_END();
1502 }
1503 }
1504}
1505
1506
1507/* Opcode VEX.66.0F38 0x7a - invalid. */
1508/* Opcode VEX.66.0F38 0x7b - invalid. */
1509/* Opcode VEX.66.0F38 0x7c - invalid. */
1510/* Opcode VEX.66.0F38 0x7d - invalid. */
1511/* Opcode VEX.66.0F38 0x7e - invalid. */
1512/* Opcode VEX.66.0F38 0x7f - invalid. */
1513
1514/* Opcode VEX.66.0F38 0x80 - invalid (legacy only). */
1515/* Opcode VEX.66.0F38 0x81 - invalid (legacy only). */
1516/* Opcode VEX.66.0F38 0x82 - invalid (legacy only). */
1517/* Opcode VEX.66.0F38 0x83 - invalid. */
1518/* Opcode VEX.66.0F38 0x84 - invalid. */
1519/* Opcode VEX.66.0F38 0x85 - invalid. */
1520/* Opcode VEX.66.0F38 0x86 - invalid. */
1521/* Opcode VEX.66.0F38 0x87 - invalid. */
1522/* Opcode VEX.66.0F38 0x88 - invalid. */
1523/* Opcode VEX.66.0F38 0x89 - invalid. */
1524/* Opcode VEX.66.0F38 0x8a - invalid. */
1525/* Opcode VEX.66.0F38 0x8b - invalid. */
1526/** Opcode VEX.66.0F38 0x8c. */
1527FNIEMOP_STUB(iemOp_vpmaskmovd_q_Vx_Hx_Mx);
1528/* Opcode VEX.66.0F38 0x8d - invalid. */
1529/** Opcode VEX.66.0F38 0x8e. */
1530FNIEMOP_STUB(iemOp_vpmaskmovd_q_Mx_Vx_Hx);
1531/* Opcode VEX.66.0F38 0x8f - invalid. */
1532
1533/** Opcode VEX.66.0F38 0x90 (vex only). */
1534FNIEMOP_STUB(iemOp_vpgatherdd_q_Vx_Hx_Wx);
1535/** Opcode VEX.66.0F38 0x91 (vex only). */
1536FNIEMOP_STUB(iemOp_vpgatherqd_q_Vx_Hx_Wx);
1537/** Opcode VEX.66.0F38 0x92 (vex only). */
1538FNIEMOP_STUB(iemOp_vgatherdps_d_Vx_Hx_Wx);
1539/** Opcode VEX.66.0F38 0x93 (vex only). */
1540FNIEMOP_STUB(iemOp_vgatherqps_d_Vx_Hx_Wx);
1541/* Opcode VEX.66.0F38 0x94 - invalid. */
1542/* Opcode VEX.66.0F38 0x95 - invalid. */
1543/** Opcode VEX.66.0F38 0x96 (vex only). */
1544FNIEMOP_STUB(iemOp_vfmaddsub132ps_d_Vx_Hx_Wx);
1545/** Opcode VEX.66.0F38 0x97 (vex only). */
1546FNIEMOP_STUB(iemOp_vfmsubadd132ps_d_Vx_Hx_Wx);
1547/** Opcode VEX.66.0F38 0x98 (vex only). */
1548FNIEMOP_STUB(iemOp_vfmadd132ps_d_Vx_Hx_Wx);
1549/** Opcode VEX.66.0F38 0x99 (vex only). */
1550FNIEMOP_STUB(iemOp_vfmadd132ss_d_Vx_Hx_Wx);
1551/** Opcode VEX.66.0F38 0x9a (vex only). */
1552FNIEMOP_STUB(iemOp_vfmsub132ps_d_Vx_Hx_Wx);
1553/** Opcode VEX.66.0F38 0x9b (vex only). */
1554FNIEMOP_STUB(iemOp_vfmsub132ss_d_Vx_Hx_Wx);
1555/** Opcode VEX.66.0F38 0x9c (vex only). */
1556FNIEMOP_STUB(iemOp_vfnmadd132ps_d_Vx_Hx_Wx);
1557/** Opcode VEX.66.0F38 0x9d (vex only). */
1558FNIEMOP_STUB(iemOp_vfnmadd132ss_d_Vx_Hx_Wx);
1559/** Opcode VEX.66.0F38 0x9e (vex only). */
1560FNIEMOP_STUB(iemOp_vfnmsub132ps_d_Vx_Hx_Wx);
1561/** Opcode VEX.66.0F38 0x9f (vex only). */
1562FNIEMOP_STUB(iemOp_vfnmsub132ss_d_Vx_Hx_Wx);
1563
1564/* Opcode VEX.66.0F38 0xa0 - invalid. */
1565/* Opcode VEX.66.0F38 0xa1 - invalid. */
1566/* Opcode VEX.66.0F38 0xa2 - invalid. */
1567/* Opcode VEX.66.0F38 0xa3 - invalid. */
1568/* Opcode VEX.66.0F38 0xa4 - invalid. */
1569/* Opcode VEX.66.0F38 0xa5 - invalid. */
1570/** Opcode VEX.66.0F38 0xa6 (vex only). */
1571FNIEMOP_STUB(iemOp_vfmaddsub213ps_d_Vx_Hx_Wx);
1572/** Opcode VEX.66.0F38 0xa7 (vex only). */
1573FNIEMOP_STUB(iemOp_vfmsubadd213ps_d_Vx_Hx_Wx);
1574/** Opcode VEX.66.0F38 0xa8 (vex only). */
1575FNIEMOP_STUB(iemOp_vfmadd213ps_d_Vx_Hx_Wx);
1576/** Opcode VEX.66.0F38 0xa9 (vex only). */
1577FNIEMOP_STUB(iemOp_vfmadd213ss_d_Vx_Hx_Wx);
1578/** Opcode VEX.66.0F38 0xaa (vex only). */
1579FNIEMOP_STUB(iemOp_vfmsub213ps_d_Vx_Hx_Wx);
1580/** Opcode VEX.66.0F38 0xab (vex only). */
1581FNIEMOP_STUB(iemOp_vfmsub213ss_d_Vx_Hx_Wx);
1582/** Opcode VEX.66.0F38 0xac (vex only). */
1583FNIEMOP_STUB(iemOp_vfnmadd213ps_d_Vx_Hx_Wx);
1584/** Opcode VEX.66.0F38 0xad (vex only). */
1585FNIEMOP_STUB(iemOp_vfnmadd213ss_d_Vx_Hx_Wx);
1586/** Opcode VEX.66.0F38 0xae (vex only). */
1587FNIEMOP_STUB(iemOp_vfnmsub213ps_d_Vx_Hx_Wx);
1588/** Opcode VEX.66.0F38 0xaf (vex only). */
1589FNIEMOP_STUB(iemOp_vfnmsub213ss_d_Vx_Hx_Wx);
1590
1591/* Opcode VEX.66.0F38 0xb0 - invalid. */
1592/* Opcode VEX.66.0F38 0xb1 - invalid. */
1593/* Opcode VEX.66.0F38 0xb2 - invalid. */
1594/* Opcode VEX.66.0F38 0xb3 - invalid. */
1595/* Opcode VEX.66.0F38 0xb4 - invalid. */
1596/* Opcode VEX.66.0F38 0xb5 - invalid. */
1597/** Opcode VEX.66.0F38 0xb6 (vex only). */
1598FNIEMOP_STUB(iemOp_vfmaddsub231ps_d_Vx_Hx_Wx);
1599/** Opcode VEX.66.0F38 0xb7 (vex only). */
1600FNIEMOP_STUB(iemOp_vfmsubadd231ps_d_Vx_Hx_Wx);
1601/** Opcode VEX.66.0F38 0xb8 (vex only). */
1602FNIEMOP_STUB(iemOp_vfmadd231ps_d_Vx_Hx_Wx);
1603/** Opcode VEX.66.0F38 0xb9 (vex only). */
1604FNIEMOP_STUB(iemOp_vfmadd231ss_d_Vx_Hx_Wx);
1605/** Opcode VEX.66.0F38 0xba (vex only). */
1606FNIEMOP_STUB(iemOp_vfmsub231ps_d_Vx_Hx_Wx);
1607/** Opcode VEX.66.0F38 0xbb (vex only). */
1608FNIEMOP_STUB(iemOp_vfmsub231ss_d_Vx_Hx_Wx);
1609/** Opcode VEX.66.0F38 0xbc (vex only). */
1610FNIEMOP_STUB(iemOp_vfnmadd231ps_d_Vx_Hx_Wx);
1611/** Opcode VEX.66.0F38 0xbd (vex only). */
1612FNIEMOP_STUB(iemOp_vfnmadd231ss_d_Vx_Hx_Wx);
1613/** Opcode VEX.66.0F38 0xbe (vex only). */
1614FNIEMOP_STUB(iemOp_vfnmsub231ps_d_Vx_Hx_Wx);
1615/** Opcode VEX.66.0F38 0xbf (vex only). */
1616FNIEMOP_STUB(iemOp_vfnmsub231ss_d_Vx_Hx_Wx);
1617
1618/* Opcode VEX.0F38 0xc0 - invalid. */
1619/* Opcode VEX.66.0F38 0xc0 - invalid. */
1620/* Opcode VEX.0F38 0xc1 - invalid. */
1621/* Opcode VEX.66.0F38 0xc1 - invalid. */
1622/* Opcode VEX.0F38 0xc2 - invalid. */
1623/* Opcode VEX.66.0F38 0xc2 - invalid. */
1624/* Opcode VEX.0F38 0xc3 - invalid. */
1625/* Opcode VEX.66.0F38 0xc3 - invalid. */
1626/* Opcode VEX.0F38 0xc4 - invalid. */
1627/* Opcode VEX.66.0F38 0xc4 - invalid. */
1628/* Opcode VEX.0F38 0xc5 - invalid. */
1629/* Opcode VEX.66.0F38 0xc5 - invalid. */
1630/* Opcode VEX.0F38 0xc6 - invalid. */
1631/* Opcode VEX.66.0F38 0xc6 - invalid. */
1632/* Opcode VEX.0F38 0xc7 - invalid. */
1633/* Opcode VEX.66.0F38 0xc7 - invalid. */
1634/* Opcode VEX.0F38 0xc8 - invalid. */
1635/* Opcode VEX.66.0F38 0xc8 - invalid. */
1636/* Opcode VEX.0F38 0xc9 - invalid. */
1637/* Opcode VEX.66.0F38 0xc9 - invalid. */
1638/* Opcode VEX.0F38 0xca. */
1639/* Opcode VEX.66.0F38 0xca - invalid. */
1640/* Opcode VEX.0F38 0xcb - invalid. */
1641/* Opcode VEX.66.0F38 0xcb - invalid. */
1642/* Opcode VEX.0F38 0xcc - invalid. */
1643/* Opcode VEX.66.0F38 0xcc - invalid. */
1644/* Opcode VEX.0F38 0xcd - invalid. */
1645/* Opcode VEX.66.0F38 0xcd - invalid. */
1646/* Opcode VEX.0F38 0xce - invalid. */
1647/* Opcode VEX.66.0F38 0xce - invalid. */
1648/* Opcode VEX.0F38 0xcf - invalid. */
1649/* Opcode VEX.66.0F38 0xcf - invalid. */
1650
1651/* Opcode VEX.66.0F38 0xd0 - invalid. */
1652/* Opcode VEX.66.0F38 0xd1 - invalid. */
1653/* Opcode VEX.66.0F38 0xd2 - invalid. */
1654/* Opcode VEX.66.0F38 0xd3 - invalid. */
1655/* Opcode VEX.66.0F38 0xd4 - invalid. */
1656/* Opcode VEX.66.0F38 0xd5 - invalid. */
1657/* Opcode VEX.66.0F38 0xd6 - invalid. */
1658/* Opcode VEX.66.0F38 0xd7 - invalid. */
1659/* Opcode VEX.66.0F38 0xd8 - invalid. */
1660/* Opcode VEX.66.0F38 0xd9 - invalid. */
1661/* Opcode VEX.66.0F38 0xda - invalid. */
1662/** Opcode VEX.66.0F38 0xdb. */
1663FNIEMOP_STUB(iemOp_vaesimc_Vdq_Wdq);
1664/** Opcode VEX.66.0F38 0xdc. */
1665FNIEMOP_STUB(iemOp_vaesenc_Vdq_Wdq);
1666/** Opcode VEX.66.0F38 0xdd. */
1667FNIEMOP_STUB(iemOp_vaesenclast_Vdq_Wdq);
1668/** Opcode VEX.66.0F38 0xde. */
1669FNIEMOP_STUB(iemOp_vaesdec_Vdq_Wdq);
1670/** Opcode VEX.66.0F38 0xdf. */
1671FNIEMOP_STUB(iemOp_vaesdeclast_Vdq_Wdq);
1672
1673/* Opcode VEX.66.0F38 0xe0 - invalid. */
1674/* Opcode VEX.66.0F38 0xe1 - invalid. */
1675/* Opcode VEX.66.0F38 0xe2 - invalid. */
1676/* Opcode VEX.66.0F38 0xe3 - invalid. */
1677/* Opcode VEX.66.0F38 0xe4 - invalid. */
1678/* Opcode VEX.66.0F38 0xe5 - invalid. */
1679/* Opcode VEX.66.0F38 0xe6 - invalid. */
1680/* Opcode VEX.66.0F38 0xe7 - invalid. */
1681/* Opcode VEX.66.0F38 0xe8 - invalid. */
1682/* Opcode VEX.66.0F38 0xe9 - invalid. */
1683/* Opcode VEX.66.0F38 0xea - invalid. */
1684/* Opcode VEX.66.0F38 0xeb - invalid. */
1685/* Opcode VEX.66.0F38 0xec - invalid. */
1686/* Opcode VEX.66.0F38 0xed - invalid. */
1687/* Opcode VEX.66.0F38 0xee - invalid. */
1688/* Opcode VEX.66.0F38 0xef - invalid. */
1689
1690
1691/* Opcode VEX.0F38 0xf0 - invalid (legacy only). */
1692/* Opcode VEX.66.0F38 0xf0 - invalid (legacy only). */
1693/* Opcode VEX.F3.0F38 0xf0 - invalid. */
1694/* Opcode VEX.F2.0F38 0xf0 - invalid (legacy only). */
1695
1696/* Opcode VEX.0F38 0xf1 - invalid (legacy only). */
1697/* Opcode VEX.66.0F38 0xf1 - invalid (legacy only). */
1698/* Opcode VEX.F3.0F38 0xf1 - invalid. */
1699/* Opcode VEX.F2.0F38 0xf1 - invalid (legacy only). */
1700
1701/**
1702 * @opcode 0xf2
1703 * @oppfx none
1704 * @opflmodify cf,pf,af,zf,sf,of
1705 * @opflclear cf,of
1706 * @opflundef pf,af
1707 * @note VEX only
1708 */
1709FNIEMOP_DEF(iemOp_andn_Gy_By_Ey)
1710{
1711 IEMOP_MNEMONIC3(VEX_RVM, ANDN, andn, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1712 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_PF);
1713 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1714 if (IEM_IS_MODRM_REG_MODE(bRm))
1715 {
1716 /*
1717 * Register, register.
1718 */
1719 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1720 {
1721 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1722 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
1723 IEM_MC_ARG(uint64_t *, pDst, 0);
1724 IEM_MC_ARG(uint64_t, uSrc1, 1);
1725 IEM_MC_ARG(uint64_t, uSrc2, 2);
1726 IEM_MC_ARG(uint32_t *, pEFlags, 3);
1727 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1728 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1729 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1730 IEM_MC_REF_EFLAGS(pEFlags);
1731 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
1732 pDst, uSrc1, uSrc2, pEFlags);
1733 IEM_MC_ADVANCE_RIP_AND_FINISH();
1734 IEM_MC_END();
1735 }
1736 else
1737 {
1738 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1739 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
1740 IEM_MC_ARG(uint32_t *, pDst, 0);
1741 IEM_MC_ARG(uint32_t, uSrc1, 1);
1742 IEM_MC_ARG(uint32_t, uSrc2, 2);
1743 IEM_MC_ARG(uint32_t *, pEFlags, 3);
1744 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1745 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1746 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1747 IEM_MC_REF_EFLAGS(pEFlags);
1748 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
1749 pDst, uSrc1, uSrc2, pEFlags);
1750 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1751 IEM_MC_ADVANCE_RIP_AND_FINISH();
1752 IEM_MC_END();
1753 }
1754 }
1755 else
1756 {
1757 /*
1758 * Register, memory.
1759 */
1760 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1761 {
1762 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1763 IEM_MC_ARG(uint64_t *, pDst, 0);
1764 IEM_MC_ARG(uint64_t, uSrc1, 1);
1765 IEM_MC_ARG(uint64_t, uSrc2, 2);
1766 IEM_MC_ARG(uint32_t *, pEFlags, 3);
1767 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1768 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1769 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
1770 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1771 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1772 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1773 IEM_MC_REF_EFLAGS(pEFlags);
1774 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
1775 pDst, uSrc1, uSrc2, pEFlags);
1776 IEM_MC_ADVANCE_RIP_AND_FINISH();
1777 IEM_MC_END();
1778 }
1779 else
1780 {
1781 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1782 IEM_MC_ARG(uint32_t *, pDst, 0);
1783 IEM_MC_ARG(uint32_t, uSrc1, 1);
1784 IEM_MC_ARG(uint32_t, uSrc2, 2);
1785 IEM_MC_ARG(uint32_t *, pEFlags, 3);
1786 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1787 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1788 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
1789 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1790 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1791 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1792 IEM_MC_REF_EFLAGS(pEFlags);
1793 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
1794 pDst, uSrc1, uSrc2, pEFlags);
1795 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1796 IEM_MC_ADVANCE_RIP_AND_FINISH();
1797 IEM_MC_END();
1798 }
1799 }
1800}
1801
1802/* Opcode VEX.66.0F38 0xf2 - invalid. */
1803/* Opcode VEX.F3.0F38 0xf2 - invalid. */
1804/* Opcode VEX.F2.0F38 0xf2 - invalid. */
1805
1806
1807/* Opcode VEX.0F38 0xf3 - invalid. */
1808/* Opcode VEX.66.0F38 0xf3 - invalid. */
1809
1810/* Opcode VEX.F3.0F38 0xf3 /0 - invalid. */
1811
1812/** Body for the vex group 17 instructions. */
1813#define IEMOP_BODY_By_Ey(a_Instr) \
1814 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_PF); \
1815 if (IEM_IS_MODRM_REG_MODE(bRm)) \
1816 { \
1817 /* \
1818 * Register, register. \
1819 */ \
1820 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1821 { \
1822 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
1823 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
1824 IEM_MC_ARG(uint64_t *, pDst, 0); \
1825 IEM_MC_ARG(uint64_t, uSrc, 1); \
1826 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1827 IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1828 IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1829 IEM_MC_REF_EFLAGS(pEFlags); \
1830 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
1831 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
1832 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1833 IEM_MC_END(); \
1834 } \
1835 else \
1836 { \
1837 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
1838 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
1839 IEM_MC_ARG(uint32_t *, pDst, 0); \
1840 IEM_MC_ARG(uint32_t, uSrc, 1); \
1841 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1842 IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1843 IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1844 IEM_MC_REF_EFLAGS(pEFlags); \
1845 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
1846 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
1847 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1848 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1849 IEM_MC_END(); \
1850 } \
1851 } \
1852 else \
1853 { \
1854 /* \
1855 * Register, memory. \
1856 */ \
1857 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1858 { \
1859 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
1860 IEM_MC_ARG(uint64_t *, pDst, 0); \
1861 IEM_MC_ARG(uint64_t, uSrc, 1); \
1862 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1863 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1864 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1865 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
1866 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1867 IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1868 IEM_MC_REF_EFLAGS(pEFlags); \
1869 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
1870 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
1871 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1872 IEM_MC_END(); \
1873 } \
1874 else \
1875 { \
1876 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
1877 IEM_MC_ARG(uint32_t *, pDst, 0); \
1878 IEM_MC_ARG(uint32_t, uSrc, 1); \
1879 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1880 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1881 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1882 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
1883 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1884 IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1885 IEM_MC_REF_EFLAGS(pEFlags); \
1886 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
1887 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
1888 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1889 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1890 IEM_MC_END(); \
1891 } \
1892 } \
1893 (void)0
1894
1895
1896/**
1897 * @opmaps vexgrp17
1898 * @opcode /1
1899 * @opflmodify cf,pf,af,zf,sf,of
1900 * @opflclear of
1901 * @opflundef pf,af
1902 */
1903FNIEMOP_DEF_1(iemOp_VGrp17_blsr_By_Ey, uint8_t, bRm)
1904{
1905 IEMOP_MNEMONIC2(VEX_VM, BLSR, blsr, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1906 IEMOP_BODY_By_Ey(blsr);
1907}
1908
1909
1910/**
1911 * @opmaps vexgrp17
1912 * @opcode /2
1913 * @opflmodify cf,pf,af,zf,sf,of
1914 * @opflclear zf,of
1915 * @opflundef pf,af
1916 */
1917FNIEMOP_DEF_1(iemOp_VGrp17_blsmsk_By_Ey, uint8_t, bRm)
1918{
1919 IEMOP_MNEMONIC2(VEX_VM, BLSMSK, blsmsk, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1920 IEMOP_BODY_By_Ey(blsmsk);
1921}
1922
1923
1924/**
1925 * @opmaps vexgrp17
1926 * @opcode /3
1927 * @opflmodify cf,pf,af,zf,sf,of
1928 * @opflclear of
1929 * @opflundef pf,af
1930 */
1931FNIEMOP_DEF_1(iemOp_VGrp17_blsi_By_Ey, uint8_t, bRm)
1932{
1933 IEMOP_MNEMONIC2(VEX_VM, BLSI, blsi, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1934 IEMOP_BODY_By_Ey(blsi);
1935}
1936
1937
1938/* Opcode VEX.F3.0F38 0xf3 /4 - invalid. */
1939/* Opcode VEX.F3.0F38 0xf3 /5 - invalid. */
1940/* Opcode VEX.F3.0F38 0xf3 /6 - invalid. */
1941/* Opcode VEX.F3.0F38 0xf3 /7 - invalid. */
1942
1943/**
1944 * Group 17 jump table for the VEX.F3 variant.
1945 */
1946IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =
1947{
1948 /* /0 */ iemOp_InvalidWithRM,
1949 /* /1 */ iemOp_VGrp17_blsr_By_Ey,
1950 /* /2 */ iemOp_VGrp17_blsmsk_By_Ey,
1951 /* /3 */ iemOp_VGrp17_blsi_By_Ey,
1952 /* /4 */ iemOp_InvalidWithRM,
1953 /* /5 */ iemOp_InvalidWithRM,
1954 /* /6 */ iemOp_InvalidWithRM,
1955 /* /7 */ iemOp_InvalidWithRM
1956};
1957AssertCompile(RT_ELEMENTS(g_apfnVexGroup17_f3) == 8);
1958
1959/** Opcode VEX.F3.0F38 0xf3 - invalid (vex only - group 17). */
1960FNIEMOP_DEF(iemOp_VGrp17_f3)
1961{
1962 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1963 return FNIEMOP_CALL_1(g_apfnVexGroup17_f3[IEM_GET_MODRM_REG_8(bRm)], bRm);
1964}
1965
1966/* Opcode VEX.F2.0F38 0xf3 - invalid (vex only - group 17). */
1967
1968
1969/* Opcode VEX.0F38 0xf4 - invalid. */
1970/* Opcode VEX.66.0F38 0xf4 - invalid. */
1971/* Opcode VEX.F3.0F38 0xf4 - invalid. */
1972/* Opcode VEX.F2.0F38 0xf4 - invalid. */
1973
1974/** Body for BZHI, BEXTR, ++; assumes VEX.L must be 0. */
1975#define IEMOP_BODY_Gy_Ey_By(a_Instr, a_fFeatureMember, a_fUndefFlags) \
1976 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
1977 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1978 if (IEM_IS_MODRM_REG_MODE(bRm)) \
1979 { \
1980 /* \
1981 * Register, register. \
1982 */ \
1983 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1984 { \
1985 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
1986 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
1987 IEM_MC_ARG(uint64_t *, pDst, 0); \
1988 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1989 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1990 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1991 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1992 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1993 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1994 IEM_MC_REF_EFLAGS(pEFlags); \
1995 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1996 iemAImpl_ ## a_Instr ## _u64_fallback), \
1997 pDst, uSrc1, uSrc2, pEFlags); \
1998 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1999 IEM_MC_END(); \
2000 } \
2001 else \
2002 { \
2003 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
2004 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2005 IEM_MC_ARG(uint32_t *, pDst, 0); \
2006 IEM_MC_ARG(uint32_t, uSrc1, 1); \
2007 IEM_MC_ARG(uint32_t, uSrc2, 2); \
2008 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
2009 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2010 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2011 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2012 IEM_MC_REF_EFLAGS(pEFlags); \
2013 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
2014 iemAImpl_ ## a_Instr ## _u32_fallback), \
2015 pDst, uSrc1, uSrc2, pEFlags); \
2016 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2017 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2018 IEM_MC_END(); \
2019 } \
2020 } \
2021 else \
2022 { \
2023 /* \
2024 * Register, memory. \
2025 */ \
2026 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2027 { \
2028 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
2029 IEM_MC_ARG(uint64_t *, pDst, 0); \
2030 IEM_MC_ARG(uint64_t, uSrc1, 1); \
2031 IEM_MC_ARG(uint64_t, uSrc2, 2); \
2032 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
2033 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2034 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2035 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2036 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2037 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2038 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2039 IEM_MC_REF_EFLAGS(pEFlags); \
2040 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
2041 iemAImpl_ ## a_Instr ## _u64_fallback), \
2042 pDst, uSrc1, uSrc2, pEFlags); \
2043 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2044 IEM_MC_END(); \
2045 } \
2046 else \
2047 { \
2048 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
2049 IEM_MC_ARG(uint32_t *, pDst, 0); \
2050 IEM_MC_ARG(uint32_t, uSrc1, 1); \
2051 IEM_MC_ARG(uint32_t, uSrc2, 2); \
2052 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
2053 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2054 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2055 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2056 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2057 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2058 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2059 IEM_MC_REF_EFLAGS(pEFlags); \
2060 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
2061 iemAImpl_ ## a_Instr ## _u32_fallback), \
2062 pDst, uSrc1, uSrc2, pEFlags); \
2063 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2064 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2065 IEM_MC_END(); \
2066 } \
2067 } \
2068 (void)0
2069
2070/** Body for SARX, SHLX, SHRX; assumes VEX.L must be 0. */
2071#define IEMOP_BODY_Gy_Ey_By_NoEflags(a_Instr, a_fFeatureMember) \
2072 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
2073 if (IEM_IS_MODRM_REG_MODE(bRm)) \
2074 { \
2075 /* \
2076 * Register, register. \
2077 */ \
2078 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2079 { \
2080 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
2081 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2082 IEM_MC_ARG(uint64_t *, pDst, 0); \
2083 IEM_MC_ARG(uint64_t, uSrc1, 1); \
2084 IEM_MC_ARG(uint64_t, uSrc2, 2); \
2085 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2086 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2087 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2088 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
2089 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
2090 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2091 IEM_MC_END(); \
2092 } \
2093 else \
2094 { \
2095 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
2096 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2097 IEM_MC_ARG(uint32_t *, pDst, 0); \
2098 IEM_MC_ARG(uint32_t, uSrc1, 1); \
2099 IEM_MC_ARG(uint32_t, uSrc2, 2); \
2100 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2101 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2102 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2103 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
2104 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
2105 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2106 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2107 IEM_MC_END(); \
2108 } \
2109 } \
2110 else \
2111 { \
2112 /* \
2113 * Register, memory. \
2114 */ \
2115 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2116 { \
2117 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
2118 IEM_MC_ARG(uint64_t *, pDst, 0); \
2119 IEM_MC_ARG(uint64_t, uSrc1, 1); \
2120 IEM_MC_ARG(uint64_t, uSrc2, 2); \
2121 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2122 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2123 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2124 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2125 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2126 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2127 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
2128 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
2129 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2130 IEM_MC_END(); \
2131 } \
2132 else \
2133 { \
2134 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
2135 IEM_MC_ARG(uint32_t *, pDst, 0); \
2136 IEM_MC_ARG(uint32_t, uSrc1, 1); \
2137 IEM_MC_ARG(uint32_t, uSrc2, 2); \
2138 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2139 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2140 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2141 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2142 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2143 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2144 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
2145 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
2146 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2147 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2148 IEM_MC_END(); \
2149 } \
2150 } \
2151 (void)0
2152
2153/**
2154 * @opcode 0xf5
2155 * @oppfx none
2156 * @opflmodify cf,pf,af,zf,sf,of
2157 * @opflclear of
2158 * @opflundef pf,af
2159 * @note VEX only
2160 */
2161FNIEMOP_DEF(iemOp_bzhi_Gy_Ey_By)
2162{
2163 IEMOP_MNEMONIC3(VEX_RMV, BZHI, bzhi, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2164 IEMOP_BODY_Gy_Ey_By(bzhi, fBmi2, X86_EFL_AF | X86_EFL_PF);
2165}
2166
2167/* Opcode VEX.66.0F38 0xf5 - invalid. */
2168
2169/** Body for PDEP and PEXT (similar to ANDN, except no EFLAGS). */
2170#define IEMOP_BODY_Gy_By_Ey_NoEflags(a_Instr, a_fFeatureMember) \
2171 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
2172 if (IEM_IS_MODRM_REG_MODE(bRm)) \
2173 { \
2174 /* \
2175 * Register, register. \
2176 */ \
2177 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2178 { \
2179 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
2180 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2181 IEM_MC_ARG(uint64_t *, pDst, 0); \
2182 IEM_MC_ARG(uint64_t, uSrc1, 1); \
2183 IEM_MC_ARG(uint64_t, uSrc2, 2); \
2184 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2185 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2186 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2187 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
2188 iemAImpl_ ## a_Instr ## _u64, \
2189 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
2190 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2191 IEM_MC_END(); \
2192 } \
2193 else \
2194 { \
2195 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
2196 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2197 IEM_MC_ARG(uint32_t *, pDst, 0); \
2198 IEM_MC_ARG(uint32_t, uSrc1, 1); \
2199 IEM_MC_ARG(uint32_t, uSrc2, 2); \
2200 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2201 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2202 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2203 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
2204 iemAImpl_ ## a_Instr ## _u32, \
2205 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
2206 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2207 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2208 IEM_MC_END(); \
2209 } \
2210 } \
2211 else \
2212 { \
2213 /* \
2214 * Register, memory. \
2215 */ \
2216 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2217 { \
2218 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
2219 IEM_MC_ARG(uint64_t *, pDst, 0); \
2220 IEM_MC_ARG(uint64_t, uSrc1, 1); \
2221 IEM_MC_ARG(uint64_t, uSrc2, 2); \
2222 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2223 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2224 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2225 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2226 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2227 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2228 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
2229 iemAImpl_ ## a_Instr ## _u64, \
2230 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
2231 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2232 IEM_MC_END(); \
2233 } \
2234 else \
2235 { \
2236 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); \
2237 IEM_MC_ARG(uint32_t *, pDst, 0); \
2238 IEM_MC_ARG(uint32_t, uSrc1, 1); \
2239 IEM_MC_ARG(uint32_t, uSrc2, 2); \
2240 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2241 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2242 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
2243 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2244 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
2245 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2246 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
2247 iemAImpl_ ## a_Instr ## _u32, \
2248 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
2249 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
2250 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2251 IEM_MC_END(); \
2252 } \
2253 } \
2254 (void)0
2255
2256
2257/** Opcode VEX.F3.0F38 0xf5 (vex only). */
2258FNIEMOP_DEF(iemOp_pext_Gy_By_Ey)
2259{
2260 IEMOP_MNEMONIC3(VEX_RVM, PEXT, pext, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2261 IEMOP_BODY_Gy_By_Ey_NoEflags(pext, fBmi2);
2262}
2263
2264
2265/** Opcode VEX.F2.0F38 0xf5 (vex only). */
2266FNIEMOP_DEF(iemOp_pdep_Gy_By_Ey)
2267{
2268 IEMOP_MNEMONIC3(VEX_RVM, PDEP, pdep, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2269 IEMOP_BODY_Gy_By_Ey_NoEflags(pdep, fBmi2);
2270}
2271
2272
2273/* Opcode VEX.0F38 0xf6 - invalid. */
2274/* Opcode VEX.66.0F38 0xf6 - invalid (legacy only). */
2275/* Opcode VEX.F3.0F38 0xf6 - invalid (legacy only). */
2276
2277
2278/**
2279 * @opcode 0xf6
2280 * @oppfx 0xf2
2281 * @opflclass unchanged
2282 */
2283FNIEMOP_DEF(iemOp_mulx_By_Gy_rDX_Ey)
2284{
2285 IEMOP_MNEMONIC4(VEX_RVM, MULX, mulx, Gy, By, Ey, rDX, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2286 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2287 if (IEM_IS_MODRM_REG_MODE(bRm))
2288 {
2289 /*
2290 * Register, register.
2291 */
2292 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2293 {
2294 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
2295 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
2296 IEM_MC_ARG(uint64_t *, pDst1, 0);
2297 IEM_MC_ARG(uint64_t *, pDst2, 1);
2298 IEM_MC_ARG(uint64_t, uSrc1, 2);
2299 IEM_MC_ARG(uint64_t, uSrc2, 3);
2300 IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
2301 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2302 IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
2303 IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
2304 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
2305 pDst1, pDst2, uSrc1, uSrc2);
2306 IEM_MC_ADVANCE_RIP_AND_FINISH();
2307 IEM_MC_END();
2308 }
2309 else
2310 {
2311 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2312 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
2313 IEM_MC_ARG(uint32_t *, pDst1, 0);
2314 IEM_MC_ARG(uint32_t *, pDst2, 1);
2315 IEM_MC_ARG(uint32_t, uSrc1, 2);
2316 IEM_MC_ARG(uint32_t, uSrc2, 3);
2317 IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
2318 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
2319 IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
2320 IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
2321 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
2322 pDst1, pDst2, uSrc1, uSrc2);
2323 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu));
2324 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
2325 IEM_MC_ADVANCE_RIP_AND_FINISH();
2326 IEM_MC_END();
2327 }
2328 }
2329 else
2330 {
2331 /*
2332 * Register, memory.
2333 */
2334 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2335 {
2336 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
2337 IEM_MC_ARG(uint64_t *, pDst1, 0);
2338 IEM_MC_ARG(uint64_t *, pDst2, 1);
2339 IEM_MC_ARG(uint64_t, uSrc1, 2);
2340 IEM_MC_ARG(uint64_t, uSrc2, 3);
2341 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2342 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2343 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
2344 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2345 IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
2346 IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
2347 IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
2348 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
2349 pDst1, pDst2, uSrc1, uSrc2);
2350 IEM_MC_ADVANCE_RIP_AND_FINISH();
2351 IEM_MC_END();
2352 }
2353 else
2354 {
2355 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
2356 IEM_MC_ARG(uint32_t *, pDst1, 0);
2357 IEM_MC_ARG(uint32_t *, pDst2, 1);
2358 IEM_MC_ARG(uint32_t, uSrc1, 2);
2359 IEM_MC_ARG(uint32_t, uSrc2, 3);
2360 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2361 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2362 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
2363 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2364 IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
2365 IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
2366 IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
2367 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
2368 pDst1, pDst2, uSrc1, uSrc2);
2369 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu));
2370 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
2371 IEM_MC_ADVANCE_RIP_AND_FINISH();
2372 IEM_MC_END();
2373 }
2374 }
2375}
2376
2377
2378/**
2379 * @opcode 0xf7
2380 * @oppfx none
2381 * @opflmodify cf,pf,af,zf,sf,of
2382 * @opflclear cf,of
2383 * @opflundef pf,af,sf
2384 */
2385FNIEMOP_DEF(iemOp_bextr_Gy_Ey_By)
2386{
2387 IEMOP_MNEMONIC3(VEX_RMV, BEXTR, bextr, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2388 IEMOP_BODY_Gy_Ey_By(bextr, fBmi1, X86_EFL_SF | X86_EFL_AF | X86_EFL_PF);
2389}
2390
2391
2392/**
2393 * @opcode 0xf7
2394 * @oppfx 0x66
2395 * @opflclass unchanged
2396 */
2397FNIEMOP_DEF(iemOp_shlx_Gy_Ey_By)
2398{
2399 IEMOP_MNEMONIC3(VEX_RMV, SHLX, shlx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2400 IEMOP_BODY_Gy_Ey_By_NoEflags(shlx, fBmi2);
2401}
2402
2403
2404/**
2405 * @opcode 0xf7
2406 * @oppfx 0xf3
2407 * @opflclass unchanged
2408 */
2409FNIEMOP_DEF(iemOp_sarx_Gy_Ey_By)
2410{
2411 IEMOP_MNEMONIC3(VEX_RMV, SARX, sarx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2412 IEMOP_BODY_Gy_Ey_By_NoEflags(sarx, fBmi2);
2413}
2414
2415
2416/**
2417 * @opcode 0xf7
2418 * @oppfx 0xf2
2419 * @opflclass unchanged
2420 */
2421FNIEMOP_DEF(iemOp_shrx_Gy_Ey_By)
2422{
2423 IEMOP_MNEMONIC3(VEX_RMV, SHRX, shrx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
2424 IEMOP_BODY_Gy_Ey_By_NoEflags(shrx, fBmi2);
2425}
2426
2427/* Opcode VEX.0F38 0xf8 - invalid. */
2428/* Opcode VEX.66.0F38 0xf8 - invalid. */
2429/* Opcode VEX.F3.0F38 0xf8 - invalid. */
2430/* Opcode VEX.F2.0F38 0xf8 - invalid. */
2431
2432/* Opcode VEX.0F38 0xf9 - invalid. */
2433/* Opcode VEX.66.0F38 0xf9 - invalid. */
2434/* Opcode VEX.F3.0F38 0xf9 - invalid. */
2435/* Opcode VEX.F2.0F38 0xf9 - invalid. */
2436
2437/* Opcode VEX.0F38 0xfa - invalid. */
2438/* Opcode VEX.66.0F38 0xfa - invalid. */
2439/* Opcode VEX.F3.0F38 0xfa - invalid. */
2440/* Opcode VEX.F2.0F38 0xfa - invalid. */
2441
2442/* Opcode VEX.0F38 0xfb - invalid. */
2443/* Opcode VEX.66.0F38 0xfb - invalid. */
2444/* Opcode VEX.F3.0F38 0xfb - invalid. */
2445/* Opcode VEX.F2.0F38 0xfb - invalid. */
2446
2447/* Opcode VEX.0F38 0xfc - invalid. */
2448/* Opcode VEX.66.0F38 0xfc - invalid. */
2449/* Opcode VEX.F3.0F38 0xfc - invalid. */
2450/* Opcode VEX.F2.0F38 0xfc - invalid. */
2451
2452/* Opcode VEX.0F38 0xfd - invalid. */
2453/* Opcode VEX.66.0F38 0xfd - invalid. */
2454/* Opcode VEX.F3.0F38 0xfd - invalid. */
2455/* Opcode VEX.F2.0F38 0xfd - invalid. */
2456
2457/* Opcode VEX.0F38 0xfe - invalid. */
2458/* Opcode VEX.66.0F38 0xfe - invalid. */
2459/* Opcode VEX.F3.0F38 0xfe - invalid. */
2460/* Opcode VEX.F2.0F38 0xfe - invalid. */
2461
2462/* Opcode VEX.0F38 0xff - invalid. */
2463/* Opcode VEX.66.0F38 0xff - invalid. */
2464/* Opcode VEX.F3.0F38 0xff - invalid. */
2465/* Opcode VEX.F2.0F38 0xff - invalid. */
2466
2467
2468/**
2469 * VEX opcode map \#2.
2470 *
2471 * @sa g_apfnThreeByte0f38
2472 */
2473const PFNIEMOP g_apfnVexMap2[] =
2474{
2475 /* no prefix, 066h prefix f3h prefix, f2h prefix */
2476 /* 0x00 */ iemOp_InvalidNeedRM, iemOp_vpshufb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2477 /* 0x01 */ iemOp_InvalidNeedRM, iemOp_vphaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2478 /* 0x02 */ iemOp_InvalidNeedRM, iemOp_vphaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2479 /* 0x03 */ iemOp_InvalidNeedRM, iemOp_vphaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2480 /* 0x04 */ iemOp_InvalidNeedRM, iemOp_vpmaddubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2481 /* 0x05 */ iemOp_InvalidNeedRM, iemOp_vphsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2482 /* 0x06 */ iemOp_InvalidNeedRM, iemOp_vphsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2483 /* 0x07 */ iemOp_InvalidNeedRM, iemOp_vphsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2484 /* 0x08 */ iemOp_InvalidNeedRM, iemOp_vpsignb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2485 /* 0x09 */ iemOp_InvalidNeedRM, iemOp_vpsignw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2486 /* 0x0a */ iemOp_InvalidNeedRM, iemOp_vpsignd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2487 /* 0x0b */ iemOp_InvalidNeedRM, iemOp_vpmulhrsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2488 /* 0x0c */ iemOp_InvalidNeedRM, iemOp_vpermilps_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2489 /* 0x0d */ iemOp_InvalidNeedRM, iemOp_vpermilpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2490 /* 0x0e */ iemOp_InvalidNeedRM, iemOp_vtestps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2491 /* 0x0f */ iemOp_InvalidNeedRM, iemOp_vtestpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2492
2493 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRM),
2494 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
2495 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
2496 /* 0x13 */ iemOp_InvalidNeedRM, iemOp_vcvtph2ps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2497 /* 0x14 */ IEMOP_X4(iemOp_InvalidNeedRM),
2498 /* 0x15 */ IEMOP_X4(iemOp_InvalidNeedRM),
2499 /* 0x16 */ iemOp_InvalidNeedRM, iemOp_vpermps_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2500 /* 0x17 */ iemOp_InvalidNeedRM, iemOp_vptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2501 /* 0x18 */ iemOp_InvalidNeedRM, iemOp_vbroadcastss_Vx_Wd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2502 /* 0x19 */ iemOp_InvalidNeedRM, iemOp_vbroadcastsd_Vqq_Wq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2503 /* 0x1a */ iemOp_InvalidNeedRM, iemOp_vbroadcastf128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2504 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
2505 /* 0x1c */ iemOp_InvalidNeedRM, iemOp_vpabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2506 /* 0x1d */ iemOp_InvalidNeedRM, iemOp_vpabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2507 /* 0x1e */ iemOp_InvalidNeedRM, iemOp_vpabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2508 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
2509
2510 /* 0x20 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2511 /* 0x21 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2512 /* 0x22 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2513 /* 0x23 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2514 /* 0x24 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2515 /* 0x25 */ iemOp_InvalidNeedRM, iemOp_vpmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2516 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
2517 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
2518 /* 0x28 */ iemOp_InvalidNeedRM, iemOp_vpmuldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2519 /* 0x29 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2520 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_vmovntdqa_Vx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2521 /* 0x2b */ iemOp_InvalidNeedRM, iemOp_vpackusdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2522 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2523 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2524 /* 0x2e */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2525 /* 0x2f */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2526
2527 /* 0x30 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2528 /* 0x31 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2529 /* 0x32 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2530 /* 0x33 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2531 /* 0x34 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2532 /* 0x35 */ iemOp_InvalidNeedRM, iemOp_vpmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2533 /* 0x36 */ iemOp_InvalidNeedRM, iemOp_vpermd_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2534 /* 0x37 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2535 /* 0x38 */ iemOp_InvalidNeedRM, iemOp_vpminsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2536 /* 0x39 */ iemOp_InvalidNeedRM, iemOp_vpminsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2537 /* 0x3a */ iemOp_InvalidNeedRM, iemOp_vpminuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2538 /* 0x3b */ iemOp_InvalidNeedRM, iemOp_vpminud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2539 /* 0x3c */ iemOp_InvalidNeedRM, iemOp_vpmaxsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2540 /* 0x3d */ iemOp_InvalidNeedRM, iemOp_vpmaxsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2541 /* 0x3e */ iemOp_InvalidNeedRM, iemOp_vpmaxuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2542 /* 0x3f */ iemOp_InvalidNeedRM, iemOp_vpmaxud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2543
2544 /* 0x40 */ iemOp_InvalidNeedRM, iemOp_vpmulld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2545 /* 0x41 */ iemOp_InvalidNeedRM, iemOp_vphminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2546 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
2547 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
2548 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
2549 /* 0x45 */ iemOp_InvalidNeedRM, iemOp_vpsrlvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2550 /* 0x46 */ iemOp_InvalidNeedRM, iemOp_vpsravd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2551 /* 0x47 */ iemOp_InvalidNeedRM, iemOp_vpsllvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2552 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
2553 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
2554 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
2555 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
2556 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
2557 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
2558 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
2559 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
2560
2561 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
2562 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
2563 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
2564 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
2565 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
2566 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
2567 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
2568 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
2569 /* 0x58 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2570 /* 0x59 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2571 /* 0x5a */ iemOp_InvalidNeedRM, iemOp_vbroadcasti128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2572 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
2573 /* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
2574 /* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
2575 /* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
2576 /* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
2577
2578 /* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
2579 /* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
2580 /* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
2581 /* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
2582 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
2583 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
2584 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
2585 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
2586 /* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
2587 /* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
2588 /* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
2589 /* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
2590 /* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
2591 /* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
2592 /* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
2593 /* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
2594
2595 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
2596 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
2597 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
2598 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
2599 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
2600 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
2601 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
2602 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
2603 /* 0x78 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2604 /* 0x79 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2605 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
2606 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
2607 /* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
2608 /* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
2609 /* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
2610 /* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
2611
2612 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
2613 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
2614 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
2615 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
2616 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
2617 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
2618 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
2619 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
2620 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
2621 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
2622 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
2623 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
2624 /* 0x8c */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2625 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
2626 /* 0x8e */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Mx_Vx_Hx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2627 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
2628
2629 /* 0x90 */ iemOp_InvalidNeedRM, iemOp_vpgatherdd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2630 /* 0x91 */ iemOp_InvalidNeedRM, iemOp_vpgatherqd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2631 /* 0x92 */ iemOp_InvalidNeedRM, iemOp_vgatherdps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2632 /* 0x93 */ iemOp_InvalidNeedRM, iemOp_vgatherqps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2633 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
2634 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
2635 /* 0x96 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2636 /* 0x97 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2637 /* 0x98 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2638 /* 0x99 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2639 /* 0x9a */ iemOp_InvalidNeedRM, iemOp_vfmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2640 /* 0x9b */ iemOp_InvalidNeedRM, iemOp_vfmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2641 /* 0x9c */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2642 /* 0x9d */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2643 /* 0x9e */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2644 /* 0x9f */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2645
2646 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2647 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2648 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2649 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2650 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2651 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2652 /* 0xa6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2653 /* 0xa7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2654 /* 0xa8 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2655 /* 0xa9 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2656 /* 0xaa */ iemOp_InvalidNeedRM, iemOp_vfmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2657 /* 0xab */ iemOp_InvalidNeedRM, iemOp_vfmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2658 /* 0xac */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2659 /* 0xad */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2660 /* 0xae */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2661 /* 0xaf */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2662
2663 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2664 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2665 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2666 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2667 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2668 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2669 /* 0xb6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2670 /* 0xb7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2671 /* 0xb8 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2672 /* 0xb9 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2673 /* 0xba */ iemOp_InvalidNeedRM, iemOp_vfmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2674 /* 0xbb */ iemOp_InvalidNeedRM, iemOp_vfmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2675 /* 0xbc */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2676 /* 0xbd */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2677 /* 0xbe */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2678 /* 0xbf */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2679
2680 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2681 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2682 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2683 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2684 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2685 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2686 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2687 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2688 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2689 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2690 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
2691 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
2692 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
2693 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
2694 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
2695 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
2696
2697 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2698 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2699 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2700 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2701 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2702 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2703 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2704 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2705 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2706 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2707 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
2708 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vaesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2709 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vaesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2710 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vaesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2711 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vaesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2712 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vaesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2713
2714 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2715 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2716 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2717 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2718 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2719 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2720 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2721 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2722 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2723 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2724 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
2725 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
2726 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
2727 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
2728 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
2729 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
2730
2731 /* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2732 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2733 /* 0xf2 */ iemOp_andn_Gy_By_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2734 /* 0xf3 */ iemOp_VGrp17_f3, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2735 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2736 /* 0xf5 */ iemOp_bzhi_Gy_Ey_By, iemOp_InvalidNeedRM, iemOp_pext_Gy_By_Ey, iemOp_pdep_Gy_By_Ey,
2737 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_mulx_By_Gy_rDX_Ey,
2738 /* 0xf7 */ iemOp_bextr_Gy_Ey_By, iemOp_shlx_Gy_Ey_By, iemOp_sarx_Gy_Ey_By, iemOp_shrx_Gy_Ey_By,
2739 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2740 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2741 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
2742 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
2743 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
2744 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
2745 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
2746 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
2747};
2748AssertCompile(RT_ELEMENTS(g_apfnVexMap2) == 1024);
2749
2750/** @} */
2751
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