IEMAllInstVexMap3.cpp.h@ 103922

Last change on this file since 103922 was 103922, checked in by vboxsync, 9 months ago
VMM/IEM: Fixed the remaining decoding issues with vblendvps/d. bugref:9898
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 77.8 KB

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1	/* $Id: IEMAllInstVexMap3.cpp.h 103922 2024-03-19 16:10:02Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4	*
5	* @remarks IEMAllInstThree0f3a.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
11	*
12	* This file is part of VirtualBox base platform packages, as
13	* available from https://www.virtualbox.org.
14	*
15	* This program is free software; you can redistribute it and/or
16	* modify it under the terms of the GNU General Public License
17	* as published by the Free Software Foundation, in version 3 of the
18	* License.
19	*
20	* This program is distributed in the hope that it will be useful, but
21	* WITHOUT ANY WARRANTY; without even the implied warranty of
22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23	* General Public License for more details.
24	*
25	* You should have received a copy of the GNU General Public License
26	* along with this program; if not, see <https://www.gnu.org/licenses>.
27	*
28	* SPDX-License-Identifier: GPL-3.0-only
29	*/
30
31
32	/** @name VEX Opcode Map 3
33	* @{
34	*/
35
36	/**
37	* Common worker for AVX2 instructions on the forms:
38	* - vpxxx xmm0, xmm1, xmm2/mem128, imm8
39	* - vpxxx ymm0, ymm1, ymm2/mem256, imm8
40	*
41	* Takes function table for function w/o implicit state parameter.
42	*
43	* Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
44	*/
45	FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF3IMM8, pImpl)
46	{
47	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48	if (IEM_IS_MODRM_REG_MODE(bRm))
49	{
50	/*
51	* Register, register.
52	*/
53	if (pVCpu->iem.s.uVexLength)
54	{
55	IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
56	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
57	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
58	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
59	IEM_MC_PREPARE_AVX_USAGE();
60
61	IEM_MC_LOCAL(RTUINT256U, uDst);
62	IEM_MC_LOCAL(RTUINT256U, uSrc1);
63	IEM_MC_LOCAL(RTUINT256U, uSrc2);
64	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
65	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
66	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
67	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
68	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
69	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
70	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
71	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
72	IEM_MC_ADVANCE_RIP_AND_FINISH();
73	IEM_MC_END();
74	}
75	else
76	{
77	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
78	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
79	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
80	IEM_MC_ARG(PRTUINT128U, puDst, 0);
81	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
82	IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
83	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
84	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
85	IEM_MC_PREPARE_AVX_USAGE();
86	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
87	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
88	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
89	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
90	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
91	IEM_MC_ADVANCE_RIP_AND_FINISH();
92	IEM_MC_END();
93	}
94	}
95	else
96	{
97	/*
98	* Register, memory.
99	*/
100	if (pVCpu->iem.s.uVexLength)
101	{
102	IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
103	IEM_MC_LOCAL(RTUINT256U, uDst);
104	IEM_MC_LOCAL(RTUINT256U, uSrc1);
105	IEM_MC_LOCAL(RTUINT256U, uSrc2);
106	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
107	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
108	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
109	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
110
111	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
112	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
113	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
114	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
115	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
116	IEM_MC_PREPARE_AVX_USAGE();
117
118	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
119	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
120	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
121	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
122
123	IEM_MC_ADVANCE_RIP_AND_FINISH();
124	IEM_MC_END();
125	}
126	else
127	{
128	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
129	IEM_MC_LOCAL(RTUINT128U, uSrc2);
130	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
131	IEM_MC_ARG(PRTUINT128U, puDst, 0);
132	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
133	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
134
135	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
136	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
137	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
138	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
139	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
140	IEM_MC_PREPARE_AVX_USAGE();
141
142	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
143	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
144	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
145	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
146	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
147
148	IEM_MC_ADVANCE_RIP_AND_FINISH();
149	IEM_MC_END();
150	}
151	}
152	}
153
154
155	/**
156	* Common worker for AVX instructions on the forms:
157	* - vpermilps/d xmm0, xmm1/mem128, imm8
158	* - vpermilps/d ymm0, ymm1/mem256, imm8
159	*
160	* Takes function table for function w/o implicit state parameter.
161	*
162	* Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operation.
163	*/
164	FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF2IMM8, pImpl)
165	{
166	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
167	if (IEM_IS_MODRM_REG_MODE(bRm))
168	{
169	/*
170	* Register, register.
171	*/
172	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
173	if (pVCpu->iem.s.uVexLength)
174	{
175	IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
176	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
177	IEM_MC_LOCAL(RTUINT256U, uDst);
178	IEM_MC_LOCAL(RTUINT256U, uSrc);
179	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
180	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
181	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
182	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
183	IEM_MC_PREPARE_AVX_USAGE();
184	IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
185	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc, bImmArg);
186	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
187	IEM_MC_ADVANCE_RIP_AND_FINISH();
188	IEM_MC_END();
189	}
190	else
191	{
192	IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
193	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
194	IEM_MC_ARG(PRTUINT128U, puDst, 0);
195	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
196	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
197	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
198	IEM_MC_PREPARE_AVX_USAGE();
199	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
200	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
201	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc, bImmArg);
202	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
203	IEM_MC_ADVANCE_RIP_AND_FINISH();
204	IEM_MC_END();
205	}
206	}
207	else
208	{
209	/*
210	* Register, memory.
211	*/
212	if (pVCpu->iem.s.uVexLength)
213	{
214	IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
215	IEM_MC_LOCAL(RTUINT256U, uDst);
216	IEM_MC_LOCAL(RTUINT256U, uSrc);
217	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
218	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
219	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
220
221	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
222	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
223	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
224	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
225	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
226	IEM_MC_PREPARE_AVX_USAGE();
227
228	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
229	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc, bImmArg);
230	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
231
232	IEM_MC_ADVANCE_RIP_AND_FINISH();
233	IEM_MC_END();
234	}
235	else
236	{
237	IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
238	IEM_MC_LOCAL(RTUINT128U, uSrc);
239	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
240	IEM_MC_ARG(PRTUINT128U, puDst, 0);
241	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
242
243	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
244	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
245	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
246	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
247	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
248	IEM_MC_PREPARE_AVX_USAGE();
249
250	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
251	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
252	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc, bImmArg);
253	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
254
255	IEM_MC_ADVANCE_RIP_AND_FINISH();
256	IEM_MC_END();
257	}
258	}
259	}
260
261
262	/**
263	* Common worker for AVX instructions on the forms:
264	* - vblendps/d xmm0, xmm1, xmm2/mem128, imm8
265	* - vblendps/d ymm0, ymm1, ymm2/mem256, imm8
266	*
267	* Takes function table for function w/o implicit state parameter.
268	*
269	* Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operation.
270	*/
271	FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF3IMM8, pImpl)
272	{
273	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
274	if (IEM_IS_MODRM_REG_MODE(bRm))
275	{
276	/*
277	* Register, register.
278	*/
279	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
280	if (pVCpu->iem.s.uVexLength)
281	{
282	IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
283	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
284	IEM_MC_LOCAL(RTUINT256U, uDst);
285	IEM_MC_LOCAL(RTUINT256U, uSrc1);
286	IEM_MC_LOCAL(RTUINT256U, uSrc2);
287	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
288	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
289	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
290	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
291	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
292	IEM_MC_PREPARE_AVX_USAGE();
293	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
294	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
295	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
296	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
297	IEM_MC_ADVANCE_RIP_AND_FINISH();
298	IEM_MC_END();
299	}
300	else
301	{
302	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
303	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
304	IEM_MC_ARG(PRTUINT128U, puDst, 0);
305	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
306	IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
307	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
308	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
309	IEM_MC_PREPARE_AVX_USAGE();
310	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
311	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
312	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
313	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
314	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
315	IEM_MC_ADVANCE_RIP_AND_FINISH();
316	IEM_MC_END();
317	}
318	}
319	else
320	{
321	/*
322	* Register, memory.
323	*/
324	if (pVCpu->iem.s.uVexLength)
325	{
326	IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
327	IEM_MC_LOCAL(RTUINT256U, uDst);
328	IEM_MC_LOCAL(RTUINT256U, uSrc1);
329	IEM_MC_LOCAL(RTUINT256U, uSrc2);
330	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
331	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
332	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
333	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
334
335	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
336	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
337	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
338	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
339	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
340	IEM_MC_PREPARE_AVX_USAGE();
341
342	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
343	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
344	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
345	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
346
347	IEM_MC_ADVANCE_RIP_AND_FINISH();
348	IEM_MC_END();
349	}
350	else
351	{
352	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
353	IEM_MC_LOCAL(RTUINT128U, uSrc2);
354	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
355	IEM_MC_ARG(PRTUINT128U, puDst, 0);
356	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
357	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
358
359	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
360	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
361	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
362	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
363	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
364	IEM_MC_PREPARE_AVX_USAGE();
365
366	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
367	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
368	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
369	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
370	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
371
372	IEM_MC_ADVANCE_RIP_AND_FINISH();
373	IEM_MC_END();
374	}
375	}
376	}
377
378
379	/** Opcode VEX.66.0F3A 0x00. */
380	FNIEMOP_STUB(iemOp_vpermq_Vqq_Wqq_Ib);
381	/** Opcode VEX.66.0F3A 0x01. */
382	FNIEMOP_STUB(iemOp_vpermqd_Vqq_Wqq_Ib);
383
384
385	/** Opcode VEX.66.0F3A 0x02.
386	* AVX2,AVX2 */
387	FNIEMOP_DEF(iemOp_vpblendd_Vx_Hx_Wx_Ib)
388	{
389	IEMOP_MNEMONIC4(VEX_RVMI, VPBLENDD, vpblendd, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
390	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpblendd);
391	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
392	}
393
394
395	/* Opcode VEX.66.0F3A 0x03 - invalid */
396
397
398	/** Opcode VEX.66.0F3A 0x04.
399	* AVX,AVX */
400	FNIEMOP_DEF(iemOp_vpermilps_Vx_Wx_Ib)
401	{
402	IEMOP_MNEMONIC3(VEX_RMI, VPERMILPS, vpermilps, Vx_WO, Wx, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_V_ZERO);
403	IEMOPMEDIAOPTF2IMM8_INIT_VARS(vpermilps);
404	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
405	}
406
407
408	/** Opcode VEX.66.0F3A 0x05.
409	* AVX,AVX */
410	FNIEMOP_DEF(iemOp_vpermilpd_Vx_Wx_Ib)
411	{
412	IEMOP_MNEMONIC3(VEX_RMI, VPERMILPD, vpermilpd, Vx_WO, Wx, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_V_ZERO);
413	IEMOPMEDIAOPTF2IMM8_INIT_VARS(vpermilpd);
414	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
415	}
416
417
418	/** Opcode VEX.66.0F3A 0x06 (vex only) */
419	FNIEMOP_DEF(iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib)
420	{
421	IEMOP_MNEMONIC4(VEX_RVMI, VPERM2F128, vperm2f128, Vqq_WO, Hqq, Wqq, Ib, DISOPTYPE_HARMLESS, 0);
422	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
423	if (IEM_IS_MODRM_REG_MODE(bRm))
424	{
425	/*
426	* Register, register.
427	*/
428	IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
429	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
430	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
431	IEM_MC_LOCAL(RTUINT256U, uDst);
432	IEM_MC_LOCAL(RTUINT256U, uSrc1);
433	IEM_MC_LOCAL(RTUINT256U, uSrc2);
434	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
435	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
436	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
437	IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
438	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
439	IEM_MC_PREPARE_AVX_USAGE();
440	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
441	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
442	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback),
443	puDst, puSrc1, puSrc2, bImmArg);
444	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
445	IEM_MC_ADVANCE_RIP_AND_FINISH();
446	IEM_MC_END();
447	}
448	else
449	{
450	/*
451	* Register, memory.
452	*/
453	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
454	IEM_MC_LOCAL(RTUINT256U, uDst);
455	IEM_MC_LOCAL(RTUINT256U, uSrc1);
456	IEM_MC_LOCAL(RTUINT256U, uSrc2);
457	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
458	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
459	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
460	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
461
462	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
463	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
464	IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
465	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
466	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
467	IEM_MC_PREPARE_AVX_USAGE();
468
469	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
470	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
471	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback),
472	puDst, puSrc1, puSrc2, bImmArg);
473	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
474
475	IEM_MC_ADVANCE_RIP_AND_FINISH();
476	IEM_MC_END();
477	}
478	}
479
480
481	/* Opcode VEX.66.0F3A 0x07 - invalid */
482	/** Opcode VEX.66.0F3A 0x08. */
483	FNIEMOP_STUB(iemOp_vroundps_Vx_Wx_Ib);
484	/** Opcode VEX.66.0F3A 0x09. */
485	FNIEMOP_STUB(iemOp_vroundpd_Vx_Wx_Ib);
486	/** Opcode VEX.66.0F3A 0x0a. */
487	FNIEMOP_STUB(iemOp_vroundss_Vss_Wss_Ib);
488	/** Opcode VEX.66.0F3A 0x0b. */
489	FNIEMOP_STUB(iemOp_vroundsd_Vsd_Wsd_Ib);
490
491
492	/** Opcode VEX.66.0F3A 0x0c.
493	* AVX,AVX */
494	FNIEMOP_DEF(iemOp_vblendps_Vx_Hx_Wx_Ib)
495	{
496	IEMOP_MNEMONIC4(VEX_RVMI, VBLENDPS, vblendps, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
497	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendps);
498	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
499	}
500
501
502	/** Opcode VEX.66.0F3A 0x0d.
503	* AVX,AVX */
504	FNIEMOP_DEF(iemOp_vblendpd_Vx_Hx_Wx_Ib)
505	{
506	IEMOP_MNEMONIC4(VEX_RVMI, VBLENDPD, vblendpd, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
507	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendpd);
508	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
509	}
510
511
512	/** Opcode VEX.66.0F3A 0x0e.
513	* AVX,AVX2 */
514	FNIEMOP_DEF(iemOp_vpblendw_Vx_Hx_Wx_Ib)
515	{
516	IEMOP_MNEMONIC4(VEX_RVMI, VPBLENDW, vpblendw, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
517	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpblendw);
518	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
519	}
520
521
522	/** Opcode VEX.0F3A 0x0f - invalid. */
523
524
525	/** Opcode VEX.66.0F3A 0x0f.
526	* AVX,AVX2 */
527	FNIEMOP_DEF(iemOp_vpalignr_Vx_Hx_Wx_Ib)
528	{
529	IEMOP_MNEMONIC4(VEX_RVMI, VPALIGNR, vpalignr, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
530	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpalignr);
531	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
532	}
533
534
535	/* Opcode VEX.66.0F3A 0x10 - invalid */
536	/* Opcode VEX.66.0F3A 0x11 - invalid */
537	/* Opcode VEX.66.0F3A 0x12 - invalid */
538	/* Opcode VEX.66.0F3A 0x13 - invalid */
539
540
541	/** Opcode VEX.66.0F3A 0x14 - vpextrb Eb, Vdq, Ib */
542	FNIEMOP_DEF(iemOp_vpextrb_Eb_Vdq_Ib)
543	{
544	IEMOP_MNEMONIC3(VEX_MRI, VPEXTRB, vpextrb, Eb, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO \| IEMOPHINT_VEX_V_ZERO); /** @todo */
545	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
546	if (IEM_IS_MODRM_REG_MODE(bRm))
547	{
548	/*
549	* greg32, XMM, imm8.
550	*/
551	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
552	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
553	IEM_MC_LOCAL(uint8_t, uValue);
554
555	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
556	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
557	IEM_MC_PREPARE_AVX_USAGE();
558
559	IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /a_iByte/);
560	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
561	IEM_MC_ADVANCE_RIP_AND_FINISH();
562	IEM_MC_END();
563	}
564	else
565	{
566	/*
567	* [mem8], XMM, imm8.
568	*/
569	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
570	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
571	IEM_MC_LOCAL(uint8_t, uValue);
572	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
573	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
574
575	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
576	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
577	IEM_MC_PREPARE_AVX_USAGE();
578
579	IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /a_iByte/);
580	IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
581	IEM_MC_ADVANCE_RIP_AND_FINISH();
582	IEM_MC_END();
583	}
584	}
585
586
587	/** Opcode VEX.66.0F3A 0x15 - vpextrw Ew, Vdq, Ib */
588	FNIEMOP_DEF(iemOp_vpextrw_Ew_Vdq_Ib)
589	{
590	IEMOP_MNEMONIC3(VEX_MRI, VPEXTRW, vpextrw, Ew_WO, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO \| IEMOPHINT_VEX_V_ZERO);
591	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
592	if (IEM_IS_MODRM_REG_MODE(bRm))
593	{
594	/*
595	* greg32, XMM, imm8.
596	*/
597	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
598	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
599	IEM_MC_LOCAL(uint16_t, uValue);
600
601	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
602	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
603	IEM_MC_PREPARE_AVX_USAGE();
604
605	IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7);
606	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
607	IEM_MC_ADVANCE_RIP_AND_FINISH();
608	IEM_MC_END();
609	}
610	else
611	{
612	/*
613	* [mem16], XMM, imm8.
614	*/
615	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
616	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
617	IEM_MC_LOCAL(uint16_t, uValue);
618	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
619	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
620
621	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
622	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
623	IEM_MC_PREPARE_AVX_USAGE();
624
625	IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7);
626	IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
627	IEM_MC_ADVANCE_RIP_AND_FINISH();
628	IEM_MC_END();
629	}
630	}
631
632
633	/** Opcode VEX.66.0F3A 0x16 - vpextrd / vpextrq Eq / Ey, Vdq, Ib */
634	FNIEMOP_DEF(iemOp_vpextrd_q_Ey_Vdq_Ib)
635	{
636	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
637	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
638	{
639	IEMOP_MNEMONIC3(VEX_MRI, VPEXTRQ, vpextrq, Eq_WO, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES \| IEMOPHINT_VEX_L_ZERO); /** @todo */
640	if (IEM_IS_MODRM_REG_MODE(bRm))
641	{
642	/*
643	* greg64, XMM, imm8.
644	*/
645	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
646	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
647	IEM_MC_LOCAL(uint64_t, uValue);
648
649	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
650	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
651	IEM_MC_PREPARE_AVX_USAGE();
652
653	IEM_MC_FETCH_XREG_U64(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
654	IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
655	IEM_MC_ADVANCE_RIP_AND_FINISH();
656	IEM_MC_END();
657	}
658	else
659	{
660	/*
661	* [mem64], XMM, imm8.
662	*/
663	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
664	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
665	IEM_MC_LOCAL(uint64_t, uValue);
666	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
667	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
668
669	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
670	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
671	IEM_MC_PREPARE_AVX_USAGE();
672
673	IEM_MC_FETCH_XREG_U64(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
674	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
675	IEM_MC_ADVANCE_RIP_AND_FINISH();
676	IEM_MC_END();
677	}
678	}
679	else
680	{
681	/**
682	* @opdone
683	*/
684	IEMOP_MNEMONIC3(VEX_MRI, VPEXTRD, vpextrd, Ey, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES \| IEMOPHINT_VEX_L_ZERO); /** @todo */
685	if (IEM_IS_MODRM_REG_MODE(bRm))
686	{
687	/*
688	* greg32, XMM, imm8.
689	*/
690	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
691	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
692	IEM_MC_LOCAL(uint32_t, uValue);
693
694	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
695	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
696	IEM_MC_PREPARE_AVX_USAGE();
697
698	IEM_MC_FETCH_XREG_U32(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3);
699	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
700	IEM_MC_ADVANCE_RIP_AND_FINISH();
701	IEM_MC_END();
702	}
703	else
704	{
705	/*
706	* [mem32], XMM, imm8.
707	*/
708	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
709	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
710	IEM_MC_LOCAL(uint32_t, uValue);
711	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
712	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
713
714	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
715	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
716	IEM_MC_PREPARE_AVX_USAGE();
717
718	IEM_MC_FETCH_XREG_U32(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3);
719	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
720	IEM_MC_ADVANCE_RIP_AND_FINISH();
721	IEM_MC_END();
722	}
723	}
724	}
725
726
727	/** Opcode VEX.66.0F3A 0x17. */
728	FNIEMOP_STUB(iemOp_vextractps_Ed_Vdq_Ib);
729
730
731	/** Opcode VEX.66.0F3A 0x18 (vex only). */
732	FNIEMOP_DEF(iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib)
733	{
734	//IEMOP_MNEMONIC4(VEX_RMI, VINSERTF128, vinsertf128, Vx, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
735	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
736	if (IEM_IS_MODRM_REG_MODE(bRm))
737	{
738	/*
739	* Register, register.
740	*/
741	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
742	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
743	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
744	IEM_MC_LOCAL(RTUINT128U, uSrc);
745
746	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
747	IEM_MC_PREPARE_AVX_USAGE();
748
749	IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
750	IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
751	IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
752
753	IEM_MC_ADVANCE_RIP_AND_FINISH();
754	IEM_MC_END();
755	}
756	else
757	{
758	/*
759	* Register, memory.
760	*/
761	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
762	IEM_MC_LOCAL(RTUINT128U, uSrc);
763	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
764
765	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
766	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
767	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
768	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
769	IEM_MC_PREPARE_AVX_USAGE();
770
771	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
772	IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
773	IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
774
775	IEM_MC_ADVANCE_RIP_AND_FINISH();
776	IEM_MC_END();
777	}
778	}
779
780
781	/** Opcode VEX.66.0F3A 0x19 (vex only). */
782	FNIEMOP_STUB(iemOp_vextractf128_Wdq_Vqq_Ib);
783	/* Opcode VEX.66.0F3A 0x1a - invalid */
784	/* Opcode VEX.66.0F3A 0x1b - invalid */
785	/* Opcode VEX.66.0F3A 0x1c - invalid */
786	/** Opcode VEX.66.0F3A 0x1d (vex only). */
787	FNIEMOP_STUB(iemOp_vcvtps2ph_Wx_Vx_Ib);
788	/* Opcode VEX.66.0F3A 0x1e - invalid */
789	/* Opcode VEX.66.0F3A 0x1f - invalid */
790
791
792	/** Opcode VEX.66.0F3A 0x20. */
793	FNIEMOP_STUB(iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib);
794	/** Opcode VEX.66.0F3A 0x21, */
795	FNIEMOP_STUB(iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib);
796	/** Opcode VEX.66.0F3A 0x22. */
797	FNIEMOP_STUB(iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib);
798	/* Opcode VEX.66.0F3A 0x23 - invalid */
799	/* Opcode VEX.66.0F3A 0x24 - invalid */
800	/* Opcode VEX.66.0F3A 0x25 - invalid */
801	/* Opcode VEX.66.0F3A 0x26 - invalid */
802	/* Opcode VEX.66.0F3A 0x27 - invalid */
803	/* Opcode VEX.66.0F3A 0x28 - invalid */
804	/* Opcode VEX.66.0F3A 0x29 - invalid */
805	/* Opcode VEX.66.0F3A 0x2a - invalid */
806	/* Opcode VEX.66.0F3A 0x2b - invalid */
807	/* Opcode VEX.66.0F3A 0x2c - invalid */
808	/* Opcode VEX.66.0F3A 0x2d - invalid */
809	/* Opcode VEX.66.0F3A 0x2e - invalid */
810	/* Opcode VEX.66.0F3A 0x2f - invalid */
811
812
813	/* Opcode VEX.66.0F3A 0x30 - invalid */
814	/* Opcode VEX.66.0F3A 0x31 - invalid */
815	/* Opcode VEX.66.0F3A 0x32 - invalid */
816	/* Opcode VEX.66.0F3A 0x33 - invalid */
817	/* Opcode VEX.66.0F3A 0x34 - invalid */
818	/* Opcode VEX.66.0F3A 0x35 - invalid */
819	/* Opcode VEX.66.0F3A 0x36 - invalid */
820	/* Opcode VEX.66.0F3A 0x37 - invalid */
821
822
823	/** Opcode VEX.66.0F3A 0x38 (vex only). */
824	FNIEMOP_DEF(iemOp_vinserti128_Vqq_Hqq_Wqq_Ib)
825	{
826	//IEMOP_MNEMONIC4(VEX_RMI, VINSERTI128, vinserti128, Vx, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
827	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
828	if (IEM_IS_MODRM_REG_MODE(bRm))
829	{
830	/*
831	* Register, register.
832	*/
833	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
834	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
835	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
836	IEM_MC_LOCAL(RTUINT128U, uSrc);
837
838	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
839	IEM_MC_PREPARE_AVX_USAGE();
840
841	IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
842	IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
843	IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
844
845	IEM_MC_ADVANCE_RIP_AND_FINISH();
846	IEM_MC_END();
847	}
848	else
849	{
850	/*
851	* Register, memory.
852	*/
853	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
854	IEM_MC_LOCAL(RTUINT128U, uSrc);
855	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
856
857	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
858	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
859	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
860	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
861	IEM_MC_PREPARE_AVX_USAGE();
862
863	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
864	IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
865	IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
866
867	IEM_MC_ADVANCE_RIP_AND_FINISH();
868	IEM_MC_END();
869	}
870	}
871
872
873	/** Opcode VEX.66.0F3A 0x39 (vex only). */
874	FNIEMOP_STUB(iemOp_vextracti128_Wdq_Vqq_Ib);
875	/* Opcode VEX.66.0F3A 0x3a - invalid */
876	/* Opcode VEX.66.0F3A 0x3b - invalid */
877	/* Opcode VEX.66.0F3A 0x3c - invalid */
878	/* Opcode VEX.66.0F3A 0x3d - invalid */
879	/* Opcode VEX.66.0F3A 0x3e - invalid */
880	/* Opcode VEX.66.0F3A 0x3f - invalid */
881
882
883	/** Opcode VEX.66.0F3A 0x40. */
884	FNIEMOP_STUB(iemOp_vdpps_Vx_Hx_Wx_Ib);
885	/** Opcode VEX.66.0F3A 0x41, */
886	FNIEMOP_STUB(iemOp_vdppd_Vdq_Hdq_Wdq_Ib);
887
888
889	/** Opcode VEX.66.0F3A 0x42. */
890	FNIEMOP_DEF(iemOp_vmpsadbw_Vx_Hx_Wx_Ib)
891	{
892	IEMOP_MNEMONIC4(VEX_RVMI, VMPSADBW, vmpsadbw, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
893	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vmpsadbw);
894	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
895	}
896
897
898	/* Opcode VEX.66.0F3A 0x43 - invalid */
899
900
901	/** Opcode VEX.66.0F3A 0x44. */
902	FNIEMOP_DEF(iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib)
903	{
904	IEMOP_MNEMONIC4(VEX_RVMI, VPCLMULQDQ, vpclmulqdq, Vdq_WO, Hdq, Wdq, Id, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
905	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
906	if (IEM_IS_MODRM_REG_MODE(bRm))
907	{
908	/*
909	* Register, register.
910	*/
911	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
912	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
913	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
914	IEM_MC_ARG(PRTUINT128U, puDst, 0);
915	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
916	IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
917	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
918	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
919	IEM_MC_PREPARE_AVX_USAGE();
920	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
921	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
922	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
923	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
924	puDst, puSrc1, puSrc2, bImmArg);
925	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
926	IEM_MC_ADVANCE_RIP_AND_FINISH();
927	IEM_MC_END();
928	}
929	else
930	{
931	/*
932	* Register, memory.
933	*/
934	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
935	IEM_MC_LOCAL(RTUINT128U, uSrc2);
936	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
937	IEM_MC_ARG(PRTUINT128U, puDst, 0);
938	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
939	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
940
941	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
942	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
943	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
944	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
945	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
946	IEM_MC_PREPARE_AVX_USAGE();
947
948	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
949	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
950	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
951	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
952	puDst, puSrc1, puSrc2, bImmArg);
953	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
954
955	IEM_MC_ADVANCE_RIP_AND_FINISH();
956	IEM_MC_END();
957	}
958	}
959
960
961	/* Opcode VEX.66.0F3A 0x45 - invalid */
962
963
964	/** Opcode VEX.66.0F3A 0x46 (vex only) */
965	FNIEMOP_DEF(iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib)
966	{
967	IEMOP_MNEMONIC4(VEX_RVMI, VPERM2I128, vperm2i128, Vqq_WO, Hqq, Wqq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ONE);
968	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
969	if (IEM_IS_MODRM_REG_MODE(bRm))
970	{
971	/*
972	* Register, register.
973	*/
974	IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
975	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
976	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
977	IEM_MC_LOCAL(RTUINT256U, uDst);
978	IEM_MC_LOCAL(RTUINT256U, uSrc1);
979	IEM_MC_LOCAL(RTUINT256U, uSrc2);
980	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
981	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
982	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
983	IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
984	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
985	IEM_MC_PREPARE_AVX_USAGE();
986	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
987	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
988	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback),
989	puDst, puSrc1, puSrc2, bImmArg);
990	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
991	IEM_MC_ADVANCE_RIP_AND_FINISH();
992	IEM_MC_END();
993	}
994	else
995	{
996	/*
997	* Register, memory.
998	*/
999	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1000	IEM_MC_LOCAL(RTUINT256U, uDst);
1001	IEM_MC_LOCAL(RTUINT256U, uSrc1);
1002	IEM_MC_LOCAL(RTUINT256U, uSrc2);
1003	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1004	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1005	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1006	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1007
1008	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1009	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1010	IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
1011	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
1012	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1013	IEM_MC_PREPARE_AVX_USAGE();
1014
1015	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1016	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1017	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback),
1018	puDst, puSrc1, puSrc2, bImmArg);
1019	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1020
1021	IEM_MC_ADVANCE_RIP_AND_FINISH();
1022	IEM_MC_END();
1023	}
1024	}
1025
1026
1027	/* Opcode VEX.66.0F3A 0x47 - invalid */
1028	/** Opcode VEX.66.0F3A 0x48 (AMD tables only). */
1029	FNIEMOP_STUB(iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx);
1030	/** Opcode VEX.66.0F3A 0x49 (AMD tables only). */
1031	FNIEMOP_STUB(iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx);
1032
1033
1034	/**
1035	* Common worker for AVX2 instructions on the forms:
1036	* - vblendvps/d xmm0, xmm1, xmm2/mem128, xmm4
1037	* - vblendvps/d ymm0, ymm1, ymm2/mem256, ymm4
1038	*
1039	* Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operations.
1040	* Additionally, it triggers \#UD if VEX.W is 1.
1041	*/
1042	FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
1043	{
1044	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1045	uint8_t const fOp4Mask = IEM_IS_64BIT_CODE(pVCpu) ? 15 : 7;
1046	if (IEM_IS_MODRM_REG_MODE(bRm))
1047	{
1048	/*
1049	* Register, register.
1050	*/
1051	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1052	if (pVCpu->iem.s.uVexLength)
1053	{
1054	IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
1055	IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1056	IEM_MC_LOCAL(RTUINT256U, uDst);
1057	IEM_MC_LOCAL(RTUINT256U, uSrc1);
1058	IEM_MC_LOCAL(RTUINT256U, uSrc2);
1059	IEM_MC_LOCAL(RTUINT256U, uSrc3);
1060	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1061	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1062	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1063	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1064	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1065	IEM_MC_PREPARE_AVX_USAGE();
1066	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1067	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1068	IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1069	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1070	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1071	IEM_MC_ADVANCE_RIP_AND_FINISH();
1072	IEM_MC_END();
1073	}
1074	else
1075	{
1076	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1077	IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1078	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1079	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1080	IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
1081	IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1082	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1083	IEM_MC_PREPARE_AVX_USAGE();
1084	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1085	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1086	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1087	IEM_MC_REF_XREG_U128_CONST(puSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1088	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1089	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1090	IEM_MC_ADVANCE_RIP_AND_FINISH();
1091	IEM_MC_END();
1092	}
1093	}
1094	else
1095	{
1096	/*
1097	* Register, memory.
1098	*/
1099	if (pVCpu->iem.s.uVexLength)
1100	{
1101	IEM_MC_BEGIN(4, 5, IEM_MC_F_NOT_286_OR_OLDER, 0);
1102	IEM_MC_LOCAL(RTUINT256U, uDst);
1103	IEM_MC_LOCAL(RTUINT256U, uSrc1);
1104	IEM_MC_LOCAL(RTUINT256U, uSrc2);
1105	IEM_MC_LOCAL(RTUINT256U, uSrc3);
1106	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1107	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1108	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1109	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1110	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1111
1112	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1113	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1114
1115	IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1116	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1117	IEM_MC_PREPARE_AVX_USAGE();
1118
1119	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1120	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1121	IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1122	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1123	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1124
1125	IEM_MC_ADVANCE_RIP_AND_FINISH();
1126	IEM_MC_END();
1127	}
1128	else
1129	{
1130	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1131	IEM_MC_LOCAL(RTUINT128U, uSrc2);
1132	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1133	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1134	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1135	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
1136	IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1137
1138	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1139	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1140
1141	IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1142	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1143	IEM_MC_PREPARE_AVX_USAGE();
1144
1145	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1146	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1147	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1148	IEM_MC_REF_XREG_U128_CONST(puSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1149	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1150	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1151
1152	IEM_MC_ADVANCE_RIP_AND_FINISH();
1153	IEM_MC_END();
1154	}
1155	}
1156	}
1157
1158
1159	/** Opcode VEX.66.0F3A 0x4a (vex only).
1160	* AVX, AVX */
1161	FNIEMOP_DEF(iemOp_vblendvps_Vx_Hx_Wx_Lx)
1162	{
1163	IEMOP_MNEMONIC4(VEX_RVMR, VBLENDVPS, vblendvps, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0);
1164	IEMOPBLENDOP_INIT_VARS(vblendvps);
1165	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
1166	}
1167
1168
1169	/** Opcode VEX.66.0F3A 0x4b (vex only).
1170	* AVX, AVX */
1171	FNIEMOP_DEF(iemOp_vblendvpd_Vx_Hx_Wx_Lx)
1172	{
1173	IEMOP_MNEMONIC4(VEX_RVMR, VBLENDVPD, vblendvpd, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0);
1174	IEMOPBLENDOP_INIT_VARS(vblendvpd);
1175	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
1176	}
1177
1178
1179	/**
1180	* Common worker for AVX2 instructions on the forms:
1181	* - vpxxx xmm0, xmm1, xmm2/mem128, xmm4
1182	* - vpxxx ymm0, ymm1, ymm2/mem256, ymm4
1183	*
1184	* Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
1185	*/
1186	FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
1187	{
1188	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1189	if (IEM_IS_MODRM_REG_MODE(bRm))
1190	{
1191	/*
1192	* Register, register.
1193	*/
1194	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1195	if (pVCpu->iem.s.uVexLength)
1196	{
1197	IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
1198	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
1199	IEM_MC_LOCAL(RTUINT256U, uDst);
1200	IEM_MC_LOCAL(RTUINT256U, uSrc1);
1201	IEM_MC_LOCAL(RTUINT256U, uSrc2);
1202	IEM_MC_LOCAL(RTUINT256U, uSrc3);
1203	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1204	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1205	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1206	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1207	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1208	IEM_MC_PREPARE_AVX_USAGE();
1209	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1210	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1211	IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
1212	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1213	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1214	IEM_MC_ADVANCE_RIP_AND_FINISH();
1215	IEM_MC_END();
1216	}
1217	else
1218	{
1219	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1220	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
1221	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1222	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1223	IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
1224	IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1225	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1226	IEM_MC_PREPARE_AVX_USAGE();
1227	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1228	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1229	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1230	IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
1231	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1232	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1233	IEM_MC_ADVANCE_RIP_AND_FINISH();
1234	IEM_MC_END();
1235	}
1236	}
1237	else
1238	{
1239	/*
1240	* Register, memory.
1241	*/
1242	if (pVCpu->iem.s.uVexLength)
1243	{
1244	IEM_MC_BEGIN(4, 5, IEM_MC_F_NOT_286_OR_OLDER, 0);
1245	IEM_MC_LOCAL(RTUINT256U, uDst);
1246	IEM_MC_LOCAL(RTUINT256U, uSrc1);
1247	IEM_MC_LOCAL(RTUINT256U, uSrc2);
1248	IEM_MC_LOCAL(RTUINT256U, uSrc3);
1249	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1250	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1251	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1252	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1253	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1254
1255	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1256	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1257
1258	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
1259	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1260	IEM_MC_PREPARE_AVX_USAGE();
1261
1262	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1263	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1264	IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1265	IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
1266	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1267	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1268
1269	IEM_MC_ADVANCE_RIP_AND_FINISH();
1270	IEM_MC_END();
1271	}
1272	else
1273	{
1274	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1275	IEM_MC_LOCAL(RTUINT128U, uSrc2);
1276	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1277	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1278	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1279	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
1280	IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1281
1282	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1283	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1284
1285	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
1286	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1287	IEM_MC_PREPARE_AVX_USAGE();
1288
1289	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1290	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1291	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1292	IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
1293	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1294	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1295
1296	IEM_MC_ADVANCE_RIP_AND_FINISH();
1297	IEM_MC_END();
1298	}
1299	}
1300	}
1301
1302
1303	/** Opcode VEX.66.0F3A 0x4c (vex only).
1304	* AVX, AVX2 */
1305	FNIEMOP_DEF(iemOp_vpblendvb_Vx_Hx_Wx_Lx)
1306	{
1307	//IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVB, vpblendvb, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
1308	IEMOPBLENDOP_INIT_VARS(vpblendvb);
1309	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1310	}
1311
1312
1313	/* Opcode VEX.66.0F3A 0x4d - invalid */
1314	/* Opcode VEX.66.0F3A 0x4e - invalid */
1315	/* Opcode VEX.66.0F3A 0x4f - invalid */
1316
1317
1318	/* Opcode VEX.66.0F3A 0x50 - invalid */
1319	/* Opcode VEX.66.0F3A 0x51 - invalid */
1320	/* Opcode VEX.66.0F3A 0x52 - invalid */
1321	/* Opcode VEX.66.0F3A 0x53 - invalid */
1322	/* Opcode VEX.66.0F3A 0x54 - invalid */
1323	/* Opcode VEX.66.0F3A 0x55 - invalid */
1324	/* Opcode VEX.66.0F3A 0x56 - invalid */
1325	/* Opcode VEX.66.0F3A 0x57 - invalid */
1326	/* Opcode VEX.66.0F3A 0x58 - invalid */
1327	/* Opcode VEX.66.0F3A 0x59 - invalid */
1328	/* Opcode VEX.66.0F3A 0x5a - invalid */
1329	/* Opcode VEX.66.0F3A 0x5b - invalid */
1330	/** Opcode VEX.66.0F3A 0x5c (AMD tables only). */
1331	FNIEMOP_STUB(iemOp_vfmaddsubps_Vx_Lx_Wx_Hx);
1332	/** Opcode VEX.66.0F3A 0x5d (AMD tables only). */
1333	FNIEMOP_STUB(iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx);
1334	/** Opcode VEX.66.0F3A 0x5e (AMD tables only). */
1335	FNIEMOP_STUB(iemOp_vfmsubaddps_Vx_Lx_Wx_Hx);
1336	/** Opcode VEX.66.0F3A 0x5f (AMD tables only). */
1337	FNIEMOP_STUB(iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx);
1338
1339
1340	/** Opcode VEX.66.0F3A 0x60. */
1341	FNIEMOP_STUB(iemOp_vpcmpestrm_Vdq_Wdq_Ib);
1342	/** Opcode VEX.66.0F3A 0x61, */
1343	FNIEMOP_STUB(iemOp_vpcmpestri_Vdq_Wdq_Ib);
1344	/** Opcode VEX.66.0F3A 0x62. */
1345	FNIEMOP_STUB(iemOp_vpcmpistrm_Vdq_Wdq_Ib);
1346	/** Opcode VEX.66.0F3A 0x63*/
1347	FNIEMOP_STUB(iemOp_vpcmpistri_Vdq_Wdq_Ib);
1348	/* Opcode VEX.66.0F3A 0x64 - invalid */
1349	/* Opcode VEX.66.0F3A 0x65 - invalid */
1350	/* Opcode VEX.66.0F3A 0x66 - invalid */
1351	/* Opcode VEX.66.0F3A 0x67 - invalid */
1352	/** Opcode VEX.66.0F3A 0x68 (AMD tables only). */
1353	FNIEMOP_STUB(iemOp_vfmaddps_Vx_Lx_Wx_Hx);
1354	/** Opcode VEX.66.0F3A 0x69 (AMD tables only). */
1355	FNIEMOP_STUB(iemOp_vfmaddpd_Vx_Lx_Wx_Hx);
1356	/** Opcode VEX.66.0F3A 0x6a (AMD tables only). */
1357	FNIEMOP_STUB(iemOp_vfmaddss_Vx_Lx_Wx_Hx);
1358	/** Opcode VEX.66.0F3A 0x6b (AMD tables only). */
1359	FNIEMOP_STUB(iemOp_vfmaddsd_Vx_Lx_Wx_Hx);
1360	/** Opcode VEX.66.0F3A 0x6c (AMD tables only). */
1361	FNIEMOP_STUB(iemOp_vfmsubps_Vx_Lx_Wx_Hx);
1362	/** Opcode VEX.66.0F3A 0x6d (AMD tables only). */
1363	FNIEMOP_STUB(iemOp_vfmsubpd_Vx_Lx_Wx_Hx);
1364	/** Opcode VEX.66.0F3A 0x6e (AMD tables only). */
1365	FNIEMOP_STUB(iemOp_vfmsubss_Vx_Lx_Wx_Hx);
1366	/** Opcode VEX.66.0F3A 0x6f (AMD tables only). */
1367	FNIEMOP_STUB(iemOp_vfmsubsd_Vx_Lx_Wx_Hx);
1368
1369	/* Opcode VEX.66.0F3A 0x70 - invalid */
1370	/* Opcode VEX.66.0F3A 0x71 - invalid */
1371	/* Opcode VEX.66.0F3A 0x72 - invalid */
1372	/* Opcode VEX.66.0F3A 0x73 - invalid */
1373	/* Opcode VEX.66.0F3A 0x74 - invalid */
1374	/* Opcode VEX.66.0F3A 0x75 - invalid */
1375	/* Opcode VEX.66.0F3A 0x76 - invalid */
1376	/* Opcode VEX.66.0F3A 0x77 - invalid */
1377	/** Opcode VEX.66.0F3A 0x78 (AMD tables only). */
1378	FNIEMOP_STUB(iemOp_vfnmaddps_Vx_Lx_Wx_Hx);
1379	/** Opcode VEX.66.0F3A 0x79 (AMD tables only). */
1380	FNIEMOP_STUB(iemOp_vfnmaddpd_Vx_Lx_Wx_Hx);
1381	/** Opcode VEX.66.0F3A 0x7a (AMD tables only). */
1382	FNIEMOP_STUB(iemOp_vfnmaddss_Vx_Lx_Wx_Hx);
1383	/** Opcode VEX.66.0F3A 0x7b (AMD tables only). */
1384	FNIEMOP_STUB(iemOp_vfnmaddsd_Vx_Lx_Wx_Hx);
1385	/** Opcode VEX.66.0F3A 0x7c (AMD tables only). */
1386	FNIEMOP_STUB(iemOp_vfnmsubps_Vx_Lx_Wx_Hx);
1387	/** Opcode VEX.66.0F3A 0x7d (AMD tables only). */
1388	FNIEMOP_STUB(iemOp_vfnmsubpd_Vx_Lx_Wx_Hx);
1389	/** Opcode VEX.66.0F3A 0x7e (AMD tables only). */
1390	FNIEMOP_STUB(iemOp_vfnmsubss_Vx_Lx_Wx_Hx);
1391	/** Opcode VEX.66.0F3A 0x7f (AMD tables only). */
1392	FNIEMOP_STUB(iemOp_vfnmsubsd_Vx_Lx_Wx_Hx);
1393
1394	/* Opcodes 0x0f 0x80 thru 0x0f 0xb0 are unused. */
1395
1396
1397	/* Opcode 0x0f 0xc0 - invalid */
1398	/* Opcode 0x0f 0xc1 - invalid */
1399	/* Opcode 0x0f 0xc2 - invalid */
1400	/* Opcode 0x0f 0xc3 - invalid */
1401	/* Opcode 0x0f 0xc4 - invalid */
1402	/* Opcode 0x0f 0xc5 - invalid */
1403	/* Opcode 0x0f 0xc6 - invalid */
1404	/* Opcode 0x0f 0xc7 - invalid */
1405	/* Opcode 0x0f 0xc8 - invalid */
1406	/* Opcode 0x0f 0xc9 - invalid */
1407	/* Opcode 0x0f 0xca - invalid */
1408	/* Opcode 0x0f 0xcb - invalid */
1409	/* Opcode 0x0f 0xcc - invalid */
1410	/* Opcode 0x0f 0xcd - invalid */
1411	/* Opcode 0x0f 0xce - invalid */
1412	/* Opcode 0x0f 0xcf - invalid */
1413
1414
1415	/* Opcode VEX.66.0F3A 0xd0 - invalid */
1416	/* Opcode VEX.66.0F3A 0xd1 - invalid */
1417	/* Opcode VEX.66.0F3A 0xd2 - invalid */
1418	/* Opcode VEX.66.0F3A 0xd3 - invalid */
1419	/* Opcode VEX.66.0F3A 0xd4 - invalid */
1420	/* Opcode VEX.66.0F3A 0xd5 - invalid */
1421	/* Opcode VEX.66.0F3A 0xd6 - invalid */
1422	/* Opcode VEX.66.0F3A 0xd7 - invalid */
1423	/* Opcode VEX.66.0F3A 0xd8 - invalid */
1424	/* Opcode VEX.66.0F3A 0xd9 - invalid */
1425	/* Opcode VEX.66.0F3A 0xda - invalid */
1426	/* Opcode VEX.66.0F3A 0xdb - invalid */
1427	/* Opcode VEX.66.0F3A 0xdc - invalid */
1428	/* Opcode VEX.66.0F3A 0xdd - invalid */
1429	/* Opcode VEX.66.0F3A 0xde - invalid */
1430	/* Opcode VEX.66.0F3A 0xdf - (aeskeygenassist). */
1431	FNIEMOP_STUB(iemOp_vaeskeygen_Vdq_Wdq_Ib);
1432
1433
1434	/**
1435	* @opcode 0xf0
1436	* @oppfx 0xf2
1437	* @opflclass unchanged
1438	*/
1439	FNIEMOP_DEF(iemOp_rorx_Gy_Ey_Ib)
1440	{
1441	IEMOP_MNEMONIC3(VEX_RMI, RORX, rorx, Gy, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO \| IEMOPHINT_VEX_V_ZERO);
1442	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1443	if (IEM_IS_MODRM_REG_MODE(bRm))
1444	{
1445	/*
1446	* Register, register.
1447	*/
1448	uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1449	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1450	{
1451	IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
1452	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1453	IEM_MC_ARG(uint64_t *, pDst, 0);
1454	IEM_MC_ARG(uint64_t, uSrc1, 1);
1455	IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
1456	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
1457	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1458	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
1459	IEM_MC_ADVANCE_RIP_AND_FINISH();
1460	IEM_MC_END();
1461	}
1462	else
1463	{
1464	IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1465	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1466	IEM_MC_ARG(uint32_t *, pDst, 0);
1467	IEM_MC_ARG(uint32_t, uSrc1, 1);
1468	IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
1469	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
1470	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1471	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
1472	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1473	IEM_MC_ADVANCE_RIP_AND_FINISH();
1474	IEM_MC_END();
1475	}
1476	}
1477	else
1478	{
1479	/*
1480	* Register, memory.
1481	*/
1482	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1483	{
1484	IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0);
1485	IEM_MC_ARG(uint64_t *, pDst, 0);
1486	IEM_MC_ARG(uint64_t, uSrc1, 1);
1487	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1488	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1489	uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1490	IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
1491	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1492	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1493	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1494	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
1495	IEM_MC_ADVANCE_RIP_AND_FINISH();
1496	IEM_MC_END();
1497	}
1498	else
1499	{
1500	IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1501	IEM_MC_ARG(uint32_t *, pDst, 0);
1502	IEM_MC_ARG(uint32_t, uSrc1, 1);
1503	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1504	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1505	uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1506	IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
1507	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1508	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1509	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1510	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
1511	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1512	IEM_MC_ADVANCE_RIP_AND_FINISH();
1513	IEM_MC_END();
1514	}
1515	}
1516	}
1517
1518
1519	/**
1520	* VEX opcode map \#3.
1521	*
1522	* @sa g_apfnThreeByte0f3a
1523	*/
1524	const PFNIEMOP g_apfnVexMap3[] =
1525	{
1526	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1527	/* 0x00 */ iemOp_InvalidNeedRMImm8, iemOp_vpermq_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1528	/* 0x01 */ iemOp_InvalidNeedRMImm8, iemOp_vpermqd_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1529	/* 0x02 */ iemOp_InvalidNeedRMImm8, iemOp_vpblendd_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1530	/* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1531	/* 0x04 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1532	/* 0x05 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1533	/* 0x06 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1534	/* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1535	/* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_vroundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1536	/* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_vroundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1537	/* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_vroundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1538	/* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_vroundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1539	/* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_vblendps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1540	/* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_vblendpd_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1541	/* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_vpblendw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1542	/* 0x0f */ iemOp_InvalidNeedRMImm8, iemOp_vpalignr_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1543
1544	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1545	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1546	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1547	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1548	/* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrb_Eb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1549	/* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrw_Ew_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1550	/* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrd_q_Ey_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1551	/* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_vextractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1552	/* 0x18 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1553	/* 0x19 */ iemOp_InvalidNeedRMImm8, iemOp_vextractf128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1554	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1555	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1556	/* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1557	/* 0x1d */ iemOp_InvalidNeedRMImm8, iemOp_vcvtps2ph_Wx_Vx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1558	/* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1559	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1560
1561	/* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1562	/* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1563	/* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1564	/* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1565	/* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1566	/* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1567	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1568	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1569	/* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1570	/* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1571	/* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1572	/* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1573	/* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1574	/* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1575	/* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1576	/* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1577
1578	/* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1579	/* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1580	/* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1581	/* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1582	/* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1583	/* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1584	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1585	/* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1586	/* 0x38 */ iemOp_InvalidNeedRMImm8, iemOp_vinserti128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1587	/* 0x39 */ iemOp_InvalidNeedRMImm8, iemOp_vextracti128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1588	/* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1589	/* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1590	/* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1591	/* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1592	/* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1593	/* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1594
1595	/* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_vdpps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1596	/* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_vdppd_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1597	/* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_vmpsadbw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1598	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1599	/* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1600	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1601	/* 0x46 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1602	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1603	/* 0x48 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1604	/* 0x49 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1605	/* 0x4a */ iemOp_InvalidNeedRMImm8, iemOp_vblendvps_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1606	/* 0x4b */ iemOp_InvalidNeedRMImm8, iemOp_vblendvpd_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1607	/* 0x4c */ iemOp_InvalidNeedRMImm8, iemOp_vpblendvb_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1608	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1609	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1610	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1611
1612	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1613	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1614	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1615	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1616	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1617	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1618	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1619	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1620	/* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1621	/* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1622	/* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1623	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1624	/* 0x5c */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1625	/* 0x5d */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1626	/* 0x5e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1627	/* 0x5f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1628
1629	/* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1630	/* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1631	/* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1632	/* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1633	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1634	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1635	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1636	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1637	/* 0x68 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1638	/* 0x69 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1639	/* 0x6a */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1640	/* 0x6b */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1641	/* 0x6c */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1642	/* 0x6d */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1643	/* 0x6e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1644	/* 0x6f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1645
1646	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1647	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1648	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1649	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1650	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1651	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1652	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1653	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1654	/* 0x78 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1655	/* 0x79 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1656	/* 0x7a */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1657	/* 0x7b */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1658	/* 0x7c */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1659	/* 0x7d */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1660	/* 0x7e */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1661	/* 0x7f */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1662
1663	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1664	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1665	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1666	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1667	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1668	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1669	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1670	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1671	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1672	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1673	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1674	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1675	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1676	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1677	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1678	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1679
1680	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1681	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1682	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1683	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1684	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1685	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1686	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1687	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1688	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1689	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1690	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1691	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1692	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1693	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1694	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1695	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1696
1697	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1698	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1699	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1700	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1701	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1702	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1703	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1704	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1705	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1706	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1707	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1708	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1709	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1710	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1711	/* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1712	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1713
1714	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1715	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1716	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1717	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1718	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1719	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1720	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1721	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1722	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1723	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1724	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1725	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1726	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1727	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1728	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1729	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1730
1731	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1732	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1733	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1734	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1735	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1736	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1737	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1738	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1739	/* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1740	/* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1741	/* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1742	/* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1743	/* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1744	/* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1745	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1746	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1747
1748	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1749	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1750	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1751	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1752	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1753	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1754	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1755	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1756	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1757	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1758	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1759	/* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1760	/* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1761	/* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1762	/* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1763	/* 0xdf */ iemOp_vaeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1764
1765	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1766	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1767	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1768	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1769	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1770	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1771	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1772	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1773	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1774	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1775	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1776	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1777	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1778	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1779	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1780	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1781
1782	/* 0xf0 */ iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_rorx_Gy_Ey_Ib,
1783	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1784	/* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1785	/* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1786	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1787	/* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1788	/* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1789	/* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1790	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1791	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1792	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1793	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1794	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1795	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1796	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1797	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1798	};
1799	AssertCompile(RT_ELEMENTS(g_apfnVexMap3) == 1024);
1800
1801	/** @} */
1802

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap3.cpp.h@ 103922

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