IEMAllInstVexMap3.cpp.h@ 103878

Last change on this file since 103878 was 103878, checked in by vboxsync, 9 months ago
VMM/IEM: Implement vpextrw AVX r/m (0f3a) variant instruction decode, bugref:9898
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1	/* $Id: IEMAllInstVexMap3.cpp.h 103878 2024-03-16 12:25:03Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4	*
5	* @remarks IEMAllInstThree0f3a.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
11	*
12	* This file is part of VirtualBox base platform packages, as
13	* available from https://www.virtualbox.org.
14	*
15	* This program is free software; you can redistribute it and/or
16	* modify it under the terms of the GNU General Public License
17	* as published by the Free Software Foundation, in version 3 of the
18	* License.
19	*
20	* This program is distributed in the hope that it will be useful, but
21	* WITHOUT ANY WARRANTY; without even the implied warranty of
22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23	* General Public License for more details.
24	*
25	* You should have received a copy of the GNU General Public License
26	* along with this program; if not, see <https://www.gnu.org/licenses>.
27	*
28	* SPDX-License-Identifier: GPL-3.0-only
29	*/
30
31
32	/** @name VEX Opcode Map 3
33	* @{
34	*/
35
36	/**
37	* Common worker for AVX2 instructions on the forms:
38	* - vpxxx xmm0, xmm1, xmm2/mem128, imm8
39	* - vpxxx ymm0, ymm1, ymm2/mem256, imm8
40	*
41	* Takes function table for function w/o implicit state parameter.
42	*
43	* Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
44	*/
45	FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF3IMM8, pImpl)
46	{
47	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48	if (IEM_IS_MODRM_REG_MODE(bRm))
49	{
50	/*
51	* Register, register.
52	*/
53	if (pVCpu->iem.s.uVexLength)
54	{
55	IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
56	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
57	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
58	IEM_MC_LOCAL(RTUINT256U, uDst);
59	IEM_MC_LOCAL(RTUINT256U, uSrc1);
60	IEM_MC_LOCAL(RTUINT256U, uSrc2);
61	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
62	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
63	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
64	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
65	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
66	IEM_MC_PREPARE_AVX_USAGE();
67	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
68	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
69	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
70	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
71	IEM_MC_ADVANCE_RIP_AND_FINISH();
72	IEM_MC_END();
73	}
74	else
75	{
76	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
77	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
78	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
79	IEM_MC_ARG(PRTUINT128U, puDst, 0);
80	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
81	IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
82	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
83	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
84	IEM_MC_PREPARE_AVX_USAGE();
85	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
86	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
87	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
88	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
89	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
90	IEM_MC_ADVANCE_RIP_AND_FINISH();
91	IEM_MC_END();
92	}
93	}
94	else
95	{
96	/*
97	* Register, memory.
98	*/
99	if (pVCpu->iem.s.uVexLength)
100	{
101	IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
102	IEM_MC_LOCAL(RTUINT256U, uDst);
103	IEM_MC_LOCAL(RTUINT256U, uSrc1);
104	IEM_MC_LOCAL(RTUINT256U, uSrc2);
105	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
106	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
107	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
108	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
109
110	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
111	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
112	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
113	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
114	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
115	IEM_MC_PREPARE_AVX_USAGE();
116
117	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
118	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
119	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
120	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
121
122	IEM_MC_ADVANCE_RIP_AND_FINISH();
123	IEM_MC_END();
124	}
125	else
126	{
127	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
128	IEM_MC_LOCAL(RTUINT128U, uSrc2);
129	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
130	IEM_MC_ARG(PRTUINT128U, puDst, 0);
131	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
132	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
133
134	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
135	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
136	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
137	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
138	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
139	IEM_MC_PREPARE_AVX_USAGE();
140
141	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
142	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
143	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
144	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
145	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
146
147	IEM_MC_ADVANCE_RIP_AND_FINISH();
148	IEM_MC_END();
149	}
150	}
151	}
152
153
154	/**
155	* Common worker for AVX instructions on the forms:
156	* - vpermilps/d xmm0, xmm1/mem128, imm8
157	* - vpermilps/d ymm0, ymm1/mem256, imm8
158	*
159	* Takes function table for function w/o implicit state parameter.
160	*
161	* Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operation.
162	*/
163	FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF2IMM8, pImpl)
164	{
165	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
166	if (IEM_IS_MODRM_REG_MODE(bRm))
167	{
168	/*
169	* Register, register.
170	*/
171	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
172	if (pVCpu->iem.s.uVexLength)
173	{
174	IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
175	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
176	IEM_MC_LOCAL(RTUINT256U, uDst);
177	IEM_MC_LOCAL(RTUINT256U, uSrc);
178	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
179	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
180	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
181	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
182	IEM_MC_PREPARE_AVX_USAGE();
183	IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
184	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc, bImmArg);
185	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
186	IEM_MC_ADVANCE_RIP_AND_FINISH();
187	IEM_MC_END();
188	}
189	else
190	{
191	IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
192	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
193	IEM_MC_ARG(PRTUINT128U, puDst, 0);
194	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
195	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
196	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
197	IEM_MC_PREPARE_AVX_USAGE();
198	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
199	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
200	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc, bImmArg);
201	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
202	IEM_MC_ADVANCE_RIP_AND_FINISH();
203	IEM_MC_END();
204	}
205	}
206	else
207	{
208	/*
209	* Register, memory.
210	*/
211	if (pVCpu->iem.s.uVexLength)
212	{
213	IEM_MC_BEGIN(3, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
214	IEM_MC_LOCAL(RTUINT256U, uDst);
215	IEM_MC_LOCAL(RTUINT256U, uSrc);
216	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
217	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
218	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
219
220	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
221	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
222	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
223	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
224	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
225	IEM_MC_PREPARE_AVX_USAGE();
226
227	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
228	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc, bImmArg);
229	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
230
231	IEM_MC_ADVANCE_RIP_AND_FINISH();
232	IEM_MC_END();
233	}
234	else
235	{
236	IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
237	IEM_MC_LOCAL(RTUINT128U, uSrc);
238	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
239	IEM_MC_ARG(PRTUINT128U, puDst, 0);
240	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
241
242	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
243	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
244	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
245	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
246	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
247	IEM_MC_PREPARE_AVX_USAGE();
248
249	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
250	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
251	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc, bImmArg);
252	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
253
254	IEM_MC_ADVANCE_RIP_AND_FINISH();
255	IEM_MC_END();
256	}
257	}
258	}
259
260
261	/**
262	* Common worker for AVX instructions on the forms:
263	* - vblendps/d xmm0, xmm1, xmm2/mem128, imm8
264	* - vblendps/d ymm0, ymm1, ymm2/mem256, imm8
265	*
266	* Takes function table for function w/o implicit state parameter.
267	*
268	* Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operation.
269	*/
270	FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF3IMM8, pImpl)
271	{
272	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
273	if (IEM_IS_MODRM_REG_MODE(bRm))
274	{
275	/*
276	* Register, register.
277	*/
278	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
279	if (pVCpu->iem.s.uVexLength)
280	{
281	IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
282	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
283	IEM_MC_LOCAL(RTUINT256U, uDst);
284	IEM_MC_LOCAL(RTUINT256U, uSrc1);
285	IEM_MC_LOCAL(RTUINT256U, uSrc2);
286	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
287	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
288	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
289	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
290	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
291	IEM_MC_PREPARE_AVX_USAGE();
292	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
293	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
294	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
295	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
296	IEM_MC_ADVANCE_RIP_AND_FINISH();
297	IEM_MC_END();
298	}
299	else
300	{
301	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
302	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
303	IEM_MC_ARG(PRTUINT128U, puDst, 0);
304	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
305	IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
306	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
307	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
308	IEM_MC_PREPARE_AVX_USAGE();
309	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
310	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
311	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
312	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
313	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
314	IEM_MC_ADVANCE_RIP_AND_FINISH();
315	IEM_MC_END();
316	}
317	}
318	else
319	{
320	/*
321	* Register, memory.
322	*/
323	if (pVCpu->iem.s.uVexLength)
324	{
325	IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
326	IEM_MC_LOCAL(RTUINT256U, uDst);
327	IEM_MC_LOCAL(RTUINT256U, uSrc1);
328	IEM_MC_LOCAL(RTUINT256U, uSrc2);
329	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
330	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
331	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
332	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
333
334	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
335	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
336	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
337	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
338	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
339	IEM_MC_PREPARE_AVX_USAGE();
340
341	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
342	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
343	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
344	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
345
346	IEM_MC_ADVANCE_RIP_AND_FINISH();
347	IEM_MC_END();
348	}
349	else
350	{
351	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
352	IEM_MC_LOCAL(RTUINT128U, uSrc2);
353	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
354	IEM_MC_ARG(PRTUINT128U, puDst, 0);
355	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
356	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
357
358	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
359	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
360	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
361	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
362	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
363	IEM_MC_PREPARE_AVX_USAGE();
364
365	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
366	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
367	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
368	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
369	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
370
371	IEM_MC_ADVANCE_RIP_AND_FINISH();
372	IEM_MC_END();
373	}
374	}
375	}
376
377
378	/** Opcode VEX.66.0F3A 0x00. */
379	FNIEMOP_STUB(iemOp_vpermq_Vqq_Wqq_Ib);
380	/** Opcode VEX.66.0F3A 0x01. */
381	FNIEMOP_STUB(iemOp_vpermqd_Vqq_Wqq_Ib);
382
383
384	/** Opcode VEX.66.0F3A 0x02.
385	* AVX2,AVX2 */
386	FNIEMOP_DEF(iemOp_vpblendd_Vx_Hx_Wx_Ib)
387	{
388	IEMOP_MNEMONIC3(VEX_RVM, VPBLENDD, vpblendd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
389	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpblendd);
390	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
391	}
392
393
394	/* Opcode VEX.66.0F3A 0x03 - invalid */
395
396
397	/** Opcode VEX.66.0F3A 0x04.
398	* AVX,AVX */
399	FNIEMOP_DEF(iemOp_vpermilps_Vx_Wx_Ib)
400	{
401	IEMOP_MNEMONIC3(VEX_RMI, VPERMILPS, vpermilps, Vx, Wx, Ib, DISOPTYPE_HARMLESS, 0); /* @todo */
402	IEMOPMEDIAOPTF2IMM8_INIT_VARS(vpermilps);
403	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
404	}
405
406
407	/** Opcode VEX.66.0F3A 0x05.
408	* AVX,AVX */
409	FNIEMOP_DEF(iemOp_vpermilpd_Vx_Wx_Ib)
410	{
411	IEMOP_MNEMONIC3(VEX_RMI, VPERMILPD, vpermilpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS, 0); /* @todo */
412	IEMOPMEDIAOPTF2IMM8_INIT_VARS(vpermilpd);
413	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
414	}
415
416
417	/** Opcode VEX.66.0F3A 0x06 (vex only) */
418	FNIEMOP_DEF(iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib)
419	{
420	//IEMOP_MNEMONIC4(VEX_RVM, VPERM2F128, vperm2f128, Vqq, Hqq, Wqq, Ib, DISOPTYPE_HARMLESS, 0); /** @todo */
421
422	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
423	if (IEM_IS_MODRM_REG_MODE(bRm))
424	{
425	/*
426	* Register, register.
427	*/
428	IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
429	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
430	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
431	IEM_MC_LOCAL(RTUINT256U, uDst);
432	IEM_MC_LOCAL(RTUINT256U, uSrc1);
433	IEM_MC_LOCAL(RTUINT256U, uSrc2);
434	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
435	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
436	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
437	IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
438	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
439	IEM_MC_PREPARE_AVX_USAGE();
440	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
441	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
442	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback),
443	puDst, puSrc1, puSrc2, bImmArg);
444	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
445	IEM_MC_ADVANCE_RIP_AND_FINISH();
446	IEM_MC_END();
447	}
448	else
449	{
450	/*
451	* Register, memory.
452	*/
453	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
454	IEM_MC_LOCAL(RTUINT256U, uDst);
455	IEM_MC_LOCAL(RTUINT256U, uSrc1);
456	IEM_MC_LOCAL(RTUINT256U, uSrc2);
457	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
458	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
459	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
460	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
461
462	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
463	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
464	IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
465	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
466	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
467	IEM_MC_PREPARE_AVX_USAGE();
468
469	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
470	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
471	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback),
472	puDst, puSrc1, puSrc2, bImmArg);
473	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
474
475	IEM_MC_ADVANCE_RIP_AND_FINISH();
476	IEM_MC_END();
477	}
478	}
479
480
481	/* Opcode VEX.66.0F3A 0x07 - invalid */
482	/** Opcode VEX.66.0F3A 0x08. */
483	FNIEMOP_STUB(iemOp_vroundps_Vx_Wx_Ib);
484	/** Opcode VEX.66.0F3A 0x09. */
485	FNIEMOP_STUB(iemOp_vroundpd_Vx_Wx_Ib);
486	/** Opcode VEX.66.0F3A 0x0a. */
487	FNIEMOP_STUB(iemOp_vroundss_Vss_Wss_Ib);
488	/** Opcode VEX.66.0F3A 0x0b. */
489	FNIEMOP_STUB(iemOp_vroundsd_Vsd_Wsd_Ib);
490
491
492	/** Opcode VEX.66.0F3A 0x0c.
493	* AVX,AVX */
494	FNIEMOP_DEF(iemOp_vblendps_Vx_Hx_Wx_Ib)
495	{
496	IEMOP_MNEMONIC3(VEX_RVM, VBLENDPS, vblendps, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
497	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendps);
498	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
499	}
500
501
502	/** Opcode VEX.66.0F3A 0x0d.
503	* AVX,AVX */
504	FNIEMOP_DEF(iemOp_vblendpd_Vx_Hx_Wx_Ib)
505	{
506	IEMOP_MNEMONIC3(VEX_RVM, VBLENDPD, vblendpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
507	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendpd);
508	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
509	}
510
511
512	/** Opcode VEX.66.0F3A 0x0e.
513	* AVX,AVX2 */
514	FNIEMOP_DEF(iemOp_vpblendw_Vx_Hx_Wx_Ib)
515	{
516	IEMOP_MNEMONIC3(VEX_RVM, VPBLENDW, vpblendw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
517	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpblendw);
518	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
519	}
520
521
522	/** Opcode VEX.0F3A 0x0f - invalid. */
523
524
525	/** Opcode VEX.66.0F3A 0x0f.
526	* AVX,AVX2 */
527	FNIEMOP_DEF(iemOp_vpalignr_Vx_Hx_Wx_Ib)
528	{
529	IEMOP_MNEMONIC3(VEX_RVM, VPALIGNR, vpalignr, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
530	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpalignr);
531	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
532	}
533
534
535	/* Opcode VEX.66.0F3A 0x10 - invalid */
536	/* Opcode VEX.66.0F3A 0x11 - invalid */
537	/* Opcode VEX.66.0F3A 0x12 - invalid */
538	/* Opcode VEX.66.0F3A 0x13 - invalid */
539	/** Opcode VEX.66.0F3A 0x14. */
540	FNIEMOP_STUB(iemOp_vpextrb_RdMb_Vdq_Ib);
541
542
543	/** Opcode VEX.66.0F3A 0x15 - vpextrw RdMw, Vdq, Ib */
544	FNIEMOP_DEF(iemOp_vpextrw_RdMw_Vdq_Ib)
545	{
546	// IEMOP_MNEMONIC3(VEX_RMI, VPEXTRW, vpextrw, RdMw, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO); /* @todo */
547	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
548	if (IEM_IS_MODRM_REG_MODE(bRm))
549	{
550	/*
551	* Register, register.
552	*/
553	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
554	IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
555	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
556	IEM_MC_LOCAL(uint16_t, u16Dst);
557	IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Dst, u16Dst, 0);
558	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
559	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
560	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
561	IEM_MC_PREPARE_AVX_USAGE();
562	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
563	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vpextrw_u128, iemAImpl_vpextrw_u128_fallback),
564	pu16Dst, puSrc, bImmArg);
565	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u16Dst);
566	IEM_MC_ADVANCE_RIP_AND_FINISH();
567	IEM_MC_END();
568	}
569	else
570	{
571	/*
572	* Memory, register.
573	*/
574	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
575	IEM_MC_BEGIN(3, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
576	IEM_MC_LOCAL(uint16_t, u16Dst);
577	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
578	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
579	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
580	IEM_MC_ARG_LOCAL_REF(uint16_t *, pu16Dst, u16Dst, 0);
581	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
582	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
583	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
584	IEM_MC_PREPARE_AVX_USAGE();
585	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_REG(pVCpu, bRm));
586	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vpextrw_u128, iemAImpl_vpextrw_u128_fallback),
587	pu16Dst, puSrc, bImmArg);
588	IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u16Dst);
589	IEM_MC_ADVANCE_RIP_AND_FINISH();
590	IEM_MC_END();
591	}
592	}
593
594
595	/** Opcode VEX.66.0F3A 0x16. */
596	FNIEMOP_STUB(iemOp_vpextrd_q_RdMw_Vdq_Ib);
597	/** Opcode VEX.66.0F3A 0x17. */
598	FNIEMOP_STUB(iemOp_vextractps_Ed_Vdq_Ib);
599
600
601	/** Opcode VEX.66.0F3A 0x18 (vex only). */
602	FNIEMOP_DEF(iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib)
603	{
604	//IEMOP_MNEMONIC4(VEX_RMI, VINSERTF128, vinsertf128, Vx, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
605	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
606	if (IEM_IS_MODRM_REG_MODE(bRm))
607	{
608	/*
609	* Register, register.
610	*/
611	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
612	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
613	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
614	IEM_MC_LOCAL(RTUINT128U, uSrc);
615
616	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
617	IEM_MC_PREPARE_AVX_USAGE();
618
619	IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
620	IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
621	IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
622
623	IEM_MC_ADVANCE_RIP_AND_FINISH();
624	IEM_MC_END();
625	}
626	else
627	{
628	/*
629	* Register, memory.
630	*/
631	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
632	IEM_MC_LOCAL(RTUINT128U, uSrc);
633	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
634
635	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
636	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
637	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
638	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
639	IEM_MC_PREPARE_AVX_USAGE();
640
641	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
642	IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
643	IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
644
645	IEM_MC_ADVANCE_RIP_AND_FINISH();
646	IEM_MC_END();
647	}
648	}
649
650
651	/** Opcode VEX.66.0F3A 0x19 (vex only). */
652	FNIEMOP_STUB(iemOp_vextractf128_Wdq_Vqq_Ib);
653	/* Opcode VEX.66.0F3A 0x1a - invalid */
654	/* Opcode VEX.66.0F3A 0x1b - invalid */
655	/* Opcode VEX.66.0F3A 0x1c - invalid */
656	/** Opcode VEX.66.0F3A 0x1d (vex only). */
657	FNIEMOP_STUB(iemOp_vcvtps2ph_Wx_Vx_Ib);
658	/* Opcode VEX.66.0F3A 0x1e - invalid */
659	/* Opcode VEX.66.0F3A 0x1f - invalid */
660
661
662	/** Opcode VEX.66.0F3A 0x20. */
663	FNIEMOP_STUB(iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib);
664	/** Opcode VEX.66.0F3A 0x21, */
665	FNIEMOP_STUB(iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib);
666	/** Opcode VEX.66.0F3A 0x22. */
667	FNIEMOP_STUB(iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib);
668	/* Opcode VEX.66.0F3A 0x23 - invalid */
669	/* Opcode VEX.66.0F3A 0x24 - invalid */
670	/* Opcode VEX.66.0F3A 0x25 - invalid */
671	/* Opcode VEX.66.0F3A 0x26 - invalid */
672	/* Opcode VEX.66.0F3A 0x27 - invalid */
673	/* Opcode VEX.66.0F3A 0x28 - invalid */
674	/* Opcode VEX.66.0F3A 0x29 - invalid */
675	/* Opcode VEX.66.0F3A 0x2a - invalid */
676	/* Opcode VEX.66.0F3A 0x2b - invalid */
677	/* Opcode VEX.66.0F3A 0x2c - invalid */
678	/* Opcode VEX.66.0F3A 0x2d - invalid */
679	/* Opcode VEX.66.0F3A 0x2e - invalid */
680	/* Opcode VEX.66.0F3A 0x2f - invalid */
681
682
683	/* Opcode VEX.66.0F3A 0x30 - invalid */
684	/* Opcode VEX.66.0F3A 0x31 - invalid */
685	/* Opcode VEX.66.0F3A 0x32 - invalid */
686	/* Opcode VEX.66.0F3A 0x33 - invalid */
687	/* Opcode VEX.66.0F3A 0x34 - invalid */
688	/* Opcode VEX.66.0F3A 0x35 - invalid */
689	/* Opcode VEX.66.0F3A 0x36 - invalid */
690	/* Opcode VEX.66.0F3A 0x37 - invalid */
691
692
693	/** Opcode VEX.66.0F3A 0x38 (vex only). */
694	FNIEMOP_DEF(iemOp_vinserti128_Vqq_Hqq_Wqq_Ib)
695	{
696	//IEMOP_MNEMONIC4(VEX_RMI, VINSERTI128, vinserti128, Vx, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
697	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
698	if (IEM_IS_MODRM_REG_MODE(bRm))
699	{
700	/*
701	* Register, register.
702	*/
703	IEM_MC_BEGIN(0, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
704	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
705	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
706	IEM_MC_LOCAL(RTUINT128U, uSrc);
707
708	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
709	IEM_MC_PREPARE_AVX_USAGE();
710
711	IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
712	IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
713	IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
714
715	IEM_MC_ADVANCE_RIP_AND_FINISH();
716	IEM_MC_END();
717	}
718	else
719	{
720	/*
721	* Register, memory.
722	*/
723	IEM_MC_BEGIN(0, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
724	IEM_MC_LOCAL(RTUINT128U, uSrc);
725	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
726
727	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
728	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
729	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
730	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
731	IEM_MC_PREPARE_AVX_USAGE();
732
733	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
734	IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
735	IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
736
737	IEM_MC_ADVANCE_RIP_AND_FINISH();
738	IEM_MC_END();
739	}
740	}
741
742
743	/** Opcode VEX.66.0F3A 0x39 (vex only). */
744	FNIEMOP_STUB(iemOp_vextracti128_Wdq_Vqq_Ib);
745	/* Opcode VEX.66.0F3A 0x3a - invalid */
746	/* Opcode VEX.66.0F3A 0x3b - invalid */
747	/* Opcode VEX.66.0F3A 0x3c - invalid */
748	/* Opcode VEX.66.0F3A 0x3d - invalid */
749	/* Opcode VEX.66.0F3A 0x3e - invalid */
750	/* Opcode VEX.66.0F3A 0x3f - invalid */
751
752
753	/** Opcode VEX.66.0F3A 0x40. */
754	FNIEMOP_STUB(iemOp_vdpps_Vx_Hx_Wx_Ib);
755	/** Opcode VEX.66.0F3A 0x41, */
756	FNIEMOP_STUB(iemOp_vdppd_Vdq_Hdq_Wdq_Ib);
757
758
759	/** Opcode VEX.66.0F3A 0x42. */
760	FNIEMOP_DEF(iemOp_vmpsadbw_Vx_Hx_Wx_Ib)
761	{
762	IEMOP_MNEMONIC3(VEX_RVM, VMPSADBW, vmpsadbw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /** @todo */
763	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vmpsadbw);
764	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
765	}
766
767
768	/* Opcode VEX.66.0F3A 0x43 - invalid */
769
770
771	/** Opcode VEX.66.0F3A 0x44. */
772	FNIEMOP_DEF(iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib)
773	{
774	//IEMOP_MNEMONIC3(VEX_RVM, VPCLMULQDQ, vpclmulqdq, Vdq, Hdq, Wdq, DISOPTYPE_HARMLESS, 0); /* @todo */
775
776	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
777	if (IEM_IS_MODRM_REG_MODE(bRm))
778	{
779	/*
780	* Register, register.
781	*/
782	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
783	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
784	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
785	IEM_MC_ARG(PRTUINT128U, puDst, 0);
786	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
787	IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
788	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
789	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
790	IEM_MC_PREPARE_AVX_USAGE();
791	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
792	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
793	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
794	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
795	puDst, puSrc1, puSrc2, bImmArg);
796	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
797	IEM_MC_ADVANCE_RIP_AND_FINISH();
798	IEM_MC_END();
799	}
800	else
801	{
802	/*
803	* Register, memory.
804	*/
805	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
806	IEM_MC_LOCAL(RTUINT128U, uSrc2);
807	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
808	IEM_MC_ARG(PRTUINT128U, puDst, 0);
809	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
810	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
811
812	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
813	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
814	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
815	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
816	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
817	IEM_MC_PREPARE_AVX_USAGE();
818
819	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
820	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
821	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
822	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
823	puDst, puSrc1, puSrc2, bImmArg);
824	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
825
826	IEM_MC_ADVANCE_RIP_AND_FINISH();
827	IEM_MC_END();
828	}
829	}
830
831
832	/* Opcode VEX.66.0F3A 0x45 - invalid */
833
834
835	/** Opcode VEX.66.0F3A 0x46 (vex only) */
836	FNIEMOP_DEF(iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib)
837	{
838	//IEMOP_MNEMONIC4(VEX_RVM, VPERM2I128, vperm2i128, Vqq, Hqq, Wqq, Ib, DISOPTYPE_HARMLESS, 0); /** @todo */
839
840	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
841	if (IEM_IS_MODRM_REG_MODE(bRm))
842	{
843	/*
844	* Register, register.
845	*/
846	IEM_MC_BEGIN(4, 3, IEM_MC_F_NOT_286_OR_OLDER, 0);
847	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
848	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
849	IEM_MC_LOCAL(RTUINT256U, uDst);
850	IEM_MC_LOCAL(RTUINT256U, uSrc1);
851	IEM_MC_LOCAL(RTUINT256U, uSrc2);
852	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
853	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
854	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
855	IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
856	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
857	IEM_MC_PREPARE_AVX_USAGE();
858	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
859	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
860	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback),
861	puDst, puSrc1, puSrc2, bImmArg);
862	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
863	IEM_MC_ADVANCE_RIP_AND_FINISH();
864	IEM_MC_END();
865	}
866	else
867	{
868	/*
869	* Register, memory.
870	*/
871	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
872	IEM_MC_LOCAL(RTUINT256U, uDst);
873	IEM_MC_LOCAL(RTUINT256U, uSrc1);
874	IEM_MC_LOCAL(RTUINT256U, uSrc2);
875	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
876	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
877	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
878	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
879
880	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
881	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
882	IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
883	IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
884	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
885	IEM_MC_PREPARE_AVX_USAGE();
886
887	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
888	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
889	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback),
890	puDst, puSrc1, puSrc2, bImmArg);
891	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
892
893	IEM_MC_ADVANCE_RIP_AND_FINISH();
894	IEM_MC_END();
895	}
896	}
897
898
899	/* Opcode VEX.66.0F3A 0x47 - invalid */
900	/** Opcode VEX.66.0F3A 0x48 (AMD tables only). */
901	FNIEMOP_STUB(iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx);
902	/** Opcode VEX.66.0F3A 0x49 (AMD tables only). */
903	FNIEMOP_STUB(iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx);
904
905
906	/**
907	* Common worker for AVX2 instructions on the forms:
908	* - vblendvps/d xmm0, xmm1, xmm2/mem128, xmm4
909	* - vblendvps/d ymm0, ymm1, ymm2/mem256, ymm4
910	*
911	* Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operations.
912	*/
913	FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
914	{
915	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
916	if (IEM_IS_MODRM_REG_MODE(bRm))
917	{
918	/*
919	* Register, register.
920	*/
921	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
922	if (pVCpu->iem.s.uVexLength)
923	{
924	IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
925	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
926	IEM_MC_LOCAL(RTUINT256U, uDst);
927	IEM_MC_LOCAL(RTUINT256U, uSrc1);
928	IEM_MC_LOCAL(RTUINT256U, uSrc2);
929	IEM_MC_LOCAL(RTUINT256U, uSrc3);
930	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
931	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
932	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
933	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
934	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
935	IEM_MC_PREPARE_AVX_USAGE();
936	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
937	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
938	IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
939	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
940	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
941	IEM_MC_ADVANCE_RIP_AND_FINISH();
942	IEM_MC_END();
943	}
944	else
945	{
946	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
947	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
948	IEM_MC_ARG(PRTUINT128U, puDst, 0);
949	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
950	IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
951	IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
952	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
953	IEM_MC_PREPARE_AVX_USAGE();
954	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
955	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
956	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
957	IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
958	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
959	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
960	IEM_MC_ADVANCE_RIP_AND_FINISH();
961	IEM_MC_END();
962	}
963	}
964	else
965	{
966	/*
967	* Register, memory.
968	*/
969	if (pVCpu->iem.s.uVexLength)
970	{
971	IEM_MC_BEGIN(4, 5, IEM_MC_F_NOT_286_OR_OLDER, 0);
972	IEM_MC_LOCAL(RTUINT256U, uDst);
973	IEM_MC_LOCAL(RTUINT256U, uSrc1);
974	IEM_MC_LOCAL(RTUINT256U, uSrc2);
975	IEM_MC_LOCAL(RTUINT256U, uSrc3);
976	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
977	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
978	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
979	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
980	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
981
982	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
983	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
984
985	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
986	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
987	IEM_MC_PREPARE_AVX_USAGE();
988
989	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
990	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
991	IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_EFFECTIVE_VVVV(pVCpu));
992	IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
993	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
994	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
995
996	IEM_MC_ADVANCE_RIP_AND_FINISH();
997	IEM_MC_END();
998	}
999	else
1000	{
1001	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1002	IEM_MC_LOCAL(RTUINT128U, uSrc2);
1003	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1004	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1005	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1006	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
1007	IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1008
1009	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1010	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1011
1012	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
1013	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1014	IEM_MC_PREPARE_AVX_USAGE();
1015
1016	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1017	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1018	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1019	IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
1020	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1021	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1022
1023	IEM_MC_ADVANCE_RIP_AND_FINISH();
1024	IEM_MC_END();
1025	}
1026	}
1027	}
1028
1029
1030	/** Opcode VEX.66.0F3A 0x4a (vex only).
1031	* AVX, AVX */
1032	FNIEMOP_DEF(iemOp_vblendvps_Vx_Hx_Wx_Lx)
1033	{
1034	//IEMOP_MNEMONIC4(VEX_RVM, VBLENDVPS, vpblendvps, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
1035	IEMOPBLENDOP_INIT_VARS(vblendvps);
1036	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1037	}
1038
1039
1040	/** Opcode VEX.66.0F3A 0x4b (vex only).
1041	* AVX, AVX */
1042	FNIEMOP_DEF(iemOp_vblendvpd_Vx_Hx_Wx_Lx)
1043	{
1044	//IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVPD, blendvpd, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
1045	IEMOPBLENDOP_INIT_VARS(vblendvpd);
1046	return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1047	}
1048
1049
1050	/**
1051	* Common worker for AVX2 instructions on the forms:
1052	* - vpxxx xmm0, xmm1, xmm2/mem128, xmm4
1053	* - vpxxx ymm0, ymm1, ymm2/mem256, ymm4
1054	*
1055	* Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
1056	*/
1057	FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
1058	{
1059	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1060	if (IEM_IS_MODRM_REG_MODE(bRm))
1061	{
1062	/*
1063	* Register, register.
1064	*/
1065	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1066	if (pVCpu->iem.s.uVexLength)
1067	{
1068	IEM_MC_BEGIN(4, 4, IEM_MC_F_NOT_286_OR_OLDER, 0);
1069	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
1070	IEM_MC_LOCAL(RTUINT256U, uDst);
1071	IEM_MC_LOCAL(RTUINT256U, uSrc1);
1072	IEM_MC_LOCAL(RTUINT256U, uSrc2);
1073	IEM_MC_LOCAL(RTUINT256U, uSrc3);
1074	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1075	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1076	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1077	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1078	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1079	IEM_MC_PREPARE_AVX_USAGE();
1080	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1081	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1082	IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
1083	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1084	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1085	IEM_MC_ADVANCE_RIP_AND_FINISH();
1086	IEM_MC_END();
1087	}
1088	else
1089	{
1090	IEM_MC_BEGIN(4, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1091	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
1092	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1093	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1094	IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
1095	IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1096	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1097	IEM_MC_PREPARE_AVX_USAGE();
1098	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1099	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1100	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1101	IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
1102	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1103	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1104	IEM_MC_ADVANCE_RIP_AND_FINISH();
1105	IEM_MC_END();
1106	}
1107	}
1108	else
1109	{
1110	/*
1111	* Register, memory.
1112	*/
1113	if (pVCpu->iem.s.uVexLength)
1114	{
1115	IEM_MC_BEGIN(4, 5, IEM_MC_F_NOT_286_OR_OLDER, 0);
1116	IEM_MC_LOCAL(RTUINT256U, uDst);
1117	IEM_MC_LOCAL(RTUINT256U, uSrc1);
1118	IEM_MC_LOCAL(RTUINT256U, uSrc2);
1119	IEM_MC_LOCAL(RTUINT256U, uSrc3);
1120	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1121	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1122	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1123	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1124	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1125
1126	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1127	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1128
1129	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
1130	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1131	IEM_MC_PREPARE_AVX_USAGE();
1132
1133	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1134	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1135	IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1136	IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
1137	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1138	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1139
1140	IEM_MC_ADVANCE_RIP_AND_FINISH();
1141	IEM_MC_END();
1142	}
1143	else
1144	{
1145	IEM_MC_BEGIN(4, 2, IEM_MC_F_NOT_286_OR_OLDER, 0);
1146	IEM_MC_LOCAL(RTUINT128U, uSrc2);
1147	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1148	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1149	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1150	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
1151	IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1152
1153	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1154	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1155
1156	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
1157	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1158	IEM_MC_PREPARE_AVX_USAGE();
1159
1160	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1161	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1162	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1163	IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
1164	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1165	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1166
1167	IEM_MC_ADVANCE_RIP_AND_FINISH();
1168	IEM_MC_END();
1169	}
1170	}
1171	}
1172
1173
1174	/** Opcode VEX.66.0F3A 0x4c (vex only).
1175	* AVX, AVX2 */
1176	FNIEMOP_DEF(iemOp_vpblendvb_Vx_Hx_Wx_Lx)
1177	{
1178	//IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVB, vpblendvb, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
1179	IEMOPBLENDOP_INIT_VARS(vpblendvb);
1180	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1181	}
1182
1183
1184	/* Opcode VEX.66.0F3A 0x4d - invalid */
1185	/* Opcode VEX.66.0F3A 0x4e - invalid */
1186	/* Opcode VEX.66.0F3A 0x4f - invalid */
1187
1188
1189	/* Opcode VEX.66.0F3A 0x50 - invalid */
1190	/* Opcode VEX.66.0F3A 0x51 - invalid */
1191	/* Opcode VEX.66.0F3A 0x52 - invalid */
1192	/* Opcode VEX.66.0F3A 0x53 - invalid */
1193	/* Opcode VEX.66.0F3A 0x54 - invalid */
1194	/* Opcode VEX.66.0F3A 0x55 - invalid */
1195	/* Opcode VEX.66.0F3A 0x56 - invalid */
1196	/* Opcode VEX.66.0F3A 0x57 - invalid */
1197	/* Opcode VEX.66.0F3A 0x58 - invalid */
1198	/* Opcode VEX.66.0F3A 0x59 - invalid */
1199	/* Opcode VEX.66.0F3A 0x5a - invalid */
1200	/* Opcode VEX.66.0F3A 0x5b - invalid */
1201	/** Opcode VEX.66.0F3A 0x5c (AMD tables only). */
1202	FNIEMOP_STUB(iemOp_vfmaddsubps_Vx_Lx_Wx_Hx);
1203	/** Opcode VEX.66.0F3A 0x5d (AMD tables only). */
1204	FNIEMOP_STUB(iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx);
1205	/** Opcode VEX.66.0F3A 0x5e (AMD tables only). */
1206	FNIEMOP_STUB(iemOp_vfmsubaddps_Vx_Lx_Wx_Hx);
1207	/** Opcode VEX.66.0F3A 0x5f (AMD tables only). */
1208	FNIEMOP_STUB(iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx);
1209
1210
1211	/** Opcode VEX.66.0F3A 0x60. */
1212	FNIEMOP_STUB(iemOp_vpcmpestrm_Vdq_Wdq_Ib);
1213	/** Opcode VEX.66.0F3A 0x61, */
1214	FNIEMOP_STUB(iemOp_vpcmpestri_Vdq_Wdq_Ib);
1215	/** Opcode VEX.66.0F3A 0x62. */
1216	FNIEMOP_STUB(iemOp_vpcmpistrm_Vdq_Wdq_Ib);
1217	/** Opcode VEX.66.0F3A 0x63*/
1218	FNIEMOP_STUB(iemOp_vpcmpistri_Vdq_Wdq_Ib);
1219	/* Opcode VEX.66.0F3A 0x64 - invalid */
1220	/* Opcode VEX.66.0F3A 0x65 - invalid */
1221	/* Opcode VEX.66.0F3A 0x66 - invalid */
1222	/* Opcode VEX.66.0F3A 0x67 - invalid */
1223	/** Opcode VEX.66.0F3A 0x68 (AMD tables only). */
1224	FNIEMOP_STUB(iemOp_vfmaddps_Vx_Lx_Wx_Hx);
1225	/** Opcode VEX.66.0F3A 0x69 (AMD tables only). */
1226	FNIEMOP_STUB(iemOp_vfmaddpd_Vx_Lx_Wx_Hx);
1227	/** Opcode VEX.66.0F3A 0x6a (AMD tables only). */
1228	FNIEMOP_STUB(iemOp_vfmaddss_Vx_Lx_Wx_Hx);
1229	/** Opcode VEX.66.0F3A 0x6b (AMD tables only). */
1230	FNIEMOP_STUB(iemOp_vfmaddsd_Vx_Lx_Wx_Hx);
1231	/** Opcode VEX.66.0F3A 0x6c (AMD tables only). */
1232	FNIEMOP_STUB(iemOp_vfmsubps_Vx_Lx_Wx_Hx);
1233	/** Opcode VEX.66.0F3A 0x6d (AMD tables only). */
1234	FNIEMOP_STUB(iemOp_vfmsubpd_Vx_Lx_Wx_Hx);
1235	/** Opcode VEX.66.0F3A 0x6e (AMD tables only). */
1236	FNIEMOP_STUB(iemOp_vfmsubss_Vx_Lx_Wx_Hx);
1237	/** Opcode VEX.66.0F3A 0x6f (AMD tables only). */
1238	FNIEMOP_STUB(iemOp_vfmsubsd_Vx_Lx_Wx_Hx);
1239
1240	/* Opcode VEX.66.0F3A 0x70 - invalid */
1241	/* Opcode VEX.66.0F3A 0x71 - invalid */
1242	/* Opcode VEX.66.0F3A 0x72 - invalid */
1243	/* Opcode VEX.66.0F3A 0x73 - invalid */
1244	/* Opcode VEX.66.0F3A 0x74 - invalid */
1245	/* Opcode VEX.66.0F3A 0x75 - invalid */
1246	/* Opcode VEX.66.0F3A 0x76 - invalid */
1247	/* Opcode VEX.66.0F3A 0x77 - invalid */
1248	/** Opcode VEX.66.0F3A 0x78 (AMD tables only). */
1249	FNIEMOP_STUB(iemOp_vfnmaddps_Vx_Lx_Wx_Hx);
1250	/** Opcode VEX.66.0F3A 0x79 (AMD tables only). */
1251	FNIEMOP_STUB(iemOp_vfnmaddpd_Vx_Lx_Wx_Hx);
1252	/** Opcode VEX.66.0F3A 0x7a (AMD tables only). */
1253	FNIEMOP_STUB(iemOp_vfnmaddss_Vx_Lx_Wx_Hx);
1254	/** Opcode VEX.66.0F3A 0x7b (AMD tables only). */
1255	FNIEMOP_STUB(iemOp_vfnmaddsd_Vx_Lx_Wx_Hx);
1256	/** Opcode VEX.66.0F3A 0x7c (AMD tables only). */
1257	FNIEMOP_STUB(iemOp_vfnmsubps_Vx_Lx_Wx_Hx);
1258	/** Opcode VEX.66.0F3A 0x7d (AMD tables only). */
1259	FNIEMOP_STUB(iemOp_vfnmsubpd_Vx_Lx_Wx_Hx);
1260	/** Opcode VEX.66.0F3A 0x7e (AMD tables only). */
1261	FNIEMOP_STUB(iemOp_vfnmsubss_Vx_Lx_Wx_Hx);
1262	/** Opcode VEX.66.0F3A 0x7f (AMD tables only). */
1263	FNIEMOP_STUB(iemOp_vfnmsubsd_Vx_Lx_Wx_Hx);
1264
1265	/* Opcodes 0x0f 0x80 thru 0x0f 0xb0 are unused. */
1266
1267
1268	/* Opcode 0x0f 0xc0 - invalid */
1269	/* Opcode 0x0f 0xc1 - invalid */
1270	/* Opcode 0x0f 0xc2 - invalid */
1271	/* Opcode 0x0f 0xc3 - invalid */
1272	/* Opcode 0x0f 0xc4 - invalid */
1273	/* Opcode 0x0f 0xc5 - invalid */
1274	/* Opcode 0x0f 0xc6 - invalid */
1275	/* Opcode 0x0f 0xc7 - invalid */
1276	/* Opcode 0x0f 0xc8 - invalid */
1277	/* Opcode 0x0f 0xc9 - invalid */
1278	/* Opcode 0x0f 0xca - invalid */
1279	/* Opcode 0x0f 0xcb - invalid */
1280	/* Opcode 0x0f 0xcc - invalid */
1281	/* Opcode 0x0f 0xcd - invalid */
1282	/* Opcode 0x0f 0xce - invalid */
1283	/* Opcode 0x0f 0xcf - invalid */
1284
1285
1286	/* Opcode VEX.66.0F3A 0xd0 - invalid */
1287	/* Opcode VEX.66.0F3A 0xd1 - invalid */
1288	/* Opcode VEX.66.0F3A 0xd2 - invalid */
1289	/* Opcode VEX.66.0F3A 0xd3 - invalid */
1290	/* Opcode VEX.66.0F3A 0xd4 - invalid */
1291	/* Opcode VEX.66.0F3A 0xd5 - invalid */
1292	/* Opcode VEX.66.0F3A 0xd6 - invalid */
1293	/* Opcode VEX.66.0F3A 0xd7 - invalid */
1294	/* Opcode VEX.66.0F3A 0xd8 - invalid */
1295	/* Opcode VEX.66.0F3A 0xd9 - invalid */
1296	/* Opcode VEX.66.0F3A 0xda - invalid */
1297	/* Opcode VEX.66.0F3A 0xdb - invalid */
1298	/* Opcode VEX.66.0F3A 0xdc - invalid */
1299	/* Opcode VEX.66.0F3A 0xdd - invalid */
1300	/* Opcode VEX.66.0F3A 0xde - invalid */
1301	/* Opcode VEX.66.0F3A 0xdf - (aeskeygenassist). */
1302	FNIEMOP_STUB(iemOp_vaeskeygen_Vdq_Wdq_Ib);
1303
1304
1305	/**
1306	* @opcode 0xf0
1307	* @oppfx 0xf2
1308	* @opflclass unchanged
1309	*/
1310	FNIEMOP_DEF(iemOp_rorx_Gy_Ey_Ib)
1311	{
1312	IEMOP_MNEMONIC3(VEX_RMI, RORX, rorx, Gy, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO \| IEMOPHINT_VEX_V_ZERO);
1313	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1314	if (IEM_IS_MODRM_REG_MODE(bRm))
1315	{
1316	/*
1317	* Register, register.
1318	*/
1319	uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1320	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1321	{
1322	IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
1323	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1324	IEM_MC_ARG(uint64_t *, pDst, 0);
1325	IEM_MC_ARG(uint64_t, uSrc1, 1);
1326	IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
1327	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
1328	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1329	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
1330	IEM_MC_ADVANCE_RIP_AND_FINISH();
1331	IEM_MC_END();
1332	}
1333	else
1334	{
1335	IEM_MC_BEGIN(3, 0, IEM_MC_F_NOT_286_OR_OLDER, 0);
1336	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1337	IEM_MC_ARG(uint32_t *, pDst, 0);
1338	IEM_MC_ARG(uint32_t, uSrc1, 1);
1339	IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
1340	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
1341	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1342	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
1343	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1344	IEM_MC_ADVANCE_RIP_AND_FINISH();
1345	IEM_MC_END();
1346	}
1347	}
1348	else
1349	{
1350	/*
1351	* Register, memory.
1352	*/
1353	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1354	{
1355	IEM_MC_BEGIN(3, 1, IEM_MC_F_64BIT, 0);
1356	IEM_MC_ARG(uint64_t *, pDst, 0);
1357	IEM_MC_ARG(uint64_t, uSrc1, 1);
1358	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1359	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1360	uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1361	IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
1362	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1363	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1364	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1365	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
1366	IEM_MC_ADVANCE_RIP_AND_FINISH();
1367	IEM_MC_END();
1368	}
1369	else
1370	{
1371	IEM_MC_BEGIN(3, 1, IEM_MC_F_NOT_286_OR_OLDER, 0);
1372	IEM_MC_ARG(uint32_t *, pDst, 0);
1373	IEM_MC_ARG(uint32_t, uSrc1, 1);
1374	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1375	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1376	uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1377	IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
1378	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1379	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1380	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1381	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
1382	IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1383	IEM_MC_ADVANCE_RIP_AND_FINISH();
1384	IEM_MC_END();
1385	}
1386	}
1387	}
1388
1389
1390	/**
1391	* VEX opcode map \#3.
1392	*
1393	* @sa g_apfnThreeByte0f3a
1394	*/
1395	const PFNIEMOP g_apfnVexMap3[] =
1396	{
1397	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1398	/* 0x00 */ iemOp_InvalidNeedRMImm8, iemOp_vpermq_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1399	/* 0x01 */ iemOp_InvalidNeedRMImm8, iemOp_vpermqd_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1400	/* 0x02 */ iemOp_InvalidNeedRMImm8, iemOp_vpblendd_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1401	/* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1402	/* 0x04 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1403	/* 0x05 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1404	/* 0x06 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1405	/* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1406	/* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_vroundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1407	/* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_vroundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1408	/* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_vroundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1409	/* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_vroundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1410	/* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_vblendps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1411	/* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_vblendpd_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1412	/* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_vpblendw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1413	/* 0x0f */ iemOp_InvalidNeedRMImm8, iemOp_vpalignr_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1414
1415	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1416	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1417	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1418	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1419	/* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1420	/* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1421	/* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1422	/* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_vextractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1423	/* 0x18 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1424	/* 0x19 */ iemOp_InvalidNeedRMImm8, iemOp_vextractf128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1425	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1426	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1427	/* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1428	/* 0x1d */ iemOp_InvalidNeedRMImm8, iemOp_vcvtps2ph_Wx_Vx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1429	/* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1430	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1431
1432	/* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1433	/* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1434	/* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1435	/* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1436	/* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1437	/* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1438	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1439	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1440	/* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1441	/* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1442	/* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1443	/* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1444	/* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1445	/* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1446	/* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1447	/* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1448
1449	/* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1450	/* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1451	/* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1452	/* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1453	/* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1454	/* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1455	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1456	/* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1457	/* 0x38 */ iemOp_InvalidNeedRMImm8, iemOp_vinserti128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1458	/* 0x39 */ iemOp_InvalidNeedRMImm8, iemOp_vextracti128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1459	/* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1460	/* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1461	/* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1462	/* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1463	/* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1464	/* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1465
1466	/* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_vdpps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1467	/* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_vdppd_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1468	/* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_vmpsadbw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1469	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1470	/* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1471	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1472	/* 0x46 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1473	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1474	/* 0x48 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1475	/* 0x49 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1476	/* 0x4a */ iemOp_InvalidNeedRMImm8, iemOp_vblendvps_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1477	/* 0x4b */ iemOp_InvalidNeedRMImm8, iemOp_vblendvpd_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1478	/* 0x4c */ iemOp_InvalidNeedRMImm8, iemOp_vpblendvb_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1479	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1480	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1481	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1482
1483	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1484	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1485	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1486	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1487	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1488	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1489	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1490	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1491	/* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1492	/* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1493	/* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1494	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1495	/* 0x5c */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1496	/* 0x5d */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1497	/* 0x5e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1498	/* 0x5f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1499
1500	/* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1501	/* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1502	/* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1503	/* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1504	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1505	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1506	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1507	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1508	/* 0x68 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1509	/* 0x69 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1510	/* 0x6a */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1511	/* 0x6b */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1512	/* 0x6c */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1513	/* 0x6d */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1514	/* 0x6e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1515	/* 0x6f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1516
1517	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1518	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1519	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1520	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1521	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1522	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1523	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1524	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1525	/* 0x78 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1526	/* 0x79 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1527	/* 0x7a */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1528	/* 0x7b */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1529	/* 0x7c */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1530	/* 0x7d */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1531	/* 0x7e */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1532	/* 0x7f */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1533
1534	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1535	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1536	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1537	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1538	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1539	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1540	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1541	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1542	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1543	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1544	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1545	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1546	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1547	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1548	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1549	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1550
1551	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1552	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1553	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1554	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1555	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1556	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1557	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1558	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1559	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1560	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1561	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1562	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1563	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1564	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1565	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1566	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1567
1568	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1569	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1570	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1571	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1572	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1573	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1574	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1575	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1576	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1577	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1578	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1579	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1580	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1581	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1582	/* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1583	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1584
1585	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1586	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1587	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1588	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1589	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1590	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1591	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1592	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1593	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1594	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1595	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1596	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1597	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1598	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1599	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1600	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1601
1602	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1603	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1604	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1605	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1606	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1607	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1608	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1609	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1610	/* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1611	/* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1612	/* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1613	/* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1614	/* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1615	/* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1616	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1617	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1618
1619	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1620	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1621	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1622	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1623	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1624	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1625	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1626	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1627	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1628	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1629	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1630	/* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1631	/* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1632	/* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1633	/* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1634	/* 0xdf */ iemOp_vaeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1635
1636	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1637	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1638	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1639	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1640	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1641	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1642	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1643	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1644	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1645	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1646	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1647	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1648	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1649	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1650	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1651	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1652
1653	/* 0xf0 */ iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_rorx_Gy_Ey_Ib,
1654	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1655	/* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1656	/* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1657	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1658	/* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1659	/* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1660	/* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1661	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1662	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1663	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1664	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1665	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1666	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1667	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1668	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1669	};
1670	AssertCompile(RT_ELEMENTS(g_apfnVexMap3) == 1024);
1671
1672	/** @} */
1673

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap3.cpp.h@ 103878

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