VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap3.cpp.h@ 104093

Last change on this file since 104093 was 104093, checked in by vboxsync, 8 months ago

VMM/IEM: scm, trailing whitespace fix, bugref:9898
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 86.3 KB
Line 
1/* $Id: IEMAllInstVexMap3.cpp.h 104093 2024-03-27 14:53:32Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4 *
5 * @remarks IEMAllInstThree0f3a.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 3
33 * @{
34 */
35
36/**
37 * Common worker for AVX2 instructions on the forms:
38 * - vpxxx xmm0, xmm1, xmm2/mem128, imm8
39 * - vpxxx ymm0, ymm1, ymm2/mem256, imm8
40 *
41 * Takes function table for function w/o implicit state parameter.
42 *
43 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
44 */
45FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF3IMM8, pImpl)
46{
47 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48 if (IEM_IS_MODRM_REG_MODE(bRm))
49 {
50 /*
51 * Register, register.
52 */
53 if (pVCpu->iem.s.uVexLength)
54 {
55 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
56 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
57 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
58 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
59 IEM_MC_PREPARE_AVX_USAGE();
60
61 IEM_MC_LOCAL(RTUINT256U, uDst);
62 IEM_MC_LOCAL(RTUINT256U, uSrc1);
63 IEM_MC_LOCAL(RTUINT256U, uSrc2);
64 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
65 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
66 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
67 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
68 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
69 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
70 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
71 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
72 IEM_MC_ADVANCE_RIP_AND_FINISH();
73 IEM_MC_END();
74 }
75 else
76 {
77 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
78 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
79 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
80 IEM_MC_ARG(PRTUINT128U, puDst, 0);
81 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
82 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
83 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
84 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
85 IEM_MC_PREPARE_AVX_USAGE();
86 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
87 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
88 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
89 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
90 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
91 IEM_MC_ADVANCE_RIP_AND_FINISH();
92 IEM_MC_END();
93 }
94 }
95 else
96 {
97 /*
98 * Register, memory.
99 */
100 if (pVCpu->iem.s.uVexLength)
101 {
102 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
103 IEM_MC_LOCAL(RTUINT256U, uDst);
104 IEM_MC_LOCAL(RTUINT256U, uSrc1);
105 IEM_MC_LOCAL(RTUINT256U, uSrc2);
106 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
107 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
108 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
109 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
110
111 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
112 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
113 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
114 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
115 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
116 IEM_MC_PREPARE_AVX_USAGE();
117
118 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
119 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
120 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
121 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
122
123 IEM_MC_ADVANCE_RIP_AND_FINISH();
124 IEM_MC_END();
125 }
126 else
127 {
128 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
129 IEM_MC_LOCAL(RTUINT128U, uSrc2);
130 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
131 IEM_MC_ARG(PRTUINT128U, puDst, 0);
132 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
133 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
134
135 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
136 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
137 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
138 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
139 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
140 IEM_MC_PREPARE_AVX_USAGE();
141
142 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
143 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
144 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
145 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
146 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
147
148 IEM_MC_ADVANCE_RIP_AND_FINISH();
149 IEM_MC_END();
150 }
151 }
152}
153
154
155/**
156 * Common worker for AVX instructions on the forms:
157 * - vpermilps/d xmm0, xmm1/mem128, imm8
158 * - vpermilps/d ymm0, ymm1/mem256, imm8
159 *
160 * Takes function table for function w/o implicit state parameter.
161 *
162 * Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operation.
163 */
164FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF2IMM8, pImpl)
165{
166 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
167 if (IEM_IS_MODRM_REG_MODE(bRm))
168 {
169 /*
170 * Register, register.
171 */
172 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
173 if (pVCpu->iem.s.uVexLength)
174 {
175 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
176 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
177 IEM_MC_LOCAL(RTUINT256U, uDst);
178 IEM_MC_LOCAL(RTUINT256U, uSrc);
179 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
180 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
181 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
182 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
183 IEM_MC_PREPARE_AVX_USAGE();
184 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
185 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc, bImmArg);
186 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
187 IEM_MC_ADVANCE_RIP_AND_FINISH();
188 IEM_MC_END();
189 }
190 else
191 {
192 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
193 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
194 IEM_MC_ARG(PRTUINT128U, puDst, 0);
195 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
196 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
197 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
198 IEM_MC_PREPARE_AVX_USAGE();
199 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
200 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
201 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc, bImmArg);
202 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
203 IEM_MC_ADVANCE_RIP_AND_FINISH();
204 IEM_MC_END();
205 }
206 }
207 else
208 {
209 /*
210 * Register, memory.
211 */
212 if (pVCpu->iem.s.uVexLength)
213 {
214 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
215 IEM_MC_LOCAL(RTUINT256U, uDst);
216 IEM_MC_LOCAL(RTUINT256U, uSrc);
217 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
218 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
219 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
220
221 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
222 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
223 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
224 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
225 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
226 IEM_MC_PREPARE_AVX_USAGE();
227
228 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
229 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc, bImmArg);
230 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
231
232 IEM_MC_ADVANCE_RIP_AND_FINISH();
233 IEM_MC_END();
234 }
235 else
236 {
237 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
238 IEM_MC_LOCAL(RTUINT128U, uSrc);
239 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
240 IEM_MC_ARG(PRTUINT128U, puDst, 0);
241 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
242
243 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
244 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
245 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
246 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
247 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
248 IEM_MC_PREPARE_AVX_USAGE();
249
250 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
251 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
252 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc, bImmArg);
253 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
254
255 IEM_MC_ADVANCE_RIP_AND_FINISH();
256 IEM_MC_END();
257 }
258 }
259}
260
261
262/**
263 * Common worker for AVX instructions on the forms:
264 * - vblendps/d xmm0, xmm1, xmm2/mem128, imm8
265 * - vblendps/d ymm0, ymm1, ymm2/mem256, imm8
266 *
267 * Takes function table for function w/o implicit state parameter.
268 *
269 * Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operation.
270 */
271FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF3IMM8, pImpl)
272{
273 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
274 if (IEM_IS_MODRM_REG_MODE(bRm))
275 {
276 /*
277 * Register, register.
278 */
279 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
280 if (pVCpu->iem.s.uVexLength)
281 {
282 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
283 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
284 IEM_MC_LOCAL(RTUINT256U, uDst);
285 IEM_MC_LOCAL(RTUINT256U, uSrc1);
286 IEM_MC_LOCAL(RTUINT256U, uSrc2);
287 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
288 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
289 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
290 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
291 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
292 IEM_MC_PREPARE_AVX_USAGE();
293 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
294 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
295 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
296 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
297 IEM_MC_ADVANCE_RIP_AND_FINISH();
298 IEM_MC_END();
299 }
300 else
301 {
302 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
303 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
304 IEM_MC_ARG(PRTUINT128U, puDst, 0);
305 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
306 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
307 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
308 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
309 IEM_MC_PREPARE_AVX_USAGE();
310 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
311 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
312 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
313 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
314 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
315 IEM_MC_ADVANCE_RIP_AND_FINISH();
316 IEM_MC_END();
317 }
318 }
319 else
320 {
321 /*
322 * Register, memory.
323 */
324 if (pVCpu->iem.s.uVexLength)
325 {
326 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
327 IEM_MC_LOCAL(RTUINT256U, uDst);
328 IEM_MC_LOCAL(RTUINT256U, uSrc1);
329 IEM_MC_LOCAL(RTUINT256U, uSrc2);
330 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
331 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
332 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
333 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
334
335 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
336 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
337 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
338 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
339 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
340 IEM_MC_PREPARE_AVX_USAGE();
341
342 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
343 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
344 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
345 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
346
347 IEM_MC_ADVANCE_RIP_AND_FINISH();
348 IEM_MC_END();
349 }
350 else
351 {
352 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
353 IEM_MC_LOCAL(RTUINT128U, uSrc2);
354 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
355 IEM_MC_ARG(PRTUINT128U, puDst, 0);
356 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
357 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
358
359 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
360 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
361 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
362 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
363 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
364 IEM_MC_PREPARE_AVX_USAGE();
365
366 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
367 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
368 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
369 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
370 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
371
372 IEM_MC_ADVANCE_RIP_AND_FINISH();
373 IEM_MC_END();
374 }
375 }
376}
377
378
379/** Opcode VEX.66.0F3A 0x00. */
380FNIEMOP_STUB(iemOp_vpermq_Vqq_Wqq_Ib);
381/** Opcode VEX.66.0F3A 0x01. */
382FNIEMOP_STUB(iemOp_vpermqd_Vqq_Wqq_Ib);
383
384
385/** Opcode VEX.66.0F3A 0x02.
386 * AVX2,AVX2 */
387FNIEMOP_DEF(iemOp_vpblendd_Vx_Hx_Wx_Ib)
388{
389 IEMOP_MNEMONIC4(VEX_RVMI, VPBLENDD, vpblendd, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
390 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpblendd);
391 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
392}
393
394
395/* Opcode VEX.66.0F3A 0x03 - invalid */
396
397
398/** Opcode VEX.66.0F3A 0x04.
399 * AVX,AVX */
400FNIEMOP_DEF(iemOp_vpermilps_Vx_Wx_Ib)
401{
402 IEMOP_MNEMONIC3(VEX_RMI, VPERMILPS, vpermilps, Vx_WO, Wx, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_V_ZERO);
403 IEMOPMEDIAOPTF2IMM8_INIT_VARS(vpermilps);
404 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
405}
406
407
408/** Opcode VEX.66.0F3A 0x05.
409 * AVX,AVX */
410FNIEMOP_DEF(iemOp_vpermilpd_Vx_Wx_Ib)
411{
412 IEMOP_MNEMONIC3(VEX_RMI, VPERMILPD, vpermilpd, Vx_WO, Wx, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_V_ZERO);
413 IEMOPMEDIAOPTF2IMM8_INIT_VARS(vpermilpd);
414 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
415}
416
417
418/** Opcode VEX.66.0F3A 0x06 (vex only) */
419FNIEMOP_DEF(iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib)
420{
421 IEMOP_MNEMONIC4(VEX_RVMI, VPERM2F128, vperm2f128, Vqq_WO, Hqq, Wqq, Ib, DISOPTYPE_HARMLESS, 0);
422 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
423 if (IEM_IS_MODRM_REG_MODE(bRm))
424 {
425 /*
426 * Register, register.
427 */
428 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
429 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
430 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
431 IEM_MC_LOCAL(RTUINT256U, uDst);
432 IEM_MC_LOCAL(RTUINT256U, uSrc1);
433 IEM_MC_LOCAL(RTUINT256U, uSrc2);
434 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
435 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
436 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
437 IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
438 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
439 IEM_MC_PREPARE_AVX_USAGE();
440 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
441 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
442 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback),
443 puDst, puSrc1, puSrc2, bImmArg);
444 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
445 IEM_MC_ADVANCE_RIP_AND_FINISH();
446 IEM_MC_END();
447 }
448 else
449 {
450 /*
451 * Register, memory.
452 */
453 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
454 IEM_MC_LOCAL(RTUINT256U, uDst);
455 IEM_MC_LOCAL(RTUINT256U, uSrc1);
456 IEM_MC_LOCAL(RTUINT256U, uSrc2);
457 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
458 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
459 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
460 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
461
462 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
463 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
464 IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
465 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
466 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
467 IEM_MC_PREPARE_AVX_USAGE();
468
469 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
470 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
471 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback),
472 puDst, puSrc1, puSrc2, bImmArg);
473 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
474
475 IEM_MC_ADVANCE_RIP_AND_FINISH();
476 IEM_MC_END();
477 }
478}
479
480
481/* Opcode VEX.66.0F3A 0x07 - invalid */
482/** Opcode VEX.66.0F3A 0x08. */
483FNIEMOP_STUB(iemOp_vroundps_Vx_Wx_Ib);
484/** Opcode VEX.66.0F3A 0x09. */
485FNIEMOP_STUB(iemOp_vroundpd_Vx_Wx_Ib);
486/** Opcode VEX.66.0F3A 0x0a. */
487FNIEMOP_STUB(iemOp_vroundss_Vss_Wss_Ib);
488/** Opcode VEX.66.0F3A 0x0b. */
489FNIEMOP_STUB(iemOp_vroundsd_Vsd_Wsd_Ib);
490
491
492/** Opcode VEX.66.0F3A 0x0c.
493 * AVX,AVX */
494FNIEMOP_DEF(iemOp_vblendps_Vx_Hx_Wx_Ib)
495{
496 IEMOP_MNEMONIC4(VEX_RVMI, VBLENDPS, vblendps, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
497 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendps);
498 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
499}
500
501
502/** Opcode VEX.66.0F3A 0x0d.
503 * AVX,AVX */
504FNIEMOP_DEF(iemOp_vblendpd_Vx_Hx_Wx_Ib)
505{
506 IEMOP_MNEMONIC4(VEX_RVMI, VBLENDPD, vblendpd, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
507 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendpd);
508 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
509}
510
511
512/** Opcode VEX.66.0F3A 0x0e.
513 * AVX,AVX2 */
514FNIEMOP_DEF(iemOp_vpblendw_Vx_Hx_Wx_Ib)
515{
516 IEMOP_MNEMONIC4(VEX_RVMI, VPBLENDW, vpblendw, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
517 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpblendw);
518 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
519}
520
521
522/** Opcode VEX.0F3A 0x0f - invalid. */
523
524
525/** Opcode VEX.66.0F3A 0x0f.
526 * AVX,AVX2 */
527FNIEMOP_DEF(iemOp_vpalignr_Vx_Hx_Wx_Ib)
528{
529 IEMOP_MNEMONIC4(VEX_RVMI, VPALIGNR, vpalignr, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
530 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpalignr);
531 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
532}
533
534
535/* Opcode VEX.66.0F3A 0x10 - invalid */
536/* Opcode VEX.66.0F3A 0x11 - invalid */
537/* Opcode VEX.66.0F3A 0x12 - invalid */
538/* Opcode VEX.66.0F3A 0x13 - invalid */
539
540
541/** Opcode VEX.66.0F3A 0x14 - vpextrb Eb, Vdq, Ib */
542FNIEMOP_DEF(iemOp_vpextrb_Eb_Vdq_Ib)
543{
544 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRB, vpextrb, Eb, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_V_ZERO | IEMOPHINT_IGNORES_REXW);
545 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
546 if (IEM_IS_MODRM_REG_MODE(bRm))
547 {
548 /*
549 * greg32, XMM, imm8.
550 */
551 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
552 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
553 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
554 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
555 IEM_MC_PREPARE_AVX_USAGE();
556
557 IEM_MC_LOCAL(uint8_t, uValue);
558 IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/);
559 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
560 IEM_MC_ADVANCE_RIP_AND_FINISH();
561 IEM_MC_END();
562 }
563 else
564 {
565 /*
566 * [mem8], XMM, imm8.
567 */
568 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
569 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
570 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
571 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
572
573 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
574 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
575 IEM_MC_PREPARE_AVX_USAGE();
576
577 IEM_MC_LOCAL(uint8_t, uValue);
578 IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/);
579 IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
580 IEM_MC_ADVANCE_RIP_AND_FINISH();
581 IEM_MC_END();
582 }
583}
584
585
586/** Opcode VEX.66.0F3A 0x15 - vpextrw Ew, Vdq, Ib */
587FNIEMOP_DEF(iemOp_vpextrw_Ew_Vdq_Ib)
588{
589 /** @todo testcase: check that this ignores VEX.W. */
590 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRW, vpextrw, Ew_WO, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_V_ZERO | IEMOPHINT_IGNORES_REXW);
591 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
592 if (IEM_IS_MODRM_REG_MODE(bRm))
593 {
594 /*
595 * greg32, XMM, imm8.
596 */
597 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
598 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
599 IEM_MC_LOCAL(uint16_t, uValue);
600
601 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
602 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
603 IEM_MC_PREPARE_AVX_USAGE();
604
605 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7);
606 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
607 IEM_MC_ADVANCE_RIP_AND_FINISH();
608 IEM_MC_END();
609 }
610 else
611 {
612 /*
613 * [mem16], XMM, imm8.
614 */
615 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
616 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
617 IEM_MC_LOCAL(uint16_t, uValue);
618 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
619 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
620
621 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
622 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
623 IEM_MC_PREPARE_AVX_USAGE();
624
625 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7);
626 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
627 IEM_MC_ADVANCE_RIP_AND_FINISH();
628 IEM_MC_END();
629 }
630}
631
632
633/** Opcode VEX.66.0F3A 0x16 - vpextrd / vpextrq Eq / Ey, Vdq, Ib */
634FNIEMOP_DEF(iemOp_vpextrd_q_Ey_Vdq_Ib)
635{
636 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
637 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
638 {
639 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRQ, vpextrq, Eq_WO, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_W_ONE);
640 if (IEM_IS_MODRM_REG_MODE(bRm))
641 {
642 /*
643 * greg64, XMM, imm8.
644 */
645 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
646 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
647 IEM_MC_LOCAL(uint64_t, uValue);
648
649 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
650 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
651 IEM_MC_PREPARE_AVX_USAGE();
652
653 IEM_MC_FETCH_XREG_U64(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
654 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
655 IEM_MC_ADVANCE_RIP_AND_FINISH();
656 IEM_MC_END();
657 }
658 else
659 {
660 /*
661 * [mem64], XMM, imm8.
662 */
663 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
664 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
665 IEM_MC_LOCAL(uint64_t, uValue);
666 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
667 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
668
669 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
670 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
671 IEM_MC_PREPARE_AVX_USAGE();
672
673 IEM_MC_FETCH_XREG_U64(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
674 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
675 IEM_MC_ADVANCE_RIP_AND_FINISH();
676 IEM_MC_END();
677 }
678 }
679 else
680 {
681 /**
682 * @opdone
683 */
684 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRD, vpextrd, Ey_WO, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_W_ZERO);
685 if (IEM_IS_MODRM_REG_MODE(bRm))
686 {
687 /*
688 * greg32, XMM, imm8.
689 */
690 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
691 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
692 IEM_MC_LOCAL(uint32_t, uValue);
693
694 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
695 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
696 IEM_MC_PREPARE_AVX_USAGE();
697
698 IEM_MC_FETCH_XREG_U32(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3);
699 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
700 IEM_MC_ADVANCE_RIP_AND_FINISH();
701 IEM_MC_END();
702 }
703 else
704 {
705 /*
706 * [mem32], XMM, imm8.
707 */
708 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
709 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
710 IEM_MC_LOCAL(uint32_t, uValue);
711 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
712 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
713
714 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
715 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
716 IEM_MC_PREPARE_AVX_USAGE();
717
718 IEM_MC_FETCH_XREG_U32(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3);
719 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
720 IEM_MC_ADVANCE_RIP_AND_FINISH();
721 IEM_MC_END();
722 }
723 }
724}
725
726
727/** Opcode VEX.66.0F3A 0x17. */
728FNIEMOP_STUB(iemOp_vextractps_Ed_Vdq_Ib);
729
730
731/** Opcode VEX.66.0F3A 0x18 (vex only). */
732FNIEMOP_DEF(iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib)
733{
734 //IEMOP_MNEMONIC4(VEX_RMI, VINSERTF128, vinsertf128, Vx, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
735 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
736 if (IEM_IS_MODRM_REG_MODE(bRm))
737 {
738 /*
739 * Register, register.
740 */
741 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
742 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
743 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
744 IEM_MC_LOCAL(RTUINT128U, uSrc);
745
746 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
747 IEM_MC_PREPARE_AVX_USAGE();
748
749 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
750 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
751 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
752
753 IEM_MC_ADVANCE_RIP_AND_FINISH();
754 IEM_MC_END();
755 }
756 else
757 {
758 /*
759 * Register, memory.
760 */
761 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
762 IEM_MC_LOCAL(RTUINT128U, uSrc);
763 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
764
765 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
766 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
767 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
768 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
769 IEM_MC_PREPARE_AVX_USAGE();
770
771 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
772 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
773 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
774
775 IEM_MC_ADVANCE_RIP_AND_FINISH();
776 IEM_MC_END();
777 }
778}
779
780
781/** Opcode VEX.66.0F3A 0x19 (vex only). */
782FNIEMOP_DEF(iemOp_vextractf128_Wdq_Vqq_Ib)
783{
784 IEMOP_MNEMONIC3(VEX_MRI, VEXTRACTF128, vextractf128, Wdq, Vqq, Ib, DISOPTYPE_HARMLESS, 0);
785 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
786 if (IEM_IS_MODRM_REG_MODE(bRm))
787 {
788 /*
789 * Register, register.
790 */
791 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
792 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
793 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx2);
794
795 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
796 IEM_MC_PREPARE_AVX_USAGE();
797
798 IEM_MC_LOCAL(RTUINT128U, uDst);
799 IEM_MC_FETCH_YREG_U128(uDst, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
800 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_RM(pVCpu, bRm), uDst);
801
802 IEM_MC_ADVANCE_RIP_AND_FINISH();
803 IEM_MC_END();
804 }
805 else
806 {
807 /*
808 * Register, memory.
809 */
810 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
811 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
812
813 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
814 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
815 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx2);
816 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
817 IEM_MC_PREPARE_AVX_USAGE();
818
819 IEM_MC_LOCAL(RTUINT128U, uDst);
820 IEM_MC_FETCH_YREG_U128(uDst, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
821 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uDst);
822
823 IEM_MC_ADVANCE_RIP_AND_FINISH();
824 IEM_MC_END();
825 }
826}
827
828
829/* Opcode VEX.66.0F3A 0x1a - invalid */
830/* Opcode VEX.66.0F3A 0x1b - invalid */
831/* Opcode VEX.66.0F3A 0x1c - invalid */
832/** Opcode VEX.66.0F3A 0x1d (vex only). */
833FNIEMOP_STUB(iemOp_vcvtps2ph_Wx_Vx_Ib);
834/* Opcode VEX.66.0F3A 0x1e - invalid */
835/* Opcode VEX.66.0F3A 0x1f - invalid */
836
837
838/** Opcode VEX.66.0F3A 0x20. */
839FNIEMOP_DEF(iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib)
840{
841 /*IEMOP_MNEMONIC4(VEX_RMVI, VPINSRB, vpinsrb, Vdq, Hdq, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);*/ /** @todo */
842 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
843 if (IEM_IS_MODRM_REG_MODE(bRm))
844 {
845 /*
846 * Register, register.
847 */
848 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
849 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
850 IEM_MC_LOCAL(RTUINT128U, uSrc1);
851 IEM_MC_LOCAL(uint8_t, uValue);
852
853 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
854 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
855 IEM_MC_PREPARE_AVX_USAGE();
856
857 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
858 IEM_MC_FETCH_GREG_U8(uValue, IEM_GET_MODRM_RM(pVCpu, bRm));
859 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
860 IEM_MC_STORE_XREG_U8( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15, uValue);
861 IEM_MC_ADVANCE_RIP_AND_FINISH();
862 IEM_MC_END();
863 }
864 else
865 {
866 /*
867 * Register, memory.
868 */
869 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
870 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
871 IEM_MC_LOCAL(RTUINT128U, uSrc1);
872 IEM_MC_LOCAL(uint8_t, uValue);
873
874 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
875 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
876 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
877 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
878 IEM_MC_PREPARE_AVX_USAGE();
879
880 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
881 IEM_MC_FETCH_MEM_U8(uValue, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
882 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
883 IEM_MC_STORE_XREG_U8( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15, uValue);
884 IEM_MC_ADVANCE_RIP_AND_FINISH();
885 IEM_MC_END();
886 }
887}
888
889
890/** Opcode VEX.66.0F3A 0x21, */
891FNIEMOP_STUB(iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib);
892
893
894/** Opcode VEX.66.0F3A 0x22. */
895FNIEMOP_DEF(iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib)
896{
897 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
898 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
899 {
900 /*IEMOP_MNEMONIC4(VEX_RMVI, VPINSRQ, vpinsrq, Vdq, Hdq, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);*/ /** @todo */
901 if (IEM_IS_MODRM_REG_MODE(bRm))
902 {
903 /*
904 * Register, register.
905 */
906 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
907 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
908 IEM_MC_LOCAL(RTUINT128U, uSrc1);
909 IEM_MC_LOCAL(uint64_t, uValue);
910
911 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
912 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
913 IEM_MC_PREPARE_AVX_USAGE();
914
915 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
916 IEM_MC_FETCH_GREG_U64(uValue, IEM_GET_MODRM_RM(pVCpu, bRm));
917 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
918 IEM_MC_STORE_XREG_U64( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uValue);
919 IEM_MC_ADVANCE_RIP_AND_FINISH();
920 IEM_MC_END();
921 }
922 else
923 {
924 /*
925 * Register, memory.
926 */
927 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
928 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
929 IEM_MC_LOCAL(RTUINT128U, uSrc1);
930 IEM_MC_LOCAL(uint64_t, uValue);
931
932 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
933 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
934 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
935 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
936 IEM_MC_PREPARE_AVX_USAGE();
937
938 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
939 IEM_MC_FETCH_MEM_U64(uValue, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
940 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
941 IEM_MC_STORE_XREG_U64( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uValue);
942 IEM_MC_ADVANCE_RIP_AND_FINISH();
943 IEM_MC_END();
944 }
945 }
946 else
947 {
948 /*IEMOP_MNEMONIC4(VEX_RMVI, VPINSRD, vpinsrd, Vdq, Hdq, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);*/ /** @todo */
949 if (IEM_IS_MODRM_REG_MODE(bRm))
950 {
951 /*
952 * Register, register.
953 */
954 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
955 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
956 IEM_MC_LOCAL(RTUINT128U, uSrc1);
957 IEM_MC_LOCAL(uint32_t, uValue);
958
959 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
960 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
961 IEM_MC_PREPARE_AVX_USAGE();
962
963 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
964 IEM_MC_FETCH_GREG_U32(uValue, IEM_GET_MODRM_RM(pVCpu, bRm));
965 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
966 IEM_MC_STORE_XREG_U32( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3, uValue);
967 IEM_MC_ADVANCE_RIP_AND_FINISH();
968 IEM_MC_END();
969 }
970 else
971 {
972 /*
973 * Register, memory.
974 */
975 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
976 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
977 IEM_MC_LOCAL(RTUINT128U, uSrc1);
978 IEM_MC_LOCAL(uint32_t, uValue);
979
980 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
981 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
982 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
983 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
984 IEM_MC_PREPARE_AVX_USAGE();
985
986 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
987 IEM_MC_FETCH_MEM_U32(uValue, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
988 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
989 IEM_MC_STORE_XREG_U32( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3, uValue);
990 IEM_MC_ADVANCE_RIP_AND_FINISH();
991 IEM_MC_END();
992 }
993 }
994}
995
996
997/* Opcode VEX.66.0F3A 0x23 - invalid */
998/* Opcode VEX.66.0F3A 0x24 - invalid */
999/* Opcode VEX.66.0F3A 0x25 - invalid */
1000/* Opcode VEX.66.0F3A 0x26 - invalid */
1001/* Opcode VEX.66.0F3A 0x27 - invalid */
1002/* Opcode VEX.66.0F3A 0x28 - invalid */
1003/* Opcode VEX.66.0F3A 0x29 - invalid */
1004/* Opcode VEX.66.0F3A 0x2a - invalid */
1005/* Opcode VEX.66.0F3A 0x2b - invalid */
1006/* Opcode VEX.66.0F3A 0x2c - invalid */
1007/* Opcode VEX.66.0F3A 0x2d - invalid */
1008/* Opcode VEX.66.0F3A 0x2e - invalid */
1009/* Opcode VEX.66.0F3A 0x2f - invalid */
1010
1011
1012/* Opcode VEX.66.0F3A 0x30 - invalid */
1013/* Opcode VEX.66.0F3A 0x31 - invalid */
1014/* Opcode VEX.66.0F3A 0x32 - invalid */
1015/* Opcode VEX.66.0F3A 0x33 - invalid */
1016/* Opcode VEX.66.0F3A 0x34 - invalid */
1017/* Opcode VEX.66.0F3A 0x35 - invalid */
1018/* Opcode VEX.66.0F3A 0x36 - invalid */
1019/* Opcode VEX.66.0F3A 0x37 - invalid */
1020
1021
1022/** Opcode VEX.66.0F3A 0x38 (vex only). */
1023FNIEMOP_DEF(iemOp_vinserti128_Vqq_Hqq_Wqq_Ib)
1024{
1025 //IEMOP_MNEMONIC4(VEX_RMI, VINSERTI128, vinserti128, Vx, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
1026 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1027 if (IEM_IS_MODRM_REG_MODE(bRm))
1028 {
1029 /*
1030 * Register, register.
1031 */
1032 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1033 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1034 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
1035 IEM_MC_LOCAL(RTUINT128U, uSrc);
1036
1037 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1038 IEM_MC_PREPARE_AVX_USAGE();
1039
1040 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1041 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
1042 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
1043
1044 IEM_MC_ADVANCE_RIP_AND_FINISH();
1045 IEM_MC_END();
1046 }
1047 else
1048 {
1049 /*
1050 * Register, memory.
1051 */
1052 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1053 IEM_MC_LOCAL(RTUINT128U, uSrc);
1054 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1055
1056 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1057 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1058 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
1059 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1060 IEM_MC_PREPARE_AVX_USAGE();
1061
1062 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1063 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
1064 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
1065
1066 IEM_MC_ADVANCE_RIP_AND_FINISH();
1067 IEM_MC_END();
1068 }
1069}
1070
1071
1072/** Opcode VEX.66.0F3A 0x39 (vex only). */
1073FNIEMOP_DEF(iemOp_vextracti128_Wdq_Vqq_Ib)
1074{
1075 IEMOP_MNEMONIC3(VEX_MRI, VEXTRACTI128, vextracti128, Wdq, Vqq, Ib, DISOPTYPE_HARMLESS, 0);
1076 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1077 if (IEM_IS_MODRM_REG_MODE(bRm))
1078 {
1079 /*
1080 * Register, register.
1081 */
1082 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1083 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1084 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx2);
1085
1086 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1087 IEM_MC_PREPARE_AVX_USAGE();
1088
1089 IEM_MC_LOCAL(RTUINT128U, uDst);
1090 IEM_MC_FETCH_YREG_U128(uDst, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
1091 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_RM(pVCpu, bRm), uDst);
1092
1093 IEM_MC_ADVANCE_RIP_AND_FINISH();
1094 IEM_MC_END();
1095 }
1096 else
1097 {
1098 /*
1099 * Register, memory.
1100 */
1101 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1102 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1103
1104 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1105 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1106 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx2);
1107 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1108 IEM_MC_PREPARE_AVX_USAGE();
1109
1110 IEM_MC_LOCAL(RTUINT128U, uDst);
1111 IEM_MC_FETCH_YREG_U128(uDst, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
1112 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uDst);
1113
1114 IEM_MC_ADVANCE_RIP_AND_FINISH();
1115 IEM_MC_END();
1116 }
1117}
1118
1119
1120/* Opcode VEX.66.0F3A 0x3a - invalid */
1121/* Opcode VEX.66.0F3A 0x3b - invalid */
1122/* Opcode VEX.66.0F3A 0x3c - invalid */
1123/* Opcode VEX.66.0F3A 0x3d - invalid */
1124/* Opcode VEX.66.0F3A 0x3e - invalid */
1125/* Opcode VEX.66.0F3A 0x3f - invalid */
1126
1127
1128/** Opcode VEX.66.0F3A 0x40. */
1129FNIEMOP_STUB(iemOp_vdpps_Vx_Hx_Wx_Ib);
1130/** Opcode VEX.66.0F3A 0x41, */
1131FNIEMOP_STUB(iemOp_vdppd_Vdq_Hdq_Wdq_Ib);
1132
1133
1134/** Opcode VEX.66.0F3A 0x42. */
1135FNIEMOP_DEF(iemOp_vmpsadbw_Vx_Hx_Wx_Ib)
1136{
1137 IEMOP_MNEMONIC4(VEX_RVMI, VMPSADBW, vmpsadbw, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
1138 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vmpsadbw);
1139 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
1140}
1141
1142
1143/* Opcode VEX.66.0F3A 0x43 - invalid */
1144
1145
1146/** Opcode VEX.66.0F3A 0x44. */
1147FNIEMOP_DEF(iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib)
1148{
1149 IEMOP_MNEMONIC4(VEX_RVMI, VPCLMULQDQ, vpclmulqdq, Vdq_WO, Hdq, Wdq, Id, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1150 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1151 if (IEM_IS_MODRM_REG_MODE(bRm))
1152 {
1153 /*
1154 * Register, register.
1155 */
1156 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1157 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1158 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
1159 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1160 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1161 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
1162 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1163 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1164 IEM_MC_PREPARE_AVX_USAGE();
1165 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1166 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1167 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1168 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
1169 puDst, puSrc1, puSrc2, bImmArg);
1170 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1171 IEM_MC_ADVANCE_RIP_AND_FINISH();
1172 IEM_MC_END();
1173 }
1174 else
1175 {
1176 /*
1177 * Register, memory.
1178 */
1179 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1180 IEM_MC_LOCAL(RTUINT128U, uSrc2);
1181 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1182 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1183 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1184 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
1185
1186 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1187 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1188 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1189 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
1190 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1191 IEM_MC_PREPARE_AVX_USAGE();
1192
1193 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1194 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1195 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1196 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
1197 puDst, puSrc1, puSrc2, bImmArg);
1198 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1199
1200 IEM_MC_ADVANCE_RIP_AND_FINISH();
1201 IEM_MC_END();
1202 }
1203}
1204
1205
1206/* Opcode VEX.66.0F3A 0x45 - invalid */
1207
1208
1209/** Opcode VEX.66.0F3A 0x46 (vex only) */
1210FNIEMOP_DEF(iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib)
1211{
1212 IEMOP_MNEMONIC4(VEX_RVMI, VPERM2I128, vperm2i128, Vqq_WO, Hqq, Wqq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ONE);
1213 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1214 if (IEM_IS_MODRM_REG_MODE(bRm))
1215 {
1216 /*
1217 * Register, register.
1218 */
1219 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1220 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1221 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
1222 IEM_MC_LOCAL(RTUINT256U, uDst);
1223 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1224 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1225 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1226 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1227 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1228 IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
1229 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1230 IEM_MC_PREPARE_AVX_USAGE();
1231 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1232 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1233 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback),
1234 puDst, puSrc1, puSrc2, bImmArg);
1235 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1236 IEM_MC_ADVANCE_RIP_AND_FINISH();
1237 IEM_MC_END();
1238 }
1239 else
1240 {
1241 /*
1242 * Register, memory.
1243 */
1244 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1245 IEM_MC_LOCAL(RTUINT256U, uDst);
1246 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1247 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1248 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1249 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1250 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1251 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1252
1253 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1254 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1255 IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
1256 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
1257 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1258 IEM_MC_PREPARE_AVX_USAGE();
1259
1260 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1261 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1262 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback),
1263 puDst, puSrc1, puSrc2, bImmArg);
1264 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1265
1266 IEM_MC_ADVANCE_RIP_AND_FINISH();
1267 IEM_MC_END();
1268 }
1269}
1270
1271
1272/* Opcode VEX.66.0F3A 0x47 - invalid */
1273/** Opcode VEX.66.0F3A 0x48 (AMD tables only). */
1274FNIEMOP_STUB(iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx);
1275/** Opcode VEX.66.0F3A 0x49 (AMD tables only). */
1276FNIEMOP_STUB(iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx);
1277
1278
1279/**
1280 * Common worker for AVX2 instructions on the forms:
1281 * - vblendvps/d xmm0, xmm1, xmm2/mem128, xmm4
1282 * - vblendvps/d ymm0, ymm1, ymm2/mem256, ymm4
1283 *
1284 * Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operations.
1285 * Additionally, it triggers \#UD if VEX.W is 1.
1286 */
1287FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
1288{
1289 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1290 if (IEM_IS_MODRM_REG_MODE(bRm))
1291 {
1292 /*
1293 * Register, register.
1294 */
1295 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1296 if (pVCpu->iem.s.uVexLength)
1297 {
1298 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1299 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1300 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1301 IEM_MC_PREPARE_AVX_USAGE();
1302 IEM_MC_LOCAL(RTUINT256U, uDst);
1303 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1304 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1305 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1306 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1307 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1308 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1309 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1310 IEM_MC_LOCAL(RTUINT256U, uSrc3);
1311 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1312 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1313 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1314 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1315 IEM_MC_ADVANCE_RIP_AND_FINISH();
1316 IEM_MC_END();
1317 }
1318 else
1319 {
1320 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1321 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1322 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1323 IEM_MC_PREPARE_AVX_USAGE();
1324 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1325 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1326 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1327 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1328 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
1329 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1330 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1331 IEM_MC_REF_XREG_U128_CONST(puSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1332 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1333 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1334 IEM_MC_ADVANCE_RIP_AND_FINISH();
1335 IEM_MC_END();
1336 }
1337 }
1338 else
1339 {
1340 /*
1341 * Register, memory.
1342 */
1343 if (pVCpu->iem.s.uVexLength)
1344 {
1345 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1346 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1347 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1348 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1349 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1350 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1351 IEM_MC_PREPARE_AVX_USAGE();
1352
1353 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1354 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1355 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1356
1357 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1358 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1359 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1360 IEM_MC_LOCAL(RTUINT256U, uSrc3);
1361 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1362 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1363 IEM_MC_LOCAL(RTUINT256U, uDst);
1364 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1365 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1366 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1367
1368 IEM_MC_ADVANCE_RIP_AND_FINISH();
1369 IEM_MC_END();
1370 }
1371 else
1372 {
1373 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1374 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1375 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1376 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1377 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1378 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1379 IEM_MC_PREPARE_AVX_USAGE();
1380
1381 IEM_MC_LOCAL(RTUINT128U, uSrc2);
1382 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
1383 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1384
1385 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1386 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1387 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1388 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1389 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1390 IEM_MC_REF_XREG_U128_CONST(puSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1391 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1392 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1393
1394 IEM_MC_ADVANCE_RIP_AND_FINISH();
1395 IEM_MC_END();
1396 }
1397 }
1398}
1399
1400
1401/** Opcode VEX.66.0F3A 0x4a (vex only).
1402 * AVX, AVX */
1403FNIEMOP_DEF(iemOp_vblendvps_Vx_Hx_Wx_Lx)
1404{
1405 IEMOP_MNEMONIC4(VEX_RVMR, VBLENDVPS, vblendvps, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0);
1406 IEMOPBLENDOP_INIT_VARS(vblendvps);
1407 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
1408}
1409
1410
1411/** Opcode VEX.66.0F3A 0x4b (vex only).
1412 * AVX, AVX */
1413FNIEMOP_DEF(iemOp_vblendvpd_Vx_Hx_Wx_Lx)
1414{
1415 IEMOP_MNEMONIC4(VEX_RVMR, VBLENDVPD, vblendvpd, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0);
1416 IEMOPBLENDOP_INIT_VARS(vblendvpd);
1417 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
1418}
1419
1420
1421/**
1422 * Common worker for AVX2 instructions on the forms:
1423 * - vpxxx xmm0, xmm1, xmm2/mem128, xmm4
1424 * - vpxxx ymm0, ymm1, ymm2/mem256, ymm4
1425 *
1426 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
1427 * Additionally, both VEX.W and VEX.L must be zero.
1428 */
1429FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
1430{
1431 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1432 if (IEM_IS_MODRM_REG_MODE(bRm))
1433 {
1434 /*
1435 * Register, register.
1436 */
1437 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1438 if (pVCpu->iem.s.uVexLength)
1439 {
1440 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1441 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx2);
1442 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1443 IEM_MC_PREPARE_AVX_USAGE();
1444
1445 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1446 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1447 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1448
1449 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1450 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1451 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1452
1453 IEM_MC_LOCAL(RTUINT256U, uSrc3);
1454 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1455 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1456
1457 IEM_MC_LOCAL(RTUINT256U, uDst);
1458 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1459
1460 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1461
1462 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1463 IEM_MC_ADVANCE_RIP_AND_FINISH();
1464 IEM_MC_END();
1465 }
1466 else
1467 {
1468 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1469 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1470 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1471 IEM_MC_PREPARE_AVX_USAGE();
1472 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1473 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1474 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1475 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1476 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
1477 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1478 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1479 IEM_MC_REF_XREG_U128_CONST(puSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1480 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1481 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1482 IEM_MC_ADVANCE_RIP_AND_FINISH();
1483 IEM_MC_END();
1484 }
1485 }
1486 else
1487 {
1488 /*
1489 * Register, memory.
1490 */
1491 if (pVCpu->iem.s.uVexLength)
1492 {
1493 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1494 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1495
1496 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1497 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1498
1499 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx2);
1500 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1501 IEM_MC_PREPARE_AVX_USAGE();
1502
1503 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1504 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1505 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1506
1507 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1508 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1509 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1510
1511 IEM_MC_LOCAL(RTUINT256U, uSrc3);
1512 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1513 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1514
1515 IEM_MC_LOCAL(RTUINT256U, uDst);
1516 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1517
1518 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1519
1520 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1521 IEM_MC_ADVANCE_RIP_AND_FINISH();
1522 IEM_MC_END();
1523 }
1524 else
1525 {
1526 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1527 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1528 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1529 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1530
1531 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1532 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1533 IEM_MC_PREPARE_AVX_USAGE();
1534
1535 IEM_MC_LOCAL(RTUINT128U, uSrc2);
1536 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
1537 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1538
1539 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1540 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1541 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1542 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1543 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1544 IEM_MC_REF_XREG_U128_CONST(puSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1545 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1546 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1547
1548 IEM_MC_ADVANCE_RIP_AND_FINISH();
1549 IEM_MC_END();
1550 }
1551 }
1552}
1553
1554
1555/** Opcode VEX.66.0F3A 0x4c (vex only).
1556 * AVX, AVX2 */
1557FNIEMOP_DEF(iemOp_vpblendvb_Vx_Hx_Wx_Lx)
1558{
1559 /** @todo testcase: cover VEX.W=1 and check that it triggers \#UD on both real
1560 * and emulated hardware. */
1561 IEMOP_MNEMONIC4(VEX_RVMR, VPBLENDVB, vpblendvb, Vx_WO, Hx, Wx, Lx, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_W_ZERO);
1562 IEMOPBLENDOP_INIT_VARS(vpblendvb);
1563 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1564}
1565
1566
1567/* Opcode VEX.66.0F3A 0x4d - invalid */
1568/* Opcode VEX.66.0F3A 0x4e - invalid */
1569/* Opcode VEX.66.0F3A 0x4f - invalid */
1570
1571
1572/* Opcode VEX.66.0F3A 0x50 - invalid */
1573/* Opcode VEX.66.0F3A 0x51 - invalid */
1574/* Opcode VEX.66.0F3A 0x52 - invalid */
1575/* Opcode VEX.66.0F3A 0x53 - invalid */
1576/* Opcode VEX.66.0F3A 0x54 - invalid */
1577/* Opcode VEX.66.0F3A 0x55 - invalid */
1578/* Opcode VEX.66.0F3A 0x56 - invalid */
1579/* Opcode VEX.66.0F3A 0x57 - invalid */
1580/* Opcode VEX.66.0F3A 0x58 - invalid */
1581/* Opcode VEX.66.0F3A 0x59 - invalid */
1582/* Opcode VEX.66.0F3A 0x5a - invalid */
1583/* Opcode VEX.66.0F3A 0x5b - invalid */
1584/** Opcode VEX.66.0F3A 0x5c (AMD tables only). */
1585FNIEMOP_STUB(iemOp_vfmaddsubps_Vx_Lx_Wx_Hx);
1586/** Opcode VEX.66.0F3A 0x5d (AMD tables only). */
1587FNIEMOP_STUB(iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx);
1588/** Opcode VEX.66.0F3A 0x5e (AMD tables only). */
1589FNIEMOP_STUB(iemOp_vfmsubaddps_Vx_Lx_Wx_Hx);
1590/** Opcode VEX.66.0F3A 0x5f (AMD tables only). */
1591FNIEMOP_STUB(iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx);
1592
1593
1594/** Opcode VEX.66.0F3A 0x60. */
1595FNIEMOP_STUB(iemOp_vpcmpestrm_Vdq_Wdq_Ib);
1596/** Opcode VEX.66.0F3A 0x61, */
1597FNIEMOP_STUB(iemOp_vpcmpestri_Vdq_Wdq_Ib);
1598/** Opcode VEX.66.0F3A 0x62. */
1599FNIEMOP_STUB(iemOp_vpcmpistrm_Vdq_Wdq_Ib);
1600/** Opcode VEX.66.0F3A 0x63*/
1601FNIEMOP_STUB(iemOp_vpcmpistri_Vdq_Wdq_Ib);
1602/* Opcode VEX.66.0F3A 0x64 - invalid */
1603/* Opcode VEX.66.0F3A 0x65 - invalid */
1604/* Opcode VEX.66.0F3A 0x66 - invalid */
1605/* Opcode VEX.66.0F3A 0x67 - invalid */
1606/** Opcode VEX.66.0F3A 0x68 (AMD tables only). */
1607FNIEMOP_STUB(iemOp_vfmaddps_Vx_Lx_Wx_Hx);
1608/** Opcode VEX.66.0F3A 0x69 (AMD tables only). */
1609FNIEMOP_STUB(iemOp_vfmaddpd_Vx_Lx_Wx_Hx);
1610/** Opcode VEX.66.0F3A 0x6a (AMD tables only). */
1611FNIEMOP_STUB(iemOp_vfmaddss_Vx_Lx_Wx_Hx);
1612/** Opcode VEX.66.0F3A 0x6b (AMD tables only). */
1613FNIEMOP_STUB(iemOp_vfmaddsd_Vx_Lx_Wx_Hx);
1614/** Opcode VEX.66.0F3A 0x6c (AMD tables only). */
1615FNIEMOP_STUB(iemOp_vfmsubps_Vx_Lx_Wx_Hx);
1616/** Opcode VEX.66.0F3A 0x6d (AMD tables only). */
1617FNIEMOP_STUB(iemOp_vfmsubpd_Vx_Lx_Wx_Hx);
1618/** Opcode VEX.66.0F3A 0x6e (AMD tables only). */
1619FNIEMOP_STUB(iemOp_vfmsubss_Vx_Lx_Wx_Hx);
1620/** Opcode VEX.66.0F3A 0x6f (AMD tables only). */
1621FNIEMOP_STUB(iemOp_vfmsubsd_Vx_Lx_Wx_Hx);
1622
1623/* Opcode VEX.66.0F3A 0x70 - invalid */
1624/* Opcode VEX.66.0F3A 0x71 - invalid */
1625/* Opcode VEX.66.0F3A 0x72 - invalid */
1626/* Opcode VEX.66.0F3A 0x73 - invalid */
1627/* Opcode VEX.66.0F3A 0x74 - invalid */
1628/* Opcode VEX.66.0F3A 0x75 - invalid */
1629/* Opcode VEX.66.0F3A 0x76 - invalid */
1630/* Opcode VEX.66.0F3A 0x77 - invalid */
1631/** Opcode VEX.66.0F3A 0x78 (AMD tables only). */
1632FNIEMOP_STUB(iemOp_vfnmaddps_Vx_Lx_Wx_Hx);
1633/** Opcode VEX.66.0F3A 0x79 (AMD tables only). */
1634FNIEMOP_STUB(iemOp_vfnmaddpd_Vx_Lx_Wx_Hx);
1635/** Opcode VEX.66.0F3A 0x7a (AMD tables only). */
1636FNIEMOP_STUB(iemOp_vfnmaddss_Vx_Lx_Wx_Hx);
1637/** Opcode VEX.66.0F3A 0x7b (AMD tables only). */
1638FNIEMOP_STUB(iemOp_vfnmaddsd_Vx_Lx_Wx_Hx);
1639/** Opcode VEX.66.0F3A 0x7c (AMD tables only). */
1640FNIEMOP_STUB(iemOp_vfnmsubps_Vx_Lx_Wx_Hx);
1641/** Opcode VEX.66.0F3A 0x7d (AMD tables only). */
1642FNIEMOP_STUB(iemOp_vfnmsubpd_Vx_Lx_Wx_Hx);
1643/** Opcode VEX.66.0F3A 0x7e (AMD tables only). */
1644FNIEMOP_STUB(iemOp_vfnmsubss_Vx_Lx_Wx_Hx);
1645/** Opcode VEX.66.0F3A 0x7f (AMD tables only). */
1646FNIEMOP_STUB(iemOp_vfnmsubsd_Vx_Lx_Wx_Hx);
1647
1648/* Opcodes 0x0f 0x80 thru 0x0f 0xb0 are unused. */
1649
1650
1651/* Opcode 0x0f 0xc0 - invalid */
1652/* Opcode 0x0f 0xc1 - invalid */
1653/* Opcode 0x0f 0xc2 - invalid */
1654/* Opcode 0x0f 0xc3 - invalid */
1655/* Opcode 0x0f 0xc4 - invalid */
1656/* Opcode 0x0f 0xc5 - invalid */
1657/* Opcode 0x0f 0xc6 - invalid */
1658/* Opcode 0x0f 0xc7 - invalid */
1659/* Opcode 0x0f 0xc8 - invalid */
1660/* Opcode 0x0f 0xc9 - invalid */
1661/* Opcode 0x0f 0xca - invalid */
1662/* Opcode 0x0f 0xcb - invalid */
1663/* Opcode 0x0f 0xcc - invalid */
1664/* Opcode 0x0f 0xcd - invalid */
1665/* Opcode 0x0f 0xce - invalid */
1666/* Opcode 0x0f 0xcf - invalid */
1667
1668
1669/* Opcode VEX.66.0F3A 0xd0 - invalid */
1670/* Opcode VEX.66.0F3A 0xd1 - invalid */
1671/* Opcode VEX.66.0F3A 0xd2 - invalid */
1672/* Opcode VEX.66.0F3A 0xd3 - invalid */
1673/* Opcode VEX.66.0F3A 0xd4 - invalid */
1674/* Opcode VEX.66.0F3A 0xd5 - invalid */
1675/* Opcode VEX.66.0F3A 0xd6 - invalid */
1676/* Opcode VEX.66.0F3A 0xd7 - invalid */
1677/* Opcode VEX.66.0F3A 0xd8 - invalid */
1678/* Opcode VEX.66.0F3A 0xd9 - invalid */
1679/* Opcode VEX.66.0F3A 0xda - invalid */
1680/* Opcode VEX.66.0F3A 0xdb - invalid */
1681/* Opcode VEX.66.0F3A 0xdc - invalid */
1682/* Opcode VEX.66.0F3A 0xdd - invalid */
1683/* Opcode VEX.66.0F3A 0xde - invalid */
1684/* Opcode VEX.66.0F3A 0xdf - (aeskeygenassist). */
1685FNIEMOP_STUB(iemOp_vaeskeygen_Vdq_Wdq_Ib);
1686
1687
1688/**
1689 * @opcode 0xf0
1690 * @oppfx 0xf2
1691 * @opflclass unchanged
1692 */
1693FNIEMOP_DEF(iemOp_rorx_Gy_Ey_Ib)
1694{
1695 IEMOP_MNEMONIC3(VEX_RMI, RORX, rorx, Gy, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_V_ZERO);
1696 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1697 if (IEM_IS_MODRM_REG_MODE(bRm))
1698 {
1699 /*
1700 * Register, register.
1701 */
1702 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1703 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1704 {
1705 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1706 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1707 IEM_MC_ARG(uint64_t *, pDst, 0);
1708 IEM_MC_ARG(uint64_t, uSrc1, 1);
1709 IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
1710 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
1711 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1712 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
1713 IEM_MC_ADVANCE_RIP_AND_FINISH();
1714 IEM_MC_END();
1715 }
1716 else
1717 {
1718 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1719 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1720 IEM_MC_ARG(uint32_t *, pDst, 0);
1721 IEM_MC_ARG(uint32_t, uSrc1, 1);
1722 IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
1723 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
1724 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1725 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
1726 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1727 IEM_MC_ADVANCE_RIP_AND_FINISH();
1728 IEM_MC_END();
1729 }
1730 }
1731 else
1732 {
1733 /*
1734 * Register, memory.
1735 */
1736 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1737 {
1738 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1739 IEM_MC_ARG(uint64_t *, pDst, 0);
1740 IEM_MC_ARG(uint64_t, uSrc1, 1);
1741 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1742 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1743 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1744 IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
1745 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1746 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1747 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1748 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
1749 IEM_MC_ADVANCE_RIP_AND_FINISH();
1750 IEM_MC_END();
1751 }
1752 else
1753 {
1754 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1755 IEM_MC_ARG(uint32_t *, pDst, 0);
1756 IEM_MC_ARG(uint32_t, uSrc1, 1);
1757 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1758 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1759 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1760 IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
1761 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1762 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1763 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1764 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
1765 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1766 IEM_MC_ADVANCE_RIP_AND_FINISH();
1767 IEM_MC_END();
1768 }
1769 }
1770}
1771
1772
1773/**
1774 * VEX opcode map \#3.
1775 *
1776 * @sa g_apfnThreeByte0f3a
1777 */
1778const PFNIEMOP g_apfnVexMap3[] =
1779{
1780 /* no prefix, 066h prefix f3h prefix, f2h prefix */
1781 /* 0x00 */ iemOp_InvalidNeedRMImm8, iemOp_vpermq_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1782 /* 0x01 */ iemOp_InvalidNeedRMImm8, iemOp_vpermqd_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1783 /* 0x02 */ iemOp_InvalidNeedRMImm8, iemOp_vpblendd_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1784 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1785 /* 0x04 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1786 /* 0x05 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1787 /* 0x06 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1788 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1789 /* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_vroundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1790 /* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_vroundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1791 /* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_vroundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1792 /* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_vroundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1793 /* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_vblendps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1794 /* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_vblendpd_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1795 /* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_vpblendw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1796 /* 0x0f */ iemOp_InvalidNeedRMImm8, iemOp_vpalignr_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1797
1798 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1799 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1800 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1801 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1802 /* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrb_Eb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1803 /* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrw_Ew_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1804 /* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrd_q_Ey_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1805 /* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_vextractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1806 /* 0x18 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1807 /* 0x19 */ iemOp_InvalidNeedRMImm8, iemOp_vextractf128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1808 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1809 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1810 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1811 /* 0x1d */ iemOp_InvalidNeedRMImm8, iemOp_vcvtps2ph_Wx_Vx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1812 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1813 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1814
1815 /* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1816 /* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1817 /* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1818 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1819 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1820 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1821 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1822 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1823 /* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1824 /* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1825 /* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1826 /* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1827 /* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1828 /* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1829 /* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1830 /* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1831
1832 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1833 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1834 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1835 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1836 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1837 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1838 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1839 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1840 /* 0x38 */ iemOp_InvalidNeedRMImm8, iemOp_vinserti128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1841 /* 0x39 */ iemOp_InvalidNeedRMImm8, iemOp_vextracti128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1842 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1843 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1844 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1845 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1846 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1847 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1848
1849 /* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_vdpps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1850 /* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_vdppd_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1851 /* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_vmpsadbw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1852 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1853 /* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1854 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1855 /* 0x46 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1856 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1857 /* 0x48 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1858 /* 0x49 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1859 /* 0x4a */ iemOp_InvalidNeedRMImm8, iemOp_vblendvps_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1860 /* 0x4b */ iemOp_InvalidNeedRMImm8, iemOp_vblendvpd_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1861 /* 0x4c */ iemOp_InvalidNeedRMImm8, iemOp_vpblendvb_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1862 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1863 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1864 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1865
1866 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1867 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1868 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1869 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1870 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1871 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1872 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1873 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1874 /* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1875 /* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1876 /* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1877 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1878 /* 0x5c */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1879 /* 0x5d */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1880 /* 0x5e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1881 /* 0x5f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1882
1883 /* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1884 /* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1885 /* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1886 /* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1887 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1888 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1889 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1890 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1891 /* 0x68 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1892 /* 0x69 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1893 /* 0x6a */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1894 /* 0x6b */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1895 /* 0x6c */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1896 /* 0x6d */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1897 /* 0x6e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1898 /* 0x6f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1899
1900 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1901 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1902 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1903 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1904 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1905 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1906 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1907 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1908 /* 0x78 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1909 /* 0x79 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1910 /* 0x7a */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1911 /* 0x7b */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1912 /* 0x7c */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1913 /* 0x7d */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1914 /* 0x7e */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1915 /* 0x7f */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1916
1917 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1918 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1919 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1920 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1921 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1922 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1923 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1924 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1925 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1926 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1927 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1928 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1929 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1930 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1931 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1932 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1933
1934 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1935 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1936 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1937 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1938 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1939 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1940 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1941 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1942 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1943 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1944 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1945 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1946 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1947 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1948 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1949 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1950
1951 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1952 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1953 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1954 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1955 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1956 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1957 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1958 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1959 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1960 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1961 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1962 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1963 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1964 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1965 /* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1966 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1967
1968 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1969 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1970 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1971 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1972 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1973 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1974 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1975 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1976 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1977 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1978 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1979 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1980 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1981 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1982 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1983 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1984
1985 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1986 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1987 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1988 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1989 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1990 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1991 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1992 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1993 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1994 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1995 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1996 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1997 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1998 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1999 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2000 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2001
2002 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2003 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2004 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2005 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2006 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2007 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2008 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2009 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2010 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2011 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2012 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2013 /* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2014 /* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2015 /* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2016 /* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2017 /* 0xdf */ iemOp_vaeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
2018
2019 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2020 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2021 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2022 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2023 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2024 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2025 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2026 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2027 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2028 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2029 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2030 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2031 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2032 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2033 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2034 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2035
2036 /* 0xf0 */ iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_rorx_Gy_Ey_Ib,
2037 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2038 /* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2039 /* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2040 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2041 /* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2042 /* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2043 /* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2044 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2045 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2046 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2047 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2048 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2049 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2050 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2051 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2052};
2053AssertCompile(RT_ELEMENTS(g_apfnVexMap3) == 1024);
2054
2055/** @} */
2056
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette