VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap3.cpp.h@ 104784

Last change on this file since 104784 was 104784, checked in by vboxsync, 6 months ago

VMM/IEM: Add helper to ignore the VEX.W prefix for non 64-bit code as required by some instructions, fixes some bootsector testcases, bugref:9898
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1/* $Id: IEMAllInstVexMap3.cpp.h 104784 2024-05-26 17:45:30Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4 *
5 * @remarks IEMAllInstThree0f3a.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 3
33 * @{
34 */
35
36/**
37 * Common worker for AVX2 instructions on the forms:
38 * - vpxxx xmm0, xmm1, xmm2/mem128, imm8
39 * - vpxxx ymm0, ymm1, ymm2/mem256, imm8
40 *
41 * Takes function table for function w/o implicit state parameter.
42 *
43 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
44 */
45FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF3IMM8, pImpl)
46{
47 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48 if (IEM_IS_MODRM_REG_MODE(bRm))
49 {
50 /*
51 * Register, register.
52 */
53 if (pVCpu->iem.s.uVexLength)
54 {
55 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
56 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
57 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
58 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
59 IEM_MC_PREPARE_AVX_USAGE();
60
61 IEM_MC_LOCAL(RTUINT256U, uDst);
62 IEM_MC_LOCAL(RTUINT256U, uSrc1);
63 IEM_MC_LOCAL(RTUINT256U, uSrc2);
64 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
65 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
66 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
67 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
68 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
69 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
70 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
71 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
72 IEM_MC_ADVANCE_RIP_AND_FINISH();
73 IEM_MC_END();
74 }
75 else
76 {
77 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
78 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
79 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
80 IEM_MC_ARG(PRTUINT128U, puDst, 0);
81 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
82 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
83 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
84 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
85 IEM_MC_PREPARE_AVX_USAGE();
86 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
87 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
88 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
89 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
90 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
91 IEM_MC_ADVANCE_RIP_AND_FINISH();
92 IEM_MC_END();
93 }
94 }
95 else
96 {
97 /*
98 * Register, memory.
99 */
100 if (pVCpu->iem.s.uVexLength)
101 {
102 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
103 IEM_MC_LOCAL(RTUINT256U, uDst);
104 IEM_MC_LOCAL(RTUINT256U, uSrc1);
105 IEM_MC_LOCAL(RTUINT256U, uSrc2);
106 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
107 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
108 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
109 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
110
111 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
112 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
113 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
114 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
115 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
116 IEM_MC_PREPARE_AVX_USAGE();
117
118 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
119 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
120 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
121 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
122
123 IEM_MC_ADVANCE_RIP_AND_FINISH();
124 IEM_MC_END();
125 }
126 else
127 {
128 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
129 IEM_MC_LOCAL(RTUINT128U, uSrc2);
130 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
131 IEM_MC_ARG(PRTUINT128U, puDst, 0);
132 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
133 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
134
135 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
136 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
137 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
138 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
139 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
140 IEM_MC_PREPARE_AVX_USAGE();
141
142 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
143 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
144 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
145 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
146 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
147
148 IEM_MC_ADVANCE_RIP_AND_FINISH();
149 IEM_MC_END();
150 }
151 }
152}
153
154
155/**
156 * Common worker for AVX instructions on the forms:
157 * - vpermilps/d xmm0, xmm1/mem128, imm8
158 * - vpermilps/d ymm0, ymm1/mem256, imm8
159 *
160 * Takes function table for function w/o implicit state parameter.
161 *
162 * Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operation.
163 */
164FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF2IMM8, pImpl)
165{
166 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
167 if (IEM_IS_MODRM_REG_MODE(bRm))
168 {
169 /*
170 * Register, register.
171 */
172 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
173 if (pVCpu->iem.s.uVexLength)
174 {
175 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
176 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
177 IEM_MC_LOCAL(RTUINT256U, uDst);
178 IEM_MC_LOCAL(RTUINT256U, uSrc);
179 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
180 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
181 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
182 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
183 IEM_MC_PREPARE_AVX_USAGE();
184 IEM_MC_FETCH_YREG_U256(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
185 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc, bImmArg);
186 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
187 IEM_MC_ADVANCE_RIP_AND_FINISH();
188 IEM_MC_END();
189 }
190 else
191 {
192 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
193 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
194 IEM_MC_ARG(PRTUINT128U, puDst, 0);
195 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
196 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
197 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
198 IEM_MC_PREPARE_AVX_USAGE();
199 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
200 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
201 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc, bImmArg);
202 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
203 IEM_MC_ADVANCE_RIP_AND_FINISH();
204 IEM_MC_END();
205 }
206 }
207 else
208 {
209 /*
210 * Register, memory.
211 */
212 if (pVCpu->iem.s.uVexLength)
213 {
214 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
215 IEM_MC_LOCAL(RTUINT256U, uDst);
216 IEM_MC_LOCAL(RTUINT256U, uSrc);
217 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
218 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
219 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 1);
220
221 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
222 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
223 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
224 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
225 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
226 IEM_MC_PREPARE_AVX_USAGE();
227
228 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
229 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc, bImmArg);
230 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
231
232 IEM_MC_ADVANCE_RIP_AND_FINISH();
233 IEM_MC_END();
234 }
235 else
236 {
237 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
238 IEM_MC_LOCAL(RTUINT128U, uSrc);
239 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
240 IEM_MC_ARG(PRTUINT128U, puDst, 0);
241 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
242
243 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
244 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
245 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
246 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 2);
247 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
248 IEM_MC_PREPARE_AVX_USAGE();
249
250 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
251 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
252 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc, bImmArg);
253 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
254
255 IEM_MC_ADVANCE_RIP_AND_FINISH();
256 IEM_MC_END();
257 }
258 }
259}
260
261
262/**
263 * Common worker for AVX instructions on the forms:
264 * - vblendps/d xmm0, xmm1, xmm2/mem128, imm8
265 * - vblendps/d ymm0, ymm1, ymm2/mem256, imm8
266 *
267 * Takes function table for function w/o implicit state parameter.
268 *
269 * Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operation.
270 */
271FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF3IMM8, pImpl)
272{
273 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
274 if (IEM_IS_MODRM_REG_MODE(bRm))
275 {
276 /*
277 * Register, register.
278 */
279 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
280 if (pVCpu->iem.s.uVexLength)
281 {
282 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
283 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
284 IEM_MC_LOCAL(RTUINT256U, uDst);
285 IEM_MC_LOCAL(RTUINT256U, uSrc1);
286 IEM_MC_LOCAL(RTUINT256U, uSrc2);
287 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
288 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
289 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
290 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
291 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
292 IEM_MC_PREPARE_AVX_USAGE();
293 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
294 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
295 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
296 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
297 IEM_MC_ADVANCE_RIP_AND_FINISH();
298 IEM_MC_END();
299 }
300 else
301 {
302 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
303 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
304 IEM_MC_ARG(PRTUINT128U, puDst, 0);
305 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
306 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
307 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
308 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
309 IEM_MC_PREPARE_AVX_USAGE();
310 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
311 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
312 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
313 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
314 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
315 IEM_MC_ADVANCE_RIP_AND_FINISH();
316 IEM_MC_END();
317 }
318 }
319 else
320 {
321 /*
322 * Register, memory.
323 */
324 if (pVCpu->iem.s.uVexLength)
325 {
326 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
327 IEM_MC_LOCAL(RTUINT256U, uDst);
328 IEM_MC_LOCAL(RTUINT256U, uSrc1);
329 IEM_MC_LOCAL(RTUINT256U, uSrc2);
330 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
331 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
332 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
333 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
334
335 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
336 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
337 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
338 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
339 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
340 IEM_MC_PREPARE_AVX_USAGE();
341
342 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
343 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
344 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
345 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
346
347 IEM_MC_ADVANCE_RIP_AND_FINISH();
348 IEM_MC_END();
349 }
350 else
351 {
352 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
353 IEM_MC_LOCAL(RTUINT128U, uSrc2);
354 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
355 IEM_MC_ARG(PRTUINT128U, puDst, 0);
356 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
357 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
358
359 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
360 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
361 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
362 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
363 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
364 IEM_MC_PREPARE_AVX_USAGE();
365
366 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
367 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
368 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
369 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
370 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
371
372 IEM_MC_ADVANCE_RIP_AND_FINISH();
373 IEM_MC_END();
374 }
375 }
376}
377
378
379/** Opcode VEX.66.0F3A 0x00. */
380FNIEMOP_STUB(iemOp_vpermq_Vqq_Wqq_Ib);
381/** Opcode VEX.66.0F3A 0x01. */
382FNIEMOP_STUB(iemOp_vpermpd_Vqq_Wqq_Ib);
383
384
385/** Opcode VEX.66.0F3A 0x02.
386 * AVX2,AVX2 */
387FNIEMOP_DEF(iemOp_vpblendd_Vx_Hx_Wx_Ib)
388{
389 IEMOP_MNEMONIC4(VEX_RVMI, VPBLENDD, vpblendd, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
390 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpblendd);
391 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
392}
393
394
395/* Opcode VEX.66.0F3A 0x03 - invalid */
396
397
398/** Opcode VEX.66.0F3A 0x04.
399 * AVX,AVX */
400FNIEMOP_DEF(iemOp_vpermilps_Vx_Wx_Ib)
401{
402 IEMOP_MNEMONIC3(VEX_RMI, VPERMILPS, vpermilps, Vx_WO, Wx, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_V_ZERO);
403 IEMOPMEDIAOPTF2IMM8_INIT_VARS(vpermilps);
404 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
405}
406
407
408/** Opcode VEX.66.0F3A 0x05.
409 * AVX,AVX */
410FNIEMOP_DEF(iemOp_vpermilpd_Vx_Wx_Ib)
411{
412 IEMOP_MNEMONIC3(VEX_RMI, VPERMILPD, vpermilpd, Vx_WO, Wx, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_V_ZERO);
413 IEMOPMEDIAOPTF2IMM8_INIT_VARS(vpermilpd);
414 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
415}
416
417
418/** Opcode VEX.66.0F3A 0x06 (vex only) */
419FNIEMOP_DEF(iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib)
420{
421 IEMOP_MNEMONIC4(VEX_RVMI, VPERM2F128, vperm2f128, Vqq_WO, Hqq, Wqq, Ib, DISOPTYPE_HARMLESS, 0);
422 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
423 if (IEM_IS_MODRM_REG_MODE(bRm))
424 {
425 /*
426 * Register, register.
427 */
428 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
429 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
430 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
431 IEM_MC_LOCAL(RTUINT256U, uDst);
432 IEM_MC_LOCAL(RTUINT256U, uSrc1);
433 IEM_MC_LOCAL(RTUINT256U, uSrc2);
434 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
435 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
436 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
437 IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
438 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
439 IEM_MC_PREPARE_AVX_USAGE();
440 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
441 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
442 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback),
443 puDst, puSrc1, puSrc2, bImmArg);
444 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
445 IEM_MC_ADVANCE_RIP_AND_FINISH();
446 IEM_MC_END();
447 }
448 else
449 {
450 /*
451 * Register, memory.
452 */
453 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
454 IEM_MC_LOCAL(RTUINT256U, uDst);
455 IEM_MC_LOCAL(RTUINT256U, uSrc1);
456 IEM_MC_LOCAL(RTUINT256U, uSrc2);
457 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
458 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
459 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
460 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
461
462 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
463 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
464 IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
465 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
466 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
467 IEM_MC_PREPARE_AVX_USAGE();
468
469 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
470 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
471 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback),
472 puDst, puSrc1, puSrc2, bImmArg);
473 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
474
475 IEM_MC_ADVANCE_RIP_AND_FINISH();
476 IEM_MC_END();
477 }
478}
479
480
481/* Opcode VEX.66.0F3A 0x07 - invalid */
482/** Opcode VEX.66.0F3A 0x08. */
483FNIEMOP_STUB(iemOp_vroundps_Vx_Wx_Ib);
484/** Opcode VEX.66.0F3A 0x09. */
485FNIEMOP_STUB(iemOp_vroundpd_Vx_Wx_Ib);
486/** Opcode VEX.66.0F3A 0x0a. */
487FNIEMOP_STUB(iemOp_vroundss_Vss_Wss_Ib);
488/** Opcode VEX.66.0F3A 0x0b. */
489FNIEMOP_STUB(iemOp_vroundsd_Vsd_Wsd_Ib);
490
491
492/** Opcode VEX.66.0F3A 0x0c.
493 * AVX,AVX */
494FNIEMOP_DEF(iemOp_vblendps_Vx_Hx_Wx_Ib)
495{
496 IEMOP_MNEMONIC4(VEX_RVMI, VBLENDPS, vblendps, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
497 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendps);
498 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
499}
500
501
502/** Opcode VEX.66.0F3A 0x0d.
503 * AVX,AVX */
504FNIEMOP_DEF(iemOp_vblendpd_Vx_Hx_Wx_Ib)
505{
506 IEMOP_MNEMONIC4(VEX_RVMI, VBLENDPD, vblendpd, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
507 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendpd);
508 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
509}
510
511
512/** Opcode VEX.66.0F3A 0x0e.
513 * AVX,AVX2 */
514FNIEMOP_DEF(iemOp_vpblendw_Vx_Hx_Wx_Ib)
515{
516 IEMOP_MNEMONIC4(VEX_RVMI, VPBLENDW, vpblendw, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
517 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpblendw);
518 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
519}
520
521
522/** Opcode VEX.0F3A 0x0f - invalid. */
523
524
525/** Opcode VEX.66.0F3A 0x0f.
526 * AVX,AVX2 */
527FNIEMOP_DEF(iemOp_vpalignr_Vx_Hx_Wx_Ib)
528{
529 IEMOP_MNEMONIC4(VEX_RVMI, VPALIGNR, vpalignr, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
530 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpalignr);
531 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
532}
533
534
535/* Opcode VEX.66.0F3A 0x10 - invalid */
536/* Opcode VEX.66.0F3A 0x11 - invalid */
537/* Opcode VEX.66.0F3A 0x12 - invalid */
538/* Opcode VEX.66.0F3A 0x13 - invalid */
539
540
541/** Opcode VEX.66.0F3A 0x14 - vpextrb Eb, Vdq, Ib */
542FNIEMOP_DEF(iemOp_vpextrb_Eb_Vdq_Ib)
543{
544 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRB, vpextrb, Eb, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_V_ZERO | IEMOPHINT_IGNORES_REXW);
545 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
546 if (IEM_IS_MODRM_REG_MODE(bRm))
547 {
548 /*
549 * greg32, XMM, imm8.
550 */
551 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
552 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
553 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
554 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
555 IEM_MC_PREPARE_AVX_USAGE();
556
557 IEM_MC_LOCAL(uint8_t, uValue);
558 IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/);
559 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
560 IEM_MC_ADVANCE_RIP_AND_FINISH();
561 IEM_MC_END();
562 }
563 else
564 {
565 /*
566 * [mem8], XMM, imm8.
567 */
568 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
569 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
570 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
571 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
572
573 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
574 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
575 IEM_MC_PREPARE_AVX_USAGE();
576
577 IEM_MC_LOCAL(uint8_t, uValue);
578 IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/);
579 IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
580 IEM_MC_ADVANCE_RIP_AND_FINISH();
581 IEM_MC_END();
582 }
583}
584
585
586/** Opcode VEX.66.0F3A 0x15 - vpextrw Ew, Vdq, Ib */
587FNIEMOP_DEF(iemOp_vpextrw_Ew_Vdq_Ib)
588{
589 /** @todo testcase: check that this ignores VEX.W. */
590 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRW, vpextrw, Ew_WO, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_V_ZERO | IEMOPHINT_IGNORES_REXW);
591 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
592 if (IEM_IS_MODRM_REG_MODE(bRm))
593 {
594 /*
595 * greg32, XMM, imm8.
596 */
597 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
598 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
599 IEM_MC_LOCAL(uint16_t, uValue);
600
601 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
602 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
603 IEM_MC_PREPARE_AVX_USAGE();
604
605 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7);
606 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
607 IEM_MC_ADVANCE_RIP_AND_FINISH();
608 IEM_MC_END();
609 }
610 else
611 {
612 /*
613 * [mem16], XMM, imm8.
614 */
615 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
616 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
617 IEM_MC_LOCAL(uint16_t, uValue);
618 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
619 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
620
621 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
622 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
623 IEM_MC_PREPARE_AVX_USAGE();
624
625 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7);
626 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
627 IEM_MC_ADVANCE_RIP_AND_FINISH();
628 IEM_MC_END();
629 }
630}
631
632
633/** Opcode VEX.66.0F3A 0x16 - vpextrd / vpextrq Eq / Ey, Vdq, Ib */
634FNIEMOP_DEF(iemOp_vpextrd_q_Ey_Vdq_Ib)
635{
636 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
637 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
638 {
639 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRQ, vpextrq, Eq_WO, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_W_ONE);
640 if (IEM_IS_MODRM_REG_MODE(bRm))
641 {
642 /*
643 * greg64, XMM, imm8.
644 */
645 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
646 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
647 IEM_MC_LOCAL(uint64_t, uValue);
648
649 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
650 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
651 IEM_MC_PREPARE_AVX_USAGE();
652
653 IEM_MC_FETCH_XREG_U64(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
654 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
655 IEM_MC_ADVANCE_RIP_AND_FINISH();
656 IEM_MC_END();
657 }
658 else
659 {
660 /*
661 * [mem64], XMM, imm8.
662 */
663 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
664 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
665 IEM_MC_LOCAL(uint64_t, uValue);
666 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
667 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
668
669 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
670 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
671 IEM_MC_PREPARE_AVX_USAGE();
672
673 IEM_MC_FETCH_XREG_U64(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
674 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
675 IEM_MC_ADVANCE_RIP_AND_FINISH();
676 IEM_MC_END();
677 }
678 }
679 else
680 {
681 /**
682 * @opdone
683 */
684 IEMOP_MNEMONIC3(VEX_MRI, VPEXTRD, vpextrd, Ey_WO, Vdq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_W_ZERO);
685 if (IEM_IS_MODRM_REG_MODE(bRm))
686 {
687 /*
688 * greg32, XMM, imm8.
689 */
690 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
691 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
692 IEM_MC_LOCAL(uint32_t, uValue);
693
694 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
695 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
696 IEM_MC_PREPARE_AVX_USAGE();
697
698 IEM_MC_FETCH_XREG_U32(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3);
699 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
700 IEM_MC_ADVANCE_RIP_AND_FINISH();
701 IEM_MC_END();
702 }
703 else
704 {
705 /*
706 * [mem32], XMM, imm8.
707 */
708 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
709 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
710 IEM_MC_LOCAL(uint32_t, uValue);
711 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
712 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
713
714 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
715 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
716 IEM_MC_PREPARE_AVX_USAGE();
717
718 IEM_MC_FETCH_XREG_U32(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3);
719 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
720 IEM_MC_ADVANCE_RIP_AND_FINISH();
721 IEM_MC_END();
722 }
723 }
724}
725
726
727/** Opcode VEX.66.0F3A 0x17. */
728FNIEMOP_DEF(iemOp_vextractps_Ed_Vdq_Ib)
729{
730 //IEMOP_MNEMONIC3(VEX_MRI_REG, VEXTRACTPS, vextractps, Ed, Vdq, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_VEX_L_ZERO);
731 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
732 if (IEM_IS_MODRM_REG_MODE(bRm))
733 {
734 /*
735 * greg32, XMM, imm8.
736 */
737 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
738 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
739 IEM_MC_LOCAL(uint32_t, uSrc);
740
741 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
742 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
743 IEM_MC_PREPARE_AVX_USAGE();
744
745 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/);
746 IEM_MC_STORE_GREG_U32( IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
747 IEM_MC_ADVANCE_RIP_AND_FINISH();
748 IEM_MC_END();
749 }
750 else
751 {
752 /*
753 * [mem32], XMM, imm8.
754 */
755 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
756 IEM_MC_LOCAL(uint32_t, uSrc);
757 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
758
759 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
760 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
761 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
762 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
763 IEM_MC_PREPARE_AVX_USAGE();
764
765 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/);
766 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
767 IEM_MC_ADVANCE_RIP_AND_FINISH();
768 IEM_MC_END();
769 }
770}
771
772
773/** Opcode VEX.66.0F3A 0x18 (vex only). */
774FNIEMOP_DEF(iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib)
775{
776 //IEMOP_MNEMONIC4(VEX_RMI, VINSERTF128, vinsertf128, Vx, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
777 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
778 if (IEM_IS_MODRM_REG_MODE(bRm))
779 {
780 /*
781 * Register, register.
782 */
783 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
784 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
785 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
786 IEM_MC_LOCAL(RTUINT128U, uSrc);
787
788 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
789 IEM_MC_PREPARE_AVX_USAGE();
790
791 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
792 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
793 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
794
795 IEM_MC_ADVANCE_RIP_AND_FINISH();
796 IEM_MC_END();
797 }
798 else
799 {
800 /*
801 * Register, memory.
802 */
803 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
804 IEM_MC_LOCAL(RTUINT128U, uSrc);
805 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
806
807 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
808 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
809 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
810 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
811 IEM_MC_PREPARE_AVX_USAGE();
812
813 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
814 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
815 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
816
817 IEM_MC_ADVANCE_RIP_AND_FINISH();
818 IEM_MC_END();
819 }
820}
821
822
823/** Opcode VEX.66.0F3A 0x19 (vex only). */
824FNIEMOP_DEF(iemOp_vextractf128_Wdq_Vqq_Ib)
825{
826 IEMOP_MNEMONIC3(VEX_MRI, VEXTRACTF128, vextractf128, Wdq, Vqq, Ib, DISOPTYPE_HARMLESS, 0);
827 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
828 if (IEM_IS_MODRM_REG_MODE(bRm))
829 {
830 /*
831 * Register, register.
832 */
833 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
834 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
835 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx2);
836
837 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
838 IEM_MC_PREPARE_AVX_USAGE();
839
840 IEM_MC_LOCAL(RTUINT128U, uDst);
841 IEM_MC_FETCH_YREG_U128(uDst, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
842 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_RM(pVCpu, bRm), uDst);
843
844 IEM_MC_ADVANCE_RIP_AND_FINISH();
845 IEM_MC_END();
846 }
847 else
848 {
849 /*
850 * Register, memory.
851 */
852 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
853 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
854
855 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
856 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
857 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx2);
858 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
859 IEM_MC_PREPARE_AVX_USAGE();
860
861 IEM_MC_LOCAL(RTUINT128U, uDst);
862 IEM_MC_FETCH_YREG_U128(uDst, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
863 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uDst);
864
865 IEM_MC_ADVANCE_RIP_AND_FINISH();
866 IEM_MC_END();
867 }
868}
869
870
871/* Opcode VEX.66.0F3A 0x1a - invalid */
872/* Opcode VEX.66.0F3A 0x1b - invalid */
873/* Opcode VEX.66.0F3A 0x1c - invalid */
874/** Opcode VEX.66.0F3A 0x1d (vex only). */
875FNIEMOP_STUB(iemOp_vcvtps2ph_Wx_Vx_Ib);
876/* Opcode VEX.66.0F3A 0x1e - invalid */
877/* Opcode VEX.66.0F3A 0x1f - invalid */
878
879
880/** Opcode VEX.66.0F3A 0x20. */
881FNIEMOP_DEF(iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib)
882{
883 /*IEMOP_MNEMONIC4(VEX_RMVI, VPINSRB, vpinsrb, Vdq, Hdq, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);*/ /** @todo */
884 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
885 if (IEM_IS_MODRM_REG_MODE(bRm))
886 {
887 /*
888 * Register, register.
889 */
890 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
891 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
892 IEM_MC_LOCAL(RTUINT128U, uSrc1);
893 IEM_MC_LOCAL(uint8_t, uValue);
894
895 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
896 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
897 IEM_MC_PREPARE_AVX_USAGE();
898
899 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
900 IEM_MC_FETCH_GREG_U8(uValue, IEM_GET_MODRM_RM(pVCpu, bRm));
901 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
902 IEM_MC_STORE_XREG_U8( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15, uValue);
903 IEM_MC_ADVANCE_RIP_AND_FINISH();
904 IEM_MC_END();
905 }
906 else
907 {
908 /*
909 * Register, memory.
910 */
911 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
912 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
913 IEM_MC_LOCAL(RTUINT128U, uSrc1);
914 IEM_MC_LOCAL(uint8_t, uValue);
915
916 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
917 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
918 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
919 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
920 IEM_MC_PREPARE_AVX_USAGE();
921
922 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
923 IEM_MC_FETCH_MEM_U8(uValue, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
924 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
925 IEM_MC_STORE_XREG_U8( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15, uValue);
926 IEM_MC_ADVANCE_RIP_AND_FINISH();
927 IEM_MC_END();
928 }
929}
930
931
932/** Opcode VEX.66.0F3A 0x21, */
933FNIEMOP_DEF(iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib)
934{
935 //IEMOP_MNEMONIC4(VEX_RVMR_REG, VINSERTPS, vinsertps, Vdq, Hdq, UdqMd, Ib, DISOPTYPE_X86_AVX, IEMOPHINT_VEX_L_ZERO); /// @todo
936 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
937 if (IEM_IS_MODRM_REG_MODE(bRm))
938 {
939 /*
940 * XMM, XMM, XMM, imm8.
941 */
942 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
943 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
944 IEM_MC_LOCAL(RTUINT128U, uSrc1);
945 IEM_MC_LOCAL(uint32_t, uSrc2);
946
947 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
948 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
949 IEM_MC_PREPARE_AVX_USAGE();
950
951 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
952 IEM_MC_FETCH_XREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), (bImm >> 6) & 3);
953 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
954 IEM_MC_STORE_XREG_U32( IEM_GET_MODRM_REG(pVCpu, bRm), (bImm >> 4) & 3, uSrc2);
955 IEM_MC_CLEAR_XREG_U32_MASK( IEM_GET_MODRM_REG(pVCpu, bRm), bImm);
956 IEM_MC_ADVANCE_RIP_AND_FINISH();
957 IEM_MC_END();
958 }
959 else
960 {
961 /*
962 * XMM, XMM, [mem32], imm8.
963 */
964 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
965 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
966 IEM_MC_LOCAL(RTUINT128U, uSrc1);
967 IEM_MC_LOCAL(uint32_t, uSrc2);
968
969 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
970 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
971 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
972 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
973 IEM_MC_PREPARE_AVX_USAGE();
974
975 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
976 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
977 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
978 IEM_MC_STORE_XREG_U32( IEM_GET_MODRM_REG(pVCpu, bRm), (bImm >> 4) & 3, uSrc2);
979 IEM_MC_CLEAR_XREG_U32_MASK( IEM_GET_MODRM_REG(pVCpu, bRm), bImm);
980 IEM_MC_ADVANCE_RIP_AND_FINISH();
981 IEM_MC_END();
982 }
983}
984
985
986/** Opcode VEX.66.0F3A 0x22. */
987FNIEMOP_DEF(iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib)
988{
989 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
990 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
991 {
992 /*IEMOP_MNEMONIC4(VEX_RMVI, VPINSRQ, vpinsrq, Vdq, Hdq, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);*/ /** @todo */
993 if (IEM_IS_MODRM_REG_MODE(bRm))
994 {
995 /*
996 * Register, register.
997 */
998 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
999 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1000 IEM_MC_LOCAL(RTUINT128U, uSrc1);
1001 IEM_MC_LOCAL(uint64_t, uValue);
1002
1003 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1004 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1005 IEM_MC_PREPARE_AVX_USAGE();
1006
1007 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1008 IEM_MC_FETCH_GREG_U64(uValue, IEM_GET_MODRM_RM(pVCpu, bRm));
1009 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
1010 IEM_MC_STORE_XREG_U64( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uValue);
1011 IEM_MC_ADVANCE_RIP_AND_FINISH();
1012 IEM_MC_END();
1013 }
1014 else
1015 {
1016 /*
1017 * Register, memory.
1018 */
1019 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1020 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1021 IEM_MC_LOCAL(RTUINT128U, uSrc1);
1022 IEM_MC_LOCAL(uint64_t, uValue);
1023
1024 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1025 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1026 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1027 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1028 IEM_MC_PREPARE_AVX_USAGE();
1029
1030 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1031 IEM_MC_FETCH_MEM_U64(uValue, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1032 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
1033 IEM_MC_STORE_XREG_U64( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uValue);
1034 IEM_MC_ADVANCE_RIP_AND_FINISH();
1035 IEM_MC_END();
1036 }
1037 }
1038 else
1039 {
1040 /*IEMOP_MNEMONIC4(VEX_RMVI, VPINSRD, vpinsrd, Vdq, Hdq, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);*/ /** @todo */
1041 if (IEM_IS_MODRM_REG_MODE(bRm))
1042 {
1043 /*
1044 * Register, register.
1045 */
1046 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1047 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1048 IEM_MC_LOCAL(RTUINT128U, uSrc1);
1049 IEM_MC_LOCAL(uint32_t, uValue);
1050
1051 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1052 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1053 IEM_MC_PREPARE_AVX_USAGE();
1054
1055 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1056 IEM_MC_FETCH_GREG_U32(uValue, IEM_GET_MODRM_RM(pVCpu, bRm));
1057 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
1058 IEM_MC_STORE_XREG_U32( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3, uValue);
1059 IEM_MC_ADVANCE_RIP_AND_FINISH();
1060 IEM_MC_END();
1061 }
1062 else
1063 {
1064 /*
1065 * Register, memory.
1066 */
1067 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1068 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1069 IEM_MC_LOCAL(RTUINT128U, uSrc1);
1070 IEM_MC_LOCAL(uint32_t, uValue);
1071
1072 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1073 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1074 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1075 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1076 IEM_MC_PREPARE_AVX_USAGE();
1077
1078 IEM_MC_FETCH_XREG_U128(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1079 IEM_MC_FETCH_MEM_U32(uValue, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1080 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1);
1081 IEM_MC_STORE_XREG_U32( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3, uValue);
1082 IEM_MC_ADVANCE_RIP_AND_FINISH();
1083 IEM_MC_END();
1084 }
1085 }
1086}
1087
1088
1089/* Opcode VEX.66.0F3A 0x23 - invalid */
1090/* Opcode VEX.66.0F3A 0x24 - invalid */
1091/* Opcode VEX.66.0F3A 0x25 - invalid */
1092/* Opcode VEX.66.0F3A 0x26 - invalid */
1093/* Opcode VEX.66.0F3A 0x27 - invalid */
1094/* Opcode VEX.66.0F3A 0x28 - invalid */
1095/* Opcode VEX.66.0F3A 0x29 - invalid */
1096/* Opcode VEX.66.0F3A 0x2a - invalid */
1097/* Opcode VEX.66.0F3A 0x2b - invalid */
1098/* Opcode VEX.66.0F3A 0x2c - invalid */
1099/* Opcode VEX.66.0F3A 0x2d - invalid */
1100/* Opcode VEX.66.0F3A 0x2e - invalid */
1101/* Opcode VEX.66.0F3A 0x2f - invalid */
1102
1103
1104/* Opcode VEX.66.0F3A 0x30 - invalid */
1105/* Opcode VEX.66.0F3A 0x31 - invalid */
1106/* Opcode VEX.66.0F3A 0x32 - invalid */
1107/* Opcode VEX.66.0F3A 0x33 - invalid */
1108/* Opcode VEX.66.0F3A 0x34 - invalid */
1109/* Opcode VEX.66.0F3A 0x35 - invalid */
1110/* Opcode VEX.66.0F3A 0x36 - invalid */
1111/* Opcode VEX.66.0F3A 0x37 - invalid */
1112
1113
1114/** Opcode VEX.66.0F3A 0x38 (vex only). */
1115FNIEMOP_DEF(iemOp_vinserti128_Vqq_Hqq_Wqq_Ib)
1116{
1117 //IEMOP_MNEMONIC4(VEX_RMI, VINSERTI128, vinserti128, Vx, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
1118 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1119 if (IEM_IS_MODRM_REG_MODE(bRm))
1120 {
1121 /*
1122 * Register, register.
1123 */
1124 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1125 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1126 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
1127 IEM_MC_LOCAL(RTUINT128U, uSrc);
1128
1129 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1130 IEM_MC_PREPARE_AVX_USAGE();
1131
1132 IEM_MC_FETCH_XREG_U128(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1133 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
1134 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
1135
1136 IEM_MC_ADVANCE_RIP_AND_FINISH();
1137 IEM_MC_END();
1138 }
1139 else
1140 {
1141 /*
1142 * Register, memory.
1143 */
1144 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1145 IEM_MC_LOCAL(RTUINT128U, uSrc);
1146 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1147
1148 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1149 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1150 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
1151 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1152 IEM_MC_PREPARE_AVX_USAGE();
1153
1154 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1155 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_EFFECTIVE_VVVV(pVCpu));
1156 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc);
1157
1158 IEM_MC_ADVANCE_RIP_AND_FINISH();
1159 IEM_MC_END();
1160 }
1161}
1162
1163
1164/** Opcode VEX.66.0F3A 0x39 (vex only). */
1165FNIEMOP_DEF(iemOp_vextracti128_Wdq_Vqq_Ib)
1166{
1167 IEMOP_MNEMONIC3(VEX_MRI, VEXTRACTI128, vextracti128, Wdq, Vqq, Ib, DISOPTYPE_HARMLESS, 0);
1168 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1169 if (IEM_IS_MODRM_REG_MODE(bRm))
1170 {
1171 /*
1172 * Register, register.
1173 */
1174 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1175 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1176 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx2);
1177
1178 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1179 IEM_MC_PREPARE_AVX_USAGE();
1180
1181 IEM_MC_LOCAL(RTUINT128U, uDst);
1182 IEM_MC_FETCH_YREG_U128(uDst, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
1183 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_RM(pVCpu, bRm), uDst);
1184
1185 IEM_MC_ADVANCE_RIP_AND_FINISH();
1186 IEM_MC_END();
1187 }
1188 else
1189 {
1190 /*
1191 * Register, memory.
1192 */
1193 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1194 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1195
1196 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1197 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1198 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx2);
1199 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1200 IEM_MC_PREPARE_AVX_USAGE();
1201
1202 IEM_MC_LOCAL(RTUINT128U, uDst);
1203 IEM_MC_FETCH_YREG_U128(uDst, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1);
1204 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uDst);
1205
1206 IEM_MC_ADVANCE_RIP_AND_FINISH();
1207 IEM_MC_END();
1208 }
1209}
1210
1211
1212/* Opcode VEX.66.0F3A 0x3a - invalid */
1213/* Opcode VEX.66.0F3A 0x3b - invalid */
1214/* Opcode VEX.66.0F3A 0x3c - invalid */
1215/* Opcode VEX.66.0F3A 0x3d - invalid */
1216/* Opcode VEX.66.0F3A 0x3e - invalid */
1217/* Opcode VEX.66.0F3A 0x3f - invalid */
1218
1219
1220/** Opcode VEX.66.0F3A 0x40. */
1221FNIEMOP_STUB(iemOp_vdpps_Vx_Hx_Wx_Ib);
1222/** Opcode VEX.66.0F3A 0x41, */
1223FNIEMOP_STUB(iemOp_vdppd_Vdq_Hdq_Wdq_Ib);
1224
1225
1226/** Opcode VEX.66.0F3A 0x42. */
1227FNIEMOP_DEF(iemOp_vmpsadbw_Vx_Hx_Wx_Ib)
1228{
1229 IEMOP_MNEMONIC4(VEX_RVMI, VMPSADBW, vmpsadbw, Vx_WO, Hx, Wx, Ib, DISOPTYPE_HARMLESS, 0);
1230 IEMOPMEDIAOPTF3IMM8_INIT_VARS(vmpsadbw);
1231 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
1232}
1233
1234
1235/* Opcode VEX.66.0F3A 0x43 - invalid */
1236
1237
1238/** Opcode VEX.66.0F3A 0x44. */
1239FNIEMOP_DEF(iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib)
1240{
1241 IEMOP_MNEMONIC4(VEX_RVMI, VPCLMULQDQ, vpclmulqdq, Vdq_WO, Hdq, Wdq, Id, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1242 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1243 if (IEM_IS_MODRM_REG_MODE(bRm))
1244 {
1245 /*
1246 * Register, register.
1247 */
1248 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1249 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1250 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
1251 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1252 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1253 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
1254 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1255 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1256 IEM_MC_PREPARE_AVX_USAGE();
1257 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1258 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1259 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1260 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
1261 puDst, puSrc1, puSrc2, bImmArg);
1262 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1263 IEM_MC_ADVANCE_RIP_AND_FINISH();
1264 IEM_MC_END();
1265 }
1266 else
1267 {
1268 /*
1269 * Register, memory.
1270 */
1271 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1272 IEM_MC_LOCAL(RTUINT128U, uSrc2);
1273 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1274 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1275 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1276 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
1277
1278 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1279 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1280 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3);
1281 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
1282 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1283 IEM_MC_PREPARE_AVX_USAGE();
1284
1285 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1286 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1287 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1288 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
1289 puDst, puSrc1, puSrc2, bImmArg);
1290 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1291
1292 IEM_MC_ADVANCE_RIP_AND_FINISH();
1293 IEM_MC_END();
1294 }
1295}
1296
1297
1298/* Opcode VEX.66.0F3A 0x45 - invalid */
1299
1300
1301/** Opcode VEX.66.0F3A 0x46 (vex only) */
1302FNIEMOP_DEF(iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib)
1303{
1304 IEMOP_MNEMONIC4(VEX_RVMI, VPERM2I128, vperm2i128, Vqq_WO, Hqq, Wqq, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ONE);
1305 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1306 if (IEM_IS_MODRM_REG_MODE(bRm))
1307 {
1308 /*
1309 * Register, register.
1310 */
1311 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1312 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1313 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
1314 IEM_MC_LOCAL(RTUINT256U, uDst);
1315 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1316 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1317 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1318 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1319 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1320 IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
1321 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1322 IEM_MC_PREPARE_AVX_USAGE();
1323 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1324 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1325 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback),
1326 puDst, puSrc1, puSrc2, bImmArg);
1327 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1328 IEM_MC_ADVANCE_RIP_AND_FINISH();
1329 IEM_MC_END();
1330 }
1331 else
1332 {
1333 /*
1334 * Register, memory.
1335 */
1336 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1337 IEM_MC_LOCAL(RTUINT256U, uDst);
1338 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1339 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1340 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1341 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1342 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1343 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1344
1345 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1346 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1347 IEM_MC_ARG_CONST(uint8_t, bImmArg, bImm, 3);
1348 IEMOP_HLP_DONE_VEX_DECODING_L1_EX(fAvx2);
1349 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1350 IEM_MC_PREPARE_AVX_USAGE();
1351
1352 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1353 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1354 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback),
1355 puDst, puSrc1, puSrc2, bImmArg);
1356 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1357
1358 IEM_MC_ADVANCE_RIP_AND_FINISH();
1359 IEM_MC_END();
1360 }
1361}
1362
1363
1364/* Opcode VEX.66.0F3A 0x47 - invalid */
1365/** Opcode VEX.66.0F3A 0x48 (AMD tables only). */
1366FNIEMOP_STUB(iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx);
1367/** Opcode VEX.66.0F3A 0x49 (AMD tables only). */
1368FNIEMOP_STUB(iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx);
1369
1370
1371/**
1372 * Common worker for AVX2 instructions on the forms:
1373 * - vblendvps/d xmm0, xmm1, xmm2/mem128, xmm4
1374 * - vblendvps/d ymm0, ymm1, ymm2/mem256, ymm4
1375 *
1376 * Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operations.
1377 * Additionally, it triggers \#UD if VEX.W is 1.
1378 */
1379FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
1380{
1381 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1382 if (IEM_IS_MODRM_REG_MODE(bRm))
1383 {
1384 /*
1385 * Register, register.
1386 */
1387 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1388 if (pVCpu->iem.s.uVexLength)
1389 {
1390 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1391 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1392 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1393 IEM_MC_PREPARE_AVX_USAGE();
1394 IEM_MC_LOCAL(RTUINT256U, uDst);
1395 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1396 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1397 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1398 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1399 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1400 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1401 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1402 IEM_MC_LOCAL(RTUINT256U, uSrc3);
1403 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1404 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1405 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1406 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1407 IEM_MC_ADVANCE_RIP_AND_FINISH();
1408 IEM_MC_END();
1409 }
1410 else
1411 {
1412 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1413 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1414 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1415 IEM_MC_PREPARE_AVX_USAGE();
1416 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1417 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1418 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1419 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1420 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
1421 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1422 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1423 IEM_MC_REF_XREG_U128_CONST(puSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1424 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1425 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1426 IEM_MC_ADVANCE_RIP_AND_FINISH();
1427 IEM_MC_END();
1428 }
1429 }
1430 else
1431 {
1432 /*
1433 * Register, memory.
1434 */
1435 if (pVCpu->iem.s.uVexLength)
1436 {
1437 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1438 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1439 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1440 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1441 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1442 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1443 IEM_MC_PREPARE_AVX_USAGE();
1444
1445 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1446 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1447 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1448
1449 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1450 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1451 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1452 IEM_MC_LOCAL(RTUINT256U, uSrc3);
1453 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1454 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1455 IEM_MC_LOCAL(RTUINT256U, uDst);
1456 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1457 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1458 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1459
1460 IEM_MC_ADVANCE_RIP_AND_FINISH();
1461 IEM_MC_END();
1462 }
1463 else
1464 {
1465 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1466 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1467 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1468 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1469 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1470 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1471 IEM_MC_PREPARE_AVX_USAGE();
1472
1473 IEM_MC_LOCAL(RTUINT128U, uSrc2);
1474 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
1475 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1476
1477 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1478 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1479 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1480 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1481 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1482 IEM_MC_REF_XREG_U128_CONST(puSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1483 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1484 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1485
1486 IEM_MC_ADVANCE_RIP_AND_FINISH();
1487 IEM_MC_END();
1488 }
1489 }
1490}
1491
1492
1493/** Opcode VEX.66.0F3A 0x4a (vex only).
1494 * AVX, AVX */
1495FNIEMOP_DEF(iemOp_vblendvps_Vx_Hx_Wx_Lx)
1496{
1497 IEMOP_MNEMONIC4(VEX_RVMR, VBLENDVPS, vblendvps, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0);
1498 IEMOPBLENDOP_INIT_VARS(vblendvps);
1499 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
1500}
1501
1502
1503/** Opcode VEX.66.0F3A 0x4b (vex only).
1504 * AVX, AVX */
1505FNIEMOP_DEF(iemOp_vblendvpd_Vx_Hx_Wx_Lx)
1506{
1507 IEMOP_MNEMONIC4(VEX_RVMR, VBLENDVPD, vblendvpd, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0);
1508 IEMOPBLENDOP_INIT_VARS(vblendvpd);
1509 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
1510}
1511
1512
1513/**
1514 * Common worker for AVX2 instructions on the forms:
1515 * - vpxxx xmm0, xmm1, xmm2/mem128, xmm4
1516 * - vpxxx ymm0, ymm1, ymm2/mem256, ymm4
1517 *
1518 * Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
1519 * Additionally, both VEX.W and VEX.L must be zero.
1520 */
1521FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
1522{
1523 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1524 if (IEM_IS_MODRM_REG_MODE(bRm))
1525 {
1526 /*
1527 * Register, register.
1528 */
1529 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1530 if (pVCpu->iem.s.uVexLength)
1531 {
1532 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1533 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx2);
1534 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1535 IEM_MC_PREPARE_AVX_USAGE();
1536
1537 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1538 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1539 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1540
1541 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1542 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1543 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1544
1545 IEM_MC_LOCAL(RTUINT256U, uSrc3);
1546 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1547 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1548
1549 IEM_MC_LOCAL(RTUINT256U, uDst);
1550 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1551
1552 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1553
1554 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1555 IEM_MC_ADVANCE_RIP_AND_FINISH();
1556 IEM_MC_END();
1557 }
1558 else
1559 {
1560 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1561 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1562 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1563 IEM_MC_PREPARE_AVX_USAGE();
1564 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1565 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1566 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1567 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1568 IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
1569 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1570 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1571 IEM_MC_REF_XREG_U128_CONST(puSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1572 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1573 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1574 IEM_MC_ADVANCE_RIP_AND_FINISH();
1575 IEM_MC_END();
1576 }
1577 }
1578 else
1579 {
1580 /*
1581 * Register, memory.
1582 */
1583 if (pVCpu->iem.s.uVexLength)
1584 {
1585 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1586 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1587
1588 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1589 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1590
1591 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx2);
1592 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1593 IEM_MC_PREPARE_AVX_USAGE();
1594
1595 IEM_MC_LOCAL(RTUINT256U, uSrc2);
1596 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
1597 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1598
1599 IEM_MC_LOCAL(RTUINT256U, uSrc1);
1600 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
1601 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1602
1603 IEM_MC_LOCAL(RTUINT256U, uSrc3);
1604 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
1605 IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1606
1607 IEM_MC_LOCAL(RTUINT256U, uDst);
1608 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
1609
1610 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
1611
1612 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
1613 IEM_MC_ADVANCE_RIP_AND_FINISH();
1614 IEM_MC_END();
1615 }
1616 else
1617 {
1618 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1619 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1620 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1621 uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
1622
1623 IEMOP_HLP_DONE_VEX_DECODING_W0_EX(fAvx);
1624 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1625 IEM_MC_PREPARE_AVX_USAGE();
1626
1627 IEM_MC_LOCAL(RTUINT128U, uSrc2);
1628 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
1629 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1630
1631 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1632 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1633 IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
1634 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1635 IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
1636 IEM_MC_REF_XREG_U128_CONST(puSrc3, IEM_GET_IMM8_REG(pVCpu, bOp4));
1637 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
1638 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1639
1640 IEM_MC_ADVANCE_RIP_AND_FINISH();
1641 IEM_MC_END();
1642 }
1643 }
1644}
1645
1646
1647/** Opcode VEX.66.0F3A 0x4c (vex only).
1648 * AVX, AVX2 */
1649FNIEMOP_DEF(iemOp_vpblendvb_Vx_Hx_Wx_Lx)
1650{
1651 /** @todo testcase: cover VEX.W=1 and check that it triggers \#UD on both real
1652 * and emulated hardware. */
1653 IEMOP_MNEMONIC4(VEX_RVMR, VPBLENDVB, vpblendvb, Vx_WO, Hx, Wx, Lx, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_W_ZERO);
1654 IEMOPBLENDOP_INIT_VARS(vpblendvb);
1655 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
1656}
1657
1658
1659/* Opcode VEX.66.0F3A 0x4d - invalid */
1660/* Opcode VEX.66.0F3A 0x4e - invalid */
1661/* Opcode VEX.66.0F3A 0x4f - invalid */
1662
1663
1664/* Opcode VEX.66.0F3A 0x50 - invalid */
1665/* Opcode VEX.66.0F3A 0x51 - invalid */
1666/* Opcode VEX.66.0F3A 0x52 - invalid */
1667/* Opcode VEX.66.0F3A 0x53 - invalid */
1668/* Opcode VEX.66.0F3A 0x54 - invalid */
1669/* Opcode VEX.66.0F3A 0x55 - invalid */
1670/* Opcode VEX.66.0F3A 0x56 - invalid */
1671/* Opcode VEX.66.0F3A 0x57 - invalid */
1672/* Opcode VEX.66.0F3A 0x58 - invalid */
1673/* Opcode VEX.66.0F3A 0x59 - invalid */
1674/* Opcode VEX.66.0F3A 0x5a - invalid */
1675/* Opcode VEX.66.0F3A 0x5b - invalid */
1676/** Opcode VEX.66.0F3A 0x5c (AMD tables only). */
1677FNIEMOP_STUB(iemOp_vfmaddsubps_Vx_Lx_Wx_Hx);
1678/** Opcode VEX.66.0F3A 0x5d (AMD tables only). */
1679FNIEMOP_STUB(iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx);
1680/** Opcode VEX.66.0F3A 0x5e (AMD tables only). */
1681FNIEMOP_STUB(iemOp_vfmsubaddps_Vx_Lx_Wx_Hx);
1682/** Opcode VEX.66.0F3A 0x5f (AMD tables only). */
1683FNIEMOP_STUB(iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx);
1684
1685
1686/** Opcode VEX.66.0F3A 0x60. */
1687FNIEMOP_STUB(iemOp_vpcmpestrm_Vdq_Wdq_Ib);
1688/** Opcode VEX.66.0F3A 0x61, */
1689FNIEMOP_STUB(iemOp_vpcmpestri_Vdq_Wdq_Ib);
1690/** Opcode VEX.66.0F3A 0x62. */
1691FNIEMOP_STUB(iemOp_vpcmpistrm_Vdq_Wdq_Ib);
1692/** Opcode VEX.66.0F3A 0x63*/
1693FNIEMOP_STUB(iemOp_vpcmpistri_Vdq_Wdq_Ib);
1694/* Opcode VEX.66.0F3A 0x64 - invalid */
1695/* Opcode VEX.66.0F3A 0x65 - invalid */
1696/* Opcode VEX.66.0F3A 0x66 - invalid */
1697/* Opcode VEX.66.0F3A 0x67 - invalid */
1698/** Opcode VEX.66.0F3A 0x68 (AMD tables only). */
1699FNIEMOP_STUB(iemOp_vfmaddps_Vx_Lx_Wx_Hx);
1700/** Opcode VEX.66.0F3A 0x69 (AMD tables only). */
1701FNIEMOP_STUB(iemOp_vfmaddpd_Vx_Lx_Wx_Hx);
1702/** Opcode VEX.66.0F3A 0x6a (AMD tables only). */
1703FNIEMOP_STUB(iemOp_vfmaddss_Vx_Lx_Wx_Hx);
1704/** Opcode VEX.66.0F3A 0x6b (AMD tables only). */
1705FNIEMOP_STUB(iemOp_vfmaddsd_Vx_Lx_Wx_Hx);
1706/** Opcode VEX.66.0F3A 0x6c (AMD tables only). */
1707FNIEMOP_STUB(iemOp_vfmsubps_Vx_Lx_Wx_Hx);
1708/** Opcode VEX.66.0F3A 0x6d (AMD tables only). */
1709FNIEMOP_STUB(iemOp_vfmsubpd_Vx_Lx_Wx_Hx);
1710/** Opcode VEX.66.0F3A 0x6e (AMD tables only). */
1711FNIEMOP_STUB(iemOp_vfmsubss_Vx_Lx_Wx_Hx);
1712/** Opcode VEX.66.0F3A 0x6f (AMD tables only). */
1713FNIEMOP_STUB(iemOp_vfmsubsd_Vx_Lx_Wx_Hx);
1714
1715/* Opcode VEX.66.0F3A 0x70 - invalid */
1716/* Opcode VEX.66.0F3A 0x71 - invalid */
1717/* Opcode VEX.66.0F3A 0x72 - invalid */
1718/* Opcode VEX.66.0F3A 0x73 - invalid */
1719/* Opcode VEX.66.0F3A 0x74 - invalid */
1720/* Opcode VEX.66.0F3A 0x75 - invalid */
1721/* Opcode VEX.66.0F3A 0x76 - invalid */
1722/* Opcode VEX.66.0F3A 0x77 - invalid */
1723/** Opcode VEX.66.0F3A 0x78 (AMD tables only). */
1724FNIEMOP_STUB(iemOp_vfnmaddps_Vx_Lx_Wx_Hx);
1725/** Opcode VEX.66.0F3A 0x79 (AMD tables only). */
1726FNIEMOP_STUB(iemOp_vfnmaddpd_Vx_Lx_Wx_Hx);
1727/** Opcode VEX.66.0F3A 0x7a (AMD tables only). */
1728FNIEMOP_STUB(iemOp_vfnmaddss_Vx_Lx_Wx_Hx);
1729/** Opcode VEX.66.0F3A 0x7b (AMD tables only). */
1730FNIEMOP_STUB(iemOp_vfnmaddsd_Vx_Lx_Wx_Hx);
1731/** Opcode VEX.66.0F3A 0x7c (AMD tables only). */
1732FNIEMOP_STUB(iemOp_vfnmsubps_Vx_Lx_Wx_Hx);
1733/** Opcode VEX.66.0F3A 0x7d (AMD tables only). */
1734FNIEMOP_STUB(iemOp_vfnmsubpd_Vx_Lx_Wx_Hx);
1735/** Opcode VEX.66.0F3A 0x7e (AMD tables only). */
1736FNIEMOP_STUB(iemOp_vfnmsubss_Vx_Lx_Wx_Hx);
1737/** Opcode VEX.66.0F3A 0x7f (AMD tables only). */
1738FNIEMOP_STUB(iemOp_vfnmsubsd_Vx_Lx_Wx_Hx);
1739
1740/* Opcodes 0x0f 0x80 thru 0x0f 0xb0 are unused. */
1741
1742
1743/* Opcode 0x0f 0xc0 - invalid */
1744/* Opcode 0x0f 0xc1 - invalid */
1745/* Opcode 0x0f 0xc2 - invalid */
1746/* Opcode 0x0f 0xc3 - invalid */
1747/* Opcode 0x0f 0xc4 - invalid */
1748/* Opcode 0x0f 0xc5 - invalid */
1749/* Opcode 0x0f 0xc6 - invalid */
1750/* Opcode 0x0f 0xc7 - invalid */
1751/* Opcode 0x0f 0xc8 - invalid */
1752/* Opcode 0x0f 0xc9 - invalid */
1753/* Opcode 0x0f 0xca - invalid */
1754/* Opcode 0x0f 0xcb - invalid */
1755/* Opcode 0x0f 0xcc - invalid */
1756/* Opcode 0x0f 0xcd - invalid */
1757/* Opcode 0x0f 0xce - invalid */
1758/* Opcode 0x0f 0xcf - invalid */
1759
1760
1761/* Opcode VEX.66.0F3A 0xd0 - invalid */
1762/* Opcode VEX.66.0F3A 0xd1 - invalid */
1763/* Opcode VEX.66.0F3A 0xd2 - invalid */
1764/* Opcode VEX.66.0F3A 0xd3 - invalid */
1765/* Opcode VEX.66.0F3A 0xd4 - invalid */
1766/* Opcode VEX.66.0F3A 0xd5 - invalid */
1767/* Opcode VEX.66.0F3A 0xd6 - invalid */
1768/* Opcode VEX.66.0F3A 0xd7 - invalid */
1769/* Opcode VEX.66.0F3A 0xd8 - invalid */
1770/* Opcode VEX.66.0F3A 0xd9 - invalid */
1771/* Opcode VEX.66.0F3A 0xda - invalid */
1772/* Opcode VEX.66.0F3A 0xdb - invalid */
1773/* Opcode VEX.66.0F3A 0xdc - invalid */
1774/* Opcode VEX.66.0F3A 0xdd - invalid */
1775/* Opcode VEX.66.0F3A 0xde - invalid */
1776/* Opcode VEX.66.0F3A 0xdf - (aeskeygenassist). */
1777FNIEMOP_STUB(iemOp_vaeskeygen_Vdq_Wdq_Ib);
1778
1779
1780/**
1781 * @opcode 0xf0
1782 * @oppfx 0xf2
1783 * @opflclass unchanged
1784 */
1785FNIEMOP_DEF(iemOp_rorx_Gy_Ey_Ib)
1786{
1787 IEMOP_MNEMONIC3(VEX_RMI, RORX, rorx, Gy, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO | IEMOPHINT_VEX_V_ZERO);
1788 IEMOP_HLP_IGNORE_VEX_W_PREFIX_IF_NOT_IN_64BIT();
1789 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1790 if (IEM_IS_MODRM_REG_MODE(bRm))
1791 {
1792 /*
1793 * Register, register.
1794 */
1795 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1796 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1797 {
1798 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1799 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1800 IEM_MC_ARG(uint64_t *, pDst, 0);
1801 IEM_MC_ARG(uint64_t, uSrc1, 1);
1802 IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
1803 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
1804 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1805 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
1806 IEM_MC_ADVANCE_RIP_AND_FINISH();
1807 IEM_MC_END();
1808 }
1809 else
1810 {
1811 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1812 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1813 IEM_MC_ARG(uint32_t *, pDst, 0);
1814 IEM_MC_ARG(uint32_t, uSrc1, 1);
1815 IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
1816 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
1817 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1818 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
1819 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1820 IEM_MC_ADVANCE_RIP_AND_FINISH();
1821 IEM_MC_END();
1822 }
1823 }
1824 else
1825 {
1826 /*
1827 * Register, memory.
1828 */
1829 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1830 {
1831 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
1832 IEM_MC_ARG(uint64_t *, pDst, 0);
1833 IEM_MC_ARG(uint64_t, uSrc1, 1);
1834 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1835 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1836 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1837 IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
1838 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1839 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1840 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1841 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
1842 IEM_MC_ADVANCE_RIP_AND_FINISH();
1843 IEM_MC_END();
1844 }
1845 else
1846 {
1847 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
1848 IEM_MC_ARG(uint32_t *, pDst, 0);
1849 IEM_MC_ARG(uint32_t, uSrc1, 1);
1850 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1851 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1852 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
1853 IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
1854 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fBmi2);
1855 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1856 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1857 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
1858 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm));
1859 IEM_MC_ADVANCE_RIP_AND_FINISH();
1860 IEM_MC_END();
1861 }
1862 }
1863}
1864
1865
1866/**
1867 * VEX opcode map \#3.
1868 *
1869 * @sa g_apfnThreeByte0f3a
1870 */
1871const PFNIEMOP g_apfnVexMap3[] =
1872{
1873 /* no prefix, 066h prefix f3h prefix, f2h prefix */
1874 /* 0x00 */ iemOp_InvalidNeedRMImm8, iemOp_vpermq_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1875 /* 0x01 */ iemOp_InvalidNeedRMImm8, iemOp_vpermpd_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1876 /* 0x02 */ iemOp_InvalidNeedRMImm8, iemOp_vpblendd_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1877 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1878 /* 0x04 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1879 /* 0x05 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1880 /* 0x06 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1881 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1882 /* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_vroundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1883 /* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_vroundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1884 /* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_vroundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1885 /* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_vroundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1886 /* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_vblendps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1887 /* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_vblendpd_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1888 /* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_vpblendw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1889 /* 0x0f */ iemOp_InvalidNeedRMImm8, iemOp_vpalignr_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1890
1891 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1892 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1893 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1894 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1895 /* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrb_Eb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1896 /* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrw_Ew_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1897 /* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrd_q_Ey_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1898 /* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_vextractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1899 /* 0x18 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1900 /* 0x19 */ iemOp_InvalidNeedRMImm8, iemOp_vextractf128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1901 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1902 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1903 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1904 /* 0x1d */ iemOp_InvalidNeedRMImm8, iemOp_vcvtps2ph_Wx_Vx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1905 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1906 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1907
1908 /* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1909 /* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1910 /* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1911 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1912 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1913 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1914 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1915 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1916 /* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1917 /* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1918 /* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1919 /* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1920 /* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1921 /* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1922 /* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1923 /* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1924
1925 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1926 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1927 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1928 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1929 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1930 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1931 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1932 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1933 /* 0x38 */ iemOp_InvalidNeedRMImm8, iemOp_vinserti128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1934 /* 0x39 */ iemOp_InvalidNeedRMImm8, iemOp_vextracti128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1935 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1936 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1937 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1938 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1939 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1940 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1941
1942 /* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_vdpps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1943 /* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_vdppd_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1944 /* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_vmpsadbw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1945 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1946 /* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1947 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1948 /* 0x46 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1949 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1950 /* 0x48 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1951 /* 0x49 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1952 /* 0x4a */ iemOp_InvalidNeedRMImm8, iemOp_vblendvps_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1953 /* 0x4b */ iemOp_InvalidNeedRMImm8, iemOp_vblendvpd_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1954 /* 0x4c */ iemOp_InvalidNeedRMImm8, iemOp_vpblendvb_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1955 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1956 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1957 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1958
1959 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1960 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1961 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1962 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1963 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1964 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1965 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1966 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1967 /* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1968 /* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1969 /* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1970 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1971 /* 0x5c */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1972 /* 0x5d */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1973 /* 0x5e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1974 /* 0x5f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1975
1976 /* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1977 /* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1978 /* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1979 /* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1980 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1981 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1982 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1983 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1984 /* 0x68 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1985 /* 0x69 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1986 /* 0x6a */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1987 /* 0x6b */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1988 /* 0x6c */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1989 /* 0x6d */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1990 /* 0x6e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1991 /* 0x6f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1992
1993 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1994 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1995 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1996 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1997 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1998 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1999 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2000 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2001 /* 0x78 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
2002 /* 0x79 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
2003 /* 0x7a */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
2004 /* 0x7b */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
2005 /* 0x7c */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
2006 /* 0x7d */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
2007 /* 0x7e */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
2008 /* 0x7f */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
2009
2010 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2011 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2012 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2013 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2014 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2015 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2016 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2017 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2018 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2019 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2020 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2021 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2022 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2023 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2024 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2025 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2026
2027 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2028 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2029 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2030 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2031 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2032 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2033 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2034 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2035 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2036 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2037 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2038 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2039 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2040 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2041 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2042 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2043
2044 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2045 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2046 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2047 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2048 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2049 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2050 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2051 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2052 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2053 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2054 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2055 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2056 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2057 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2058 /* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2059 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2060
2061 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2062 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2063 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2064 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2065 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2066 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2067 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2068 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2069 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2070 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2071 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2072 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2073 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2074 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2075 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2076 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2077
2078 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2079 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2080 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2081 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2082 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2083 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2084 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2085 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2086 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2087 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2088 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2089 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2090 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2091 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2092 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2093 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2094
2095 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2096 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2097 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2098 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2099 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2100 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2101 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2102 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2103 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2104 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2105 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2106 /* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2107 /* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2108 /* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2109 /* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2110 /* 0xdf */ iemOp_vaeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
2111
2112 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2113 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2114 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2115 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2116 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2117 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2118 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2119 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2120 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2121 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2122 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2123 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2124 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2125 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2126 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2127 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2128
2129 /* 0xf0 */ iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_rorx_Gy_Ey_Ib,
2130 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2131 /* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2132 /* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2133 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2134 /* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2135 /* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2136 /* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2137 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2138 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2139 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2140 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2141 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2142 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2143 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2144 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
2145};
2146AssertCompile(RT_ELEMENTS(g_apfnVexMap3) == 1024);
2147
2148/** @} */
2149
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