VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsCommon.cpp.h@ 99051

Last change on this file since 99051 was 98916, checked in by vboxsync, 21 months ago

VMM/IEM: More work on processing MC blocks, mainly related to reworking common functions for binary operations into body macros. bugref:10369
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1/* $Id: IEMAllInstructionsCommon.cpp.h 98916 2023-03-12 01:27:21Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation, Common Bits.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Defined Constants And Macros *
31*********************************************************************************************************************************/
32/** Repeats a_fn four times. For decoding tables. */
33#define IEMOP_X4(a_fn) a_fn, a_fn, a_fn, a_fn
34
35
36/*********************************************************************************************************************************
37* Global Variables *
38*********************************************************************************************************************************/
39#ifndef TST_IEM_CHECK_MC
40/** Function table for the ADD instruction. */
41IEM_STATIC const IEMOPBINSIZES g_iemAImpl_add =
42{
43 iemAImpl_add_u8, iemAImpl_add_u8_locked,
44 iemAImpl_add_u16, iemAImpl_add_u16_locked,
45 iemAImpl_add_u32, iemAImpl_add_u32_locked,
46 iemAImpl_add_u64, iemAImpl_add_u64_locked
47};
48
49/** Function table for the ADC instruction. */
50IEM_STATIC const IEMOPBINSIZES g_iemAImpl_adc =
51{
52 iemAImpl_adc_u8, iemAImpl_adc_u8_locked,
53 iemAImpl_adc_u16, iemAImpl_adc_u16_locked,
54 iemAImpl_adc_u32, iemAImpl_adc_u32_locked,
55 iemAImpl_adc_u64, iemAImpl_adc_u64_locked
56};
57
58/** Function table for the SUB instruction. */
59IEM_STATIC const IEMOPBINSIZES g_iemAImpl_sub =
60{
61 iemAImpl_sub_u8, iemAImpl_sub_u8_locked,
62 iemAImpl_sub_u16, iemAImpl_sub_u16_locked,
63 iemAImpl_sub_u32, iemAImpl_sub_u32_locked,
64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked
65};
66
67/** Function table for the SBB instruction. */
68IEM_STATIC const IEMOPBINSIZES g_iemAImpl_sbb =
69{
70 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked,
71 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked,
72 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked,
73 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked
74};
75
76/** Function table for the OR instruction. */
77IEM_STATIC const IEMOPBINSIZES g_iemAImpl_or =
78{
79 iemAImpl_or_u8, iemAImpl_or_u8_locked,
80 iemAImpl_or_u16, iemAImpl_or_u16_locked,
81 iemAImpl_or_u32, iemAImpl_or_u32_locked,
82 iemAImpl_or_u64, iemAImpl_or_u64_locked
83};
84
85/** Function table for the XOR instruction. */
86IEM_STATIC const IEMOPBINSIZES g_iemAImpl_xor =
87{
88 iemAImpl_xor_u8, iemAImpl_xor_u8_locked,
89 iemAImpl_xor_u16, iemAImpl_xor_u16_locked,
90 iemAImpl_xor_u32, iemAImpl_xor_u32_locked,
91 iemAImpl_xor_u64, iemAImpl_xor_u64_locked
92};
93
94/** Function table for the AND instruction. */
95IEM_STATIC const IEMOPBINSIZES g_iemAImpl_and =
96{
97 iemAImpl_and_u8, iemAImpl_and_u8_locked,
98 iemAImpl_and_u16, iemAImpl_and_u16_locked,
99 iemAImpl_and_u32, iemAImpl_and_u32_locked,
100 iemAImpl_and_u64, iemAImpl_and_u64_locked
101};
102
103/** Function table for the CMP instruction.
104 * @remarks Making operand order ASSUMPTIONS.
105 */
106IEM_STATIC const IEMOPBINSIZES g_iemAImpl_cmp =
107{
108 iemAImpl_cmp_u8, NULL,
109 iemAImpl_cmp_u16, NULL,
110 iemAImpl_cmp_u32, NULL,
111 iemAImpl_cmp_u64, NULL
112};
113
114/** Function table for the TEST instruction.
115 * @remarks Making operand order ASSUMPTIONS.
116 */
117IEM_STATIC const IEMOPBINSIZES g_iemAImpl_test =
118{
119 iemAImpl_test_u8, NULL,
120 iemAImpl_test_u16, NULL,
121 iemAImpl_test_u32, NULL,
122 iemAImpl_test_u64, NULL
123};
124
125
126/** Function table for the BT instruction. */
127IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bt =
128{
129 NULL, NULL,
130 iemAImpl_bt_u16, NULL,
131 iemAImpl_bt_u32, NULL,
132 iemAImpl_bt_u64, NULL
133};
134
135/** Function table for the BTC instruction. */
136IEM_STATIC const IEMOPBINSIZES g_iemAImpl_btc =
137{
138 NULL, NULL,
139 iemAImpl_btc_u16, iemAImpl_btc_u16_locked,
140 iemAImpl_btc_u32, iemAImpl_btc_u32_locked,
141 iemAImpl_btc_u64, iemAImpl_btc_u64_locked
142};
143
144/** Function table for the BTR instruction. */
145IEM_STATIC const IEMOPBINSIZES g_iemAImpl_btr =
146{
147 NULL, NULL,
148 iemAImpl_btr_u16, iemAImpl_btr_u16_locked,
149 iemAImpl_btr_u32, iemAImpl_btr_u32_locked,
150 iemAImpl_btr_u64, iemAImpl_btr_u64_locked
151};
152
153/** Function table for the BTS instruction. */
154IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bts =
155{
156 NULL, NULL,
157 iemAImpl_bts_u16, iemAImpl_bts_u16_locked,
158 iemAImpl_bts_u32, iemAImpl_bts_u32_locked,
159 iemAImpl_bts_u64, iemAImpl_bts_u64_locked
160};
161
162/** Function table for the BSF instruction. */
163IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf =
164{
165 NULL, NULL,
166 iemAImpl_bsf_u16, NULL,
167 iemAImpl_bsf_u32, NULL,
168 iemAImpl_bsf_u64, NULL
169};
170
171/** Function table for the BSF instruction, AMD EFLAGS variant. */
172IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf_amd =
173{
174 NULL, NULL,
175 iemAImpl_bsf_u16_amd, NULL,
176 iemAImpl_bsf_u32_amd, NULL,
177 iemAImpl_bsf_u64_amd, NULL
178};
179
180/** Function table for the BSF instruction, Intel EFLAGS variant. */
181IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf_intel =
182{
183 NULL, NULL,
184 iemAImpl_bsf_u16_intel, NULL,
185 iemAImpl_bsf_u32_intel, NULL,
186 iemAImpl_bsf_u64_intel, NULL
187};
188
189/** EFLAGS variation selection table for the BSF instruction. */
190IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_bsf_eflags[] =
191{
192 &g_iemAImpl_bsf,
193 &g_iemAImpl_bsf_intel,
194 &g_iemAImpl_bsf_amd,
195 &g_iemAImpl_bsf,
196};
197
198/** Function table for the BSR instruction. */
199IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr =
200{
201 NULL, NULL,
202 iemAImpl_bsr_u16, NULL,
203 iemAImpl_bsr_u32, NULL,
204 iemAImpl_bsr_u64, NULL
205};
206
207/** Function table for the BSR instruction, AMD EFLAGS variant. */
208IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr_amd =
209{
210 NULL, NULL,
211 iemAImpl_bsr_u16_amd, NULL,
212 iemAImpl_bsr_u32_amd, NULL,
213 iemAImpl_bsr_u64_amd, NULL
214};
215
216/** Function table for the BSR instruction, Intel EFLAGS variant. */
217IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr_intel =
218{
219 NULL, NULL,
220 iemAImpl_bsr_u16_intel, NULL,
221 iemAImpl_bsr_u32_intel, NULL,
222 iemAImpl_bsr_u64_intel, NULL
223};
224
225/** EFLAGS variation selection table for the BSR instruction. */
226IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_bsr_eflags[] =
227{
228 &g_iemAImpl_bsr,
229 &g_iemAImpl_bsr_intel,
230 &g_iemAImpl_bsr_amd,
231 &g_iemAImpl_bsr,
232};
233
234/** Function table for the IMUL instruction. */
235IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two =
236{
237 NULL, NULL,
238 iemAImpl_imul_two_u16, NULL,
239 iemAImpl_imul_two_u32, NULL,
240 iemAImpl_imul_two_u64, NULL
241};
242
243/** Function table for the IMUL instruction, AMD EFLAGS variant. */
244IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two_amd =
245{
246 NULL, NULL,
247 iemAImpl_imul_two_u16_amd, NULL,
248 iemAImpl_imul_two_u32_amd, NULL,
249 iemAImpl_imul_two_u64_amd, NULL
250};
251
252/** Function table for the IMUL instruction, Intel EFLAGS variant. */
253IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two_intel =
254{
255 NULL, NULL,
256 iemAImpl_imul_two_u16_intel, NULL,
257 iemAImpl_imul_two_u32_intel, NULL,
258 iemAImpl_imul_two_u64_intel, NULL
259};
260
261/** EFLAGS variation selection table for the IMUL instruction. */
262IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_imul_two_eflags[] =
263{
264 &g_iemAImpl_imul_two,
265 &g_iemAImpl_imul_two_intel,
266 &g_iemAImpl_imul_two_amd,
267 &g_iemAImpl_imul_two,
268};
269
270/** EFLAGS variation selection table for the 16-bit IMUL instruction. */
271IEM_STATIC PFNIEMAIMPLBINU16 const g_iemAImpl_imul_two_u16_eflags[] =
272{
273 iemAImpl_imul_two_u16,
274 iemAImpl_imul_two_u16_intel,
275 iemAImpl_imul_two_u16_amd,
276 iemAImpl_imul_two_u16,
277};
278
279/** EFLAGS variation selection table for the 32-bit IMUL instruction. */
280IEM_STATIC PFNIEMAIMPLBINU32 const g_iemAImpl_imul_two_u32_eflags[] =
281{
282 iemAImpl_imul_two_u32,
283 iemAImpl_imul_two_u32_intel,
284 iemAImpl_imul_two_u32_amd,
285 iemAImpl_imul_two_u32,
286};
287
288/** EFLAGS variation selection table for the 64-bit IMUL instruction. */
289IEM_STATIC PFNIEMAIMPLBINU64 const g_iemAImpl_imul_two_u64_eflags[] =
290{
291 iemAImpl_imul_two_u64,
292 iemAImpl_imul_two_u64_intel,
293 iemAImpl_imul_two_u64_amd,
294 iemAImpl_imul_two_u64,
295};
296
297/** Group 1 /r lookup table. */
298IEM_STATIC const PCIEMOPBINSIZES g_apIemImplGrp1[8] =
299{
300 &g_iemAImpl_add,
301 &g_iemAImpl_or,
302 &g_iemAImpl_adc,
303 &g_iemAImpl_sbb,
304 &g_iemAImpl_and,
305 &g_iemAImpl_sub,
306 &g_iemAImpl_xor,
307 &g_iemAImpl_cmp
308};
309
310/** Function table for the INC instruction. */
311IEM_STATIC const IEMOPUNARYSIZES g_iemAImpl_inc =
312{
313 iemAImpl_inc_u8, iemAImpl_inc_u8_locked,
314 iemAImpl_inc_u16, iemAImpl_inc_u16_locked,
315 iemAImpl_inc_u32, iemAImpl_inc_u32_locked,
316 iemAImpl_inc_u64, iemAImpl_inc_u64_locked
317};
318
319/** Function table for the DEC instruction. */
320IEM_STATIC const IEMOPUNARYSIZES g_iemAImpl_dec =
321{
322 iemAImpl_dec_u8, iemAImpl_dec_u8_locked,
323 iemAImpl_dec_u16, iemAImpl_dec_u16_locked,
324 iemAImpl_dec_u32, iemAImpl_dec_u32_locked,
325 iemAImpl_dec_u64, iemAImpl_dec_u64_locked
326};
327
328/** Function table for the NEG instruction. */
329IEM_STATIC const IEMOPUNARYSIZES g_iemAImpl_neg =
330{
331 iemAImpl_neg_u8, iemAImpl_neg_u8_locked,
332 iemAImpl_neg_u16, iemAImpl_neg_u16_locked,
333 iemAImpl_neg_u32, iemAImpl_neg_u32_locked,
334 iemAImpl_neg_u64, iemAImpl_neg_u64_locked
335};
336
337/** Function table for the NOT instruction. */
338IEM_STATIC const IEMOPUNARYSIZES g_iemAImpl_not =
339{
340 iemAImpl_not_u8, iemAImpl_not_u8_locked,
341 iemAImpl_not_u16, iemAImpl_not_u16_locked,
342 iemAImpl_not_u32, iemAImpl_not_u32_locked,
343 iemAImpl_not_u64, iemAImpl_not_u64_locked
344};
345
346
347/** Function table for the ROL instruction. */
348IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rol =
349{
350 iemAImpl_rol_u8,
351 iemAImpl_rol_u16,
352 iemAImpl_rol_u32,
353 iemAImpl_rol_u64
354};
355
356/** Function table for the ROL instruction, AMD EFLAGS variant. */
357IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rol_amd =
358{
359 iemAImpl_rol_u8_amd,
360 iemAImpl_rol_u16_amd,
361 iemAImpl_rol_u32_amd,
362 iemAImpl_rol_u64_amd
363};
364
365/** Function table for the ROL instruction, Intel EFLAGS variant. */
366IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rol_intel =
367{
368 iemAImpl_rol_u8_intel,
369 iemAImpl_rol_u16_intel,
370 iemAImpl_rol_u32_intel,
371 iemAImpl_rol_u64_intel
372};
373
374/** EFLAGS variation selection table for the ROL instruction. */
375IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_rol_eflags[] =
376{
377 &g_iemAImpl_rol,
378 &g_iemAImpl_rol_intel,
379 &g_iemAImpl_rol_amd,
380 &g_iemAImpl_rol,
381};
382
383
384/** Function table for the ROR instruction. */
385IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_ror =
386{
387 iemAImpl_ror_u8,
388 iemAImpl_ror_u16,
389 iemAImpl_ror_u32,
390 iemAImpl_ror_u64
391};
392
393/** Function table for the ROR instruction, AMD EFLAGS variant. */
394IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_ror_amd =
395{
396 iemAImpl_ror_u8_amd,
397 iemAImpl_ror_u16_amd,
398 iemAImpl_ror_u32_amd,
399 iemAImpl_ror_u64_amd
400};
401
402/** Function table for the ROR instruction, Intel EFLAGS variant. */
403IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_ror_intel =
404{
405 iemAImpl_ror_u8_intel,
406 iemAImpl_ror_u16_intel,
407 iemAImpl_ror_u32_intel,
408 iemAImpl_ror_u64_intel
409};
410
411/** EFLAGS variation selection table for the ROR instruction. */
412IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_ror_eflags[] =
413{
414 &g_iemAImpl_ror,
415 &g_iemAImpl_ror_intel,
416 &g_iemAImpl_ror_amd,
417 &g_iemAImpl_ror,
418};
419
420
421/** Function table for the RCL instruction. */
422IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcl =
423{
424 iemAImpl_rcl_u8,
425 iemAImpl_rcl_u16,
426 iemAImpl_rcl_u32,
427 iemAImpl_rcl_u64
428};
429
430/** Function table for the RCL instruction, AMD EFLAGS variant. */
431IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcl_amd =
432{
433 iemAImpl_rcl_u8_amd,
434 iemAImpl_rcl_u16_amd,
435 iemAImpl_rcl_u32_amd,
436 iemAImpl_rcl_u64_amd
437};
438
439/** Function table for the RCL instruction, Intel EFLAGS variant. */
440IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcl_intel =
441{
442 iemAImpl_rcl_u8_intel,
443 iemAImpl_rcl_u16_intel,
444 iemAImpl_rcl_u32_intel,
445 iemAImpl_rcl_u64_intel
446};
447
448/** EFLAGS variation selection table for the RCL instruction. */
449IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_rcl_eflags[] =
450{
451 &g_iemAImpl_rcl,
452 &g_iemAImpl_rcl_intel,
453 &g_iemAImpl_rcl_amd,
454 &g_iemAImpl_rcl,
455};
456
457
458/** Function table for the RCR instruction. */
459IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcr =
460{
461 iemAImpl_rcr_u8,
462 iemAImpl_rcr_u16,
463 iemAImpl_rcr_u32,
464 iemAImpl_rcr_u64
465};
466
467/** Function table for the RCR instruction, AMD EFLAGS variant. */
468IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcr_amd =
469{
470 iemAImpl_rcr_u8_amd,
471 iemAImpl_rcr_u16_amd,
472 iemAImpl_rcr_u32_amd,
473 iemAImpl_rcr_u64_amd
474};
475
476/** Function table for the RCR instruction, Intel EFLAGS variant. */
477IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcr_intel =
478{
479 iemAImpl_rcr_u8_intel,
480 iemAImpl_rcr_u16_intel,
481 iemAImpl_rcr_u32_intel,
482 iemAImpl_rcr_u64_intel
483};
484
485/** EFLAGS variation selection table for the RCR instruction. */
486IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_rcr_eflags[] =
487{
488 &g_iemAImpl_rcr,
489 &g_iemAImpl_rcr_intel,
490 &g_iemAImpl_rcr_amd,
491 &g_iemAImpl_rcr,
492};
493
494
495/** Function table for the SHL instruction. */
496IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shl =
497{
498 iemAImpl_shl_u8,
499 iemAImpl_shl_u16,
500 iemAImpl_shl_u32,
501 iemAImpl_shl_u64
502};
503
504/** Function table for the SHL instruction, AMD EFLAGS variant. */
505IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shl_amd =
506{
507 iemAImpl_shl_u8_amd,
508 iemAImpl_shl_u16_amd,
509 iemAImpl_shl_u32_amd,
510 iemAImpl_shl_u64_amd
511};
512
513/** Function table for the SHL instruction, Intel EFLAGS variant. */
514IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shl_intel =
515{
516 iemAImpl_shl_u8_intel,
517 iemAImpl_shl_u16_intel,
518 iemAImpl_shl_u32_intel,
519 iemAImpl_shl_u64_intel
520};
521
522/** EFLAGS variation selection table for the SHL instruction. */
523IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_shl_eflags[] =
524{
525 &g_iemAImpl_shl,
526 &g_iemAImpl_shl_intel,
527 &g_iemAImpl_shl_amd,
528 &g_iemAImpl_shl,
529};
530
531
532/** Function table for the SHR instruction. */
533IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shr =
534{
535 iemAImpl_shr_u8,
536 iemAImpl_shr_u16,
537 iemAImpl_shr_u32,
538 iemAImpl_shr_u64
539};
540
541/** Function table for the SHR instruction, AMD EFLAGS variant. */
542IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shr_amd =
543{
544 iemAImpl_shr_u8_amd,
545 iemAImpl_shr_u16_amd,
546 iemAImpl_shr_u32_amd,
547 iemAImpl_shr_u64_amd
548};
549
550/** Function table for the SHR instruction, Intel EFLAGS variant. */
551IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shr_intel =
552{
553 iemAImpl_shr_u8_intel,
554 iemAImpl_shr_u16_intel,
555 iemAImpl_shr_u32_intel,
556 iemAImpl_shr_u64_intel
557};
558
559/** EFLAGS variation selection table for the SHR instruction. */
560IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_shr_eflags[] =
561{
562 &g_iemAImpl_shr,
563 &g_iemAImpl_shr_intel,
564 &g_iemAImpl_shr_amd,
565 &g_iemAImpl_shr,
566};
567
568
569/** Function table for the SAR instruction. */
570IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_sar =
571{
572 iemAImpl_sar_u8,
573 iemAImpl_sar_u16,
574 iemAImpl_sar_u32,
575 iemAImpl_sar_u64
576};
577
578/** Function table for the SAR instruction, AMD EFLAGS variant. */
579IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_sar_amd =
580{
581 iemAImpl_sar_u8_amd,
582 iemAImpl_sar_u16_amd,
583 iemAImpl_sar_u32_amd,
584 iemAImpl_sar_u64_amd
585};
586
587/** Function table for the SAR instruction, Intel EFLAGS variant. */
588IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_sar_intel =
589{
590 iemAImpl_sar_u8_intel,
591 iemAImpl_sar_u16_intel,
592 iemAImpl_sar_u32_intel,
593 iemAImpl_sar_u64_intel
594};
595
596/** EFLAGS variation selection table for the SAR instruction. */
597IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_sar_eflags[] =
598{
599 &g_iemAImpl_sar,
600 &g_iemAImpl_sar_intel,
601 &g_iemAImpl_sar_amd,
602 &g_iemAImpl_sar,
603};
604
605
606/** Function table for the MUL instruction. */
607IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_mul =
608{
609 iemAImpl_mul_u8,
610 iemAImpl_mul_u16,
611 iemAImpl_mul_u32,
612 iemAImpl_mul_u64
613};
614
615/** Function table for the MUL instruction, AMD EFLAGS variation. */
616IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_mul_amd =
617{
618 iemAImpl_mul_u8_amd,
619 iemAImpl_mul_u16_amd,
620 iemAImpl_mul_u32_amd,
621 iemAImpl_mul_u64_amd
622};
623
624/** Function table for the MUL instruction, Intel EFLAGS variation. */
625IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_mul_intel =
626{
627 iemAImpl_mul_u8_intel,
628 iemAImpl_mul_u16_intel,
629 iemAImpl_mul_u32_intel,
630 iemAImpl_mul_u64_intel
631};
632
633/** EFLAGS variation selection table for the MUL instruction. */
634IEM_STATIC const IEMOPMULDIVSIZES * const g_iemAImpl_mul_eflags[] =
635{
636 &g_iemAImpl_mul,
637 &g_iemAImpl_mul_intel,
638 &g_iemAImpl_mul_amd,
639 &g_iemAImpl_mul,
640};
641
642/** EFLAGS variation selection table for the 8-bit MUL instruction. */
643IEM_STATIC PFNIEMAIMPLMULDIVU8 const g_iemAImpl_mul_u8_eflags[] =
644{
645 iemAImpl_mul_u8,
646 iemAImpl_mul_u8_intel,
647 iemAImpl_mul_u8_amd,
648 iemAImpl_mul_u8
649};
650
651
652/** Function table for the IMUL instruction working implicitly on rAX. */
653IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_imul =
654{
655 iemAImpl_imul_u8,
656 iemAImpl_imul_u16,
657 iemAImpl_imul_u32,
658 iemAImpl_imul_u64
659};
660
661/** Function table for the IMUL instruction working implicitly on rAX, AMD EFLAGS variation. */
662IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_imul_amd =
663{
664 iemAImpl_imul_u8_amd,
665 iemAImpl_imul_u16_amd,
666 iemAImpl_imul_u32_amd,
667 iemAImpl_imul_u64_amd
668};
669
670/** Function table for the IMUL instruction working implicitly on rAX, Intel EFLAGS variation. */
671IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_imul_intel =
672{
673 iemAImpl_imul_u8_intel,
674 iemAImpl_imul_u16_intel,
675 iemAImpl_imul_u32_intel,
676 iemAImpl_imul_u64_intel
677};
678
679/** EFLAGS variation selection table for the IMUL instruction. */
680IEM_STATIC const IEMOPMULDIVSIZES * const g_iemAImpl_imul_eflags[] =
681{
682 &g_iemAImpl_imul,
683 &g_iemAImpl_imul_intel,
684 &g_iemAImpl_imul_amd,
685 &g_iemAImpl_imul,
686};
687
688/** EFLAGS variation selection table for the 8-bit IMUL instruction. */
689IEM_STATIC PFNIEMAIMPLMULDIVU8 const g_iemAImpl_imul_u8_eflags[] =
690{
691 iemAImpl_imul_u8,
692 iemAImpl_imul_u8_intel,
693 iemAImpl_imul_u8_amd,
694 iemAImpl_imul_u8
695};
696
697
698/** Function table for the DIV instruction. */
699IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_div =
700{
701 iemAImpl_div_u8,
702 iemAImpl_div_u16,
703 iemAImpl_div_u32,
704 iemAImpl_div_u64
705};
706
707/** Function table for the DIV instruction, AMD EFLAGS variation. */
708IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_div_amd =
709{
710 iemAImpl_div_u8_amd,
711 iemAImpl_div_u16_amd,
712 iemAImpl_div_u32_amd,
713 iemAImpl_div_u64_amd
714};
715
716/** Function table for the DIV instruction, Intel EFLAGS variation. */
717IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_div_intel =
718{
719 iemAImpl_div_u8_intel,
720 iemAImpl_div_u16_intel,
721 iemAImpl_div_u32_intel,
722 iemAImpl_div_u64_intel
723};
724
725/** EFLAGS variation selection table for the DIV instruction. */
726IEM_STATIC const IEMOPMULDIVSIZES * const g_iemAImpl_div_eflags[] =
727{
728 &g_iemAImpl_div,
729 &g_iemAImpl_div_intel,
730 &g_iemAImpl_div_amd,
731 &g_iemAImpl_div,
732};
733
734/** EFLAGS variation selection table for the 8-bit DIV instruction. */
735IEM_STATIC PFNIEMAIMPLMULDIVU8 const g_iemAImpl_div_u8_eflags[] =
736{
737 iemAImpl_div_u8,
738 iemAImpl_div_u8_intel,
739 iemAImpl_div_u8_amd,
740 iemAImpl_div_u8
741};
742
743
744/** Function table for the IDIV instruction. */
745IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_idiv =
746{
747 iemAImpl_idiv_u8,
748 iemAImpl_idiv_u16,
749 iemAImpl_idiv_u32,
750 iemAImpl_idiv_u64
751};
752
753/** Function table for the IDIV instruction, AMD EFLAGS variation. */
754IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_idiv_amd =
755{
756 iemAImpl_idiv_u8_amd,
757 iemAImpl_idiv_u16_amd,
758 iemAImpl_idiv_u32_amd,
759 iemAImpl_idiv_u64_amd
760};
761
762/** Function table for the IDIV instruction, Intel EFLAGS variation. */
763IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_idiv_intel =
764{
765 iemAImpl_idiv_u8_intel,
766 iemAImpl_idiv_u16_intel,
767 iemAImpl_idiv_u32_intel,
768 iemAImpl_idiv_u64_intel
769};
770
771/** EFLAGS variation selection table for the IDIV instruction. */
772IEM_STATIC const IEMOPMULDIVSIZES * const g_iemAImpl_idiv_eflags[] =
773{
774 &g_iemAImpl_idiv,
775 &g_iemAImpl_idiv_intel,
776 &g_iemAImpl_idiv_amd,
777 &g_iemAImpl_idiv,
778};
779
780/** EFLAGS variation selection table for the 8-bit IDIV instruction. */
781IEM_STATIC PFNIEMAIMPLMULDIVU8 const g_iemAImpl_idiv_u8_eflags[] =
782{
783 iemAImpl_idiv_u8,
784 iemAImpl_idiv_u8_intel,
785 iemAImpl_idiv_u8_amd,
786 iemAImpl_idiv_u8
787};
788
789
790/** Function table for the SHLD instruction. */
791IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shld =
792{
793 iemAImpl_shld_u16,
794 iemAImpl_shld_u32,
795 iemAImpl_shld_u64,
796};
797
798/** Function table for the SHLD instruction, AMD EFLAGS variation. */
799IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shld_amd =
800{
801 iemAImpl_shld_u16_amd,
802 iemAImpl_shld_u32_amd,
803 iemAImpl_shld_u64_amd
804};
805
806/** Function table for the SHLD instruction, Intel EFLAGS variation. */
807IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shld_intel =
808{
809 iemAImpl_shld_u16_intel,
810 iemAImpl_shld_u32_intel,
811 iemAImpl_shld_u64_intel
812};
813
814/** EFLAGS variation selection table for the SHLD instruction. */
815IEM_STATIC const IEMOPSHIFTDBLSIZES * const g_iemAImpl_shld_eflags[] =
816{
817 &g_iemAImpl_shld,
818 &g_iemAImpl_shld_intel,
819 &g_iemAImpl_shld_amd,
820 &g_iemAImpl_shld
821};
822
823/** Function table for the SHRD instruction. */
824IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shrd =
825{
826 iemAImpl_shrd_u16,
827 iemAImpl_shrd_u32,
828 iemAImpl_shrd_u64
829};
830
831/** Function table for the SHRD instruction, AMD EFLAGS variation. */
832IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shrd_amd =
833{
834 iemAImpl_shrd_u16_amd,
835 iemAImpl_shrd_u32_amd,
836 iemAImpl_shrd_u64_amd
837};
838
839/** Function table for the SHRD instruction, Intel EFLAGS variation. */
840IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shrd_intel =
841{
842 iemAImpl_shrd_u16_intel,
843 iemAImpl_shrd_u32_intel,
844 iemAImpl_shrd_u64_intel
845};
846
847/** EFLAGS variation selection table for the SHRD instruction. */
848IEM_STATIC const IEMOPSHIFTDBLSIZES * const g_iemAImpl_shrd_eflags[] =
849{
850 &g_iemAImpl_shrd,
851 &g_iemAImpl_shrd_intel,
852 &g_iemAImpl_shrd_amd,
853 &g_iemAImpl_shrd
854};
855
856
857# ifndef IEM_WITHOUT_ASSEMBLY
858/** Function table for the VPXOR instruction */
859IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpand = { iemAImpl_vpand_u128, iemAImpl_vpand_u256 };
860/** Function table for the VPXORN instruction */
861IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpandn = { iemAImpl_vpandn_u128, iemAImpl_vpandn_u256 };
862/** Function table for the VPOR instruction */
863IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpor = { iemAImpl_vpor_u128, iemAImpl_vpor_u256 };
864/** Function table for the VPXOR instruction */
865IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpxor = { iemAImpl_vpxor_u128, iemAImpl_vpxor_u256 };
866# endif
867
868/** Function table for the VPAND instruction, software fallback. */
869IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpand_fallback = { iemAImpl_vpand_u128_fallback, iemAImpl_vpand_u256_fallback };
870/** Function table for the VPANDN instruction, software fallback. */
871IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpandn_fallback= { iemAImpl_vpandn_u128_fallback, iemAImpl_vpandn_u256_fallback };
872/** Function table for the VPOR instruction, software fallback. */
873IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpor_fallback = { iemAImpl_vpor_u128_fallback, iemAImpl_vpor_u256_fallback };
874/** Function table for the VPXOR instruction, software fallback. */
875IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpxor_fallback = { iemAImpl_vpxor_u128_fallback, iemAImpl_vpxor_u256_fallback };
876
877#endif /* !TST_IEM_CHECK_MC */
878
879
880
881/** Opcodes 0xf1, 0xd6. */
882FNIEMOP_DEF(iemOp_Invalid)
883{
884 IEMOP_MNEMONIC(Invalid, "Invalid");
885 return IEMOP_RAISE_INVALID_OPCODE();
886}
887
888
889/** Invalid with RM byte . */
890FNIEMOPRM_DEF(iemOp_InvalidWithRM)
891{
892 RT_NOREF_PV(bRm);
893 IEMOP_MNEMONIC(InvalidWithRm, "InvalidWithRM");
894 return IEMOP_RAISE_INVALID_OPCODE();
895}
896
897
898/** Invalid with RM byte where intel decodes any additional address encoding
899 * bytes. */
900FNIEMOPRM_DEF(iemOp_InvalidWithRMNeedDecode)
901{
902 IEMOP_MNEMONIC(InvalidWithRMNeedDecode, "InvalidWithRMNeedDecode");
903 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
904 {
905#ifndef TST_IEM_CHECK_MC
906 if (IEM_IS_MODRM_MEM_MODE(bRm))
907 {
908 RTGCPTR GCPtrEff;
909 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
910 if (rcStrict != VINF_SUCCESS)
911 return rcStrict;
912 }
913#endif
914 }
915 IEMOP_HLP_DONE_DECODING();
916 return IEMOP_RAISE_INVALID_OPCODE();
917}
918
919
920/** Invalid with RM byte where both AMD and Intel decodes any additional
921 * address encoding bytes. */
922FNIEMOPRM_DEF(iemOp_InvalidWithRMAllNeeded)
923{
924 IEMOP_MNEMONIC(InvalidWithRMAllNeeded, "InvalidWithRMAllNeeded");
925#ifndef TST_IEM_CHECK_MC
926 if (IEM_IS_MODRM_MEM_MODE(bRm))
927 {
928 RTGCPTR GCPtrEff;
929 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
930 if (rcStrict != VINF_SUCCESS)
931 return rcStrict;
932 }
933#endif
934 IEMOP_HLP_DONE_DECODING();
935 return IEMOP_RAISE_INVALID_OPCODE();
936}
937
938
939/** Invalid with RM byte where intel requires 8-byte immediate.
940 * Intel will also need SIB and displacement if bRm indicates memory. */
941FNIEMOPRM_DEF(iemOp_InvalidWithRMNeedImm8)
942{
943 IEMOP_MNEMONIC(InvalidWithRMNeedImm8, "InvalidWithRMNeedImm8");
944 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
945 {
946#ifndef TST_IEM_CHECK_MC
947 if (IEM_IS_MODRM_MEM_MODE(bRm))
948 {
949 RTGCPTR GCPtrEff;
950 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
951 if (rcStrict != VINF_SUCCESS)
952 return rcStrict;
953 }
954#endif
955 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8); RT_NOREF(bRm);
956 }
957 IEMOP_HLP_DONE_DECODING();
958 return IEMOP_RAISE_INVALID_OPCODE();
959}
960
961
962/** Invalid with RM byte where intel requires 8-byte immediate.
963 * Both AMD and Intel also needs SIB and displacement according to bRm. */
964FNIEMOPRM_DEF(iemOp_InvalidWithRMAllNeedImm8)
965{
966 IEMOP_MNEMONIC(InvalidWithRMAllNeedImm8, "InvalidWithRMAllNeedImm8");
967#ifndef TST_IEM_CHECK_MC
968 if (IEM_IS_MODRM_MEM_MODE(bRm))
969 {
970 RTGCPTR GCPtrEff;
971 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
972 if (rcStrict != VINF_SUCCESS)
973 return rcStrict;
974 }
975#endif
976 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8); RT_NOREF(bRm);
977 IEMOP_HLP_DONE_DECODING();
978 return IEMOP_RAISE_INVALID_OPCODE();
979}
980
981
982/** Invalid opcode where intel requires Mod R/M sequence. */
983FNIEMOP_DEF(iemOp_InvalidNeedRM)
984{
985 IEMOP_MNEMONIC(InvalidNeedRM, "InvalidNeedRM");
986 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
987 {
988 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
989#ifndef TST_IEM_CHECK_MC
990 if (IEM_IS_MODRM_MEM_MODE(bRm))
991 {
992 RTGCPTR GCPtrEff;
993 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
994 if (rcStrict != VINF_SUCCESS)
995 return rcStrict;
996 }
997#endif
998 }
999 IEMOP_HLP_DONE_DECODING();
1000 return IEMOP_RAISE_INVALID_OPCODE();
1001}
1002
1003
1004/** Invalid opcode where both AMD and Intel requires Mod R/M sequence. */
1005FNIEMOP_DEF(iemOp_InvalidAllNeedRM)
1006{
1007 IEMOP_MNEMONIC(InvalidAllNeedRM, "InvalidAllNeedRM");
1008 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
1009#ifndef TST_IEM_CHECK_MC
1010 if (IEM_IS_MODRM_MEM_MODE(bRm))
1011 {
1012 RTGCPTR GCPtrEff;
1013 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
1014 if (rcStrict != VINF_SUCCESS)
1015 return rcStrict;
1016 }
1017#endif
1018 IEMOP_HLP_DONE_DECODING();
1019 return IEMOP_RAISE_INVALID_OPCODE();
1020}
1021
1022
1023/** Invalid opcode where intel requires Mod R/M sequence and 8-byte
1024 * immediate. */
1025FNIEMOP_DEF(iemOp_InvalidNeedRMImm8)
1026{
1027 IEMOP_MNEMONIC(InvalidNeedRMImm8, "InvalidNeedRMImm8");
1028 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1029 {
1030 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
1031#ifndef TST_IEM_CHECK_MC
1032 if (IEM_IS_MODRM_MEM_MODE(bRm))
1033 {
1034 RTGCPTR GCPtrEff;
1035 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
1036 if (rcStrict != VINF_SUCCESS)
1037 return rcStrict;
1038 }
1039#endif
1040 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); RT_NOREF(bImm);
1041 }
1042 IEMOP_HLP_DONE_DECODING();
1043 return IEMOP_RAISE_INVALID_OPCODE();
1044}
1045
1046
1047/** Invalid opcode where intel requires a 3rd escape byte and a Mod R/M
1048 * sequence. */
1049FNIEMOP_DEF(iemOp_InvalidNeed3ByteEscRM)
1050{
1051 IEMOP_MNEMONIC(InvalidNeed3ByteEscRM, "InvalidNeed3ByteEscRM");
1052 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1053 {
1054 uint8_t b3rd; IEM_OPCODE_GET_NEXT_U8(&b3rd); RT_NOREF(b3rd);
1055 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
1056#ifndef TST_IEM_CHECK_MC
1057 if (IEM_IS_MODRM_MEM_MODE(bRm))
1058 {
1059 RTGCPTR GCPtrEff;
1060 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
1061 if (rcStrict != VINF_SUCCESS)
1062 return rcStrict;
1063 }
1064#endif
1065 }
1066 IEMOP_HLP_DONE_DECODING();
1067 return IEMOP_RAISE_INVALID_OPCODE();
1068}
1069
1070
1071/** Invalid opcode where intel requires a 3rd escape byte, Mod R/M sequence, and
1072 * a 8-byte immediate. */
1073FNIEMOP_DEF(iemOp_InvalidNeed3ByteEscRMImm8)
1074{
1075 IEMOP_MNEMONIC(InvalidNeed3ByteEscRMImm8, "InvalidNeed3ByteEscRMImm8");
1076 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1077 {
1078 uint8_t b3rd; IEM_OPCODE_GET_NEXT_U8(&b3rd); RT_NOREF(b3rd);
1079 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
1080#ifndef TST_IEM_CHECK_MC
1081 if (IEM_IS_MODRM_MEM_MODE(bRm))
1082 {
1083 RTGCPTR GCPtrEff;
1084 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 1, &GCPtrEff);
1085 if (rcStrict != VINF_SUCCESS)
1086 return rcStrict;
1087 }
1088#endif
1089 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); RT_NOREF(bImm);
1090 IEMOP_HLP_DONE_DECODING();
1091 }
1092 return IEMOP_RAISE_INVALID_OPCODE();
1093}
1094
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