VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsCommon.cpp.h@ 99654

Last change on this file since 99654 was 99309, checked in by vboxsync, 21 months ago

VMM/IEM: Removed some unused function tables. bugref:10369
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1/* $Id: IEMAllInstructionsCommon.cpp.h 99309 2023-04-06 02:16:17Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation, Common Bits.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Defined Constants And Macros *
31*********************************************************************************************************************************/
32/** Repeats a_fn four times. For decoding tables. */
33#define IEMOP_X4(a_fn) a_fn, a_fn, a_fn, a_fn
34
35
36/*********************************************************************************************************************************
37* Global Variables *
38*********************************************************************************************************************************/
39#ifndef TST_IEM_CHECK_MC
40
41/** Function table for the BSF instruction. */
42IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf =
43{
44 NULL, NULL,
45 iemAImpl_bsf_u16, NULL,
46 iemAImpl_bsf_u32, NULL,
47 iemAImpl_bsf_u64, NULL
48};
49
50/** Function table for the BSF instruction, AMD EFLAGS variant. */
51IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf_amd =
52{
53 NULL, NULL,
54 iemAImpl_bsf_u16_amd, NULL,
55 iemAImpl_bsf_u32_amd, NULL,
56 iemAImpl_bsf_u64_amd, NULL
57};
58
59/** Function table for the BSF instruction, Intel EFLAGS variant. */
60IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf_intel =
61{
62 NULL, NULL,
63 iemAImpl_bsf_u16_intel, NULL,
64 iemAImpl_bsf_u32_intel, NULL,
65 iemAImpl_bsf_u64_intel, NULL
66};
67
68/** EFLAGS variation selection table for the BSF instruction. */
69IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_bsf_eflags[] =
70{
71 &g_iemAImpl_bsf,
72 &g_iemAImpl_bsf_intel,
73 &g_iemAImpl_bsf_amd,
74 &g_iemAImpl_bsf,
75};
76
77/** Function table for the BSR instruction. */
78IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr =
79{
80 NULL, NULL,
81 iemAImpl_bsr_u16, NULL,
82 iemAImpl_bsr_u32, NULL,
83 iemAImpl_bsr_u64, NULL
84};
85
86/** Function table for the BSR instruction, AMD EFLAGS variant. */
87IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr_amd =
88{
89 NULL, NULL,
90 iemAImpl_bsr_u16_amd, NULL,
91 iemAImpl_bsr_u32_amd, NULL,
92 iemAImpl_bsr_u64_amd, NULL
93};
94
95/** Function table for the BSR instruction, Intel EFLAGS variant. */
96IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr_intel =
97{
98 NULL, NULL,
99 iemAImpl_bsr_u16_intel, NULL,
100 iemAImpl_bsr_u32_intel, NULL,
101 iemAImpl_bsr_u64_intel, NULL
102};
103
104/** EFLAGS variation selection table for the BSR instruction. */
105IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_bsr_eflags[] =
106{
107 &g_iemAImpl_bsr,
108 &g_iemAImpl_bsr_intel,
109 &g_iemAImpl_bsr_amd,
110 &g_iemAImpl_bsr,
111};
112
113/** Function table for the IMUL instruction. */
114IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two =
115{
116 NULL, NULL,
117 iemAImpl_imul_two_u16, NULL,
118 iemAImpl_imul_two_u32, NULL,
119 iemAImpl_imul_two_u64, NULL
120};
121
122/** Function table for the IMUL instruction, AMD EFLAGS variant. */
123IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two_amd =
124{
125 NULL, NULL,
126 iemAImpl_imul_two_u16_amd, NULL,
127 iemAImpl_imul_two_u32_amd, NULL,
128 iemAImpl_imul_two_u64_amd, NULL
129};
130
131/** Function table for the IMUL instruction, Intel EFLAGS variant. */
132IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two_intel =
133{
134 NULL, NULL,
135 iemAImpl_imul_two_u16_intel, NULL,
136 iemAImpl_imul_two_u32_intel, NULL,
137 iemAImpl_imul_two_u64_intel, NULL
138};
139
140/** EFLAGS variation selection table for the IMUL instruction. */
141IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_imul_two_eflags[] =
142{
143 &g_iemAImpl_imul_two,
144 &g_iemAImpl_imul_two_intel,
145 &g_iemAImpl_imul_two_amd,
146 &g_iemAImpl_imul_two,
147};
148
149/** EFLAGS variation selection table for the 16-bit IMUL instruction. */
150IEM_STATIC PFNIEMAIMPLBINU16 const g_iemAImpl_imul_two_u16_eflags[] =
151{
152 iemAImpl_imul_two_u16,
153 iemAImpl_imul_two_u16_intel,
154 iemAImpl_imul_two_u16_amd,
155 iemAImpl_imul_two_u16,
156};
157
158/** EFLAGS variation selection table for the 32-bit IMUL instruction. */
159IEM_STATIC PFNIEMAIMPLBINU32 const g_iemAImpl_imul_two_u32_eflags[] =
160{
161 iemAImpl_imul_two_u32,
162 iemAImpl_imul_two_u32_intel,
163 iemAImpl_imul_two_u32_amd,
164 iemAImpl_imul_two_u32,
165};
166
167/** EFLAGS variation selection table for the 64-bit IMUL instruction. */
168IEM_STATIC PFNIEMAIMPLBINU64 const g_iemAImpl_imul_two_u64_eflags[] =
169{
170 iemAImpl_imul_two_u64,
171 iemAImpl_imul_two_u64_intel,
172 iemAImpl_imul_two_u64_amd,
173 iemAImpl_imul_two_u64,
174};
175
176/** Function table for the ROL instruction. */
177IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rol =
178{
179 iemAImpl_rol_u8,
180 iemAImpl_rol_u16,
181 iemAImpl_rol_u32,
182 iemAImpl_rol_u64
183};
184
185/** Function table for the ROL instruction, AMD EFLAGS variant. */
186IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rol_amd =
187{
188 iemAImpl_rol_u8_amd,
189 iemAImpl_rol_u16_amd,
190 iemAImpl_rol_u32_amd,
191 iemAImpl_rol_u64_amd
192};
193
194/** Function table for the ROL instruction, Intel EFLAGS variant. */
195IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rol_intel =
196{
197 iemAImpl_rol_u8_intel,
198 iemAImpl_rol_u16_intel,
199 iemAImpl_rol_u32_intel,
200 iemAImpl_rol_u64_intel
201};
202
203/** EFLAGS variation selection table for the ROL instruction. */
204IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_rol_eflags[] =
205{
206 &g_iemAImpl_rol,
207 &g_iemAImpl_rol_intel,
208 &g_iemAImpl_rol_amd,
209 &g_iemAImpl_rol,
210};
211
212
213/** Function table for the ROR instruction. */
214IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_ror =
215{
216 iemAImpl_ror_u8,
217 iemAImpl_ror_u16,
218 iemAImpl_ror_u32,
219 iemAImpl_ror_u64
220};
221
222/** Function table for the ROR instruction, AMD EFLAGS variant. */
223IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_ror_amd =
224{
225 iemAImpl_ror_u8_amd,
226 iemAImpl_ror_u16_amd,
227 iemAImpl_ror_u32_amd,
228 iemAImpl_ror_u64_amd
229};
230
231/** Function table for the ROR instruction, Intel EFLAGS variant. */
232IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_ror_intel =
233{
234 iemAImpl_ror_u8_intel,
235 iemAImpl_ror_u16_intel,
236 iemAImpl_ror_u32_intel,
237 iemAImpl_ror_u64_intel
238};
239
240/** EFLAGS variation selection table for the ROR instruction. */
241IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_ror_eflags[] =
242{
243 &g_iemAImpl_ror,
244 &g_iemAImpl_ror_intel,
245 &g_iemAImpl_ror_amd,
246 &g_iemAImpl_ror,
247};
248
249
250/** Function table for the RCL instruction. */
251IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcl =
252{
253 iemAImpl_rcl_u8,
254 iemAImpl_rcl_u16,
255 iemAImpl_rcl_u32,
256 iemAImpl_rcl_u64
257};
258
259/** Function table for the RCL instruction, AMD EFLAGS variant. */
260IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcl_amd =
261{
262 iemAImpl_rcl_u8_amd,
263 iemAImpl_rcl_u16_amd,
264 iemAImpl_rcl_u32_amd,
265 iemAImpl_rcl_u64_amd
266};
267
268/** Function table for the RCL instruction, Intel EFLAGS variant. */
269IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcl_intel =
270{
271 iemAImpl_rcl_u8_intel,
272 iemAImpl_rcl_u16_intel,
273 iemAImpl_rcl_u32_intel,
274 iemAImpl_rcl_u64_intel
275};
276
277/** EFLAGS variation selection table for the RCL instruction. */
278IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_rcl_eflags[] =
279{
280 &g_iemAImpl_rcl,
281 &g_iemAImpl_rcl_intel,
282 &g_iemAImpl_rcl_amd,
283 &g_iemAImpl_rcl,
284};
285
286
287/** Function table for the RCR instruction. */
288IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcr =
289{
290 iemAImpl_rcr_u8,
291 iemAImpl_rcr_u16,
292 iemAImpl_rcr_u32,
293 iemAImpl_rcr_u64
294};
295
296/** Function table for the RCR instruction, AMD EFLAGS variant. */
297IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcr_amd =
298{
299 iemAImpl_rcr_u8_amd,
300 iemAImpl_rcr_u16_amd,
301 iemAImpl_rcr_u32_amd,
302 iemAImpl_rcr_u64_amd
303};
304
305/** Function table for the RCR instruction, Intel EFLAGS variant. */
306IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_rcr_intel =
307{
308 iemAImpl_rcr_u8_intel,
309 iemAImpl_rcr_u16_intel,
310 iemAImpl_rcr_u32_intel,
311 iemAImpl_rcr_u64_intel
312};
313
314/** EFLAGS variation selection table for the RCR instruction. */
315IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_rcr_eflags[] =
316{
317 &g_iemAImpl_rcr,
318 &g_iemAImpl_rcr_intel,
319 &g_iemAImpl_rcr_amd,
320 &g_iemAImpl_rcr,
321};
322
323
324/** Function table for the SHL instruction. */
325IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shl =
326{
327 iemAImpl_shl_u8,
328 iemAImpl_shl_u16,
329 iemAImpl_shl_u32,
330 iemAImpl_shl_u64
331};
332
333/** Function table for the SHL instruction, AMD EFLAGS variant. */
334IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shl_amd =
335{
336 iemAImpl_shl_u8_amd,
337 iemAImpl_shl_u16_amd,
338 iemAImpl_shl_u32_amd,
339 iemAImpl_shl_u64_amd
340};
341
342/** Function table for the SHL instruction, Intel EFLAGS variant. */
343IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shl_intel =
344{
345 iemAImpl_shl_u8_intel,
346 iemAImpl_shl_u16_intel,
347 iemAImpl_shl_u32_intel,
348 iemAImpl_shl_u64_intel
349};
350
351/** EFLAGS variation selection table for the SHL instruction. */
352IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_shl_eflags[] =
353{
354 &g_iemAImpl_shl,
355 &g_iemAImpl_shl_intel,
356 &g_iemAImpl_shl_amd,
357 &g_iemAImpl_shl,
358};
359
360
361/** Function table for the SHR instruction. */
362IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shr =
363{
364 iemAImpl_shr_u8,
365 iemAImpl_shr_u16,
366 iemAImpl_shr_u32,
367 iemAImpl_shr_u64
368};
369
370/** Function table for the SHR instruction, AMD EFLAGS variant. */
371IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shr_amd =
372{
373 iemAImpl_shr_u8_amd,
374 iemAImpl_shr_u16_amd,
375 iemAImpl_shr_u32_amd,
376 iemAImpl_shr_u64_amd
377};
378
379/** Function table for the SHR instruction, Intel EFLAGS variant. */
380IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_shr_intel =
381{
382 iemAImpl_shr_u8_intel,
383 iemAImpl_shr_u16_intel,
384 iemAImpl_shr_u32_intel,
385 iemAImpl_shr_u64_intel
386};
387
388/** EFLAGS variation selection table for the SHR instruction. */
389IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_shr_eflags[] =
390{
391 &g_iemAImpl_shr,
392 &g_iemAImpl_shr_intel,
393 &g_iemAImpl_shr_amd,
394 &g_iemAImpl_shr,
395};
396
397
398/** Function table for the SAR instruction. */
399IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_sar =
400{
401 iemAImpl_sar_u8,
402 iemAImpl_sar_u16,
403 iemAImpl_sar_u32,
404 iemAImpl_sar_u64
405};
406
407/** Function table for the SAR instruction, AMD EFLAGS variant. */
408IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_sar_amd =
409{
410 iemAImpl_sar_u8_amd,
411 iemAImpl_sar_u16_amd,
412 iemAImpl_sar_u32_amd,
413 iemAImpl_sar_u64_amd
414};
415
416/** Function table for the SAR instruction, Intel EFLAGS variant. */
417IEM_STATIC const IEMOPSHIFTSIZES g_iemAImpl_sar_intel =
418{
419 iemAImpl_sar_u8_intel,
420 iemAImpl_sar_u16_intel,
421 iemAImpl_sar_u32_intel,
422 iemAImpl_sar_u64_intel
423};
424
425/** EFLAGS variation selection table for the SAR instruction. */
426IEM_STATIC const IEMOPSHIFTSIZES * const g_iemAImpl_sar_eflags[] =
427{
428 &g_iemAImpl_sar,
429 &g_iemAImpl_sar_intel,
430 &g_iemAImpl_sar_amd,
431 &g_iemAImpl_sar,
432};
433
434
435/** Function table for the MUL instruction. */
436IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_mul =
437{
438 iemAImpl_mul_u8,
439 iemAImpl_mul_u16,
440 iemAImpl_mul_u32,
441 iemAImpl_mul_u64
442};
443
444/** Function table for the MUL instruction, AMD EFLAGS variation. */
445IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_mul_amd =
446{
447 iemAImpl_mul_u8_amd,
448 iemAImpl_mul_u16_amd,
449 iemAImpl_mul_u32_amd,
450 iemAImpl_mul_u64_amd
451};
452
453/** Function table for the MUL instruction, Intel EFLAGS variation. */
454IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_mul_intel =
455{
456 iemAImpl_mul_u8_intel,
457 iemAImpl_mul_u16_intel,
458 iemAImpl_mul_u32_intel,
459 iemAImpl_mul_u64_intel
460};
461
462/** EFLAGS variation selection table for the MUL instruction. */
463IEM_STATIC const IEMOPMULDIVSIZES * const g_iemAImpl_mul_eflags[] =
464{
465 &g_iemAImpl_mul,
466 &g_iemAImpl_mul_intel,
467 &g_iemAImpl_mul_amd,
468 &g_iemAImpl_mul,
469};
470
471/** EFLAGS variation selection table for the 8-bit MUL instruction. */
472IEM_STATIC PFNIEMAIMPLMULDIVU8 const g_iemAImpl_mul_u8_eflags[] =
473{
474 iemAImpl_mul_u8,
475 iemAImpl_mul_u8_intel,
476 iemAImpl_mul_u8_amd,
477 iemAImpl_mul_u8
478};
479
480
481/** Function table for the IMUL instruction working implicitly on rAX. */
482IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_imul =
483{
484 iemAImpl_imul_u8,
485 iemAImpl_imul_u16,
486 iemAImpl_imul_u32,
487 iemAImpl_imul_u64
488};
489
490/** Function table for the IMUL instruction working implicitly on rAX, AMD EFLAGS variation. */
491IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_imul_amd =
492{
493 iemAImpl_imul_u8_amd,
494 iemAImpl_imul_u16_amd,
495 iemAImpl_imul_u32_amd,
496 iemAImpl_imul_u64_amd
497};
498
499/** Function table for the IMUL instruction working implicitly on rAX, Intel EFLAGS variation. */
500IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_imul_intel =
501{
502 iemAImpl_imul_u8_intel,
503 iemAImpl_imul_u16_intel,
504 iemAImpl_imul_u32_intel,
505 iemAImpl_imul_u64_intel
506};
507
508/** EFLAGS variation selection table for the IMUL instruction. */
509IEM_STATIC const IEMOPMULDIVSIZES * const g_iemAImpl_imul_eflags[] =
510{
511 &g_iemAImpl_imul,
512 &g_iemAImpl_imul_intel,
513 &g_iemAImpl_imul_amd,
514 &g_iemAImpl_imul,
515};
516
517/** EFLAGS variation selection table for the 8-bit IMUL instruction. */
518IEM_STATIC PFNIEMAIMPLMULDIVU8 const g_iemAImpl_imul_u8_eflags[] =
519{
520 iemAImpl_imul_u8,
521 iemAImpl_imul_u8_intel,
522 iemAImpl_imul_u8_amd,
523 iemAImpl_imul_u8
524};
525
526
527/** Function table for the DIV instruction. */
528IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_div =
529{
530 iemAImpl_div_u8,
531 iemAImpl_div_u16,
532 iemAImpl_div_u32,
533 iemAImpl_div_u64
534};
535
536/** Function table for the DIV instruction, AMD EFLAGS variation. */
537IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_div_amd =
538{
539 iemAImpl_div_u8_amd,
540 iemAImpl_div_u16_amd,
541 iemAImpl_div_u32_amd,
542 iemAImpl_div_u64_amd
543};
544
545/** Function table for the DIV instruction, Intel EFLAGS variation. */
546IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_div_intel =
547{
548 iemAImpl_div_u8_intel,
549 iemAImpl_div_u16_intel,
550 iemAImpl_div_u32_intel,
551 iemAImpl_div_u64_intel
552};
553
554/** EFLAGS variation selection table for the DIV instruction. */
555IEM_STATIC const IEMOPMULDIVSIZES * const g_iemAImpl_div_eflags[] =
556{
557 &g_iemAImpl_div,
558 &g_iemAImpl_div_intel,
559 &g_iemAImpl_div_amd,
560 &g_iemAImpl_div,
561};
562
563/** EFLAGS variation selection table for the 8-bit DIV instruction. */
564IEM_STATIC PFNIEMAIMPLMULDIVU8 const g_iemAImpl_div_u8_eflags[] =
565{
566 iemAImpl_div_u8,
567 iemAImpl_div_u8_intel,
568 iemAImpl_div_u8_amd,
569 iemAImpl_div_u8
570};
571
572
573/** Function table for the IDIV instruction. */
574IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_idiv =
575{
576 iemAImpl_idiv_u8,
577 iemAImpl_idiv_u16,
578 iemAImpl_idiv_u32,
579 iemAImpl_idiv_u64
580};
581
582/** Function table for the IDIV instruction, AMD EFLAGS variation. */
583IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_idiv_amd =
584{
585 iemAImpl_idiv_u8_amd,
586 iemAImpl_idiv_u16_amd,
587 iemAImpl_idiv_u32_amd,
588 iemAImpl_idiv_u64_amd
589};
590
591/** Function table for the IDIV instruction, Intel EFLAGS variation. */
592IEM_STATIC const IEMOPMULDIVSIZES g_iemAImpl_idiv_intel =
593{
594 iemAImpl_idiv_u8_intel,
595 iemAImpl_idiv_u16_intel,
596 iemAImpl_idiv_u32_intel,
597 iemAImpl_idiv_u64_intel
598};
599
600/** EFLAGS variation selection table for the IDIV instruction. */
601IEM_STATIC const IEMOPMULDIVSIZES * const g_iemAImpl_idiv_eflags[] =
602{
603 &g_iemAImpl_idiv,
604 &g_iemAImpl_idiv_intel,
605 &g_iemAImpl_idiv_amd,
606 &g_iemAImpl_idiv,
607};
608
609/** EFLAGS variation selection table for the 8-bit IDIV instruction. */
610IEM_STATIC PFNIEMAIMPLMULDIVU8 const g_iemAImpl_idiv_u8_eflags[] =
611{
612 iemAImpl_idiv_u8,
613 iemAImpl_idiv_u8_intel,
614 iemAImpl_idiv_u8_amd,
615 iemAImpl_idiv_u8
616};
617
618
619/** Function table for the SHLD instruction. */
620IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shld =
621{
622 iemAImpl_shld_u16,
623 iemAImpl_shld_u32,
624 iemAImpl_shld_u64,
625};
626
627/** Function table for the SHLD instruction, AMD EFLAGS variation. */
628IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shld_amd =
629{
630 iemAImpl_shld_u16_amd,
631 iemAImpl_shld_u32_amd,
632 iemAImpl_shld_u64_amd
633};
634
635/** Function table for the SHLD instruction, Intel EFLAGS variation. */
636IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shld_intel =
637{
638 iemAImpl_shld_u16_intel,
639 iemAImpl_shld_u32_intel,
640 iemAImpl_shld_u64_intel
641};
642
643/** EFLAGS variation selection table for the SHLD instruction. */
644IEM_STATIC const IEMOPSHIFTDBLSIZES * const g_iemAImpl_shld_eflags[] =
645{
646 &g_iemAImpl_shld,
647 &g_iemAImpl_shld_intel,
648 &g_iemAImpl_shld_amd,
649 &g_iemAImpl_shld
650};
651
652/** Function table for the SHRD instruction. */
653IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shrd =
654{
655 iemAImpl_shrd_u16,
656 iemAImpl_shrd_u32,
657 iemAImpl_shrd_u64
658};
659
660/** Function table for the SHRD instruction, AMD EFLAGS variation. */
661IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shrd_amd =
662{
663 iemAImpl_shrd_u16_amd,
664 iemAImpl_shrd_u32_amd,
665 iemAImpl_shrd_u64_amd
666};
667
668/** Function table for the SHRD instruction, Intel EFLAGS variation. */
669IEM_STATIC const IEMOPSHIFTDBLSIZES g_iemAImpl_shrd_intel =
670{
671 iemAImpl_shrd_u16_intel,
672 iemAImpl_shrd_u32_intel,
673 iemAImpl_shrd_u64_intel
674};
675
676/** EFLAGS variation selection table for the SHRD instruction. */
677IEM_STATIC const IEMOPSHIFTDBLSIZES * const g_iemAImpl_shrd_eflags[] =
678{
679 &g_iemAImpl_shrd,
680 &g_iemAImpl_shrd_intel,
681 &g_iemAImpl_shrd_amd,
682 &g_iemAImpl_shrd
683};
684
685
686# ifndef IEM_WITHOUT_ASSEMBLY
687/** Function table for the VPXOR instruction */
688IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpand = { iemAImpl_vpand_u128, iemAImpl_vpand_u256 };
689/** Function table for the VPXORN instruction */
690IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpandn = { iemAImpl_vpandn_u128, iemAImpl_vpandn_u256 };
691/** Function table for the VPOR instruction */
692IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpor = { iemAImpl_vpor_u128, iemAImpl_vpor_u256 };
693/** Function table for the VPXOR instruction */
694IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpxor = { iemAImpl_vpxor_u128, iemAImpl_vpxor_u256 };
695# endif
696
697/** Function table for the VPAND instruction, software fallback. */
698IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpand_fallback = { iemAImpl_vpand_u128_fallback, iemAImpl_vpand_u256_fallback };
699/** Function table for the VPANDN instruction, software fallback. */
700IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpandn_fallback= { iemAImpl_vpandn_u128_fallback, iemAImpl_vpandn_u256_fallback };
701/** Function table for the VPOR instruction, software fallback. */
702IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpor_fallback = { iemAImpl_vpor_u128_fallback, iemAImpl_vpor_u256_fallback };
703/** Function table for the VPXOR instruction, software fallback. */
704IEM_STATIC const IEMOPMEDIAF3 g_iemAImpl_vpxor_fallback = { iemAImpl_vpxor_u128_fallback, iemAImpl_vpxor_u256_fallback };
705
706#endif /* !TST_IEM_CHECK_MC */
707
708
709
710/** Opcodes 0xf1, 0xd6. */
711FNIEMOP_DEF(iemOp_Invalid)
712{
713 IEMOP_MNEMONIC(Invalid, "Invalid");
714 return IEMOP_RAISE_INVALID_OPCODE();
715}
716
717
718/** Invalid with RM byte . */
719FNIEMOPRM_DEF(iemOp_InvalidWithRM)
720{
721 RT_NOREF_PV(bRm);
722 IEMOP_MNEMONIC(InvalidWithRm, "InvalidWithRM");
723 return IEMOP_RAISE_INVALID_OPCODE();
724}
725
726
727/** Invalid with RM byte where intel decodes any additional address encoding
728 * bytes. */
729FNIEMOPRM_DEF(iemOp_InvalidWithRMNeedDecode)
730{
731 IEMOP_MNEMONIC(InvalidWithRMNeedDecode, "InvalidWithRMNeedDecode");
732 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
733 {
734#ifndef TST_IEM_CHECK_MC
735 if (IEM_IS_MODRM_MEM_MODE(bRm))
736 {
737 RTGCPTR GCPtrEff;
738 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
739 if (rcStrict != VINF_SUCCESS)
740 return rcStrict;
741 }
742#endif
743 }
744 IEMOP_HLP_DONE_DECODING();
745 return IEMOP_RAISE_INVALID_OPCODE();
746}
747
748
749/** Invalid with RM byte where both AMD and Intel decodes any additional
750 * address encoding bytes. */
751FNIEMOPRM_DEF(iemOp_InvalidWithRMAllNeeded)
752{
753 IEMOP_MNEMONIC(InvalidWithRMAllNeeded, "InvalidWithRMAllNeeded");
754#ifndef TST_IEM_CHECK_MC
755 if (IEM_IS_MODRM_MEM_MODE(bRm))
756 {
757 RTGCPTR GCPtrEff;
758 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
759 if (rcStrict != VINF_SUCCESS)
760 return rcStrict;
761 }
762#endif
763 IEMOP_HLP_DONE_DECODING();
764 return IEMOP_RAISE_INVALID_OPCODE();
765}
766
767
768/** Invalid with RM byte where intel requires 8-byte immediate.
769 * Intel will also need SIB and displacement if bRm indicates memory. */
770FNIEMOPRM_DEF(iemOp_InvalidWithRMNeedImm8)
771{
772 IEMOP_MNEMONIC(InvalidWithRMNeedImm8, "InvalidWithRMNeedImm8");
773 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
774 {
775#ifndef TST_IEM_CHECK_MC
776 if (IEM_IS_MODRM_MEM_MODE(bRm))
777 {
778 RTGCPTR GCPtrEff;
779 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
780 if (rcStrict != VINF_SUCCESS)
781 return rcStrict;
782 }
783#endif
784 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8); RT_NOREF(bRm);
785 }
786 IEMOP_HLP_DONE_DECODING();
787 return IEMOP_RAISE_INVALID_OPCODE();
788}
789
790
791/** Invalid with RM byte where intel requires 8-byte immediate.
792 * Both AMD and Intel also needs SIB and displacement according to bRm. */
793FNIEMOPRM_DEF(iemOp_InvalidWithRMAllNeedImm8)
794{
795 IEMOP_MNEMONIC(InvalidWithRMAllNeedImm8, "InvalidWithRMAllNeedImm8");
796#ifndef TST_IEM_CHECK_MC
797 if (IEM_IS_MODRM_MEM_MODE(bRm))
798 {
799 RTGCPTR GCPtrEff;
800 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
801 if (rcStrict != VINF_SUCCESS)
802 return rcStrict;
803 }
804#endif
805 uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8); RT_NOREF(bRm);
806 IEMOP_HLP_DONE_DECODING();
807 return IEMOP_RAISE_INVALID_OPCODE();
808}
809
810
811/** Invalid opcode where intel requires Mod R/M sequence. */
812FNIEMOP_DEF(iemOp_InvalidNeedRM)
813{
814 IEMOP_MNEMONIC(InvalidNeedRM, "InvalidNeedRM");
815 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
816 {
817 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
818#ifndef TST_IEM_CHECK_MC
819 if (IEM_IS_MODRM_MEM_MODE(bRm))
820 {
821 RTGCPTR GCPtrEff;
822 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
823 if (rcStrict != VINF_SUCCESS)
824 return rcStrict;
825 }
826#endif
827 }
828 IEMOP_HLP_DONE_DECODING();
829 return IEMOP_RAISE_INVALID_OPCODE();
830}
831
832
833/** Invalid opcode where both AMD and Intel requires Mod R/M sequence. */
834FNIEMOP_DEF(iemOp_InvalidAllNeedRM)
835{
836 IEMOP_MNEMONIC(InvalidAllNeedRM, "InvalidAllNeedRM");
837 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
838#ifndef TST_IEM_CHECK_MC
839 if (IEM_IS_MODRM_MEM_MODE(bRm))
840 {
841 RTGCPTR GCPtrEff;
842 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
843 if (rcStrict != VINF_SUCCESS)
844 return rcStrict;
845 }
846#endif
847 IEMOP_HLP_DONE_DECODING();
848 return IEMOP_RAISE_INVALID_OPCODE();
849}
850
851
852/** Invalid opcode where intel requires Mod R/M sequence and 8-byte
853 * immediate. */
854FNIEMOP_DEF(iemOp_InvalidNeedRMImm8)
855{
856 IEMOP_MNEMONIC(InvalidNeedRMImm8, "InvalidNeedRMImm8");
857 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
858 {
859 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
860#ifndef TST_IEM_CHECK_MC
861 if (IEM_IS_MODRM_MEM_MODE(bRm))
862 {
863 RTGCPTR GCPtrEff;
864 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
865 if (rcStrict != VINF_SUCCESS)
866 return rcStrict;
867 }
868#endif
869 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); RT_NOREF(bImm);
870 }
871 IEMOP_HLP_DONE_DECODING();
872 return IEMOP_RAISE_INVALID_OPCODE();
873}
874
875
876/** Invalid opcode where intel requires a 3rd escape byte and a Mod R/M
877 * sequence. */
878FNIEMOP_DEF(iemOp_InvalidNeed3ByteEscRM)
879{
880 IEMOP_MNEMONIC(InvalidNeed3ByteEscRM, "InvalidNeed3ByteEscRM");
881 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
882 {
883 uint8_t b3rd; IEM_OPCODE_GET_NEXT_U8(&b3rd); RT_NOREF(b3rd);
884 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
885#ifndef TST_IEM_CHECK_MC
886 if (IEM_IS_MODRM_MEM_MODE(bRm))
887 {
888 RTGCPTR GCPtrEff;
889 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
890 if (rcStrict != VINF_SUCCESS)
891 return rcStrict;
892 }
893#endif
894 }
895 IEMOP_HLP_DONE_DECODING();
896 return IEMOP_RAISE_INVALID_OPCODE();
897}
898
899
900/** Invalid opcode where intel requires a 3rd escape byte, Mod R/M sequence, and
901 * a 8-byte immediate. */
902FNIEMOP_DEF(iemOp_InvalidNeed3ByteEscRMImm8)
903{
904 IEMOP_MNEMONIC(InvalidNeed3ByteEscRMImm8, "InvalidNeed3ByteEscRMImm8");
905 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
906 {
907 uint8_t b3rd; IEM_OPCODE_GET_NEXT_U8(&b3rd); RT_NOREF(b3rd);
908 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
909#ifndef TST_IEM_CHECK_MC
910 if (IEM_IS_MODRM_MEM_MODE(bRm))
911 {
912 RTGCPTR GCPtrEff;
913 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 1, &GCPtrEff);
914 if (rcStrict != VINF_SUCCESS)
915 return rcStrict;
916 }
917#endif
918 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); RT_NOREF(bImm);
919 IEMOP_HLP_DONE_DECODING();
920 }
921 return IEMOP_RAISE_INVALID_OPCODE();
922}
923
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