IEMAllInstructionsThree0f38.cpp.h@ 96020

Last change on this file since 96020 was 96020, checked in by vboxsync, 2 years ago
VMM/IEM: Implement missing [v]pmull{w,d} instructions, bugref:9898
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 62.2 KB

Line
1	/* $Id: IEMAllInstructionsThree0f38.cpp.h 96020 2022-08-04 08:54:09Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation.
4	*
5	* @remarks IEMAllInstructionsVexMap2.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/** @name Three byte opcodes with first two bytes 0x0f 0x38
23	* @{
24	*/
25
26	FNIEMOP_DEF_2(iemOpCommonMmx_FullFull_To_Full_Ex, PFNIEMAIMPLMEDIAF2U64, pfnU64, bool, fSupported); /* in IEMAllInstructionsTwoByteOf.cpp.h */
27
28
29	/**
30	* Common worker for SSSE3 instructions on the forms:
31	* pxxx xmm1, xmm2/mem128
32	*
33	* Proper alignment of the 128-bit operand is enforced.
34	* Exceptions type 4. SSSE3 cpuid checks.
35	*
36	* @sa iemOpCommonSse2_FullFull_To_Full
37	*/
38	FNIEMOP_DEF_1(iemOpCommonSsse3_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128)
39	{
40	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
41	if (IEM_IS_MODRM_REG_MODE(bRm))
42	{
43	/*
44	* Register, register.
45	*/
46	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
47	IEM_MC_BEGIN(2, 0);
48	IEM_MC_ARG(PRTUINT128U, puDst, 0);
49	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
50	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
51	IEM_MC_PREPARE_SSE_USAGE();
52	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
53	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
54	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
55	IEM_MC_ADVANCE_RIP();
56	IEM_MC_END();
57	}
58	else
59	{
60	/*
61	* Register, memory.
62	*/
63	IEM_MC_BEGIN(2, 2);
64	IEM_MC_ARG(PRTUINT128U, puDst, 0);
65	IEM_MC_LOCAL(RTUINT128U, uSrc);
66	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
67	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
68
69	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
70	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
71	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
72	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
73
74	IEM_MC_PREPARE_SSE_USAGE();
75	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
76	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
77
78	IEM_MC_ADVANCE_RIP();
79	IEM_MC_END();
80	}
81	return VINF_SUCCESS;
82	}
83
84
85	/**
86	* Common worker for SSE4.1 instructions on the forms:
87	* pxxx xmm1, xmm2/mem128
88	*
89	* Proper alignment of the 128-bit operand is enforced.
90	* Exceptions type 4. SSE4.1 cpuid checks.
91	*
92	* @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
93	* iemOpCommonSse42_FullFull_To_Full
94	*/
95	FNIEMOP_DEF_1(iemOpCommonSse41_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128)
96	{
97	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
98	if (IEM_IS_MODRM_REG_MODE(bRm))
99	{
100	/*
101	* Register, register.
102	*/
103	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
104	IEM_MC_BEGIN(2, 0);
105	IEM_MC_ARG(PRTUINT128U, puDst, 0);
106	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
107	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
108	IEM_MC_PREPARE_SSE_USAGE();
109	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
110	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
111	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
112	IEM_MC_ADVANCE_RIP();
113	IEM_MC_END();
114	}
115	else
116	{
117	/*
118	* Register, memory.
119	*/
120	IEM_MC_BEGIN(2, 2);
121	IEM_MC_ARG(PRTUINT128U, puDst, 0);
122	IEM_MC_LOCAL(RTUINT128U, uSrc);
123	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
124	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
125
126	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
127	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
128	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
129	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
130
131	IEM_MC_PREPARE_SSE_USAGE();
132	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
133	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
134
135	IEM_MC_ADVANCE_RIP();
136	IEM_MC_END();
137	}
138	return VINF_SUCCESS;
139	}
140
141
142	/**
143	* Common worker for SSE4.1 instructions on the forms:
144	* pxxx xmm1, xmm2/mem128
145	*
146	* Proper alignment of the 128-bit operand is enforced.
147	* Exceptions type 4. SSE4.1 cpuid checks.
148	*
149	* Unlike iemOpCommonSse41_FullFull_To_Full, the @a pfnU128 worker function
150	* takes no FXSAVE state, just the operands.
151	*
152	* @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
153	* iemOpCommonSse41_FullFull_To_Full, iemOpCommonSse42_FullFull_To_Full
154	*/
155	FNIEMOP_DEF_1(iemOpCommonSse41Opt_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU128)
156	{
157	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
158	if (IEM_IS_MODRM_REG_MODE(bRm))
159	{
160	/*
161	* Register, register.
162	*/
163	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
164	IEM_MC_BEGIN(2, 0);
165	IEM_MC_ARG(PRTUINT128U, puDst, 0);
166	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
167	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
168	IEM_MC_PREPARE_SSE_USAGE();
169	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
170	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
171	IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
172	IEM_MC_ADVANCE_RIP();
173	IEM_MC_END();
174	}
175	else
176	{
177	/*
178	* Register, memory.
179	*/
180	IEM_MC_BEGIN(2, 2);
181	IEM_MC_ARG(PRTUINT128U, puDst, 0);
182	IEM_MC_LOCAL(RTUINT128U, uSrc);
183	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
184	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
185
186	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
187	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
188	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
189	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
190
191	IEM_MC_PREPARE_SSE_USAGE();
192	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
193	IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
194
195	IEM_MC_ADVANCE_RIP();
196	IEM_MC_END();
197	}
198	return VINF_SUCCESS;
199	}
200
201
202	/**
203	* Common worker for SSE4.2 instructions on the forms:
204	* pxxx xmm1, xmm2/mem128
205	*
206	* Proper alignment of the 128-bit operand is enforced.
207	* Exceptions type 4. SSE4.2 cpuid checks.
208	*
209	* @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
210	* iemOpCommonSse41_FullFull_To_Full
211	*/
212	FNIEMOP_DEF_1(iemOpCommonSse42_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128)
213	{
214	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
215	if (IEM_IS_MODRM_REG_MODE(bRm))
216	{
217	/*
218	* Register, register.
219	*/
220	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
221	IEM_MC_BEGIN(2, 0);
222	IEM_MC_ARG(PRTUINT128U, puDst, 0);
223	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
224	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
225	IEM_MC_PREPARE_SSE_USAGE();
226	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
227	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
228	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
229	IEM_MC_ADVANCE_RIP();
230	IEM_MC_END();
231	}
232	else
233	{
234	/*
235	* Register, memory.
236	*/
237	IEM_MC_BEGIN(2, 2);
238	IEM_MC_ARG(PRTUINT128U, puDst, 0);
239	IEM_MC_LOCAL(RTUINT128U, uSrc);
240	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
241	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
242
243	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
244	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
245	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
246	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
247
248	IEM_MC_PREPARE_SSE_USAGE();
249	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
250	IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
251
252	IEM_MC_ADVANCE_RIP();
253	IEM_MC_END();
254	}
255	return VINF_SUCCESS;
256	}
257
258
259	/** Opcode 0x0f 0x38 0x00. */
260	FNIEMOP_DEF(iemOp_pshufb_Pq_Qq)
261	{
262	IEMOP_MNEMONIC2(RM, PSHUFB, pshufb, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
263	return FNIEMOP_CALL_2(iemOpCommonMmx_FullFull_To_Full_Ex,
264	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pshufb_u64,&iemAImpl_pshufb_u64_fallback),
265	IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
266	}
267
268
269	/** Opcode 0x66 0x0f 0x38 0x00. */
270	FNIEMOP_DEF(iemOp_pshufb_Vx_Wx)
271	{
272	IEMOP_MNEMONIC2(RM, PSHUFB, pshufb, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
273	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
274	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback));
275
276	}
277
278
279	/* Opcode 0x0f 0x38 0x01. */
280	FNIEMOP_STUB(iemOp_phaddw_Pq_Qq);
281	/** Opcode 0x66 0x0f 0x38 0x01. */
282	FNIEMOP_STUB(iemOp_phaddw_Vx_Wx);
283	/** Opcode 0x0f 0x38 0x02. */
284	FNIEMOP_STUB(iemOp_phaddd_Pq_Qq);
285	/** Opcode 0x66 0x0f 0x38 0x02. */
286	FNIEMOP_STUB(iemOp_phaddd_Vx_Wx);
287	/** Opcode 0x0f 0x38 0x03. */
288	FNIEMOP_STUB(iemOp_phaddsw_Pq_Qq);
289	/** Opcode 0x66 0x0f 0x38 0x03. */
290	FNIEMOP_STUB(iemOp_phaddsw_Vx_Wx);
291	/** Opcode 0x0f 0x38 0x04. */
292	FNIEMOP_STUB(iemOp_pmaddubsw_Pq_Qq);
293	/** Opcode 0x66 0x0f 0x38 0x04. */
294	FNIEMOP_STUB(iemOp_pmaddubsw_Vx_Wx);
295	/** Opcode 0x0f 0x38 0x05. */
296	FNIEMOP_STUB(iemOp_phsubw_Pq_Qq);
297	/** Opcode 0x66 0x0f 0x38 0x05. */
298	FNIEMOP_STUB(iemOp_phsubw_Vx_Wx);
299	/** Opcode 0x0f 0x38 0x06. */
300	FNIEMOP_STUB(iemOp_phsubd_Pq_Qq);
301	/** Opcode 0x66 0x0f 0x38 0x06. */
302	FNIEMOP_STUB(iemOp_phsubdq_Vx_Wx);
303	/** Opcode 0x0f 0x38 0x07. */
304	FNIEMOP_STUB(iemOp_phsubsw_Pq_Qq);
305	/** Opcode 0x66 0x0f 0x38 0x07. */
306	FNIEMOP_STUB(iemOp_phsubsw_Vx_Wx);
307	/** Opcode 0x0f 0x38 0x08. */
308	FNIEMOP_STUB(iemOp_psignb_Pq_Qq);
309	/** Opcode 0x66 0x0f 0x38 0x08. */
310	FNIEMOP_STUB(iemOp_psignb_Vx_Wx);
311	/** Opcode 0x0f 0x38 0x09. */
312	FNIEMOP_STUB(iemOp_psignw_Pq_Qq);
313	/** Opcode 0x66 0x0f 0x38 0x09. */
314	FNIEMOP_STUB(iemOp_psignw_Vx_Wx);
315	/** Opcode 0x0f 0x38 0x0a. */
316	FNIEMOP_STUB(iemOp_psignd_Pq_Qq);
317	/** Opcode 0x66 0x0f 0x38 0x0a. */
318	FNIEMOP_STUB(iemOp_psignd_Vx_Wx);
319	/** Opcode 0x0f 0x38 0x0b. */
320	FNIEMOP_STUB(iemOp_pmulhrsw_Pq_Qq);
321	/** Opcode 0x66 0x0f 0x38 0x0b. */
322	FNIEMOP_STUB(iemOp_pmulhrsw_Vx_Wx);
323	/* Opcode 0x0f 0x38 0x0c - invalid. */
324	/* Opcode 0x66 0x0f 0x38 0x0c - invalid (vex only). */
325	/* Opcode 0x0f 0x38 0x0d - invalid. */
326	/* Opcode 0x66 0x0f 0x38 0x0d - invalid (vex only). */
327	/* Opcode 0x0f 0x38 0x0e - invalid. */
328	/* Opcode 0x66 0x0f 0x38 0x0e - invalid (vex only). */
329	/* Opcode 0x0f 0x38 0x0f - invalid. */
330	/* Opcode 0x66 0x0f 0x38 0x0f - invalid (vex only). */
331
332
333	/* Opcode 0x0f 0x38 0x10 - invalid */
334	/** Opcode 0x66 0x0f 0x38 0x10 (legacy only). */
335	FNIEMOP_STUB(iemOp_pblendvb_Vdq_Wdq);
336	/* Opcode 0x0f 0x38 0x11 - invalid */
337	/* Opcode 0x66 0x0f 0x38 0x11 - invalid */
338	/* Opcode 0x0f 0x38 0x12 - invalid */
339	/* Opcode 0x66 0x0f 0x38 0x12 - invalid */
340	/* Opcode 0x0f 0x38 0x13 - invalid */
341	/* Opcode 0x66 0x0f 0x38 0x13 - invalid (vex only). */
342	/* Opcode 0x0f 0x38 0x14 - invalid */
343	/** Opcode 0x66 0x0f 0x38 0x14 (legacy only). */
344	FNIEMOP_STUB(iemOp_blendvps_Vdq_Wdq);
345	/* Opcode 0x0f 0x38 0x15 - invalid */
346	/** Opcode 0x66 0x0f 0x38 0x15 (legacy only). */
347	FNIEMOP_STUB(iemOp_blendvpd_Vdq_Wdq);
348	/* Opcode 0x0f 0x38 0x16 - invalid */
349	/* Opcode 0x66 0x0f 0x38 0x16 - invalid (vex only). */
350	/* Opcode 0x0f 0x38 0x17 - invalid */
351
352
353	/** Opcode 0x66 0x0f 0x38 0x17 - invalid */
354	FNIEMOP_DEF(iemOp_ptest_Vx_Wx)
355	{
356	IEMOP_MNEMONIC2(RM, PTEST, ptest, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
357	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
358	if (IEM_IS_MODRM_REG_MODE(bRm))
359	{
360	/*
361	* Register, register.
362	*/
363	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
364	IEM_MC_BEGIN(3, 0);
365	IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
366	IEM_MC_ARG(PCRTUINT128U, puSrc2, 1);
367	IEM_MC_ARG(uint32_t *, pEFlags, 2);
368	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
369	IEM_MC_PREPARE_SSE_USAGE();
370	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
371	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
372	IEM_MC_REF_EFLAGS(pEFlags);
373	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
374	IEM_MC_ADVANCE_RIP();
375	IEM_MC_END();
376	}
377	else
378	{
379	/*
380	* Register, memory.
381	*/
382	IEM_MC_BEGIN(3, 2);
383	IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
384	IEM_MC_LOCAL(RTUINT128U, uSrc2);
385	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1);
386	IEM_MC_ARG(uint32_t *, pEFlags, 2);
387	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
388
389	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
390	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
391	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
392	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
393
394	IEM_MC_PREPARE_SSE_USAGE();
395	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
396	IEM_MC_REF_EFLAGS(pEFlags);
397	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
398
399	IEM_MC_ADVANCE_RIP();
400	IEM_MC_END();
401	}
402	return VINF_SUCCESS;
403	}
404
405
406	/* Opcode 0x0f 0x38 0x18 - invalid */
407	/* Opcode 0x66 0x0f 0x38 0x18 - invalid (vex only). */
408	/* Opcode 0x0f 0x38 0x19 - invalid */
409	/* Opcode 0x66 0x0f 0x38 0x19 - invalid (vex only). */
410	/* Opcode 0x0f 0x38 0x1a - invalid */
411	/* Opcode 0x66 0x0f 0x38 0x1a - invalid (vex only). */
412	/* Opcode 0x0f 0x38 0x1b - invalid */
413	/* Opcode 0x66 0x0f 0x38 0x1b - invalid */
414	/** Opcode 0x0f 0x38 0x1c. */
415	FNIEMOP_STUB(iemOp_pabsb_Pq_Qq);
416	/** Opcode 0x66 0x0f 0x38 0x1c. */
417	FNIEMOP_STUB(iemOp_pabsb_Vx_Wx);
418	/** Opcode 0x0f 0x38 0x1d. */
419	FNIEMOP_STUB(iemOp_pabsw_Pq_Qq);
420	/** Opcode 0x66 0x0f 0x38 0x1d. */
421	FNIEMOP_STUB(iemOp_pabsw_Vx_Wx);
422	/** Opcode 0x0f 0x38 0x1e. */
423	FNIEMOP_STUB(iemOp_pabsd_Pq_Qq);
424	/** Opcode 0x66 0x0f 0x38 0x1e. */
425	FNIEMOP_STUB(iemOp_pabsd_Vx_Wx);
426	/* Opcode 0x0f 0x38 0x1f - invalid */
427	/* Opcode 0x66 0x0f 0x38 0x1f - invalid */
428
429
430	/** Opcode 0x66 0x0f 0x38 0x20. */
431	FNIEMOP_STUB(iemOp_pmovsxbw_Vx_UxMq);
432	/** Opcode 0x66 0x0f 0x38 0x21. */
433	FNIEMOP_STUB(iemOp_pmovsxbd_Vx_UxMd);
434	/** Opcode 0x66 0x0f 0x38 0x22. */
435	FNIEMOP_STUB(iemOp_pmovsxbq_Vx_UxMw);
436	/** Opcode 0x66 0x0f 0x38 0x23. */
437	FNIEMOP_STUB(iemOp_pmovsxwd_Vx_UxMq);
438	/** Opcode 0x66 0x0f 0x38 0x24. */
439	FNIEMOP_STUB(iemOp_pmovsxwq_Vx_UxMd);
440	/** Opcode 0x66 0x0f 0x38 0x25. */
441	FNIEMOP_STUB(iemOp_pmovsxdq_Vx_UxMq);
442	/* Opcode 0x66 0x0f 0x38 0x26 - invalid */
443	/* Opcode 0x66 0x0f 0x38 0x27 - invalid */
444	/** Opcode 0x66 0x0f 0x38 0x28. */
445	FNIEMOP_STUB(iemOp_pmuldq_Vx_Wx);
446
447
448	/** Opcode 0x66 0x0f 0x38 0x29. */
449	FNIEMOP_DEF(iemOp_pcmpeqq_Vx_Wx)
450	{
451	IEMOP_MNEMONIC2(RM, PCMPEQQ, pcmpeqq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
452	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
453	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback));
454	}
455
456
457	/**
458	* @opcode 0x2a
459	* @opcodesub !11 mr/reg
460	* @oppfx 0x66
461	* @opcpuid sse4.1
462	* @opgroup og_sse41_cachect
463	* @opxcpttype 1
464	* @optest op1=-1 op2=2 -> op1=2
465	* @optest op1=0 op2=-42 -> op1=-42
466	*/
467	FNIEMOP_DEF(iemOp_movntdqa_Vdq_Mdq)
468	{
469	IEMOP_MNEMONIC2(RM_MEM, MOVNTDQA, movntdqa, Vdq_WO, Mdq, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
470	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
471	if (IEM_IS_MODRM_MEM_MODE(bRm))
472	{
473	/* Register, memory. */
474	IEM_MC_BEGIN(0, 2);
475	IEM_MC_LOCAL(RTUINT128U, uSrc);
476	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
477
478	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
479	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
480	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
481	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
482
483	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
484	IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
485
486	IEM_MC_ADVANCE_RIP();
487	IEM_MC_END();
488	return VINF_SUCCESS;
489	}
490
491	/**
492	* @opdone
493	* @opmnemonic ud660f382areg
494	* @opcode 0x2a
495	* @opcodesub 11 mr/reg
496	* @oppfx 0x66
497	* @opunused immediate
498	* @opcpuid sse
499	* @optest ->
500	*/
501	return IEMOP_RAISE_INVALID_OPCODE();
502	}
503
504
505	/** Opcode 0x66 0x0f 0x38 0x2b. */
506	FNIEMOP_DEF(iemOp_packusdw_Vx_Wx)
507	{
508	IEMOP_MNEMONIC2(RM, PACKUSDW, packusdw, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
509	return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full, iemAImpl_packusdw_u128);
510	}
511
512
513	/* Opcode 0x66 0x0f 0x38 0x2c - invalid (vex only). */
514	/* Opcode 0x66 0x0f 0x38 0x2d - invalid (vex only). */
515	/* Opcode 0x66 0x0f 0x38 0x2e - invalid (vex only). */
516	/* Opcode 0x66 0x0f 0x38 0x2f - invalid (vex only). */
517
518	/** Opcode 0x66 0x0f 0x38 0x30. */
519	FNIEMOP_STUB(iemOp_pmovzxbw_Vx_UxMq);
520	/** Opcode 0x66 0x0f 0x38 0x31. */
521	FNIEMOP_STUB(iemOp_pmovzxbd_Vx_UxMd);
522	/** Opcode 0x66 0x0f 0x38 0x32. */
523	FNIEMOP_STUB(iemOp_pmovzxbq_Vx_UxMw);
524	/** Opcode 0x66 0x0f 0x38 0x33. */
525	FNIEMOP_STUB(iemOp_pmovzxwd_Vx_UxMq);
526	/** Opcode 0x66 0x0f 0x38 0x34. */
527	FNIEMOP_STUB(iemOp_pmovzxwq_Vx_UxMd);
528	/** Opcode 0x66 0x0f 0x38 0x35. */
529	FNIEMOP_STUB(iemOp_pmovzxdq_Vx_UxMq);
530	/* Opcode 0x66 0x0f 0x38 0x36 - invalid (vex only). */
531
532
533	/** Opcode 0x66 0x0f 0x38 0x37. */
534	FNIEMOP_DEF(iemOp_pcmpgtq_Vx_Wx)
535	{
536	IEMOP_MNEMONIC2(RM, PCMPGTQ, pcmpgtq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
537	return FNIEMOP_CALL_1(iemOpCommonSse42_FullFull_To_Full,
538	IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback));
539	}
540
541
542	/** Opcode 0x66 0x0f 0x38 0x38. */
543	FNIEMOP_DEF(iemOp_pminsb_Vx_Wx)
544	{
545	IEMOP_MNEMONIC2(RM, PMINSB, pminsb, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
546	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
547	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback));
548	}
549
550
551	/** Opcode 0x66 0x0f 0x38 0x39. */
552	FNIEMOP_DEF(iemOp_pminsd_Vx_Wx)
553	{
554	IEMOP_MNEMONIC2(RM, PMINSD, pminsd, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
555	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
556	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback));
557	}
558
559
560	/** Opcode 0x66 0x0f 0x38 0x3a. */
561	FNIEMOP_DEF(iemOp_pminuw_Vx_Wx)
562	{
563	IEMOP_MNEMONIC2(RM, PMINUW, pminuw, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
564	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
565	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback));
566	}
567
568
569	/** Opcode 0x66 0x0f 0x38 0x3b. */
570	FNIEMOP_DEF(iemOp_pminud_Vx_Wx)
571	{
572	IEMOP_MNEMONIC2(RM, PMINUD, pminud, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
573	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
574	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback));
575	}
576
577
578	/** Opcode 0x66 0x0f 0x38 0x3c. */
579	FNIEMOP_DEF(iemOp_pmaxsb_Vx_Wx)
580	{
581	IEMOP_MNEMONIC2(RM, PMAXSB, pmaxsb, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
582	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
583	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback));
584	}
585
586
587	/** Opcode 0x66 0x0f 0x38 0x3d. */
588	FNIEMOP_DEF(iemOp_pmaxsd_Vx_Wx)
589	{
590	IEMOP_MNEMONIC2(RM, PMAXSD, pmaxsd, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
591	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
592	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback));
593	}
594
595
596	/** Opcode 0x66 0x0f 0x38 0x3e. */
597	FNIEMOP_DEF(iemOp_pmaxuw_Vx_Wx)
598	{
599	IEMOP_MNEMONIC2(RM, PMAXUW, pmaxuw, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
600	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
601	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback));
602	}
603
604
605	/** Opcode 0x66 0x0f 0x38 0x3f. */
606	FNIEMOP_DEF(iemOp_pmaxud_Vx_Wx)
607	{
608	IEMOP_MNEMONIC2(RM, PMAXUD, pmaxud, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
609	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
610	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback));
611	}
612
613
614	/** Opcode 0x66 0x0f 0x38 0x40. */
615	FNIEMOP_DEF(iemOp_pmulld_Vx_Wx)
616	{
617	IEMOP_MNEMONIC2(RM, PMULLD, pmulld, Vx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
618	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
619	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback));
620	}
621
622
623	/** Opcode 0x66 0x0f 0x38 0x41. */
624	FNIEMOP_STUB(iemOp_phminposuw_Vdq_Wdq);
625	/* Opcode 0x66 0x0f 0x38 0x42 - invalid. */
626	/* Opcode 0x66 0x0f 0x38 0x43 - invalid. */
627	/* Opcode 0x66 0x0f 0x38 0x44 - invalid. */
628	/* Opcode 0x66 0x0f 0x38 0x45 - invalid (vex only). */
629	/* Opcode 0x66 0x0f 0x38 0x46 - invalid (vex only). */
630	/* Opcode 0x66 0x0f 0x38 0x47 - invalid (vex only). */
631	/* Opcode 0x66 0x0f 0x38 0x48 - invalid. */
632	/* Opcode 0x66 0x0f 0x38 0x49 - invalid. */
633	/* Opcode 0x66 0x0f 0x38 0x4a - invalid. */
634	/* Opcode 0x66 0x0f 0x38 0x4b - invalid. */
635	/* Opcode 0x66 0x0f 0x38 0x4c - invalid. */
636	/* Opcode 0x66 0x0f 0x38 0x4d - invalid. */
637	/* Opcode 0x66 0x0f 0x38 0x4e - invalid. */
638	/* Opcode 0x66 0x0f 0x38 0x4f - invalid. */
639
640	/* Opcode 0x66 0x0f 0x38 0x50 - invalid. */
641	/* Opcode 0x66 0x0f 0x38 0x51 - invalid. */
642	/* Opcode 0x66 0x0f 0x38 0x52 - invalid. */
643	/* Opcode 0x66 0x0f 0x38 0x53 - invalid. */
644	/* Opcode 0x66 0x0f 0x38 0x54 - invalid. */
645	/* Opcode 0x66 0x0f 0x38 0x55 - invalid. */
646	/* Opcode 0x66 0x0f 0x38 0x56 - invalid. */
647	/* Opcode 0x66 0x0f 0x38 0x57 - invalid. */
648	/* Opcode 0x66 0x0f 0x38 0x58 - invalid (vex only). */
649	/* Opcode 0x66 0x0f 0x38 0x59 - invalid (vex only). */
650	/* Opcode 0x66 0x0f 0x38 0x5a - invalid (vex only). */
651	/* Opcode 0x66 0x0f 0x38 0x5b - invalid. */
652	/* Opcode 0x66 0x0f 0x38 0x5c - invalid. */
653	/* Opcode 0x66 0x0f 0x38 0x5d - invalid. */
654	/* Opcode 0x66 0x0f 0x38 0x5e - invalid. */
655	/* Opcode 0x66 0x0f 0x38 0x5f - invalid. */
656
657	/* Opcode 0x66 0x0f 0x38 0x60 - invalid. */
658	/* Opcode 0x66 0x0f 0x38 0x61 - invalid. */
659	/* Opcode 0x66 0x0f 0x38 0x62 - invalid. */
660	/* Opcode 0x66 0x0f 0x38 0x63 - invalid. */
661	/* Opcode 0x66 0x0f 0x38 0x64 - invalid. */
662	/* Opcode 0x66 0x0f 0x38 0x65 - invalid. */
663	/* Opcode 0x66 0x0f 0x38 0x66 - invalid. */
664	/* Opcode 0x66 0x0f 0x38 0x67 - invalid. */
665	/* Opcode 0x66 0x0f 0x38 0x68 - invalid. */
666	/* Opcode 0x66 0x0f 0x38 0x69 - invalid. */
667	/* Opcode 0x66 0x0f 0x38 0x6a - invalid. */
668	/* Opcode 0x66 0x0f 0x38 0x6b - invalid. */
669	/* Opcode 0x66 0x0f 0x38 0x6c - invalid. */
670	/* Opcode 0x66 0x0f 0x38 0x6d - invalid. */
671	/* Opcode 0x66 0x0f 0x38 0x6e - invalid. */
672	/* Opcode 0x66 0x0f 0x38 0x6f - invalid. */
673
674	/* Opcode 0x66 0x0f 0x38 0x70 - invalid. */
675	/* Opcode 0x66 0x0f 0x38 0x71 - invalid. */
676	/* Opcode 0x66 0x0f 0x38 0x72 - invalid. */
677	/* Opcode 0x66 0x0f 0x38 0x73 - invalid. */
678	/* Opcode 0x66 0x0f 0x38 0x74 - invalid. */
679	/* Opcode 0x66 0x0f 0x38 0x75 - invalid. */
680	/* Opcode 0x66 0x0f 0x38 0x76 - invalid. */
681	/* Opcode 0x66 0x0f 0x38 0x77 - invalid. */
682	/* Opcode 0x66 0x0f 0x38 0x78 - invalid (vex only). */
683	/* Opcode 0x66 0x0f 0x38 0x79 - invalid (vex only). */
684	/* Opcode 0x66 0x0f 0x38 0x7a - invalid. */
685	/* Opcode 0x66 0x0f 0x38 0x7b - invalid. */
686	/* Opcode 0x66 0x0f 0x38 0x7c - invalid. */
687	/* Opcode 0x66 0x0f 0x38 0x7d - invalid. */
688	/* Opcode 0x66 0x0f 0x38 0x7e - invalid. */
689	/* Opcode 0x66 0x0f 0x38 0x7f - invalid. */
690
691	/** Opcode 0x66 0x0f 0x38 0x80. */
692	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
693	FNIEMOP_DEF(iemOp_invept_Gy_Mdq)
694	{
695	IEMOP_MNEMONIC(invept, "invept Gy,Mdq");
696	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
697	IEMOP_HLP_IN_VMX_OPERATION("invept", kVmxVDiag_Invept);
698	IEMOP_HLP_VMX_INSTR("invept", kVmxVDiag_Invept);
699	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
700	if (IEM_IS_MODRM_MEM_MODE(bRm))
701	{
702	/* Register, memory. */
703	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
704	{
705	IEM_MC_BEGIN(3, 0);
706	IEM_MC_ARG(uint8_t, iEffSeg, 0);
707	IEM_MC_ARG(RTGCPTR, GCPtrInveptDesc, 1);
708	IEM_MC_ARG(uint64_t, uInveptType, 2);
709	IEM_MC_FETCH_GREG_U64(uInveptType, IEM_GET_MODRM_REG(pVCpu, bRm));
710	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
711	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
712	IEM_MC_CALL_CIMPL_3(iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType);
713	IEM_MC_END();
714	}
715	else
716	{
717	IEM_MC_BEGIN(3, 0);
718	IEM_MC_ARG(uint8_t, iEffSeg, 0);
719	IEM_MC_ARG(RTGCPTR, GCPtrInveptDesc, 1);
720	IEM_MC_ARG(uint32_t, uInveptType, 2);
721	IEM_MC_FETCH_GREG_U32(uInveptType, IEM_GET_MODRM_REG(pVCpu, bRm));
722	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
723	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
724	IEM_MC_CALL_CIMPL_3(iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType);
725	IEM_MC_END();
726	}
727	}
728	Log(("iemOp_invept_Gy_Mdq: invalid encoding -> #UD\n"));
729	return IEMOP_RAISE_INVALID_OPCODE();
730	}
731	#else
732	FNIEMOP_STUB(iemOp_invept_Gy_Mdq);
733	#endif
734
735	/** Opcode 0x66 0x0f 0x38 0x81. */
736	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
737	FNIEMOP_DEF(iemOp_invvpid_Gy_Mdq)
738	{
739	IEMOP_MNEMONIC(invvpid, "invvpid Gy,Mdq");
740	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
741	IEMOP_HLP_IN_VMX_OPERATION("invvpid", kVmxVDiag_Invvpid);
742	IEMOP_HLP_VMX_INSTR("invvpid", kVmxVDiag_Invvpid);
743	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
744	if (IEM_IS_MODRM_MEM_MODE(bRm))
745	{
746	/* Register, memory. */
747	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
748	{
749	IEM_MC_BEGIN(3, 0);
750	IEM_MC_ARG(uint8_t, iEffSeg, 0);
751	IEM_MC_ARG(RTGCPTR, GCPtrInvvpidDesc, 1);
752	IEM_MC_ARG(uint64_t, uInvvpidType, 2);
753	IEM_MC_FETCH_GREG_U64(uInvvpidType, IEM_GET_MODRM_REG(pVCpu, bRm));
754	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
755	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
756	IEM_MC_CALL_CIMPL_3(iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType);
757	IEM_MC_END();
758	}
759	else
760	{
761	IEM_MC_BEGIN(3, 0);
762	IEM_MC_ARG(uint8_t, iEffSeg, 0);
763	IEM_MC_ARG(RTGCPTR, GCPtrInvvpidDesc, 1);
764	IEM_MC_ARG(uint32_t, uInvvpidType, 2);
765	IEM_MC_FETCH_GREG_U32(uInvvpidType, IEM_GET_MODRM_REG(pVCpu, bRm));
766	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
767	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
768	IEM_MC_CALL_CIMPL_3(iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType);
769	IEM_MC_END();
770	}
771	}
772	Log(("iemOp_invvpid_Gy_Mdq: invalid encoding -> #UD\n"));
773	return IEMOP_RAISE_INVALID_OPCODE();
774	}
775	#else
776	FNIEMOP_STUB(iemOp_invvpid_Gy_Mdq);
777	#endif
778
779	/** Opcode 0x66 0x0f 0x38 0x82. */
780	FNIEMOP_DEF(iemOp_invpcid_Gy_Mdq)
781	{
782	IEMOP_MNEMONIC(invpcid, "invpcid Gy,Mdq");
783	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
784	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
785	if (IEM_IS_MODRM_MEM_MODE(bRm))
786	{
787	/* Register, memory. */
788	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
789	{
790	IEM_MC_BEGIN(3, 0);
791	IEM_MC_ARG(uint8_t, iEffSeg, 0);
792	IEM_MC_ARG(RTGCPTR, GCPtrInvpcidDesc, 1);
793	IEM_MC_ARG(uint64_t, uInvpcidType, 2);
794	IEM_MC_FETCH_GREG_U64(uInvpcidType, IEM_GET_MODRM_REG(pVCpu, bRm));
795	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
796	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
797	IEM_MC_CALL_CIMPL_3(iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
798	IEM_MC_END();
799	}
800	else
801	{
802	IEM_MC_BEGIN(3, 0);
803	IEM_MC_ARG(uint8_t, iEffSeg, 0);
804	IEM_MC_ARG(RTGCPTR, GCPtrInvpcidDesc, 1);
805	IEM_MC_ARG(uint32_t, uInvpcidType, 2);
806	IEM_MC_FETCH_GREG_U32(uInvpcidType, IEM_GET_MODRM_REG(pVCpu, bRm));
807	IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
808	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
809	IEM_MC_CALL_CIMPL_3(iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
810	IEM_MC_END();
811	}
812	}
813	Log(("iemOp_invpcid_Gy_Mdq: invalid encoding -> #UD\n"));
814	return IEMOP_RAISE_INVALID_OPCODE();
815	}
816
817
818	/* Opcode 0x66 0x0f 0x38 0x83 - invalid. */
819	/* Opcode 0x66 0x0f 0x38 0x84 - invalid. */
820	/* Opcode 0x66 0x0f 0x38 0x85 - invalid. */
821	/* Opcode 0x66 0x0f 0x38 0x86 - invalid. */
822	/* Opcode 0x66 0x0f 0x38 0x87 - invalid. */
823	/* Opcode 0x66 0x0f 0x38 0x88 - invalid. */
824	/* Opcode 0x66 0x0f 0x38 0x89 - invalid. */
825	/* Opcode 0x66 0x0f 0x38 0x8a - invalid. */
826	/* Opcode 0x66 0x0f 0x38 0x8b - invalid. */
827	/* Opcode 0x66 0x0f 0x38 0x8c - invalid (vex only). */
828	/* Opcode 0x66 0x0f 0x38 0x8d - invalid. */
829	/* Opcode 0x66 0x0f 0x38 0x8e - invalid (vex only). */
830	/* Opcode 0x66 0x0f 0x38 0x8f - invalid. */
831
832	/* Opcode 0x66 0x0f 0x38 0x90 - invalid (vex only). */
833	/* Opcode 0x66 0x0f 0x38 0x91 - invalid (vex only). */
834	/* Opcode 0x66 0x0f 0x38 0x92 - invalid (vex only). */
835	/* Opcode 0x66 0x0f 0x38 0x93 - invalid (vex only). */
836	/* Opcode 0x66 0x0f 0x38 0x94 - invalid. */
837	/* Opcode 0x66 0x0f 0x38 0x95 - invalid. */
838	/* Opcode 0x66 0x0f 0x38 0x96 - invalid (vex only). */
839	/* Opcode 0x66 0x0f 0x38 0x97 - invalid (vex only). */
840	/* Opcode 0x66 0x0f 0x38 0x98 - invalid (vex only). */
841	/* Opcode 0x66 0x0f 0x38 0x99 - invalid (vex only). */
842	/* Opcode 0x66 0x0f 0x38 0x9a - invalid (vex only). */
843	/* Opcode 0x66 0x0f 0x38 0x9b - invalid (vex only). */
844	/* Opcode 0x66 0x0f 0x38 0x9c - invalid (vex only). */
845	/* Opcode 0x66 0x0f 0x38 0x9d - invalid (vex only). */
846	/* Opcode 0x66 0x0f 0x38 0x9e - invalid (vex only). */
847	/* Opcode 0x66 0x0f 0x38 0x9f - invalid (vex only). */
848
849	/* Opcode 0x66 0x0f 0x38 0xa0 - invalid. */
850	/* Opcode 0x66 0x0f 0x38 0xa1 - invalid. */
851	/* Opcode 0x66 0x0f 0x38 0xa2 - invalid. */
852	/* Opcode 0x66 0x0f 0x38 0xa3 - invalid. */
853	/* Opcode 0x66 0x0f 0x38 0xa4 - invalid. */
854	/* Opcode 0x66 0x0f 0x38 0xa5 - invalid. */
855	/* Opcode 0x66 0x0f 0x38 0xa6 - invalid (vex only). */
856	/* Opcode 0x66 0x0f 0x38 0xa7 - invalid (vex only). */
857	/* Opcode 0x66 0x0f 0x38 0xa8 - invalid (vex only). */
858	/* Opcode 0x66 0x0f 0x38 0xa9 - invalid (vex only). */
859	/* Opcode 0x66 0x0f 0x38 0xaa - invalid (vex only). */
860	/* Opcode 0x66 0x0f 0x38 0xab - invalid (vex only). */
861	/* Opcode 0x66 0x0f 0x38 0xac - invalid (vex only). */
862	/* Opcode 0x66 0x0f 0x38 0xad - invalid (vex only). */
863	/* Opcode 0x66 0x0f 0x38 0xae - invalid (vex only). */
864	/* Opcode 0x66 0x0f 0x38 0xaf - invalid (vex only). */
865
866	/* Opcode 0x66 0x0f 0x38 0xb0 - invalid. */
867	/* Opcode 0x66 0x0f 0x38 0xb1 - invalid. */
868	/* Opcode 0x66 0x0f 0x38 0xb2 - invalid. */
869	/* Opcode 0x66 0x0f 0x38 0xb3 - invalid. */
870	/* Opcode 0x66 0x0f 0x38 0xb4 - invalid. */
871	/* Opcode 0x66 0x0f 0x38 0xb5 - invalid. */
872	/* Opcode 0x66 0x0f 0x38 0xb6 - invalid (vex only). */
873	/* Opcode 0x66 0x0f 0x38 0xb7 - invalid (vex only). */
874	/* Opcode 0x66 0x0f 0x38 0xb8 - invalid (vex only). */
875	/* Opcode 0x66 0x0f 0x38 0xb9 - invalid (vex only). */
876	/* Opcode 0x66 0x0f 0x38 0xba - invalid (vex only). */
877	/* Opcode 0x66 0x0f 0x38 0xbb - invalid (vex only). */
878	/* Opcode 0x66 0x0f 0x38 0xbc - invalid (vex only). */
879	/* Opcode 0x66 0x0f 0x38 0xbd - invalid (vex only). */
880	/* Opcode 0x66 0x0f 0x38 0xbe - invalid (vex only). */
881	/* Opcode 0x66 0x0f 0x38 0xbf - invalid (vex only). */
882
883	/* Opcode 0x0f 0x38 0xc0 - invalid. */
884	/* Opcode 0x66 0x0f 0x38 0xc0 - invalid. */
885	/* Opcode 0x0f 0x38 0xc1 - invalid. */
886	/* Opcode 0x66 0x0f 0x38 0xc1 - invalid. */
887	/* Opcode 0x0f 0x38 0xc2 - invalid. */
888	/* Opcode 0x66 0x0f 0x38 0xc2 - invalid. */
889	/* Opcode 0x0f 0x38 0xc3 - invalid. */
890	/* Opcode 0x66 0x0f 0x38 0xc3 - invalid. */
891	/* Opcode 0x0f 0x38 0xc4 - invalid. */
892	/* Opcode 0x66 0x0f 0x38 0xc4 - invalid. */
893	/* Opcode 0x0f 0x38 0xc5 - invalid. */
894	/* Opcode 0x66 0x0f 0x38 0xc5 - invalid. */
895	/* Opcode 0x0f 0x38 0xc6 - invalid. */
896	/* Opcode 0x66 0x0f 0x38 0xc6 - invalid. */
897	/* Opcode 0x0f 0x38 0xc7 - invalid. */
898	/* Opcode 0x66 0x0f 0x38 0xc7 - invalid. */
899	/** Opcode 0x0f 0x38 0xc8. */
900	FNIEMOP_STUB(iemOp_sha1nexte_Vdq_Wdq);
901	/* Opcode 0x66 0x0f 0x38 0xc8 - invalid. */
902	/** Opcode 0x0f 0x38 0xc9. */
903	FNIEMOP_STUB(iemOp_sha1msg1_Vdq_Wdq);
904	/* Opcode 0x66 0x0f 0x38 0xc9 - invalid. */
905	/** Opcode 0x0f 0x38 0xca. */
906	FNIEMOP_STUB(iemOp_sha1msg2_Vdq_Wdq);
907	/* Opcode 0x66 0x0f 0x38 0xca - invalid. */
908	/** Opcode 0x0f 0x38 0xcb. */
909	FNIEMOP_STUB(iemOp_sha256rnds2_Vdq_Wdq);
910	/* Opcode 0x66 0x0f 0x38 0xcb - invalid. */
911	/** Opcode 0x0f 0x38 0xcc. */
912	FNIEMOP_STUB(iemOp_sha256msg1_Vdq_Wdq);
913	/* Opcode 0x66 0x0f 0x38 0xcc - invalid. */
914	/** Opcode 0x0f 0x38 0xcd. */
915	FNIEMOP_STUB(iemOp_sha256msg2_Vdq_Wdq);
916	/* Opcode 0x66 0x0f 0x38 0xcd - invalid. */
917	/* Opcode 0x0f 0x38 0xce - invalid. */
918	/* Opcode 0x66 0x0f 0x38 0xce - invalid. */
919	/* Opcode 0x0f 0x38 0xcf - invalid. */
920	/* Opcode 0x66 0x0f 0x38 0xcf - invalid. */
921
922	/* Opcode 0x66 0x0f 0x38 0xd0 - invalid. */
923	/* Opcode 0x66 0x0f 0x38 0xd1 - invalid. */
924	/* Opcode 0x66 0x0f 0x38 0xd2 - invalid. */
925	/* Opcode 0x66 0x0f 0x38 0xd3 - invalid. */
926	/* Opcode 0x66 0x0f 0x38 0xd4 - invalid. */
927	/* Opcode 0x66 0x0f 0x38 0xd5 - invalid. */
928	/* Opcode 0x66 0x0f 0x38 0xd6 - invalid. */
929	/* Opcode 0x66 0x0f 0x38 0xd7 - invalid. */
930	/* Opcode 0x66 0x0f 0x38 0xd8 - invalid. */
931	/* Opcode 0x66 0x0f 0x38 0xd9 - invalid. */
932	/* Opcode 0x66 0x0f 0x38 0xda - invalid. */
933	/** Opcode 0x66 0x0f 0x38 0xdb. */
934	FNIEMOP_STUB(iemOp_aesimc_Vdq_Wdq);
935	/** Opcode 0x66 0x0f 0x38 0xdc. */
936	FNIEMOP_STUB(iemOp_aesenc_Vdq_Wdq);
937	/** Opcode 0x66 0x0f 0x38 0xdd. */
938	FNIEMOP_STUB(iemOp_aesenclast_Vdq_Wdq);
939	/** Opcode 0x66 0x0f 0x38 0xde. */
940	FNIEMOP_STUB(iemOp_aesdec_Vdq_Wdq);
941	/** Opcode 0x66 0x0f 0x38 0xdf. */
942	FNIEMOP_STUB(iemOp_aesdeclast_Vdq_Wdq);
943
944	/* Opcode 0x66 0x0f 0x38 0xe0 - invalid. */
945	/* Opcode 0x66 0x0f 0x38 0xe1 - invalid. */
946	/* Opcode 0x66 0x0f 0x38 0xe2 - invalid. */
947	/* Opcode 0x66 0x0f 0x38 0xe3 - invalid. */
948	/* Opcode 0x66 0x0f 0x38 0xe4 - invalid. */
949	/* Opcode 0x66 0x0f 0x38 0xe5 - invalid. */
950	/* Opcode 0x66 0x0f 0x38 0xe6 - invalid. */
951	/* Opcode 0x66 0x0f 0x38 0xe7 - invalid. */
952	/* Opcode 0x66 0x0f 0x38 0xe8 - invalid. */
953	/* Opcode 0x66 0x0f 0x38 0xe9 - invalid. */
954	/* Opcode 0x66 0x0f 0x38 0xea - invalid. */
955	/* Opcode 0x66 0x0f 0x38 0xeb - invalid. */
956	/* Opcode 0x66 0x0f 0x38 0xec - invalid. */
957	/* Opcode 0x66 0x0f 0x38 0xed - invalid. */
958	/* Opcode 0x66 0x0f 0x38 0xee - invalid. */
959	/* Opcode 0x66 0x0f 0x38 0xef - invalid. */
960
961
962	/** Opcode 0x0f 0x38 0xf0. */
963	FNIEMOP_STUB(iemOp_movbe_Gy_My);
964	/** Opcode 0x66 0x0f 0x38 0xf0. */
965	FNIEMOP_STUB(iemOp_movbe_Gw_Mw);
966	/* Opcode 0xf3 0x0f 0x38 0xf0 - invalid. */
967
968
969	/** Opcode 0xf2 0x0f 0x38 0xf0. */
970	FNIEMOP_DEF(iemOp_crc32_Gd_Eb)
971	{
972	IEMOP_MNEMONIC2(RM, CRC32, crc32, Gd, Eb, DISOPTYPE_HARMLESS, 0);
973	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42)
974	return iemOp_InvalidNeedRM(pVCpu);
975
976	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
977	if (IEM_IS_MODRM_REG_MODE(bRm))
978	{
979	/*
980	* Register, register.
981	*/
982	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
983	IEM_MC_BEGIN(2, 0);
984	IEM_MC_ARG(uint32_t *, puDst, 0);
985	IEM_MC_ARG(uint8_t, uSrc, 1);
986	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
987	IEM_MC_FETCH_GREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
988	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback), puDst, uSrc);
989	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
990	IEM_MC_ADVANCE_RIP();
991	IEM_MC_END();
992	}
993	else
994	{
995	/*
996	* Register, memory.
997	*/
998	IEM_MC_BEGIN(2, 1);
999	IEM_MC_ARG(uint32_t *, puDst, 0);
1000	IEM_MC_ARG(uint8_t, uSrc, 1);
1001	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1002
1003	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1004	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1005	IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1006
1007	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1008	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback), puDst, uSrc);
1009	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1010
1011	IEM_MC_ADVANCE_RIP();
1012	IEM_MC_END();
1013	}
1014	return VINF_SUCCESS;
1015	}
1016
1017
1018	/** Opcode 0x0f 0x38 0xf1. */
1019	FNIEMOP_STUB(iemOp_movbe_My_Gy);
1020	/** Opcode 0x66 0x0f 0x38 0xf1. */
1021	FNIEMOP_STUB(iemOp_movbe_Mw_Gw);
1022	/* Opcode 0xf3 0x0f 0x38 0xf1 - invalid. */
1023
1024
1025	/** Opcode 0xf2 0x0f 0x38 0xf1. */
1026	FNIEMOP_DEF(iemOp_crc32_Gv_Ev)
1027	{
1028	IEMOP_MNEMONIC2(RM, CRC32, crc32, Gd, Ev, DISOPTYPE_HARMLESS, 0);
1029	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42)
1030	return iemOp_InvalidNeedRM(pVCpu);
1031
1032	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1033	if (IEM_IS_MODRM_REG_MODE(bRm))
1034	{
1035	/*
1036	* Register, register.
1037	*/
1038	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1039	switch (pVCpu->iem.s.enmEffOpSize)
1040	{
1041	case IEMMODE_16BIT:
1042	IEM_MC_BEGIN(2, 0);
1043	IEM_MC_ARG(uint32_t *, puDst, 0);
1044	IEM_MC_ARG(uint16_t, uSrc, 1);
1045	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1046	IEM_MC_FETCH_GREG_U16(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1047	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback),
1048	puDst, uSrc);
1049	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1050	IEM_MC_ADVANCE_RIP();
1051	IEM_MC_END();
1052	return VINF_SUCCESS;
1053
1054	case IEMMODE_32BIT:
1055	IEM_MC_BEGIN(2, 0);
1056	IEM_MC_ARG(uint32_t *, puDst, 0);
1057	IEM_MC_ARG(uint32_t, uSrc, 1);
1058	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1059	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1060	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback),
1061	puDst, uSrc);
1062	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1063	IEM_MC_ADVANCE_RIP();
1064	IEM_MC_END();
1065	return VINF_SUCCESS;
1066
1067	case IEMMODE_64BIT:
1068	IEM_MC_BEGIN(2, 0);
1069	IEM_MC_ARG(uint32_t *, puDst, 0);
1070	IEM_MC_ARG(uint64_t, uSrc, 1);
1071	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1072	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1073	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback),
1074	puDst, uSrc);
1075	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1076	IEM_MC_ADVANCE_RIP();
1077	IEM_MC_END();
1078	return VINF_SUCCESS;
1079
1080	IEM_NOT_REACHED_DEFAULT_CASE_RET();
1081	}
1082	}
1083	else
1084	{
1085	/*
1086	* Register, memory.
1087	*/
1088	switch (pVCpu->iem.s.enmEffOpSize)
1089	{
1090	case IEMMODE_16BIT:
1091	IEM_MC_BEGIN(2, 1);
1092	IEM_MC_ARG(uint32_t *, puDst, 0);
1093	IEM_MC_ARG(uint16_t, uSrc, 1);
1094	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1095
1096	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1097	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1098	IEM_MC_FETCH_MEM_U16(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1099
1100	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1101	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback),
1102	puDst, uSrc);
1103	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1104
1105	IEM_MC_ADVANCE_RIP();
1106	IEM_MC_END();
1107	return VINF_SUCCESS;
1108
1109	case IEMMODE_32BIT:
1110	IEM_MC_BEGIN(2, 1);
1111	IEM_MC_ARG(uint32_t *, puDst, 0);
1112	IEM_MC_ARG(uint32_t, uSrc, 1);
1113	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1114
1115	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1116	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1117	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1118
1119	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1120	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback),
1121	puDst, uSrc);
1122	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1123
1124	IEM_MC_ADVANCE_RIP();
1125	IEM_MC_END();
1126	return VINF_SUCCESS;
1127
1128	case IEMMODE_64BIT:
1129	IEM_MC_BEGIN(2, 1);
1130	IEM_MC_ARG(uint32_t *, puDst, 0);
1131	IEM_MC_ARG(uint64_t, uSrc, 1);
1132	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1133
1134	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1135	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1136	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1137
1138	IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1139	IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback),
1140	puDst, uSrc);
1141	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1142
1143	IEM_MC_ADVANCE_RIP();
1144	IEM_MC_END();
1145	return VINF_SUCCESS;
1146
1147	IEM_NOT_REACHED_DEFAULT_CASE_RET();
1148	}
1149	}
1150	}
1151
1152
1153	/* Opcode 0x0f 0x38 0xf2 - invalid (vex only). */
1154	/* Opcode 0x66 0x0f 0x38 0xf2 - invalid. */
1155	/* Opcode 0xf3 0x0f 0x38 0xf2 - invalid. */
1156	/* Opcode 0xf2 0x0f 0x38 0xf2 - invalid. */
1157
1158	/* Opcode 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
1159	/* Opcode 0x66 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
1160	/* Opcode 0xf3 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
1161	/* Opcode 0xf2 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
1162
1163	/* Opcode 0x0f 0x38 0xf4 - invalid. */
1164	/* Opcode 0x66 0x0f 0x38 0xf4 - invalid. */
1165	/* Opcode 0xf3 0x0f 0x38 0xf4 - invalid. */
1166	/* Opcode 0xf2 0x0f 0x38 0xf4 - invalid. */
1167
1168	/* Opcode 0x0f 0x38 0xf5 - invalid (vex only). */
1169	/* Opcode 0x66 0x0f 0x38 0xf5 - invalid. */
1170	/* Opcode 0xf3 0x0f 0x38 0xf5 - invalid (vex only). */
1171	/* Opcode 0xf2 0x0f 0x38 0xf5 - invalid (vex only). */
1172
1173	/* Opcode 0x0f 0x38 0xf6 - invalid. */
1174	/** Opcode 0x66 0x0f 0x38 0xf6. */
1175	FNIEMOP_STUB(iemOp_adcx_Gy_Ey);
1176	/** Opcode 0xf3 0x0f 0x38 0xf6. */
1177	FNIEMOP_STUB(iemOp_adox_Gy_Ey);
1178	/* Opcode 0xf2 0x0f 0x38 0xf6 - invalid (vex only). */
1179
1180	/* Opcode 0x0f 0x38 0xf7 - invalid (vex only). */
1181	/* Opcode 0x66 0x0f 0x38 0xf7 - invalid (vex only). */
1182	/* Opcode 0xf3 0x0f 0x38 0xf7 - invalid (vex only). */
1183	/* Opcode 0xf2 0x0f 0x38 0xf7 - invalid (vex only). */
1184
1185	/* Opcode 0x0f 0x38 0xf8 - invalid. */
1186	/* Opcode 0x66 0x0f 0x38 0xf8 - invalid. */
1187	/* Opcode 0xf3 0x0f 0x38 0xf8 - invalid. */
1188	/* Opcode 0xf2 0x0f 0x38 0xf8 - invalid. */
1189
1190	/* Opcode 0x0f 0x38 0xf9 - invalid. */
1191	/* Opcode 0x66 0x0f 0x38 0xf9 - invalid. */
1192	/* Opcode 0xf3 0x0f 0x38 0xf9 - invalid. */
1193	/* Opcode 0xf2 0x0f 0x38 0xf9 - invalid. */
1194
1195	/* Opcode 0x0f 0x38 0xfa - invalid. */
1196	/* Opcode 0x66 0x0f 0x38 0xfa - invalid. */
1197	/* Opcode 0xf3 0x0f 0x38 0xfa - invalid. */
1198	/* Opcode 0xf2 0x0f 0x38 0xfa - invalid. */
1199
1200	/* Opcode 0x0f 0x38 0xfb - invalid. */
1201	/* Opcode 0x66 0x0f 0x38 0xfb - invalid. */
1202	/* Opcode 0xf3 0x0f 0x38 0xfb - invalid. */
1203	/* Opcode 0xf2 0x0f 0x38 0xfb - invalid. */
1204
1205	/* Opcode 0x0f 0x38 0xfc - invalid. */
1206	/* Opcode 0x66 0x0f 0x38 0xfc - invalid. */
1207	/* Opcode 0xf3 0x0f 0x38 0xfc - invalid. */
1208	/* Opcode 0xf2 0x0f 0x38 0xfc - invalid. */
1209
1210	/* Opcode 0x0f 0x38 0xfd - invalid. */
1211	/* Opcode 0x66 0x0f 0x38 0xfd - invalid. */
1212	/* Opcode 0xf3 0x0f 0x38 0xfd - invalid. */
1213	/* Opcode 0xf2 0x0f 0x38 0xfd - invalid. */
1214
1215	/* Opcode 0x0f 0x38 0xfe - invalid. */
1216	/* Opcode 0x66 0x0f 0x38 0xfe - invalid. */
1217	/* Opcode 0xf3 0x0f 0x38 0xfe - invalid. */
1218	/* Opcode 0xf2 0x0f 0x38 0xfe - invalid. */
1219
1220	/* Opcode 0x0f 0x38 0xff - invalid. */
1221	/* Opcode 0x66 0x0f 0x38 0xff - invalid. */
1222	/* Opcode 0xf3 0x0f 0x38 0xff - invalid. */
1223	/* Opcode 0xf2 0x0f 0x38 0xff - invalid. */
1224
1225
1226	/**
1227	* Three byte opcode map, first two bytes are 0x0f 0x38.
1228	* @sa g_apfnVexMap2
1229	*/
1230	IEM_STATIC const PFNIEMOP g_apfnThreeByte0f38[] =
1231	{
1232	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1233	/* 0x00 */ iemOp_pshufb_Pq_Qq, iemOp_pshufb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1234	/* 0x01 */ iemOp_phaddw_Pq_Qq, iemOp_phaddw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1235	/* 0x02 */ iemOp_phaddd_Pq_Qq, iemOp_phaddd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1236	/* 0x03 */ iemOp_phaddsw_Pq_Qq, iemOp_phaddsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1237	/* 0x04 */ iemOp_pmaddubsw_Pq_Qq, iemOp_pmaddubsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1238	/* 0x05 */ iemOp_phsubw_Pq_Qq, iemOp_phsubw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1239	/* 0x06 */ iemOp_phsubd_Pq_Qq, iemOp_phsubdq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1240	/* 0x07 */ iemOp_phsubsw_Pq_Qq, iemOp_phsubsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1241	/* 0x08 */ iemOp_psignb_Pq_Qq, iemOp_psignb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1242	/* 0x09 */ iemOp_psignw_Pq_Qq, iemOp_psignw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1243	/* 0x0a */ iemOp_psignd_Pq_Qq, iemOp_psignd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1244	/* 0x0b */ iemOp_pmulhrsw_Pq_Qq, iemOp_pmulhrsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1245	/* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
1246	/* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
1247	/* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
1248	/* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
1249
1250	/* 0x10 */ iemOp_InvalidNeedRM, iemOp_pblendvb_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1251	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
1252	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
1253	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
1254	/* 0x14 */ iemOp_InvalidNeedRM, iemOp_blendvps_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1255	/* 0x15 */ iemOp_InvalidNeedRM, iemOp_blendvpd_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1256	/* 0x16 */ IEMOP_X4(iemOp_InvalidNeedRM),
1257	/* 0x17 */ iemOp_InvalidNeedRM, iemOp_ptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1258	/* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
1259	/* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
1260	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
1261	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
1262	/* 0x1c */ iemOp_pabsb_Pq_Qq, iemOp_pabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1263	/* 0x1d */ iemOp_pabsw_Pq_Qq, iemOp_pabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1264	/* 0x1e */ iemOp_pabsd_Pq_Qq, iemOp_pabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1265	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
1266
1267	/* 0x20 */ iemOp_InvalidNeedRM, iemOp_pmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1268	/* 0x21 */ iemOp_InvalidNeedRM, iemOp_pmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1269	/* 0x22 */ iemOp_InvalidNeedRM, iemOp_pmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1270	/* 0x23 */ iemOp_InvalidNeedRM, iemOp_pmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1271	/* 0x24 */ iemOp_InvalidNeedRM, iemOp_pmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1272	/* 0x25 */ iemOp_InvalidNeedRM, iemOp_pmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1273	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
1274	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
1275	/* 0x28 */ iemOp_InvalidNeedRM, iemOp_pmuldq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1276	/* 0x29 */ iemOp_InvalidNeedRM, iemOp_pcmpeqq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1277	/* 0x2a */ iemOp_InvalidNeedRM, iemOp_movntdqa_Vdq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1278	/* 0x2b */ iemOp_InvalidNeedRM, iemOp_packusdw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1279	/* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRM),
1280	/* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRM),
1281	/* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRM),
1282	/* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRM),
1283
1284	/* 0x30 */ iemOp_InvalidNeedRM, iemOp_pmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1285	/* 0x31 */ iemOp_InvalidNeedRM, iemOp_pmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1286	/* 0x32 */ iemOp_InvalidNeedRM, iemOp_pmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1287	/* 0x33 */ iemOp_InvalidNeedRM, iemOp_pmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1288	/* 0x34 */ iemOp_InvalidNeedRM, iemOp_pmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1289	/* 0x35 */ iemOp_InvalidNeedRM, iemOp_pmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1290	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
1291	/* 0x37 */ iemOp_InvalidNeedRM, iemOp_pcmpgtq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1292	/* 0x38 */ iemOp_InvalidNeedRM, iemOp_pminsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1293	/* 0x39 */ iemOp_InvalidNeedRM, iemOp_pminsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1294	/* 0x3a */ iemOp_InvalidNeedRM, iemOp_pminuw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1295	/* 0x3b */ iemOp_InvalidNeedRM, iemOp_pminud_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1296	/* 0x3c */ iemOp_InvalidNeedRM, iemOp_pmaxsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1297	/* 0x3d */ iemOp_InvalidNeedRM, iemOp_pmaxsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1298	/* 0x3e */ iemOp_InvalidNeedRM, iemOp_pmaxuw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1299	/* 0x3f */ iemOp_InvalidNeedRM, iemOp_pmaxud_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1300
1301	/* 0x40 */ iemOp_InvalidNeedRM, iemOp_pmulld_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1302	/* 0x41 */ iemOp_InvalidNeedRM, iemOp_phminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1303	/* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
1304	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
1305	/* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
1306	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
1307	/* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
1308	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
1309	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
1310	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
1311	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
1312	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
1313	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
1314	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
1315	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
1316	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
1317
1318	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
1319	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
1320	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
1321	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
1322	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
1323	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
1324	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
1325	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
1326	/* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRM),
1327	/* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRM),
1328	/* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRM),
1329	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
1330	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
1331	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
1332	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
1333	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
1334
1335	/* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
1336	/* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
1337	/* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
1338	/* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
1339	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
1340	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
1341	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
1342	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
1343	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
1344	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
1345	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
1346	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
1347	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
1348	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
1349	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
1350	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
1351
1352	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
1353	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
1354	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
1355	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
1356	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
1357	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
1358	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
1359	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
1360	/* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
1361	/* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
1362	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
1363	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
1364	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
1365	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
1366	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
1367	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
1368
1369	/* 0x80 */ iemOp_InvalidNeedRM, iemOp_invept_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1370	/* 0x81 */ iemOp_InvalidNeedRM, iemOp_invvpid_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1371	/* 0x82 */ iemOp_InvalidNeedRM, iemOp_invpcid_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1372	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
1373	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
1374	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
1375	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
1376	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
1377	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
1378	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
1379	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
1380	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
1381	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
1382	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
1383	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
1384	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
1385
1386	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
1387	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
1388	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
1389	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
1390	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
1391	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
1392	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
1393	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
1394	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
1395	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
1396	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
1397	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
1398	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
1399	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
1400	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
1401	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
1402
1403	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1404	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1405	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1406	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1407	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1408	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1409	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1410	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1411	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1412	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1413	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
1414	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
1415	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
1416	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
1417	/* 0xae */ IEMOP_X4(iemOp_InvalidNeedRM),
1418	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
1419
1420	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1421	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1422	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1423	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1424	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1425	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1426	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1427	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1428	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1429	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1430	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
1431	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
1432	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
1433	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
1434	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
1435	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
1436
1437	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1438	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1439	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1440	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1441	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1442	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1443	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1444	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1445	/* 0xc8 */ iemOp_sha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1446	/* 0xc9 */ iemOp_sha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1447	/* 0xca */ iemOp_sha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1448	/* 0xcb */ iemOp_sha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1449	/* 0xcc */ iemOp_sha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1450	/* 0xcd */ iemOp_sha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1451	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
1452	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
1453
1454	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1455	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1456	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1457	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1458	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1459	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1460	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1461	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1462	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1463	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1464	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
1465	/* 0xdb */ iemOp_InvalidNeedRM, iemOp_aesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1466	/* 0xdc */ iemOp_InvalidNeedRM, iemOp_aesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1467	/* 0xdd */ iemOp_InvalidNeedRM, iemOp_aesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1468	/* 0xde */ iemOp_InvalidNeedRM, iemOp_aesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1469	/* 0xdf */ iemOp_InvalidNeedRM, iemOp_aesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1470
1471	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1472	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1473	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1474	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1475	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1476	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1477	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1478	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1479	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1480	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1481	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
1482	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
1483	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
1484	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
1485	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
1486	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
1487
1488	/* 0xf0 */ iemOp_movbe_Gy_My, iemOp_movbe_Gw_Mw, iemOp_InvalidNeedRM, iemOp_crc32_Gd_Eb,
1489	/* 0xf1 */ iemOp_movbe_My_Gy, iemOp_movbe_Mw_Gw, iemOp_InvalidNeedRM, iemOp_crc32_Gv_Ev,
1490	/* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1491	/* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1492	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1493	/* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1494	/* 0xf6 */ iemOp_InvalidNeedRM, iemOp_adcx_Gy_Ey, iemOp_adox_Gy_Ey, iemOp_InvalidNeedRM,
1495	/* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1496	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1497	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1498	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
1499	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
1500	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
1501	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
1502	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
1503	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
1504	};
1505	AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f38) == 1024);
1506
1507	/** @} */
1508

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f38.cpp.h@ 96020

Download in other formats: