VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f38.cpp.h@ 99748

Last change on this file since 99748 was 99342, checked in by vboxsync, 21 months ago

VMM/IEM: IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT -> IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT, since the CPUID check was removed they are identical. bugref:10369
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File size: 98.8 KB
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1/* $Id: IEMAllInstructionsThree0f38.cpp.h 99342 2023-04-07 12:43:12Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstructionsVexMap2.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name Three byte opcodes with first two bytes 0x0f 0x38
33 * @{
34 */
35
36/**
37 * Common worker for MMX instructions on the form:
38 * pxxx mm1, mm2/mem64
39 * that was introduced with SSE3.
40 */
41FNIEMOP_DEF_1(iemOpCommonMmx_FullFull_To_Full_Ssse3, PFNIEMAIMPLMEDIAF2U64, pfnU64)
42{
43 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
44 if (IEM_IS_MODRM_REG_MODE(bRm))
45 {
46 /*
47 * MMX, MMX.
48 */
49 /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
50 /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
51 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
52 IEM_MC_BEGIN(2, 0);
53 IEM_MC_ARG(uint64_t *, pDst, 0);
54 IEM_MC_ARG(uint64_t const *, pSrc, 1);
55 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
56 IEM_MC_PREPARE_FPU_USAGE();
57 IEM_MC_FPU_TO_MMX_MODE();
58
59 IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
60 IEM_MC_REF_MREG_U64_CONST(pSrc, IEM_GET_MODRM_RM_8(bRm));
61 IEM_MC_CALL_MMX_AIMPL_2(pfnU64, pDst, pSrc);
62 IEM_MC_MODIFIED_MREG_BY_REF(pDst);
63
64 IEM_MC_ADVANCE_RIP_AND_FINISH();
65 IEM_MC_END();
66 }
67 else
68 {
69 /*
70 * MMX, [mem64].
71 */
72 IEM_MC_BEGIN(2, 2);
73 IEM_MC_ARG(uint64_t *, pDst, 0);
74 IEM_MC_LOCAL(uint64_t, uSrc);
75 IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
76 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
77
78 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
79 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
80 IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
81 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
82
83 IEM_MC_PREPARE_FPU_USAGE();
84 IEM_MC_FPU_TO_MMX_MODE();
85
86 IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
87 IEM_MC_CALL_MMX_AIMPL_2(pfnU64, pDst, pSrc);
88 IEM_MC_MODIFIED_MREG_BY_REF(pDst);
89
90 IEM_MC_ADVANCE_RIP_AND_FINISH();
91 IEM_MC_END();
92 }
93}
94
95
96/**
97 * Common worker for SSSE3 instructions on the forms:
98 * pxxx xmm1, xmm2/mem128
99 *
100 * Proper alignment of the 128-bit operand is enforced.
101 * Exceptions type 4. SSSE3 cpuid checks.
102 *
103 * @sa iemOpCommonSse2_FullFull_To_Full
104 */
105FNIEMOP_DEF_1(iemOpCommonSsse3_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128)
106{
107 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
108 if (IEM_IS_MODRM_REG_MODE(bRm))
109 {
110 /*
111 * Register, register.
112 */
113 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
114 IEM_MC_BEGIN(2, 0);
115 IEM_MC_ARG(PRTUINT128U, puDst, 0);
116 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
117 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
118 IEM_MC_PREPARE_SSE_USAGE();
119 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
120 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
121 IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
122 IEM_MC_ADVANCE_RIP_AND_FINISH();
123 IEM_MC_END();
124 }
125 else
126 {
127 /*
128 * Register, memory.
129 */
130 IEM_MC_BEGIN(2, 2);
131 IEM_MC_ARG(PRTUINT128U, puDst, 0);
132 IEM_MC_LOCAL(RTUINT128U, uSrc);
133 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
134 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
135
136 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
137 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSsse3);
138 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
139 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
140
141 IEM_MC_PREPARE_SSE_USAGE();
142 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
143 IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
144
145 IEM_MC_ADVANCE_RIP_AND_FINISH();
146 IEM_MC_END();
147 }
148}
149
150
151/**
152 * Common worker for SSE4.1 instructions on the forms:
153 * pxxx xmm1, xmm2/mem128
154 *
155 * Proper alignment of the 128-bit operand is enforced.
156 * Exceptions type 4. SSE4.1 cpuid checks.
157 *
158 * @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
159 * iemOpCommonSse42_FullFull_To_Full
160 */
161FNIEMOP_DEF_1(iemOpCommonSse41_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128)
162{
163 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
164 if (IEM_IS_MODRM_REG_MODE(bRm))
165 {
166 /*
167 * Register, register.
168 */
169 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
170 IEM_MC_BEGIN(2, 0);
171 IEM_MC_ARG(PRTUINT128U, puDst, 0);
172 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
173 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
174 IEM_MC_PREPARE_SSE_USAGE();
175 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
176 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
177 IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
178 IEM_MC_ADVANCE_RIP_AND_FINISH();
179 IEM_MC_END();
180 }
181 else
182 {
183 /*
184 * Register, memory.
185 */
186 IEM_MC_BEGIN(2, 2);
187 IEM_MC_ARG(PRTUINT128U, puDst, 0);
188 IEM_MC_LOCAL(RTUINT128U, uSrc);
189 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
190 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
191
192 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
193 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
194 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
195 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
196
197 IEM_MC_PREPARE_SSE_USAGE();
198 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
199 IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
200
201 IEM_MC_ADVANCE_RIP_AND_FINISH();
202 IEM_MC_END();
203 }
204}
205
206
207/**
208 * Common worker for SSE4.1 instructions on the forms:
209 * pxxx xmm1, xmm2/mem128
210 *
211 * Proper alignment of the 128-bit operand is enforced.
212 * Exceptions type 4. SSE4.1 cpuid checks.
213 *
214 * Unlike iemOpCommonSse41_FullFull_To_Full, the @a pfnU128 worker function
215 * takes no FXSAVE state, just the operands.
216 *
217 * @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
218 * iemOpCommonSse41_FullFull_To_Full, iemOpCommonSse42_FullFull_To_Full
219 */
220FNIEMOP_DEF_1(iemOpCommonSse41Opt_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU128)
221{
222 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
223 if (IEM_IS_MODRM_REG_MODE(bRm))
224 {
225 /*
226 * Register, register.
227 */
228 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
229 IEM_MC_BEGIN(2, 0);
230 IEM_MC_ARG(PRTUINT128U, puDst, 0);
231 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
232 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
233 IEM_MC_PREPARE_SSE_USAGE();
234 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
235 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
236 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
237 IEM_MC_ADVANCE_RIP_AND_FINISH();
238 IEM_MC_END();
239 }
240 else
241 {
242 /*
243 * Register, memory.
244 */
245 IEM_MC_BEGIN(2, 2);
246 IEM_MC_ARG(PRTUINT128U, puDst, 0);
247 IEM_MC_LOCAL(RTUINT128U, uSrc);
248 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
249 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
250
251 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
252 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
253 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
254 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
255
256 IEM_MC_PREPARE_SSE_USAGE();
257 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
258 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
259
260 IEM_MC_ADVANCE_RIP_AND_FINISH();
261 IEM_MC_END();
262 }
263}
264
265
266/**
267 * Common worker for SSE4.2 instructions on the forms:
268 * pxxx xmm1, xmm2/mem128
269 *
270 * Proper alignment of the 128-bit operand is enforced.
271 * Exceptions type 4. SSE4.2 cpuid checks.
272 *
273 * @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
274 * iemOpCommonSse41_FullFull_To_Full
275 */
276FNIEMOP_DEF_1(iemOpCommonSse42_FullFull_To_Full, PFNIEMAIMPLMEDIAF2U128, pfnU128)
277{
278 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
279 if (IEM_IS_MODRM_REG_MODE(bRm))
280 {
281 /*
282 * Register, register.
283 */
284 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
285 IEM_MC_BEGIN(2, 0);
286 IEM_MC_ARG(PRTUINT128U, puDst, 0);
287 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
288 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
289 IEM_MC_PREPARE_SSE_USAGE();
290 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
291 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
292 IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
293 IEM_MC_ADVANCE_RIP_AND_FINISH();
294 IEM_MC_END();
295 }
296 else
297 {
298 /*
299 * Register, memory.
300 */
301 IEM_MC_BEGIN(2, 2);
302 IEM_MC_ARG(PRTUINT128U, puDst, 0);
303 IEM_MC_LOCAL(RTUINT128U, uSrc);
304 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
305 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
306
307 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
308 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42);
309 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
310 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
311
312 IEM_MC_PREPARE_SSE_USAGE();
313 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
314 IEM_MC_CALL_SSE_AIMPL_2(pfnU128, puDst, puSrc);
315
316 IEM_MC_ADVANCE_RIP_AND_FINISH();
317 IEM_MC_END();
318 }
319}
320
321
322/**
323 * Common worker for SSE-style AES-NI instructions of the form:
324 * aesxxx xmm1, xmm2/mem128
325 *
326 * Proper alignment of the 128-bit operand is enforced.
327 * Exceptions type 4. AES-NI cpuid checks.
328 *
329 * Unlike iemOpCommonSse41_FullFull_To_Full, the @a pfnU128 worker function
330 * takes no FXSAVE state, just the operands.
331 *
332 * @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
333 * iemOpCommonSse41_FullFull_To_Full, iemOpCommonSse42_FullFull_To_Full,
334 * iemOpCommonSha_FullFull_To_Full
335 */
336FNIEMOP_DEF_1(iemOpCommonAesNi_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU128)
337{
338 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
339 if (IEM_IS_MODRM_REG_MODE(bRm))
340 {
341 /*
342 * Register, register.
343 */
344 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
345 IEM_MC_BEGIN(2, 0);
346 IEM_MC_ARG(PRTUINT128U, puDst, 0);
347 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
348 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
349 IEM_MC_PREPARE_SSE_USAGE();
350 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
351 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
352 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
353 IEM_MC_ADVANCE_RIP_AND_FINISH();
354 IEM_MC_END();
355 }
356 else
357 {
358 /*
359 * Register, memory.
360 */
361 IEM_MC_BEGIN(2, 2);
362 IEM_MC_ARG(PRTUINT128U, puDst, 0);
363 IEM_MC_LOCAL(RTUINT128U, uSrc);
364 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
365 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
366
367 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
368 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fAesNi);
369 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
370 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
371
372 IEM_MC_PREPARE_SSE_USAGE();
373 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
374 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
375
376 IEM_MC_ADVANCE_RIP_AND_FINISH();
377 IEM_MC_END();
378 }
379}
380
381
382/**
383 * Common worker for SSE-style SHA instructions of the form:
384 * shaxxx xmm1, xmm2/mem128
385 *
386 * Proper alignment of the 128-bit operand is enforced.
387 * Exceptions type 4. SHA cpuid checks.
388 *
389 * Unlike iemOpCommonSse41_FullFull_To_Full, the @a pfnU128 worker function
390 * takes no FXSAVE state, just the operands.
391 *
392 * @sa iemOpCommonSse2_FullFull_To_Full, iemOpCommonSsse3_FullFull_To_Full,
393 * iemOpCommonSse41_FullFull_To_Full, iemOpCommonSse42_FullFull_To_Full,
394 * iemOpCommonAesNi_FullFull_To_Full
395 */
396FNIEMOP_DEF_1(iemOpCommonSha_FullFull_To_Full, PFNIEMAIMPLMEDIAOPTF2U128, pfnU128)
397{
398 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
399 if (IEM_IS_MODRM_REG_MODE(bRm))
400 {
401 /*
402 * Register, register.
403 */
404 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
405 IEM_MC_BEGIN(2, 0);
406 IEM_MC_ARG(PRTUINT128U, puDst, 0);
407 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
408 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
409 IEM_MC_PREPARE_SSE_USAGE();
410 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
411 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
412 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
413 IEM_MC_ADVANCE_RIP_AND_FINISH();
414 IEM_MC_END();
415 }
416 else
417 {
418 /*
419 * Register, memory.
420 */
421 IEM_MC_BEGIN(2, 2);
422 IEM_MC_ARG(PRTUINT128U, puDst, 0);
423 IEM_MC_LOCAL(RTUINT128U, uSrc);
424 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
425 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
426
427 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
428 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
429 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
430 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
431
432 IEM_MC_PREPARE_SSE_USAGE();
433 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
434 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc);
435
436 IEM_MC_ADVANCE_RIP_AND_FINISH();
437 IEM_MC_END();
438 }
439}
440
441
442/** Opcode 0x0f 0x38 0x00. */
443FNIEMOP_DEF(iemOp_pshufb_Pq_Qq)
444{
445 IEMOP_MNEMONIC2(RM, PSHUFB, pshufb, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
446 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
447 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pshufb_u64,&iemAImpl_pshufb_u64_fallback));
448}
449
450
451/** Opcode 0x66 0x0f 0x38 0x00. */
452FNIEMOP_DEF(iemOp_pshufb_Vx_Wx)
453{
454 IEMOP_MNEMONIC2(RM, PSHUFB, pshufb, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
455 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
456 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback));
457
458}
459
460
461/* Opcode 0x0f 0x38 0x01. */
462FNIEMOP_DEF(iemOp_phaddw_Pq_Qq)
463{
464 IEMOP_MNEMONIC2(RM, PHADDW, phaddw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
465 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
466 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddw_u64,&iemAImpl_phaddw_u64_fallback));
467}
468
469
470/** Opcode 0x66 0x0f 0x38 0x01. */
471FNIEMOP_DEF(iemOp_phaddw_Vx_Wx)
472{
473 IEMOP_MNEMONIC2(RM, PHADDW, phaddw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
474 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
475 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback));
476
477}
478
479
480/** Opcode 0x0f 0x38 0x02. */
481FNIEMOP_DEF(iemOp_phaddd_Pq_Qq)
482{
483 IEMOP_MNEMONIC2(RM, PHADDD, phaddd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
484 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
485 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddd_u64,&iemAImpl_phaddd_u64_fallback));
486}
487
488
489/** Opcode 0x66 0x0f 0x38 0x02. */
490FNIEMOP_DEF(iemOp_phaddd_Vx_Wx)
491{
492 IEMOP_MNEMONIC2(RM, PHADDD, phaddd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
493 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
494 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback));
495
496}
497
498
499/** Opcode 0x0f 0x38 0x03. */
500FNIEMOP_DEF(iemOp_phaddsw_Pq_Qq)
501{
502 IEMOP_MNEMONIC2(RM, PHADDSW, phaddsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
503 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
504 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddsw_u64,&iemAImpl_phaddsw_u64_fallback));
505}
506
507
508/** Opcode 0x66 0x0f 0x38 0x03. */
509FNIEMOP_DEF(iemOp_phaddsw_Vx_Wx)
510{
511 IEMOP_MNEMONIC2(RM, PHADDSW, phaddsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
512 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
513 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback));
514
515}
516
517
518/** Opcode 0x0f 0x38 0x04. */
519FNIEMOP_DEF(iemOp_pmaddubsw_Pq_Qq)
520{
521 IEMOP_MNEMONIC2(RM, PMADDUBSW, pmaddubsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
522 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
523 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmaddubsw_u64, &iemAImpl_pmaddubsw_u64_fallback));
524}
525
526
527/** Opcode 0x66 0x0f 0x38 0x04. */
528FNIEMOP_DEF(iemOp_pmaddubsw_Vx_Wx)
529{
530 IEMOP_MNEMONIC2(RM, PMADDUBSW, pmaddubsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
531 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
532 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback));
533
534}
535
536
537/** Opcode 0x0f 0x38 0x05. */
538FNIEMOP_DEF(iemOp_phsubw_Pq_Qq)
539{
540 IEMOP_MNEMONIC2(RM, PHSUBW, phsubw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
541 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
542 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubw_u64,&iemAImpl_phsubw_u64_fallback));
543}
544
545
546/** Opcode 0x66 0x0f 0x38 0x05. */
547FNIEMOP_DEF(iemOp_phsubw_Vx_Wx)
548{
549 IEMOP_MNEMONIC2(RM, PHSUBW, phsubw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
550 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
551 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback));
552
553}
554
555
556/** Opcode 0x0f 0x38 0x06. */
557FNIEMOP_DEF(iemOp_phsubd_Pq_Qq)
558{
559 IEMOP_MNEMONIC2(RM, PHSUBD, phsubd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
560 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
561 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubd_u64,&iemAImpl_phsubd_u64_fallback));
562}
563
564
565
566/** Opcode 0x66 0x0f 0x38 0x06. */
567FNIEMOP_DEF(iemOp_phsubd_Vx_Wx)
568{
569 IEMOP_MNEMONIC2(RM, PHSUBD, phsubd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
570 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
571 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback));
572
573}
574
575
576/** Opcode 0x0f 0x38 0x07. */
577FNIEMOP_DEF(iemOp_phsubsw_Pq_Qq)
578{
579 IEMOP_MNEMONIC2(RM, PHSUBSW, phsubsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
580 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
581 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubsw_u64,&iemAImpl_phsubsw_u64_fallback));
582}
583
584
585/** Opcode 0x66 0x0f 0x38 0x07. */
586FNIEMOP_DEF(iemOp_phsubsw_Vx_Wx)
587{
588 IEMOP_MNEMONIC2(RM, PHSUBSW, phsubsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
589 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
590 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback));
591
592}
593
594
595/** Opcode 0x0f 0x38 0x08. */
596FNIEMOP_DEF(iemOp_psignb_Pq_Qq)
597{
598 IEMOP_MNEMONIC2(RM, PSIGNB, psignb, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
599 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
600 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignb_u64, &iemAImpl_psignb_u64_fallback));
601}
602
603
604/** Opcode 0x66 0x0f 0x38 0x08. */
605FNIEMOP_DEF(iemOp_psignb_Vx_Wx)
606{
607 IEMOP_MNEMONIC2(RM, PSIGNB, psignb, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
608 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
609 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback));
610
611}
612
613
614/** Opcode 0x0f 0x38 0x09. */
615FNIEMOP_DEF(iemOp_psignw_Pq_Qq)
616{
617 IEMOP_MNEMONIC2(RM, PSIGNW, psignw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
618 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
619 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignw_u64, &iemAImpl_psignw_u64_fallback));
620}
621
622
623/** Opcode 0x66 0x0f 0x38 0x09. */
624FNIEMOP_DEF(iemOp_psignw_Vx_Wx)
625{
626 IEMOP_MNEMONIC2(RM, PSIGNW, psignw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
627 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
628 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback));
629
630}
631
632
633/** Opcode 0x0f 0x38 0x0a. */
634FNIEMOP_DEF(iemOp_psignd_Pq_Qq)
635{
636 IEMOP_MNEMONIC2(RM, PSIGND, psignd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
637 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
638 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignd_u64, &iemAImpl_psignd_u64_fallback));
639}
640
641
642/** Opcode 0x66 0x0f 0x38 0x0a. */
643FNIEMOP_DEF(iemOp_psignd_Vx_Wx)
644{
645 IEMOP_MNEMONIC2(RM, PSIGND, psignd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
646 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
647 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback));
648
649}
650
651
652/** Opcode 0x0f 0x38 0x0b. */
653FNIEMOP_DEF(iemOp_pmulhrsw_Pq_Qq)
654{
655 IEMOP_MNEMONIC2(RM, PMULHRSW, pmulhrsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
656 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
657 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmulhrsw_u64, &iemAImpl_pmulhrsw_u64_fallback));
658}
659
660
661/** Opcode 0x66 0x0f 0x38 0x0b. */
662FNIEMOP_DEF(iemOp_pmulhrsw_Vx_Wx)
663{
664 IEMOP_MNEMONIC2(RM, PMULHRSW, pmulhrsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
665 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
666 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback));
667
668}
669
670
671/* Opcode 0x0f 0x38 0x0c - invalid. */
672/* Opcode 0x66 0x0f 0x38 0x0c - invalid (vex only). */
673/* Opcode 0x0f 0x38 0x0d - invalid. */
674/* Opcode 0x66 0x0f 0x38 0x0d - invalid (vex only). */
675/* Opcode 0x0f 0x38 0x0e - invalid. */
676/* Opcode 0x66 0x0f 0x38 0x0e - invalid (vex only). */
677/* Opcode 0x0f 0x38 0x0f - invalid. */
678/* Opcode 0x66 0x0f 0x38 0x0f - invalid (vex only). */
679
680
681/* Opcode 0x0f 0x38 0x10 - invalid */
682
683
684/** Body for the *blend* instructions. */
685#define IEMOP_BODY_P_BLEND_X(a_Instr) \
686 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
687 if (IEM_IS_MODRM_REG_MODE(bRm)) \
688 { \
689 /* \
690 * Register, register. \
691 */ \
692 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \
693 IEM_MC_BEGIN(3, 0); \
694 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
695 IEM_MC_ARG(PCRTUINT128U, puSrc, 1); \
696 IEM_MC_ARG(PCRTUINT128U, puMask, 2); \
697 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); \
698 IEM_MC_PREPARE_SSE_USAGE(); \
699 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
700 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
701 IEM_MC_REF_XREG_U128_CONST(puMask, 0); \
702 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSse41, \
703 iemAImpl_ ## a_Instr ## _u128, \
704 iemAImpl_ ## a_Instr ## _u128_fallback), \
705 puDst, puSrc, puMask); \
706 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
707 IEM_MC_END(); \
708 } \
709 else \
710 { \
711 /* \
712 * Register, memory. \
713 */ \
714 IEM_MC_BEGIN(3, 2); \
715 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
716 IEM_MC_LOCAL(RTUINT128U, uSrc); \
717 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
718 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1); \
719 IEM_MC_ARG(PCRTUINT128U, puMask, 2); \
720 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
721 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \
722 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); \
723 IEM_MC_PREPARE_SSE_USAGE(); \
724 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
725 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
726 IEM_MC_REF_XREG_U128_CONST(puMask, 0); \
727 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSse41, \
728 iemAImpl_ ## a_Instr ## _u128, \
729 iemAImpl_ ## a_Instr ## _u128_fallback), \
730 puDst, puSrc, puMask); \
731 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
732 IEM_MC_END(); \
733 } \
734 (void)0
735
736/** Opcode 0x66 0x0f 0x38 0x10 (legacy only). */
737FNIEMOP_DEF(iemOp_pblendvb_Vdq_Wdq)
738{
739 IEMOP_MNEMONIC2(RM, PBLENDVB, pblendvb, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES); /** @todo RM0 */
740 IEMOP_BODY_P_BLEND_X(pblendvb);
741}
742
743
744/* Opcode 0x0f 0x38 0x11 - invalid */
745/* Opcode 0x66 0x0f 0x38 0x11 - invalid */
746/* Opcode 0x0f 0x38 0x12 - invalid */
747/* Opcode 0x66 0x0f 0x38 0x12 - invalid */
748/* Opcode 0x0f 0x38 0x13 - invalid */
749/* Opcode 0x66 0x0f 0x38 0x13 - invalid (vex only). */
750/* Opcode 0x0f 0x38 0x14 - invalid */
751
752
753/** Opcode 0x66 0x0f 0x38 0x14 (legacy only). */
754FNIEMOP_DEF(iemOp_blendvps_Vdq_Wdq)
755{
756 IEMOP_MNEMONIC2(RM, BLENDVPS, blendvps, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES); /** @todo RM0 */
757 IEMOP_BODY_P_BLEND_X(blendvps);
758}
759
760
761/* Opcode 0x0f 0x38 0x15 - invalid */
762
763
764/** Opcode 0x66 0x0f 0x38 0x15 (legacy only). */
765FNIEMOP_DEF(iemOp_blendvpd_Vdq_Wdq)
766{
767 IEMOP_MNEMONIC2(RM, BLENDVPD, blendvpd, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES); /** @todo RM0 */
768 IEMOP_BODY_P_BLEND_X(blendvpd);
769}
770
771
772/* Opcode 0x0f 0x38 0x16 - invalid */
773/* Opcode 0x66 0x0f 0x38 0x16 - invalid (vex only). */
774/* Opcode 0x0f 0x38 0x17 - invalid */
775
776
777/** Opcode 0x66 0x0f 0x38 0x17 - invalid */
778FNIEMOP_DEF(iemOp_ptest_Vx_Wx)
779{
780 IEMOP_MNEMONIC2(RM, PTEST, ptest, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
781 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
782 if (IEM_IS_MODRM_REG_MODE(bRm))
783 {
784 /*
785 * Register, register.
786 */
787 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
788 IEM_MC_BEGIN(3, 0);
789 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
790 IEM_MC_ARG(PCRTUINT128U, puSrc2, 1);
791 IEM_MC_ARG(uint32_t *, pEFlags, 2);
792 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
793 IEM_MC_PREPARE_SSE_USAGE();
794 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
795 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
796 IEM_MC_REF_EFLAGS(pEFlags);
797 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
798 IEM_MC_ADVANCE_RIP_AND_FINISH();
799 IEM_MC_END();
800 }
801 else
802 {
803 /*
804 * Register, memory.
805 */
806 IEM_MC_BEGIN(3, 2);
807 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
808 IEM_MC_LOCAL(RTUINT128U, uSrc2);
809 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1);
810 IEM_MC_ARG(uint32_t *, pEFlags, 2);
811 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
812
813 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
814 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
815 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
816 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
817
818 IEM_MC_PREPARE_SSE_USAGE();
819 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
820 IEM_MC_REF_EFLAGS(pEFlags);
821 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
822
823 IEM_MC_ADVANCE_RIP_AND_FINISH();
824 IEM_MC_END();
825 }
826}
827
828
829/* Opcode 0x0f 0x38 0x18 - invalid */
830/* Opcode 0x66 0x0f 0x38 0x18 - invalid (vex only). */
831/* Opcode 0x0f 0x38 0x19 - invalid */
832/* Opcode 0x66 0x0f 0x38 0x19 - invalid (vex only). */
833/* Opcode 0x0f 0x38 0x1a - invalid */
834/* Opcode 0x66 0x0f 0x38 0x1a - invalid (vex only). */
835/* Opcode 0x0f 0x38 0x1b - invalid */
836/* Opcode 0x66 0x0f 0x38 0x1b - invalid */
837
838
839/** Opcode 0x0f 0x38 0x1c. */
840FNIEMOP_DEF(iemOp_pabsb_Pq_Qq)
841{
842 IEMOP_MNEMONIC2(RM, PABSB, pabsb, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
843 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
844 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsb_u64, &iemAImpl_pabsb_u64_fallback));
845}
846
847
848/** Opcode 0x66 0x0f 0x38 0x1c. */
849FNIEMOP_DEF(iemOp_pabsb_Vx_Wx)
850{
851 IEMOP_MNEMONIC2(RM, PABSB, pabsb, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
852 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
853 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback));
854
855}
856
857
858/** Opcode 0x0f 0x38 0x1d. */
859FNIEMOP_DEF(iemOp_pabsw_Pq_Qq)
860{
861 IEMOP_MNEMONIC2(RM, PABSW, pabsw, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
862 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
863 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsw_u64, &iemAImpl_pabsw_u64_fallback));
864}
865
866
867/** Opcode 0x66 0x0f 0x38 0x1d. */
868FNIEMOP_DEF(iemOp_pabsw_Vx_Wx)
869{
870 IEMOP_MNEMONIC2(RM, PABSW, pabsw, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
871 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
872 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback));
873
874}
875
876
877/** Opcode 0x0f 0x38 0x1e. */
878FNIEMOP_DEF(iemOp_pabsd_Pq_Qq)
879{
880 IEMOP_MNEMONIC2(RM, PABSD, pabsd, Pq, Qq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
881 return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full_Ssse3,
882 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsd_u64, &iemAImpl_pabsd_u64_fallback));
883}
884
885
886/** Opcode 0x66 0x0f 0x38 0x1e. */
887FNIEMOP_DEF(iemOp_pabsd_Vx_Wx)
888{
889 IEMOP_MNEMONIC2(RM, PABSD, pabsd, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
890 return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFull_To_Full,
891 IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback));
892
893}
894
895
896/* Opcode 0x0f 0x38 0x1f - invalid */
897/* Opcode 0x66 0x0f 0x38 0x1f - invalid */
898
899
900/** Body for the pmov{s,z}x* instructions. */
901#define IEMOP_BODY_PMOV_S_Z(a_Instr, a_SrcWidth) \
902 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
903 if (IEM_IS_MODRM_REG_MODE(bRm)) \
904 { \
905 /* \
906 * Register, register. \
907 */ \
908 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \
909 IEM_MC_BEGIN(2, 0); \
910 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
911 IEM_MC_ARG(uint64_t, uSrc, 1); \
912 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); \
913 IEM_MC_PREPARE_SSE_USAGE(); \
914 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /* a_iQword */); \
915 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
916 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse41, \
917 iemAImpl_ ## a_Instr ## _u128, \
918 iemAImpl_v ## a_Instr ## _u128_fallback), \
919 puDst, uSrc); \
920 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
921 IEM_MC_END(); \
922 } \
923 else \
924 { \
925 /* \
926 * Register, memory. \
927 */ \
928 IEM_MC_BEGIN(2, 2); \
929 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
930 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
931 IEM_MC_ARG(uint ## a_SrcWidth ## _t, uSrc, 1); \
932 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
933 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41); \
934 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); \
935 IEM_MC_PREPARE_SSE_USAGE(); \
936 IEM_MC_FETCH_MEM_U## a_SrcWidth (uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
937 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
938 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse41, \
939 iemAImpl_ ## a_Instr ## _u128, \
940 iemAImpl_v ## a_Instr ## _u128_fallback), \
941 puDst, uSrc); \
942 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
943 IEM_MC_END(); \
944 } \
945 (void)0
946
947
948/** Opcode 0x66 0x0f 0x38 0x20. */
949FNIEMOP_DEF(iemOp_pmovsxbw_Vx_UxMq)
950{
951 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
952 IEMOP_MNEMONIC2(RM, PMOVSXBW, pmovsxbw, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
953 IEMOP_BODY_PMOV_S_Z(pmovsxbw, 64);
954}
955
956
957/** Opcode 0x66 0x0f 0x38 0x21. */
958FNIEMOP_DEF(iemOp_pmovsxbd_Vx_UxMd)
959{
960 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
961 IEMOP_MNEMONIC2(RM, PMOVSXBD, pmovsxbd, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
962 IEMOP_BODY_PMOV_S_Z(pmovsxbd, 32);
963}
964
965
966/** Opcode 0x66 0x0f 0x38 0x22. */
967FNIEMOP_DEF(iemOp_pmovsxbq_Vx_UxMw)
968{
969 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
970 IEMOP_MNEMONIC2(RM, PMOVSXBQ, pmovsxbq, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
971 IEMOP_BODY_PMOV_S_Z(pmovsxbq, 16);
972}
973
974
975/** Opcode 0x66 0x0f 0x38 0x23. */
976FNIEMOP_DEF(iemOp_pmovsxwd_Vx_UxMq)
977{
978 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
979 IEMOP_MNEMONIC2(RM, PMOVSXWD, pmovsxwd, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
980 IEMOP_BODY_PMOV_S_Z(pmovsxwd, 64);
981}
982
983
984/** Opcode 0x66 0x0f 0x38 0x24. */
985FNIEMOP_DEF(iemOp_pmovsxwq_Vx_UxMd)
986{
987 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
988 IEMOP_MNEMONIC2(RM, PMOVSXWQ, pmovsxwq, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
989 IEMOP_BODY_PMOV_S_Z(pmovsxwq, 32);
990}
991
992
993/** Opcode 0x66 0x0f 0x38 0x25. */
994FNIEMOP_DEF(iemOp_pmovsxdq_Vx_UxMq)
995{
996 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
997 IEMOP_MNEMONIC2(RM, PMOVSXDQ, pmovsxdq, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
998 IEMOP_BODY_PMOV_S_Z(pmovsxdq, 64);
999}
1000
1001
1002/* Opcode 0x66 0x0f 0x38 0x26 - invalid */
1003/* Opcode 0x66 0x0f 0x38 0x27 - invalid */
1004
1005
1006/** Opcode 0x66 0x0f 0x38 0x28. */
1007FNIEMOP_DEF(iemOp_pmuldq_Vx_Wx)
1008{
1009 IEMOP_MNEMONIC2(RM, PMULDQ, pmuldq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1010 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
1011 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback));
1012}
1013
1014
1015/** Opcode 0x66 0x0f 0x38 0x29. */
1016FNIEMOP_DEF(iemOp_pcmpeqq_Vx_Wx)
1017{
1018 IEMOP_MNEMONIC2(RM, PCMPEQQ, pcmpeqq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1019 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
1020 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback));
1021}
1022
1023
1024/**
1025 * @opcode 0x2a
1026 * @opcodesub !11 mr/reg
1027 * @oppfx 0x66
1028 * @opcpuid sse4.1
1029 * @opgroup og_sse41_cachect
1030 * @opxcpttype 1
1031 * @optest op1=-1 op2=2 -> op1=2
1032 * @optest op1=0 op2=-42 -> op1=-42
1033 */
1034FNIEMOP_DEF(iemOp_movntdqa_Vdq_Mdq)
1035{
1036 IEMOP_MNEMONIC2(RM_MEM, MOVNTDQA, movntdqa, Vdq_WO, Mdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1037 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1038 if (IEM_IS_MODRM_MEM_MODE(bRm))
1039 {
1040 /* Register, memory. */
1041 IEM_MC_BEGIN(0, 2);
1042 IEM_MC_LOCAL(RTUINT128U, uSrc);
1043 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1044
1045 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1046 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse41);
1047 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1048 IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1049
1050 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1051 IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1052
1053 IEM_MC_ADVANCE_RIP_AND_FINISH();
1054 IEM_MC_END();
1055 }
1056
1057 /**
1058 * @opdone
1059 * @opmnemonic ud660f382areg
1060 * @opcode 0x2a
1061 * @opcodesub 11 mr/reg
1062 * @oppfx 0x66
1063 * @opunused immediate
1064 * @opcpuid sse
1065 * @optest ->
1066 */
1067 else
1068 return IEMOP_RAISE_INVALID_OPCODE();
1069}
1070
1071
1072/** Opcode 0x66 0x0f 0x38 0x2b. */
1073FNIEMOP_DEF(iemOp_packusdw_Vx_Wx)
1074{
1075 IEMOP_MNEMONIC2(RM, PACKUSDW, packusdw, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
1076 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full, iemAImpl_packusdw_u128);
1077}
1078
1079
1080/* Opcode 0x66 0x0f 0x38 0x2c - invalid (vex only). */
1081/* Opcode 0x66 0x0f 0x38 0x2d - invalid (vex only). */
1082/* Opcode 0x66 0x0f 0x38 0x2e - invalid (vex only). */
1083/* Opcode 0x66 0x0f 0x38 0x2f - invalid (vex only). */
1084
1085/** Opcode 0x66 0x0f 0x38 0x30. */
1086FNIEMOP_DEF(iemOp_pmovzxbw_Vx_UxMq)
1087{
1088 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1089 IEMOP_MNEMONIC2(RM, PMOVZXBW, pmovzxbw, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1090 IEMOP_BODY_PMOV_S_Z(pmovzxbw, 64);
1091}
1092
1093
1094/** Opcode 0x66 0x0f 0x38 0x31. */
1095FNIEMOP_DEF(iemOp_pmovzxbd_Vx_UxMd)
1096{
1097 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1098 IEMOP_MNEMONIC2(RM, PMOVZXBD, pmovzxbd, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1099 IEMOP_BODY_PMOV_S_Z(pmovzxbd, 32);
1100}
1101
1102
1103/** Opcode 0x66 0x0f 0x38 0x32. */
1104FNIEMOP_DEF(iemOp_pmovzxbq_Vx_UxMw)
1105{
1106 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1107 IEMOP_MNEMONIC2(RM, PMOVZXBQ, pmovzxbq, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1108 IEMOP_BODY_PMOV_S_Z(pmovzxbq, 16);
1109}
1110
1111
1112/** Opcode 0x66 0x0f 0x38 0x33. */
1113FNIEMOP_DEF(iemOp_pmovzxwd_Vx_UxMq)
1114{
1115 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1116 IEMOP_MNEMONIC2(RM, PMOVZXWD, pmovzxwd, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1117 IEMOP_BODY_PMOV_S_Z(pmovzxwd, 64);
1118}
1119
1120
1121/** Opcode 0x66 0x0f 0x38 0x34. */
1122FNIEMOP_DEF(iemOp_pmovzxwq_Vx_UxMd)
1123{
1124 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1125 IEMOP_MNEMONIC2(RM, PMOVZXWQ, pmovzxwq, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1126 IEMOP_BODY_PMOV_S_Z(pmovzxwq, 32);
1127}
1128
1129
1130/** Opcode 0x66 0x0f 0x38 0x35. */
1131FNIEMOP_DEF(iemOp_pmovzxdq_Vx_UxMq)
1132{
1133 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
1134 IEMOP_MNEMONIC2(RM, PMOVZXDQ, pmovzxdq, Vx, Wq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1135 IEMOP_BODY_PMOV_S_Z(pmovzxdq, 64);
1136}
1137
1138
1139/* Opcode 0x66 0x0f 0x38 0x36 - invalid (vex only). */
1140
1141
1142/** Opcode 0x66 0x0f 0x38 0x37. */
1143FNIEMOP_DEF(iemOp_pcmpgtq_Vx_Wx)
1144{
1145 IEMOP_MNEMONIC2(RM, PCMPGTQ, pcmpgtq, Vx, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1146 return FNIEMOP_CALL_1(iemOpCommonSse42_FullFull_To_Full,
1147 IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback));
1148}
1149
1150
1151/** Opcode 0x66 0x0f 0x38 0x38. */
1152FNIEMOP_DEF(iemOp_pminsb_Vx_Wx)
1153{
1154 IEMOP_MNEMONIC2(RM, PMINSB, pminsb, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1155 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
1156 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback));
1157}
1158
1159
1160/** Opcode 0x66 0x0f 0x38 0x39. */
1161FNIEMOP_DEF(iemOp_pminsd_Vx_Wx)
1162{
1163 IEMOP_MNEMONIC2(RM, PMINSD, pminsd, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1164 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
1165 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback));
1166}
1167
1168
1169/** Opcode 0x66 0x0f 0x38 0x3a. */
1170FNIEMOP_DEF(iemOp_pminuw_Vx_Wx)
1171{
1172 IEMOP_MNEMONIC2(RM, PMINUW, pminuw, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1173 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
1174 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback));
1175}
1176
1177
1178/** Opcode 0x66 0x0f 0x38 0x3b. */
1179FNIEMOP_DEF(iemOp_pminud_Vx_Wx)
1180{
1181 IEMOP_MNEMONIC2(RM, PMINUD, pminud, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1182 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
1183 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback));
1184}
1185
1186
1187/** Opcode 0x66 0x0f 0x38 0x3c. */
1188FNIEMOP_DEF(iemOp_pmaxsb_Vx_Wx)
1189{
1190 IEMOP_MNEMONIC2(RM, PMAXSB, pmaxsb, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1191 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
1192 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback));
1193}
1194
1195
1196/** Opcode 0x66 0x0f 0x38 0x3d. */
1197FNIEMOP_DEF(iemOp_pmaxsd_Vx_Wx)
1198{
1199 IEMOP_MNEMONIC2(RM, PMAXSD, pmaxsd, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1200 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
1201 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback));
1202}
1203
1204
1205/** Opcode 0x66 0x0f 0x38 0x3e. */
1206FNIEMOP_DEF(iemOp_pmaxuw_Vx_Wx)
1207{
1208 IEMOP_MNEMONIC2(RM, PMAXUW, pmaxuw, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1209 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
1210 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback));
1211}
1212
1213
1214/** Opcode 0x66 0x0f 0x38 0x3f. */
1215FNIEMOP_DEF(iemOp_pmaxud_Vx_Wx)
1216{
1217 IEMOP_MNEMONIC2(RM, PMAXUD, pmaxud, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1218 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
1219 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback));
1220}
1221
1222
1223/** Opcode 0x66 0x0f 0x38 0x40. */
1224FNIEMOP_DEF(iemOp_pmulld_Vx_Wx)
1225{
1226 IEMOP_MNEMONIC2(RM, PMULLD, pmulld, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1227 return FNIEMOP_CALL_1(iemOpCommonSse41_FullFull_To_Full,
1228 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback));
1229}
1230
1231
1232/** Opcode 0x66 0x0f 0x38 0x41. */
1233FNIEMOP_DEF(iemOp_phminposuw_Vdq_Wdq)
1234{
1235 IEMOP_MNEMONIC2(RM, PHMINPOSUW, phminposuw, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1236 return FNIEMOP_CALL_1(iemOpCommonSse41Opt_FullFull_To_Full,
1237 IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback));
1238}
1239
1240
1241/* Opcode 0x66 0x0f 0x38 0x42 - invalid. */
1242/* Opcode 0x66 0x0f 0x38 0x43 - invalid. */
1243/* Opcode 0x66 0x0f 0x38 0x44 - invalid. */
1244/* Opcode 0x66 0x0f 0x38 0x45 - invalid (vex only). */
1245/* Opcode 0x66 0x0f 0x38 0x46 - invalid (vex only). */
1246/* Opcode 0x66 0x0f 0x38 0x47 - invalid (vex only). */
1247/* Opcode 0x66 0x0f 0x38 0x48 - invalid. */
1248/* Opcode 0x66 0x0f 0x38 0x49 - invalid. */
1249/* Opcode 0x66 0x0f 0x38 0x4a - invalid. */
1250/* Opcode 0x66 0x0f 0x38 0x4b - invalid. */
1251/* Opcode 0x66 0x0f 0x38 0x4c - invalid. */
1252/* Opcode 0x66 0x0f 0x38 0x4d - invalid. */
1253/* Opcode 0x66 0x0f 0x38 0x4e - invalid. */
1254/* Opcode 0x66 0x0f 0x38 0x4f - invalid. */
1255
1256/* Opcode 0x66 0x0f 0x38 0x50 - invalid. */
1257/* Opcode 0x66 0x0f 0x38 0x51 - invalid. */
1258/* Opcode 0x66 0x0f 0x38 0x52 - invalid. */
1259/* Opcode 0x66 0x0f 0x38 0x53 - invalid. */
1260/* Opcode 0x66 0x0f 0x38 0x54 - invalid. */
1261/* Opcode 0x66 0x0f 0x38 0x55 - invalid. */
1262/* Opcode 0x66 0x0f 0x38 0x56 - invalid. */
1263/* Opcode 0x66 0x0f 0x38 0x57 - invalid. */
1264/* Opcode 0x66 0x0f 0x38 0x58 - invalid (vex only). */
1265/* Opcode 0x66 0x0f 0x38 0x59 - invalid (vex only). */
1266/* Opcode 0x66 0x0f 0x38 0x5a - invalid (vex only). */
1267/* Opcode 0x66 0x0f 0x38 0x5b - invalid. */
1268/* Opcode 0x66 0x0f 0x38 0x5c - invalid. */
1269/* Opcode 0x66 0x0f 0x38 0x5d - invalid. */
1270/* Opcode 0x66 0x0f 0x38 0x5e - invalid. */
1271/* Opcode 0x66 0x0f 0x38 0x5f - invalid. */
1272
1273/* Opcode 0x66 0x0f 0x38 0x60 - invalid. */
1274/* Opcode 0x66 0x0f 0x38 0x61 - invalid. */
1275/* Opcode 0x66 0x0f 0x38 0x62 - invalid. */
1276/* Opcode 0x66 0x0f 0x38 0x63 - invalid. */
1277/* Opcode 0x66 0x0f 0x38 0x64 - invalid. */
1278/* Opcode 0x66 0x0f 0x38 0x65 - invalid. */
1279/* Opcode 0x66 0x0f 0x38 0x66 - invalid. */
1280/* Opcode 0x66 0x0f 0x38 0x67 - invalid. */
1281/* Opcode 0x66 0x0f 0x38 0x68 - invalid. */
1282/* Opcode 0x66 0x0f 0x38 0x69 - invalid. */
1283/* Opcode 0x66 0x0f 0x38 0x6a - invalid. */
1284/* Opcode 0x66 0x0f 0x38 0x6b - invalid. */
1285/* Opcode 0x66 0x0f 0x38 0x6c - invalid. */
1286/* Opcode 0x66 0x0f 0x38 0x6d - invalid. */
1287/* Opcode 0x66 0x0f 0x38 0x6e - invalid. */
1288/* Opcode 0x66 0x0f 0x38 0x6f - invalid. */
1289
1290/* Opcode 0x66 0x0f 0x38 0x70 - invalid. */
1291/* Opcode 0x66 0x0f 0x38 0x71 - invalid. */
1292/* Opcode 0x66 0x0f 0x38 0x72 - invalid. */
1293/* Opcode 0x66 0x0f 0x38 0x73 - invalid. */
1294/* Opcode 0x66 0x0f 0x38 0x74 - invalid. */
1295/* Opcode 0x66 0x0f 0x38 0x75 - invalid. */
1296/* Opcode 0x66 0x0f 0x38 0x76 - invalid. */
1297/* Opcode 0x66 0x0f 0x38 0x77 - invalid. */
1298/* Opcode 0x66 0x0f 0x38 0x78 - invalid (vex only). */
1299/* Opcode 0x66 0x0f 0x38 0x79 - invalid (vex only). */
1300/* Opcode 0x66 0x0f 0x38 0x7a - invalid. */
1301/* Opcode 0x66 0x0f 0x38 0x7b - invalid. */
1302/* Opcode 0x66 0x0f 0x38 0x7c - invalid. */
1303/* Opcode 0x66 0x0f 0x38 0x7d - invalid. */
1304/* Opcode 0x66 0x0f 0x38 0x7e - invalid. */
1305/* Opcode 0x66 0x0f 0x38 0x7f - invalid. */
1306
1307/** Opcode 0x66 0x0f 0x38 0x80. */
1308#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1309FNIEMOP_DEF(iemOp_invept_Gy_Mdq)
1310{
1311 IEMOP_MNEMONIC(invept, "invept Gy,Mdq");
1312 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1313 IEMOP_HLP_IN_VMX_OPERATION("invept", kVmxVDiag_Invept);
1314 IEMOP_HLP_VMX_INSTR("invept", kVmxVDiag_Invept);
1315 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1316 if (IEM_IS_MODRM_MEM_MODE(bRm))
1317 {
1318 /* Register, memory. */
1319 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
1320 {
1321 IEM_MC_BEGIN(3, 0);
1322 IEM_MC_ARG(uint8_t, iEffSeg, 0);
1323 IEM_MC_ARG(RTGCPTR, GCPtrInveptDesc, 1);
1324 IEM_MC_ARG(uint64_t, uInveptType, 2);
1325 IEM_MC_FETCH_GREG_U64(uInveptType, IEM_GET_MODRM_REG(pVCpu, bRm));
1326 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
1327 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1328 IEM_MC_CALL_CIMPL_3(iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType);
1329 IEM_MC_END();
1330 }
1331 else
1332 {
1333 IEM_MC_BEGIN(3, 0);
1334 IEM_MC_ARG(uint8_t, iEffSeg, 0);
1335 IEM_MC_ARG(RTGCPTR, GCPtrInveptDesc, 1);
1336 IEM_MC_ARG(uint32_t, uInveptType, 2);
1337 IEM_MC_FETCH_GREG_U32(uInveptType, IEM_GET_MODRM_REG(pVCpu, bRm));
1338 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInveptDesc, bRm, 0);
1339 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1340 IEM_MC_CALL_CIMPL_3(iemCImpl_invept, iEffSeg, GCPtrInveptDesc, uInveptType);
1341 IEM_MC_END();
1342 }
1343 }
1344 Log(("iemOp_invept_Gy_Mdq: invalid encoding -> #UD\n"));
1345 return IEMOP_RAISE_INVALID_OPCODE();
1346}
1347#else
1348FNIEMOP_STUB(iemOp_invept_Gy_Mdq);
1349#endif
1350
1351/** Opcode 0x66 0x0f 0x38 0x81. */
1352#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1353FNIEMOP_DEF(iemOp_invvpid_Gy_Mdq)
1354{
1355 IEMOP_MNEMONIC(invvpid, "invvpid Gy,Mdq");
1356 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1357 IEMOP_HLP_IN_VMX_OPERATION("invvpid", kVmxVDiag_Invvpid);
1358 IEMOP_HLP_VMX_INSTR("invvpid", kVmxVDiag_Invvpid);
1359 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1360 if (IEM_IS_MODRM_MEM_MODE(bRm))
1361 {
1362 /* Register, memory. */
1363 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
1364 {
1365 IEM_MC_BEGIN(3, 0);
1366 IEM_MC_ARG(uint8_t, iEffSeg, 0);
1367 IEM_MC_ARG(RTGCPTR, GCPtrInvvpidDesc, 1);
1368 IEM_MC_ARG(uint64_t, uInvvpidType, 2);
1369 IEM_MC_FETCH_GREG_U64(uInvvpidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1370 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
1371 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1372 IEM_MC_CALL_CIMPL_3(iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType);
1373 IEM_MC_END();
1374 }
1375 else
1376 {
1377 IEM_MC_BEGIN(3, 0);
1378 IEM_MC_ARG(uint8_t, iEffSeg, 0);
1379 IEM_MC_ARG(RTGCPTR, GCPtrInvvpidDesc, 1);
1380 IEM_MC_ARG(uint32_t, uInvvpidType, 2);
1381 IEM_MC_FETCH_GREG_U32(uInvvpidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1382 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvvpidDesc, bRm, 0);
1383 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1384 IEM_MC_CALL_CIMPL_3(iemCImpl_invvpid, iEffSeg, GCPtrInvvpidDesc, uInvvpidType);
1385 IEM_MC_END();
1386 }
1387 }
1388 Log(("iemOp_invvpid_Gy_Mdq: invalid encoding -> #UD\n"));
1389 return IEMOP_RAISE_INVALID_OPCODE();
1390}
1391#else
1392FNIEMOP_STUB(iemOp_invvpid_Gy_Mdq);
1393#endif
1394
1395/** Opcode 0x66 0x0f 0x38 0x82. */
1396FNIEMOP_DEF(iemOp_invpcid_Gy_Mdq)
1397{
1398 IEMOP_MNEMONIC(invpcid, "invpcid Gy,Mdq");
1399 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1400 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1401 if (IEM_IS_MODRM_MEM_MODE(bRm))
1402 {
1403 /* Register, memory. */
1404 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
1405 {
1406 IEM_MC_BEGIN(3, 0);
1407 IEM_MC_ARG(uint8_t, iEffSeg, 0);
1408 IEM_MC_ARG(RTGCPTR, GCPtrInvpcidDesc, 1);
1409 IEM_MC_ARG(uint64_t, uInvpcidType, 2);
1410 IEM_MC_FETCH_GREG_U64(uInvpcidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1411 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
1412 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1413 IEM_MC_CALL_CIMPL_3(iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
1414 IEM_MC_END();
1415 }
1416 else
1417 {
1418 IEM_MC_BEGIN(3, 0);
1419 IEM_MC_ARG(uint8_t, iEffSeg, 0);
1420 IEM_MC_ARG(RTGCPTR, GCPtrInvpcidDesc, 1);
1421 IEM_MC_ARG(uint32_t, uInvpcidType, 2);
1422 IEM_MC_FETCH_GREG_U32(uInvpcidType, IEM_GET_MODRM_REG(pVCpu, bRm));
1423 IEM_MC_CALC_RM_EFF_ADDR(GCPtrInvpcidDesc, bRm, 0);
1424 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
1425 IEM_MC_CALL_CIMPL_3(iemCImpl_invpcid, iEffSeg, GCPtrInvpcidDesc, uInvpcidType);
1426 IEM_MC_END();
1427 }
1428 }
1429 Log(("iemOp_invpcid_Gy_Mdq: invalid encoding -> #UD\n"));
1430 return IEMOP_RAISE_INVALID_OPCODE();
1431}
1432
1433
1434/* Opcode 0x66 0x0f 0x38 0x83 - invalid. */
1435/* Opcode 0x66 0x0f 0x38 0x84 - invalid. */
1436/* Opcode 0x66 0x0f 0x38 0x85 - invalid. */
1437/* Opcode 0x66 0x0f 0x38 0x86 - invalid. */
1438/* Opcode 0x66 0x0f 0x38 0x87 - invalid. */
1439/* Opcode 0x66 0x0f 0x38 0x88 - invalid. */
1440/* Opcode 0x66 0x0f 0x38 0x89 - invalid. */
1441/* Opcode 0x66 0x0f 0x38 0x8a - invalid. */
1442/* Opcode 0x66 0x0f 0x38 0x8b - invalid. */
1443/* Opcode 0x66 0x0f 0x38 0x8c - invalid (vex only). */
1444/* Opcode 0x66 0x0f 0x38 0x8d - invalid. */
1445/* Opcode 0x66 0x0f 0x38 0x8e - invalid (vex only). */
1446/* Opcode 0x66 0x0f 0x38 0x8f - invalid. */
1447
1448/* Opcode 0x66 0x0f 0x38 0x90 - invalid (vex only). */
1449/* Opcode 0x66 0x0f 0x38 0x91 - invalid (vex only). */
1450/* Opcode 0x66 0x0f 0x38 0x92 - invalid (vex only). */
1451/* Opcode 0x66 0x0f 0x38 0x93 - invalid (vex only). */
1452/* Opcode 0x66 0x0f 0x38 0x94 - invalid. */
1453/* Opcode 0x66 0x0f 0x38 0x95 - invalid. */
1454/* Opcode 0x66 0x0f 0x38 0x96 - invalid (vex only). */
1455/* Opcode 0x66 0x0f 0x38 0x97 - invalid (vex only). */
1456/* Opcode 0x66 0x0f 0x38 0x98 - invalid (vex only). */
1457/* Opcode 0x66 0x0f 0x38 0x99 - invalid (vex only). */
1458/* Opcode 0x66 0x0f 0x38 0x9a - invalid (vex only). */
1459/* Opcode 0x66 0x0f 0x38 0x9b - invalid (vex only). */
1460/* Opcode 0x66 0x0f 0x38 0x9c - invalid (vex only). */
1461/* Opcode 0x66 0x0f 0x38 0x9d - invalid (vex only). */
1462/* Opcode 0x66 0x0f 0x38 0x9e - invalid (vex only). */
1463/* Opcode 0x66 0x0f 0x38 0x9f - invalid (vex only). */
1464
1465/* Opcode 0x66 0x0f 0x38 0xa0 - invalid. */
1466/* Opcode 0x66 0x0f 0x38 0xa1 - invalid. */
1467/* Opcode 0x66 0x0f 0x38 0xa2 - invalid. */
1468/* Opcode 0x66 0x0f 0x38 0xa3 - invalid. */
1469/* Opcode 0x66 0x0f 0x38 0xa4 - invalid. */
1470/* Opcode 0x66 0x0f 0x38 0xa5 - invalid. */
1471/* Opcode 0x66 0x0f 0x38 0xa6 - invalid (vex only). */
1472/* Opcode 0x66 0x0f 0x38 0xa7 - invalid (vex only). */
1473/* Opcode 0x66 0x0f 0x38 0xa8 - invalid (vex only). */
1474/* Opcode 0x66 0x0f 0x38 0xa9 - invalid (vex only). */
1475/* Opcode 0x66 0x0f 0x38 0xaa - invalid (vex only). */
1476/* Opcode 0x66 0x0f 0x38 0xab - invalid (vex only). */
1477/* Opcode 0x66 0x0f 0x38 0xac - invalid (vex only). */
1478/* Opcode 0x66 0x0f 0x38 0xad - invalid (vex only). */
1479/* Opcode 0x66 0x0f 0x38 0xae - invalid (vex only). */
1480/* Opcode 0x66 0x0f 0x38 0xaf - invalid (vex only). */
1481
1482/* Opcode 0x66 0x0f 0x38 0xb0 - invalid. */
1483/* Opcode 0x66 0x0f 0x38 0xb1 - invalid. */
1484/* Opcode 0x66 0x0f 0x38 0xb2 - invalid. */
1485/* Opcode 0x66 0x0f 0x38 0xb3 - invalid. */
1486/* Opcode 0x66 0x0f 0x38 0xb4 - invalid. */
1487/* Opcode 0x66 0x0f 0x38 0xb5 - invalid. */
1488/* Opcode 0x66 0x0f 0x38 0xb6 - invalid (vex only). */
1489/* Opcode 0x66 0x0f 0x38 0xb7 - invalid (vex only). */
1490/* Opcode 0x66 0x0f 0x38 0xb8 - invalid (vex only). */
1491/* Opcode 0x66 0x0f 0x38 0xb9 - invalid (vex only). */
1492/* Opcode 0x66 0x0f 0x38 0xba - invalid (vex only). */
1493/* Opcode 0x66 0x0f 0x38 0xbb - invalid (vex only). */
1494/* Opcode 0x66 0x0f 0x38 0xbc - invalid (vex only). */
1495/* Opcode 0x66 0x0f 0x38 0xbd - invalid (vex only). */
1496/* Opcode 0x66 0x0f 0x38 0xbe - invalid (vex only). */
1497/* Opcode 0x66 0x0f 0x38 0xbf - invalid (vex only). */
1498
1499/* Opcode 0x0f 0x38 0xc0 - invalid. */
1500/* Opcode 0x66 0x0f 0x38 0xc0 - invalid. */
1501/* Opcode 0x0f 0x38 0xc1 - invalid. */
1502/* Opcode 0x66 0x0f 0x38 0xc1 - invalid. */
1503/* Opcode 0x0f 0x38 0xc2 - invalid. */
1504/* Opcode 0x66 0x0f 0x38 0xc2 - invalid. */
1505/* Opcode 0x0f 0x38 0xc3 - invalid. */
1506/* Opcode 0x66 0x0f 0x38 0xc3 - invalid. */
1507/* Opcode 0x0f 0x38 0xc4 - invalid. */
1508/* Opcode 0x66 0x0f 0x38 0xc4 - invalid. */
1509/* Opcode 0x0f 0x38 0xc5 - invalid. */
1510/* Opcode 0x66 0x0f 0x38 0xc5 - invalid. */
1511/* Opcode 0x0f 0x38 0xc6 - invalid. */
1512/* Opcode 0x66 0x0f 0x38 0xc6 - invalid. */
1513/* Opcode 0x0f 0x38 0xc7 - invalid. */
1514/* Opcode 0x66 0x0f 0x38 0xc7 - invalid. */
1515
1516
1517/** Opcode 0x0f 0x38 0xc8. */
1518FNIEMOP_DEF(iemOp_sha1nexte_Vdq_Wdq)
1519{
1520 IEMOP_MNEMONIC2(RM, SHA1NEXTE, sha1nexte, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1521 return FNIEMOP_CALL_1(iemOpCommonSha_FullFull_To_Full,
1522 IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback));
1523}
1524
1525
1526/* Opcode 0x66 0x0f 0x38 0xc8 - invalid. */
1527
1528
1529/** Opcode 0x0f 0x38 0xc9. */
1530FNIEMOP_DEF(iemOp_sha1msg1_Vdq_Wdq)
1531{
1532 IEMOP_MNEMONIC2(RM, SHA1MSG1, sha1msg1, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1533 return FNIEMOP_CALL_1(iemOpCommonSha_FullFull_To_Full,
1534 IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback));
1535}
1536
1537
1538/* Opcode 0x66 0x0f 0x38 0xc9 - invalid. */
1539
1540
1541/** Opcode 0x0f 0x38 0xca. */
1542FNIEMOP_DEF(iemOp_sha1msg2_Vdq_Wdq)
1543{
1544 IEMOP_MNEMONIC2(RM, SHA1MSG2, sha1msg2, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1545 return FNIEMOP_CALL_1(iemOpCommonSha_FullFull_To_Full,
1546 IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback));
1547}
1548
1549
1550/* Opcode 0x66 0x0f 0x38 0xca - invalid. */
1551
1552
1553/** Opcode 0x0f 0x38 0xcb. */
1554FNIEMOP_DEF(iemOp_sha256rnds2_Vdq_Wdq)
1555{
1556 IEMOP_MNEMONIC2(RM, SHA256RNDS2, sha256rnds2, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES); /** @todo Actually RMI with implicit XMM0 */
1557 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1558 if (IEM_IS_MODRM_REG_MODE(bRm))
1559 {
1560 /*
1561 * Register, register.
1562 */
1563 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
1564 IEM_MC_BEGIN(3, 0);
1565 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1566 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1567 IEM_MC_ARG(PCRTUINT128U, puXmm0, 2);
1568 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1569 IEM_MC_PREPARE_SSE_USAGE();
1570 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1571 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1572 IEM_MC_REF_XREG_U128_CONST(puXmm0, 0);
1573 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha256rnds2_u128, iemAImpl_sha256rnds2_u128_fallback),
1574 puDst, puSrc, puXmm0);
1575 IEM_MC_ADVANCE_RIP_AND_FINISH();
1576 IEM_MC_END();
1577 }
1578 else
1579 {
1580 /*
1581 * Register, memory.
1582 */
1583 IEM_MC_BEGIN(3, 2);
1584 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1585 IEM_MC_LOCAL(RTUINT128U, uSrc);
1586 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1587 IEM_MC_ARG(PCRTUINT128U, puXmm0, 2);
1588 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1589
1590 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1591 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSha);
1592 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1593 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1594
1595 IEM_MC_PREPARE_SSE_USAGE();
1596 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1597 IEM_MC_REF_XREG_U128_CONST(puXmm0, 0);
1598 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha256rnds2_u128, iemAImpl_sha256rnds2_u128_fallback),
1599 puDst, puSrc, puXmm0);
1600 IEM_MC_ADVANCE_RIP_AND_FINISH();
1601 IEM_MC_END();
1602 }
1603}
1604
1605
1606/* Opcode 0x66 0x0f 0x38 0xcb - invalid. */
1607
1608
1609/** Opcode 0x0f 0x38 0xcc. */
1610FNIEMOP_DEF(iemOp_sha256msg1_Vdq_Wdq)
1611{
1612 IEMOP_MNEMONIC2(RM, SHA256MSG1, sha256msg1, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1613 return FNIEMOP_CALL_1(iemOpCommonSha_FullFull_To_Full,
1614 IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback));
1615}
1616
1617
1618/* Opcode 0x66 0x0f 0x38 0xcc - invalid. */
1619
1620
1621/** Opcode 0x0f 0x38 0xcd. */
1622FNIEMOP_DEF(iemOp_sha256msg2_Vdq_Wdq)
1623{
1624 IEMOP_MNEMONIC2(RM, SHA256MSG2, sha256msg2, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1625 return FNIEMOP_CALL_1(iemOpCommonSha_FullFull_To_Full,
1626 IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback));
1627}
1628
1629
1630/* Opcode 0x66 0x0f 0x38 0xcd - invalid. */
1631/* Opcode 0x0f 0x38 0xce - invalid. */
1632/* Opcode 0x66 0x0f 0x38 0xce - invalid. */
1633/* Opcode 0x0f 0x38 0xcf - invalid. */
1634/* Opcode 0x66 0x0f 0x38 0xcf - invalid. */
1635
1636/* Opcode 0x66 0x0f 0x38 0xd0 - invalid. */
1637/* Opcode 0x66 0x0f 0x38 0xd1 - invalid. */
1638/* Opcode 0x66 0x0f 0x38 0xd2 - invalid. */
1639/* Opcode 0x66 0x0f 0x38 0xd3 - invalid. */
1640/* Opcode 0x66 0x0f 0x38 0xd4 - invalid. */
1641/* Opcode 0x66 0x0f 0x38 0xd5 - invalid. */
1642/* Opcode 0x66 0x0f 0x38 0xd6 - invalid. */
1643/* Opcode 0x66 0x0f 0x38 0xd7 - invalid. */
1644/* Opcode 0x66 0x0f 0x38 0xd8 - invalid. */
1645/* Opcode 0x66 0x0f 0x38 0xd9 - invalid. */
1646/* Opcode 0x66 0x0f 0x38 0xda - invalid. */
1647
1648
1649/** Opcode 0x66 0x0f 0x38 0xdb. */
1650FNIEMOP_DEF(iemOp_aesimc_Vdq_Wdq)
1651{
1652 IEMOP_MNEMONIC2(RM, AESIMC, aesimc, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1653 return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFull_To_Full,
1654 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback));
1655}
1656
1657
1658/** Opcode 0x66 0x0f 0x38 0xdc. */
1659FNIEMOP_DEF(iemOp_aesenc_Vdq_Wdq)
1660{
1661 IEMOP_MNEMONIC2(RM, AESENC, aesenc, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1662 return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFull_To_Full,
1663 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback));
1664}
1665
1666
1667/** Opcode 0x66 0x0f 0x38 0xdd. */
1668FNIEMOP_DEF(iemOp_aesenclast_Vdq_Wdq)
1669{
1670 IEMOP_MNEMONIC2(RM, AESENCLAST, aesenclast, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1671 return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFull_To_Full,
1672 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback));
1673}
1674
1675
1676/** Opcode 0x66 0x0f 0x38 0xde. */
1677FNIEMOP_DEF(iemOp_aesdec_Vdq_Wdq)
1678{
1679 IEMOP_MNEMONIC2(RM, AESDEC, aesdec, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1680 return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFull_To_Full,
1681 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback));
1682}
1683
1684
1685/** Opcode 0x66 0x0f 0x38 0xdf. */
1686FNIEMOP_DEF(iemOp_aesdeclast_Vdq_Wdq)
1687{
1688 IEMOP_MNEMONIC2(RM, AESDECLAST, aesdeclast, Vdq, Wdq, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
1689 return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFull_To_Full,
1690 IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback));
1691}
1692
1693
1694/* Opcode 0x66 0x0f 0x38 0xe0 - invalid. */
1695/* Opcode 0x66 0x0f 0x38 0xe1 - invalid. */
1696/* Opcode 0x66 0x0f 0x38 0xe2 - invalid. */
1697/* Opcode 0x66 0x0f 0x38 0xe3 - invalid. */
1698/* Opcode 0x66 0x0f 0x38 0xe4 - invalid. */
1699/* Opcode 0x66 0x0f 0x38 0xe5 - invalid. */
1700/* Opcode 0x66 0x0f 0x38 0xe6 - invalid. */
1701/* Opcode 0x66 0x0f 0x38 0xe7 - invalid. */
1702/* Opcode 0x66 0x0f 0x38 0xe8 - invalid. */
1703/* Opcode 0x66 0x0f 0x38 0xe9 - invalid. */
1704/* Opcode 0x66 0x0f 0x38 0xea - invalid. */
1705/* Opcode 0x66 0x0f 0x38 0xeb - invalid. */
1706/* Opcode 0x66 0x0f 0x38 0xec - invalid. */
1707/* Opcode 0x66 0x0f 0x38 0xed - invalid. */
1708/* Opcode 0x66 0x0f 0x38 0xee - invalid. */
1709/* Opcode 0x66 0x0f 0x38 0xef - invalid. */
1710
1711
1712/** Opcode [0x66] 0x0f 0x38 0xf0. */
1713FNIEMOP_DEF(iemOp_movbe_Gv_Mv)
1714{
1715 IEMOP_MNEMONIC2(RM, MOVBE, movbe, Gv, Ev, DISOPTYPE_HARMLESS, 0);
1716 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovBe)
1717 return iemOp_InvalidNeedRM(pVCpu);
1718
1719 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1720 if (!IEM_IS_MODRM_REG_MODE(bRm))
1721 {
1722 /*
1723 * Register, memory.
1724 */
1725 switch (pVCpu->iem.s.enmEffOpSize)
1726 {
1727 case IEMMODE_16BIT:
1728 IEM_MC_BEGIN(0, 2);
1729 IEM_MC_LOCAL(uint16_t, uSrc);
1730 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1731
1732 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1733 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1734 IEM_MC_FETCH_MEM_U16(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1735
1736 IEM_MC_BSWAP_LOCAL_U16(uSrc);
1737 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1738
1739 IEM_MC_ADVANCE_RIP_AND_FINISH();
1740 IEM_MC_END();
1741 break;
1742
1743 case IEMMODE_32BIT:
1744 IEM_MC_BEGIN(0, 2);
1745 IEM_MC_LOCAL(uint32_t, uSrc);
1746 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1747
1748 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1749 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1750 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1751
1752 IEM_MC_BSWAP_LOCAL_U32(uSrc);
1753 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1754
1755 IEM_MC_ADVANCE_RIP_AND_FINISH();
1756 IEM_MC_END();
1757 break;
1758
1759 case IEMMODE_64BIT:
1760 IEM_MC_BEGIN(0, 2);
1761 IEM_MC_LOCAL(uint64_t, uSrc);
1762 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1763
1764 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1765 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1766 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1767
1768 IEM_MC_BSWAP_LOCAL_U64(uSrc);
1769 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
1770
1771 IEM_MC_ADVANCE_RIP_AND_FINISH();
1772 IEM_MC_END();
1773 break;
1774
1775 IEM_NOT_REACHED_DEFAULT_CASE_RET();
1776 }
1777 }
1778 else
1779 {
1780 /* Reg/reg not supported. */
1781 return IEMOP_RAISE_INVALID_OPCODE();
1782 }
1783}
1784
1785
1786/* Opcode 0xf3 0x0f 0x38 0xf0 - invalid. */
1787
1788
1789/** Opcode 0xf2 0x0f 0x38 0xf0. */
1790FNIEMOP_DEF(iemOp_crc32_Gd_Eb)
1791{
1792 IEMOP_MNEMONIC2(RM, CRC32, crc32, Gd, Eb, DISOPTYPE_HARMLESS, 0);
1793 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42)
1794 return iemOp_InvalidNeedRM(pVCpu);
1795
1796 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1797 if (IEM_IS_MODRM_REG_MODE(bRm))
1798 {
1799 /*
1800 * Register, register.
1801 */
1802 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1803 IEM_MC_BEGIN(2, 0);
1804 IEM_MC_ARG(uint32_t *, puDst, 0);
1805 IEM_MC_ARG(uint8_t, uSrc, 1);
1806 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1807 IEM_MC_FETCH_GREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1808 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback), puDst, uSrc);
1809 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1810 IEM_MC_ADVANCE_RIP_AND_FINISH();
1811 IEM_MC_END();
1812 }
1813 else
1814 {
1815 /*
1816 * Register, memory.
1817 */
1818 IEM_MC_BEGIN(2, 1);
1819 IEM_MC_ARG(uint32_t *, puDst, 0);
1820 IEM_MC_ARG(uint8_t, uSrc, 1);
1821 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1822
1823 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1824 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1825 IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1826
1827 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1828 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback), puDst, uSrc);
1829 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1830
1831 IEM_MC_ADVANCE_RIP_AND_FINISH();
1832 IEM_MC_END();
1833 }
1834}
1835
1836
1837/** Opcode [0x66] 0x0f 0x38 0xf1. */
1838FNIEMOP_DEF(iemOp_movbe_Mv_Gv)
1839{
1840 IEMOP_MNEMONIC2(MR, MOVBE, movbe, Ev, Gv, DISOPTYPE_HARMLESS, 0);
1841 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovBe)
1842 return iemOp_InvalidNeedRM(pVCpu);
1843
1844 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1845 if (!IEM_IS_MODRM_REG_MODE(bRm))
1846 {
1847 /*
1848 * Memory, register.
1849 */
1850 switch (pVCpu->iem.s.enmEffOpSize)
1851 {
1852 case IEMMODE_16BIT:
1853 IEM_MC_BEGIN(0, 2);
1854 IEM_MC_LOCAL(uint16_t, u16Value);
1855 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
1856 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
1857 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1858 IEM_MC_FETCH_GREG_U16(u16Value, IEM_GET_MODRM_REG(pVCpu, bRm));
1859 IEM_MC_BSWAP_LOCAL_U16(u16Value);
1860 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Value);
1861 IEM_MC_ADVANCE_RIP_AND_FINISH();
1862 IEM_MC_END();
1863 break;
1864
1865 case IEMMODE_32BIT:
1866 IEM_MC_BEGIN(0, 2);
1867 IEM_MC_LOCAL(uint32_t, u32Value);
1868 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
1869 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
1870 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1871 IEM_MC_FETCH_GREG_U32(u32Value, IEM_GET_MODRM_REG(pVCpu, bRm));
1872 IEM_MC_BSWAP_LOCAL_U32(u32Value);
1873 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u32Value);
1874 IEM_MC_ADVANCE_RIP_AND_FINISH();
1875 IEM_MC_END();
1876 break;
1877
1878 case IEMMODE_64BIT:
1879 IEM_MC_BEGIN(0, 2);
1880 IEM_MC_LOCAL(uint64_t, u64Value);
1881 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
1882 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
1883 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1884 IEM_MC_FETCH_GREG_U64(u64Value, IEM_GET_MODRM_REG(pVCpu, bRm));
1885 IEM_MC_BSWAP_LOCAL_U64(u64Value);
1886 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u64Value);
1887 IEM_MC_ADVANCE_RIP_AND_FINISH();
1888 IEM_MC_END();
1889 break;
1890
1891 IEM_NOT_REACHED_DEFAULT_CASE_RET();
1892 }
1893 }
1894 else
1895 {
1896 /* Reg/reg not supported. */
1897 return IEMOP_RAISE_INVALID_OPCODE();
1898 }
1899}
1900
1901
1902/* Opcode 0xf3 0x0f 0x38 0xf1 - invalid. */
1903
1904
1905/** Opcode 0xf2 0x0f 0x38 0xf1. */
1906FNIEMOP_DEF(iemOp_crc32_Gv_Ev)
1907{
1908 IEMOP_MNEMONIC2(RM, CRC32, crc32, Gd, Ev, DISOPTYPE_HARMLESS, 0);
1909 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42)
1910 return iemOp_InvalidNeedRM(pVCpu);
1911
1912 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1913 if (IEM_IS_MODRM_REG_MODE(bRm))
1914 {
1915 /*
1916 * Register, register.
1917 */
1918 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1919 switch (pVCpu->iem.s.enmEffOpSize)
1920 {
1921 case IEMMODE_16BIT:
1922 IEM_MC_BEGIN(2, 0);
1923 IEM_MC_ARG(uint32_t *, puDst, 0);
1924 IEM_MC_ARG(uint16_t, uSrc, 1);
1925 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1926 IEM_MC_FETCH_GREG_U16(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1927 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback),
1928 puDst, uSrc);
1929 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1930 IEM_MC_ADVANCE_RIP_AND_FINISH();
1931 IEM_MC_END();
1932 break;
1933
1934 case IEMMODE_32BIT:
1935 IEM_MC_BEGIN(2, 0);
1936 IEM_MC_ARG(uint32_t *, puDst, 0);
1937 IEM_MC_ARG(uint32_t, uSrc, 1);
1938 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1939 IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1940 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback),
1941 puDst, uSrc);
1942 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1943 IEM_MC_ADVANCE_RIP_AND_FINISH();
1944 IEM_MC_END();
1945 break;
1946
1947 case IEMMODE_64BIT:
1948 IEM_MC_BEGIN(2, 0);
1949 IEM_MC_ARG(uint32_t *, puDst, 0);
1950 IEM_MC_ARG(uint64_t, uSrc, 1);
1951 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1952 IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1953 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback),
1954 puDst, uSrc);
1955 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1956 IEM_MC_ADVANCE_RIP_AND_FINISH();
1957 IEM_MC_END();
1958 break;
1959
1960 IEM_NOT_REACHED_DEFAULT_CASE_RET();
1961 }
1962 }
1963 else
1964 {
1965 /*
1966 * Register, memory.
1967 */
1968 switch (pVCpu->iem.s.enmEffOpSize)
1969 {
1970 case IEMMODE_16BIT:
1971 IEM_MC_BEGIN(2, 1);
1972 IEM_MC_ARG(uint32_t *, puDst, 0);
1973 IEM_MC_ARG(uint16_t, uSrc, 1);
1974 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1975
1976 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1977 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1978 IEM_MC_FETCH_MEM_U16(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1979
1980 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1981 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback),
1982 puDst, uSrc);
1983 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
1984
1985 IEM_MC_ADVANCE_RIP_AND_FINISH();
1986 IEM_MC_END();
1987 break;
1988
1989 case IEMMODE_32BIT:
1990 IEM_MC_BEGIN(2, 1);
1991 IEM_MC_ARG(uint32_t *, puDst, 0);
1992 IEM_MC_ARG(uint32_t, uSrc, 1);
1993 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1994
1995 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1996 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1997 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1998
1999 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
2000 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback),
2001 puDst, uSrc);
2002 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
2003
2004 IEM_MC_ADVANCE_RIP_AND_FINISH();
2005 IEM_MC_END();
2006 break;
2007
2008 case IEMMODE_64BIT:
2009 IEM_MC_BEGIN(2, 1);
2010 IEM_MC_ARG(uint32_t *, puDst, 0);
2011 IEM_MC_ARG(uint64_t, uSrc, 1);
2012 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2013
2014 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2015 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2016 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2017
2018 IEM_MC_REF_GREG_U32(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
2019 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback),
2020 puDst, uSrc);
2021 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(puDst);
2022
2023 IEM_MC_ADVANCE_RIP_AND_FINISH();
2024 IEM_MC_END();
2025 break;
2026
2027 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2028 }
2029 }
2030}
2031
2032
2033/* Opcode 0x0f 0x38 0xf2 - invalid (vex only). */
2034/* Opcode 0x66 0x0f 0x38 0xf2 - invalid. */
2035/* Opcode 0xf3 0x0f 0x38 0xf2 - invalid. */
2036/* Opcode 0xf2 0x0f 0x38 0xf2 - invalid. */
2037
2038/* Opcode 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
2039/* Opcode 0x66 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
2040/* Opcode 0xf3 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
2041/* Opcode 0xf2 0x0f 0x38 0xf3 - invalid (vex only - group 17). */
2042
2043/* Opcode 0x0f 0x38 0xf4 - invalid. */
2044/* Opcode 0x66 0x0f 0x38 0xf4 - invalid. */
2045/* Opcode 0xf3 0x0f 0x38 0xf4 - invalid. */
2046/* Opcode 0xf2 0x0f 0x38 0xf4 - invalid. */
2047
2048/* Opcode 0x0f 0x38 0xf5 - invalid (vex only). */
2049/* Opcode 0x66 0x0f 0x38 0xf5 - invalid. */
2050/* Opcode 0xf3 0x0f 0x38 0xf5 - invalid (vex only). */
2051/* Opcode 0xf2 0x0f 0x38 0xf5 - invalid (vex only). */
2052
2053/* Opcode 0x0f 0x38 0xf6 - invalid. */
2054
2055#define ADX_EMIT(a_Variant) \
2056 do \
2057 { \
2058 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAdx) \
2059 return iemOp_InvalidNeedRM(pVCpu); \
2060 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
2061 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
2062 { \
2063 if (IEM_IS_MODRM_REG_MODE(bRm)) \
2064 { \
2065 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
2066 IEM_MC_BEGIN(3, 0); \
2067 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
2068 IEM_MC_ARG(uint32_t *, pEFlags, 1); \
2069 IEM_MC_ARG(uint64_t, u64Src, 2); \
2070 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2071 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2072 IEM_MC_REF_EFLAGS(pEFlags); \
2073 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAdx, iemAImpl_## a_Variant ##_u64, iemAImpl_## a_Variant ##_u64_fallback), \
2074 pu64Dst, pEFlags, u64Src); \
2075 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2076 IEM_MC_END(); \
2077 } \
2078 else \
2079 { \
2080 IEM_MC_BEGIN(3, 1); \
2081 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
2082 IEM_MC_ARG(uint32_t *, pEFlags, 1); \
2083 IEM_MC_ARG(uint64_t, u64Src, 2); \
2084 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2085 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
2086 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
2087 IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2088 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2089 IEM_MC_REF_EFLAGS(pEFlags); \
2090 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAdx, iemAImpl_## a_Variant ##_u64, iemAImpl_## a_Variant ##_u64_fallback), \
2091 pu64Dst, pEFlags, u64Src); \
2092 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2093 IEM_MC_END(); \
2094 } \
2095 } \
2096 else \
2097 { \
2098 if (IEM_IS_MODRM_REG_MODE(bRm)) \
2099 { \
2100 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
2101 IEM_MC_BEGIN(3, 0); \
2102 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
2103 IEM_MC_ARG(uint32_t *, pEFlags, 1); \
2104 IEM_MC_ARG(uint32_t, u32Src, 2); \
2105 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2106 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); \
2107 IEM_MC_REF_EFLAGS(pEFlags); \
2108 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAdx, iemAImpl_## a_Variant ##_u32, iemAImpl_## a_Variant ##_u32_fallback), \
2109 pu32Dst, pEFlags, u32Src); \
2110 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2111 IEM_MC_END(); \
2112 } \
2113 else \
2114 { \
2115 IEM_MC_BEGIN(3, 1); \
2116 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
2117 IEM_MC_ARG(uint32_t *, pEFlags, 1); \
2118 IEM_MC_ARG(uint32_t, u32Src, 2); \
2119 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2120 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1); \
2121 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
2122 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2123 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
2124 IEM_MC_REF_EFLAGS(pEFlags); \
2125 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAdx, iemAImpl_## a_Variant ##_u32, iemAImpl_## a_Variant ##_u32_fallback), \
2126 pu32Dst, pEFlags, u32Src); \
2127 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
2128 IEM_MC_END(); \
2129 } \
2130 } \
2131 } while(0)
2132
2133/** Opcode 0x66 0x0f 0x38 0xf6. */
2134FNIEMOP_DEF(iemOp_adcx_Gy_Ey)
2135{
2136 IEMOP_MNEMONIC2(RM, ADCX, adcx, Gy, Ey, DISOPTYPE_HARMLESS, 0);
2137 ADX_EMIT(adcx);
2138}
2139
2140
2141/** Opcode 0xf3 0x0f 0x38 0xf6. */
2142FNIEMOP_DEF(iemOp_adox_Gy_Ey)
2143{
2144 IEMOP_MNEMONIC2(RM, ADOX, adox, Gy, Ey, DISOPTYPE_HARMLESS, 0);
2145 ADX_EMIT(adox);
2146}
2147
2148
2149/* Opcode 0xf2 0x0f 0x38 0xf6 - invalid (vex only). */
2150
2151/* Opcode 0x0f 0x38 0xf7 - invalid (vex only). */
2152/* Opcode 0x66 0x0f 0x38 0xf7 - invalid (vex only). */
2153/* Opcode 0xf3 0x0f 0x38 0xf7 - invalid (vex only). */
2154/* Opcode 0xf2 0x0f 0x38 0xf7 - invalid (vex only). */
2155
2156/* Opcode 0x0f 0x38 0xf8 - invalid. */
2157/* Opcode 0x66 0x0f 0x38 0xf8 - invalid. */
2158/* Opcode 0xf3 0x0f 0x38 0xf8 - invalid. */
2159/* Opcode 0xf2 0x0f 0x38 0xf8 - invalid. */
2160
2161/* Opcode 0x0f 0x38 0xf9 - invalid. */
2162/* Opcode 0x66 0x0f 0x38 0xf9 - invalid. */
2163/* Opcode 0xf3 0x0f 0x38 0xf9 - invalid. */
2164/* Opcode 0xf2 0x0f 0x38 0xf9 - invalid. */
2165
2166/* Opcode 0x0f 0x38 0xfa - invalid. */
2167/* Opcode 0x66 0x0f 0x38 0xfa - invalid. */
2168/* Opcode 0xf3 0x0f 0x38 0xfa - invalid. */
2169/* Opcode 0xf2 0x0f 0x38 0xfa - invalid. */
2170
2171/* Opcode 0x0f 0x38 0xfb - invalid. */
2172/* Opcode 0x66 0x0f 0x38 0xfb - invalid. */
2173/* Opcode 0xf3 0x0f 0x38 0xfb - invalid. */
2174/* Opcode 0xf2 0x0f 0x38 0xfb - invalid. */
2175
2176/* Opcode 0x0f 0x38 0xfc - invalid. */
2177/* Opcode 0x66 0x0f 0x38 0xfc - invalid. */
2178/* Opcode 0xf3 0x0f 0x38 0xfc - invalid. */
2179/* Opcode 0xf2 0x0f 0x38 0xfc - invalid. */
2180
2181/* Opcode 0x0f 0x38 0xfd - invalid. */
2182/* Opcode 0x66 0x0f 0x38 0xfd - invalid. */
2183/* Opcode 0xf3 0x0f 0x38 0xfd - invalid. */
2184/* Opcode 0xf2 0x0f 0x38 0xfd - invalid. */
2185
2186/* Opcode 0x0f 0x38 0xfe - invalid. */
2187/* Opcode 0x66 0x0f 0x38 0xfe - invalid. */
2188/* Opcode 0xf3 0x0f 0x38 0xfe - invalid. */
2189/* Opcode 0xf2 0x0f 0x38 0xfe - invalid. */
2190
2191/* Opcode 0x0f 0x38 0xff - invalid. */
2192/* Opcode 0x66 0x0f 0x38 0xff - invalid. */
2193/* Opcode 0xf3 0x0f 0x38 0xff - invalid. */
2194/* Opcode 0xf2 0x0f 0x38 0xff - invalid. */
2195
2196
2197/**
2198 * Three byte opcode map, first two bytes are 0x0f 0x38.
2199 * @sa g_apfnVexMap2
2200 */
2201IEM_STATIC const PFNIEMOP g_apfnThreeByte0f38[] =
2202{
2203 /* no prefix, 066h prefix f3h prefix, f2h prefix */
2204 /* 0x00 */ iemOp_pshufb_Pq_Qq, iemOp_pshufb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2205 /* 0x01 */ iemOp_phaddw_Pq_Qq, iemOp_phaddw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2206 /* 0x02 */ iemOp_phaddd_Pq_Qq, iemOp_phaddd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2207 /* 0x03 */ iemOp_phaddsw_Pq_Qq, iemOp_phaddsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2208 /* 0x04 */ iemOp_pmaddubsw_Pq_Qq, iemOp_pmaddubsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2209 /* 0x05 */ iemOp_phsubw_Pq_Qq, iemOp_phsubw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2210 /* 0x06 */ iemOp_phsubd_Pq_Qq, iemOp_phsubd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2211 /* 0x07 */ iemOp_phsubsw_Pq_Qq, iemOp_phsubsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2212 /* 0x08 */ iemOp_psignb_Pq_Qq, iemOp_psignb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2213 /* 0x09 */ iemOp_psignw_Pq_Qq, iemOp_psignw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2214 /* 0x0a */ iemOp_psignd_Pq_Qq, iemOp_psignd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2215 /* 0x0b */ iemOp_pmulhrsw_Pq_Qq, iemOp_pmulhrsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2216 /* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
2217 /* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
2218 /* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
2219 /* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
2220
2221 /* 0x10 */ iemOp_InvalidNeedRM, iemOp_pblendvb_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2222 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
2223 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
2224 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
2225 /* 0x14 */ iemOp_InvalidNeedRM, iemOp_blendvps_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2226 /* 0x15 */ iemOp_InvalidNeedRM, iemOp_blendvpd_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2227 /* 0x16 */ IEMOP_X4(iemOp_InvalidNeedRM),
2228 /* 0x17 */ iemOp_InvalidNeedRM, iemOp_ptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2229 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
2230 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
2231 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
2232 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
2233 /* 0x1c */ iemOp_pabsb_Pq_Qq, iemOp_pabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2234 /* 0x1d */ iemOp_pabsw_Pq_Qq, iemOp_pabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2235 /* 0x1e */ iemOp_pabsd_Pq_Qq, iemOp_pabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2236 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
2237
2238 /* 0x20 */ iemOp_InvalidNeedRM, iemOp_pmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2239 /* 0x21 */ iemOp_InvalidNeedRM, iemOp_pmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2240 /* 0x22 */ iemOp_InvalidNeedRM, iemOp_pmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2241 /* 0x23 */ iemOp_InvalidNeedRM, iemOp_pmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2242 /* 0x24 */ iemOp_InvalidNeedRM, iemOp_pmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2243 /* 0x25 */ iemOp_InvalidNeedRM, iemOp_pmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2244 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
2245 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
2246 /* 0x28 */ iemOp_InvalidNeedRM, iemOp_pmuldq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2247 /* 0x29 */ iemOp_InvalidNeedRM, iemOp_pcmpeqq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2248 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_movntdqa_Vdq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2249 /* 0x2b */ iemOp_InvalidNeedRM, iemOp_packusdw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2250 /* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRM),
2251 /* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRM),
2252 /* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRM),
2253 /* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRM),
2254
2255 /* 0x30 */ iemOp_InvalidNeedRM, iemOp_pmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2256 /* 0x31 */ iemOp_InvalidNeedRM, iemOp_pmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2257 /* 0x32 */ iemOp_InvalidNeedRM, iemOp_pmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2258 /* 0x33 */ iemOp_InvalidNeedRM, iemOp_pmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2259 /* 0x34 */ iemOp_InvalidNeedRM, iemOp_pmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2260 /* 0x35 */ iemOp_InvalidNeedRM, iemOp_pmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2261 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
2262 /* 0x37 */ iemOp_InvalidNeedRM, iemOp_pcmpgtq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2263 /* 0x38 */ iemOp_InvalidNeedRM, iemOp_pminsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2264 /* 0x39 */ iemOp_InvalidNeedRM, iemOp_pminsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2265 /* 0x3a */ iemOp_InvalidNeedRM, iemOp_pminuw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2266 /* 0x3b */ iemOp_InvalidNeedRM, iemOp_pminud_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2267 /* 0x3c */ iemOp_InvalidNeedRM, iemOp_pmaxsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2268 /* 0x3d */ iemOp_InvalidNeedRM, iemOp_pmaxsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2269 /* 0x3e */ iemOp_InvalidNeedRM, iemOp_pmaxuw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2270 /* 0x3f */ iemOp_InvalidNeedRM, iemOp_pmaxud_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2271
2272 /* 0x40 */ iemOp_InvalidNeedRM, iemOp_pmulld_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2273 /* 0x41 */ iemOp_InvalidNeedRM, iemOp_phminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2274 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
2275 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
2276 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
2277 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
2278 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
2279 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
2280 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
2281 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
2282 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
2283 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
2284 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
2285 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
2286 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
2287 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
2288
2289 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
2290 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
2291 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
2292 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
2293 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
2294 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
2295 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
2296 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
2297 /* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRM),
2298 /* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRM),
2299 /* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRM),
2300 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
2301 /* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
2302 /* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
2303 /* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
2304 /* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
2305
2306 /* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
2307 /* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
2308 /* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
2309 /* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
2310 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
2311 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
2312 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
2313 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
2314 /* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
2315 /* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
2316 /* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
2317 /* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
2318 /* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
2319 /* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
2320 /* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
2321 /* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
2322
2323 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
2324 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
2325 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
2326 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
2327 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
2328 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
2329 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
2330 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
2331 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
2332 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
2333 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
2334 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
2335 /* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
2336 /* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
2337 /* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
2338 /* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
2339
2340 /* 0x80 */ iemOp_InvalidNeedRM, iemOp_invept_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2341 /* 0x81 */ iemOp_InvalidNeedRM, iemOp_invvpid_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2342 /* 0x82 */ iemOp_InvalidNeedRM, iemOp_invpcid_Gy_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2343 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
2344 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
2345 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
2346 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
2347 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
2348 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
2349 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
2350 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
2351 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
2352 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
2353 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
2354 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
2355 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
2356
2357 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
2358 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
2359 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
2360 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
2361 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
2362 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
2363 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
2364 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
2365 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
2366 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
2367 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
2368 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
2369 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
2370 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
2371 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
2372 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
2373
2374 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2375 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2376 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2377 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2378 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2379 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2380 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2381 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2382 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2383 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2384 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
2385 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
2386 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
2387 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
2388 /* 0xae */ IEMOP_X4(iemOp_InvalidNeedRM),
2389 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
2390
2391 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2392 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2393 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2394 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2395 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2396 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2397 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2398 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2399 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2400 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2401 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
2402 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
2403 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
2404 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
2405 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
2406 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
2407
2408 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2409 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2410 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2411 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2412 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2413 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2414 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2415 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2416 /* 0xc8 */ iemOp_sha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2417 /* 0xc9 */ iemOp_sha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2418 /* 0xca */ iemOp_sha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2419 /* 0xcb */ iemOp_sha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2420 /* 0xcc */ iemOp_sha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2421 /* 0xcd */ iemOp_sha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2422 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
2423 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
2424
2425 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2426 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2427 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2428 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2429 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2430 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2431 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2432 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2433 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2434 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2435 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
2436 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_aesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2437 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_aesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2438 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_aesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2439 /* 0xde */ iemOp_InvalidNeedRM, iemOp_aesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2440 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_aesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2441
2442 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2443 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2444 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2445 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2446 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2447 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2448 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2449 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2450 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2451 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2452 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
2453 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
2454 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
2455 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
2456 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
2457 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
2458
2459 /* 0xf0 */ iemOp_movbe_Gv_Mv, iemOp_movbe_Gv_Mv, iemOp_InvalidNeedRM, iemOp_crc32_Gd_Eb,
2460 /* 0xf1 */ iemOp_movbe_Mv_Gv, iemOp_movbe_Mv_Gv, iemOp_InvalidNeedRM, iemOp_crc32_Gv_Ev,
2461 /* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2462 /* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2463 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2464 /* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2465 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_adcx_Gy_Ey, iemOp_adox_Gy_Ey, iemOp_InvalidNeedRM,
2466 /* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2467 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2468 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2469 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
2470 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
2471 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
2472 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
2473 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
2474 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
2475};
2476AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f38) == 1024);
2477
2478/** @} */
2479
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