IEMAllInstructionsThree0f3a.cpp.h@ 97534

Last change on this file since 97534 was 97534, checked in by vboxsync, 2 years ago
IEM: Reworked [V]MOVxDUP to be done directly in microcode. Added MOVBE instruction.
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File size: 41.4 KB

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1	/* $Id: IEMAllInstructionsThree0f3a.cpp.h 97534 2022-11-14 16:55:57Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4	*
5	* @remarks IEMAllInstructionsVexMap3.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle and/or its affiliates.
11	*
12	* This file is part of VirtualBox base platform packages, as
13	* available from https://www.virtualbox.org.
14	*
15	* This program is free software; you can redistribute it and/or
16	* modify it under the terms of the GNU General Public License
17	* as published by the Free Software Foundation, in version 3 of the
18	* License.
19	*
20	* This program is distributed in the hope that it will be useful, but
21	* WITHOUT ANY WARRANTY; without even the implied warranty of
22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23	* General Public License for more details.
24	*
25	* You should have received a copy of the GNU General Public License
26	* along with this program; if not, see <https://www.gnu.org/licenses>.
27	*
28	* SPDX-License-Identifier: GPL-3.0-only
29	*/
30
31
32	/** @name Three byte opcodes with first two bytes 0x0f 0x3a
33	* @{
34	*/
35
36	/**
37	* Common worker for SSSE3 instructions on the forms:
38	* pxxx xmm1, xmm2/mem128, imm8
39	*
40	* Proper alignment of the 128-bit operand is enforced.
41	* Exceptions type 4. SSSE3 cpuid checks.
42	*
43	* @sa iemOpCommonSse41_FullFullImm8_To_Full
44	*/
45	FNIEMOP_DEF_1(iemOpCommonSsse3_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
46	{
47	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48	if (IEM_IS_MODRM_REG_MODE(bRm))
49	{
50	/*
51	* Register, register.
52	*/
53	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
54	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
55	IEM_MC_BEGIN(3, 0);
56	IEM_MC_ARG(PRTUINT128U, puDst, 0);
57	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
58	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
59	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
60	IEM_MC_PREPARE_SSE_USAGE();
61	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
62	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
63	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
64	IEM_MC_ADVANCE_RIP_AND_FINISH();
65	IEM_MC_END();
66	}
67	else
68	{
69	/*
70	* Register, memory.
71	*/
72	IEM_MC_BEGIN(3, 2);
73	IEM_MC_ARG(PRTUINT128U, puDst, 0);
74	IEM_MC_LOCAL(RTUINT128U, uSrc);
75	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
76	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
77
78	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
79	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
80	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
81	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
82	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
83	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
84
85	IEM_MC_PREPARE_SSE_USAGE();
86	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
87	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
88
89	IEM_MC_ADVANCE_RIP_AND_FINISH();
90	IEM_MC_END();
91	}
92	}
93
94
95	/**
96	* Common worker for SSE 4.1 instructions on the forms:
97	* pxxx xmm1, xmm2/mem128, imm8
98	*
99	* Proper alignment of the 128-bit operand is enforced.
100	* Exceptions type 4. SSE 4.1 cpuid checks.
101	*
102	* @sa iemOpCommonSsse3_FullFullImm8_To_Full
103	*/
104	FNIEMOP_DEF_1(iemOpCommonSse41_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
105	{
106	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
107	if (IEM_IS_MODRM_REG_MODE(bRm))
108	{
109	/*
110	* Register, register.
111	*/
112	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
113	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
114	IEM_MC_BEGIN(3, 0);
115	IEM_MC_ARG(PRTUINT128U, puDst, 0);
116	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
117	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
118	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
119	IEM_MC_PREPARE_SSE_USAGE();
120	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
121	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
122	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
123	IEM_MC_ADVANCE_RIP_AND_FINISH();
124	IEM_MC_END();
125	}
126	else
127	{
128	/*
129	* Register, memory.
130	*/
131	IEM_MC_BEGIN(3, 2);
132	IEM_MC_ARG(PRTUINT128U, puDst, 0);
133	IEM_MC_LOCAL(RTUINT128U, uSrc);
134	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
135	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
136
137	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
138	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
139	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
140	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
141	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
142	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
143
144	IEM_MC_PREPARE_SSE_USAGE();
145	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
146	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
147
148	IEM_MC_ADVANCE_RIP_AND_FINISH();
149	IEM_MC_END();
150	}
151	}
152
153
154	/**
155	* Common worker for SSE-style AES-NI instructions of the form:
156	* aesxxx xmm1, xmm2/mem128, imm8
157	*
158	* Proper alignment of the 128-bit operand is enforced.
159	* Exceptions type 4. AES-NI cpuid checks.
160	*
161	* @sa iemOpCommonSsse3_FullFullImm8_To_Full
162	* @sa iemOpCommonSse41_FullFullImm8_To_Full
163	*/
164	FNIEMOP_DEF_1(iemOpCommonAesNi_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
165	{
166	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
167	if (IEM_IS_MODRM_REG_MODE(bRm))
168	{
169	/*
170	* Register, register.
171	*/
172	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
173	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
174	IEM_MC_BEGIN(3, 0);
175	IEM_MC_ARG(PRTUINT128U, puDst, 0);
176	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
177	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
178	IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT();
179	IEM_MC_PREPARE_SSE_USAGE();
180	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
181	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
182	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
183	IEM_MC_ADVANCE_RIP_AND_FINISH();
184	IEM_MC_END();
185	}
186	else
187	{
188	/*
189	* Register, memory.
190	*/
191	IEM_MC_BEGIN(3, 2);
192	IEM_MC_ARG(PRTUINT128U, puDst, 0);
193	IEM_MC_LOCAL(RTUINT128U, uSrc);
194	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
195	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
196
197	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
198	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
199	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
200	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
201	IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT();
202	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
203
204	IEM_MC_PREPARE_SSE_USAGE();
205	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
206	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
207
208	IEM_MC_ADVANCE_RIP_AND_FINISH();
209	IEM_MC_END();
210	}
211	}
212
213
214	/** Opcode 0x66 0x0f 0x00 - invalid (vex only). */
215	/** Opcode 0x66 0x0f 0x01 - invalid (vex only). */
216	/** Opcode 0x66 0x0f 0x02 - invalid (vex only). */
217	/* Opcode 0x66 0x0f 0x03 - invalid */
218	/** Opcode 0x66 0x0f 0x04 - invalid (vex only). */
219	/** Opcode 0x66 0x0f 0x05 - invalid (vex only). */
220	/* Opcode 0x66 0x0f 0x06 - invalid (vex only) */
221	/* Opcode 0x66 0x0f 0x07 - invalid */
222	/** Opcode 0x66 0x0f 0x08. */
223	FNIEMOP_STUB(iemOp_roundps_Vx_Wx_Ib);
224	/** Opcode 0x66 0x0f 0x09. */
225	FNIEMOP_STUB(iemOp_roundpd_Vx_Wx_Ib);
226	/** Opcode 0x66 0x0f 0x0a. */
227	FNIEMOP_STUB(iemOp_roundss_Vss_Wss_Ib);
228	/** Opcode 0x66 0x0f 0x0b. */
229	FNIEMOP_STUB(iemOp_roundsd_Vsd_Wsd_Ib);
230
231
232	/** Opcode 0x66 0x0f 0x0c. */
233	FNIEMOP_DEF(iemOp_blendps_Vx_Wx_Ib)
234	{
235	IEMOP_MNEMONIC3(RMI, BLENDPS, blendps, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
236	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
237	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback));
238	}
239
240
241	/** Opcode 0x66 0x0f 0x0d. */
242	FNIEMOP_DEF(iemOp_blendpd_Vx_Wx_Ib)
243	{
244	IEMOP_MNEMONIC3(RMI, BLENDPD, blendpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
245	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
246	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback));
247	}
248
249
250	/** Opcode 0x66 0x0f 0x0e. */
251	FNIEMOP_DEF(iemOp_pblendw_Vx_Wx_Ib)
252	{
253	IEMOP_MNEMONIC3(RMI, PBLENDW, pblendw, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
254	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
255	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback));
256	}
257
258
259	/** Opcode 0x0f 0x0f. */
260	FNIEMOP_DEF(iemOp_palignr_Pq_Qq_Ib)
261	{
262	IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Pq, Qq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
263	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
264	if (IEM_IS_MODRM_REG_MODE(bRm))
265	{
266	/*
267	* Register, register.
268	*/
269	/** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
270	/** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
271	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
272	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
273	IEM_MC_BEGIN(3, 0);
274	IEM_MC_ARG(uint64_t *, pDst, 0);
275	IEM_MC_ARG(uint64_t, uSrc, 1);
276	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
277	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
278	IEM_MC_PREPARE_FPU_USAGE();
279	IEM_MC_FPU_TO_MMX_MODE();
280	IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
281	IEM_MC_FETCH_MREG_U64(uSrc, IEM_GET_MODRM_RM_8(bRm));
282	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
283	pDst, uSrc, bImmArg);
284	IEM_MC_MODIFIED_MREG_BY_REF(pDst);
285	IEM_MC_ADVANCE_RIP_AND_FINISH();
286	IEM_MC_END();
287	}
288	else
289	{
290	/*
291	* Register, memory.
292	*/
293	IEM_MC_BEGIN(3, 1);
294	IEM_MC_ARG(uint64_t *, pDst, 0);
295	IEM_MC_ARG(uint64_t, uSrc, 1);
296	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
297
298	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
299	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
300	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
301	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
302	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
303	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
304
305	IEM_MC_PREPARE_FPU_USAGE();
306	IEM_MC_FPU_TO_MMX_MODE();
307	IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
308	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
309	pDst, uSrc, bImmArg);
310	IEM_MC_MODIFIED_MREG_BY_REF(pDst);
311
312	IEM_MC_ADVANCE_RIP_AND_FINISH();
313	IEM_MC_END();
314	}
315	}
316
317
318	/** Opcode 0x66 0x0f 0x0f. */
319	FNIEMOP_DEF(iemOp_palignr_Vx_Wx_Ib)
320	{
321	IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
322	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFullImm8_To_Full,
323	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback));
324	}
325
326
327	/* Opcode 0x66 0x0f 0x10 - invalid */
328	/* Opcode 0x66 0x0f 0x11 - invalid */
329	/* Opcode 0x66 0x0f 0x12 - invalid */
330	/* Opcode 0x66 0x0f 0x13 - invalid */
331	/** Opcode 0x66 0x0f 0x14. */
332	FNIEMOP_STUB(iemOp_pextrb_RdMb_Vdq_Ib);
333	/** Opcode 0x66 0x0f 0x15. */
334	FNIEMOP_STUB(iemOp_pextrw_RdMw_Vdq_Ib);
335	/** Opcode 0x66 0x0f 0x16. */
336	FNIEMOP_STUB(iemOp_pextrd_q_RdMw_Vdq_Ib);
337	/** Opcode 0x66 0x0f 0x17. */
338	FNIEMOP_STUB(iemOp_extractps_Ed_Vdq_Ib);
339	/* Opcode 0x66 0x0f 0x18 - invalid (vex only). */
340	/* Opcode 0x66 0x0f 0x19 - invalid (vex only). */
341	/* Opcode 0x66 0x0f 0x1a - invalid */
342	/* Opcode 0x66 0x0f 0x1b - invalid */
343	/* Opcode 0x66 0x0f 0x1c - invalid */
344	/* Opcode 0x66 0x0f 0x1d - invalid (vex only). */
345	/* Opcode 0x66 0x0f 0x1e - invalid */
346	/* Opcode 0x66 0x0f 0x1f - invalid */
347
348
349	/** Opcode 0x66 0x0f 0x20. */
350	FNIEMOP_STUB(iemOp_pinsrb_Vdq_RyMb_Ib);
351	/** Opcode 0x66 0x0f 0x21, */
352	FNIEMOP_STUB(iemOp_insertps_Vdq_UdqMd_Ib);
353
354
355	FNIEMOP_DEF(iemOp_pinsrd_q_Vdq_Ey_Ib)
356	{
357	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
358	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
359	{
360	/**
361	* @opcode 0x22
362	* @opcodesub rex.w=1
363	* @oppfx 0x66
364	* @opcpuid sse
365	*/
366	IEMOP_MNEMONIC3(RMI, PINSRQ, pinsrq, Vq, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
367	if (IEM_IS_MODRM_REG_MODE(bRm))
368	{
369	/*
370	* XMM, greg64.
371	*/
372	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
373	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
374	IEM_MC_BEGIN(0, 1);
375	IEM_MC_LOCAL(uint64_t, uSrc);
376	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
377	IEM_MC_PREPARE_SSE_USAGE();
378	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
379	IEM_MC_AND_LOCAL_U8(bImm, 1);
380	IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/, uSrc);
381	IEM_MC_ADVANCE_RIP_AND_FINISH();
382	IEM_MC_END();
383	}
384	else
385	{
386	/*
387	* XMM, [mem64].
388	*/
389	IEM_MC_BEGIN(0, 2);
390	IEM_MC_LOCAL(uint64_t, uSrc);
391	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
392
393	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
394	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
395	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
396	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
397	IEM_MC_PREPARE_SSE_USAGE();
398
399	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
400	IEM_MC_AND_LOCAL_U8(bImm, 1);
401	IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/, uSrc);
402	IEM_MC_ADVANCE_RIP_AND_FINISH();
403	IEM_MC_END();
404	}
405	}
406	else
407	{
408	/**
409	* @opdone
410	* @opcode 0x22
411	* @opcodesub rex.w=0
412	* @oppfx 0x66
413	* @opcpuid sse
414	*/
415	IEMOP_MNEMONIC3(RMI, PINSRD, pinsrd, Vd, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
416	if (IEM_IS_MODRM_REG_MODE(bRm))
417	{
418	/*
419	* XMM, greg32.
420	*/
421	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
422	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
423	IEM_MC_BEGIN(0, 1);
424	IEM_MC_LOCAL(uint32_t, uSrc);
425	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
426	IEM_MC_PREPARE_SSE_USAGE();
427	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
428	IEM_MC_AND_LOCAL_U8(bImm, 3);
429	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/, uSrc);
430	IEM_MC_ADVANCE_RIP_AND_FINISH();
431	IEM_MC_END();
432	}
433	else
434	{
435	/*
436	* XMM, [mem32].
437	*/
438	IEM_MC_BEGIN(0, 2);
439	IEM_MC_LOCAL(uint32_t, uSrc);
440	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
441
442	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
443	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
444	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
445	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
446	IEM_MC_PREPARE_SSE_USAGE();
447
448	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
449	IEM_MC_AND_LOCAL_U8(bImm, 3);
450	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/, uSrc);
451	IEM_MC_ADVANCE_RIP_AND_FINISH();
452	IEM_MC_END();
453	}
454	}
455	}
456
457
458	/* Opcode 0x66 0x0f 0x23 - invalid */
459	/* Opcode 0x66 0x0f 0x24 - invalid */
460	/* Opcode 0x66 0x0f 0x25 - invalid */
461	/* Opcode 0x66 0x0f 0x26 - invalid */
462	/* Opcode 0x66 0x0f 0x27 - invalid */
463	/* Opcode 0x66 0x0f 0x28 - invalid */
464	/* Opcode 0x66 0x0f 0x29 - invalid */
465	/* Opcode 0x66 0x0f 0x2a - invalid */
466	/* Opcode 0x66 0x0f 0x2b - invalid */
467	/* Opcode 0x66 0x0f 0x2c - invalid */
468	/* Opcode 0x66 0x0f 0x2d - invalid */
469	/* Opcode 0x66 0x0f 0x2e - invalid */
470	/* Opcode 0x66 0x0f 0x2f - invalid */
471
472
473	/* Opcode 0x66 0x0f 0x30 - invalid */
474	/* Opcode 0x66 0x0f 0x31 - invalid */
475	/* Opcode 0x66 0x0f 0x32 - invalid */
476	/* Opcode 0x66 0x0f 0x33 - invalid */
477	/* Opcode 0x66 0x0f 0x34 - invalid */
478	/* Opcode 0x66 0x0f 0x35 - invalid */
479	/* Opcode 0x66 0x0f 0x36 - invalid */
480	/* Opcode 0x66 0x0f 0x37 - invalid */
481	/* Opcode 0x66 0x0f 0x38 - invalid (vex only). */
482	/* Opcode 0x66 0x0f 0x39 - invalid (vex only). */
483	/* Opcode 0x66 0x0f 0x3a - invalid */
484	/* Opcode 0x66 0x0f 0x3b - invalid */
485	/* Opcode 0x66 0x0f 0x3c - invalid */
486	/* Opcode 0x66 0x0f 0x3d - invalid */
487	/* Opcode 0x66 0x0f 0x3e - invalid */
488	/* Opcode 0x66 0x0f 0x3f - invalid */
489
490
491	/** Opcode 0x66 0x0f 0x40. */
492	FNIEMOP_STUB(iemOp_dpps_Vx_Wx_Ib);
493	/** Opcode 0x66 0x0f 0x41, */
494	FNIEMOP_STUB(iemOp_dppd_Vdq_Wdq_Ib);
495	/** Opcode 0x66 0x0f 0x42. */
496	FNIEMOP_STUB(iemOp_mpsadbw_Vx_Wx_Ib);
497	/* Opcode 0x66 0x0f 0x43 - invalid */
498
499
500	/** Opcode 0x66 0x0f 0x44. */
501	FNIEMOP_DEF(iemOp_pclmulqdq_Vdq_Wdq_Ib)
502	{
503	IEMOP_MNEMONIC3(RMI, PCLMULQDQ, pclmulqdq, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
504
505	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
506	if (IEM_IS_MODRM_REG_MODE(bRm))
507	{
508	/*
509	* Register, register.
510	*/
511	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
512	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
513	IEM_MC_BEGIN(3, 0);
514	IEM_MC_ARG(PRTUINT128U, puDst, 0);
515	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
516	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
517	IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT();
518	IEM_MC_PREPARE_SSE_USAGE();
519	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
520	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
521	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
522	iemAImpl_pclmulqdq_u128,
523	iemAImpl_pclmulqdq_u128_fallback),
524	puDst, puSrc, bImmArg);
525	IEM_MC_ADVANCE_RIP_AND_FINISH();
526	IEM_MC_END();
527	}
528	else
529	{
530	/*
531	* Register, memory.
532	*/
533	IEM_MC_BEGIN(3, 2);
534	IEM_MC_ARG(PRTUINT128U, puDst, 0);
535	IEM_MC_LOCAL(RTUINT128U, uSrc);
536	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
537	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
538
539	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
540	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
541	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
542	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
543	IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT();
544	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
545
546	IEM_MC_PREPARE_SSE_USAGE();
547	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
548	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
549	iemAImpl_pclmulqdq_u128,
550	iemAImpl_pclmulqdq_u128_fallback),
551	puDst, puSrc, bImmArg);
552
553	IEM_MC_ADVANCE_RIP_AND_FINISH();
554	IEM_MC_END();
555	}
556	}
557
558
559	/* Opcode 0x66 0x0f 0x45 - invalid */
560	/* Opcode 0x66 0x0f 0x46 - invalid (vex only) */
561	/* Opcode 0x66 0x0f 0x47 - invalid */
562	/* Opcode 0x66 0x0f 0x48 - invalid */
563	/* Opcode 0x66 0x0f 0x49 - invalid */
564	/* Opcode 0x66 0x0f 0x4a - invalid (vex only). */
565	/* Opcode 0x66 0x0f 0x4b - invalid (vex only). */
566	/* Opcode 0x66 0x0f 0x4c - invalid (vex only). */
567	/* Opcode 0x66 0x0f 0x4d - invalid */
568	/* Opcode 0x66 0x0f 0x4e - invalid */
569	/* Opcode 0x66 0x0f 0x4f - invalid */
570
571
572	/* Opcode 0x66 0x0f 0x50 - invalid */
573	/* Opcode 0x66 0x0f 0x51 - invalid */
574	/* Opcode 0x66 0x0f 0x52 - invalid */
575	/* Opcode 0x66 0x0f 0x53 - invalid */
576	/* Opcode 0x66 0x0f 0x54 - invalid */
577	/* Opcode 0x66 0x0f 0x55 - invalid */
578	/* Opcode 0x66 0x0f 0x56 - invalid */
579	/* Opcode 0x66 0x0f 0x57 - invalid */
580	/* Opcode 0x66 0x0f 0x58 - invalid */
581	/* Opcode 0x66 0x0f 0x59 - invalid */
582	/* Opcode 0x66 0x0f 0x5a - invalid */
583	/* Opcode 0x66 0x0f 0x5b - invalid */
584	/* Opcode 0x66 0x0f 0x5c - invalid */
585	/* Opcode 0x66 0x0f 0x5d - invalid */
586	/* Opcode 0x66 0x0f 0x5e - invalid */
587	/* Opcode 0x66 0x0f 0x5f - invalid */
588
589
590	/** Opcode 0x66 0x0f 0x60. */
591	FNIEMOP_STUB(iemOp_pcmpestrm_Vdq_Wdq_Ib);
592	/** Opcode 0x66 0x0f 0x61, */
593	FNIEMOP_STUB(iemOp_pcmpestri_Vdq_Wdq_Ib);
594	/** Opcode 0x66 0x0f 0x62. */
595	FNIEMOP_STUB(iemOp_pcmpistrm_Vdq_Wdq_Ib);
596
597
598	/** Opcode 0x66 0x0f 0x63*/
599	FNIEMOP_DEF(iemOp_pcmpistri_Vdq_Wdq_Ib)
600	{
601	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
602	if (IEM_IS_MODRM_REG_MODE(bRm))
603	{
604	/*
605	* Register, register.
606	*/
607	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
608	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
609	IEM_MC_BEGIN(4, 1);
610	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
611	IEM_MC_ARG(uint32_t *, pEFlags, 1);
612	IEM_MC_LOCAL(IEMPCMPISTRISRC, Src);
613	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRISRC, pSrc, Src, 2);
614	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
615	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
616	IEM_MC_PREPARE_SSE_USAGE();
617	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
618	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
619	IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
620	IEM_MC_REF_EFLAGS(pEFlags);
621	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
622	iemAImpl_pcmpistri_u128,
623	iemAImpl_pcmpistri_u128_fallback),
624	pu32Ecx, pEFlags, pSrc, bImmArg);
625	/** @todo testcase: High dword of RCX cleared? */
626	IEM_MC_ADVANCE_RIP_AND_FINISH();
627	IEM_MC_END();
628	}
629	else
630	{
631	/*
632	* Register, memory.
633	*/
634	IEM_MC_BEGIN(4, 3);
635	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
636	IEM_MC_ARG(uint32_t *, pEFlags, 1);
637	IEM_MC_LOCAL(IEMPCMPISTRISRC, Src);
638	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRISRC, pSrc, Src, 2);
639	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
640
641	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
642	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
643	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
644	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
645	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
646	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
647
648	IEM_MC_PREPARE_SSE_USAGE();
649	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
650	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
651	IEM_MC_REF_EFLAGS(pEFlags);
652	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
653	iemAImpl_pcmpistri_u128,
654	iemAImpl_pcmpistri_u128_fallback),
655	pu32Ecx, pEFlags, pSrc, bImmArg);
656	/** @todo testcase: High dword of RCX cleared? */
657	IEM_MC_ADVANCE_RIP_AND_FINISH();
658	IEM_MC_END();
659	}
660	}
661
662
663	/* Opcode 0x66 0x0f 0x64 - invalid */
664	/* Opcode 0x66 0x0f 0x65 - invalid */
665	/* Opcode 0x66 0x0f 0x66 - invalid */
666	/* Opcode 0x66 0x0f 0x67 - invalid */
667	/* Opcode 0x66 0x0f 0x68 - invalid */
668	/* Opcode 0x66 0x0f 0x69 - invalid */
669	/* Opcode 0x66 0x0f 0x6a - invalid */
670	/* Opcode 0x66 0x0f 0x6b - invalid */
671	/* Opcode 0x66 0x0f 0x6c - invalid */
672	/* Opcode 0x66 0x0f 0x6d - invalid */
673	/* Opcode 0x66 0x0f 0x6e - invalid */
674	/* Opcode 0x66 0x0f 0x6f - invalid */
675
676	/* Opcodes 0x0f 0x70 thru 0x0f 0xb0 are unused. */
677
678
679	/* Opcode 0x0f 0xc0 - invalid */
680	/* Opcode 0x0f 0xc1 - invalid */
681	/* Opcode 0x0f 0xc2 - invalid */
682	/* Opcode 0x0f 0xc3 - invalid */
683	/* Opcode 0x0f 0xc4 - invalid */
684	/* Opcode 0x0f 0xc5 - invalid */
685	/* Opcode 0x0f 0xc6 - invalid */
686	/* Opcode 0x0f 0xc7 - invalid */
687	/* Opcode 0x0f 0xc8 - invalid */
688	/* Opcode 0x0f 0xc9 - invalid */
689	/* Opcode 0x0f 0xca - invalid */
690	/* Opcode 0x0f 0xcb - invalid */
691	/* Opcode 0x0f 0xcc */
692	FNIEMOP_STUB(iemOp_sha1rnds4_Vdq_Wdq_Ib);
693	/* Opcode 0x0f 0xcd - invalid */
694	/* Opcode 0x0f 0xce - invalid */
695	/* Opcode 0x0f 0xcf - invalid */
696
697
698	/* Opcode 0x66 0x0f 0xd0 - invalid */
699	/* Opcode 0x66 0x0f 0xd1 - invalid */
700	/* Opcode 0x66 0x0f 0xd2 - invalid */
701	/* Opcode 0x66 0x0f 0xd3 - invalid */
702	/* Opcode 0x66 0x0f 0xd4 - invalid */
703	/* Opcode 0x66 0x0f 0xd5 - invalid */
704	/* Opcode 0x66 0x0f 0xd6 - invalid */
705	/* Opcode 0x66 0x0f 0xd7 - invalid */
706	/* Opcode 0x66 0x0f 0xd8 - invalid */
707	/* Opcode 0x66 0x0f 0xd9 - invalid */
708	/* Opcode 0x66 0x0f 0xda - invalid */
709	/* Opcode 0x66 0x0f 0xdb - invalid */
710	/* Opcode 0x66 0x0f 0xdc - invalid */
711	/* Opcode 0x66 0x0f 0xdd - invalid */
712	/* Opcode 0x66 0x0f 0xde - invalid */
713
714
715	/* Opcode 0x66 0x0f 0xdf - (aeskeygenassist). */
716	FNIEMOP_DEF(iemOp_aeskeygen_Vdq_Wdq_Ib)
717	{
718	IEMOP_MNEMONIC3(RMI, AESKEYGEN, aeskeygen, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
719	return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFullImm8_To_Full,
720	IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback));
721	}
722
723
724	/* Opcode 0xf2 0x0f 0xf0 - invalid (vex only) */
725
726
727	/**
728	* Three byte opcode map, first two bytes are 0x0f 0x3a.
729	* @sa g_apfnVexMap2
730	*/
731	IEM_STATIC const PFNIEMOP g_apfnThreeByte0f3a[] =
732	{
733	/* no prefix, 066h prefix f3h prefix, f2h prefix */
734	/* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
735	/* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
736	/* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
737	/* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
738	/* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
739	/* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
740	/* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
741	/* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
742	/* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_roundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
743	/* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_roundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
744	/* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_roundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
745	/* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_roundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
746	/* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_blendps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
747	/* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_blendpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
748	/* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_pblendw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
749	/* 0x0f */ iemOp_palignr_Pq_Qq_Ib, iemOp_palignr_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
750
751	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
752	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
753	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
754	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
755	/* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_pextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
756	/* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_pextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
757	/* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_pextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
758	/* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_extractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
759	/* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
760	/* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
761	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
762	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
763	/* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
764	/* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
765	/* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
766	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
767
768	/* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrb_Vdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
769	/* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_insertps_Vdq_UdqMd_Ib,iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
770	/* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrd_q_Vdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
771	/* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
772	/* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
773	/* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
774	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
775	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
776	/* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
777	/* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
778	/* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
779	/* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
780	/* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
781	/* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
782	/* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
783	/* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
784
785	/* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
786	/* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
787	/* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
788	/* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
789	/* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
790	/* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
791	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
792	/* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
793	/* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
794	/* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
795	/* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
796	/* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
797	/* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
798	/* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
799	/* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
800	/* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
801
802	/* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_dpps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
803	/* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_dppd_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
804	/* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_mpsadbw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
805	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
806	/* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_pclmulqdq_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
807	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
808	/* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
809	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
810	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
811	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
812	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
813	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
814	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
815	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
816	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
817	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
818
819	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
820	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
821	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
822	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
823	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
824	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
825	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
826	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
827	/* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
828	/* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
829	/* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
830	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
831	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
832	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
833	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
834	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
835
836	/* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
837	/* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
838	/* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
839	/* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
840	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
841	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
842	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
843	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
844	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
845	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
846	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
847	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
848	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
849	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
850	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
851	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
852
853	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
854	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
855	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
856	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
857	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
858	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
859	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
860	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
861	/* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
862	/* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
863	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
864	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
865	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
866	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
867	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
868	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
869
870	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
871	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
872	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
873	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
874	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
875	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
876	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
877	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
878	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
879	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
880	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
881	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
882	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
883	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
884	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
885	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
886
887	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
888	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
889	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
890	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
891	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
892	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
893	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
894	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
895	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
896	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
897	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
898	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
899	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
900	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
901	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
902	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
903
904	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
905	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
906	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
907	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
908	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
909	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
910	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
911	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
912	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
913	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
914	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
915	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
916	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
917	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
918	/* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
919	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
920
921	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
922	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
923	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
924	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
925	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
926	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
927	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
928	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
929	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
930	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
931	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
932	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
933	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
934	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
935	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
936	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
937
938	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
939	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
940	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
941	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
942	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
943	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
944	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
945	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
946	/* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
947	/* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
948	/* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
949	/* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
950	/* 0xcc */ iemOp_sha1rnds4_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
951	/* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
952	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
953	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
954
955	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
956	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
957	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
958	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
959	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
960	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
961	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
962	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
963	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
964	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
965	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
966	/* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
967	/* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
968	/* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
969	/* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
970	/* 0xdf */ iemOp_InvalidNeedRMImm8, iemOp_aeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
971
972	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
973	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
974	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
975	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
976	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
977	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
978	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
979	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
980	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
981	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
982	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
983	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
984	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
985	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
986	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
987	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
988
989	/* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
990	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
991	/* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
992	/* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
993	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
994	/* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
995	/* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
996	/* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
997	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
998	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
999	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1000	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1001	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1002	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1003	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1004	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1005	};
1006	AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f3a) == 1024);
1007
1008	/** @} */
1009

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h@ 97534

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