IEMAllInstructionsThree0f3a.cpp.h@ 97543

Last change on this file since 97543 was 97543, checked in by vboxsync, 2 years ago
IEM: Modified microcode XMM accessors to fetch specified qword/dword etc.; added PEXTRD instruction.
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File size: 44.9 KB

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1	/* $Id: IEMAllInstructionsThree0f3a.cpp.h 97543 2022-11-15 12:59:28Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4	*
5	* @remarks IEMAllInstructionsVexMap3.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle and/or its affiliates.
11	*
12	* This file is part of VirtualBox base platform packages, as
13	* available from https://www.virtualbox.org.
14	*
15	* This program is free software; you can redistribute it and/or
16	* modify it under the terms of the GNU General Public License
17	* as published by the Free Software Foundation, in version 3 of the
18	* License.
19	*
20	* This program is distributed in the hope that it will be useful, but
21	* WITHOUT ANY WARRANTY; without even the implied warranty of
22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23	* General Public License for more details.
24	*
25	* You should have received a copy of the GNU General Public License
26	* along with this program; if not, see <https://www.gnu.org/licenses>.
27	*
28	* SPDX-License-Identifier: GPL-3.0-only
29	*/
30
31
32	/** @name Three byte opcodes with first two bytes 0x0f 0x3a
33	* @{
34	*/
35
36	/**
37	* Common worker for SSSE3 instructions on the forms:
38	* pxxx xmm1, xmm2/mem128, imm8
39	*
40	* Proper alignment of the 128-bit operand is enforced.
41	* Exceptions type 4. SSSE3 cpuid checks.
42	*
43	* @sa iemOpCommonSse41_FullFullImm8_To_Full
44	*/
45	FNIEMOP_DEF_1(iemOpCommonSsse3_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
46	{
47	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48	if (IEM_IS_MODRM_REG_MODE(bRm))
49	{
50	/*
51	* Register, register.
52	*/
53	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
54	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
55	IEM_MC_BEGIN(3, 0);
56	IEM_MC_ARG(PRTUINT128U, puDst, 0);
57	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
58	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
59	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
60	IEM_MC_PREPARE_SSE_USAGE();
61	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
62	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
63	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
64	IEM_MC_ADVANCE_RIP_AND_FINISH();
65	IEM_MC_END();
66	}
67	else
68	{
69	/*
70	* Register, memory.
71	*/
72	IEM_MC_BEGIN(3, 2);
73	IEM_MC_ARG(PRTUINT128U, puDst, 0);
74	IEM_MC_LOCAL(RTUINT128U, uSrc);
75	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
76	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
77
78	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
79	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
80	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
81	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
82	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
83	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
84
85	IEM_MC_PREPARE_SSE_USAGE();
86	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
87	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
88
89	IEM_MC_ADVANCE_RIP_AND_FINISH();
90	IEM_MC_END();
91	}
92	}
93
94
95	/**
96	* Common worker for SSE 4.1 instructions on the forms:
97	* pxxx xmm1, xmm2/mem128, imm8
98	*
99	* Proper alignment of the 128-bit operand is enforced.
100	* Exceptions type 4. SSE 4.1 cpuid checks.
101	*
102	* @sa iemOpCommonSsse3_FullFullImm8_To_Full
103	*/
104	FNIEMOP_DEF_1(iemOpCommonSse41_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
105	{
106	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
107	if (IEM_IS_MODRM_REG_MODE(bRm))
108	{
109	/*
110	* Register, register.
111	*/
112	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
113	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
114	IEM_MC_BEGIN(3, 0);
115	IEM_MC_ARG(PRTUINT128U, puDst, 0);
116	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
117	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
118	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
119	IEM_MC_PREPARE_SSE_USAGE();
120	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
121	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
122	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
123	IEM_MC_ADVANCE_RIP_AND_FINISH();
124	IEM_MC_END();
125	}
126	else
127	{
128	/*
129	* Register, memory.
130	*/
131	IEM_MC_BEGIN(3, 2);
132	IEM_MC_ARG(PRTUINT128U, puDst, 0);
133	IEM_MC_LOCAL(RTUINT128U, uSrc);
134	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
135	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
136
137	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
138	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
139	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
140	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
141	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
142	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
143
144	IEM_MC_PREPARE_SSE_USAGE();
145	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
146	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
147
148	IEM_MC_ADVANCE_RIP_AND_FINISH();
149	IEM_MC_END();
150	}
151	}
152
153
154	/**
155	* Common worker for SSE-style AES-NI instructions of the form:
156	* aesxxx xmm1, xmm2/mem128, imm8
157	*
158	* Proper alignment of the 128-bit operand is enforced.
159	* Exceptions type 4. AES-NI cpuid checks.
160	*
161	* @sa iemOpCommonSsse3_FullFullImm8_To_Full
162	* @sa iemOpCommonSse41_FullFullImm8_To_Full
163	*/
164	FNIEMOP_DEF_1(iemOpCommonAesNi_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
165	{
166	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
167	if (IEM_IS_MODRM_REG_MODE(bRm))
168	{
169	/*
170	* Register, register.
171	*/
172	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
173	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
174	IEM_MC_BEGIN(3, 0);
175	IEM_MC_ARG(PRTUINT128U, puDst, 0);
176	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
177	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
178	IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT();
179	IEM_MC_PREPARE_SSE_USAGE();
180	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
181	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
182	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
183	IEM_MC_ADVANCE_RIP_AND_FINISH();
184	IEM_MC_END();
185	}
186	else
187	{
188	/*
189	* Register, memory.
190	*/
191	IEM_MC_BEGIN(3, 2);
192	IEM_MC_ARG(PRTUINT128U, puDst, 0);
193	IEM_MC_LOCAL(RTUINT128U, uSrc);
194	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
195	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
196
197	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
198	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
199	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
200	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
201	IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT();
202	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
203
204	IEM_MC_PREPARE_SSE_USAGE();
205	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
206	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
207
208	IEM_MC_ADVANCE_RIP_AND_FINISH();
209	IEM_MC_END();
210	}
211	}
212
213
214	/** Opcode 0x66 0x0f 0x00 - invalid (vex only). */
215	/** Opcode 0x66 0x0f 0x01 - invalid (vex only). */
216	/** Opcode 0x66 0x0f 0x02 - invalid (vex only). */
217	/* Opcode 0x66 0x0f 0x03 - invalid */
218	/** Opcode 0x66 0x0f 0x04 - invalid (vex only). */
219	/** Opcode 0x66 0x0f 0x05 - invalid (vex only). */
220	/* Opcode 0x66 0x0f 0x06 - invalid (vex only) */
221	/* Opcode 0x66 0x0f 0x07 - invalid */
222	/** Opcode 0x66 0x0f 0x08. */
223	FNIEMOP_STUB(iemOp_roundps_Vx_Wx_Ib);
224	/** Opcode 0x66 0x0f 0x09. */
225	FNIEMOP_STUB(iemOp_roundpd_Vx_Wx_Ib);
226	/** Opcode 0x66 0x0f 0x0a. */
227	FNIEMOP_STUB(iemOp_roundss_Vss_Wss_Ib);
228	/** Opcode 0x66 0x0f 0x0b. */
229	FNIEMOP_STUB(iemOp_roundsd_Vsd_Wsd_Ib);
230
231
232	/** Opcode 0x66 0x0f 0x0c. */
233	FNIEMOP_DEF(iemOp_blendps_Vx_Wx_Ib)
234	{
235	IEMOP_MNEMONIC3(RMI, BLENDPS, blendps, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
236	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
237	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback));
238	}
239
240
241	/** Opcode 0x66 0x0f 0x0d. */
242	FNIEMOP_DEF(iemOp_blendpd_Vx_Wx_Ib)
243	{
244	IEMOP_MNEMONIC3(RMI, BLENDPD, blendpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
245	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
246	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback));
247	}
248
249
250	/** Opcode 0x66 0x0f 0x0e. */
251	FNIEMOP_DEF(iemOp_pblendw_Vx_Wx_Ib)
252	{
253	IEMOP_MNEMONIC3(RMI, PBLENDW, pblendw, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
254	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
255	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback));
256	}
257
258
259	/** Opcode 0x0f 0x0f. */
260	FNIEMOP_DEF(iemOp_palignr_Pq_Qq_Ib)
261	{
262	IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Pq, Qq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
263	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
264	if (IEM_IS_MODRM_REG_MODE(bRm))
265	{
266	/*
267	* Register, register.
268	*/
269	/** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
270	/** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
271	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
272	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
273	IEM_MC_BEGIN(3, 0);
274	IEM_MC_ARG(uint64_t *, pDst, 0);
275	IEM_MC_ARG(uint64_t, uSrc, 1);
276	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
277	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
278	IEM_MC_PREPARE_FPU_USAGE();
279	IEM_MC_FPU_TO_MMX_MODE();
280	IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
281	IEM_MC_FETCH_MREG_U64(uSrc, IEM_GET_MODRM_RM_8(bRm));
282	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
283	pDst, uSrc, bImmArg);
284	IEM_MC_MODIFIED_MREG_BY_REF(pDst);
285	IEM_MC_ADVANCE_RIP_AND_FINISH();
286	IEM_MC_END();
287	}
288	else
289	{
290	/*
291	* Register, memory.
292	*/
293	IEM_MC_BEGIN(3, 1);
294	IEM_MC_ARG(uint64_t *, pDst, 0);
295	IEM_MC_ARG(uint64_t, uSrc, 1);
296	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
297
298	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
299	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
300	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
301	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
302	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
303	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
304
305	IEM_MC_PREPARE_FPU_USAGE();
306	IEM_MC_FPU_TO_MMX_MODE();
307	IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
308	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
309	pDst, uSrc, bImmArg);
310	IEM_MC_MODIFIED_MREG_BY_REF(pDst);
311
312	IEM_MC_ADVANCE_RIP_AND_FINISH();
313	IEM_MC_END();
314	}
315	}
316
317
318	/** Opcode 0x66 0x0f 0x0f. */
319	FNIEMOP_DEF(iemOp_palignr_Vx_Wx_Ib)
320	{
321	IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
322	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFullImm8_To_Full,
323	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback));
324	}
325
326
327	/* Opcode 0x66 0x0f 0x10 - invalid */
328	/* Opcode 0x66 0x0f 0x11 - invalid */
329	/* Opcode 0x66 0x0f 0x12 - invalid */
330	/* Opcode 0x66 0x0f 0x13 - invalid */
331	/** Opcode 0x66 0x0f 0x14. */
332	FNIEMOP_STUB(iemOp_pextrb_RdMb_Vdq_Ib);
333	/** Opcode 0x66 0x0f 0x15. */
334	FNIEMOP_STUB(iemOp_pextrw_RdMw_Vdq_Ib);
335
336
337	FNIEMOP_DEF(iemOp_pextrd_q_RdMw_Vdq_Ib)
338	{
339	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
340	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
341	{
342	/**
343	* @opcode 0x16
344	* @opcodesub rex.w=1
345	* @oppfx 0x66
346	* @opcpuid sse
347	*/
348	IEMOP_MNEMONIC3(RMI, PEXTRQ, pextrq, Ev, Vq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
349	if (IEM_IS_MODRM_REG_MODE(bRm))
350	{
351	/*
352	* XMM, greg64.
353	*/
354	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
355	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
356	IEM_MC_BEGIN(0, 1);
357	IEM_MC_LOCAL(uint64_t, uSrc);
358	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
359	IEM_MC_PREPARE_SSE_USAGE();
360	IEM_MC_AND_LOCAL_U8(bImm, 1);
361	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/);
362	IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
363	IEM_MC_ADVANCE_RIP_AND_FINISH();
364	IEM_MC_END();
365	}
366	else
367	{
368	/*
369	* XMM, [mem64].
370	*/
371	IEM_MC_BEGIN(0, 2);
372	IEM_MC_LOCAL(uint64_t, uSrc);
373	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
374
375	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
376	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
377	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
378	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
379	IEM_MC_PREPARE_SSE_USAGE();
380
381	IEM_MC_AND_LOCAL_U8(bImm, 1);
382	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/);
383	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
384	IEM_MC_ADVANCE_RIP_AND_FINISH();
385	IEM_MC_END();
386	}
387	}
388	else
389	{
390	/**
391	* @opdone
392	* @opcode 0x16
393	* @opcodesub rex.w=0
394	* @oppfx 0x66
395	* @opcpuid sse
396	*/
397	IEMOP_MNEMONIC3(RMI, PEXTRD, pextrd, Ey, Vd, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
398	if (IEM_IS_MODRM_REG_MODE(bRm))
399	{
400	/*
401	* XMM, greg32.
402	*/
403	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
404	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
405	IEM_MC_BEGIN(0, 1);
406	IEM_MC_LOCAL(uint32_t, uSrc);
407	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
408	IEM_MC_PREPARE_SSE_USAGE();
409	IEM_MC_AND_LOCAL_U8(bImm, 3);
410	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/);
411	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
412	IEM_MC_ADVANCE_RIP_AND_FINISH();
413	IEM_MC_END();
414	}
415	else
416	{
417	/*
418	* XMM, [mem32].
419	*/
420	IEM_MC_BEGIN(0, 2);
421	IEM_MC_LOCAL(uint32_t, uSrc);
422	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
423
424	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
425	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
426	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
427	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
428	IEM_MC_PREPARE_SSE_USAGE();
429	IEM_MC_AND_LOCAL_U8(bImm, 3);
430	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/);
431	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
432	IEM_MC_ADVANCE_RIP_AND_FINISH();
433	IEM_MC_END();
434	}
435	}
436	}
437
438
439	/** Opcode 0x66 0x0f 0x17. */
440	FNIEMOP_STUB(iemOp_extractps_Ed_Vdq_Ib);
441	/* Opcode 0x66 0x0f 0x18 - invalid (vex only). */
442	/* Opcode 0x66 0x0f 0x19 - invalid (vex only). */
443	/* Opcode 0x66 0x0f 0x1a - invalid */
444	/* Opcode 0x66 0x0f 0x1b - invalid */
445	/* Opcode 0x66 0x0f 0x1c - invalid */
446	/* Opcode 0x66 0x0f 0x1d - invalid (vex only). */
447	/* Opcode 0x66 0x0f 0x1e - invalid */
448	/* Opcode 0x66 0x0f 0x1f - invalid */
449
450
451	/** Opcode 0x66 0x0f 0x20. */
452	FNIEMOP_STUB(iemOp_pinsrb_Vdq_RyMb_Ib);
453	/** Opcode 0x66 0x0f 0x21, */
454	FNIEMOP_STUB(iemOp_insertps_Vdq_UdqMd_Ib);
455
456
457	FNIEMOP_DEF(iemOp_pinsrd_q_Vdq_Ey_Ib)
458	{
459	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
460	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
461	{
462	/**
463	* @opcode 0x22
464	* @opcodesub rex.w=1
465	* @oppfx 0x66
466	* @opcpuid sse
467	*/
468	IEMOP_MNEMONIC3(RMI, PINSRQ, pinsrq, Vq, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
469	if (IEM_IS_MODRM_REG_MODE(bRm))
470	{
471	/*
472	* XMM, greg64.
473	*/
474	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
475	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
476	IEM_MC_BEGIN(0, 1);
477	IEM_MC_LOCAL(uint64_t, uSrc);
478	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
479	IEM_MC_PREPARE_SSE_USAGE();
480	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
481	IEM_MC_AND_LOCAL_U8(bImm, 1);
482	IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/, uSrc);
483	IEM_MC_ADVANCE_RIP_AND_FINISH();
484	IEM_MC_END();
485	}
486	else
487	{
488	/*
489	* XMM, [mem64].
490	*/
491	IEM_MC_BEGIN(0, 2);
492	IEM_MC_LOCAL(uint64_t, uSrc);
493	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
494
495	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
496	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
497	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
498	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
499	IEM_MC_PREPARE_SSE_USAGE();
500
501	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
502	IEM_MC_AND_LOCAL_U8(bImm, 1);
503	IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/, uSrc);
504	IEM_MC_ADVANCE_RIP_AND_FINISH();
505	IEM_MC_END();
506	}
507	}
508	else
509	{
510	/**
511	* @opdone
512	* @opcode 0x22
513	* @opcodesub rex.w=0
514	* @oppfx 0x66
515	* @opcpuid sse
516	*/
517	IEMOP_MNEMONIC3(RMI, PINSRD, pinsrd, Vd, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
518	if (IEM_IS_MODRM_REG_MODE(bRm))
519	{
520	/*
521	* XMM, greg32.
522	*/
523	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
524	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
525	IEM_MC_BEGIN(0, 1);
526	IEM_MC_LOCAL(uint32_t, uSrc);
527	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
528	IEM_MC_PREPARE_SSE_USAGE();
529	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
530	IEM_MC_AND_LOCAL_U8(bImm, 3);
531	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/, uSrc);
532	IEM_MC_ADVANCE_RIP_AND_FINISH();
533	IEM_MC_END();
534	}
535	else
536	{
537	/*
538	* XMM, [mem32].
539	*/
540	IEM_MC_BEGIN(0, 2);
541	IEM_MC_LOCAL(uint32_t, uSrc);
542	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
543
544	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
545	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
546	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
547	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
548	IEM_MC_PREPARE_SSE_USAGE();
549
550	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
551	IEM_MC_AND_LOCAL_U8(bImm, 3);
552	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/, uSrc);
553	IEM_MC_ADVANCE_RIP_AND_FINISH();
554	IEM_MC_END();
555	}
556	}
557	}
558
559
560	/* Opcode 0x66 0x0f 0x23 - invalid */
561	/* Opcode 0x66 0x0f 0x24 - invalid */
562	/* Opcode 0x66 0x0f 0x25 - invalid */
563	/* Opcode 0x66 0x0f 0x26 - invalid */
564	/* Opcode 0x66 0x0f 0x27 - invalid */
565	/* Opcode 0x66 0x0f 0x28 - invalid */
566	/* Opcode 0x66 0x0f 0x29 - invalid */
567	/* Opcode 0x66 0x0f 0x2a - invalid */
568	/* Opcode 0x66 0x0f 0x2b - invalid */
569	/* Opcode 0x66 0x0f 0x2c - invalid */
570	/* Opcode 0x66 0x0f 0x2d - invalid */
571	/* Opcode 0x66 0x0f 0x2e - invalid */
572	/* Opcode 0x66 0x0f 0x2f - invalid */
573
574
575	/* Opcode 0x66 0x0f 0x30 - invalid */
576	/* Opcode 0x66 0x0f 0x31 - invalid */
577	/* Opcode 0x66 0x0f 0x32 - invalid */
578	/* Opcode 0x66 0x0f 0x33 - invalid */
579	/* Opcode 0x66 0x0f 0x34 - invalid */
580	/* Opcode 0x66 0x0f 0x35 - invalid */
581	/* Opcode 0x66 0x0f 0x36 - invalid */
582	/* Opcode 0x66 0x0f 0x37 - invalid */
583	/* Opcode 0x66 0x0f 0x38 - invalid (vex only). */
584	/* Opcode 0x66 0x0f 0x39 - invalid (vex only). */
585	/* Opcode 0x66 0x0f 0x3a - invalid */
586	/* Opcode 0x66 0x0f 0x3b - invalid */
587	/* Opcode 0x66 0x0f 0x3c - invalid */
588	/* Opcode 0x66 0x0f 0x3d - invalid */
589	/* Opcode 0x66 0x0f 0x3e - invalid */
590	/* Opcode 0x66 0x0f 0x3f - invalid */
591
592
593	/** Opcode 0x66 0x0f 0x40. */
594	FNIEMOP_STUB(iemOp_dpps_Vx_Wx_Ib);
595	/** Opcode 0x66 0x0f 0x41, */
596	FNIEMOP_STUB(iemOp_dppd_Vdq_Wdq_Ib);
597	/** Opcode 0x66 0x0f 0x42. */
598	FNIEMOP_STUB(iemOp_mpsadbw_Vx_Wx_Ib);
599	/* Opcode 0x66 0x0f 0x43 - invalid */
600
601
602	/** Opcode 0x66 0x0f 0x44. */
603	FNIEMOP_DEF(iemOp_pclmulqdq_Vdq_Wdq_Ib)
604	{
605	IEMOP_MNEMONIC3(RMI, PCLMULQDQ, pclmulqdq, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
606
607	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
608	if (IEM_IS_MODRM_REG_MODE(bRm))
609	{
610	/*
611	* Register, register.
612	*/
613	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
614	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
615	IEM_MC_BEGIN(3, 0);
616	IEM_MC_ARG(PRTUINT128U, puDst, 0);
617	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
618	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
619	IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT();
620	IEM_MC_PREPARE_SSE_USAGE();
621	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
622	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
623	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
624	iemAImpl_pclmulqdq_u128,
625	iemAImpl_pclmulqdq_u128_fallback),
626	puDst, puSrc, bImmArg);
627	IEM_MC_ADVANCE_RIP_AND_FINISH();
628	IEM_MC_END();
629	}
630	else
631	{
632	/*
633	* Register, memory.
634	*/
635	IEM_MC_BEGIN(3, 2);
636	IEM_MC_ARG(PRTUINT128U, puDst, 0);
637	IEM_MC_LOCAL(RTUINT128U, uSrc);
638	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
639	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
640
641	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
642	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
643	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
644	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
645	IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT();
646	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
647
648	IEM_MC_PREPARE_SSE_USAGE();
649	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
650	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
651	iemAImpl_pclmulqdq_u128,
652	iemAImpl_pclmulqdq_u128_fallback),
653	puDst, puSrc, bImmArg);
654
655	IEM_MC_ADVANCE_RIP_AND_FINISH();
656	IEM_MC_END();
657	}
658	}
659
660
661	/* Opcode 0x66 0x0f 0x45 - invalid */
662	/* Opcode 0x66 0x0f 0x46 - invalid (vex only) */
663	/* Opcode 0x66 0x0f 0x47 - invalid */
664	/* Opcode 0x66 0x0f 0x48 - invalid */
665	/* Opcode 0x66 0x0f 0x49 - invalid */
666	/* Opcode 0x66 0x0f 0x4a - invalid (vex only). */
667	/* Opcode 0x66 0x0f 0x4b - invalid (vex only). */
668	/* Opcode 0x66 0x0f 0x4c - invalid (vex only). */
669	/* Opcode 0x66 0x0f 0x4d - invalid */
670	/* Opcode 0x66 0x0f 0x4e - invalid */
671	/* Opcode 0x66 0x0f 0x4f - invalid */
672
673
674	/* Opcode 0x66 0x0f 0x50 - invalid */
675	/* Opcode 0x66 0x0f 0x51 - invalid */
676	/* Opcode 0x66 0x0f 0x52 - invalid */
677	/* Opcode 0x66 0x0f 0x53 - invalid */
678	/* Opcode 0x66 0x0f 0x54 - invalid */
679	/* Opcode 0x66 0x0f 0x55 - invalid */
680	/* Opcode 0x66 0x0f 0x56 - invalid */
681	/* Opcode 0x66 0x0f 0x57 - invalid */
682	/* Opcode 0x66 0x0f 0x58 - invalid */
683	/* Opcode 0x66 0x0f 0x59 - invalid */
684	/* Opcode 0x66 0x0f 0x5a - invalid */
685	/* Opcode 0x66 0x0f 0x5b - invalid */
686	/* Opcode 0x66 0x0f 0x5c - invalid */
687	/* Opcode 0x66 0x0f 0x5d - invalid */
688	/* Opcode 0x66 0x0f 0x5e - invalid */
689	/* Opcode 0x66 0x0f 0x5f - invalid */
690
691
692	/** Opcode 0x66 0x0f 0x60. */
693	FNIEMOP_STUB(iemOp_pcmpestrm_Vdq_Wdq_Ib);
694	/** Opcode 0x66 0x0f 0x61, */
695	FNIEMOP_STUB(iemOp_pcmpestri_Vdq_Wdq_Ib);
696	/** Opcode 0x66 0x0f 0x62. */
697	FNIEMOP_STUB(iemOp_pcmpistrm_Vdq_Wdq_Ib);
698
699
700	/** Opcode 0x66 0x0f 0x63*/
701	FNIEMOP_DEF(iemOp_pcmpistri_Vdq_Wdq_Ib)
702	{
703	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
704	if (IEM_IS_MODRM_REG_MODE(bRm))
705	{
706	/*
707	* Register, register.
708	*/
709	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
710	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
711	IEM_MC_BEGIN(4, 1);
712	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
713	IEM_MC_ARG(uint32_t *, pEFlags, 1);
714	IEM_MC_LOCAL(IEMPCMPISTRISRC, Src);
715	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRISRC, pSrc, Src, 2);
716	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
717	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
718	IEM_MC_PREPARE_SSE_USAGE();
719	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
720	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
721	IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
722	IEM_MC_REF_EFLAGS(pEFlags);
723	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
724	iemAImpl_pcmpistri_u128,
725	iemAImpl_pcmpistri_u128_fallback),
726	pu32Ecx, pEFlags, pSrc, bImmArg);
727	/** @todo testcase: High dword of RCX cleared? */
728	IEM_MC_ADVANCE_RIP_AND_FINISH();
729	IEM_MC_END();
730	}
731	else
732	{
733	/*
734	* Register, memory.
735	*/
736	IEM_MC_BEGIN(4, 3);
737	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
738	IEM_MC_ARG(uint32_t *, pEFlags, 1);
739	IEM_MC_LOCAL(IEMPCMPISTRISRC, Src);
740	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRISRC, pSrc, Src, 2);
741	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
742
743	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
744	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
745	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
746	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
747	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
748	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
749
750	IEM_MC_PREPARE_SSE_USAGE();
751	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
752	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
753	IEM_MC_REF_EFLAGS(pEFlags);
754	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
755	iemAImpl_pcmpistri_u128,
756	iemAImpl_pcmpistri_u128_fallback),
757	pu32Ecx, pEFlags, pSrc, bImmArg);
758	/** @todo testcase: High dword of RCX cleared? */
759	IEM_MC_ADVANCE_RIP_AND_FINISH();
760	IEM_MC_END();
761	}
762	}
763
764
765	/* Opcode 0x66 0x0f 0x64 - invalid */
766	/* Opcode 0x66 0x0f 0x65 - invalid */
767	/* Opcode 0x66 0x0f 0x66 - invalid */
768	/* Opcode 0x66 0x0f 0x67 - invalid */
769	/* Opcode 0x66 0x0f 0x68 - invalid */
770	/* Opcode 0x66 0x0f 0x69 - invalid */
771	/* Opcode 0x66 0x0f 0x6a - invalid */
772	/* Opcode 0x66 0x0f 0x6b - invalid */
773	/* Opcode 0x66 0x0f 0x6c - invalid */
774	/* Opcode 0x66 0x0f 0x6d - invalid */
775	/* Opcode 0x66 0x0f 0x6e - invalid */
776	/* Opcode 0x66 0x0f 0x6f - invalid */
777
778	/* Opcodes 0x0f 0x70 thru 0x0f 0xb0 are unused. */
779
780
781	/* Opcode 0x0f 0xc0 - invalid */
782	/* Opcode 0x0f 0xc1 - invalid */
783	/* Opcode 0x0f 0xc2 - invalid */
784	/* Opcode 0x0f 0xc3 - invalid */
785	/* Opcode 0x0f 0xc4 - invalid */
786	/* Opcode 0x0f 0xc5 - invalid */
787	/* Opcode 0x0f 0xc6 - invalid */
788	/* Opcode 0x0f 0xc7 - invalid */
789	/* Opcode 0x0f 0xc8 - invalid */
790	/* Opcode 0x0f 0xc9 - invalid */
791	/* Opcode 0x0f 0xca - invalid */
792	/* Opcode 0x0f 0xcb - invalid */
793	/* Opcode 0x0f 0xcc */
794	FNIEMOP_STUB(iemOp_sha1rnds4_Vdq_Wdq_Ib);
795	/* Opcode 0x0f 0xcd - invalid */
796	/* Opcode 0x0f 0xce - invalid */
797	/* Opcode 0x0f 0xcf - invalid */
798
799
800	/* Opcode 0x66 0x0f 0xd0 - invalid */
801	/* Opcode 0x66 0x0f 0xd1 - invalid */
802	/* Opcode 0x66 0x0f 0xd2 - invalid */
803	/* Opcode 0x66 0x0f 0xd3 - invalid */
804	/* Opcode 0x66 0x0f 0xd4 - invalid */
805	/* Opcode 0x66 0x0f 0xd5 - invalid */
806	/* Opcode 0x66 0x0f 0xd6 - invalid */
807	/* Opcode 0x66 0x0f 0xd7 - invalid */
808	/* Opcode 0x66 0x0f 0xd8 - invalid */
809	/* Opcode 0x66 0x0f 0xd9 - invalid */
810	/* Opcode 0x66 0x0f 0xda - invalid */
811	/* Opcode 0x66 0x0f 0xdb - invalid */
812	/* Opcode 0x66 0x0f 0xdc - invalid */
813	/* Opcode 0x66 0x0f 0xdd - invalid */
814	/* Opcode 0x66 0x0f 0xde - invalid */
815
816
817	/* Opcode 0x66 0x0f 0xdf - (aeskeygenassist). */
818	FNIEMOP_DEF(iemOp_aeskeygen_Vdq_Wdq_Ib)
819	{
820	IEMOP_MNEMONIC3(RMI, AESKEYGEN, aeskeygen, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
821	return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFullImm8_To_Full,
822	IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback));
823	}
824
825
826	/* Opcode 0xf2 0x0f 0xf0 - invalid (vex only) */
827
828
829	/**
830	* Three byte opcode map, first two bytes are 0x0f 0x3a.
831	* @sa g_apfnVexMap2
832	*/
833	IEM_STATIC const PFNIEMOP g_apfnThreeByte0f3a[] =
834	{
835	/* no prefix, 066h prefix f3h prefix, f2h prefix */
836	/* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
837	/* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
838	/* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
839	/* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
840	/* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
841	/* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
842	/* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
843	/* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
844	/* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_roundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
845	/* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_roundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
846	/* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_roundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
847	/* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_roundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
848	/* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_blendps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
849	/* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_blendpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
850	/* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_pblendw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
851	/* 0x0f */ iemOp_palignr_Pq_Qq_Ib, iemOp_palignr_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
852
853	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
854	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
855	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
856	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
857	/* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_pextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
858	/* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_pextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
859	/* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_pextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
860	/* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_extractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
861	/* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
862	/* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
863	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
864	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
865	/* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
866	/* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
867	/* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
868	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
869
870	/* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrb_Vdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
871	/* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_insertps_Vdq_UdqMd_Ib,iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
872	/* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrd_q_Vdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
873	/* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
874	/* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
875	/* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
876	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
877	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
878	/* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
879	/* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
880	/* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
881	/* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
882	/* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
883	/* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
884	/* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
885	/* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
886
887	/* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
888	/* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
889	/* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
890	/* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
891	/* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
892	/* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
893	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
894	/* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
895	/* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
896	/* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
897	/* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
898	/* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
899	/* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
900	/* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
901	/* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
902	/* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
903
904	/* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_dpps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
905	/* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_dppd_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
906	/* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_mpsadbw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
907	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
908	/* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_pclmulqdq_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
909	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
910	/* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
911	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
912	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
913	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
914	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
915	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
916	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
917	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
918	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
919	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
920
921	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
922	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
923	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
924	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
925	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
926	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
927	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
928	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
929	/* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
930	/* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
931	/* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
932	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
933	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
934	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
935	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
936	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
937
938	/* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
939	/* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
940	/* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
941	/* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
942	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
943	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
944	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
945	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
946	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
947	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
948	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
949	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
950	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
951	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
952	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
953	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
954
955	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
956	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
957	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
958	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
959	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
960	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
961	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
962	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
963	/* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
964	/* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
965	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
966	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
967	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
968	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
969	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
970	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
971
972	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
973	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
974	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
975	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
976	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
977	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
978	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
979	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
980	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
981	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
982	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
983	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
984	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
985	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
986	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
987	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
988
989	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
990	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
991	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
992	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
993	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
994	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
995	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
996	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
997	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
998	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
999	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1000	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1001	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1002	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1003	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1004	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1005
1006	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1007	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1008	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1009	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1010	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1011	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1012	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1013	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1014	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1015	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1016	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1017	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1018	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1019	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1020	/* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1021	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1022
1023	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1024	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1025	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1026	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1027	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1028	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1029	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1030	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1031	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1032	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1033	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1034	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1035	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1036	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1037	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1038	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1039
1040	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1041	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1042	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1043	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1044	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1045	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1046	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1047	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1048	/* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1049	/* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1050	/* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1051	/* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1052	/* 0xcc */ iemOp_sha1rnds4_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1053	/* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1054	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1055	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1056
1057	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1058	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1059	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1060	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1061	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1062	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1063	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1064	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1065	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1066	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1067	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1068	/* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1069	/* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1070	/* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1071	/* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1072	/* 0xdf */ iemOp_InvalidNeedRMImm8, iemOp_aeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1073
1074	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1075	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1076	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1077	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1078	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1079	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1080	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1081	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1082	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1083	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1084	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1085	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1086	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1087	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1088	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1089	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1090
1091	/* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1092	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1093	/* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1094	/* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1095	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1096	/* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1097	/* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1098	/* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1099	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1100	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1101	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1102	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1103	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1104	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1105	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1106	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1107	};
1108	AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f3a) == 1024);
1109
1110	/** @} */
1111

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h@ 97543

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