IEMAllInstructionsThree0f3a.cpp.h@ 97676

Last change on this file since 97676 was 97676, checked in by vboxsync, 2 years ago
IEM: PCMPISTRI does not enforce 128-bit alignment of memory operands.
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1	/* $Id: IEMAllInstructionsThree0f3a.cpp.h 97676 2022-11-24 15:09:47Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4	*
5	* @remarks IEMAllInstructionsVexMap3.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle and/or its affiliates.
11	*
12	* This file is part of VirtualBox base platform packages, as
13	* available from https://www.virtualbox.org.
14	*
15	* This program is free software; you can redistribute it and/or
16	* modify it under the terms of the GNU General Public License
17	* as published by the Free Software Foundation, in version 3 of the
18	* License.
19	*
20	* This program is distributed in the hope that it will be useful, but
21	* WITHOUT ANY WARRANTY; without even the implied warranty of
22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23	* General Public License for more details.
24	*
25	* You should have received a copy of the GNU General Public License
26	* along with this program; if not, see <https://www.gnu.org/licenses>.
27	*
28	* SPDX-License-Identifier: GPL-3.0-only
29	*/
30
31
32	/** @name Three byte opcodes with first two bytes 0x0f 0x3a
33	* @{
34	*/
35
36	/**
37	* Common worker for SSSE3 instructions on the forms:
38	* pxxx xmm1, xmm2/mem128, imm8
39	*
40	* Proper alignment of the 128-bit operand is enforced.
41	* Exceptions type 4. SSSE3 cpuid checks.
42	*
43	* @sa iemOpCommonSse41_FullFullImm8_To_Full
44	*/
45	FNIEMOP_DEF_1(iemOpCommonSsse3_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
46	{
47	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48	if (IEM_IS_MODRM_REG_MODE(bRm))
49	{
50	/*
51	* Register, register.
52	*/
53	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
54	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
55	IEM_MC_BEGIN(3, 0);
56	IEM_MC_ARG(PRTUINT128U, puDst, 0);
57	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
58	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
59	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
60	IEM_MC_PREPARE_SSE_USAGE();
61	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
62	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
63	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
64	IEM_MC_ADVANCE_RIP_AND_FINISH();
65	IEM_MC_END();
66	}
67	else
68	{
69	/*
70	* Register, memory.
71	*/
72	IEM_MC_BEGIN(3, 2);
73	IEM_MC_ARG(PRTUINT128U, puDst, 0);
74	IEM_MC_LOCAL(RTUINT128U, uSrc);
75	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
76	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
77
78	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
79	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
80	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
81	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
82	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
83	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
84
85	IEM_MC_PREPARE_SSE_USAGE();
86	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
87	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
88
89	IEM_MC_ADVANCE_RIP_AND_FINISH();
90	IEM_MC_END();
91	}
92	}
93
94
95	/**
96	* Common worker for SSE 4.1 instructions on the forms:
97	* pxxx xmm1, xmm2/mem128, imm8
98	*
99	* Proper alignment of the 128-bit operand is enforced.
100	* Exceptions type 4. SSE 4.1 cpuid checks.
101	*
102	* @sa iemOpCommonSsse3_FullFullImm8_To_Full
103	*/
104	FNIEMOP_DEF_1(iemOpCommonSse41_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
105	{
106	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
107	if (IEM_IS_MODRM_REG_MODE(bRm))
108	{
109	/*
110	* Register, register.
111	*/
112	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
113	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
114	IEM_MC_BEGIN(3, 0);
115	IEM_MC_ARG(PRTUINT128U, puDst, 0);
116	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
117	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
118	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
119	IEM_MC_PREPARE_SSE_USAGE();
120	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
121	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
122	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
123	IEM_MC_ADVANCE_RIP_AND_FINISH();
124	IEM_MC_END();
125	}
126	else
127	{
128	/*
129	* Register, memory.
130	*/
131	IEM_MC_BEGIN(3, 2);
132	IEM_MC_ARG(PRTUINT128U, puDst, 0);
133	IEM_MC_LOCAL(RTUINT128U, uSrc);
134	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
135	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
136
137	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
138	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
139	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
140	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
141	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
142	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
143
144	IEM_MC_PREPARE_SSE_USAGE();
145	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
146	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
147
148	IEM_MC_ADVANCE_RIP_AND_FINISH();
149	IEM_MC_END();
150	}
151	}
152
153
154	/**
155	* Common worker for SSE-style AES-NI instructions of the form:
156	* aesxxx xmm1, xmm2/mem128, imm8
157	*
158	* Proper alignment of the 128-bit operand is enforced.
159	* Exceptions type 4. AES-NI cpuid checks.
160	*
161	* @sa iemOpCommonSsse3_FullFullImm8_To_Full
162	* @sa iemOpCommonSse41_FullFullImm8_To_Full
163	*/
164	FNIEMOP_DEF_1(iemOpCommonAesNi_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
165	{
166	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
167	if (IEM_IS_MODRM_REG_MODE(bRm))
168	{
169	/*
170	* Register, register.
171	*/
172	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
173	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
174	IEM_MC_BEGIN(3, 0);
175	IEM_MC_ARG(PRTUINT128U, puDst, 0);
176	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
177	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
178	IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT();
179	IEM_MC_PREPARE_SSE_USAGE();
180	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
181	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
182	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
183	IEM_MC_ADVANCE_RIP_AND_FINISH();
184	IEM_MC_END();
185	}
186	else
187	{
188	/*
189	* Register, memory.
190	*/
191	IEM_MC_BEGIN(3, 2);
192	IEM_MC_ARG(PRTUINT128U, puDst, 0);
193	IEM_MC_LOCAL(RTUINT128U, uSrc);
194	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
195	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
196
197	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
198	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
199	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
200	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
201	IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT();
202	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
203
204	IEM_MC_PREPARE_SSE_USAGE();
205	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
206	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
207
208	IEM_MC_ADVANCE_RIP_AND_FINISH();
209	IEM_MC_END();
210	}
211	}
212
213
214	/** Opcode 0x66 0x0f 0x00 - invalid (vex only). */
215	/** Opcode 0x66 0x0f 0x01 - invalid (vex only). */
216	/** Opcode 0x66 0x0f 0x02 - invalid (vex only). */
217	/* Opcode 0x66 0x0f 0x03 - invalid */
218	/** Opcode 0x66 0x0f 0x04 - invalid (vex only). */
219	/** Opcode 0x66 0x0f 0x05 - invalid (vex only). */
220	/* Opcode 0x66 0x0f 0x06 - invalid (vex only) */
221	/* Opcode 0x66 0x0f 0x07 - invalid */
222	/** Opcode 0x66 0x0f 0x08. */
223	FNIEMOP_STUB(iemOp_roundps_Vx_Wx_Ib);
224	/** Opcode 0x66 0x0f 0x09. */
225	FNIEMOP_STUB(iemOp_roundpd_Vx_Wx_Ib);
226	/** Opcode 0x66 0x0f 0x0a. */
227	FNIEMOP_STUB(iemOp_roundss_Vss_Wss_Ib);
228	/** Opcode 0x66 0x0f 0x0b. */
229	FNIEMOP_STUB(iemOp_roundsd_Vsd_Wsd_Ib);
230
231
232	/** Opcode 0x66 0x0f 0x0c. */
233	FNIEMOP_DEF(iemOp_blendps_Vx_Wx_Ib)
234	{
235	IEMOP_MNEMONIC3(RMI, BLENDPS, blendps, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
236	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
237	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback));
238	}
239
240
241	/** Opcode 0x66 0x0f 0x0d. */
242	FNIEMOP_DEF(iemOp_blendpd_Vx_Wx_Ib)
243	{
244	IEMOP_MNEMONIC3(RMI, BLENDPD, blendpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
245	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
246	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback));
247	}
248
249
250	/** Opcode 0x66 0x0f 0x0e. */
251	FNIEMOP_DEF(iemOp_pblendw_Vx_Wx_Ib)
252	{
253	IEMOP_MNEMONIC3(RMI, PBLENDW, pblendw, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
254	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
255	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback));
256	}
257
258
259	/** Opcode 0x0f 0x0f. */
260	FNIEMOP_DEF(iemOp_palignr_Pq_Qq_Ib)
261	{
262	IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Pq, Qq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
263	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
264	if (IEM_IS_MODRM_REG_MODE(bRm))
265	{
266	/*
267	* Register, register.
268	*/
269	/** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
270	/** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
271	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
272	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
273	IEM_MC_BEGIN(3, 0);
274	IEM_MC_ARG(uint64_t *, pDst, 0);
275	IEM_MC_ARG(uint64_t, uSrc, 1);
276	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
277	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
278	IEM_MC_PREPARE_FPU_USAGE();
279	IEM_MC_FPU_TO_MMX_MODE();
280	IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
281	IEM_MC_FETCH_MREG_U64(uSrc, IEM_GET_MODRM_RM_8(bRm));
282	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
283	pDst, uSrc, bImmArg);
284	IEM_MC_MODIFIED_MREG_BY_REF(pDst);
285	IEM_MC_ADVANCE_RIP_AND_FINISH();
286	IEM_MC_END();
287	}
288	else
289	{
290	/*
291	* Register, memory.
292	*/
293	IEM_MC_BEGIN(3, 1);
294	IEM_MC_ARG(uint64_t *, pDst, 0);
295	IEM_MC_ARG(uint64_t, uSrc, 1);
296	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
297
298	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
299	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
300	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
301	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
302	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
303	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
304
305	IEM_MC_PREPARE_FPU_USAGE();
306	IEM_MC_FPU_TO_MMX_MODE();
307	IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
308	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
309	pDst, uSrc, bImmArg);
310	IEM_MC_MODIFIED_MREG_BY_REF(pDst);
311
312	IEM_MC_ADVANCE_RIP_AND_FINISH();
313	IEM_MC_END();
314	}
315	}
316
317
318	/** Opcode 0x66 0x0f 0x0f. */
319	FNIEMOP_DEF(iemOp_palignr_Vx_Wx_Ib)
320	{
321	IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
322	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFullImm8_To_Full,
323	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback));
324	}
325
326
327	/* Opcode 0x66 0x0f 0x10 - invalid */
328	/* Opcode 0x66 0x0f 0x11 - invalid */
329	/* Opcode 0x66 0x0f 0x12 - invalid */
330	/* Opcode 0x66 0x0f 0x13 - invalid */
331
332
333	/** Opcode 0x66 0x0f 0x14. */
334	FNIEMOP_DEF(iemOp_pextrb_RdMb_Vdq_Ib)
335	{
336	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
337	IEMOP_MNEMONIC3(MRI, PEXTRB, pextrb, Ev, Vq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
338	if (IEM_IS_MODRM_REG_MODE(bRm))
339	{
340	/*
341	* greg32, XMM.
342	*/
343	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
344	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
345	IEM_MC_BEGIN(0, 1);
346	IEM_MC_LOCAL(uint8_t, uValue);
347	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
348	IEM_MC_PREPARE_SSE_USAGE();
349	IEM_MC_AND_LOCAL_U8(bImm, 15);
350	IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iByte/);
351	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
352	IEM_MC_ADVANCE_RIP_AND_FINISH();
353	IEM_MC_END();
354	}
355	else
356	{
357	/*
358	* [mem8], XMM.
359	*/
360	IEM_MC_BEGIN(0, 2);
361	IEM_MC_LOCAL(uint8_t, uValue);
362	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
363
364	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
365	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
366	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
367	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
368	IEM_MC_PREPARE_SSE_USAGE();
369
370	IEM_MC_AND_LOCAL_U8(bImm, 15);
371	IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iByte/);
372	IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
373	IEM_MC_ADVANCE_RIP_AND_FINISH();
374	IEM_MC_END();
375	}
376	}
377
378
379	/** Opcode 0x66 0x0f 0x15. */
380	FNIEMOP_DEF(iemOp_pextrw_RdMw_Vdq_Ib)
381	{
382	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
383	IEMOP_MNEMONIC3(MRI, PEXTRW, pextrw, Ev, Vq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
384	if (IEM_IS_MODRM_REG_MODE(bRm))
385	{
386	/*
387	* greg32, XMM.
388	*/
389	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
390	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
391	IEM_MC_BEGIN(0, 1);
392	IEM_MC_LOCAL(uint16_t, uValue);
393	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
394	IEM_MC_PREPARE_SSE_USAGE();
395	IEM_MC_AND_LOCAL_U8(bImm, 7);
396	IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iWord/);
397	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
398	IEM_MC_ADVANCE_RIP_AND_FINISH();
399	IEM_MC_END();
400	}
401	else
402	{
403	/*
404	* [mem16], XMM.
405	*/
406	IEM_MC_BEGIN(0, 2);
407	IEM_MC_LOCAL(uint16_t, uValue);
408	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
409
410	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
411	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
412	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
413	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
414	IEM_MC_PREPARE_SSE_USAGE();
415
416	IEM_MC_AND_LOCAL_U8(bImm, 7);
417	IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iWord/);
418	IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
419	IEM_MC_ADVANCE_RIP_AND_FINISH();
420	IEM_MC_END();
421	}
422	}
423
424
425	FNIEMOP_DEF(iemOp_pextrd_q_RdMw_Vdq_Ib)
426	{
427	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
428	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
429	{
430	/**
431	* @opcode 0x16
432	* @opcodesub rex.w=1
433	* @oppfx 0x66
434	* @opcpuid sse
435	*/
436	IEMOP_MNEMONIC3(MRI, PEXTRQ, pextrq, Ev, Vq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
437	if (IEM_IS_MODRM_REG_MODE(bRm))
438	{
439	/*
440	* greg64, XMM.
441	*/
442	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
443	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
444	IEM_MC_BEGIN(0, 1);
445	IEM_MC_LOCAL(uint64_t, uSrc);
446	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
447	IEM_MC_PREPARE_SSE_USAGE();
448	IEM_MC_AND_LOCAL_U8(bImm, 1);
449	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/);
450	IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
451	IEM_MC_ADVANCE_RIP_AND_FINISH();
452	IEM_MC_END();
453	}
454	else
455	{
456	/*
457	* [mem64], XMM.
458	*/
459	IEM_MC_BEGIN(0, 2);
460	IEM_MC_LOCAL(uint64_t, uSrc);
461	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
462
463	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
464	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
465	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
466	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
467	IEM_MC_PREPARE_SSE_USAGE();
468
469	IEM_MC_AND_LOCAL_U8(bImm, 1);
470	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/);
471	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
472	IEM_MC_ADVANCE_RIP_AND_FINISH();
473	IEM_MC_END();
474	}
475	}
476	else
477	{
478	/**
479	* @opdone
480	* @opcode 0x16
481	* @opcodesub rex.w=0
482	* @oppfx 0x66
483	* @opcpuid sse
484	*/
485	IEMOP_MNEMONIC3(MRI, PEXTRD, pextrd, Ey, Vd, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
486	if (IEM_IS_MODRM_REG_MODE(bRm))
487	{
488	/*
489	* greg32, XMM.
490	*/
491	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
492	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
493	IEM_MC_BEGIN(0, 1);
494	IEM_MC_LOCAL(uint32_t, uSrc);
495	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
496	IEM_MC_PREPARE_SSE_USAGE();
497	IEM_MC_AND_LOCAL_U8(bImm, 3);
498	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/);
499	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
500	IEM_MC_ADVANCE_RIP_AND_FINISH();
501	IEM_MC_END();
502	}
503	else
504	{
505	/*
506	* [mem32], XMM.
507	*/
508	IEM_MC_BEGIN(0, 2);
509	IEM_MC_LOCAL(uint32_t, uSrc);
510	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
511
512	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
513	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
514	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
515	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
516	IEM_MC_PREPARE_SSE_USAGE();
517	IEM_MC_AND_LOCAL_U8(bImm, 3);
518	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/);
519	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
520	IEM_MC_ADVANCE_RIP_AND_FINISH();
521	IEM_MC_END();
522	}
523	}
524	}
525
526
527	/** Opcode 0x66 0x0f 0x17. */
528	FNIEMOP_DEF(iemOp_extractps_Ed_Vdq_Ib)
529	{
530	IEMOP_MNEMONIC3(MRI, EXTRACTPS, extractps, Ed, Vdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
531	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
532	if (IEM_IS_MODRM_REG_MODE(bRm))
533	{
534	/*
535	* greg32, XMM.
536	*/
537	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
538	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
539	IEM_MC_BEGIN(0, 1);
540	IEM_MC_LOCAL(uint32_t, uSrc);
541	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
542	IEM_MC_PREPARE_SSE_USAGE();
543	IEM_MC_AND_LOCAL_U8(bImm, 3);
544	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/);
545	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
546	IEM_MC_ADVANCE_RIP_AND_FINISH();
547	IEM_MC_END();
548	}
549	else
550	{
551	/*
552	* [mem32], XMM.
553	*/
554	IEM_MC_BEGIN(0, 2);
555	IEM_MC_LOCAL(uint32_t, uSrc);
556	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
557
558	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
559	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
560	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
561	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
562	IEM_MC_PREPARE_SSE_USAGE();
563	IEM_MC_AND_LOCAL_U8(bImm, 3);
564	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/);
565	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
566	IEM_MC_ADVANCE_RIP_AND_FINISH();
567	IEM_MC_END();
568	}
569	}
570
571
572	/* Opcode 0x66 0x0f 0x18 - invalid (vex only). */
573	/* Opcode 0x66 0x0f 0x19 - invalid (vex only). */
574	/* Opcode 0x66 0x0f 0x1a - invalid */
575	/* Opcode 0x66 0x0f 0x1b - invalid */
576	/* Opcode 0x66 0x0f 0x1c - invalid */
577	/* Opcode 0x66 0x0f 0x1d - invalid (vex only). */
578	/* Opcode 0x66 0x0f 0x1e - invalid */
579	/* Opcode 0x66 0x0f 0x1f - invalid */
580
581
582	/** Opcode 0x66 0x0f 0x20. */
583	FNIEMOP_DEF(iemOp_pinsrb_Vdq_RyMb_Ib)
584	{
585	IEMOP_MNEMONIC3(RMI, PINSRB, pinsrb, Vd, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
586	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
587	if (IEM_IS_MODRM_REG_MODE(bRm))
588	{
589	/*
590	* XMM, greg32.
591	*/
592	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
593	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
594	IEM_MC_BEGIN(0, 1);
595	IEM_MC_LOCAL(uint8_t, uSrc);
596	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
597	IEM_MC_PREPARE_SSE_USAGE();
598	IEM_MC_FETCH_GREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
599	IEM_MC_AND_LOCAL_U8(bImm, 15);
600	IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iByte/, uSrc);
601	IEM_MC_ADVANCE_RIP_AND_FINISH();
602	IEM_MC_END();
603	}
604	else
605	{
606	/*
607	* XMM, [mem8].
608	*/
609	IEM_MC_BEGIN(0, 2);
610	IEM_MC_LOCAL(uint8_t, uSrc);
611	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
612
613	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
614	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
615	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
616	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
617	IEM_MC_PREPARE_SSE_USAGE();
618
619	IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
620	IEM_MC_AND_LOCAL_U8(bImm, 15);
621	IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iByte/, uSrc);
622	IEM_MC_ADVANCE_RIP_AND_FINISH();
623	IEM_MC_END();
624	}
625	}
626
627	/** Opcode 0x66 0x0f 0x21, */
628	FNIEMOP_STUB(iemOp_insertps_Vdq_UdqMd_Ib);
629
630
631	FNIEMOP_DEF(iemOp_pinsrd_q_Vdq_Ey_Ib)
632	{
633	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
634	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
635	{
636	/**
637	* @opcode 0x22
638	* @opcodesub rex.w=1
639	* @oppfx 0x66
640	* @opcpuid sse
641	*/
642	IEMOP_MNEMONIC3(RMI, PINSRQ, pinsrq, Vq, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
643	if (IEM_IS_MODRM_REG_MODE(bRm))
644	{
645	/*
646	* XMM, greg64.
647	*/
648	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
649	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
650	IEM_MC_BEGIN(0, 1);
651	IEM_MC_LOCAL(uint64_t, uSrc);
652	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
653	IEM_MC_PREPARE_SSE_USAGE();
654	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
655	IEM_MC_AND_LOCAL_U8(bImm, 1);
656	IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/, uSrc);
657	IEM_MC_ADVANCE_RIP_AND_FINISH();
658	IEM_MC_END();
659	}
660	else
661	{
662	/*
663	* XMM, [mem64].
664	*/
665	IEM_MC_BEGIN(0, 2);
666	IEM_MC_LOCAL(uint64_t, uSrc);
667	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
668
669	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
670	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
671	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
672	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
673	IEM_MC_PREPARE_SSE_USAGE();
674
675	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
676	IEM_MC_AND_LOCAL_U8(bImm, 1);
677	IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/, uSrc);
678	IEM_MC_ADVANCE_RIP_AND_FINISH();
679	IEM_MC_END();
680	}
681	}
682	else
683	{
684	/**
685	* @opdone
686	* @opcode 0x22
687	* @opcodesub rex.w=0
688	* @oppfx 0x66
689	* @opcpuid sse
690	*/
691	IEMOP_MNEMONIC3(RMI, PINSRD, pinsrd, Vd, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, IEMOPHINT_IGNORES_OZ_PFX);
692	if (IEM_IS_MODRM_REG_MODE(bRm))
693	{
694	/*
695	* XMM, greg32.
696	*/
697	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
698	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
699	IEM_MC_BEGIN(0, 1);
700	IEM_MC_LOCAL(uint32_t, uSrc);
701	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
702	IEM_MC_PREPARE_SSE_USAGE();
703	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
704	IEM_MC_AND_LOCAL_U8(bImm, 3);
705	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/, uSrc);
706	IEM_MC_ADVANCE_RIP_AND_FINISH();
707	IEM_MC_END();
708	}
709	else
710	{
711	/*
712	* XMM, [mem32].
713	*/
714	IEM_MC_BEGIN(0, 2);
715	IEM_MC_LOCAL(uint32_t, uSrc);
716	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
717
718	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
719	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
720	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
721	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
722	IEM_MC_PREPARE_SSE_USAGE();
723
724	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
725	IEM_MC_AND_LOCAL_U8(bImm, 3);
726	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/, uSrc);
727	IEM_MC_ADVANCE_RIP_AND_FINISH();
728	IEM_MC_END();
729	}
730	}
731	}
732
733
734	/* Opcode 0x66 0x0f 0x23 - invalid */
735	/* Opcode 0x66 0x0f 0x24 - invalid */
736	/* Opcode 0x66 0x0f 0x25 - invalid */
737	/* Opcode 0x66 0x0f 0x26 - invalid */
738	/* Opcode 0x66 0x0f 0x27 - invalid */
739	/* Opcode 0x66 0x0f 0x28 - invalid */
740	/* Opcode 0x66 0x0f 0x29 - invalid */
741	/* Opcode 0x66 0x0f 0x2a - invalid */
742	/* Opcode 0x66 0x0f 0x2b - invalid */
743	/* Opcode 0x66 0x0f 0x2c - invalid */
744	/* Opcode 0x66 0x0f 0x2d - invalid */
745	/* Opcode 0x66 0x0f 0x2e - invalid */
746	/* Opcode 0x66 0x0f 0x2f - invalid */
747
748
749	/* Opcode 0x66 0x0f 0x30 - invalid */
750	/* Opcode 0x66 0x0f 0x31 - invalid */
751	/* Opcode 0x66 0x0f 0x32 - invalid */
752	/* Opcode 0x66 0x0f 0x33 - invalid */
753	/* Opcode 0x66 0x0f 0x34 - invalid */
754	/* Opcode 0x66 0x0f 0x35 - invalid */
755	/* Opcode 0x66 0x0f 0x36 - invalid */
756	/* Opcode 0x66 0x0f 0x37 - invalid */
757	/* Opcode 0x66 0x0f 0x38 - invalid (vex only). */
758	/* Opcode 0x66 0x0f 0x39 - invalid (vex only). */
759	/* Opcode 0x66 0x0f 0x3a - invalid */
760	/* Opcode 0x66 0x0f 0x3b - invalid */
761	/* Opcode 0x66 0x0f 0x3c - invalid */
762	/* Opcode 0x66 0x0f 0x3d - invalid */
763	/* Opcode 0x66 0x0f 0x3e - invalid */
764	/* Opcode 0x66 0x0f 0x3f - invalid */
765
766
767	/** Opcode 0x66 0x0f 0x40. */
768	FNIEMOP_STUB(iemOp_dpps_Vx_Wx_Ib);
769	/** Opcode 0x66 0x0f 0x41, */
770	FNIEMOP_STUB(iemOp_dppd_Vdq_Wdq_Ib);
771	/** Opcode 0x66 0x0f 0x42. */
772	FNIEMOP_STUB(iemOp_mpsadbw_Vx_Wx_Ib);
773	/* Opcode 0x66 0x0f 0x43 - invalid */
774
775
776	/** Opcode 0x66 0x0f 0x44. */
777	FNIEMOP_DEF(iemOp_pclmulqdq_Vdq_Wdq_Ib)
778	{
779	IEMOP_MNEMONIC3(RMI, PCLMULQDQ, pclmulqdq, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
780
781	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
782	if (IEM_IS_MODRM_REG_MODE(bRm))
783	{
784	/*
785	* Register, register.
786	*/
787	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
788	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
789	IEM_MC_BEGIN(3, 0);
790	IEM_MC_ARG(PRTUINT128U, puDst, 0);
791	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
792	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
793	IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT();
794	IEM_MC_PREPARE_SSE_USAGE();
795	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
796	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
797	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
798	iemAImpl_pclmulqdq_u128,
799	iemAImpl_pclmulqdq_u128_fallback),
800	puDst, puSrc, bImmArg);
801	IEM_MC_ADVANCE_RIP_AND_FINISH();
802	IEM_MC_END();
803	}
804	else
805	{
806	/*
807	* Register, memory.
808	*/
809	IEM_MC_BEGIN(3, 2);
810	IEM_MC_ARG(PRTUINT128U, puDst, 0);
811	IEM_MC_LOCAL(RTUINT128U, uSrc);
812	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
813	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
814
815	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
816	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
817	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
818	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
819	IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT();
820	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
821
822	IEM_MC_PREPARE_SSE_USAGE();
823	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
824	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
825	iemAImpl_pclmulqdq_u128,
826	iemAImpl_pclmulqdq_u128_fallback),
827	puDst, puSrc, bImmArg);
828
829	IEM_MC_ADVANCE_RIP_AND_FINISH();
830	IEM_MC_END();
831	}
832	}
833
834
835	/* Opcode 0x66 0x0f 0x45 - invalid */
836	/* Opcode 0x66 0x0f 0x46 - invalid (vex only) */
837	/* Opcode 0x66 0x0f 0x47 - invalid */
838	/* Opcode 0x66 0x0f 0x48 - invalid */
839	/* Opcode 0x66 0x0f 0x49 - invalid */
840	/* Opcode 0x66 0x0f 0x4a - invalid (vex only). */
841	/* Opcode 0x66 0x0f 0x4b - invalid (vex only). */
842	/* Opcode 0x66 0x0f 0x4c - invalid (vex only). */
843	/* Opcode 0x66 0x0f 0x4d - invalid */
844	/* Opcode 0x66 0x0f 0x4e - invalid */
845	/* Opcode 0x66 0x0f 0x4f - invalid */
846
847
848	/* Opcode 0x66 0x0f 0x50 - invalid */
849	/* Opcode 0x66 0x0f 0x51 - invalid */
850	/* Opcode 0x66 0x0f 0x52 - invalid */
851	/* Opcode 0x66 0x0f 0x53 - invalid */
852	/* Opcode 0x66 0x0f 0x54 - invalid */
853	/* Opcode 0x66 0x0f 0x55 - invalid */
854	/* Opcode 0x66 0x0f 0x56 - invalid */
855	/* Opcode 0x66 0x0f 0x57 - invalid */
856	/* Opcode 0x66 0x0f 0x58 - invalid */
857	/* Opcode 0x66 0x0f 0x59 - invalid */
858	/* Opcode 0x66 0x0f 0x5a - invalid */
859	/* Opcode 0x66 0x0f 0x5b - invalid */
860	/* Opcode 0x66 0x0f 0x5c - invalid */
861	/* Opcode 0x66 0x0f 0x5d - invalid */
862	/* Opcode 0x66 0x0f 0x5e - invalid */
863	/* Opcode 0x66 0x0f 0x5f - invalid */
864
865
866	/** Opcode 0x66 0x0f 0x60. */
867	FNIEMOP_STUB(iemOp_pcmpestrm_Vdq_Wdq_Ib);
868	/** Opcode 0x66 0x0f 0x61, */
869	FNIEMOP_STUB(iemOp_pcmpestri_Vdq_Wdq_Ib);
870	/** Opcode 0x66 0x0f 0x62. */
871	FNIEMOP_STUB(iemOp_pcmpistrm_Vdq_Wdq_Ib);
872
873
874	/** Opcode 0x66 0x0f 0x63*/
875	FNIEMOP_DEF(iemOp_pcmpistri_Vdq_Wdq_Ib)
876	{
877	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
878	if (IEM_IS_MODRM_REG_MODE(bRm))
879	{
880	/*
881	* Register, register.
882	*/
883	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
884	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
885	IEM_MC_BEGIN(4, 1);
886	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
887	IEM_MC_ARG(uint32_t *, pEFlags, 1);
888	IEM_MC_LOCAL(IEMPCMPISTRISRC, Src);
889	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRISRC, pSrc, Src, 2);
890	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
891	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
892	IEM_MC_PREPARE_SSE_USAGE();
893	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
894	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
895	IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
896	IEM_MC_REF_EFLAGS(pEFlags);
897	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
898	iemAImpl_pcmpistri_u128,
899	iemAImpl_pcmpistri_u128_fallback),
900	pu32Ecx, pEFlags, pSrc, bImmArg);
901	/** @todo testcase: High dword of RCX cleared? */
902	IEM_MC_ADVANCE_RIP_AND_FINISH();
903	IEM_MC_END();
904	}
905	else
906	{
907	/*
908	* Register, memory.
909	*/
910	IEM_MC_BEGIN(4, 3);
911	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
912	IEM_MC_ARG(uint32_t *, pEFlags, 1);
913	IEM_MC_LOCAL(IEMPCMPISTRISRC, Src);
914	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRISRC, pSrc, Src, 2);
915	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
916
917	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
918	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
919	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
920	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
921	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
922	IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
923
924	IEM_MC_PREPARE_SSE_USAGE();
925	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
926	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
927	IEM_MC_REF_EFLAGS(pEFlags);
928	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
929	iemAImpl_pcmpistri_u128,
930	iemAImpl_pcmpistri_u128_fallback),
931	pu32Ecx, pEFlags, pSrc, bImmArg);
932	/** @todo testcase: High dword of RCX cleared? */
933	IEM_MC_ADVANCE_RIP_AND_FINISH();
934	IEM_MC_END();
935	}
936	}
937
938
939	/* Opcode 0x66 0x0f 0x64 - invalid */
940	/* Opcode 0x66 0x0f 0x65 - invalid */
941	/* Opcode 0x66 0x0f 0x66 - invalid */
942	/* Opcode 0x66 0x0f 0x67 - invalid */
943	/* Opcode 0x66 0x0f 0x68 - invalid */
944	/* Opcode 0x66 0x0f 0x69 - invalid */
945	/* Opcode 0x66 0x0f 0x6a - invalid */
946	/* Opcode 0x66 0x0f 0x6b - invalid */
947	/* Opcode 0x66 0x0f 0x6c - invalid */
948	/* Opcode 0x66 0x0f 0x6d - invalid */
949	/* Opcode 0x66 0x0f 0x6e - invalid */
950	/* Opcode 0x66 0x0f 0x6f - invalid */
951
952	/* Opcodes 0x0f 0x70 thru 0x0f 0xb0 are unused. */
953
954
955	/* Opcode 0x0f 0xc0 - invalid */
956	/* Opcode 0x0f 0xc1 - invalid */
957	/* Opcode 0x0f 0xc2 - invalid */
958	/* Opcode 0x0f 0xc3 - invalid */
959	/* Opcode 0x0f 0xc4 - invalid */
960	/* Opcode 0x0f 0xc5 - invalid */
961	/* Opcode 0x0f 0xc6 - invalid */
962	/* Opcode 0x0f 0xc7 - invalid */
963	/* Opcode 0x0f 0xc8 - invalid */
964	/* Opcode 0x0f 0xc9 - invalid */
965	/* Opcode 0x0f 0xca - invalid */
966	/* Opcode 0x0f 0xcb - invalid */
967	/* Opcode 0x0f 0xcc */
968	FNIEMOP_STUB(iemOp_sha1rnds4_Vdq_Wdq_Ib);
969	/* Opcode 0x0f 0xcd - invalid */
970	/* Opcode 0x0f 0xce - invalid */
971	/* Opcode 0x0f 0xcf - invalid */
972
973
974	/* Opcode 0x66 0x0f 0xd0 - invalid */
975	/* Opcode 0x66 0x0f 0xd1 - invalid */
976	/* Opcode 0x66 0x0f 0xd2 - invalid */
977	/* Opcode 0x66 0x0f 0xd3 - invalid */
978	/* Opcode 0x66 0x0f 0xd4 - invalid */
979	/* Opcode 0x66 0x0f 0xd5 - invalid */
980	/* Opcode 0x66 0x0f 0xd6 - invalid */
981	/* Opcode 0x66 0x0f 0xd7 - invalid */
982	/* Opcode 0x66 0x0f 0xd8 - invalid */
983	/* Opcode 0x66 0x0f 0xd9 - invalid */
984	/* Opcode 0x66 0x0f 0xda - invalid */
985	/* Opcode 0x66 0x0f 0xdb - invalid */
986	/* Opcode 0x66 0x0f 0xdc - invalid */
987	/* Opcode 0x66 0x0f 0xdd - invalid */
988	/* Opcode 0x66 0x0f 0xde - invalid */
989
990
991	/* Opcode 0x66 0x0f 0xdf - (aeskeygenassist). */
992	FNIEMOP_DEF(iemOp_aeskeygen_Vdq_Wdq_Ib)
993	{
994	IEMOP_MNEMONIC3(RMI, AESKEYGEN, aeskeygen, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_SSE, 0);
995	return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFullImm8_To_Full,
996	IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback));
997	}
998
999
1000	/* Opcode 0xf2 0x0f 0xf0 - invalid (vex only) */
1001
1002
1003	/**
1004	* Three byte opcode map, first two bytes are 0x0f 0x3a.
1005	* @sa g_apfnVexMap2
1006	*/
1007	IEM_STATIC const PFNIEMOP g_apfnThreeByte0f3a[] =
1008	{
1009	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1010	/* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1011	/* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1012	/* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1013	/* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1014	/* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1015	/* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1016	/* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1017	/* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1018	/* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_roundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1019	/* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_roundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1020	/* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_roundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1021	/* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_roundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1022	/* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_blendps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1023	/* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_blendpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1024	/* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_pblendw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1025	/* 0x0f */ iemOp_palignr_Pq_Qq_Ib, iemOp_palignr_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1026
1027	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1028	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1029	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1030	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1031	/* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_pextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1032	/* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_pextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1033	/* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_pextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1034	/* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_extractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1035	/* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1036	/* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1037	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1038	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1039	/* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1040	/* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1041	/* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1042	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1043
1044	/* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrb_Vdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1045	/* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_insertps_Vdq_UdqMd_Ib,iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1046	/* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrd_q_Vdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1047	/* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1048	/* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1049	/* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1050	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1051	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1052	/* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1053	/* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1054	/* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1055	/* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1056	/* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1057	/* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1058	/* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1059	/* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1060
1061	/* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1062	/* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1063	/* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1064	/* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1065	/* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1066	/* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1067	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1068	/* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1069	/* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1070	/* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1071	/* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1072	/* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1073	/* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1074	/* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1075	/* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1076	/* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1077
1078	/* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_dpps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1079	/* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_dppd_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1080	/* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_mpsadbw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1081	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1082	/* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_pclmulqdq_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1083	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1084	/* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1085	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1086	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1087	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1088	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1089	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1090	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1091	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1092	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1093	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1094
1095	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1096	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1097	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1098	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1099	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1100	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1101	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1102	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1103	/* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1104	/* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1105	/* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1106	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1107	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1108	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1109	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1110	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1111
1112	/* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1113	/* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1114	/* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1115	/* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1116	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1117	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1118	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1119	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1120	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1121	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1122	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1123	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1124	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1125	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1126	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1127	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1128
1129	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1130	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1131	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1132	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1133	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1134	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1135	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1136	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1137	/* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1138	/* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1139	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1140	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1141	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1142	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1143	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1144	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1145
1146	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1147	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1148	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1149	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1150	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1151	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1152	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1153	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1154	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1155	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1156	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1157	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1158	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1159	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1160	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1161	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1162
1163	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1164	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1165	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1166	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1167	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1168	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1169	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1170	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1171	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1172	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1173	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1174	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1175	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1176	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1177	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1178	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1179
1180	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1181	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1182	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1183	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1184	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1185	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1186	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1187	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1188	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1189	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1190	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1191	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1192	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1193	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1194	/* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1195	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1196
1197	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1198	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1199	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1200	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1201	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1202	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1203	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1204	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1205	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1206	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1207	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1208	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1209	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1210	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1211	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1212	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1213
1214	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1215	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1216	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1217	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1218	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1219	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1220	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1221	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1222	/* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1223	/* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1224	/* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1225	/* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1226	/* 0xcc */ iemOp_sha1rnds4_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1227	/* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1228	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1229	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1230
1231	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1232	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1233	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1234	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1235	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1236	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1237	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1238	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1239	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1240	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1241	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1242	/* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1243	/* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1244	/* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1245	/* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1246	/* 0xdf */ iemOp_InvalidNeedRMImm8, iemOp_aeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1247
1248	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1249	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1250	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1251	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1252	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1253	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1254	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1255	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1256	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1257	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1258	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1259	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1260	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1261	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1262	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1263	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1264
1265	/* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1266	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1267	/* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1268	/* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1269	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1270	/* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1271	/* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1272	/* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1273	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1274	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1275	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1276	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1277	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1278	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1279	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1280	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1281	};
1282	AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f3a) == 1024);
1283
1284	/** @} */
1285

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h@ 97676

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