IEMAllInstructionsThree0f3a.cpp.h@ 99220

Last change on this file since 99220 was 99220, checked in by vboxsync, 21 months ago
Disassember,*: Start separating the disassembler into a architecture specific and common part, bugref:10394
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1	/* $Id: IEMAllInstructionsThree0f3a.cpp.h 99220 2023-03-30 12:40:46Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4	*
5	* @remarks IEMAllInstructionsVexMap3.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
11	*
12	* This file is part of VirtualBox base platform packages, as
13	* available from https://www.virtualbox.org.
14	*
15	* This program is free software; you can redistribute it and/or
16	* modify it under the terms of the GNU General Public License
17	* as published by the Free Software Foundation, in version 3 of the
18	* License.
19	*
20	* This program is distributed in the hope that it will be useful, but
21	* WITHOUT ANY WARRANTY; without even the implied warranty of
22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23	* General Public License for more details.
24	*
25	* You should have received a copy of the GNU General Public License
26	* along with this program; if not, see <https://www.gnu.org/licenses>.
27	*
28	* SPDX-License-Identifier: GPL-3.0-only
29	*/
30
31
32	/** @name Three byte opcodes with first two bytes 0x0f 0x3a
33	* @{
34	*/
35
36	/**
37	* Common worker for SSSE3 instructions on the forms:
38	* pxxx xmm1, xmm2/mem128, imm8
39	*
40	* Proper alignment of the 128-bit operand is enforced.
41	* Exceptions type 4. SSSE3 cpuid checks.
42	*
43	* @sa iemOpCommonSse41_FullFullImm8_To_Full
44	*/
45	FNIEMOP_DEF_1(iemOpCommonSsse3_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
46	{
47	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48	if (IEM_IS_MODRM_REG_MODE(bRm))
49	{
50	/*
51	* Register, register.
52	*/
53	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
54	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
55	IEM_MC_BEGIN(3, 0);
56	IEM_MC_ARG(PRTUINT128U, puDst, 0);
57	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
58	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
59	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
60	IEM_MC_PREPARE_SSE_USAGE();
61	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
62	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
63	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
64	IEM_MC_ADVANCE_RIP_AND_FINISH();
65	IEM_MC_END();
66	}
67	else
68	{
69	/*
70	* Register, memory.
71	*/
72	IEM_MC_BEGIN(3, 2);
73	IEM_MC_ARG(PRTUINT128U, puDst, 0);
74	IEM_MC_LOCAL(RTUINT128U, uSrc);
75	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
76	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
77
78	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
79	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
80	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
81	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
82	IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT();
83	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
84
85	IEM_MC_PREPARE_SSE_USAGE();
86	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
87	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
88
89	IEM_MC_ADVANCE_RIP_AND_FINISH();
90	IEM_MC_END();
91	}
92	}
93
94
95	/**
96	* Common worker for SSE 4.1 instructions on the forms:
97	* pxxx xmm1, xmm2/mem128, imm8
98	*
99	* Proper alignment of the 128-bit operand is enforced.
100	* No SIMD exceptions. SSE 4.1 cpuid checks.
101	*
102	* @sa iemOpCommonSsse3_FullFullImm8_To_Full
103	*/
104	FNIEMOP_DEF_1(iemOpCommonSse41_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
105	{
106	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
107	if (IEM_IS_MODRM_REG_MODE(bRm))
108	{
109	/*
110	* XMM, XMM, imm8
111	*/
112	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
113	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
114	IEM_MC_BEGIN(3, 0);
115	IEM_MC_ARG(PRTUINT128U, puDst, 0);
116	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
117	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
118	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
119	IEM_MC_PREPARE_SSE_USAGE();
120	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
121	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
122	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
123	IEM_MC_ADVANCE_RIP_AND_FINISH();
124	IEM_MC_END();
125	}
126	else
127	{
128	/*
129	* XMM, [mem128], imm8.
130	*/
131	IEM_MC_BEGIN(3, 2);
132	IEM_MC_ARG(PRTUINT128U, puDst, 0);
133	IEM_MC_LOCAL(RTUINT128U, uSrc);
134	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
135	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
136
137	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
138	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
139	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
140	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
141	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
142	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
143
144	IEM_MC_PREPARE_SSE_USAGE();
145	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
146	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
147
148	IEM_MC_ADVANCE_RIP_AND_FINISH();
149	IEM_MC_END();
150	}
151	}
152
153
154	/**
155	* Common worker for SSE 4.1 instructions of the form:
156	* xxx xmm1, xmm2/mem128, imm8
157	*
158	* Proper alignment of the 128-bit operand is enforced.
159	* MXCSR is used as input and output.
160	* Exceptions type 4. SSE 4.1 cpuid checks.
161	*
162	* @sa iemOpCommonSse41_FullFullImm8_To_Full
163	*/
164	FNIEMOP_DEF_1(iemOpCommonSse41Fp_FullFullImm8_To_Full, FNIEMAIMPLMXCSRF2XMMIMM8, pfnU128)
165	{
166	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
167	if (IEM_IS_MODRM_REG_MODE(bRm))
168	{
169	/*
170	* XMM, XMM, imm8.
171	*/
172	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
173	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
174	IEM_MC_BEGIN(4, 2);
175	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
176	IEM_MC_LOCAL(X86XMMREG, Dst);
177	IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
178	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
179	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
180	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
181	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
182	IEM_MC_PREPARE_SSE_USAGE();
183	IEM_MC_REF_MXCSR(pfMxcsr);
184	IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
185	IEM_MC_FETCH_XREG_XMM(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
186	IEM_MC_CALL_VOID_AIMPL_4(pfnU128, pfMxcsr, pDst, pSrc, bImmArg);
187	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
188	IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
189
190	IEM_MC_ADVANCE_RIP_AND_FINISH();
191	IEM_MC_END();
192	}
193	else
194	{
195	/*
196	* XMM, [mem128], imm8.
197	*/
198	IEM_MC_BEGIN(4, 3);
199	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
200	IEM_MC_LOCAL(X86XMMREG, Dst);
201	IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
202	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
203	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
204	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
205
206	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
207	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
208	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
209	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
210	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
211	IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
212
213	IEM_MC_PREPARE_SSE_USAGE();
214	IEM_MC_REF_MXCSR(pfMxcsr);
215	IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
216	IEM_MC_CALL_VOID_AIMPL_4(pfnU128, pfMxcsr, pDst, pSrc, bImmArg);
217	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
218	IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
219
220	IEM_MC_ADVANCE_RIP_AND_FINISH();
221	IEM_MC_END();
222	}
223	}
224
225
226	/**
227	* Common worker for SSE-style AES-NI instructions of the form:
228	* aesxxx xmm1, xmm2/mem128, imm8
229	*
230	* Proper alignment of the 128-bit operand is enforced.
231	* Exceptions type 4. AES-NI cpuid checks.
232	*
233	* @sa iemOpCommonSsse3_FullFullImm8_To_Full
234	* @sa iemOpCommonSse41_FullFullImm8_To_Full
235	*/
236	FNIEMOP_DEF_1(iemOpCommonAesNi_FullFullImm8_To_Full, PFNIEMAIMPLMEDIAOPTF2U128IMM8, pfnU128)
237	{
238	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
239	if (IEM_IS_MODRM_REG_MODE(bRm))
240	{
241	/*
242	* Register, register.
243	*/
244	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
245	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
246	IEM_MC_BEGIN(3, 0);
247	IEM_MC_ARG(PRTUINT128U, puDst, 0);
248	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
249	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
250	IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT();
251	IEM_MC_PREPARE_SSE_USAGE();
252	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
253	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
254	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
255	IEM_MC_ADVANCE_RIP_AND_FINISH();
256	IEM_MC_END();
257	}
258	else
259	{
260	/*
261	* Register, memory.
262	*/
263	IEM_MC_BEGIN(3, 2);
264	IEM_MC_ARG(PRTUINT128U, puDst, 0);
265	IEM_MC_LOCAL(RTUINT128U, uSrc);
266	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
267	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
268
269	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
270	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
271	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
272	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
273	IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT();
274	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
275
276	IEM_MC_PREPARE_SSE_USAGE();
277	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
278	IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg);
279
280	IEM_MC_ADVANCE_RIP_AND_FINISH();
281	IEM_MC_END();
282	}
283	}
284
285
286	/** Opcode 0x66 0x0f 0x00 - invalid (vex only). */
287	/** Opcode 0x66 0x0f 0x01 - invalid (vex only). */
288	/** Opcode 0x66 0x0f 0x02 - invalid (vex only). */
289	/* Opcode 0x66 0x0f 0x03 - invalid */
290	/** Opcode 0x66 0x0f 0x04 - invalid (vex only). */
291	/** Opcode 0x66 0x0f 0x05 - invalid (vex only). */
292	/* Opcode 0x66 0x0f 0x06 - invalid (vex only) */
293	/* Opcode 0x66 0x0f 0x07 - invalid */
294	/** Opcode 0x66 0x0f 0x08. */
295	FNIEMOP_DEF(iemOp_roundps_Vx_Wx_Ib)
296	{
297	IEMOP_MNEMONIC3(RMI, ROUNDPS, roundps, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
298	return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
299	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback));
300	}
301
302
303	/** Opcode 0x66 0x0f 0x09. */
304	FNIEMOP_DEF(iemOp_roundpd_Vx_Wx_Ib)
305	{
306	IEMOP_MNEMONIC3(RMI, ROUNDPD, roundpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
307	return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
308	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback));
309	}
310
311
312	/** Opcode 0x66 0x0f 0x0a. */
313	FNIEMOP_DEF(iemOp_roundss_Vss_Wss_Ib)
314	{
315	/* The instruction form is very similar to CMPSS. */
316	IEMOP_MNEMONIC3(RMI, ROUNDSS, roundss, Vss, Wss, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
317
318	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
319	if (IEM_IS_MODRM_REG_MODE(bRm))
320	{
321	/*
322	* XMM32, XMM32.
323	*/
324	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
325	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
326	IEM_MC_BEGIN(4, 2);
327	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
328	IEM_MC_LOCAL(X86XMMREG, Dst);
329	IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
330	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
331	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
332	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
333	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
334	IEM_MC_PREPARE_SSE_USAGE();
335	IEM_MC_REF_MXCSR(pfMxcsr);
336	IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
337	IEM_MC_FETCH_XREG_XMM(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
338	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_roundss_u128, pfMxcsr, pDst, pSrc, bImmArg);
339	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
340	IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /a_iDword/, Dst);
341
342	IEM_MC_ADVANCE_RIP_AND_FINISH();
343	IEM_MC_END();
344	}
345	else
346	{
347	/*
348	* XMM32, [mem32].
349	*/
350	IEM_MC_BEGIN(4, 3);
351	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
352	IEM_MC_LOCAL(X86XMMREG, Dst);
353	IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
354	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
355	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
356	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
357
358	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
359	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
360	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
361	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
362	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
363	IEM_MC_FETCH_MEM_XMM_U32(Src.uSrc2, 0 /a_iDword /, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
364
365	IEM_MC_PREPARE_SSE_USAGE();
366	IEM_MC_REF_MXCSR(pfMxcsr);
367	IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
368	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_roundss_u128, pfMxcsr, pDst, pSrc, bImmArg);
369	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
370	IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /a_iDword/, Dst);
371
372	IEM_MC_ADVANCE_RIP_AND_FINISH();
373	IEM_MC_END();
374	}
375	}
376
377	/** Opcode 0x66 0x0f 0x0b. */
378	FNIEMOP_DEF(iemOp_roundsd_Vsd_Wsd_Ib)
379	{
380	/* The instruction form is very similar to CMPSD. */
381	IEMOP_MNEMONIC3(RMI, ROUNDSD, roundsd, Vsd, Wsd, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
382
383	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
384	if (IEM_IS_MODRM_REG_MODE(bRm))
385	{
386	/*
387	* XMM64, XMM64, imm8.
388	*/
389	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
390	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
391	IEM_MC_BEGIN(4, 2);
392	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
393	IEM_MC_LOCAL(X86XMMREG, Dst);
394	IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
395	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
396	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
397	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
398	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
399	IEM_MC_PREPARE_SSE_USAGE();
400	IEM_MC_REF_MXCSR(pfMxcsr);
401	IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
402	IEM_MC_FETCH_XREG_XMM(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
403	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_roundsd_u128, pfMxcsr, pDst, pSrc, bImmArg);
404	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
405	IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /a_iQword/, Dst);
406
407	IEM_MC_ADVANCE_RIP_AND_FINISH();
408	IEM_MC_END();
409	}
410	else
411	{
412	/*
413	* XMM64, [mem64], imm8.
414	*/
415	IEM_MC_BEGIN(4, 3);
416	IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src);
417	IEM_MC_LOCAL(X86XMMREG, Dst);
418	IEM_MC_ARG(uint32_t *, pfMxcsr, 0);
419	IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1);
420	IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2);
421	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
422
423	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
424	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
425	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
426	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
427	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
428	IEM_MC_FETCH_MEM_XMM_U64(Src.uSrc2, 0 /a_iQword /, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
429
430	IEM_MC_PREPARE_SSE_USAGE();
431	IEM_MC_REF_MXCSR(pfMxcsr);
432	IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
433	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_roundsd_u128, pfMxcsr, pDst, pSrc, bImmArg);
434	IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
435	IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /a_iQword/, Dst);
436
437	IEM_MC_ADVANCE_RIP_AND_FINISH();
438	IEM_MC_END();
439	}
440	}
441
442
443	/** Opcode 0x66 0x0f 0x0c. */
444	FNIEMOP_DEF(iemOp_blendps_Vx_Wx_Ib)
445	{
446	IEMOP_MNEMONIC3(RMI, BLENDPS, blendps, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
447	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
448	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback));
449	}
450
451
452	/** Opcode 0x66 0x0f 0x0d. */
453	FNIEMOP_DEF(iemOp_blendpd_Vx_Wx_Ib)
454	{
455	IEMOP_MNEMONIC3(RMI, BLENDPD, blendpd, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
456	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
457	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback));
458	}
459
460
461	/** Opcode 0x66 0x0f 0x0e. */
462	FNIEMOP_DEF(iemOp_pblendw_Vx_Wx_Ib)
463	{
464	IEMOP_MNEMONIC3(RMI, PBLENDW, pblendw, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
465	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
466	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback));
467	}
468
469
470	/** Opcode 0x0f 0x0f. */
471	FNIEMOP_DEF(iemOp_palignr_Pq_Qq_Ib)
472	{
473	IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Pq, Qq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
474	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
475	if (IEM_IS_MODRM_REG_MODE(bRm))
476	{
477	/*
478	* Register, register.
479	*/
480	/** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
481	/** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
482	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
483	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
484	IEM_MC_BEGIN(3, 0);
485	IEM_MC_ARG(uint64_t *, pDst, 0);
486	IEM_MC_ARG(uint64_t, uSrc, 1);
487	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
488	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
489	IEM_MC_PREPARE_FPU_USAGE();
490	IEM_MC_FPU_TO_MMX_MODE();
491	IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
492	IEM_MC_FETCH_MREG_U64(uSrc, IEM_GET_MODRM_RM_8(bRm));
493	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
494	pDst, uSrc, bImmArg);
495	IEM_MC_MODIFIED_MREG_BY_REF(pDst);
496	IEM_MC_ADVANCE_RIP_AND_FINISH();
497	IEM_MC_END();
498	}
499	else
500	{
501	/*
502	* Register, memory.
503	*/
504	IEM_MC_BEGIN(3, 1);
505	IEM_MC_ARG(uint64_t *, pDst, 0);
506	IEM_MC_ARG(uint64_t, uSrc, 1);
507	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
508
509	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
510	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
511	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
512	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
513	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3);
514	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
515
516	IEM_MC_PREPARE_FPU_USAGE();
517	IEM_MC_FPU_TO_MMX_MODE();
518	IEM_MC_REF_MREG_U64(pDst, IEM_GET_MODRM_REG_8(bRm));
519	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u64, iemAImpl_palignr_u64_fallback),
520	pDst, uSrc, bImmArg);
521	IEM_MC_MODIFIED_MREG_BY_REF(pDst);
522
523	IEM_MC_ADVANCE_RIP_AND_FINISH();
524	IEM_MC_END();
525	}
526	}
527
528
529	/** Opcode 0x66 0x0f 0x0f. */
530	FNIEMOP_DEF(iemOp_palignr_Vx_Wx_Ib)
531	{
532	IEMOP_MNEMONIC3(RMI, PALIGNR, palignr, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
533	return FNIEMOP_CALL_1(iemOpCommonSsse3_FullFullImm8_To_Full,
534	IEM_SELECT_HOST_OR_FALLBACK(fSsse3, iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback));
535	}
536
537
538	/* Opcode 0x66 0x0f 0x10 - invalid */
539	/* Opcode 0x66 0x0f 0x11 - invalid */
540	/* Opcode 0x66 0x0f 0x12 - invalid */
541	/* Opcode 0x66 0x0f 0x13 - invalid */
542
543
544	/** Opcode 0x66 0x0f 0x14. */
545	FNIEMOP_DEF(iemOp_pextrb_RdMb_Vdq_Ib)
546	{
547	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
548	IEMOP_MNEMONIC3(MRI, PEXTRB, pextrb, Ev, Vq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
549	if (IEM_IS_MODRM_REG_MODE(bRm))
550	{
551	/*
552	* greg32, XMM.
553	*/
554	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
555	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
556	IEM_MC_BEGIN(0, 1);
557	IEM_MC_LOCAL(uint8_t, uValue);
558	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
559	IEM_MC_PREPARE_SSE_USAGE();
560	IEM_MC_AND_LOCAL_U8(bImm, 15);
561	IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iByte/);
562	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
563	IEM_MC_ADVANCE_RIP_AND_FINISH();
564	IEM_MC_END();
565	}
566	else
567	{
568	/*
569	* [mem8], XMM.
570	*/
571	IEM_MC_BEGIN(0, 2);
572	IEM_MC_LOCAL(uint8_t, uValue);
573	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
574
575	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
576	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
577	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
578	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
579	IEM_MC_PREPARE_SSE_USAGE();
580
581	IEM_MC_AND_LOCAL_U8(bImm, 15);
582	IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iByte/);
583	IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
584	IEM_MC_ADVANCE_RIP_AND_FINISH();
585	IEM_MC_END();
586	}
587	}
588
589
590	/** Opcode 0x66 0x0f 0x15. */
591	FNIEMOP_DEF(iemOp_pextrw_RdMw_Vdq_Ib)
592	{
593	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
594	IEMOP_MNEMONIC3(MRI, PEXTRW, pextrw, Ev, Vq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
595	if (IEM_IS_MODRM_REG_MODE(bRm))
596	{
597	/*
598	* greg32, XMM.
599	*/
600	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
601	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
602	IEM_MC_BEGIN(0, 1);
603	IEM_MC_LOCAL(uint16_t, uValue);
604	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
605	IEM_MC_PREPARE_SSE_USAGE();
606	IEM_MC_AND_LOCAL_U8(bImm, 7);
607	IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iWord/);
608	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue);
609	IEM_MC_ADVANCE_RIP_AND_FINISH();
610	IEM_MC_END();
611	}
612	else
613	{
614	/*
615	* [mem16], XMM.
616	*/
617	IEM_MC_BEGIN(0, 2);
618	IEM_MC_LOCAL(uint16_t, uValue);
619	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
620
621	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
622	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
623	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
624	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
625	IEM_MC_PREPARE_SSE_USAGE();
626
627	IEM_MC_AND_LOCAL_U8(bImm, 7);
628	IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iWord/);
629	IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue);
630	IEM_MC_ADVANCE_RIP_AND_FINISH();
631	IEM_MC_END();
632	}
633	}
634
635
636	FNIEMOP_DEF(iemOp_pextrd_q_RdMw_Vdq_Ib)
637	{
638	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
639	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
640	{
641	/**
642	* @opcode 0x16
643	* @opcodesub rex.w=1
644	* @oppfx 0x66
645	* @opcpuid sse
646	*/
647	IEMOP_MNEMONIC3(MRI, PEXTRQ, pextrq, Ev, Vq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
648	if (IEM_IS_MODRM_REG_MODE(bRm))
649	{
650	/*
651	* greg64, XMM.
652	*/
653	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
654	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
655	IEM_MC_BEGIN(0, 1);
656	IEM_MC_LOCAL(uint64_t, uSrc);
657	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
658	IEM_MC_PREPARE_SSE_USAGE();
659	IEM_MC_AND_LOCAL_U8(bImm, 1);
660	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/);
661	IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
662	IEM_MC_ADVANCE_RIP_AND_FINISH();
663	IEM_MC_END();
664	}
665	else
666	{
667	/*
668	* [mem64], XMM.
669	*/
670	IEM_MC_BEGIN(0, 2);
671	IEM_MC_LOCAL(uint64_t, uSrc);
672	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
673
674	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
675	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
676	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
677	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
678	IEM_MC_PREPARE_SSE_USAGE();
679
680	IEM_MC_AND_LOCAL_U8(bImm, 1);
681	IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/);
682	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
683	IEM_MC_ADVANCE_RIP_AND_FINISH();
684	IEM_MC_END();
685	}
686	}
687	else
688	{
689	/**
690	* @opdone
691	* @opcode 0x16
692	* @opcodesub rex.w=0
693	* @oppfx 0x66
694	* @opcpuid sse
695	*/
696	IEMOP_MNEMONIC3(MRI, PEXTRD, pextrd, Ey, Vd, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
697	if (IEM_IS_MODRM_REG_MODE(bRm))
698	{
699	/*
700	* greg32, XMM.
701	*/
702	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
703	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
704	IEM_MC_BEGIN(0, 1);
705	IEM_MC_LOCAL(uint32_t, uSrc);
706	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
707	IEM_MC_PREPARE_SSE_USAGE();
708	IEM_MC_AND_LOCAL_U8(bImm, 3);
709	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/);
710	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
711	IEM_MC_ADVANCE_RIP_AND_FINISH();
712	IEM_MC_END();
713	}
714	else
715	{
716	/*
717	* [mem32], XMM.
718	*/
719	IEM_MC_BEGIN(0, 2);
720	IEM_MC_LOCAL(uint32_t, uSrc);
721	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
722
723	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
724	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
725	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
726	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
727	IEM_MC_PREPARE_SSE_USAGE();
728	IEM_MC_AND_LOCAL_U8(bImm, 3);
729	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/);
730	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
731	IEM_MC_ADVANCE_RIP_AND_FINISH();
732	IEM_MC_END();
733	}
734	}
735	}
736
737
738	/** Opcode 0x66 0x0f 0x17. */
739	FNIEMOP_DEF(iemOp_extractps_Ed_Vdq_Ib)
740	{
741	IEMOP_MNEMONIC3(MRI, EXTRACTPS, extractps, Ed, Vdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
742	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
743	if (IEM_IS_MODRM_REG_MODE(bRm))
744	{
745	/*
746	* greg32, XMM.
747	*/
748	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
749	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
750	IEM_MC_BEGIN(0, 1);
751	IEM_MC_LOCAL(uint32_t, uSrc);
752	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
753	IEM_MC_PREPARE_SSE_USAGE();
754	IEM_MC_AND_LOCAL_U8(bImm, 3);
755	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/);
756	IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc);
757	IEM_MC_ADVANCE_RIP_AND_FINISH();
758	IEM_MC_END();
759	}
760	else
761	{
762	/*
763	* [mem32], XMM.
764	*/
765	IEM_MC_BEGIN(0, 2);
766	IEM_MC_LOCAL(uint32_t, uSrc);
767	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
768
769	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
770	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
771	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
772	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
773	IEM_MC_PREPARE_SSE_USAGE();
774	IEM_MC_AND_LOCAL_U8(bImm, 3);
775	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/);
776	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
777	IEM_MC_ADVANCE_RIP_AND_FINISH();
778	IEM_MC_END();
779	}
780	}
781
782
783	/* Opcode 0x66 0x0f 0x18 - invalid (vex only). */
784	/* Opcode 0x66 0x0f 0x19 - invalid (vex only). */
785	/* Opcode 0x66 0x0f 0x1a - invalid */
786	/* Opcode 0x66 0x0f 0x1b - invalid */
787	/* Opcode 0x66 0x0f 0x1c - invalid */
788	/* Opcode 0x66 0x0f 0x1d - invalid (vex only). */
789	/* Opcode 0x66 0x0f 0x1e - invalid */
790	/* Opcode 0x66 0x0f 0x1f - invalid */
791
792
793	/** Opcode 0x66 0x0f 0x20. */
794	FNIEMOP_DEF(iemOp_pinsrb_Vdq_RyMb_Ib)
795	{
796	IEMOP_MNEMONIC3(RMI, PINSRB, pinsrb, Vd, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OP_SIZES);
797	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
798	if (IEM_IS_MODRM_REG_MODE(bRm))
799	{
800	/*
801	* XMM, greg32.
802	*/
803	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
804	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
805	IEM_MC_BEGIN(0, 1);
806	IEM_MC_LOCAL(uint8_t, uSrc);
807	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
808	IEM_MC_PREPARE_SSE_USAGE();
809	IEM_MC_FETCH_GREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
810	IEM_MC_AND_LOCAL_U8(bImm, 15);
811	IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iByte/, uSrc);
812	IEM_MC_ADVANCE_RIP_AND_FINISH();
813	IEM_MC_END();
814	}
815	else
816	{
817	/*
818	* XMM, [mem8].
819	*/
820	IEM_MC_BEGIN(0, 2);
821	IEM_MC_LOCAL(uint8_t, uSrc);
822	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
823
824	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
825	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
826	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
827	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
828	IEM_MC_PREPARE_SSE_USAGE();
829
830	IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
831	IEM_MC_AND_LOCAL_U8(bImm, 15);
832	IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iByte/, uSrc);
833	IEM_MC_ADVANCE_RIP_AND_FINISH();
834	IEM_MC_END();
835	}
836	}
837
838	/** Opcode 0x66 0x0f 0x21, */
839	FNIEMOP_DEF(iemOp_insertps_Vdq_UdqMd_Ib)
840	{
841	IEMOP_MNEMONIC3(RMI, INSERTPS, insertps, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0); /// @todo
842	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
843	if (IEM_IS_MODRM_REG_MODE(bRm))
844	{
845	/*
846	* XMM, XMM.
847	*/
848	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
849	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
850	IEM_MC_BEGIN(0, 3);
851	IEM_MC_LOCAL(uint32_t, uSrc);
852	IEM_MC_LOCAL(uint8_t, uSrcSel);
853	IEM_MC_LOCAL(uint8_t, uDstSel);
854	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
855	IEM_MC_PREPARE_SSE_USAGE();
856	IEM_MC_ASSIGN(uSrcSel, bImm);
857	IEM_MC_SHR_LOCAL_U8(uSrcSel, 6);
858	IEM_MC_AND_LOCAL_U8(uSrcSel, 3);
859	IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), uSrcSel);
860	IEM_MC_ASSIGN(uDstSel, bImm);
861	IEM_MC_SHR_LOCAL_U8(uDstSel, 4);
862	IEM_MC_AND_LOCAL_U8(uDstSel, 3);
863	IEM_MC_CLEAR_XREG_U32_MASK(IEM_GET_MODRM_REG(pVCpu, bRm), bImm);
864	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uDstSel, uSrc);
865	IEM_MC_ADVANCE_RIP_AND_FINISH();
866	IEM_MC_END();
867	}
868	else
869	{
870	/*
871	* XMM, [mem32].
872	*/
873	IEM_MC_BEGIN(0, 3);
874	IEM_MC_LOCAL(uint32_t, uSrc);
875	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
876	IEM_MC_LOCAL(uint8_t, uDstSel);
877
878	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
879	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
880	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
881	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
882	IEM_MC_PREPARE_SSE_USAGE();
883
884	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
885	IEM_MC_ASSIGN(uDstSel, bImm);
886	IEM_MC_SHR_LOCAL_U8(uDstSel, 4);
887	IEM_MC_AND_LOCAL_U8(uDstSel, 3);
888	IEM_MC_CLEAR_XREG_U32_MASK(IEM_GET_MODRM_REG(pVCpu, bRm), bImm);
889	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uDstSel, uSrc);
890	IEM_MC_ADVANCE_RIP_AND_FINISH();
891	IEM_MC_END();
892	}
893	}
894
895	FNIEMOP_DEF(iemOp_pinsrd_q_Vdq_Ey_Ib)
896	{
897	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
898	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
899	{
900	/**
901	* @opcode 0x22
902	* @opcodesub rex.w=1
903	* @oppfx 0x66
904	* @opcpuid sse
905	*/
906	IEMOP_MNEMONIC3(RMI, PINSRQ, pinsrq, Vq, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
907	if (IEM_IS_MODRM_REG_MODE(bRm))
908	{
909	/*
910	* XMM, greg64.
911	*/
912	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
913	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
914	IEM_MC_BEGIN(0, 1);
915	IEM_MC_LOCAL(uint64_t, uSrc);
916	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
917	IEM_MC_PREPARE_SSE_USAGE();
918	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
919	IEM_MC_AND_LOCAL_U8(bImm, 1);
920	IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/, uSrc);
921	IEM_MC_ADVANCE_RIP_AND_FINISH();
922	IEM_MC_END();
923	}
924	else
925	{
926	/*
927	* XMM, [mem64].
928	*/
929	IEM_MC_BEGIN(0, 2);
930	IEM_MC_LOCAL(uint64_t, uSrc);
931	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
932
933	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
934	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
935	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
936	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
937	IEM_MC_PREPARE_SSE_USAGE();
938
939	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
940	IEM_MC_AND_LOCAL_U8(bImm, 1);
941	IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iQword/, uSrc);
942	IEM_MC_ADVANCE_RIP_AND_FINISH();
943	IEM_MC_END();
944	}
945	}
946	else
947	{
948	/**
949	* @opdone
950	* @opcode 0x22
951	* @opcodesub rex.w=0
952	* @oppfx 0x66
953	* @opcpuid sse
954	*/
955	IEMOP_MNEMONIC3(RMI, PINSRD, pinsrd, Vd, Ey, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, IEMOPHINT_IGNORES_OZ_PFX);
956	if (IEM_IS_MODRM_REG_MODE(bRm))
957	{
958	/*
959	* XMM, greg32.
960	*/
961	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
962	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
963	IEM_MC_BEGIN(0, 1);
964	IEM_MC_LOCAL(uint32_t, uSrc);
965	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
966	IEM_MC_PREPARE_SSE_USAGE();
967	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
968	IEM_MC_AND_LOCAL_U8(bImm, 3);
969	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/, uSrc);
970	IEM_MC_ADVANCE_RIP_AND_FINISH();
971	IEM_MC_END();
972	}
973	else
974	{
975	/*
976	* XMM, [mem32].
977	*/
978	IEM_MC_BEGIN(0, 2);
979	IEM_MC_LOCAL(uint32_t, uSrc);
980	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
981
982	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
983	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
984	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
985	IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT();
986	IEM_MC_PREPARE_SSE_USAGE();
987
988	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
989	IEM_MC_AND_LOCAL_U8(bImm, 3);
990	IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm /a_iDword/, uSrc);
991	IEM_MC_ADVANCE_RIP_AND_FINISH();
992	IEM_MC_END();
993	}
994	}
995	}
996
997
998	/* Opcode 0x66 0x0f 0x23 - invalid */
999	/* Opcode 0x66 0x0f 0x24 - invalid */
1000	/* Opcode 0x66 0x0f 0x25 - invalid */
1001	/* Opcode 0x66 0x0f 0x26 - invalid */
1002	/* Opcode 0x66 0x0f 0x27 - invalid */
1003	/* Opcode 0x66 0x0f 0x28 - invalid */
1004	/* Opcode 0x66 0x0f 0x29 - invalid */
1005	/* Opcode 0x66 0x0f 0x2a - invalid */
1006	/* Opcode 0x66 0x0f 0x2b - invalid */
1007	/* Opcode 0x66 0x0f 0x2c - invalid */
1008	/* Opcode 0x66 0x0f 0x2d - invalid */
1009	/* Opcode 0x66 0x0f 0x2e - invalid */
1010	/* Opcode 0x66 0x0f 0x2f - invalid */
1011
1012
1013	/* Opcode 0x66 0x0f 0x30 - invalid */
1014	/* Opcode 0x66 0x0f 0x31 - invalid */
1015	/* Opcode 0x66 0x0f 0x32 - invalid */
1016	/* Opcode 0x66 0x0f 0x33 - invalid */
1017	/* Opcode 0x66 0x0f 0x34 - invalid */
1018	/* Opcode 0x66 0x0f 0x35 - invalid */
1019	/* Opcode 0x66 0x0f 0x36 - invalid */
1020	/* Opcode 0x66 0x0f 0x37 - invalid */
1021	/* Opcode 0x66 0x0f 0x38 - invalid (vex only). */
1022	/* Opcode 0x66 0x0f 0x39 - invalid (vex only). */
1023	/* Opcode 0x66 0x0f 0x3a - invalid */
1024	/* Opcode 0x66 0x0f 0x3b - invalid */
1025	/* Opcode 0x66 0x0f 0x3c - invalid */
1026	/* Opcode 0x66 0x0f 0x3d - invalid */
1027	/* Opcode 0x66 0x0f 0x3e - invalid */
1028	/* Opcode 0x66 0x0f 0x3f - invalid */
1029
1030
1031	/** Opcode 0x66 0x0f 0x40. */
1032	FNIEMOP_DEF(iemOp_dpps_Vx_Wx_Ib)
1033	{
1034	IEMOP_MNEMONIC3(RMI, DPPS, dpps, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1035	return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
1036	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback));
1037	}
1038
1039
1040	/** Opcode 0x66 0x0f 0x41, */
1041	FNIEMOP_DEF(iemOp_dppd_Vdq_Wdq_Ib)
1042	{
1043	IEMOP_MNEMONIC3(RMI, DPPD, dppd, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1044	return FNIEMOP_CALL_1(iemOpCommonSse41Fp_FullFullImm8_To_Full,
1045	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback));
1046	}
1047
1048
1049	/** Opcode 0x66 0x0f 0x42. */
1050	FNIEMOP_DEF(iemOp_mpsadbw_Vx_Wx_Ib)
1051	{
1052	IEMOP_MNEMONIC3(RMI, MPSADBW, mpsadbw, Vx, Wx, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1053	return FNIEMOP_CALL_1(iemOpCommonSse41_FullFullImm8_To_Full,
1054	IEM_SELECT_HOST_OR_FALLBACK(fSse41, iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback));
1055	}
1056
1057
1058	/* Opcode 0x66 0x0f 0x43 - invalid */
1059
1060
1061	/** Opcode 0x66 0x0f 0x44. */
1062	FNIEMOP_DEF(iemOp_pclmulqdq_Vdq_Wdq_Ib)
1063	{
1064	IEMOP_MNEMONIC3(RMI, PCLMULQDQ, pclmulqdq, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1065
1066	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1067	if (IEM_IS_MODRM_REG_MODE(bRm))
1068	{
1069	/*
1070	* Register, register.
1071	*/
1072	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1073	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1074	IEM_MC_BEGIN(3, 0);
1075	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1076	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1077	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
1078	IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT();
1079	IEM_MC_PREPARE_SSE_USAGE();
1080	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1081	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1082	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
1083	iemAImpl_pclmulqdq_u128,
1084	iemAImpl_pclmulqdq_u128_fallback),
1085	puDst, puSrc, bImmArg);
1086	IEM_MC_ADVANCE_RIP_AND_FINISH();
1087	IEM_MC_END();
1088	}
1089	else
1090	{
1091	/*
1092	* Register, memory.
1093	*/
1094	IEM_MC_BEGIN(3, 2);
1095	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1096	IEM_MC_LOCAL(RTUINT128U, uSrc);
1097	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1098	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1099
1100	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1101	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1102	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
1103	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1104	IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT();
1105	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1106
1107	IEM_MC_PREPARE_SSE_USAGE();
1108	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1109	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fPclMul,
1110	iemAImpl_pclmulqdq_u128,
1111	iemAImpl_pclmulqdq_u128_fallback),
1112	puDst, puSrc, bImmArg);
1113
1114	IEM_MC_ADVANCE_RIP_AND_FINISH();
1115	IEM_MC_END();
1116	}
1117	}
1118
1119
1120	/* Opcode 0x66 0x0f 0x45 - invalid */
1121	/* Opcode 0x66 0x0f 0x46 - invalid (vex only) */
1122	/* Opcode 0x66 0x0f 0x47 - invalid */
1123	/* Opcode 0x66 0x0f 0x48 - invalid */
1124	/* Opcode 0x66 0x0f 0x49 - invalid */
1125	/* Opcode 0x66 0x0f 0x4a - invalid (vex only). */
1126	/* Opcode 0x66 0x0f 0x4b - invalid (vex only). */
1127	/* Opcode 0x66 0x0f 0x4c - invalid (vex only). */
1128	/* Opcode 0x66 0x0f 0x4d - invalid */
1129	/* Opcode 0x66 0x0f 0x4e - invalid */
1130	/* Opcode 0x66 0x0f 0x4f - invalid */
1131
1132
1133	/* Opcode 0x66 0x0f 0x50 - invalid */
1134	/* Opcode 0x66 0x0f 0x51 - invalid */
1135	/* Opcode 0x66 0x0f 0x52 - invalid */
1136	/* Opcode 0x66 0x0f 0x53 - invalid */
1137	/* Opcode 0x66 0x0f 0x54 - invalid */
1138	/* Opcode 0x66 0x0f 0x55 - invalid */
1139	/* Opcode 0x66 0x0f 0x56 - invalid */
1140	/* Opcode 0x66 0x0f 0x57 - invalid */
1141	/* Opcode 0x66 0x0f 0x58 - invalid */
1142	/* Opcode 0x66 0x0f 0x59 - invalid */
1143	/* Opcode 0x66 0x0f 0x5a - invalid */
1144	/* Opcode 0x66 0x0f 0x5b - invalid */
1145	/* Opcode 0x66 0x0f 0x5c - invalid */
1146	/* Opcode 0x66 0x0f 0x5d - invalid */
1147	/* Opcode 0x66 0x0f 0x5e - invalid */
1148	/* Opcode 0x66 0x0f 0x5f - invalid */
1149
1150
1151	/** Opcode 0x66 0x0f 0x60. */
1152	FNIEMOP_DEF(iemOp_pcmpestrm_Vdq_Wdq_Ib)
1153	{
1154	IEMOP_MNEMONIC3(RMI, PCMPESTRM, pcmpestrm, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1155
1156	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1157	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1158	{
1159	if (IEM_IS_MODRM_REG_MODE(bRm))
1160	{
1161	/*
1162	* Register, register.
1163	*/
1164	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1165	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1166	IEM_MC_BEGIN(4, 1);
1167	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1168	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1169	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1170	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1171	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1172	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1173	IEM_MC_PREPARE_SSE_USAGE();
1174	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1175	IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1176	IEM_MC_FETCH_GREG_U64(Src.u64Rax, X86_GREG_xAX);
1177	IEM_MC_FETCH_GREG_U64(Src.u64Rdx, X86_GREG_xDX);
1178	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1179	IEM_MC_REF_EFLAGS(pEFlags);
1180	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1181	iemAImpl_pcmpestrm_u128,
1182	iemAImpl_pcmpestrm_u128_fallback),
1183	puDst, pEFlags, pSrc, bImmArg);
1184	IEM_MC_ADVANCE_RIP_AND_FINISH();
1185	IEM_MC_END();
1186	}
1187	else
1188	{
1189	/*
1190	* Register, memory.
1191	*/
1192	IEM_MC_BEGIN(4, 3);
1193	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1194	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1195	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1196	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1197	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1198
1199	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1200	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1201	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1202	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1203	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1204	IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1205
1206	IEM_MC_PREPARE_SSE_USAGE();
1207	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1208	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1209	IEM_MC_FETCH_GREG_U64(Src.u64Rax, X86_GREG_xAX);
1210	IEM_MC_FETCH_GREG_U64(Src.u64Rdx, X86_GREG_xDX);
1211
1212	IEM_MC_REF_EFLAGS(pEFlags);
1213	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1214	iemAImpl_pcmpestri_u128,
1215	iemAImpl_pcmpestri_u128_fallback),
1216	pu32Ecx, pEFlags, pSrc, bImmArg);
1217	IEM_MC_ADVANCE_RIP_AND_FINISH();
1218	IEM_MC_END();
1219	}
1220	}
1221	else
1222	{
1223	if (IEM_IS_MODRM_REG_MODE(bRm))
1224	{
1225	/*
1226	* Register, register.
1227	*/
1228	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1229	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1230	IEM_MC_BEGIN(4, 1);
1231	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1232	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1233	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1234	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1235	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1236	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1237	IEM_MC_PREPARE_SSE_USAGE();
1238	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1239	IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1240	IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rax, X86_GREG_xAX);
1241	IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rdx, X86_GREG_xDX);
1242	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1243	IEM_MC_REF_EFLAGS(pEFlags);
1244	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1245	iemAImpl_pcmpestrm_u128,
1246	iemAImpl_pcmpestrm_u128_fallback),
1247	puDst, pEFlags, pSrc, bImmArg);
1248	IEM_MC_ADVANCE_RIP_AND_FINISH();
1249	IEM_MC_END();
1250	}
1251	else
1252	{
1253	/*
1254	* Register, memory.
1255	*/
1256	IEM_MC_BEGIN(4, 3);
1257	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1258	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1259	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1260	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1261	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1262
1263	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1264	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1265	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1266	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1267	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1268	IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1269
1270	IEM_MC_PREPARE_SSE_USAGE();
1271	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1272	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1273	IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rax, X86_GREG_xAX);
1274	IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rdx, X86_GREG_xDX);
1275	IEM_MC_REF_EFLAGS(pEFlags);
1276	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1277	iemAImpl_pcmpestri_u128,
1278	iemAImpl_pcmpestri_u128_fallback),
1279	pu32Ecx, pEFlags, pSrc, bImmArg);
1280	IEM_MC_ADVANCE_RIP_AND_FINISH();
1281	IEM_MC_END();
1282	}
1283	}
1284	}
1285
1286
1287	/** Opcode 0x66 0x0f 0x61, */
1288	FNIEMOP_DEF(iemOp_pcmpestri_Vdq_Wdq_Ib)
1289	{
1290	IEMOP_MNEMONIC3(RMI, PCMPESTRI, pcmpestri, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1291
1292	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1293	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1294	{
1295	if (IEM_IS_MODRM_REG_MODE(bRm))
1296	{
1297	/*
1298	* Register, register.
1299	*/
1300	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1301	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1302	IEM_MC_BEGIN(4, 1);
1303	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1304	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1305	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1306	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1307	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1308	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1309	IEM_MC_PREPARE_SSE_USAGE();
1310	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1311	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1312	IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1313	IEM_MC_FETCH_GREG_U64(Src.u64Rax, X86_GREG_xAX);
1314	IEM_MC_FETCH_GREG_U64(Src.u64Rdx, X86_GREG_xDX);
1315	IEM_MC_REF_EFLAGS(pEFlags);
1316	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1317	iemAImpl_pcmpestri_u128,
1318	iemAImpl_pcmpestri_u128_fallback),
1319	pu32Ecx, pEFlags, pSrc, bImmArg);
1320	/** @todo testcase: High dword of RCX cleared? */
1321	IEM_MC_ADVANCE_RIP_AND_FINISH();
1322	IEM_MC_END();
1323	}
1324	else
1325	{
1326	/*
1327	* Register, memory.
1328	*/
1329	IEM_MC_BEGIN(4, 3);
1330	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1331	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1332	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1333	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1334	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1335
1336	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1337	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1338	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1339	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1340	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1341	IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1342
1343	IEM_MC_PREPARE_SSE_USAGE();
1344	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1345	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1346	IEM_MC_FETCH_GREG_U64(Src.u64Rax, X86_GREG_xAX);
1347	IEM_MC_FETCH_GREG_U64(Src.u64Rdx, X86_GREG_xDX);
1348	IEM_MC_REF_EFLAGS(pEFlags);
1349	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1350	iemAImpl_pcmpestri_u128,
1351	iemAImpl_pcmpestri_u128_fallback),
1352	pu32Ecx, pEFlags, pSrc, bImmArg);
1353	/** @todo testcase: High dword of RCX cleared? */
1354	IEM_MC_ADVANCE_RIP_AND_FINISH();
1355	IEM_MC_END();
1356	}
1357	}
1358	else
1359	{
1360	if (IEM_IS_MODRM_REG_MODE(bRm))
1361	{
1362	/*
1363	* Register, register.
1364	*/
1365	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1366	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1367	IEM_MC_BEGIN(4, 1);
1368	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1369	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1370	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1371	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1372	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1373	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1374	IEM_MC_PREPARE_SSE_USAGE();
1375	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1376	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1377	IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1378	IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rax, X86_GREG_xAX);
1379	IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rdx, X86_GREG_xDX);
1380	IEM_MC_REF_EFLAGS(pEFlags);
1381	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1382	iemAImpl_pcmpestri_u128,
1383	iemAImpl_pcmpestri_u128_fallback),
1384	pu32Ecx, pEFlags, pSrc, bImmArg);
1385	/** @todo testcase: High dword of RCX cleared? */
1386	IEM_MC_ADVANCE_RIP_AND_FINISH();
1387	IEM_MC_END();
1388	}
1389	else
1390	{
1391	/*
1392	* Register, memory.
1393	*/
1394	IEM_MC_BEGIN(4, 3);
1395	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1396	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1397	IEM_MC_LOCAL(IEMPCMPESTRXSRC, Src);
1398	IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2);
1399	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1400
1401	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1402	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1403	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1404	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1405	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1406	IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1407
1408	IEM_MC_PREPARE_SSE_USAGE();
1409	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1410	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1411	IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rax, X86_GREG_xAX);
1412	IEM_MC_FETCH_GREG_U32_SX_U64(Src.u64Rdx, X86_GREG_xDX);
1413	IEM_MC_REF_EFLAGS(pEFlags);
1414	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1415	iemAImpl_pcmpestri_u128,
1416	iemAImpl_pcmpestri_u128_fallback),
1417	pu32Ecx, pEFlags, pSrc, bImmArg);
1418	/** @todo testcase: High dword of RCX cleared? */
1419	IEM_MC_ADVANCE_RIP_AND_FINISH();
1420	IEM_MC_END();
1421	}
1422	}
1423	}
1424
1425
1426	/** Opcode 0x66 0x0f 0x62. */
1427	FNIEMOP_DEF(iemOp_pcmpistrm_Vdq_Wdq_Ib)
1428	{
1429	IEMOP_MNEMONIC3(RMI, PCMPISTRM, pcmpistrm, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1430
1431	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1432	if (IEM_IS_MODRM_REG_MODE(bRm))
1433	{
1434	/*
1435	* Register, register.
1436	*/
1437	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1438	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1439	IEM_MC_BEGIN(4, 1);
1440	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1441	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1442	IEM_MC_LOCAL(IEMPCMPISTRXSRC, Src);
1443	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2);
1444	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1445	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1446	IEM_MC_PREPARE_SSE_USAGE();
1447	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1448	IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1449	IEM_MC_REF_XREG_U128(puDst, 0 /xmm0/);
1450	IEM_MC_REF_EFLAGS(pEFlags);
1451	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1452	iemAImpl_pcmpistrm_u128,
1453	iemAImpl_pcmpistrm_u128_fallback),
1454	puDst, pEFlags, pSrc, bImmArg);
1455	IEM_MC_ADVANCE_RIP_AND_FINISH();
1456	IEM_MC_END();
1457	}
1458	else
1459	{
1460	/*
1461	* Register, memory.
1462	*/
1463	IEM_MC_BEGIN(4, 3);
1464	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1465	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1466	IEM_MC_LOCAL(IEMPCMPISTRXSRC, Src);
1467	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2);
1468	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1469
1470	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1471	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1472	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1473	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1474	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1475	IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1476
1477	IEM_MC_PREPARE_SSE_USAGE();
1478	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1479	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1480	IEM_MC_REF_EFLAGS(pEFlags);
1481	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1482	iemAImpl_pcmpistri_u128,
1483	iemAImpl_pcmpistri_u128_fallback),
1484	pu32Ecx, pEFlags, pSrc, bImmArg);
1485	IEM_MC_ADVANCE_RIP_AND_FINISH();
1486	IEM_MC_END();
1487	}
1488	}
1489
1490
1491	/** Opcode 0x66 0x0f 0x63*/
1492	FNIEMOP_DEF(iemOp_pcmpistri_Vdq_Wdq_Ib)
1493	{
1494	IEMOP_MNEMONIC3(RMI, PCMPISTRI, pcmpistri, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1495
1496	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1497	if (IEM_IS_MODRM_REG_MODE(bRm))
1498	{
1499	/*
1500	* Register, register.
1501	*/
1502	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1503	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1504	IEM_MC_BEGIN(4, 1);
1505	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1506	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1507	IEM_MC_LOCAL(IEMPCMPISTRXSRC, Src);
1508	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2);
1509	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1510	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1511	IEM_MC_PREPARE_SSE_USAGE();
1512	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1513	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1514	IEM_MC_FETCH_XREG_U128(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1515	IEM_MC_REF_EFLAGS(pEFlags);
1516	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1517	iemAImpl_pcmpistri_u128,
1518	iemAImpl_pcmpistri_u128_fallback),
1519	pu32Ecx, pEFlags, pSrc, bImmArg);
1520	/** @todo testcase: High dword of RCX cleared? */
1521	IEM_MC_ADVANCE_RIP_AND_FINISH();
1522	IEM_MC_END();
1523	}
1524	else
1525	{
1526	/*
1527	* Register, memory.
1528	*/
1529	IEM_MC_BEGIN(4, 3);
1530	IEM_MC_ARG(uint32_t *, pu32Ecx, 0);
1531	IEM_MC_ARG(uint32_t *, pEFlags, 1);
1532	IEM_MC_LOCAL(IEMPCMPISTRXSRC, Src);
1533	IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2);
1534	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1535
1536	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1537	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1538	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
1539	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1540	IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT();
1541	IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1542
1543	IEM_MC_PREPARE_SSE_USAGE();
1544	IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX);
1545	IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
1546	IEM_MC_REF_EFLAGS(pEFlags);
1547	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fSse42,
1548	iemAImpl_pcmpistri_u128,
1549	iemAImpl_pcmpistri_u128_fallback),
1550	pu32Ecx, pEFlags, pSrc, bImmArg);
1551	/** @todo testcase: High dword of RCX cleared? */
1552	IEM_MC_ADVANCE_RIP_AND_FINISH();
1553	IEM_MC_END();
1554	}
1555	}
1556
1557
1558	/* Opcode 0x66 0x0f 0x64 - invalid */
1559	/* Opcode 0x66 0x0f 0x65 - invalid */
1560	/* Opcode 0x66 0x0f 0x66 - invalid */
1561	/* Opcode 0x66 0x0f 0x67 - invalid */
1562	/* Opcode 0x66 0x0f 0x68 - invalid */
1563	/* Opcode 0x66 0x0f 0x69 - invalid */
1564	/* Opcode 0x66 0x0f 0x6a - invalid */
1565	/* Opcode 0x66 0x0f 0x6b - invalid */
1566	/* Opcode 0x66 0x0f 0x6c - invalid */
1567	/* Opcode 0x66 0x0f 0x6d - invalid */
1568	/* Opcode 0x66 0x0f 0x6e - invalid */
1569	/* Opcode 0x66 0x0f 0x6f - invalid */
1570
1571	/* Opcodes 0x0f 0x70 thru 0x0f 0xb0 are unused. */
1572
1573
1574	/* Opcode 0x0f 0xc0 - invalid */
1575	/* Opcode 0x0f 0xc1 - invalid */
1576	/* Opcode 0x0f 0xc2 - invalid */
1577	/* Opcode 0x0f 0xc3 - invalid */
1578	/* Opcode 0x0f 0xc4 - invalid */
1579	/* Opcode 0x0f 0xc5 - invalid */
1580	/* Opcode 0x0f 0xc6 - invalid */
1581	/* Opcode 0x0f 0xc7 - invalid */
1582	/* Opcode 0x0f 0xc8 - invalid */
1583	/* Opcode 0x0f 0xc9 - invalid */
1584	/* Opcode 0x0f 0xca - invalid */
1585	/* Opcode 0x0f 0xcb - invalid */
1586
1587
1588	/* Opcode 0x0f 0xcc */
1589	FNIEMOP_DEF(iemOp_sha1rnds4_Vdq_Wdq_Ib)
1590	{
1591	IEMOP_MNEMONIC3(RMI, SHA1RNDS4, sha1rnds4, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1592
1593	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1594	if (IEM_IS_MODRM_REG_MODE(bRm))
1595	{
1596	/*
1597	* XMM, XMM, imm8
1598	*/
1599	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1600	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1601	IEM_MC_BEGIN(3, 0);
1602	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1603	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1604	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
1605	IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT();
1606	IEM_MC_PREPARE_SSE_USAGE();
1607	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1608	IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1609	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha,
1610	iemAImpl_sha1rnds4_u128,
1611	iemAImpl_sha1rnds4_u128_fallback),
1612	puDst, puSrc, bImmArg);
1613	IEM_MC_ADVANCE_RIP_AND_FINISH();
1614	IEM_MC_END();
1615	}
1616	else
1617	{
1618	/*
1619	* XMM, [mem128], imm8.
1620	*/
1621	IEM_MC_BEGIN(3, 2);
1622	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1623	IEM_MC_LOCAL(RTUINT128U, uSrc);
1624	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1625	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1626
1627	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1628	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
1629	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 2);
1630	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1631	IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT();
1632	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1633
1634	IEM_MC_PREPARE_SSE_USAGE();
1635	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1636	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha,
1637	iemAImpl_sha1rnds4_u128,
1638	iemAImpl_sha1rnds4_u128_fallback),
1639	puDst, puSrc, bImmArg);
1640	IEM_MC_ADVANCE_RIP_AND_FINISH();
1641	IEM_MC_END();
1642	}
1643	}
1644
1645
1646	/* Opcode 0x0f 0xcd - invalid */
1647	/* Opcode 0x0f 0xce - invalid */
1648	/* Opcode 0x0f 0xcf - invalid */
1649
1650
1651	/* Opcode 0x66 0x0f 0xd0 - invalid */
1652	/* Opcode 0x66 0x0f 0xd1 - invalid */
1653	/* Opcode 0x66 0x0f 0xd2 - invalid */
1654	/* Opcode 0x66 0x0f 0xd3 - invalid */
1655	/* Opcode 0x66 0x0f 0xd4 - invalid */
1656	/* Opcode 0x66 0x0f 0xd5 - invalid */
1657	/* Opcode 0x66 0x0f 0xd6 - invalid */
1658	/* Opcode 0x66 0x0f 0xd7 - invalid */
1659	/* Opcode 0x66 0x0f 0xd8 - invalid */
1660	/* Opcode 0x66 0x0f 0xd9 - invalid */
1661	/* Opcode 0x66 0x0f 0xda - invalid */
1662	/* Opcode 0x66 0x0f 0xdb - invalid */
1663	/* Opcode 0x66 0x0f 0xdc - invalid */
1664	/* Opcode 0x66 0x0f 0xdd - invalid */
1665	/* Opcode 0x66 0x0f 0xde - invalid */
1666
1667
1668	/* Opcode 0x66 0x0f 0xdf - (aeskeygenassist). */
1669	FNIEMOP_DEF(iemOp_aeskeygen_Vdq_Wdq_Ib)
1670	{
1671	IEMOP_MNEMONIC3(RMI, AESKEYGEN, aeskeygen, Vdq, Wdq, Ib, DISOPTYPE_HARMLESS \| DISOPTYPE_X86_SSE, 0);
1672	return FNIEMOP_CALL_1(iemOpCommonAesNi_FullFullImm8_To_Full,
1673	IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback));
1674	}
1675
1676
1677	/* Opcode 0xf2 0x0f 0xf0 - invalid (vex only) */
1678
1679
1680	/**
1681	* Three byte opcode map, first two bytes are 0x0f 0x3a.
1682	* @sa g_apfnVexMap2
1683	*/
1684	IEM_STATIC const PFNIEMOP g_apfnThreeByte0f3a[] =
1685	{
1686	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1687	/* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1688	/* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1689	/* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1690	/* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1691	/* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1692	/* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1693	/* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1694	/* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1695	/* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_roundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1696	/* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_roundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1697	/* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_roundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1698	/* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_roundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1699	/* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_blendps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1700	/* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_blendpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1701	/* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_pblendw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1702	/* 0x0f */ iemOp_palignr_Pq_Qq_Ib, iemOp_palignr_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1703
1704	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1705	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1706	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1707	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1708	/* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_pextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1709	/* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_pextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1710	/* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_pextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1711	/* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_extractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1712	/* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1713	/* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1714	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1715	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1716	/* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1717	/* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1718	/* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1719	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1720
1721	/* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrb_Vdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1722	/* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_insertps_Vdq_UdqMd_Ib,iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1723	/* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_pinsrd_q_Vdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1724	/* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1725	/* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1726	/* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1727	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1728	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1729	/* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1730	/* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1731	/* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1732	/* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1733	/* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1734	/* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1735	/* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1736	/* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1737
1738	/* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1739	/* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1740	/* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1741	/* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1742	/* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1743	/* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1744	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1745	/* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1746	/* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1747	/* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1748	/* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1749	/* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1750	/* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1751	/* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1752	/* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1753	/* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1754
1755	/* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_dpps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1756	/* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_dppd_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1757	/* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_mpsadbw_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1758	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1759	/* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_pclmulqdq_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1760	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1761	/* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1762	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1763	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1764	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1765	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1766	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1767	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1768	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1769	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1770	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1771
1772	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1773	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1774	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1775	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1776	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1777	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1778	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1779	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1780	/* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1781	/* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1782	/* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1783	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1784	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1785	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1786	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1787	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1788
1789	/* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1790	/* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1791	/* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1792	/* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_pcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1793	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1794	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1795	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1796	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1797	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1798	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1799	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1800	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1801	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1802	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1803	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1804	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1805
1806	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1807	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1808	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1809	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1810	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1811	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1812	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1813	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1814	/* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1815	/* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1816	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1817	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1818	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1819	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1820	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1821	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1822
1823	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1824	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1825	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1826	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1827	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1828	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1829	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1830	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1831	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1832	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1833	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1834	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1835	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1836	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1837	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1838	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1839
1840	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1841	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1842	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1843	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1844	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1845	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1846	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1847	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1848	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1849	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1850	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1851	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1852	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1853	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1854	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1855	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1856
1857	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1858	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1859	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1860	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1861	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1862	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1863	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1864	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1865	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1866	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1867	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1868	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1869	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1870	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1871	/* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1872	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1873
1874	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1875	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1876	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1877	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1878	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1879	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1880	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1881	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1882	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1883	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1884	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1885	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1886	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1887	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1888	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1889	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1890
1891	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1892	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1893	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1894	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1895	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1896	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1897	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1898	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1899	/* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1900	/* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1901	/* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1902	/* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1903	/* 0xcc */ iemOp_sha1rnds4_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1904	/* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1905	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1906	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1907
1908	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1909	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1910	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1911	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1912	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1913	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1914	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1915	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1916	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1917	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1918	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1919	/* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1920	/* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1921	/* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1922	/* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1923	/* 0xdf */ iemOp_InvalidNeedRMImm8, iemOp_aeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
1924
1925	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1926	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1927	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1928	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1929	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1930	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1931	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1932	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1933	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1934	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1935	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1936	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1937	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1938	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1939	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1940	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1941
1942	/* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1943	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1944	/* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1945	/* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1946	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1947	/* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1948	/* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1949	/* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1950	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1951	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1952	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1953	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1954	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1955	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1956	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1957	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1958	};
1959	AssertCompile(RT_ELEMENTS(g_apfnThreeByte0f3a) == 1024);
1960
1961	/** @} */
1962

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h@ 99220

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