VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h@ 66921

Last change on this file since 66921 was 66921, checked in by vboxsync, 8 years ago

IEM: Implemented movsd Usd,Hsd,Vsd (VEX.F2.0F 11 mod=3) and movsd Mq,Vsd (VEX.F2.0F 11 mod!=3).
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File size: 129.3 KB
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1/* $Id: IEMAllInstructionsVexMap1.cpp.h 66921 2017-05-16 19:31:36Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstructionsTwoByte0f.cpp.h is a legacy mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2016 Oracle Corporation
11 *
12 * This file is part of VirtualBox Open Source Edition (OSE), as
13 * available from http://www.virtualbox.org. This file is free software;
14 * you can redistribute it and/or modify it under the terms of the GNU
15 * General Public License (GPL) as published by the Free Software
16 * Foundation, in version 2 as it comes in the "COPYING" file of the
17 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19 */
20
21
22/** @name VEX Opcode Map 1
23 * @{
24 */
25
26
27/* Opcode VEX.0F 0x00 - invalid */
28/* Opcode VEX.0F 0x01 - invalid */
29/* Opcode VEX.0F 0x02 - invalid */
30/* Opcode VEX.0F 0x03 - invalid */
31/* Opcode VEX.0F 0x04 - invalid */
32/* Opcode VEX.0F 0x05 - invalid */
33/* Opcode VEX.0F 0x06 - invalid */
34/* Opcode VEX.0F 0x07 - invalid */
35/* Opcode VEX.0F 0x08 - invalid */
36/* Opcode VEX.0F 0x09 - invalid */
37/* Opcode VEX.0F 0x0a - invalid */
38
39/** Opcode VEX.0F 0x0b. */
40FNIEMOP_DEF(iemOp_vud2)
41{
42 IEMOP_MNEMONIC(vud2, "vud2");
43 return IEMOP_RAISE_INVALID_OPCODE();
44}
45
46/* Opcode VEX.0F 0x0c - invalid */
47/* Opcode VEX.0F 0x0d - invalid */
48/* Opcode VEX.0F 0x0e - invalid */
49/* Opcode VEX.0F 0x0f - invalid */
50
51
52/**
53 * @opcode 0x10
54 * @oppfx none
55 * @opcpuid avx
56 * @opgroup og_avx_simdfp_datamove
57 * @opxcpttype 4UA
58 * @optest op1=1 op2=2 -> op1=2
59 * @optest op1=0 op2=-22 -> op1=-22
60 */
61FNIEMOP_DEF(iemOp_vmovups_Vps_Wps)
62{
63 IEMOP_MNEMONIC2(VEX_RM, VMOVUPS, vmovups, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
64 Assert(pVCpu->iem.s.uVexLength <= 1);
65 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
66 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
67 {
68 /*
69 * Register, register.
70 */
71 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
72 IEM_MC_BEGIN(0, 0);
73 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
74 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
75 if (pVCpu->iem.s.uVexLength == 0)
76 IEM_MC_COPY_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
77 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
78 else
79 IEM_MC_COPY_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
80 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
81 IEM_MC_ADVANCE_RIP();
82 IEM_MC_END();
83 }
84 else if (pVCpu->iem.s.uVexLength == 0)
85 {
86 /*
87 * 128-bit: Memory, register.
88 */
89 IEM_MC_BEGIN(0, 2);
90 IEM_MC_LOCAL(RTUINT128U, uSrc);
91 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
92
93 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
94 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
95 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
96 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
97
98 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
99 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
100
101 IEM_MC_ADVANCE_RIP();
102 IEM_MC_END();
103 }
104 else
105 {
106 /*
107 * 256-bit: Memory, register.
108 */
109 IEM_MC_BEGIN(0, 2);
110 IEM_MC_LOCAL(RTUINT256U, uSrc);
111 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
112
113 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
114 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
115 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
116 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
117
118 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
119 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
120
121 IEM_MC_ADVANCE_RIP();
122 IEM_MC_END();
123 }
124 return VINF_SUCCESS;
125}
126
127
128/**
129 * @opcode 0x10
130 * @oppfx 0x66
131 * @opcpuid avx
132 * @opgroup og_avx_simdfp_datamove
133 * @opxcpttype 4UA
134 * @optest op1=1 op2=2 -> op1=2
135 * @optest op1=0 op2=-22 -> op1=-22
136 */
137FNIEMOP_DEF(iemOp_vmovupd_Vpd_Wpd)
138{
139 IEMOP_MNEMONIC2(VEX_RM, VMOVUPD, vmovupd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
140 Assert(pVCpu->iem.s.uVexLength <= 1);
141 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
142 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
143 {
144 /*
145 * Register, register.
146 */
147 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
148 IEM_MC_BEGIN(0, 0);
149 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
150 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
151 if (pVCpu->iem.s.uVexLength == 0)
152 IEM_MC_COPY_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
153 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
154 else
155 IEM_MC_COPY_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
156 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
157 IEM_MC_ADVANCE_RIP();
158 IEM_MC_END();
159 }
160 else if (pVCpu->iem.s.uVexLength == 0)
161 {
162 /*
163 * 128-bit: Memory, register.
164 */
165 IEM_MC_BEGIN(0, 2);
166 IEM_MC_LOCAL(RTUINT128U, uSrc);
167 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
168
169 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
170 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
171 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
172 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
173
174 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
175 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
176
177 IEM_MC_ADVANCE_RIP();
178 IEM_MC_END();
179 }
180 else
181 {
182 /*
183 * 256-bit: Memory, register.
184 */
185 IEM_MC_BEGIN(0, 2);
186 IEM_MC_LOCAL(RTUINT256U, uSrc);
187 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
188
189 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
190 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
191 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
192 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
193
194 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
195 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
196
197 IEM_MC_ADVANCE_RIP();
198 IEM_MC_END();
199 }
200 return VINF_SUCCESS;
201}
202
203
204FNIEMOP_DEF(iemOp_vmovss_Vss_Hss_Wss)
205{
206 Assert(pVCpu->iem.s.uVexLength <= 1);
207 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
208 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
209 {
210 /**
211 * @opcode 0x10
212 * @oppfx 0xf3
213 * @opcodesub 11 mr/reg
214 * @opcpuid avx
215 * @opgroup og_avx_simdfp_datamerge
216 * @opxcpttype 5
217 * @optest op1=1 op2=0 op3=2 -> op1=2
218 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
219 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
220 */
221 IEMOP_MNEMONIC3(VEX_RVM, VMOVSS, vmovss, Vss_WO, HdqCss, Uss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
222 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX();
223 IEM_MC_BEGIN(0, 0);
224
225 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
226 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
227 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
228 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB /*U32*/,
229 pVCpu->iem.s.uVex3rdReg /*Hss*/);
230 IEM_MC_ADVANCE_RIP();
231 IEM_MC_END();
232 }
233 else
234 {
235 /**
236 * @opdone
237 * @opcode 0x10
238 * @oppfx 0xf3
239 * @opcodesub 11 mr/reg
240 * @opcpuid avx
241 * @opgroup og_avx_simdfp_datamove
242 * @opxcpttype 5
243 * @opfunction iemOp_vmovss_Vss_Hss_Wss
244 * @optest op1=1 op2=2 -> op1=2
245 * @optest op1=0 op2=-22 -> op1=-22
246 */
247 IEMOP_MNEMONIC2(VEX_XM, VMOVSS, vmovss, VssZx_WO, Md, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
248 IEM_MC_BEGIN(0, 2);
249 IEM_MC_LOCAL(uint32_t, uSrc);
250 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
251
252 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
253 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
254 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
255 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
256
257 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
258 IEM_MC_STORE_YREG_U32_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
259
260 IEM_MC_ADVANCE_RIP();
261 IEM_MC_END();
262 }
263
264 return VINF_SUCCESS;
265}
266
267
268FNIEMOP_DEF(iemOp_vmovsd_Vsd_Hsd_Wsd)
269{
270 Assert(pVCpu->iem.s.uVexLength <= 1);
271 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
272 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
273 {
274 /**
275 * @opcode 0x10
276 * @oppfx 0xf2
277 * @opcodesub 11 mr/reg
278 * @opcpuid avx
279 * @opgroup og_avx_simdfp_datamerge
280 * @opxcpttype 5
281 * @optest op1=1 op2=0 op3=2 -> op1=2
282 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
283 * @optest op1=3 op2=-1 op3=0x77 ->
284 * op1=0xffffffffffffffff0000000000000077
285 */
286 IEMOP_MNEMONIC3(VEX_RVM, VMOVSD, vmovsd, Vsd_WO, HdqCsd, Usd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
287 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX();
288 IEM_MC_BEGIN(0, 0);
289
290 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
291 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
292 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
293 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB /*U32*/,
294 pVCpu->iem.s.uVex3rdReg /*Hss*/);
295 IEM_MC_ADVANCE_RIP();
296 IEM_MC_END();
297 }
298 else
299 {
300 /**
301 * @opdone
302 * @opcode 0x10
303 * @oppfx 0xf2
304 * @opcodesub 11 mr/reg
305 * @opcpuid avx
306 * @opgroup og_avx_simdfp_datamove
307 * @opxcpttype 5
308 * @opfunction iemOp_vmovsd_Vsd_Hsd_Wsd
309 * @optest op1=1 op2=2 -> op1=2
310 * @optest op1=0 op2=-22 -> op1=-22
311 */
312 IEMOP_MNEMONIC2(VEX_XM, VMOVSD, vmovsd, VsdZx_WO, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
313 IEM_MC_BEGIN(0, 2);
314 IEM_MC_LOCAL(uint64_t, uSrc);
315 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
316
317 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
318 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
319 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
320 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
321
322 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
323 IEM_MC_STORE_YREG_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
324
325 IEM_MC_ADVANCE_RIP();
326 IEM_MC_END();
327 }
328
329 return VINF_SUCCESS;
330}
331
332
333/**
334 * @opcode 0x11
335 * @oppfx none
336 * @opcpuid avx
337 * @opgroup og_avx_simdfp_datamove
338 * @opxcpttype 4UA
339 * @optest op1=1 op2=2 -> op1=2
340 * @optest op1=0 op2=-22 -> op1=-22
341 */
342FNIEMOP_DEF(iemOp_vmovups_Wps_Vps)
343{
344 IEMOP_MNEMONIC2(VEX_MR, VMOVUPS, vmovups, Wps_WO, Vps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
345 Assert(pVCpu->iem.s.uVexLength <= 1);
346 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
347 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
348 {
349 /*
350 * Register, register.
351 */
352 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
353 IEM_MC_BEGIN(0, 0);
354 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
355 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
356 if (pVCpu->iem.s.uVexLength == 0)
357 IEM_MC_COPY_YREG_U128_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
358 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
359 else
360 IEM_MC_COPY_YREG_U256_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
361 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
362 IEM_MC_ADVANCE_RIP();
363 IEM_MC_END();
364 }
365 else if (pVCpu->iem.s.uVexLength == 0)
366 {
367 /*
368 * 128-bit: Memory, register.
369 */
370 IEM_MC_BEGIN(0, 2);
371 IEM_MC_LOCAL(RTUINT128U, uSrc);
372 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
373
374 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
375 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
376 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
377 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
378
379 IEM_MC_FETCH_YREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
380 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
381
382 IEM_MC_ADVANCE_RIP();
383 IEM_MC_END();
384 }
385 else
386 {
387 /*
388 * 256-bit: Memory, register.
389 */
390 IEM_MC_BEGIN(0, 2);
391 IEM_MC_LOCAL(RTUINT256U, uSrc);
392 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
393
394 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
395 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
396 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
397 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
398
399 IEM_MC_FETCH_YREG_U256(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
400 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
401
402 IEM_MC_ADVANCE_RIP();
403 IEM_MC_END();
404 }
405 return VINF_SUCCESS;
406}
407
408
409/**
410 * @opcode 0x11
411 * @oppfx 0x66
412 * @opcpuid avx
413 * @opgroup og_avx_simdfp_datamove
414 * @opxcpttype 4UA
415 * @optest op1=1 op2=2 -> op1=2
416 * @optest op1=0 op2=-22 -> op1=-22
417 */
418FNIEMOP_DEF(iemOp_vmovupd_Wpd_Vpd)
419{
420 IEMOP_MNEMONIC2(VEX_MR, VMOVUPD, vmovupd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
421 Assert(pVCpu->iem.s.uVexLength <= 1);
422 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
423 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
424 {
425 /*
426 * Register, register.
427 */
428 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
429 IEM_MC_BEGIN(0, 0);
430 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
431 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
432 if (pVCpu->iem.s.uVexLength == 0)
433 IEM_MC_COPY_YREG_U128_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
434 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
435 else
436 IEM_MC_COPY_YREG_U256_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
437 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
438 IEM_MC_ADVANCE_RIP();
439 IEM_MC_END();
440 }
441 else if (pVCpu->iem.s.uVexLength == 0)
442 {
443 /*
444 * 128-bit: Memory, register.
445 */
446 IEM_MC_BEGIN(0, 2);
447 IEM_MC_LOCAL(RTUINT128U, uSrc);
448 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
449
450 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
451 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
452 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
453 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
454
455 IEM_MC_FETCH_YREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
456 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
457
458 IEM_MC_ADVANCE_RIP();
459 IEM_MC_END();
460 }
461 else
462 {
463 /*
464 * 256-bit: Memory, register.
465 */
466 IEM_MC_BEGIN(0, 2);
467 IEM_MC_LOCAL(RTUINT256U, uSrc);
468 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
469
470 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
471 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
472 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
473 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
474
475 IEM_MC_FETCH_YREG_U256(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
476 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
477
478 IEM_MC_ADVANCE_RIP();
479 IEM_MC_END();
480 }
481 return VINF_SUCCESS;
482}
483
484
485FNIEMOP_DEF(iemOp_vmovss_Wss_Hss_Vss)
486{
487 Assert(pVCpu->iem.s.uVexLength <= 1);
488 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
489 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
490 {
491 /**
492 * @opcode 0x11
493 * @oppfx 0xf3
494 * @opcodesub 11 mr/reg
495 * @opcpuid avx
496 * @opgroup og_avx_simdfp_datamerge
497 * @opxcpttype 5
498 * @optest op1=1 op2=0 op3=2 -> op1=2
499 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
500 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
501 */
502 IEMOP_MNEMONIC3(VEX_MVR, VMOVSS, vmovss, Uss_WO, HdqCss, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
503 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX();
504 IEM_MC_BEGIN(0, 0);
505
506 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
507 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
508 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB /*U32*/,
509 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
510 pVCpu->iem.s.uVex3rdReg /*Hss*/);
511 IEM_MC_ADVANCE_RIP();
512 IEM_MC_END();
513 }
514 else
515 {
516 /**
517 * @opdone
518 * @opcode 0x11
519 * @oppfx 0xf3
520 * @opcodesub 11 mr/reg
521 * @opcpuid avx
522 * @opgroup og_avx_simdfp_datamove
523 * @opxcpttype 5
524 * @opfunction iemOp_vmovss_Vss_Hss_Wss
525 * @optest op1=1 op2=2 -> op1=2
526 * @optest op1=0 op2=-22 -> op1=-22
527 */
528 IEMOP_MNEMONIC2(VEX_MR, VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
529 IEM_MC_BEGIN(0, 2);
530 IEM_MC_LOCAL(uint32_t, uSrc);
531 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
532
533 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
534 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
535 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
536 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
537
538 IEM_MC_FETCH_YREG_U32(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
539 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
540
541 IEM_MC_ADVANCE_RIP();
542 IEM_MC_END();
543 }
544
545 return VINF_SUCCESS;
546}
547
548
549FNIEMOP_DEF(iemOp_vmovsd_Wsd_Hsd_Vsd)
550{
551 Assert(pVCpu->iem.s.uVexLength <= 1);
552 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
553 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
554 {
555 /**
556 * @opcode 0x11
557 * @oppfx 0xf2
558 * @opcodesub 11 mr/reg
559 * @opcpuid avx
560 * @opgroup og_avx_simdfp_datamerge
561 * @opxcpttype 5
562 * @optest op1=1 op2=0 op3=2 -> op1=2
563 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
564 * @optest op1=3 op2=-1 op3=0x77 ->
565 * op1=0xffffffffffffffff0000000000000077
566 */
567 IEMOP_MNEMONIC3(VEX_MVR, VMOVSD, vmovsd, Usd_WO, HdqCsd, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
568 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX();
569 IEM_MC_BEGIN(0, 0);
570
571 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
572 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
573 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
574 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
575 pVCpu->iem.s.uVex3rdReg /*Hss*/);
576 IEM_MC_ADVANCE_RIP();
577 IEM_MC_END();
578 }
579 else
580 {
581 /**
582 * @opdone
583 * @opcode 0x11
584 * @oppfx 0xf2
585 * @opcodesub 11 mr/reg
586 * @opcpuid avx
587 * @opgroup og_avx_simdfp_datamove
588 * @opxcpttype 5
589 * @opfunction iemOp_vmovsd_Wsd_Hsd_Vsd
590 * @optest op1=1 op2=2 -> op1=2
591 * @optest op1=0 op2=-22 -> op1=-22
592 */
593 IEMOP_MNEMONIC2(VEX_MR, VMOVSD, vmovsd, Mq_WO, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
594 IEM_MC_BEGIN(0, 2);
595 IEM_MC_LOCAL(uint64_t, uSrc);
596 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
597
598 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
599 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV();
600 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
601 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
602
603 IEM_MC_FETCH_YREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
604 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
605
606 IEM_MC_ADVANCE_RIP();
607 IEM_MC_END();
608 }
609
610 return VINF_SUCCESS;
611}
612
613
614FNIEMOP_STUB(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps);
615//FNIEMOP_DEF(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps)
616//{
617// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
618// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
619// {
620// /**
621// * @ opcode 0x12
622// * @ opcodesub 11 mr/reg
623// * @ oppfx none
624// * @ opcpuid sse
625// * @ opgroup og_sse_simdfp_datamove
626// * @ opxcpttype 5
627// * @ optest op1=1 op2=2 -> op1=2
628// * @ optest op1=0 op2=-42 -> op1=-42
629// */
630// IEMOP_MNEMONIC2(RM_REG, VMOVHLPS, vmovhlps, Vq, UqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
631//
632// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
633// IEM_MC_BEGIN(0, 1);
634// IEM_MC_LOCAL(uint64_t, uSrc);
635//
636// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
637// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
638// IEM_MC_FETCH_XREG_HI_U64(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
639// IEM_MC_STORE_XREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
640//
641// IEM_MC_ADVANCE_RIP();
642// IEM_MC_END();
643// }
644// else
645// {
646// /**
647// * @ opdone
648// * @ opcode 0x12
649// * @ opcodesub !11 mr/reg
650// * @ oppfx none
651// * @ opcpuid sse
652// * @ opgroup og_sse_simdfp_datamove
653// * @ opxcpttype 5
654// * @ optest op1=1 op2=2 -> op1=2
655// * @ optest op1=0 op2=-42 -> op1=-42
656// * @ opfunction iemOp_vmovlps_Vq_Hq_Mq__vmovhlps
657// */
658// IEMOP_MNEMONIC2(RM_MEM, VMOVLPS, vmovlps, Vq, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
659//
660// IEM_MC_BEGIN(0, 2);
661// IEM_MC_LOCAL(uint64_t, uSrc);
662// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
663//
664// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
665// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
666// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
667// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
668//
669// IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
670// IEM_MC_STORE_XREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
671//
672// IEM_MC_ADVANCE_RIP();
673// IEM_MC_END();
674// }
675// return VINF_SUCCESS;
676//}
677
678
679/**
680 * @ opcode 0x12
681 * @ opcodesub !11 mr/reg
682 * @ oppfx 0x66
683 * @ opcpuid sse2
684 * @ opgroup og_sse2_pcksclr_datamove
685 * @ opxcpttype 5
686 * @ optest op1=1 op2=2 -> op1=2
687 * @ optest op1=0 op2=-42 -> op1=-42
688 */
689FNIEMOP_STUB(iemOp_vmovlpd_Vq_Hq_Mq);
690//FNIEMOP_DEF(iemOp_vmovlpd_Vq_Hq_Mq)
691//{
692// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
693// if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
694// {
695// IEMOP_MNEMONIC2(RM_MEM, VMOVLPD, vmovlpd, Vq, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
696//
697// IEM_MC_BEGIN(0, 2);
698// IEM_MC_LOCAL(uint64_t, uSrc);
699// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
700//
701// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
702// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
703// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
704// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
705//
706// IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
707// IEM_MC_STORE_XREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
708//
709// IEM_MC_ADVANCE_RIP();
710// IEM_MC_END();
711// return VINF_SUCCESS;
712// }
713//
714// /**
715// * @ opdone
716// * @ opmnemonic ud660f12m3
717// * @ opcode 0x12
718// * @ opcodesub 11 mr/reg
719// * @ oppfx 0x66
720// * @ opunused immediate
721// * @ opcpuid sse
722// * @ optest ->
723// */
724// return IEMOP_RAISE_INVALID_OPCODE();
725//}
726
727
728/**
729 * @ opcode 0x12
730 * @ oppfx 0xf3
731 * @ opcpuid sse3
732 * @ opgroup og_sse3_pcksclr_datamove
733 * @ opxcpttype 4
734 * @ optest op1=-1 op2=0xdddddddd00000002eeeeeeee00000001 ->
735 * op1=0x00000002000000020000000100000001
736 */
737FNIEMOP_STUB(iemOp_vmovsldup_Vx_Wx);
738//FNIEMOP_DEF(iemOp_vmovsldup_Vx_Wx)
739//{
740// IEMOP_MNEMONIC2(RM, VMOVSLDUP, vmovsldup, Vdq, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
741// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
742// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
743// {
744// /*
745// * Register, register.
746// */
747// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
748// IEM_MC_BEGIN(2, 0);
749// IEM_MC_ARG(PRTUINT128U, puDst, 0);
750// IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
751//
752// IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
753// IEM_MC_PREPARE_SSE_USAGE();
754//
755// IEM_MC_REF_XREG_U128_CONST(puSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
756// IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
757// IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
758//
759// IEM_MC_ADVANCE_RIP();
760// IEM_MC_END();
761// }
762// else
763// {
764// /*
765// * Register, memory.
766// */
767// IEM_MC_BEGIN(2, 2);
768// IEM_MC_LOCAL(RTUINT128U, uSrc);
769// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
770// IEM_MC_ARG(PRTUINT128U, puDst, 0);
771// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
772//
773// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
774// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
775// IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
776// IEM_MC_PREPARE_SSE_USAGE();
777//
778// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
779// IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
780// IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
781//
782// IEM_MC_ADVANCE_RIP();
783// IEM_MC_END();
784// }
785// return VINF_SUCCESS;
786//}
787
788
789/**
790 * @ opcode 0x12
791 * @ oppfx 0xf2
792 * @ opcpuid sse3
793 * @ opgroup og_sse3_pcksclr_datamove
794 * @ opxcpttype 5
795 * @ optest op1=-1 op2=0xddddddddeeeeeeee2222222211111111 ->
796 * op1=0x22222222111111112222222211111111
797 */
798FNIEMOP_STUB(iemOp_vmovddup_Vx_Wx);
799//FNIEMOP_DEF(iemOp_vmovddup_Vx_Wx)
800//{
801// IEMOP_MNEMONIC2(RM, VMOVDDUP, vmovddup, Vdq, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
802// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
803// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
804// {
805// /*
806// * Register, register.
807// */
808// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
809// IEM_MC_BEGIN(2, 0);
810// IEM_MC_ARG(PRTUINT128U, puDst, 0);
811// IEM_MC_ARG(uint64_t, uSrc, 1);
812//
813// IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
814// IEM_MC_PREPARE_SSE_USAGE();
815//
816// IEM_MC_FETCH_XREG_U64(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
817// IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
818// IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
819//
820// IEM_MC_ADVANCE_RIP();
821// IEM_MC_END();
822// }
823// else
824// {
825// /*
826// * Register, memory.
827// */
828// IEM_MC_BEGIN(2, 2);
829// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
830// IEM_MC_ARG(PRTUINT128U, puDst, 0);
831// IEM_MC_ARG(uint64_t, uSrc, 1);
832//
833// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
834// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
835// IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
836// IEM_MC_PREPARE_SSE_USAGE();
837//
838// IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
839// IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
840// IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
841//
842// IEM_MC_ADVANCE_RIP();
843// IEM_MC_END();
844// }
845// return VINF_SUCCESS;
846//}
847
848
849/** Opcode VEX.0F 0x13 - vmovlps Mq, Vq */
850FNIEMOP_STUB(iemOp_vmovlps_Mq_Vq);
851
852/** Opcode VEX.66.0F 0x13 - vmovlpd Mq, Vq */
853FNIEMOP_STUB(iemOp_vmovlpd_Mq_Vq);
854//FNIEMOP_DEF(iemOp_vmovlpd_Mq_Vq)
855//{
856// IEMOP_MNEMONIC(vmovlpd_Mq_Vq, "movlpd Mq,Vq");
857// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
858// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
859// {
860//#if 0
861// /*
862// * Register, register.
863// */
864// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
865// IEM_MC_BEGIN(0, 1);
866// IEM_MC_LOCAL(uint64_t, uSrc);
867// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
868// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
869// IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
870// IEM_MC_STORE_XREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uSrc);
871// IEM_MC_ADVANCE_RIP();
872// IEM_MC_END();
873//#else
874// return IEMOP_RAISE_INVALID_OPCODE();
875//#endif
876// }
877// else
878// {
879// /*
880// * Memory, register.
881// */
882// IEM_MC_BEGIN(0, 2);
883// IEM_MC_LOCAL(uint64_t, uSrc);
884// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
885//
886// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
887// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
888// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
889// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
890//
891// IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
892// IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
893//
894// IEM_MC_ADVANCE_RIP();
895// IEM_MC_END();
896// }
897// return VINF_SUCCESS;
898//}
899
900/* Opcode VEX.F3.0F 0x13 - invalid */
901/* Opcode VEX.F2.0F 0x13 - invalid */
902
903/** Opcode VEX.0F 0x14 - vunpcklps Vx, Hx, Wx*/
904FNIEMOP_STUB(iemOp_vunpcklps_Vx_Hx_Wx);
905/** Opcode VEX.66.0F 0x14 - vunpcklpd Vx,Hx,Wx */
906FNIEMOP_STUB(iemOp_vunpcklpd_Vx_Hx_Wx);
907/* Opcode VEX.F3.0F 0x14 - invalid */
908/* Opcode VEX.F2.0F 0x14 - invalid */
909/** Opcode VEX.0F 0x15 - vunpckhps Vx, Hx, Wx */
910FNIEMOP_STUB(iemOp_vunpckhps_Vx_Hx_Wx);
911/** Opcode VEX.66.0F 0x15 - vunpckhpd Vx,Hx,Wx */
912FNIEMOP_STUB(iemOp_vunpckhpd_Vx_Hx_Wx);
913/* Opcode VEX.F3.0F 0x15 - invalid */
914/* Opcode VEX.F2.0F 0x15 - invalid */
915/** Opcode VEX.0F 0x16 - vmovhpsv1 Vdq, Hq, Mq vmovlhps Vdq, Hq, Uq */
916FNIEMOP_STUB(iemOp_vmovhpsv1_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq); //NEXT
917/** Opcode VEX.66.0F 0x16 - vmovhpdv1 Vdq, Hq, Mq */
918FNIEMOP_STUB(iemOp_vmovhpdv1_Vdq_Hq_Mq); //NEXT
919/** Opcode VEX.F3.0F 0x16 - vmovshdup Vx, Wx */
920FNIEMOP_STUB(iemOp_vmovshdup_Vx_Wx); //NEXT
921/* Opcode VEX.F2.0F 0x16 - invalid */
922/** Opcode VEX.0F 0x17 - vmovhpsv1 Mq, Vq */
923FNIEMOP_STUB(iemOp_vmovhpsv1_Mq_Vq); //NEXT
924/** Opcode VEX.66.0F 0x17 - vmovhpdv1 Mq, Vq */
925FNIEMOP_STUB(iemOp_vmovhpdv1_Mq_Vq); //NEXT
926/* Opcode VEX.F3.0F 0x17 - invalid */
927/* Opcode VEX.F2.0F 0x17 - invalid */
928
929
930/* Opcode VEX.0F 0x18 - invalid */
931/* Opcode VEX.0F 0x19 - invalid */
932/* Opcode VEX.0F 0x1a - invalid */
933/* Opcode VEX.0F 0x1b - invalid */
934/* Opcode VEX.0F 0x1c - invalid */
935/* Opcode VEX.0F 0x1d - invalid */
936/* Opcode VEX.0F 0x1e - invalid */
937/* Opcode VEX.0F 0x1f - invalid */
938
939/* Opcode VEX.0F 0x20 - invalid */
940/* Opcode VEX.0F 0x21 - invalid */
941/* Opcode VEX.0F 0x22 - invalid */
942/* Opcode VEX.0F 0x23 - invalid */
943/* Opcode VEX.0F 0x24 - invalid */
944/* Opcode VEX.0F 0x25 - invalid */
945/* Opcode VEX.0F 0x26 - invalid */
946/* Opcode VEX.0F 0x27 - invalid */
947
948/** Opcode VEX.0F 0x28 - vmovaps Vps, Wps */
949FNIEMOP_STUB(iemOp_vmovaps_Vps_Wps);
950//FNIEMOP_DEF(iemOp_vmovaps_Vps_Wps)
951//{
952// IEMOP_MNEMONIC(vmovaps_Vps_Wps, "vmovaps Vps,Wps");
953// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
954// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
955// {
956// /*
957// * Register, register.
958// */
959// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
960// IEM_MC_BEGIN(0, 0);
961// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
962// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
963// IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
964// (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
965// IEM_MC_ADVANCE_RIP();
966// IEM_MC_END();
967// }
968// else
969// {
970// /*
971// * Register, memory.
972// */
973// IEM_MC_BEGIN(0, 2);
974// IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
975// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
976//
977// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
978// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
979// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
980// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
981//
982// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
983// IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
984//
985// IEM_MC_ADVANCE_RIP();
986// IEM_MC_END();
987// }
988// return VINF_SUCCESS;
989//}
990
991/** Opcode VEX.66.0F 0x28 - vmovapd Vpd, Wpd */
992FNIEMOP_STUB(iemOp_vmovapd_Vpd_Wpd);
993//FNIEMOP_DEF(iemOp_vmovapd_Vpd_Wpd)
994//{
995// IEMOP_MNEMONIC(vmovapd_Wpd_Wpd, "vmovapd Wpd,Wpd");
996// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
997// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
998// {
999// /*
1000// * Register, register.
1001// */
1002// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1003// IEM_MC_BEGIN(0, 0);
1004// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1005// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1006// IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1007// (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1008// IEM_MC_ADVANCE_RIP();
1009// IEM_MC_END();
1010// }
1011// else
1012// {
1013// /*
1014// * Register, memory.
1015// */
1016// IEM_MC_BEGIN(0, 2);
1017// IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1018// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1019//
1020// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1021// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1022// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1023// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1024//
1025// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1026// IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1027//
1028// IEM_MC_ADVANCE_RIP();
1029// IEM_MC_END();
1030// }
1031// return VINF_SUCCESS;
1032//}
1033
1034/* Opcode VEX.F3.0F 0x28 - invalid */
1035/* Opcode VEX.F2.0F 0x28 - invalid */
1036
1037/** Opcode VEX.0F 0x29 - vmovaps Wps, Vps */
1038FNIEMOP_STUB(iemOp_vmovaps_Wps_Vps);
1039//FNIEMOP_DEF(iemOp_vmovaps_Wps_Vps)
1040//{
1041// IEMOP_MNEMONIC(vmovaps_Wps_Vps, "vmovaps Wps,Vps");
1042// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1043// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1044// {
1045// /*
1046// * Register, register.
1047// */
1048// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1049// IEM_MC_BEGIN(0, 0);
1050// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1051// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1052// IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
1053// ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1054// IEM_MC_ADVANCE_RIP();
1055// IEM_MC_END();
1056// }
1057// else
1058// {
1059// /*
1060// * Memory, register.
1061// */
1062// IEM_MC_BEGIN(0, 2);
1063// IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1064// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1065//
1066// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1067// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1068// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1069// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1070//
1071// IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1072// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1073//
1074// IEM_MC_ADVANCE_RIP();
1075// IEM_MC_END();
1076// }
1077// return VINF_SUCCESS;
1078//}
1079
1080/** Opcode VEX.66.0F 0x29 - vmovapd Wpd,Vpd */
1081FNIEMOP_STUB(iemOp_vmovapd_Wpd_Vpd);
1082//FNIEMOP_DEF(iemOp_vmovapd_Wpd_Vpd)
1083//{
1084// IEMOP_MNEMONIC(vmovapd_Wpd_Vpd, "movapd Wpd,Vpd");
1085// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1086// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1087// {
1088// /*
1089// * Register, register.
1090// */
1091// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1092// IEM_MC_BEGIN(0, 0);
1093// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1094// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1095// IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
1096// ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1097// IEM_MC_ADVANCE_RIP();
1098// IEM_MC_END();
1099// }
1100// else
1101// {
1102// /*
1103// * Memory, register.
1104// */
1105// IEM_MC_BEGIN(0, 2);
1106// IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1107// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1108//
1109// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1110// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1111// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1112// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1113//
1114// IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1115// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1116//
1117// IEM_MC_ADVANCE_RIP();
1118// IEM_MC_END();
1119// }
1120// return VINF_SUCCESS;
1121//}
1122
1123/* Opcode VEX.F3.0F 0x29 - invalid */
1124/* Opcode VEX.F2.0F 0x29 - invalid */
1125
1126
1127/** Opcode VEX.0F 0x2a - invalid */
1128/** Opcode VEX.66.0F 0x2a - invalid */
1129/** Opcode VEX.F3.0F 0x2a - vcvtsi2ss Vss, Hss, Ey */
1130FNIEMOP_STUB(iemOp_vcvtsi2ss_Vss_Hss_Ey);
1131/** Opcode VEX.F2.0F 0x2a - vcvtsi2sd Vsd, Hsd, Ey */
1132FNIEMOP_STUB(iemOp_vcvtsi2sd_Vsd_Hsd_Ey);
1133
1134
1135/** Opcode VEX.0F 0x2b - vmovntps Mps, Vps */
1136FNIEMOP_STUB(iemOp_vmovntps_Mps_Vps);
1137//FNIEMOP_DEF(iemOp_vmovntps_Mps_Vps)
1138//{
1139// IEMOP_MNEMONIC(vmovntps_Mps_Vps, "movntps Mps,Vps");
1140// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1141// if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1142// {
1143// /*
1144// * memory, register.
1145// */
1146// IEM_MC_BEGIN(0, 2);
1147// IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1148// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1149//
1150// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1151// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1152// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1153// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1154//
1155// IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1156// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1157//
1158// IEM_MC_ADVANCE_RIP();
1159// IEM_MC_END();
1160// }
1161// /* The register, register encoding is invalid. */
1162// else
1163// return IEMOP_RAISE_INVALID_OPCODE();
1164// return VINF_SUCCESS;
1165//}
1166
1167/** Opcode VEX.66.0F 0x2b - vmovntpd Mpd, Vpd */
1168FNIEMOP_STUB(iemOp_vmovntpd_Mpd_Vpd);
1169//FNIEMOP_DEF(iemOp_vmovntpd_Mpd_Vpd)
1170//{
1171// IEMOP_MNEMONIC(vmovntpd_Mpd_Vpd, "movntpd Mdq,Vpd");
1172// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1173// if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1174// {
1175// /*
1176// * memory, register.
1177// */
1178// IEM_MC_BEGIN(0, 2);
1179// IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1180// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1181//
1182// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1183// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1184// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1185// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1186//
1187// IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1188// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1189//
1190// IEM_MC_ADVANCE_RIP();
1191// IEM_MC_END();
1192// }
1193// /* The register, register encoding is invalid. */
1194// else
1195// return IEMOP_RAISE_INVALID_OPCODE();
1196// return VINF_SUCCESS;
1197//}
1198/* Opcode VEX.F3.0F 0x2b - invalid */
1199/* Opcode VEX.F2.0F 0x2b - invalid */
1200
1201
1202/* Opcode VEX.0F 0x2c - invalid */
1203/* Opcode VEX.66.0F 0x2c - invalid */
1204/** Opcode VEX.F3.0F 0x2c - vcvttss2si Gy, Wss */
1205FNIEMOP_STUB(iemOp_vcvttss2si_Gy_Wss);
1206/** Opcode VEX.F2.0F 0x2c - vcvttsd2si Gy, Wsd */
1207FNIEMOP_STUB(iemOp_vcvttsd2si_Gy_Wsd);
1208
1209/* Opcode VEX.0F 0x2d - invalid */
1210/* Opcode VEX.66.0F 0x2d - invalid */
1211/** Opcode VEX.F3.0F 0x2d - vcvtss2si Gy, Wss */
1212FNIEMOP_STUB(iemOp_vcvtss2si_Gy_Wss);
1213/** Opcode VEX.F2.0F 0x2d - vcvtsd2si Gy, Wsd */
1214FNIEMOP_STUB(iemOp_vcvtsd2si_Gy_Wsd);
1215
1216/** Opcode VEX.0F 0x2e - vucomiss Vss, Wss */
1217FNIEMOP_STUB(iemOp_vucomiss_Vss_Wss);
1218/** Opcode VEX.66.0F 0x2e - vucomisd Vsd, Wsd */
1219FNIEMOP_STUB(iemOp_vucomisd_Vsd_Wsd);
1220/* Opcode VEX.F3.0F 0x2e - invalid */
1221/* Opcode VEX.F2.0F 0x2e - invalid */
1222
1223/** Opcode VEX.0F 0x2f - vcomiss Vss, Wss */
1224FNIEMOP_STUB(iemOp_vcomiss_Vss_Wss);
1225/** Opcode VEX.66.0F 0x2f - vcomisd Vsd, Wsd */
1226FNIEMOP_STUB(iemOp_vcomisd_Vsd_Wsd);
1227/* Opcode VEX.F3.0F 0x2f - invalid */
1228/* Opcode VEX.F2.0F 0x2f - invalid */
1229
1230/* Opcode VEX.0F 0x30 - invalid */
1231/* Opcode VEX.0F 0x31 - invalid */
1232/* Opcode VEX.0F 0x32 - invalid */
1233/* Opcode VEX.0F 0x33 - invalid */
1234/* Opcode VEX.0F 0x34 - invalid */
1235/* Opcode VEX.0F 0x35 - invalid */
1236/* Opcode VEX.0F 0x36 - invalid */
1237/* Opcode VEX.0F 0x37 - invalid */
1238/* Opcode VEX.0F 0x38 - invalid */
1239/* Opcode VEX.0F 0x39 - invalid */
1240/* Opcode VEX.0F 0x3a - invalid */
1241/* Opcode VEX.0F 0x3b - invalid */
1242/* Opcode VEX.0F 0x3c - invalid */
1243/* Opcode VEX.0F 0x3d - invalid */
1244/* Opcode VEX.0F 0x3e - invalid */
1245/* Opcode VEX.0F 0x3f - invalid */
1246/* Opcode VEX.0F 0x40 - invalid */
1247/* Opcode VEX.0F 0x41 - invalid */
1248/* Opcode VEX.0F 0x42 - invalid */
1249/* Opcode VEX.0F 0x43 - invalid */
1250/* Opcode VEX.0F 0x44 - invalid */
1251/* Opcode VEX.0F 0x45 - invalid */
1252/* Opcode VEX.0F 0x46 - invalid */
1253/* Opcode VEX.0F 0x47 - invalid */
1254/* Opcode VEX.0F 0x48 - invalid */
1255/* Opcode VEX.0F 0x49 - invalid */
1256/* Opcode VEX.0F 0x4a - invalid */
1257/* Opcode VEX.0F 0x4b - invalid */
1258/* Opcode VEX.0F 0x4c - invalid */
1259/* Opcode VEX.0F 0x4d - invalid */
1260/* Opcode VEX.0F 0x4e - invalid */
1261/* Opcode VEX.0F 0x4f - invalid */
1262
1263/** Opcode VEX.0F 0x50 - vmovmskps Gy, Ups */
1264FNIEMOP_STUB(iemOp_vmovmskps_Gy_Ups);
1265/** Opcode VEX.66.0F 0x50 - vmovmskpd Gy,Upd */
1266FNIEMOP_STUB(iemOp_vmovmskpd_Gy_Upd);
1267/* Opcode VEX.F3.0F 0x50 - invalid */
1268/* Opcode VEX.F2.0F 0x50 - invalid */
1269
1270/** Opcode VEX.0F 0x51 - vsqrtps Vps, Wps */
1271FNIEMOP_STUB(iemOp_vsqrtps_Vps_Wps);
1272/** Opcode VEX.66.0F 0x51 - vsqrtpd Vpd, Wpd */
1273FNIEMOP_STUB(iemOp_vsqrtpd_Vpd_Wpd);
1274/** Opcode VEX.F3.0F 0x51 - vsqrtss Vss, Hss, Wss */
1275FNIEMOP_STUB(iemOp_vsqrtss_Vss_Hss_Wss);
1276/** Opcode VEX.F2.0F 0x51 - vsqrtsd Vsd, Hsd, Wsd */
1277FNIEMOP_STUB(iemOp_vsqrtsd_Vsd_Hsd_Wsd);
1278
1279/** Opcode VEX.0F 0x52 - vrsqrtps Vps, Wps */
1280FNIEMOP_STUB(iemOp_vrsqrtps_Vps_Wps);
1281/* Opcode VEX.66.0F 0x52 - invalid */
1282/** Opcode VEX.F3.0F 0x52 - vrsqrtss Vss, Hss, Wss */
1283FNIEMOP_STUB(iemOp_vrsqrtss_Vss_Hss_Wss);
1284/* Opcode VEX.F2.0F 0x52 - invalid */
1285
1286/** Opcode VEX.0F 0x53 - vrcpps Vps, Wps */
1287FNIEMOP_STUB(iemOp_vrcpps_Vps_Wps);
1288/* Opcode VEX.66.0F 0x53 - invalid */
1289/** Opcode VEX.F3.0F 0x53 - vrcpss Vss, Hss, Wss */
1290FNIEMOP_STUB(iemOp_vrcpss_Vss_Hss_Wss);
1291/* Opcode VEX.F2.0F 0x53 - invalid */
1292
1293/** Opcode VEX.0F 0x54 - vandps Vps, Hps, Wps */
1294FNIEMOP_STUB(iemOp_vandps_Vps_Hps_Wps);
1295/** Opcode VEX.66.0F 0x54 - vandpd Vpd, Hpd, Wpd */
1296FNIEMOP_STUB(iemOp_vandpd_Vpd_Hpd_Wpd);
1297/* Opcode VEX.F3.0F 0x54 - invalid */
1298/* Opcode VEX.F2.0F 0x54 - invalid */
1299
1300/** Opcode VEX.0F 0x55 - vandnps Vps, Hps, Wps */
1301FNIEMOP_STUB(iemOp_vandnps_Vps_Hps_Wps);
1302/** Opcode VEX.66.0F 0x55 - vandnpd Vpd, Hpd, Wpd */
1303FNIEMOP_STUB(iemOp_vandnpd_Vpd_Hpd_Wpd);
1304/* Opcode VEX.F3.0F 0x55 - invalid */
1305/* Opcode VEX.F2.0F 0x55 - invalid */
1306
1307/** Opcode VEX.0F 0x56 - vorps Vps, Hps, Wps */
1308FNIEMOP_STUB(iemOp_vorps_Vps_Hps_Wps);
1309/** Opcode VEX.66.0F 0x56 - vorpd Vpd, Hpd, Wpd */
1310FNIEMOP_STUB(iemOp_vorpd_Vpd_Hpd_Wpd);
1311/* Opcode VEX.F3.0F 0x56 - invalid */
1312/* Opcode VEX.F2.0F 0x56 - invalid */
1313
1314/** Opcode VEX.0F 0x57 - vxorps Vps, Hps, Wps */
1315FNIEMOP_STUB(iemOp_vxorps_Vps_Hps_Wps);
1316/** Opcode VEX.66.0F 0x57 - vxorpd Vpd, Hpd, Wpd */
1317FNIEMOP_STUB(iemOp_vxorpd_Vpd_Hpd_Wpd);
1318/* Opcode VEX.F3.0F 0x57 - invalid */
1319/* Opcode VEX.F2.0F 0x57 - invalid */
1320
1321/** Opcode VEX.0F 0x58 - vaddps Vps, Hps, Wps */
1322FNIEMOP_STUB(iemOp_vaddps_Vps_Hps_Wps);
1323/** Opcode VEX.66.0F 0x58 - vaddpd Vpd, Hpd, Wpd */
1324FNIEMOP_STUB(iemOp_vaddpd_Vpd_Hpd_Wpd);
1325/** Opcode VEX.F3.0F 0x58 - vaddss Vss, Hss, Wss */
1326FNIEMOP_STUB(iemOp_vaddss_Vss_Hss_Wss);
1327/** Opcode VEX.F2.0F 0x58 - vaddsd Vsd, Hsd, Wsd */
1328FNIEMOP_STUB(iemOp_vaddsd_Vsd_Hsd_Wsd);
1329
1330/** Opcode VEX.0F 0x59 - vmulps Vps, Hps, Wps */
1331FNIEMOP_STUB(iemOp_vmulps_Vps_Hps_Wps);
1332/** Opcode VEX.66.0F 0x59 - vmulpd Vpd, Hpd, Wpd */
1333FNIEMOP_STUB(iemOp_vmulpd_Vpd_Hpd_Wpd);
1334/** Opcode VEX.F3.0F 0x59 - vmulss Vss, Hss, Wss */
1335FNIEMOP_STUB(iemOp_vmulss_Vss_Hss_Wss);
1336/** Opcode VEX.F2.0F 0x59 - vmulsd Vsd, Hsd, Wsd */
1337FNIEMOP_STUB(iemOp_vmulsd_Vsd_Hsd_Wsd);
1338
1339/** Opcode VEX.0F 0x5a - vcvtps2pd Vpd, Wps */
1340FNIEMOP_STUB(iemOp_vcvtps2pd_Vpd_Wps);
1341/** Opcode VEX.66.0F 0x5a - vcvtpd2ps Vps, Wpd */
1342FNIEMOP_STUB(iemOp_vcvtpd2ps_Vps_Wpd);
1343/** Opcode VEX.F3.0F 0x5a - vcvtss2sd Vsd, Hx, Wss */
1344FNIEMOP_STUB(iemOp_vcvtss2sd_Vsd_Hx_Wss);
1345/** Opcode VEX.F2.0F 0x5a - vcvtsd2ss Vss, Hx, Wsd */
1346FNIEMOP_STUB(iemOp_vcvtsd2ss_Vss_Hx_Wsd);
1347
1348/** Opcode VEX.0F 0x5b - vcvtdq2ps Vps, Wdq */
1349FNIEMOP_STUB(iemOp_vcvtdq2ps_Vps_Wdq);
1350/** Opcode VEX.66.0F 0x5b - vcvtps2dq Vdq, Wps */
1351FNIEMOP_STUB(iemOp_vcvtps2dq_Vdq_Wps);
1352/** Opcode VEX.F3.0F 0x5b - vcvttps2dq Vdq, Wps */
1353FNIEMOP_STUB(iemOp_vcvttps2dq_Vdq_Wps);
1354/* Opcode VEX.F2.0F 0x5b - invalid */
1355
1356/** Opcode VEX.0F 0x5c - vsubps Vps, Hps, Wps */
1357FNIEMOP_STUB(iemOp_vsubps_Vps_Hps_Wps);
1358/** Opcode VEX.66.0F 0x5c - vsubpd Vpd, Hpd, Wpd */
1359FNIEMOP_STUB(iemOp_vsubpd_Vpd_Hpd_Wpd);
1360/** Opcode VEX.F3.0F 0x5c - vsubss Vss, Hss, Wss */
1361FNIEMOP_STUB(iemOp_vsubss_Vss_Hss_Wss);
1362/** Opcode VEX.F2.0F 0x5c - vsubsd Vsd, Hsd, Wsd */
1363FNIEMOP_STUB(iemOp_vsubsd_Vsd_Hsd_Wsd);
1364
1365/** Opcode VEX.0F 0x5d - vminps Vps, Hps, Wps */
1366FNIEMOP_STUB(iemOp_vminps_Vps_Hps_Wps);
1367/** Opcode VEX.66.0F 0x5d - vminpd Vpd, Hpd, Wpd */
1368FNIEMOP_STUB(iemOp_vminpd_Vpd_Hpd_Wpd);
1369/** Opcode VEX.F3.0F 0x5d - vminss Vss, Hss, Wss */
1370FNIEMOP_STUB(iemOp_vminss_Vss_Hss_Wss);
1371/** Opcode VEX.F2.0F 0x5d - vminsd Vsd, Hsd, Wsd */
1372FNIEMOP_STUB(iemOp_vminsd_Vsd_Hsd_Wsd);
1373
1374/** Opcode VEX.0F 0x5e - vdivps Vps, Hps, Wps */
1375FNIEMOP_STUB(iemOp_vdivps_Vps_Hps_Wps);
1376/** Opcode VEX.66.0F 0x5e - vdivpd Vpd, Hpd, Wpd */
1377FNIEMOP_STUB(iemOp_vdivpd_Vpd_Hpd_Wpd);
1378/** Opcode VEX.F3.0F 0x5e - vdivss Vss, Hss, Wss */
1379FNIEMOP_STUB(iemOp_vdivss_Vss_Hss_Wss);
1380/** Opcode VEX.F2.0F 0x5e - vdivsd Vsd, Hsd, Wsd */
1381FNIEMOP_STUB(iemOp_vdivsd_Vsd_Hsd_Wsd);
1382
1383/** Opcode VEX.0F 0x5f - vmaxps Vps, Hps, Wps */
1384FNIEMOP_STUB(iemOp_vmaxps_Vps_Hps_Wps);
1385/** Opcode VEX.66.0F 0x5f - vmaxpd Vpd, Hpd, Wpd */
1386FNIEMOP_STUB(iemOp_vmaxpd_Vpd_Hpd_Wpd);
1387/** Opcode VEX.F3.0F 0x5f - vmaxss Vss, Hss, Wss */
1388FNIEMOP_STUB(iemOp_vmaxss_Vss_Hss_Wss);
1389/** Opcode VEX.F2.0F 0x5f - vmaxsd Vsd, Hsd, Wsd */
1390FNIEMOP_STUB(iemOp_vmaxsd_Vsd_Hsd_Wsd);
1391
1392
1393///**
1394// * Common worker for SSE2 instructions on the forms:
1395// * pxxxx xmm1, xmm2/mem128
1396// *
1397// * The 2nd operand is the first half of a register, which in the memory case
1398// * means a 32-bit memory access for MMX and 128-bit aligned 64-bit or 128-bit
1399// * memory accessed for MMX.
1400// *
1401// * Exceptions type 4.
1402// */
1403//FNIEMOP_DEF_1(iemOpCommonSse_LowLow_To_Full, PCIEMOPMEDIAF1L1, pImpl)
1404//{
1405// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1406// if (!pImpl->pfnU64)
1407// return IEMOP_RAISE_INVALID_OPCODE();
1408// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1409// {
1410// /*
1411// * Register, register.
1412// */
1413// /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
1414// /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
1415// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1416// IEM_MC_BEGIN(2, 0);
1417// IEM_MC_ARG(uint64_t *, pDst, 0);
1418// IEM_MC_ARG(uint32_t const *, pSrc, 1);
1419// IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
1420// IEM_MC_PREPARE_FPU_USAGE();
1421// IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
1422// IEM_MC_REF_MREG_U32_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
1423// IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
1424// IEM_MC_ADVANCE_RIP();
1425// IEM_MC_END();
1426// }
1427// else
1428// {
1429// /*
1430// * Register, memory.
1431// */
1432// IEM_MC_BEGIN(2, 2);
1433// IEM_MC_ARG(uint64_t *, pDst, 0);
1434// IEM_MC_LOCAL(uint32_t, uSrc);
1435// IEM_MC_ARG_LOCAL_REF(uint32_t const *, pSrc, uSrc, 1);
1436// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1437//
1438// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1439// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1440// IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
1441// IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1442//
1443// IEM_MC_PREPARE_FPU_USAGE();
1444// IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
1445// IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
1446//
1447// IEM_MC_ADVANCE_RIP();
1448// IEM_MC_END();
1449// }
1450// return VINF_SUCCESS;
1451//}
1452
1453
1454/* Opcode VEX.0F 0x60 - invalid */
1455
1456/** Opcode VEX.66.0F 0x60 - vpunpcklbw Vx, Hx, W */
1457FNIEMOP_STUB(iemOp_vpunpcklbw_Vx_Hx_Wx);
1458//FNIEMOP_DEF(iemOp_vpunpcklbw_Vx_Hx_Wx)
1459//{
1460// IEMOP_MNEMONIC(vpunpcklbw, "vpunpcklbw Vx, Hx, Wx");
1461// return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklbw);
1462//}
1463
1464/* Opcode VEX.F3.0F 0x60 - invalid */
1465
1466
1467/* Opcode VEX.0F 0x61 - invalid */
1468
1469/** Opcode VEX.66.0F 0x61 - vpunpcklwd Vx, Hx, Wx */
1470FNIEMOP_STUB(iemOp_vpunpcklwd_Vx_Hx_Wx);
1471//FNIEMOP_DEF(iemOp_vpunpcklwd_Vx_Hx_Wx)
1472//{
1473// IEMOP_MNEMONIC(vpunpcklwd, "vpunpcklwd Vx, Hx, Wx");
1474// return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklwd);
1475//}
1476
1477/* Opcode VEX.F3.0F 0x61 - invalid */
1478
1479
1480/* Opcode VEX.0F 0x62 - invalid */
1481
1482/** Opcode VEX.66.0F 0x62 - vpunpckldq Vx, Hx, Wx */
1483FNIEMOP_STUB(iemOp_vpunpckldq_Vx_Hx_Wx);
1484//FNIEMOP_DEF(iemOp_vpunpckldq_Vx_Hx_Wx)
1485//{
1486// IEMOP_MNEMONIC(vpunpckldq, "vpunpckldq Vx, Hx, Wx");
1487// return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpckldq);
1488//}
1489
1490/* Opcode VEX.F3.0F 0x62 - invalid */
1491
1492
1493
1494/* Opcode VEX.0F 0x63 - invalid */
1495/** Opcode VEX.66.0F 0x63 - vpacksswb Vx, Hx, Wx */
1496FNIEMOP_STUB(iemOp_vpacksswb_Vx_Hx_Wx);
1497/* Opcode VEX.F3.0F 0x63 - invalid */
1498
1499/* Opcode VEX.0F 0x64 - invalid */
1500/** Opcode VEX.66.0F 0x64 - vpcmpgtb Vx, Hx, Wx */
1501FNIEMOP_STUB(iemOp_vpcmpgtb_Vx_Hx_Wx);
1502/* Opcode VEX.F3.0F 0x64 - invalid */
1503
1504/* Opcode VEX.0F 0x65 - invalid */
1505/** Opcode VEX.66.0F 0x65 - vpcmpgtw Vx, Hx, Wx */
1506FNIEMOP_STUB(iemOp_vpcmpgtw_Vx_Hx_Wx);
1507/* Opcode VEX.F3.0F 0x65 - invalid */
1508
1509/* Opcode VEX.0F 0x66 - invalid */
1510/** Opcode VEX.66.0F 0x66 - vpcmpgtd Vx, Hx, Wx */
1511FNIEMOP_STUB(iemOp_vpcmpgtd_Vx_Hx_Wx);
1512/* Opcode VEX.F3.0F 0x66 - invalid */
1513
1514/* Opcode VEX.0F 0x67 - invalid */
1515/** Opcode VEX.66.0F 0x67 - vpackuswb Vx, Hx, W */
1516FNIEMOP_STUB(iemOp_vpackuswb_Vx_Hx_W);
1517/* Opcode VEX.F3.0F 0x67 - invalid */
1518
1519
1520///**
1521// * Common worker for SSE2 instructions on the form:
1522// * pxxxx xmm1, xmm2/mem128
1523// *
1524// * The 2nd operand is the second half of a register, which in the memory case
1525// * means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
1526// * where it may read the full 128 bits or only the upper 64 bits.
1527// *
1528// * Exceptions type 4.
1529// */
1530//FNIEMOP_DEF_1(iemOpCommonSse_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
1531//{
1532// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1533// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1534// {
1535// /*
1536// * Register, register.
1537// */
1538// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1539// IEM_MC_BEGIN(2, 0);
1540// IEM_MC_ARG(PRTUINT128U, pDst, 0);
1541// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
1542// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1543// IEM_MC_PREPARE_SSE_USAGE();
1544// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1545// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1546// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
1547// IEM_MC_ADVANCE_RIP();
1548// IEM_MC_END();
1549// }
1550// else
1551// {
1552// /*
1553// * Register, memory.
1554// */
1555// IEM_MC_BEGIN(2, 2);
1556// IEM_MC_ARG(PRTUINT128U, pDst, 0);
1557// IEM_MC_LOCAL(RTUINT128U, uSrc);
1558// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
1559// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1560//
1561// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1562// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1563// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1564// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */
1565//
1566// IEM_MC_PREPARE_SSE_USAGE();
1567// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1568// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
1569//
1570// IEM_MC_ADVANCE_RIP();
1571// IEM_MC_END();
1572// }
1573// return VINF_SUCCESS;
1574//}
1575
1576
1577/* Opcode VEX.0F 0x68 - invalid */
1578
1579/** Opcode VEX.66.0F 0x68 - vpunpckhbw Vx, Hx, Wx */
1580FNIEMOP_STUB(iemOp_vpunpckhbw_Vx_Hx_Wx);
1581//FNIEMOP_DEF(iemOp_vpunpckhbw_Vx_Hx_Wx)
1582//{
1583// IEMOP_MNEMONIC(vpunpckhbw, "vpunpckhbw Vx, Hx, Wx");
1584// return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhbw);
1585//}
1586/* Opcode VEX.F3.0F 0x68 - invalid */
1587
1588
1589/* Opcode VEX.0F 0x69 - invalid */
1590
1591/** Opcode VEX.66.0F 0x69 - vpunpckhwd Vx, Hx, Wx */
1592FNIEMOP_STUB(iemOp_vpunpckhwd_Vx_Hx_Wx);
1593//FNIEMOP_DEF(iemOp_vpunpckhwd_Vx_Hx_Wx)
1594//{
1595// IEMOP_MNEMONIC(vpunpckhwd, "vpunpckhwd Vx, Hx, Wx");
1596// return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhwd);
1597//
1598//}
1599/* Opcode VEX.F3.0F 0x69 - invalid */
1600
1601
1602/* Opcode VEX.0F 0x6a - invalid */
1603
1604/** Opcode VEX.66.0F 0x6a - vpunpckhdq Vx, Hx, W */
1605FNIEMOP_STUB(iemOp_vpunpckhdq_Vx_Hx_W);
1606//FNIEMOP_DEF(iemOp_vpunpckhdq_Vx_Hx_W)
1607//{
1608// IEMOP_MNEMONIC(vpunpckhdq, "vpunpckhdq Vx, Hx, W");
1609// return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhdq);
1610//}
1611/* Opcode VEX.F3.0F 0x6a - invalid */
1612
1613
1614/* Opcode VEX.0F 0x6b - invalid */
1615/** Opcode VEX.66.0F 0x6b - vpackssdw Vx, Hx, Wx */
1616FNIEMOP_STUB(iemOp_vpackssdw_Vx_Hx_Wx);
1617/* Opcode VEX.F3.0F 0x6b - invalid */
1618
1619
1620/* Opcode VEX.0F 0x6c - invalid */
1621
1622/** Opcode VEX.66.0F 0x6c - vpunpcklqdq Vx, Hx, Wx */
1623FNIEMOP_STUB(iemOp_vpunpcklqdq_Vx_Hx_Wx);
1624//FNIEMOP_DEF(iemOp_vpunpcklqdq_Vx_Hx_Wx)
1625//{
1626// IEMOP_MNEMONIC(vpunpcklqdq, "vpunpcklqdq Vx, Hx, Wx");
1627// return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklqdq);
1628//}
1629
1630/* Opcode VEX.F3.0F 0x6c - invalid */
1631/* Opcode VEX.F2.0F 0x6c - invalid */
1632
1633
1634/* Opcode VEX.0F 0x6d - invalid */
1635
1636/** Opcode VEX.66.0F 0x6d - vpunpckhqdq Vx, Hx, W */
1637FNIEMOP_STUB(iemOp_vpunpckhqdq_Vx_Hx_W);
1638//FNIEMOP_DEF(iemOp_vpunpckhqdq_Vx_Hx_W)
1639//{
1640// IEMOP_MNEMONIC(punpckhqdq, "punpckhqdq");
1641// return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhqdq);
1642//}
1643
1644/* Opcode VEX.F3.0F 0x6d - invalid */
1645
1646
1647/* Opcode VEX.0F 0x6e - invalid */
1648
1649/** Opcode VEX.66.0F 0x6e - vmovd/q Vy, Ey */
1650FNIEMOP_STUB(iemOp_vmovd_q_Vy_Ey);
1651//FNIEMOP_DEF(iemOp_vmovd_q_Vy_Ey)
1652//{
1653// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1654// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1655// IEMOP_MNEMONIC(vmovdq_Wq_Eq, "vmovq Wq,Eq");
1656// else
1657// IEMOP_MNEMONIC(vmovdq_Wd_Ed, "vmovd Wd,Ed");
1658// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1659// {
1660// /* XMM, greg*/
1661// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1662// IEM_MC_BEGIN(0, 1);
1663// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1664// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1665// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1666// {
1667// IEM_MC_LOCAL(uint64_t, u64Tmp);
1668// IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1669// IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
1670// }
1671// else
1672// {
1673// IEM_MC_LOCAL(uint32_t, u32Tmp);
1674// IEM_MC_FETCH_GREG_U32(u32Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1675// IEM_MC_STORE_XREG_U32_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
1676// }
1677// IEM_MC_ADVANCE_RIP();
1678// IEM_MC_END();
1679// }
1680// else
1681// {
1682// /* XMM, [mem] */
1683// IEM_MC_BEGIN(0, 2);
1684// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1685// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); /** @todo order */
1686// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1687// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1688// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1689// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1690// {
1691// IEM_MC_LOCAL(uint64_t, u64Tmp);
1692// IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1693// IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
1694// }
1695// else
1696// {
1697// IEM_MC_LOCAL(uint32_t, u32Tmp);
1698// IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1699// IEM_MC_STORE_XREG_U32_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
1700// }
1701// IEM_MC_ADVANCE_RIP();
1702// IEM_MC_END();
1703// }
1704// return VINF_SUCCESS;
1705//}
1706
1707/* Opcode VEX.F3.0F 0x6e - invalid */
1708
1709
1710/* Opcode VEX.0F 0x6f - invalid */
1711
1712/** Opcode VEX.66.0F 0x6f - vmovdqa Vx, Wx */
1713FNIEMOP_STUB(iemOp_vmovdqa_Vx_Wx);
1714//FNIEMOP_DEF(iemOp_vmovdqa_Vx_Wx)
1715//{
1716// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1717// IEMOP_MNEMONIC(vmovdqa_Vdq_Wdq, "movdqa Vdq,Wdq");
1718// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1719// {
1720// /*
1721// * Register, register.
1722// */
1723// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1724// IEM_MC_BEGIN(0, 0);
1725// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1726// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1727// IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1728// (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1729// IEM_MC_ADVANCE_RIP();
1730// IEM_MC_END();
1731// }
1732// else
1733// {
1734// /*
1735// * Register, memory.
1736// */
1737// IEM_MC_BEGIN(0, 2);
1738// IEM_MC_LOCAL(RTUINT128U, u128Tmp);
1739// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1740//
1741// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1742// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1743// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1744// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1745// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1746// IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u128Tmp);
1747//
1748// IEM_MC_ADVANCE_RIP();
1749// IEM_MC_END();
1750// }
1751// return VINF_SUCCESS;
1752//}
1753
1754/** Opcode VEX.F3.0F 0x6f - vmovdqu Vx, Wx */
1755FNIEMOP_STUB(iemOp_vmovdqu_Vx_Wx);
1756//FNIEMOP_DEF(iemOp_vmovdqu_Vx_Wx)
1757//{
1758// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1759// IEMOP_MNEMONIC(vmovdqu_Vdq_Wdq, "movdqu Vdq,Wdq");
1760// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1761// {
1762// /*
1763// * Register, register.
1764// */
1765// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1766// IEM_MC_BEGIN(0, 0);
1767// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1768// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1769// IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1770// (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1771// IEM_MC_ADVANCE_RIP();
1772// IEM_MC_END();
1773// }
1774// else
1775// {
1776// /*
1777// * Register, memory.
1778// */
1779// IEM_MC_BEGIN(0, 2);
1780// IEM_MC_LOCAL(RTUINT128U, u128Tmp);
1781// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1782//
1783// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1784// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1785// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1786// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1787// IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1788// IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u128Tmp);
1789//
1790// IEM_MC_ADVANCE_RIP();
1791// IEM_MC_END();
1792// }
1793// return VINF_SUCCESS;
1794//}
1795
1796
1797/* Opcode VEX.0F 0x70 - invalid */
1798
1799/** Opcode VEX.66.0F 0x70 - vpshufd Vx, Wx, Ib */
1800FNIEMOP_STUB(iemOp_vpshufd_Vx_Wx_Ib);
1801//FNIEMOP_DEF(iemOp_vpshufd_Vx_Wx_Ib)
1802//{
1803// IEMOP_MNEMONIC(vpshufd_Vx_Wx_Ib, "vpshufd Vx,Wx,Ib");
1804// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1805// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1806// {
1807// /*
1808// * Register, register.
1809// */
1810// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
1811// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1812//
1813// IEM_MC_BEGIN(3, 0);
1814// IEM_MC_ARG(PRTUINT128U, pDst, 0);
1815// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
1816// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
1817// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1818// IEM_MC_PREPARE_SSE_USAGE();
1819// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1820// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1821// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufd, pDst, pSrc, bEvilArg);
1822// IEM_MC_ADVANCE_RIP();
1823// IEM_MC_END();
1824// }
1825// else
1826// {
1827// /*
1828// * Register, memory.
1829// */
1830// IEM_MC_BEGIN(3, 2);
1831// IEM_MC_ARG(PRTUINT128U, pDst, 0);
1832// IEM_MC_LOCAL(RTUINT128U, uSrc);
1833// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
1834// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1835//
1836// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1837// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
1838// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
1839// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1840// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1841//
1842// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1843// IEM_MC_PREPARE_SSE_USAGE();
1844// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1845// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufd, pDst, pSrc, bEvilArg);
1846//
1847// IEM_MC_ADVANCE_RIP();
1848// IEM_MC_END();
1849// }
1850// return VINF_SUCCESS;
1851//}
1852
1853/** Opcode VEX.F3.0F 0x70 - vpshufhw Vx, Wx, Ib */
1854FNIEMOP_STUB(iemOp_vpshufhw_Vx_Wx_Ib);
1855//FNIEMOP_DEF(iemOp_vpshufhw_Vx_Wx_Ib)
1856//{
1857// IEMOP_MNEMONIC(vpshufhw_Vx_Wx_Ib, "vpshufhw Vx,Wx,Ib");
1858// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1859// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1860// {
1861// /*
1862// * Register, register.
1863// */
1864// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
1865// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1866//
1867// IEM_MC_BEGIN(3, 0);
1868// IEM_MC_ARG(PRTUINT128U, pDst, 0);
1869// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
1870// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
1871// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1872// IEM_MC_PREPARE_SSE_USAGE();
1873// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1874// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1875// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufhw, pDst, pSrc, bEvilArg);
1876// IEM_MC_ADVANCE_RIP();
1877// IEM_MC_END();
1878// }
1879// else
1880// {
1881// /*
1882// * Register, memory.
1883// */
1884// IEM_MC_BEGIN(3, 2);
1885// IEM_MC_ARG(PRTUINT128U, pDst, 0);
1886// IEM_MC_LOCAL(RTUINT128U, uSrc);
1887// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
1888// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1889//
1890// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1891// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
1892// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
1893// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1894// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1895//
1896// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1897// IEM_MC_PREPARE_SSE_USAGE();
1898// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1899// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufhw, pDst, pSrc, bEvilArg);
1900//
1901// IEM_MC_ADVANCE_RIP();
1902// IEM_MC_END();
1903// }
1904// return VINF_SUCCESS;
1905//}
1906
1907/** Opcode VEX.F2.0F 0x70 - vpshuflw Vx, Wx, Ib */
1908FNIEMOP_STUB(iemOp_vpshuflw_Vx_Wx_Ib);
1909//FNIEMOP_DEF(iemOp_vpshuflw_Vx_Wx_Ib)
1910//{
1911// IEMOP_MNEMONIC(vpshuflw_Vx_Wx_Ib, "vpshuflw Vx,Wx,Ib");
1912// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1913// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1914// {
1915// /*
1916// * Register, register.
1917// */
1918// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
1919// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1920//
1921// IEM_MC_BEGIN(3, 0);
1922// IEM_MC_ARG(PRTUINT128U, pDst, 0);
1923// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
1924// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
1925// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1926// IEM_MC_PREPARE_SSE_USAGE();
1927// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1928// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1929// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshuflw, pDst, pSrc, bEvilArg);
1930// IEM_MC_ADVANCE_RIP();
1931// IEM_MC_END();
1932// }
1933// else
1934// {
1935// /*
1936// * Register, memory.
1937// */
1938// IEM_MC_BEGIN(3, 2);
1939// IEM_MC_ARG(PRTUINT128U, pDst, 0);
1940// IEM_MC_LOCAL(RTUINT128U, uSrc);
1941// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
1942// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1943//
1944// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1945// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
1946// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
1947// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1948// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1949//
1950// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1951// IEM_MC_PREPARE_SSE_USAGE();
1952// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1953// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshuflw, pDst, pSrc, bEvilArg);
1954//
1955// IEM_MC_ADVANCE_RIP();
1956// IEM_MC_END();
1957// }
1958// return VINF_SUCCESS;
1959//}
1960
1961
1962/* Opcode VEX.0F 0x71 11/2 - invalid. */
1963/** Opcode VEX.66.0F 0x71 11/2. */
1964FNIEMOP_STUB_1(iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, uint8_t, bRm);
1965
1966/* Opcode VEX.0F 0x71 11/4 - invalid */
1967/** Opcode VEX.66.0F 0x71 11/4. */
1968FNIEMOP_STUB_1(iemOp_VGrp12_vpsraw_Hx_Ux_Ib, uint8_t, bRm);
1969
1970/* Opcode VEX.0F 0x71 11/6 - invalid */
1971/** Opcode VEX.66.0F 0x71 11/6. */
1972FNIEMOP_STUB_1(iemOp_VGrp12_vpsllw_Hx_Ux_Ib, uint8_t, bRm);
1973
1974
1975/**
1976 * VEX Group 12 jump table for register variant.
1977 */
1978IEM_STATIC const PFNIEMOPRM g_apfnVexGroup12RegReg[] =
1979{
1980 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
1981 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
1982 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
1983 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
1984 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsraw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
1985 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
1986 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsllw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
1987 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
1988};
1989AssertCompile(RT_ELEMENTS(g_apfnVexGroup12RegReg) == 8*4);
1990
1991
1992/** Opcode VEX.0F 0x71. */
1993FNIEMOP_DEF(iemOp_VGrp12)
1994{
1995 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1996 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1997 /* register, register */
1998 return FNIEMOP_CALL_1(g_apfnVexGroup12RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
1999 + pVCpu->iem.s.idxPrefix], bRm);
2000 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
2001}
2002
2003
2004/* Opcode VEX.0F 0x72 11/2 - invalid. */
2005/** Opcode VEX.66.0F 0x72 11/2. */
2006FNIEMOP_STUB_1(iemOp_VGrp13_vpsrld_Hx_Ux_Ib, uint8_t, bRm);
2007
2008/* Opcode VEX.0F 0x72 11/4 - invalid. */
2009/** Opcode VEX.66.0F 0x72 11/4. */
2010FNIEMOP_STUB_1(iemOp_VGrp13_vpsrad_Hx_Ux_Ib, uint8_t, bRm);
2011
2012/* Opcode VEX.0F 0x72 11/6 - invalid. */
2013/** Opcode VEX.66.0F 0x72 11/6. */
2014FNIEMOP_STUB_1(iemOp_VGrp13_vpslld_Hx_Ux_Ib, uint8_t, bRm);
2015
2016
2017/**
2018 * Group 13 jump table for register variant.
2019 */
2020IEM_STATIC const PFNIEMOPRM g_apfnVexGroup13RegReg[] =
2021{
2022 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2023 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2024 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2025 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2026 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrad_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2027 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2028 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpslld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2029 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
2030};
2031AssertCompile(RT_ELEMENTS(g_apfnVexGroup13RegReg) == 8*4);
2032
2033/** Opcode VEX.0F 0x72. */
2034FNIEMOP_DEF(iemOp_VGrp13)
2035{
2036 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2037 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2038 /* register, register */
2039 return FNIEMOP_CALL_1(g_apfnVexGroup13RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
2040 + pVCpu->iem.s.idxPrefix], bRm);
2041 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
2042}
2043
2044
2045/* Opcode VEX.0F 0x73 11/2 - invalid. */
2046/** Opcode VEX.66.0F 0x73 11/2. */
2047FNIEMOP_STUB_1(iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, uint8_t, bRm);
2048
2049/** Opcode VEX.66.0F 0x73 11/3. */
2050FNIEMOP_STUB_1(iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, uint8_t, bRm);
2051
2052/* Opcode VEX.0F 0x73 11/6 - invalid. */
2053/** Opcode VEX.66.0F 0x73 11/6. */
2054FNIEMOP_STUB_1(iemOp_VGrp14_vpsllq_Hx_Ux_Ib, uint8_t, bRm);
2055
2056/** Opcode VEX.66.0F 0x73 11/7. */
2057FNIEMOP_STUB_1(iemOp_VGrp14_vpslldq_Hx_Ux_Ib, uint8_t, bRm);
2058
2059/**
2060 * Group 14 jump table for register variant.
2061 */
2062IEM_STATIC const PFNIEMOPRM g_apfnVexGroup14RegReg[] =
2063{
2064 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2065 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2066 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2067 /* /3 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2068 /* /4 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2069 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2070 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsllq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2071 /* /7 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpslldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2072};
2073AssertCompile(RT_ELEMENTS(g_apfnVexGroup14RegReg) == 8*4);
2074
2075
2076/** Opcode VEX.0F 0x73. */
2077FNIEMOP_DEF(iemOp_VGrp14)
2078{
2079 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2080 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2081 /* register, register */
2082 return FNIEMOP_CALL_1(g_apfnVexGroup14RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
2083 + pVCpu->iem.s.idxPrefix], bRm);
2084 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
2085}
2086
2087
2088///**
2089// * Common worker for SSE2 instructions on the forms:
2090// * pxxx xmm1, xmm2/mem128
2091// *
2092// * Proper alignment of the 128-bit operand is enforced.
2093// * Exceptions type 4. SSE2 cpuid checks.
2094// */
2095//FNIEMOP_DEF_1(iemOpCommonSse2_FullFull_To_Full, PCIEMOPMEDIAF2, pImpl)
2096//{
2097// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2098// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2099// {
2100// /*
2101// * Register, register.
2102// */
2103// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2104// IEM_MC_BEGIN(2, 0);
2105// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2106// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2107// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2108// IEM_MC_PREPARE_SSE_USAGE();
2109// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2110// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2111// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2112// IEM_MC_ADVANCE_RIP();
2113// IEM_MC_END();
2114// }
2115// else
2116// {
2117// /*
2118// * Register, memory.
2119// */
2120// IEM_MC_BEGIN(2, 2);
2121// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2122// IEM_MC_LOCAL(RTUINT128U, uSrc);
2123// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
2124// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2125//
2126// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2127// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2128// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2129// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2130//
2131// IEM_MC_PREPARE_SSE_USAGE();
2132// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2133// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2134//
2135// IEM_MC_ADVANCE_RIP();
2136// IEM_MC_END();
2137// }
2138// return VINF_SUCCESS;
2139//}
2140
2141
2142/* Opcode VEX.0F 0x74 - invalid */
2143
2144/** Opcode VEX.66.0F 0x74 - vpcmpeqb Vx, Hx, Wx */
2145FNIEMOP_STUB(iemOp_vpcmpeqb_Vx_Hx_Wx);
2146//FNIEMOP_DEF(iemOp_vpcmpeqb_Vx_Hx_Wx)
2147//{
2148// IEMOP_MNEMONIC(vpcmpeqb, "vpcmpeqb");
2149// return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqb);
2150//}
2151
2152/* Opcode VEX.F3.0F 0x74 - invalid */
2153/* Opcode VEX.F2.0F 0x74 - invalid */
2154
2155
2156/* Opcode VEX.0F 0x75 - invalid */
2157
2158/** Opcode VEX.66.0F 0x75 - vpcmpeqw Vx, Hx, Wx */
2159FNIEMOP_STUB(iemOp_vpcmpeqw_Vx_Hx_Wx);
2160//FNIEMOP_DEF(iemOp_vpcmpeqw_Vx_Hx_Wx)
2161//{
2162// IEMOP_MNEMONIC(vpcmpeqw, "vpcmpeqw");
2163// return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqw);
2164//}
2165
2166/* Opcode VEX.F3.0F 0x75 - invalid */
2167/* Opcode VEX.F2.0F 0x75 - invalid */
2168
2169
2170/* Opcode VEX.0F 0x76 - invalid */
2171
2172/** Opcode VEX.66.0F 0x76 - vpcmpeqd Vx, Hx, Wx */
2173FNIEMOP_STUB(iemOp_vpcmpeqd_Vx_Hx_Wx);
2174//FNIEMOP_DEF(iemOp_vpcmpeqd_Vx_Hx_Wx)
2175//{
2176// IEMOP_MNEMONIC(vpcmpeqd, "vpcmpeqd");
2177// return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqd);
2178//}
2179
2180/* Opcode VEX.F3.0F 0x76 - invalid */
2181/* Opcode VEX.F2.0F 0x76 - invalid */
2182
2183
2184/** Opcode VEX.0F 0x77 - vzeroupperv vzeroallv */
2185FNIEMOP_STUB(iemOp_vzeroupperv__vzeroallv);
2186/* Opcode VEX.66.0F 0x77 - invalid */
2187/* Opcode VEX.F3.0F 0x77 - invalid */
2188/* Opcode VEX.F2.0F 0x77 - invalid */
2189
2190/* Opcode VEX.0F 0x78 - invalid */
2191/* Opcode VEX.66.0F 0x78 - invalid */
2192/* Opcode VEX.F3.0F 0x78 - invalid */
2193/* Opcode VEX.F2.0F 0x78 - invalid */
2194
2195/* Opcode VEX.0F 0x79 - invalid */
2196/* Opcode VEX.66.0F 0x79 - invalid */
2197/* Opcode VEX.F3.0F 0x79 - invalid */
2198/* Opcode VEX.F2.0F 0x79 - invalid */
2199
2200/* Opcode VEX.0F 0x7a - invalid */
2201/* Opcode VEX.66.0F 0x7a - invalid */
2202/* Opcode VEX.F3.0F 0x7a - invalid */
2203/* Opcode VEX.F2.0F 0x7a - invalid */
2204
2205/* Opcode VEX.0F 0x7b - invalid */
2206/* Opcode VEX.66.0F 0x7b - invalid */
2207/* Opcode VEX.F3.0F 0x7b - invalid */
2208/* Opcode VEX.F2.0F 0x7b - invalid */
2209
2210/* Opcode VEX.0F 0x7c - invalid */
2211/** Opcode VEX.66.0F 0x7c - vhaddpd Vpd, Hpd, Wpd */
2212FNIEMOP_STUB(iemOp_vhaddpd_Vpd_Hpd_Wpd);
2213/* Opcode VEX.F3.0F 0x7c - invalid */
2214/** Opcode VEX.F2.0F 0x7c - vhaddps Vps, Hps, Wps */
2215FNIEMOP_STUB(iemOp_vhaddps_Vps_Hps_Wps);
2216
2217/* Opcode VEX.0F 0x7d - invalid */
2218/** Opcode VEX.66.0F 0x7d - vhsubpd Vpd, Hpd, Wpd */
2219FNIEMOP_STUB(iemOp_vhsubpd_Vpd_Hpd_Wpd);
2220/* Opcode VEX.F3.0F 0x7d - invalid */
2221/** Opcode VEX.F2.0F 0x7d - vhsubps Vps, Hps, Wps */
2222FNIEMOP_STUB(iemOp_vhsubps_Vps_Hps_Wps);
2223
2224
2225/* Opcode VEX.0F 0x7e - invalid */
2226
2227/** Opcode VEX.66.0F 0x7e - vmovd_q Ey, Vy */
2228FNIEMOP_STUB(iemOp_vmovd_q_Ey_Vy);
2229//FNIEMOP_DEF(iemOp_vmovd_q_Ey_Vy)
2230//{
2231// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2232// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2233// IEMOP_MNEMONIC(vmovq_Eq_Wq, "vmovq Eq,Wq");
2234// else
2235// IEMOP_MNEMONIC(vmovd_Ed_Wd, "vmovd Ed,Wd");
2236// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2237// {
2238// /* greg, XMM */
2239// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2240// IEM_MC_BEGIN(0, 1);
2241// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2242// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2243// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2244// {
2245// IEM_MC_LOCAL(uint64_t, u64Tmp);
2246// IEM_MC_FETCH_XREG_U64(u64Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2247// IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Tmp);
2248// }
2249// else
2250// {
2251// IEM_MC_LOCAL(uint32_t, u32Tmp);
2252// IEM_MC_FETCH_XREG_U32(u32Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2253// IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Tmp);
2254// }
2255// IEM_MC_ADVANCE_RIP();
2256// IEM_MC_END();
2257// }
2258// else
2259// {
2260// /* [mem], XMM */
2261// IEM_MC_BEGIN(0, 2);
2262// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2263// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2264// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
2265// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2266// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2267// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2268// {
2269// IEM_MC_LOCAL(uint64_t, u64Tmp);
2270// IEM_MC_FETCH_XREG_U64(u64Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2271// IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
2272// }
2273// else
2274// {
2275// IEM_MC_LOCAL(uint32_t, u32Tmp);
2276// IEM_MC_FETCH_XREG_U32(u32Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2277// IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
2278// }
2279// IEM_MC_ADVANCE_RIP();
2280// IEM_MC_END();
2281// }
2282// return VINF_SUCCESS;
2283//}
2284
2285/** Opcode VEX.F3.0F 0x7e - vmovq Vq, Wq */
2286FNIEMOP_STUB(iemOp_vmovq_Vq_Wq);
2287/* Opcode VEX.F2.0F 0x7e - invalid */
2288
2289
2290/* Opcode VEX.0F 0x7f - invalid */
2291
2292/** Opcode VEX.66.0F 0x7f - vmovdqa Wx,Vx */
2293FNIEMOP_STUB(iemOp_vmovdqa_Wx_Vx);
2294//FNIEMOP_DEF(iemOp_vmovdqa_Wx_Vx)
2295//{
2296// IEMOP_MNEMONIC(vmovdqa_Wdq_Vdq, "vmovdqa Wx,Vx");
2297// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2298// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2299// {
2300// /*
2301// * Register, register.
2302// */
2303// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2304// IEM_MC_BEGIN(0, 0);
2305// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2306// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2307// IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
2308// ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2309// IEM_MC_ADVANCE_RIP();
2310// IEM_MC_END();
2311// }
2312// else
2313// {
2314// /*
2315// * Register, memory.
2316// */
2317// IEM_MC_BEGIN(0, 2);
2318// IEM_MC_LOCAL(RTUINT128U, u128Tmp);
2319// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2320//
2321// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2322// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2323// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2324// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2325//
2326// IEM_MC_FETCH_XREG_U128(u128Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2327// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
2328//
2329// IEM_MC_ADVANCE_RIP();
2330// IEM_MC_END();
2331// }
2332// return VINF_SUCCESS;
2333//}
2334
2335/** Opcode VEX.F3.0F 0x7f - vmovdqu Wx,Vx */
2336FNIEMOP_STUB(iemOp_vmovdqu_Wx_Vx);
2337//FNIEMOP_DEF(iemOp_vmovdqu_Wx_Vx)
2338//{
2339// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2340// IEMOP_MNEMONIC(vmovdqu_Wdq_Vdq, "vmovdqu Wx,Vx");
2341// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2342// {
2343// /*
2344// * Register, register.
2345// */
2346// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2347// IEM_MC_BEGIN(0, 0);
2348// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2349// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2350// IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
2351// ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2352// IEM_MC_ADVANCE_RIP();
2353// IEM_MC_END();
2354// }
2355// else
2356// {
2357// /*
2358// * Register, memory.
2359// */
2360// IEM_MC_BEGIN(0, 2);
2361// IEM_MC_LOCAL(RTUINT128U, u128Tmp);
2362// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2363//
2364// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2365// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2366// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2367// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2368//
2369// IEM_MC_FETCH_XREG_U128(u128Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2370// IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
2371//
2372// IEM_MC_ADVANCE_RIP();
2373// IEM_MC_END();
2374// }
2375// return VINF_SUCCESS;
2376//}
2377
2378/* Opcode VEX.F2.0F 0x7f - invalid */
2379
2380
2381/* Opcode VEX.0F 0x80 - invalid */
2382/* Opcode VEX.0F 0x81 - invalid */
2383/* Opcode VEX.0F 0x82 - invalid */
2384/* Opcode VEX.0F 0x83 - invalid */
2385/* Opcode VEX.0F 0x84 - invalid */
2386/* Opcode VEX.0F 0x85 - invalid */
2387/* Opcode VEX.0F 0x86 - invalid */
2388/* Opcode VEX.0F 0x87 - invalid */
2389/* Opcode VEX.0F 0x88 - invalid */
2390/* Opcode VEX.0F 0x89 - invalid */
2391/* Opcode VEX.0F 0x8a - invalid */
2392/* Opcode VEX.0F 0x8b - invalid */
2393/* Opcode VEX.0F 0x8c - invalid */
2394/* Opcode VEX.0F 0x8d - invalid */
2395/* Opcode VEX.0F 0x8e - invalid */
2396/* Opcode VEX.0F 0x8f - invalid */
2397/* Opcode VEX.0F 0x90 - invalid */
2398/* Opcode VEX.0F 0x91 - invalid */
2399/* Opcode VEX.0F 0x92 - invalid */
2400/* Opcode VEX.0F 0x93 - invalid */
2401/* Opcode VEX.0F 0x94 - invalid */
2402/* Opcode VEX.0F 0x95 - invalid */
2403/* Opcode VEX.0F 0x96 - invalid */
2404/* Opcode VEX.0F 0x97 - invalid */
2405/* Opcode VEX.0F 0x98 - invalid */
2406/* Opcode VEX.0F 0x99 - invalid */
2407/* Opcode VEX.0F 0x9a - invalid */
2408/* Opcode VEX.0F 0x9b - invalid */
2409/* Opcode VEX.0F 0x9c - invalid */
2410/* Opcode VEX.0F 0x9d - invalid */
2411/* Opcode VEX.0F 0x9e - invalid */
2412/* Opcode VEX.0F 0x9f - invalid */
2413/* Opcode VEX.0F 0xa0 - invalid */
2414/* Opcode VEX.0F 0xa1 - invalid */
2415/* Opcode VEX.0F 0xa2 - invalid */
2416/* Opcode VEX.0F 0xa3 - invalid */
2417/* Opcode VEX.0F 0xa4 - invalid */
2418/* Opcode VEX.0F 0xa5 - invalid */
2419/* Opcode VEX.0F 0xa6 - invalid */
2420/* Opcode VEX.0F 0xa7 - invalid */
2421/* Opcode VEX.0F 0xa8 - invalid */
2422/* Opcode VEX.0F 0xa9 - invalid */
2423/* Opcode VEX.0F 0xaa - invalid */
2424/* Opcode VEX.0F 0xab - invalid */
2425/* Opcode VEX.0F 0xac - invalid */
2426/* Opcode VEX.0F 0xad - invalid */
2427
2428
2429/* Opcode VEX.0F 0xae mem/0 - invalid. */
2430/* Opcode VEX.0F 0xae mem/1 - invalid. */
2431
2432/**
2433 * @ opmaps grp15
2434 * @ opcode !11/2
2435 * @ oppfx none
2436 * @ opcpuid sse
2437 * @ opgroup og_sse_mxcsrsm
2438 * @ opxcpttype 5
2439 * @ optest op1=0 -> mxcsr=0
2440 * @ optest op1=0x2083 -> mxcsr=0x2083
2441 * @ optest op1=0xfffffffe -> value.xcpt=0xd
2442 * @ optest op1=0x2083 cr0|=ts -> value.xcpt=0x7
2443 * @ optest op1=0x2083 cr0|=em -> value.xcpt=0x6
2444 * @ optest op1=0x2083 cr0|=mp -> mxcsr=0x2083
2445 * @ optest op1=0x2083 cr4&~=osfxsr -> value.xcpt=0x6
2446 * @ optest op1=0x2083 cr0|=ts,em -> value.xcpt=0x6
2447 * @ optest op1=0x2083 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
2448 * @ optest op1=0x2083 cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
2449 * @ optest op1=0x2083 cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
2450 */
2451FNIEMOP_STUB_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm);
2452//FNIEMOP_DEF_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm)
2453//{
2454// IEMOP_MNEMONIC1(M_MEM, VLDMXCSR, vldmxcsr, MdRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
2455// if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse)
2456// return IEMOP_RAISE_INVALID_OPCODE();
2457//
2458// IEM_MC_BEGIN(2, 0);
2459// IEM_MC_ARG(uint8_t, iEffSeg, 0);
2460// IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
2461// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
2462// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2463// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2464// IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
2465// IEM_MC_CALL_CIMPL_2(iemCImpl_ldmxcsr, iEffSeg, GCPtrEff);
2466// IEM_MC_END();
2467// return VINF_SUCCESS;
2468//}
2469
2470
2471/**
2472 * @opmaps vexgrp15
2473 * @opcode !11/3
2474 * @oppfx none
2475 * @opcpuid avx
2476 * @opgroup og_avx_mxcsrsm
2477 * @opxcpttype 5
2478 * @optest mxcsr=0 -> op1=0
2479 * @optest mxcsr=0x2083 -> op1=0x2083
2480 * @optest mxcsr=0x2084 cr0|=ts -> value.xcpt=0x7
2481 * @optest !amd / mxcsr=0x2085 cr0|=em -> op1=0x2085
2482 * @optest amd / mxcsr=0x2085 cr0|=em -> value.xcpt=0x6
2483 * @optest mxcsr=0x2086 cr0|=mp -> op1=0x2086
2484 * @optest mxcsr=0x2087 cr4&~=osfxsr -> op1=0x2087
2485 * @optest mxcsr=0x208f cr4&~=osxsave -> value.xcpt=0x6
2486 * @optest mxcsr=0x2087 cr4&~=osfxsr,osxsave -> value.xcpt=0x6
2487 * @optest !amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x7
2488 * @optest amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x6
2489 * @optest !amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> op1=0x2089
2490 * @optest amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
2491 * @optest !amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x7
2492 * @optest amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
2493 * @optest !amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x7
2494 * @optest amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
2495 * @optest !amd / mxcsr=0x208c xcr0&~=all_avx -> value.xcpt=0x6
2496 * @optest amd / mxcsr=0x208c xcr0&~=all_avx -> op1=0x208c
2497 * @optest !amd / mxcsr=0x208d xcr0&~=all_avx_sse -> value.xcpt=0x6
2498 * @optest amd / mxcsr=0x208d xcr0&~=all_avx_sse -> op1=0x208d
2499 * @optest !amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x6
2500 * @optest amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x7
2501 * @optest mxcsr=0x2082 cr0|=ts cr4&~=osxsave -> value.xcpt=0x6
2502 * @optest mxcsr=0x2081 xcr0&~=all_avx cr0|=ts cr4&~=osxsave
2503 * -> value.xcpt=0x6
2504 * @remarks AMD Jaguar CPU (f0x16,m0,s1) \#UD when CR0.EM is set. It also
2505 * doesn't seem to check XCR0[2:1] != 11b. This does not match the
2506 * APMv4 rev 3.17 page 509.
2507 * @todo Test this instruction on AMD Ryzen.
2508 */
2509FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr, uint8_t, bRm)
2510{
2511 IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
2512 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx)
2513 return IEMOP_RAISE_INVALID_OPCODE();
2514
2515 IEM_MC_BEGIN(2, 0);
2516 IEM_MC_ARG(uint8_t, iEffSeg, 0);
2517 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
2518 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
2519 IEMOP_HLP_DONE_VEX_DECODING_L_ZERO_NO_VVV();
2520 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2521 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
2522 IEM_MC_CALL_CIMPL_2(iemCImpl_vstmxcsr, iEffSeg, GCPtrEff);
2523 IEM_MC_END();
2524 return VINF_SUCCESS;
2525}
2526
2527/* Opcode VEX.0F 0xae mem/4 - invalid. */
2528/* Opcode VEX.0F 0xae mem/5 - invalid. */
2529/* Opcode VEX.0F 0xae mem/6 - invalid. */
2530/* Opcode VEX.0F 0xae mem/7 - invalid. */
2531
2532/* Opcode VEX.0F 0xae 11b/0 - invalid. */
2533/* Opcode VEX.0F 0xae 11b/1 - invalid. */
2534/* Opcode VEX.0F 0xae 11b/2 - invalid. */
2535/* Opcode VEX.0F 0xae 11b/3 - invalid. */
2536/* Opcode VEX.0F 0xae 11b/4 - invalid. */
2537/* Opcode VEX.0F 0xae 11b/5 - invalid. */
2538/* Opcode VEX.0F 0xae 11b/6 - invalid. */
2539/* Opcode VEX.0F 0xae 11b/7 - invalid. */
2540
2541/**
2542 * Vex group 15 jump table for memory variant.
2543 */
2544IEM_STATIC const PFNIEMOPRM g_apfnVexGroup15MemReg[] =
2545{ /* pfx: none, 066h, 0f3h, 0f2h */
2546 /* /0 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2547 /* /1 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2548 /* /2 */ iemOp_VGrp15_vldmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2549 /* /3 */ iemOp_VGrp15_vstmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2550 /* /4 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2551 /* /5 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2552 /* /6 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2553 /* /7 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2554};
2555AssertCompile(RT_ELEMENTS(g_apfnVexGroup15MemReg) == 8*4);
2556
2557
2558/** Opcode vex. 0xae. */
2559FNIEMOP_DEF(iemOp_VGrp15)
2560{
2561 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2562 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2563 /* register, register */
2564 return FNIEMOP_CALL_1(iemOp_InvalidWithRM, bRm);
2565
2566 /* memory, register */
2567 return FNIEMOP_CALL_1(g_apfnVexGroup15MemReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
2568 + pVCpu->iem.s.idxPrefix], bRm);
2569}
2570
2571
2572/* Opcode VEX.0F 0xaf - invalid. */
2573
2574/* Opcode VEX.0F 0xb0 - invalid. */
2575/* Opcode VEX.0F 0xb1 - invalid. */
2576/* Opcode VEX.0F 0xb2 - invalid. */
2577/* Opcode VEX.0F 0xb2 - invalid. */
2578/* Opcode VEX.0F 0xb3 - invalid. */
2579/* Opcode VEX.0F 0xb4 - invalid. */
2580/* Opcode VEX.0F 0xb5 - invalid. */
2581/* Opcode VEX.0F 0xb6 - invalid. */
2582/* Opcode VEX.0F 0xb7 - invalid. */
2583/* Opcode VEX.0F 0xb8 - invalid. */
2584/* Opcode VEX.0F 0xb9 - invalid. */
2585/* Opcode VEX.0F 0xba - invalid. */
2586/* Opcode VEX.0F 0xbb - invalid. */
2587/* Opcode VEX.0F 0xbc - invalid. */
2588/* Opcode VEX.0F 0xbd - invalid. */
2589/* Opcode VEX.0F 0xbe - invalid. */
2590/* Opcode VEX.0F 0xbf - invalid. */
2591
2592/* Opcode VEX.0F 0xc0 - invalid. */
2593/* Opcode VEX.66.0F 0xc0 - invalid. */
2594/* Opcode VEX.F3.0F 0xc0 - invalid. */
2595/* Opcode VEX.F2.0F 0xc0 - invalid. */
2596
2597/* Opcode VEX.0F 0xc1 - invalid. */
2598/* Opcode VEX.66.0F 0xc1 - invalid. */
2599/* Opcode VEX.F3.0F 0xc1 - invalid. */
2600/* Opcode VEX.F2.0F 0xc1 - invalid. */
2601
2602/** Opcode VEX.0F 0xc2 - vcmpps Vps,Hps,Wps,Ib */
2603FNIEMOP_STUB(iemOp_vcmpps_Vps_Hps_Wps_Ib);
2604/** Opcode VEX.66.0F 0xc2 - vcmppd Vpd,Hpd,Wpd,Ib */
2605FNIEMOP_STUB(iemOp_vcmppd_Vpd_Hpd_Wpd_Ib);
2606/** Opcode VEX.F3.0F 0xc2 - vcmpss Vss,Hss,Wss,Ib */
2607FNIEMOP_STUB(iemOp_vcmpss_Vss_Hss_Wss_Ib);
2608/** Opcode VEX.F2.0F 0xc2 - vcmpsd Vsd,Hsd,Wsd,Ib */
2609FNIEMOP_STUB(iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib);
2610
2611/* Opcode VEX.0F 0xc3 - invalid */
2612/* Opcode VEX.66.0F 0xc3 - invalid */
2613/* Opcode VEX.F3.0F 0xc3 - invalid */
2614/* Opcode VEX.F2.0F 0xc3 - invalid */
2615
2616/* Opcode VEX.0F 0xc4 - invalid */
2617/** Opcode VEX.66.0F 0xc4 - vpinsrw Vdq,Hdq,Ry/Mw,Ib */
2618FNIEMOP_STUB(iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib);
2619/* Opcode VEX.F3.0F 0xc4 - invalid */
2620/* Opcode VEX.F2.0F 0xc4 - invalid */
2621
2622/* Opcode VEX.0F 0xc5 - invlid */
2623/** Opcode VEX.66.0F 0xc5 - vpextrw Gd, Udq, Ib */
2624FNIEMOP_STUB(iemOp_vpextrw_Gd_Udq_Ib);
2625/* Opcode VEX.F3.0F 0xc5 - invalid */
2626/* Opcode VEX.F2.0F 0xc5 - invalid */
2627
2628/** Opcode VEX.0F 0xc6 - vshufps Vps,Hps,Wps,Ib */
2629FNIEMOP_STUB(iemOp_vshufps_Vps_Hps_Wps_Ib);
2630/** Opcode VEX.66.0F 0xc6 - vshufpd Vpd,Hpd,Wpd,Ib */
2631FNIEMOP_STUB(iemOp_vshufpd_Vpd_Hpd_Wpd_Ib);
2632/* Opcode VEX.F3.0F 0xc6 - invalid */
2633/* Opcode VEX.F2.0F 0xc6 - invalid */
2634
2635/* Opcode VEX.0F 0xc7 - invalid */
2636/* Opcode VEX.66.0F 0xc7 - invalid */
2637/* Opcode VEX.F3.0F 0xc7 - invalid */
2638/* Opcode VEX.F2.0F 0xc7 - invalid */
2639
2640/* Opcode VEX.0F 0xc8 - invalid */
2641/* Opcode VEX.0F 0xc9 - invalid */
2642/* Opcode VEX.0F 0xca - invalid */
2643/* Opcode VEX.0F 0xcb - invalid */
2644/* Opcode VEX.0F 0xcc - invalid */
2645/* Opcode VEX.0F 0xcd - invalid */
2646/* Opcode VEX.0F 0xce - invalid */
2647/* Opcode VEX.0F 0xcf - invalid */
2648
2649
2650/* Opcode VEX.0F 0xd0 - invalid */
2651/** Opcode VEX.66.0F 0xd0 - vaddsubpd Vpd, Hpd, Wpd */
2652FNIEMOP_STUB(iemOp_vaddsubpd_Vpd_Hpd_Wpd);
2653/* Opcode VEX.F3.0F 0xd0 - invalid */
2654/** Opcode VEX.F2.0F 0xd0 - vaddsubps Vps, Hps, Wps */
2655FNIEMOP_STUB(iemOp_vaddsubps_Vps_Hps_Wps);
2656
2657/* Opcode VEX.0F 0xd1 - invalid */
2658/** Opcode VEX.66.0F 0xd1 - vpsrlw Vx, Hx, W */
2659FNIEMOP_STUB(iemOp_vpsrlw_Vx_Hx_W);
2660/* Opcode VEX.F3.0F 0xd1 - invalid */
2661/* Opcode VEX.F2.0F 0xd1 - invalid */
2662
2663/* Opcode VEX.0F 0xd2 - invalid */
2664/** Opcode VEX.66.0F 0xd2 - vpsrld Vx, Hx, Wx */
2665FNIEMOP_STUB(iemOp_vpsrld_Vx_Hx_Wx);
2666/* Opcode VEX.F3.0F 0xd2 - invalid */
2667/* Opcode VEX.F2.0F 0xd2 - invalid */
2668
2669/* Opcode VEX.0F 0xd3 - invalid */
2670/** Opcode VEX.66.0F 0xd3 - vpsrlq Vx, Hx, Wx */
2671FNIEMOP_STUB(iemOp_vpsrlq_Vx_Hx_Wx);
2672/* Opcode VEX.F3.0F 0xd3 - invalid */
2673/* Opcode VEX.F2.0F 0xd3 - invalid */
2674
2675/* Opcode VEX.0F 0xd4 - invalid */
2676/** Opcode VEX.66.0F 0xd4 - vpaddq Vx, Hx, W */
2677FNIEMOP_STUB(iemOp_vpaddq_Vx_Hx_W);
2678/* Opcode VEX.F3.0F 0xd4 - invalid */
2679/* Opcode VEX.F2.0F 0xd4 - invalid */
2680
2681/* Opcode VEX.0F 0xd5 - invalid */
2682/** Opcode VEX.66.0F 0xd5 - vpmullw Vx, Hx, Wx */
2683FNIEMOP_STUB(iemOp_vpmullw_Vx_Hx_Wx);
2684/* Opcode VEX.F3.0F 0xd5 - invalid */
2685/* Opcode VEX.F2.0F 0xd5 - invalid */
2686
2687/* Opcode VEX.0F 0xd6 - invalid */
2688
2689/**
2690 * @ opcode 0xd6
2691 * @ oppfx 0x66
2692 * @ opcpuid sse2
2693 * @ opgroup og_sse2_pcksclr_datamove
2694 * @ opxcpttype none
2695 * @ optest op1=-1 op2=2 -> op1=2
2696 * @ optest op1=0 op2=-42 -> op1=-42
2697 */
2698FNIEMOP_STUB(iemOp_vmovq_Wq_Vq);
2699//FNIEMOP_DEF(iemOp_vmovq_Wq_Vq)
2700//{
2701// IEMOP_MNEMONIC2(MR, VMOVQ, vmovq, WqZxReg, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
2702// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2703// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2704// {
2705// /*
2706// * Register, register.
2707// */
2708// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2709// IEM_MC_BEGIN(0, 2);
2710// IEM_MC_LOCAL(uint64_t, uSrc);
2711//
2712// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2713// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2714//
2715// IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2716// IEM_MC_STORE_XREG_U64_ZX_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uSrc);
2717//
2718// IEM_MC_ADVANCE_RIP();
2719// IEM_MC_END();
2720// }
2721// else
2722// {
2723// /*
2724// * Memory, register.
2725// */
2726// IEM_MC_BEGIN(0, 2);
2727// IEM_MC_LOCAL(uint64_t, uSrc);
2728// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2729//
2730// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2731// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2732// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2733// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2734//
2735// IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2736// IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2737//
2738// IEM_MC_ADVANCE_RIP();
2739// IEM_MC_END();
2740// }
2741// return VINF_SUCCESS;
2742//}
2743
2744/* Opcode VEX.F3.0F 0xd6 - invalid */
2745/* Opcode VEX.F2.0F 0xd6 - invalid */
2746
2747
2748/* Opcode VEX.0F 0xd7 - invalid */
2749
2750/** Opcode VEX.66.0F 0xd7 - */
2751FNIEMOP_STUB(iemOp_vpmovmskb_Gd_Ux);
2752//FNIEMOP_DEF(iemOp_vpmovmskb_Gd_Ux)
2753//{
2754// /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
2755// /** @todo testcase: Check that the instruction implicitly clears the high
2756// * bits in 64-bit mode. The REX.W is first necessary when VLMAX > 256
2757// * and opcode modifications are made to work with the whole width (not
2758// * just 128). */
2759// IEMOP_MNEMONIC(vpmovmskb_Gd_Nq, "vpmovmskb Gd, Ux");
2760// /* Docs says register only. */
2761// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2762// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) /** @todo test that this is registers only. */
2763// {
2764// IEMOP_HLP_DECODED_NL_2(OP_PMOVMSKB, IEMOPFORM_RM_REG, OP_PARM_Gd, OP_PARM_Vdq, DISOPTYPE_SSE | DISOPTYPE_HARMLESS);
2765// IEM_MC_BEGIN(2, 0);
2766// IEM_MC_ARG(uint64_t *, pDst, 0);
2767// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2768// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2769// IEM_MC_PREPARE_SSE_USAGE();
2770// IEM_MC_REF_GREG_U64(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2771// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2772// IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_pmovmskb_u128, pDst, pSrc);
2773// IEM_MC_ADVANCE_RIP();
2774// IEM_MC_END();
2775// return VINF_SUCCESS;
2776// }
2777// return IEMOP_RAISE_INVALID_OPCODE();
2778//}
2779
2780/* Opcode VEX.F3.0F 0xd7 - invalid */
2781/* Opcode VEX.F2.0F 0xd7 - invalid */
2782
2783
2784/* Opcode VEX.0F 0xd8 - invalid */
2785/** Opcode VEX.66.0F 0xd8 - vpsubusb Vx, Hx, W */
2786FNIEMOP_STUB(iemOp_vpsubusb_Vx_Hx_W);
2787/* Opcode VEX.F3.0F 0xd8 - invalid */
2788/* Opcode VEX.F2.0F 0xd8 - invalid */
2789
2790/* Opcode VEX.0F 0xd9 - invalid */
2791/** Opcode VEX.66.0F 0xd9 - vpsubusw Vx, Hx, Wx */
2792FNIEMOP_STUB(iemOp_vpsubusw_Vx_Hx_Wx);
2793/* Opcode VEX.F3.0F 0xd9 - invalid */
2794/* Opcode VEX.F2.0F 0xd9 - invalid */
2795
2796/* Opcode VEX.0F 0xda - invalid */
2797/** Opcode VEX.66.0F 0xda - vpminub Vx, Hx, Wx */
2798FNIEMOP_STUB(iemOp_vpminub_Vx_Hx_Wx);
2799/* Opcode VEX.F3.0F 0xda - invalid */
2800/* Opcode VEX.F2.0F 0xda - invalid */
2801
2802/* Opcode VEX.0F 0xdb - invalid */
2803/** Opcode VEX.66.0F 0xdb - vpand Vx, Hx, W */
2804FNIEMOP_STUB(iemOp_vpand_Vx_Hx_W);
2805/* Opcode VEX.F3.0F 0xdb - invalid */
2806/* Opcode VEX.F2.0F 0xdb - invalid */
2807
2808/* Opcode VEX.0F 0xdc - invalid */
2809/** Opcode VEX.66.0F 0xdc - vpaddusb Vx, Hx, Wx */
2810FNIEMOP_STUB(iemOp_vpaddusb_Vx_Hx_Wx);
2811/* Opcode VEX.F3.0F 0xdc - invalid */
2812/* Opcode VEX.F2.0F 0xdc - invalid */
2813
2814/* Opcode VEX.0F 0xdd - invalid */
2815/** Opcode VEX.66.0F 0xdd - vpaddusw Vx, Hx, Wx */
2816FNIEMOP_STUB(iemOp_vpaddusw_Vx_Hx_Wx);
2817/* Opcode VEX.F3.0F 0xdd - invalid */
2818/* Opcode VEX.F2.0F 0xdd - invalid */
2819
2820/* Opcode VEX.0F 0xde - invalid */
2821/** Opcode VEX.66.0F 0xde - vpmaxub Vx, Hx, W */
2822FNIEMOP_STUB(iemOp_vpmaxub_Vx_Hx_W);
2823/* Opcode VEX.F3.0F 0xde - invalid */
2824/* Opcode VEX.F2.0F 0xde - invalid */
2825
2826/* Opcode VEX.0F 0xdf - invalid */
2827/** Opcode VEX.66.0F 0xdf - vpandn Vx, Hx, Wx */
2828FNIEMOP_STUB(iemOp_vpandn_Vx_Hx_Wx);
2829/* Opcode VEX.F3.0F 0xdf - invalid */
2830/* Opcode VEX.F2.0F 0xdf - invalid */
2831
2832/* Opcode VEX.0F 0xe0 - invalid */
2833/** Opcode VEX.66.0F 0xe0 - vpavgb Vx, Hx, Wx */
2834FNIEMOP_STUB(iemOp_vpavgb_Vx_Hx_Wx);
2835/* Opcode VEX.F3.0F 0xe0 - invalid */
2836/* Opcode VEX.F2.0F 0xe0 - invalid */
2837
2838/* Opcode VEX.0F 0xe1 - invalid */
2839/** Opcode VEX.66.0F 0xe1 - vpsraw Vx, Hx, W */
2840FNIEMOP_STUB(iemOp_vpsraw_Vx_Hx_W);
2841/* Opcode VEX.F3.0F 0xe1 - invalid */
2842/* Opcode VEX.F2.0F 0xe1 - invalid */
2843
2844/* Opcode VEX.0F 0xe2 - invalid */
2845/** Opcode VEX.66.0F 0xe2 - vpsrad Vx, Hx, Wx */
2846FNIEMOP_STUB(iemOp_vpsrad_Vx_Hx_Wx);
2847/* Opcode VEX.F3.0F 0xe2 - invalid */
2848/* Opcode VEX.F2.0F 0xe2 - invalid */
2849
2850/* Opcode VEX.0F 0xe3 - invalid */
2851/** Opcode VEX.66.0F 0xe3 - vpavgw Vx, Hx, Wx */
2852FNIEMOP_STUB(iemOp_vpavgw_Vx_Hx_Wx);
2853/* Opcode VEX.F3.0F 0xe3 - invalid */
2854/* Opcode VEX.F2.0F 0xe3 - invalid */
2855
2856/* Opcode VEX.0F 0xe4 - invalid */
2857/** Opcode VEX.66.0F 0xe4 - vpmulhuw Vx, Hx, W */
2858FNIEMOP_STUB(iemOp_vpmulhuw_Vx_Hx_W);
2859/* Opcode VEX.F3.0F 0xe4 - invalid */
2860/* Opcode VEX.F2.0F 0xe4 - invalid */
2861
2862/* Opcode VEX.0F 0xe5 - invalid */
2863/** Opcode VEX.66.0F 0xe5 - vpmulhw Vx, Hx, Wx */
2864FNIEMOP_STUB(iemOp_vpmulhw_Vx_Hx_Wx);
2865/* Opcode VEX.F3.0F 0xe5 - invalid */
2866/* Opcode VEX.F2.0F 0xe5 - invalid */
2867
2868/* Opcode VEX.0F 0xe6 - invalid */
2869/** Opcode VEX.66.0F 0xe6 - vcvttpd2dq Vx, Wpd */
2870FNIEMOP_STUB(iemOp_vcvttpd2dq_Vx_Wpd);
2871/** Opcode VEX.F3.0F 0xe6 - vcvtdq2pd Vx, Wpd */
2872FNIEMOP_STUB(iemOp_vcvtdq2pd_Vx_Wpd);
2873/** Opcode VEX.F2.0F 0xe6 - vcvtpd2dq Vx, Wpd */
2874FNIEMOP_STUB(iemOp_vcvtpd2dq_Vx_Wpd);
2875
2876
2877/* Opcode VEX.0F 0xe7 - invalid */
2878
2879/** Opcode VEX.66.0F 0xe7 - vmovntdq Mx, Vx */
2880FNIEMOP_STUB(iemOp_vmovntdq_Mx_Vx);
2881//FNIEMOP_DEF(iemOp_vmovntdq_Mx_Vx)
2882//{
2883// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2884// if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
2885// {
2886// /* Register, memory. */
2887// IEMOP_MNEMONIC(vmovntdq_Mx_Vx, "vmovntdq Mx,Vx");
2888// IEM_MC_BEGIN(0, 2);
2889// IEM_MC_LOCAL(RTUINT128U, uSrc);
2890// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2891//
2892// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2893// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2894// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2895// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2896//
2897// IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2898// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2899//
2900// IEM_MC_ADVANCE_RIP();
2901// IEM_MC_END();
2902// return VINF_SUCCESS;
2903// }
2904//
2905// /* The register, register encoding is invalid. */
2906// return IEMOP_RAISE_INVALID_OPCODE();
2907//}
2908
2909/* Opcode VEX.F3.0F 0xe7 - invalid */
2910/* Opcode VEX.F2.0F 0xe7 - invalid */
2911
2912
2913/* Opcode VEX.0F 0xe8 - invalid */
2914/** Opcode VEX.66.0F 0xe8 - vpsubsb Vx, Hx, W */
2915FNIEMOP_STUB(iemOp_vpsubsb_Vx_Hx_W);
2916/* Opcode VEX.F3.0F 0xe8 - invalid */
2917/* Opcode VEX.F2.0F 0xe8 - invalid */
2918
2919/* Opcode VEX.0F 0xe9 - invalid */
2920/** Opcode VEX.66.0F 0xe9 - vpsubsw Vx, Hx, Wx */
2921FNIEMOP_STUB(iemOp_vpsubsw_Vx_Hx_Wx);
2922/* Opcode VEX.F3.0F 0xe9 - invalid */
2923/* Opcode VEX.F2.0F 0xe9 - invalid */
2924
2925/* Opcode VEX.0F 0xea - invalid */
2926/** Opcode VEX.66.0F 0xea - vpminsw Vx, Hx, Wx */
2927FNIEMOP_STUB(iemOp_vpminsw_Vx_Hx_Wx);
2928/* Opcode VEX.F3.0F 0xea - invalid */
2929/* Opcode VEX.F2.0F 0xea - invalid */
2930
2931/* Opcode VEX.0F 0xeb - invalid */
2932/** Opcode VEX.66.0F 0xeb - vpor Vx, Hx, W */
2933FNIEMOP_STUB(iemOp_vpor_Vx_Hx_W);
2934/* Opcode VEX.F3.0F 0xeb - invalid */
2935/* Opcode VEX.F2.0F 0xeb - invalid */
2936
2937/* Opcode VEX.0F 0xec - invalid */
2938/** Opcode VEX.66.0F 0xec - vpaddsb Vx, Hx, Wx */
2939FNIEMOP_STUB(iemOp_vpaddsb_Vx_Hx_Wx);
2940/* Opcode VEX.F3.0F 0xec - invalid */
2941/* Opcode VEX.F2.0F 0xec - invalid */
2942
2943/* Opcode VEX.0F 0xed - invalid */
2944/** Opcode VEX.66.0F 0xed - vpaddsw Vx, Hx, Wx */
2945FNIEMOP_STUB(iemOp_vpaddsw_Vx_Hx_Wx);
2946/* Opcode VEX.F3.0F 0xed - invalid */
2947/* Opcode VEX.F2.0F 0xed - invalid */
2948
2949/* Opcode VEX.0F 0xee - invalid */
2950/** Opcode VEX.66.0F 0xee - vpmaxsw Vx, Hx, W */
2951FNIEMOP_STUB(iemOp_vpmaxsw_Vx_Hx_W);
2952/* Opcode VEX.F3.0F 0xee - invalid */
2953/* Opcode VEX.F2.0F 0xee - invalid */
2954
2955
2956/* Opcode VEX.0F 0xef - invalid */
2957
2958/** Opcode VEX.66.0F 0xef - vpxor Vx, Hx, Wx */
2959FNIEMOP_DEF(iemOp_vpxor_Vx_Hx_Wx)
2960{
2961 IEMOP_MNEMONIC(vpxor, "vpxor");
2962 return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pxor);
2963}
2964
2965/* Opcode VEX.F3.0F 0xef - invalid */
2966/* Opcode VEX.F2.0F 0xef - invalid */
2967
2968/* Opcode VEX.0F 0xf0 - invalid */
2969/* Opcode VEX.66.0F 0xf0 - invalid */
2970/** Opcode VEX.F2.0F 0xf0 - vlddqu Vx, Mx */
2971FNIEMOP_STUB(iemOp_vlddqu_Vx_Mx);
2972
2973/* Opcode VEX.0F 0xf1 - invalid */
2974/** Opcode VEX.66.0F 0xf1 - vpsllw Vx, Hx, W */
2975FNIEMOP_STUB(iemOp_vpsllw_Vx_Hx_W);
2976/* Opcode VEX.F2.0F 0xf1 - invalid */
2977
2978/* Opcode VEX.0F 0xf2 - invalid */
2979/** Opcode VEX.66.0F 0xf2 - vpslld Vx, Hx, Wx */
2980FNIEMOP_STUB(iemOp_vpslld_Vx_Hx_Wx);
2981/* Opcode VEX.F2.0F 0xf2 - invalid */
2982
2983/* Opcode VEX.0F 0xf3 - invalid */
2984/** Opcode VEX.66.0F 0xf3 - vpsllq Vx, Hx, Wx */
2985FNIEMOP_STUB(iemOp_vpsllq_Vx_Hx_Wx);
2986/* Opcode VEX.F2.0F 0xf3 - invalid */
2987
2988/* Opcode VEX.0F 0xf4 - invalid */
2989/** Opcode VEX.66.0F 0xf4 - vpmuludq Vx, Hx, W */
2990FNIEMOP_STUB(iemOp_vpmuludq_Vx_Hx_W);
2991/* Opcode VEX.F2.0F 0xf4 - invalid */
2992
2993/* Opcode VEX.0F 0xf5 - invalid */
2994/** Opcode VEX.66.0F 0xf5 - vpmaddwd Vx, Hx, Wx */
2995FNIEMOP_STUB(iemOp_vpmaddwd_Vx_Hx_Wx);
2996/* Opcode VEX.F2.0F 0xf5 - invalid */
2997
2998/* Opcode VEX.0F 0xf6 - invalid */
2999/** Opcode VEX.66.0F 0xf6 - vpsadbw Vx, Hx, Wx */
3000FNIEMOP_STUB(iemOp_vpsadbw_Vx_Hx_Wx);
3001/* Opcode VEX.F2.0F 0xf6 - invalid */
3002
3003/* Opcode VEX.0F 0xf7 - invalid */
3004/** Opcode VEX.66.0F 0xf7 - vmaskmovdqu Vdq, Udq */
3005FNIEMOP_STUB(iemOp_vmaskmovdqu_Vdq_Udq);
3006/* Opcode VEX.F2.0F 0xf7 - invalid */
3007
3008/* Opcode VEX.0F 0xf8 - invalid */
3009/** Opcode VEX.66.0F 0xf8 - vpsubb Vx, Hx, W */
3010FNIEMOP_STUB(iemOp_vpsubb_Vx_Hx_W);
3011/* Opcode VEX.F2.0F 0xf8 - invalid */
3012
3013/* Opcode VEX.0F 0xf9 - invalid */
3014/** Opcode VEX.66.0F 0xf9 - vpsubw Vx, Hx, Wx */
3015FNIEMOP_STUB(iemOp_vpsubw_Vx_Hx_Wx);
3016/* Opcode VEX.F2.0F 0xf9 - invalid */
3017
3018/* Opcode VEX.0F 0xfa - invalid */
3019/** Opcode VEX.66.0F 0xfa - vpsubd Vx, Hx, Wx */
3020FNIEMOP_STUB(iemOp_vpsubd_Vx_Hx_Wx);
3021/* Opcode VEX.F2.0F 0xfa - invalid */
3022
3023/* Opcode VEX.0F 0xfb - invalid */
3024/** Opcode VEX.66.0F 0xfb - vpsubq Vx, Hx, W */
3025FNIEMOP_STUB(iemOp_vpsubq_Vx_Hx_W);
3026/* Opcode VEX.F2.0F 0xfb - invalid */
3027
3028/* Opcode VEX.0F 0xfc - invalid */
3029/** Opcode VEX.66.0F 0xfc - vpaddb Vx, Hx, Wx */
3030FNIEMOP_STUB(iemOp_vpaddb_Vx_Hx_Wx);
3031/* Opcode VEX.F2.0F 0xfc - invalid */
3032
3033/* Opcode VEX.0F 0xfd - invalid */
3034/** Opcode VEX.66.0F 0xfd - vpaddw Vx, Hx, Wx */
3035FNIEMOP_STUB(iemOp_vpaddw_Vx_Hx_Wx);
3036/* Opcode VEX.F2.0F 0xfd - invalid */
3037
3038/* Opcode VEX.0F 0xfe - invalid */
3039/** Opcode VEX.66.0F 0xfe - vpaddd Vx, Hx, W */
3040FNIEMOP_STUB(iemOp_vpaddd_Vx_Hx_W);
3041/* Opcode VEX.F2.0F 0xfe - invalid */
3042
3043
3044/** Opcode **** 0x0f 0xff - UD0 */
3045FNIEMOP_DEF(iemOp_vud0)
3046{
3047 IEMOP_MNEMONIC(vud0, "vud0");
3048 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3049 {
3050 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
3051#ifndef TST_IEM_CHECK_MC
3052 RTGCPTR GCPtrEff;
3053 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
3054 if (rcStrict != VINF_SUCCESS)
3055 return rcStrict;
3056#endif
3057 IEMOP_HLP_DONE_DECODING();
3058 }
3059 return IEMOP_RAISE_INVALID_OPCODE();
3060}
3061
3062
3063
3064/**
3065 * VEX opcode map \#1.
3066 *
3067 * @sa g_apfnTwoByteMap
3068 */
3069IEM_STATIC const PFNIEMOP g_apfnVexMap1[] =
3070{
3071 /* no prefix, 066h prefix f3h prefix, f2h prefix */
3072 /* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRM),
3073 /* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRM),
3074 /* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRM),
3075 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRM),
3076 /* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRM),
3077 /* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRM),
3078 /* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRM),
3079 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRM),
3080 /* 0x08 */ IEMOP_X4(iemOp_InvalidNeedRM),
3081 /* 0x09 */ IEMOP_X4(iemOp_InvalidNeedRM),
3082 /* 0x0a */ IEMOP_X4(iemOp_InvalidNeedRM),
3083 /* 0x0b */ IEMOP_X4(iemOp_vud2), /* ?? */
3084 /* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
3085 /* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
3086 /* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
3087 /* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
3088
3089 /* 0x10 */ iemOp_vmovups_Vps_Wps, iemOp_vmovupd_Vpd_Wpd, iemOp_vmovss_Vss_Hss_Wss, iemOp_vmovsd_Vsd_Hsd_Wsd,
3090 /* 0x11 */ iemOp_vmovups_Wps_Vps, iemOp_vmovupd_Wpd_Vpd, iemOp_vmovss_Wss_Hss_Vss, iemOp_vmovsd_Wsd_Hsd_Vsd,
3091 /* 0x12 */ iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx, iemOp_vmovddup_Vx_Wx,
3092 /* 0x13 */ iemOp_vmovlps_Mq_Vq, iemOp_vmovlpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3093 /* 0x14 */ iemOp_vunpcklps_Vx_Hx_Wx, iemOp_vunpcklpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3094 /* 0x15 */ iemOp_vunpckhps_Vx_Hx_Wx, iemOp_vunpckhpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3095 /* 0x16 */ iemOp_vmovhpsv1_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq, iemOp_vmovhpdv1_Vdq_Hq_Mq, iemOp_vmovshdup_Vx_Wx, iemOp_InvalidNeedRM,
3096 /* 0x17 */ iemOp_vmovhpsv1_Mq_Vq, iemOp_vmovhpdv1_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3097 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
3098 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
3099 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
3100 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
3101 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRM),
3102 /* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRM),
3103 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRM),
3104 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
3105
3106 /* 0x20 */ IEMOP_X4(iemOp_InvalidNeedRM),
3107 /* 0x21 */ IEMOP_X4(iemOp_InvalidNeedRM),
3108 /* 0x22 */ IEMOP_X4(iemOp_InvalidNeedRM),
3109 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRM),
3110 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRM),
3111 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRM),
3112 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
3113 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
3114 /* 0x28 */ iemOp_vmovaps_Vps_Wps, iemOp_vmovapd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3115 /* 0x29 */ iemOp_vmovaps_Wps_Vps, iemOp_vmovapd_Wpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3116 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtsi2ss_Vss_Hss_Ey, iemOp_vcvtsi2sd_Vsd_Hsd_Ey,
3117 /* 0x2b */ iemOp_vmovntps_Mps_Vps, iemOp_vmovntpd_Mpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3118 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvttss2si_Gy_Wss, iemOp_vcvttsd2si_Gy_Wsd,
3119 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtss2si_Gy_Wss, iemOp_vcvtsd2si_Gy_Wsd,
3120 /* 0x2e */ iemOp_vucomiss_Vss_Wss, iemOp_vucomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3121 /* 0x2f */ iemOp_vcomiss_Vss_Wss, iemOp_vcomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3122
3123 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRM),
3124 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRM),
3125 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRM),
3126 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRM),
3127 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRM),
3128 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRM),
3129 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
3130 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRM),
3131 /* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3132 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3133 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3134 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3135 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3136 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3137 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3138 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3139
3140 /* 0x40 */ IEMOP_X4(iemOp_InvalidNeedRM),
3141 /* 0x41 */ IEMOP_X4(iemOp_InvalidNeedRM),
3142 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
3143 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
3144 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
3145 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
3146 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
3147 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
3148 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
3149 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
3150 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
3151 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
3152 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
3153 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
3154 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
3155 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
3156
3157 /* 0x50 */ iemOp_vmovmskps_Gy_Ups, iemOp_vmovmskpd_Gy_Upd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3158 /* 0x51 */ iemOp_vsqrtps_Vps_Wps, iemOp_vsqrtpd_Vpd_Wpd, iemOp_vsqrtss_Vss_Hss_Wss, iemOp_vsqrtsd_Vsd_Hsd_Wsd,
3159 /* 0x52 */ iemOp_vrsqrtps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrsqrtss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
3160 /* 0x53 */ iemOp_vrcpps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrcpss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
3161 /* 0x54 */ iemOp_vandps_Vps_Hps_Wps, iemOp_vandpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3162 /* 0x55 */ iemOp_vandnps_Vps_Hps_Wps, iemOp_vandnpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3163 /* 0x56 */ iemOp_vorps_Vps_Hps_Wps, iemOp_vorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3164 /* 0x57 */ iemOp_vxorps_Vps_Hps_Wps, iemOp_vxorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3165 /* 0x58 */ iemOp_vaddps_Vps_Hps_Wps, iemOp_vaddpd_Vpd_Hpd_Wpd, iemOp_vaddss_Vss_Hss_Wss, iemOp_vaddsd_Vsd_Hsd_Wsd,
3166 /* 0x59 */ iemOp_vmulps_Vps_Hps_Wps, iemOp_vmulpd_Vpd_Hpd_Wpd, iemOp_vmulss_Vss_Hss_Wss, iemOp_vmulsd_Vsd_Hsd_Wsd,
3167 /* 0x5a */ iemOp_vcvtps2pd_Vpd_Wps, iemOp_vcvtpd2ps_Vps_Wpd, iemOp_vcvtss2sd_Vsd_Hx_Wss, iemOp_vcvtsd2ss_Vss_Hx_Wsd,
3168 /* 0x5b */ iemOp_vcvtdq2ps_Vps_Wdq, iemOp_vcvtps2dq_Vdq_Wps, iemOp_vcvttps2dq_Vdq_Wps, iemOp_InvalidNeedRM,
3169 /* 0x5c */ iemOp_vsubps_Vps_Hps_Wps, iemOp_vsubpd_Vpd_Hpd_Wpd, iemOp_vsubss_Vss_Hss_Wss, iemOp_vsubsd_Vsd_Hsd_Wsd,
3170 /* 0x5d */ iemOp_vminps_Vps_Hps_Wps, iemOp_vminpd_Vpd_Hpd_Wpd, iemOp_vminss_Vss_Hss_Wss, iemOp_vminsd_Vsd_Hsd_Wsd,
3171 /* 0x5e */ iemOp_vdivps_Vps_Hps_Wps, iemOp_vdivpd_Vpd_Hpd_Wpd, iemOp_vdivss_Vss_Hss_Wss, iemOp_vdivsd_Vsd_Hsd_Wsd,
3172 /* 0x5f */ iemOp_vmaxps_Vps_Hps_Wps, iemOp_vmaxpd_Vpd_Hpd_Wpd, iemOp_vmaxss_Vss_Hss_Wss, iemOp_vmaxsd_Vsd_Hsd_Wsd,
3173
3174 /* 0x60 */ iemOp_InvalidNeedRM, iemOp_vpunpcklbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3175 /* 0x61 */ iemOp_InvalidNeedRM, iemOp_vpunpcklwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3176 /* 0x62 */ iemOp_InvalidNeedRM, iemOp_vpunpckldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3177 /* 0x63 */ iemOp_InvalidNeedRM, iemOp_vpacksswb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3178 /* 0x64 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3179 /* 0x65 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3180 /* 0x66 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3181 /* 0x67 */ iemOp_InvalidNeedRM, iemOp_vpackuswb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3182 /* 0x68 */ iemOp_InvalidNeedRM, iemOp_vpunpckhbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3183 /* 0x69 */ iemOp_InvalidNeedRM, iemOp_vpunpckhwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3184 /* 0x6a */ iemOp_InvalidNeedRM, iemOp_vpunpckhdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3185 /* 0x6b */ iemOp_InvalidNeedRM, iemOp_vpackssdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3186 /* 0x6c */ iemOp_InvalidNeedRM, iemOp_vpunpcklqdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3187 /* 0x6d */ iemOp_InvalidNeedRM, iemOp_vpunpckhqdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3188 /* 0x6e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Vy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3189 /* 0x6f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Vx_Wx, iemOp_vmovdqu_Vx_Wx, iemOp_InvalidNeedRM,
3190
3191 /* 0x70 */ iemOp_InvalidNeedRM, iemOp_vpshufd_Vx_Wx_Ib, iemOp_vpshufhw_Vx_Wx_Ib, iemOp_vpshuflw_Vx_Wx_Ib,
3192 /* 0x71 */ iemOp_InvalidNeedRM, iemOp_VGrp12, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3193 /* 0x72 */ iemOp_InvalidNeedRM, iemOp_VGrp13, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3194 /* 0x73 */ iemOp_InvalidNeedRM, iemOp_VGrp14, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3195 /* 0x74 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3196 /* 0x75 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3197 /* 0x76 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3198 /* 0x77 */ iemOp_vzeroupperv__vzeroallv, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3199 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
3200 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
3201 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
3202 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
3203 /* 0x7c */ iemOp_InvalidNeedRM, iemOp_vhaddpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhaddps_Vps_Hps_Wps,
3204 /* 0x7d */ iemOp_InvalidNeedRM, iemOp_vhsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhsubps_Vps_Hps_Wps,
3205 /* 0x7e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Ey_Vy, iemOp_vmovq_Vq_Wq, iemOp_InvalidNeedRM,
3206 /* 0x7f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Wx_Vx, iemOp_vmovdqu_Wx_Vx, iemOp_InvalidNeedRM,
3207
3208 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
3209 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
3210 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
3211 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
3212 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
3213 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
3214 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
3215 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
3216 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
3217 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
3218 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
3219 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
3220 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
3221 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
3222 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
3223 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
3224
3225 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
3226 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
3227 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
3228 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
3229 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
3230 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
3231 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
3232 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
3233 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
3234 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
3235 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
3236 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
3237 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
3238 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
3239 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
3240 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
3241
3242 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3243 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3244 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
3245 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3246 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
3247 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
3248 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
3249 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
3250 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
3251 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
3252 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
3253 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
3254 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
3255 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
3256 /* 0xae */ IEMOP_X4(iemOp_VGrp15),
3257 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
3258
3259 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3260 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3261 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
3262 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3263 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
3264 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
3265 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
3266 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
3267 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
3268 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
3269 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
3270 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
3271 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
3272 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
3273 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
3274 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
3275
3276 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3277 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3278 /* 0xc2 */ iemOp_vcmpps_Vps_Hps_Wps_Ib, iemOp_vcmppd_Vpd_Hpd_Wpd_Ib, iemOp_vcmpss_Vss_Hss_Wss_Ib, iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib,
3279 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3280 /* 0xc4 */ iemOp_InvalidNeedRM, iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
3281 /* 0xc5 */ iemOp_InvalidNeedRM, iemOp_vpextrw_Gd_Udq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
3282 /* 0xc6 */ iemOp_vshufps_Vps_Hps_Wps_Ib, iemOp_vshufpd_Vpd_Hpd_Wpd_Ib, iemOp_InvalidNeedRMImm8,iemOp_InvalidNeedRMImm8,
3283 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
3284 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
3285 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
3286 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
3287 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
3288 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
3289 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
3290 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
3291 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
3292
3293 /* 0xd0 */ iemOp_InvalidNeedRM, iemOp_vaddsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vaddsubps_Vps_Hps_Wps,
3294 /* 0xd1 */ iemOp_InvalidNeedRM, iemOp_vpsrlw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3295 /* 0xd2 */ iemOp_InvalidNeedRM, iemOp_vpsrld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3296 /* 0xd3 */ iemOp_InvalidNeedRM, iemOp_vpsrlq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3297 /* 0xd4 */ iemOp_InvalidNeedRM, iemOp_vpaddq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3298 /* 0xd5 */ iemOp_InvalidNeedRM, iemOp_vpmullw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3299 /* 0xd6 */ iemOp_InvalidNeedRM, iemOp_vmovq_Wq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3300 /* 0xd7 */ iemOp_InvalidNeedRM, iemOp_vpmovmskb_Gd_Ux, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3301 /* 0xd8 */ iemOp_InvalidNeedRM, iemOp_vpsubusb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3302 /* 0xd9 */ iemOp_InvalidNeedRM, iemOp_vpsubusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3303 /* 0xda */ iemOp_InvalidNeedRM, iemOp_vpminub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3304 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vpand_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3305 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vpaddusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3306 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vpaddusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3307 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vpmaxub_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3308 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vpandn_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3309
3310 /* 0xe0 */ iemOp_InvalidNeedRM, iemOp_vpavgb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3311 /* 0xe1 */ iemOp_InvalidNeedRM, iemOp_vpsraw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3312 /* 0xe2 */ iemOp_InvalidNeedRM, iemOp_vpsrad_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3313 /* 0xe3 */ iemOp_InvalidNeedRM, iemOp_vpavgw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3314 /* 0xe4 */ iemOp_InvalidNeedRM, iemOp_vpmulhuw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3315 /* 0xe5 */ iemOp_InvalidNeedRM, iemOp_vpmulhw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3316 /* 0xe6 */ iemOp_InvalidNeedRM, iemOp_vcvttpd2dq_Vx_Wpd, iemOp_vcvtdq2pd_Vx_Wpd, iemOp_vcvtpd2dq_Vx_Wpd,
3317 /* 0xe7 */ iemOp_InvalidNeedRM, iemOp_vmovntdq_Mx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3318 /* 0xe8 */ iemOp_InvalidNeedRM, iemOp_vpsubsb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3319 /* 0xe9 */ iemOp_InvalidNeedRM, iemOp_vpsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3320 /* 0xea */ iemOp_InvalidNeedRM, iemOp_vpminsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3321 /* 0xeb */ iemOp_InvalidNeedRM, iemOp_vpor_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3322 /* 0xec */ iemOp_InvalidNeedRM, iemOp_vpaddsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3323 /* 0xed */ iemOp_InvalidNeedRM, iemOp_vpaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3324 /* 0xee */ iemOp_InvalidNeedRM, iemOp_vpmaxsw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3325 /* 0xef */ iemOp_InvalidNeedRM, iemOp_vpxor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3326
3327 /* 0xf0 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vlddqu_Vx_Mx,
3328 /* 0xf1 */ iemOp_InvalidNeedRM, iemOp_vpsllw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3329 /* 0xf2 */ iemOp_InvalidNeedRM, iemOp_vpslld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3330 /* 0xf3 */ iemOp_InvalidNeedRM, iemOp_vpsllq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3331 /* 0xf4 */ iemOp_InvalidNeedRM, iemOp_vpmuludq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3332 /* 0xf5 */ iemOp_InvalidNeedRM, iemOp_vpmaddwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3333 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_vpsadbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3334 /* 0xf7 */ iemOp_InvalidNeedRM, iemOp_vmaskmovdqu_Vdq_Udq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3335 /* 0xf8 */ iemOp_InvalidNeedRM, iemOp_vpsubb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3336 /* 0xf9 */ iemOp_InvalidNeedRM, iemOp_vpsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3337 /* 0xfa */ iemOp_InvalidNeedRM, iemOp_vpsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3338 /* 0xfb */ iemOp_InvalidNeedRM, iemOp_vpsubq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3339 /* 0xfc */ iemOp_InvalidNeedRM, iemOp_vpaddb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3340 /* 0xfd */ iemOp_InvalidNeedRM, iemOp_vpaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3341 /* 0xfe */ iemOp_InvalidNeedRM, iemOp_vpaddd_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3342 /* 0xff */ IEMOP_X4(iemOp_vud0) /* ?? */
3343};
3344AssertCompile(RT_ELEMENTS(g_apfnVexMap1) == 1024);
3345/** @} */
3346
3347
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