VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h@ 66976

Last change on this file since 66976 was 66976, checked in by vboxsync, 8 years ago

IEM: Implemented vmovapd Vpd,Wpd (VEX.66.28).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 137.5 KB
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1/* $Id: IEMAllInstructionsVexMap1.cpp.h 66976 2017-05-19 12:23:32Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstructionsTwoByte0f.cpp.h is a legacy mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2016 Oracle Corporation
11 *
12 * This file is part of VirtualBox Open Source Edition (OSE), as
13 * available from http://www.virtualbox.org. This file is free software;
14 * you can redistribute it and/or modify it under the terms of the GNU
15 * General Public License (GPL) as published by the Free Software
16 * Foundation, in version 2 as it comes in the "COPYING" file of the
17 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19 */
20
21
22/** @name VEX Opcode Map 1
23 * @{
24 */
25
26
27/* Opcode VEX.0F 0x00 - invalid */
28/* Opcode VEX.0F 0x01 - invalid */
29/* Opcode VEX.0F 0x02 - invalid */
30/* Opcode VEX.0F 0x03 - invalid */
31/* Opcode VEX.0F 0x04 - invalid */
32/* Opcode VEX.0F 0x05 - invalid */
33/* Opcode VEX.0F 0x06 - invalid */
34/* Opcode VEX.0F 0x07 - invalid */
35/* Opcode VEX.0F 0x08 - invalid */
36/* Opcode VEX.0F 0x09 - invalid */
37/* Opcode VEX.0F 0x0a - invalid */
38
39/** Opcode VEX.0F 0x0b. */
40FNIEMOP_DEF(iemOp_vud2)
41{
42 IEMOP_MNEMONIC(vud2, "vud2");
43 return IEMOP_RAISE_INVALID_OPCODE();
44}
45
46/* Opcode VEX.0F 0x0c - invalid */
47/* Opcode VEX.0F 0x0d - invalid */
48/* Opcode VEX.0F 0x0e - invalid */
49/* Opcode VEX.0F 0x0f - invalid */
50
51
52/**
53 * @opcode 0x10
54 * @oppfx none
55 * @opcpuid avx
56 * @opgroup og_avx_simdfp_datamove
57 * @opxcpttype 4UA
58 * @optest op1=1 op2=2 -> op1=2
59 * @optest op1=0 op2=-22 -> op1=-22
60 */
61FNIEMOP_DEF(iemOp_vmovups_Vps_Wps)
62{
63 IEMOP_MNEMONIC2(VEX_RM, VMOVUPS, vmovups, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
64 Assert(pVCpu->iem.s.uVexLength <= 1);
65 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
66 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
67 {
68 /*
69 * Register, register.
70 */
71 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
72 IEM_MC_BEGIN(0, 0);
73 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
74 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
75 if (pVCpu->iem.s.uVexLength == 0)
76 IEM_MC_COPY_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
77 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
78 else
79 IEM_MC_COPY_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
80 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
81 IEM_MC_ADVANCE_RIP();
82 IEM_MC_END();
83 }
84 else if (pVCpu->iem.s.uVexLength == 0)
85 {
86 /*
87 * 128-bit: Memory, register.
88 */
89 IEM_MC_BEGIN(0, 2);
90 IEM_MC_LOCAL(RTUINT128U, uSrc);
91 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
92
93 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
94 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
95 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
96 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
97
98 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
99 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
100
101 IEM_MC_ADVANCE_RIP();
102 IEM_MC_END();
103 }
104 else
105 {
106 /*
107 * 256-bit: Memory, register.
108 */
109 IEM_MC_BEGIN(0, 2);
110 IEM_MC_LOCAL(RTUINT256U, uSrc);
111 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
112
113 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
114 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
115 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
116 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
117
118 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
119 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
120
121 IEM_MC_ADVANCE_RIP();
122 IEM_MC_END();
123 }
124 return VINF_SUCCESS;
125}
126
127
128/**
129 * @opcode 0x10
130 * @oppfx 0x66
131 * @opcpuid avx
132 * @opgroup og_avx_simdfp_datamove
133 * @opxcpttype 4UA
134 * @optest op1=1 op2=2 -> op1=2
135 * @optest op1=0 op2=-22 -> op1=-22
136 */
137FNIEMOP_DEF(iemOp_vmovupd_Vpd_Wpd)
138{
139 IEMOP_MNEMONIC2(VEX_RM, VMOVUPD, vmovupd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
140 Assert(pVCpu->iem.s.uVexLength <= 1);
141 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
142 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
143 {
144 /*
145 * Register, register.
146 */
147 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
148 IEM_MC_BEGIN(0, 0);
149 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
150 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
151 if (pVCpu->iem.s.uVexLength == 0)
152 IEM_MC_COPY_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
153 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
154 else
155 IEM_MC_COPY_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
156 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
157 IEM_MC_ADVANCE_RIP();
158 IEM_MC_END();
159 }
160 else if (pVCpu->iem.s.uVexLength == 0)
161 {
162 /*
163 * 128-bit: Memory, register.
164 */
165 IEM_MC_BEGIN(0, 2);
166 IEM_MC_LOCAL(RTUINT128U, uSrc);
167 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
168
169 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
170 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
171 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
172 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
173
174 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
175 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
176
177 IEM_MC_ADVANCE_RIP();
178 IEM_MC_END();
179 }
180 else
181 {
182 /*
183 * 256-bit: Memory, register.
184 */
185 IEM_MC_BEGIN(0, 2);
186 IEM_MC_LOCAL(RTUINT256U, uSrc);
187 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
188
189 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
190 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
191 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
192 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
193
194 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
195 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
196
197 IEM_MC_ADVANCE_RIP();
198 IEM_MC_END();
199 }
200 return VINF_SUCCESS;
201}
202
203
204FNIEMOP_DEF(iemOp_vmovss_Vss_Hss_Wss)
205{
206 Assert(pVCpu->iem.s.uVexLength <= 1);
207 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
208 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
209 {
210 /**
211 * @opcode 0x10
212 * @oppfx 0xf3
213 * @opcodesub 11 mr/reg
214 * @opcpuid avx
215 * @opgroup og_avx_simdfp_datamerge
216 * @opxcpttype 5
217 * @optest op1=1 op2=0 op3=2 -> op1=2
218 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
219 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
220 * @optest op1=3 op2=-2 op3=0x77 -> op1=-8589934473
221 * @note HssHi refers to bits 127:32.
222 */
223 IEMOP_MNEMONIC3(VEX_RVM, VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE | IEMOPHINT_IGNORES_VEX_L);
224 IEMOP_HLP_DONE_VEX_DECODING();
225 IEM_MC_BEGIN(0, 0);
226
227 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
228 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
229 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
230 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB /*U32*/,
231 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
232 IEM_MC_ADVANCE_RIP();
233 IEM_MC_END();
234 }
235 else
236 {
237 /**
238 * @opdone
239 * @opcode 0x10
240 * @oppfx 0xf3
241 * @opcodesub 11 mr/reg
242 * @opcpuid avx
243 * @opgroup og_avx_simdfp_datamove
244 * @opxcpttype 5
245 * @opfunction iemOp_vmovss_Vss_Hss_Wss
246 * @optest op1=1 op2=2 -> op1=2
247 * @optest op1=0 op2=-22 -> op1=-22
248 */
249 IEMOP_MNEMONIC2(VEX_XM, VMOVSS, vmovss, VssZx_WO, Md, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE | IEMOPHINT_IGNORES_VEX_L);
250 IEM_MC_BEGIN(0, 2);
251 IEM_MC_LOCAL(uint32_t, uSrc);
252 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
253
254 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
255 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
256 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
257 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
258
259 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
260 IEM_MC_STORE_YREG_U32_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
261
262 IEM_MC_ADVANCE_RIP();
263 IEM_MC_END();
264 }
265
266 return VINF_SUCCESS;
267}
268
269
270FNIEMOP_DEF(iemOp_vmovsd_Vsd_Hsd_Wsd)
271{
272 Assert(pVCpu->iem.s.uVexLength <= 1);
273 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
274 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
275 {
276 /**
277 * @opcode 0x10
278 * @oppfx 0xf2
279 * @opcodesub 11 mr/reg
280 * @opcpuid avx
281 * @opgroup og_avx_simdfp_datamerge
282 * @opxcpttype 5
283 * @optest op1=1 op2=0 op3=2 -> op1=2
284 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
285 * @optest op1=3 op2=-1 op3=0x77 ->
286 * op1=0xffffffffffffffff0000000000000077
287 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x420000000000000077
288 */
289 IEMOP_MNEMONIC3(VEX_RVM, VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE | IEMOPHINT_IGNORES_VEX_L);
290 IEMOP_HLP_DONE_VEX_DECODING();
291 IEM_MC_BEGIN(0, 0);
292
293 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
294 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
295 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
296 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB /*U32*/,
297 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
298 IEM_MC_ADVANCE_RIP();
299 IEM_MC_END();
300 }
301 else
302 {
303 /**
304 * @opdone
305 * @opcode 0x10
306 * @oppfx 0xf2
307 * @opcodesub 11 mr/reg
308 * @opcpuid avx
309 * @opgroup og_avx_simdfp_datamove
310 * @opxcpttype 5
311 * @opfunction iemOp_vmovsd_Vsd_Hsd_Wsd
312 * @optest op1=1 op2=2 -> op1=2
313 * @optest op1=0 op2=-22 -> op1=-22
314 */
315 IEMOP_MNEMONIC2(VEX_XM, VMOVSD, vmovsd, VsdZx_WO, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE | IEMOPHINT_IGNORES_VEX_L);
316 IEM_MC_BEGIN(0, 2);
317 IEM_MC_LOCAL(uint64_t, uSrc);
318 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
319
320 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
321 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
322 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
323 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
324
325 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
326 IEM_MC_STORE_YREG_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
327
328 IEM_MC_ADVANCE_RIP();
329 IEM_MC_END();
330 }
331
332 return VINF_SUCCESS;
333}
334
335
336/**
337 * @opcode 0x11
338 * @oppfx none
339 * @opcpuid avx
340 * @opgroup og_avx_simdfp_datamove
341 * @opxcpttype 4UA
342 * @optest op1=1 op2=2 -> op1=2
343 * @optest op1=0 op2=-22 -> op1=-22
344 */
345FNIEMOP_DEF(iemOp_vmovups_Wps_Vps)
346{
347 IEMOP_MNEMONIC2(VEX_MR, VMOVUPS, vmovups, Wps_WO, Vps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
348 Assert(pVCpu->iem.s.uVexLength <= 1);
349 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
350 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
351 {
352 /*
353 * Register, register.
354 */
355 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
356 IEM_MC_BEGIN(0, 0);
357 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
358 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
359 if (pVCpu->iem.s.uVexLength == 0)
360 IEM_MC_COPY_YREG_U128_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
361 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
362 else
363 IEM_MC_COPY_YREG_U256_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
364 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
365 IEM_MC_ADVANCE_RIP();
366 IEM_MC_END();
367 }
368 else if (pVCpu->iem.s.uVexLength == 0)
369 {
370 /*
371 * 128-bit: Memory, register.
372 */
373 IEM_MC_BEGIN(0, 2);
374 IEM_MC_LOCAL(RTUINT128U, uSrc);
375 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
376
377 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
378 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
379 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
380 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
381
382 IEM_MC_FETCH_YREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
383 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
384
385 IEM_MC_ADVANCE_RIP();
386 IEM_MC_END();
387 }
388 else
389 {
390 /*
391 * 256-bit: Memory, register.
392 */
393 IEM_MC_BEGIN(0, 2);
394 IEM_MC_LOCAL(RTUINT256U, uSrc);
395 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
396
397 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
398 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
399 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
400 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
401
402 IEM_MC_FETCH_YREG_U256(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
403 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
404
405 IEM_MC_ADVANCE_RIP();
406 IEM_MC_END();
407 }
408 return VINF_SUCCESS;
409}
410
411
412/**
413 * @opcode 0x11
414 * @oppfx 0x66
415 * @opcpuid avx
416 * @opgroup og_avx_simdfp_datamove
417 * @opxcpttype 4UA
418 * @optest op1=1 op2=2 -> op1=2
419 * @optest op1=0 op2=-22 -> op1=-22
420 */
421FNIEMOP_DEF(iemOp_vmovupd_Wpd_Vpd)
422{
423 IEMOP_MNEMONIC2(VEX_MR, VMOVUPD, vmovupd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
424 Assert(pVCpu->iem.s.uVexLength <= 1);
425 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
426 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
427 {
428 /*
429 * Register, register.
430 */
431 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
432 IEM_MC_BEGIN(0, 0);
433 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
434 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
435 if (pVCpu->iem.s.uVexLength == 0)
436 IEM_MC_COPY_YREG_U128_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
437 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
438 else
439 IEM_MC_COPY_YREG_U256_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
440 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
441 IEM_MC_ADVANCE_RIP();
442 IEM_MC_END();
443 }
444 else if (pVCpu->iem.s.uVexLength == 0)
445 {
446 /*
447 * 128-bit: Memory, register.
448 */
449 IEM_MC_BEGIN(0, 2);
450 IEM_MC_LOCAL(RTUINT128U, uSrc);
451 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
452
453 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
454 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
455 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
456 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
457
458 IEM_MC_FETCH_YREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
459 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
460
461 IEM_MC_ADVANCE_RIP();
462 IEM_MC_END();
463 }
464 else
465 {
466 /*
467 * 256-bit: Memory, register.
468 */
469 IEM_MC_BEGIN(0, 2);
470 IEM_MC_LOCAL(RTUINT256U, uSrc);
471 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
472
473 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
474 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
475 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
476 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
477
478 IEM_MC_FETCH_YREG_U256(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
479 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
480
481 IEM_MC_ADVANCE_RIP();
482 IEM_MC_END();
483 }
484 return VINF_SUCCESS;
485}
486
487
488FNIEMOP_DEF(iemOp_vmovss_Wss_Hss_Vss)
489{
490 Assert(pVCpu->iem.s.uVexLength <= 1);
491 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
492 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
493 {
494 /**
495 * @opcode 0x11
496 * @oppfx 0xf3
497 * @opcodesub 11 mr/reg
498 * @opcpuid avx
499 * @opgroup og_avx_simdfp_datamerge
500 * @opxcpttype 5
501 * @optest op1=1 op2=0 op3=2 -> op1=2
502 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
503 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
504 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x4200000077
505 */
506 IEMOP_MNEMONIC3(VEX_MVR, VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE | IEMOPHINT_IGNORES_VEX_L);
507 IEMOP_HLP_DONE_VEX_DECODING();
508 IEM_MC_BEGIN(0, 0);
509
510 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
511 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
512 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB /*U32*/,
513 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
514 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
515 IEM_MC_ADVANCE_RIP();
516 IEM_MC_END();
517 }
518 else
519 {
520 /**
521 * @opdone
522 * @opcode 0x11
523 * @oppfx 0xf3
524 * @opcodesub 11 mr/reg
525 * @opcpuid avx
526 * @opgroup og_avx_simdfp_datamove
527 * @opxcpttype 5
528 * @opfunction iemOp_vmovss_Vss_Hss_Wss
529 * @optest op1=1 op2=2 -> op1=2
530 * @optest op1=0 op2=-22 -> op1=-22
531 */
532 IEMOP_MNEMONIC2(VEX_MR, VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE | IEMOPHINT_IGNORES_VEX_L);
533 IEM_MC_BEGIN(0, 2);
534 IEM_MC_LOCAL(uint32_t, uSrc);
535 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
536
537 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
538 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
539 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
540 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
541
542 IEM_MC_FETCH_YREG_U32(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
543 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
544
545 IEM_MC_ADVANCE_RIP();
546 IEM_MC_END();
547 }
548
549 return VINF_SUCCESS;
550}
551
552
553FNIEMOP_DEF(iemOp_vmovsd_Wsd_Hsd_Vsd)
554{
555 Assert(pVCpu->iem.s.uVexLength <= 1);
556 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
557 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
558 {
559 /**
560 * @opcode 0x11
561 * @oppfx 0xf2
562 * @opcodesub 11 mr/reg
563 * @opcpuid avx
564 * @opgroup og_avx_simdfp_datamerge
565 * @opxcpttype 5
566 * @optest op1=1 op2=0 op3=2 -> op1=2
567 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
568 * @optest op1=3 op2=-1 op3=0x77 ->
569 * op1=0xffffffffffffffff0000000000000077
570 * @optest op2=0x42 op3=0x77 -> op1=0x420000000000000077
571 */
572 IEMOP_MNEMONIC3(VEX_MVR, VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE | IEMOPHINT_IGNORES_VEX_L);
573 IEMOP_HLP_DONE_VEX_DECODING();
574 IEM_MC_BEGIN(0, 0);
575
576 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
577 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
578 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
579 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
580 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
581 IEM_MC_ADVANCE_RIP();
582 IEM_MC_END();
583 }
584 else
585 {
586 /**
587 * @opdone
588 * @opcode 0x11
589 * @oppfx 0xf2
590 * @opcodesub 11 mr/reg
591 * @opcpuid avx
592 * @opgroup og_avx_simdfp_datamove
593 * @opxcpttype 5
594 * @opfunction iemOp_vmovsd_Wsd_Hsd_Vsd
595 * @optest op1=1 op2=2 -> op1=2
596 * @optest op1=0 op2=-22 -> op1=-22
597 */
598 IEMOP_MNEMONIC2(VEX_MR, VMOVSD, vmovsd, Mq_WO, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE | IEMOPHINT_IGNORES_VEX_L);
599 IEM_MC_BEGIN(0, 2);
600 IEM_MC_LOCAL(uint64_t, uSrc);
601 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
602
603 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
604 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
605 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
606 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
607
608 IEM_MC_FETCH_YREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
609 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
610
611 IEM_MC_ADVANCE_RIP();
612 IEM_MC_END();
613 }
614
615 return VINF_SUCCESS;
616}
617
618
619FNIEMOP_DEF(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps)
620{
621 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
622 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
623 {
624 /**
625 * @opcode 0x12
626 * @opcodesub 11 mr/reg
627 * @oppfx none
628 * @opcpuid avx
629 * @opgroup og_avx_simdfp_datamerge
630 * @opxcpttype 7LZ
631 * @optest op2=0x2200220122022203
632 * op3=0x3304330533063307
633 * -> op1=0x22002201220222033304330533063307
634 * @optest op2=-1 op3=-42 -> op1=-42
635 * @note op3 and op2 are only the 8-byte high XMM register halfs.
636 */
637 IEMOP_MNEMONIC3(VEX_RVM, VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE | IEMOPHINT_VEX_L_ZERO);
638
639 IEMOP_HLP_DONE_VEX_DECODING_L0();
640 IEM_MC_BEGIN(0, 0);
641
642 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
643 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
644 IEM_MC_MERGE_YREG_U64HI_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
645 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
646 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
647
648 IEM_MC_ADVANCE_RIP();
649 IEM_MC_END();
650 }
651 else
652 {
653 /**
654 * @opdone
655 * @opcode 0x12
656 * @opcodesub !11 mr/reg
657 * @oppfx none
658 * @opcpuid avx
659 * @opgroup og_avx_simdfp_datamove
660 * @opxcpttype 5LZ
661 * @opfunction iemOp_vmovlps_Vq_Hq_Mq__vmovhlps
662 * @optest op1=1 op2=0 op3=0 -> op1=0
663 * @optest op1=0 op2=-1 op3=-1 -> op1=-1
664 * @optest op1=1 op2=2 op3=3 -> op1=0x20000000000000003
665 * @optest op2=-1 op3=0x42 -> op1=0xffffffffffffffff0000000000000042
666 */
667 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPS, vmovlps, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE | IEMOPHINT_VEX_L_ZERO);
668
669 IEM_MC_BEGIN(0, 2);
670 IEM_MC_LOCAL(uint64_t, uSrc);
671 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
672
673 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
674 IEMOP_HLP_DONE_VEX_DECODING_L0();
675 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
676 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
677
678 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
679 IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
680 uSrc,
681 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
682
683 IEM_MC_ADVANCE_RIP();
684 IEM_MC_END();
685 }
686 return VINF_SUCCESS;
687}
688
689
690/**
691 * @opcode 0x12
692 * @opcodesub !11 mr/reg
693 * @oppfx 0x66
694 * @opcpuid avx
695 * @opgroup og_avx_pcksclr_datamerge
696 * @opxcpttype 5LZ
697 * @optest op2=0 op3=2 -> op1=2
698 * @optest op2=0x22 op3=0x33 -> op1=0x220000000000000033
699 * @optest op2=0xfffffff0fffffff1 op3=0xeeeeeee8eeeeeee9
700 * -> op1=0xfffffff0fffffff1eeeeeee8eeeeeee9
701 */
702FNIEMOP_DEF(iemOp_vmovlpd_Vq_Hq_Mq)
703{
704 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
705 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
706 {
707 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPD, vmovlpd, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE | IEMOPHINT_VEX_L_ZERO);
708
709 IEM_MC_BEGIN(0, 2);
710 IEM_MC_LOCAL(uint64_t, uSrc);
711 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
712
713 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
714 IEMOP_HLP_DONE_VEX_DECODING_L0();
715 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
716 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
717
718 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
719 IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
720 uSrc,
721 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
722
723 IEM_MC_ADVANCE_RIP();
724 IEM_MC_END();
725 return VINF_SUCCESS;
726 }
727
728 /**
729 * @opdone
730 * @opmnemonic udvex660f12m3
731 * @opcode 0x12
732 * @opcodesub 11 mr/reg
733 * @oppfx 0x66
734 * @opunused immediate
735 * @opcpuid avx
736 * @optest ->
737 */
738 return IEMOP_RAISE_INVALID_OPCODE();
739}
740
741
742/**
743 * @opcode 0x12
744 * @oppfx 0xf3
745 * @opcpuid avx
746 * @opgroup og_avx_pcksclr_datamove
747 * @opxcpttype 4
748 * @optest vex.l==0 / op1=-1 op2=0xdddddddd00000002eeeeeeee00000001
749 * -> op1=0x00000002000000020000000100000001
750 * @optest vex.l==1 /
751 * op2=0xbbbbbbbb00000004cccccccc00000003dddddddd00000002eeeeeeee00000001
752 * -> op1=0x0000000400000004000000030000000300000002000000020000000100000001
753 */
754FNIEMOP_DEF(iemOp_vmovsldup_Vx_Wx)
755{
756 IEMOP_MNEMONIC2(VEX_RM, VMOVSLDUP, vmovsldup, Vx_WO, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
757 Assert(pVCpu->iem.s.uVexLength <= 1);
758 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
759 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
760 {
761 /*
762 * Register, register.
763 */
764 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
765 if (pVCpu->iem.s.uVexLength == 0)
766 {
767 IEM_MC_BEGIN(2, 0);
768 IEM_MC_ARG(PRTUINT128U, puDst, 0);
769 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
770
771 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
772 IEM_MC_PREPARE_AVX_USAGE();
773
774 IEM_MC_REF_XREG_U128_CONST(puSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
775 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
776 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
777 IEM_MC_CLEAR_YREG_128_UP(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
778
779 IEM_MC_ADVANCE_RIP();
780 IEM_MC_END();
781 }
782 else
783 {
784 IEM_MC_BEGIN(3, 0);
785 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
786 IEM_MC_ARG_CONST(uint8_t, iYRegDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 1);
787 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 2);
788
789 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
790 IEM_MC_PREPARE_AVX_USAGE();
791 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rr, iYRegDst, iYRegSrc);
792
793 IEM_MC_ADVANCE_RIP();
794 IEM_MC_END();
795 }
796 }
797 else
798 {
799 /*
800 * Register, memory.
801 */
802 if (pVCpu->iem.s.uVexLength == 0)
803 {
804 IEM_MC_BEGIN(2, 2);
805 IEM_MC_LOCAL(RTUINT128U, uSrc);
806 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
807 IEM_MC_ARG(PRTUINT128U, puDst, 0);
808 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
809
810 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
811 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
812 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
813 IEM_MC_PREPARE_AVX_USAGE();
814
815 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
816 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
817 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
818 IEM_MC_CLEAR_YREG_128_UP(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
819
820 IEM_MC_ADVANCE_RIP();
821 IEM_MC_END();
822 }
823 else
824 {
825 IEM_MC_BEGIN(3, 2);
826 IEM_MC_LOCAL(RTUINT256U, uSrc);
827 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
828 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
829 IEM_MC_ARG_CONST(uint8_t, iYRegDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 1);
830 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
831
832 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
833 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
834 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
835 IEM_MC_PREPARE_AVX_USAGE();
836
837 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
838 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rm, iYRegDst, puSrc);
839
840 IEM_MC_ADVANCE_RIP();
841 IEM_MC_END();
842 }
843 }
844 return VINF_SUCCESS;
845}
846
847
848/**
849 * @opcode 0x12
850 * @oppfx 0xf2
851 * @opcpuid avx
852 * @opgroup og_avx_pcksclr_datamove
853 * @opxcpttype 5
854 * @optest vex.l==0 / op2=0xddddddddeeeeeeee2222222211111111
855 * -> op1=0x22222222111111112222222211111111
856 * @optest vex.l==1 / op2=0xbbbbbbbbcccccccc4444444433333333ddddddddeeeeeeee2222222211111111
857 * -> op1=0x4444444433333333444444443333333322222222111111112222222211111111
858 */
859FNIEMOP_DEF(iemOp_vmovddup_Vx_Wx)
860{
861 IEMOP_MNEMONIC2(VEX_RM, VMOVDDUP, vmovddup, Vx_WO, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
862 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
863 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
864 {
865 /*
866 * Register, register.
867 */
868 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
869 if (pVCpu->iem.s.uVexLength == 0)
870 {
871 IEM_MC_BEGIN(2, 0);
872 IEM_MC_ARG(PRTUINT128U, puDst, 0);
873 IEM_MC_ARG(uint64_t, uSrc, 1);
874
875 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
876 IEM_MC_PREPARE_AVX_USAGE();
877
878 IEM_MC_FETCH_XREG_U64(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
879 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
880 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
881 IEM_MC_CLEAR_YREG_128_UP(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
882
883 IEM_MC_ADVANCE_RIP();
884 IEM_MC_END();
885 }
886 else
887 {
888 IEM_MC_BEGIN(3, 0);
889 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
890 IEM_MC_ARG_CONST(uint8_t, iYRegDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 1);
891 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 2);
892
893 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
894 IEM_MC_PREPARE_AVX_USAGE();
895 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rr, iYRegDst, iYRegSrc);
896
897 IEM_MC_ADVANCE_RIP();
898 IEM_MC_END();
899 }
900 }
901 else
902 {
903 /*
904 * Register, memory.
905 */
906 if (pVCpu->iem.s.uVexLength == 0)
907 {
908 IEM_MC_BEGIN(2, 2);
909 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
910 IEM_MC_ARG(PRTUINT128U, puDst, 0);
911 IEM_MC_ARG(uint64_t, uSrc, 1);
912
913 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
914 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
915 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
916 IEM_MC_PREPARE_AVX_USAGE();
917
918 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
919 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
920 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
921 IEM_MC_CLEAR_YREG_128_UP(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
922
923 IEM_MC_ADVANCE_RIP();
924 IEM_MC_END();
925 }
926 else
927 {
928 IEM_MC_BEGIN(3, 2);
929 IEM_MC_LOCAL(RTUINT256U, uSrc);
930 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
931 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
932 IEM_MC_ARG_CONST(uint8_t, iYRegDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 1);
933 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
934
935 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
936 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
937 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
938 IEM_MC_PREPARE_AVX_USAGE();
939
940 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
941 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rm, iYRegDst, puSrc);
942
943 IEM_MC_ADVANCE_RIP();
944 IEM_MC_END();
945 }
946 }
947 return VINF_SUCCESS;
948}
949
950
951/**
952 * @opcode 0x13
953 * @opcodesub !11 mr/reg
954 * @oppfx none
955 * @opcpuid avx
956 * @opgroup og_avx_simdfp_datamove
957 * @opxcpttype 5
958 * @optest op1=1 op2=2 -> op1=2
959 * @optest op1=0 op2=-42 -> op1=-42
960 */
961FNIEMOP_DEF(iemOp_vmovlps_Mq_Vq)
962{
963 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
964 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
965 {
966 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPS, vmovlps, Mq_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE | IEMOPHINT_VEX_L_ZERO);
967
968 IEM_MC_BEGIN(0, 2);
969 IEM_MC_LOCAL(uint64_t, uSrc);
970 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
971
972 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
973 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
974 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
975 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
976
977 IEM_MC_FETCH_YREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
978 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
979
980 IEM_MC_ADVANCE_RIP();
981 IEM_MC_END();
982 return VINF_SUCCESS;
983 }
984
985 /**
986 * @opdone
987 * @opmnemonic udvex0f13m3
988 * @opcode 0x13
989 * @opcodesub 11 mr/reg
990 * @oppfx none
991 * @opunused immediate
992 * @opcpuid avx
993 * @optest ->
994 */
995 return IEMOP_RAISE_INVALID_OPCODE();
996}
997
998
999/**
1000 * @opcode 0x13
1001 * @opcodesub !11 mr/reg
1002 * @oppfx 0x66
1003 * @opcpuid avx
1004 * @opgroup og_avx_pcksclr_datamove
1005 * @opxcpttype 5
1006 * @optest op1=1 op2=2 -> op1=2
1007 * @optest op1=0 op2=-42 -> op1=-42
1008 */
1009FNIEMOP_DEF(iemOp_vmovlpd_Mq_Vq)
1010{
1011 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1012 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1013 {
1014 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPD, vmovlpd, Mq_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE | IEMOPHINT_VEX_L_ZERO);
1015 IEM_MC_BEGIN(0, 2);
1016 IEM_MC_LOCAL(uint64_t, uSrc);
1017 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1018
1019 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1020 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1021 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1022 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1023
1024 IEM_MC_FETCH_YREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1025 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1026
1027 IEM_MC_ADVANCE_RIP();
1028 IEM_MC_END();
1029 return VINF_SUCCESS;
1030 }
1031
1032 /**
1033 * @opdone
1034 * @opmnemonic udvex660f13m3
1035 * @opcode 0x13
1036 * @opcodesub 11 mr/reg
1037 * @oppfx 0x66
1038 * @opunused immediate
1039 * @opcpuid avx
1040 * @optest ->
1041 */
1042 return IEMOP_RAISE_INVALID_OPCODE();
1043}
1044
1045/* Opcode VEX.F3.0F 0x13 - invalid */
1046/* Opcode VEX.F2.0F 0x13 - invalid */
1047
1048/** Opcode VEX.0F 0x14 - vunpcklps Vx, Hx, Wx*/
1049FNIEMOP_STUB(iemOp_vunpcklps_Vx_Hx_Wx);
1050/** Opcode VEX.66.0F 0x14 - vunpcklpd Vx,Hx,Wx */
1051FNIEMOP_STUB(iemOp_vunpcklpd_Vx_Hx_Wx);
1052/* Opcode VEX.F3.0F 0x14 - invalid */
1053/* Opcode VEX.F2.0F 0x14 - invalid */
1054/** Opcode VEX.0F 0x15 - vunpckhps Vx, Hx, Wx */
1055FNIEMOP_STUB(iemOp_vunpckhps_Vx_Hx_Wx);
1056/** Opcode VEX.66.0F 0x15 - vunpckhpd Vx,Hx,Wx */
1057FNIEMOP_STUB(iemOp_vunpckhpd_Vx_Hx_Wx);
1058/* Opcode VEX.F3.0F 0x15 - invalid */
1059/* Opcode VEX.F2.0F 0x15 - invalid */
1060/** Opcode VEX.0F 0x16 - vmovhpsv1 Vdq, Hq, Mq vmovlhps Vdq, Hq, Uq */
1061FNIEMOP_STUB(iemOp_vmovhpsv1_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq); //NEXT
1062/** Opcode VEX.66.0F 0x16 - vmovhpdv1 Vdq, Hq, Mq */
1063FNIEMOP_STUB(iemOp_vmovhpdv1_Vdq_Hq_Mq); //NEXT
1064/** Opcode VEX.F3.0F 0x16 - vmovshdup Vx, Wx */
1065FNIEMOP_STUB(iemOp_vmovshdup_Vx_Wx); //NEXT
1066/* Opcode VEX.F2.0F 0x16 - invalid */
1067/** Opcode VEX.0F 0x17 - vmovhpsv1 Mq, Vq */
1068FNIEMOP_STUB(iemOp_vmovhpsv1_Mq_Vq); //NEXT
1069/** Opcode VEX.66.0F 0x17 - vmovhpdv1 Mq, Vq */
1070FNIEMOP_STUB(iemOp_vmovhpdv1_Mq_Vq); //NEXT
1071/* Opcode VEX.F3.0F 0x17 - invalid */
1072/* Opcode VEX.F2.0F 0x17 - invalid */
1073
1074
1075/* Opcode VEX.0F 0x18 - invalid */
1076/* Opcode VEX.0F 0x19 - invalid */
1077/* Opcode VEX.0F 0x1a - invalid */
1078/* Opcode VEX.0F 0x1b - invalid */
1079/* Opcode VEX.0F 0x1c - invalid */
1080/* Opcode VEX.0F 0x1d - invalid */
1081/* Opcode VEX.0F 0x1e - invalid */
1082/* Opcode VEX.0F 0x1f - invalid */
1083
1084/* Opcode VEX.0F 0x20 - invalid */
1085/* Opcode VEX.0F 0x21 - invalid */
1086/* Opcode VEX.0F 0x22 - invalid */
1087/* Opcode VEX.0F 0x23 - invalid */
1088/* Opcode VEX.0F 0x24 - invalid */
1089/* Opcode VEX.0F 0x25 - invalid */
1090/* Opcode VEX.0F 0x26 - invalid */
1091/* Opcode VEX.0F 0x27 - invalid */
1092
1093/**
1094 * @opcode 0x28
1095 * @oppfx none
1096 * @opcpuid avx
1097 * @opgroup og_avx_pcksclr_datamove
1098 * @opxcpttype 1
1099 * @optest op1=1 op2=2 -> op1=2
1100 * @optest op1=0 op2=-42 -> op1=-42
1101 * @note Almost identical to vmovapd.
1102 */
1103FNIEMOP_DEF(iemOp_vmovaps_Vps_Wps)
1104{
1105 IEMOP_MNEMONIC2(VEX_RM, VMOVAPS, vmovaps, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
1106 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1107 Assert(pVCpu->iem.s.uVexLength <= 1);
1108 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1109 {
1110 /*
1111 * Register, register.
1112 */
1113 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1114 IEM_MC_BEGIN(1, 0);
1115
1116 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1117 IEM_MC_PREPARE_AVX_USAGE();
1118 if (pVCpu->iem.s.uVexLength == 0)
1119 IEM_MC_COPY_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1120 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1121 else
1122 IEM_MC_COPY_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1123 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1124 IEM_MC_ADVANCE_RIP();
1125 IEM_MC_END();
1126 }
1127 else
1128 {
1129 /*
1130 * Register, memory.
1131 */
1132 if (pVCpu->iem.s.uVexLength == 0)
1133 {
1134 IEM_MC_BEGIN(0, 2);
1135 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1136 IEM_MC_LOCAL(RTUINT128U, uSrc);
1137
1138 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1139 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1140 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1141 IEM_MC_PREPARE_AVX_USAGE();
1142
1143 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1144 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1145
1146 IEM_MC_ADVANCE_RIP();
1147 IEM_MC_END();
1148 }
1149 else
1150 {
1151 IEM_MC_BEGIN(0, 2);
1152 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1153 IEM_MC_LOCAL(RTUINT256U, uSrc);
1154
1155 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1156 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1157 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1158 IEM_MC_PREPARE_AVX_USAGE();
1159
1160 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1161 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1162
1163 IEM_MC_ADVANCE_RIP();
1164 IEM_MC_END();
1165 }
1166 }
1167 return VINF_SUCCESS;
1168}
1169
1170
1171/**
1172 * @opcode 0x28
1173 * @oppfx 66
1174 * @opcpuid avx
1175 * @opgroup og_avx_pcksclr_datamove
1176 * @opxcpttype 1
1177 * @optest op1=1 op2=2 -> op1=2
1178 * @optest op1=0 op2=-42 -> op1=-42
1179 * @note Almost identical to vmovaps
1180 */
1181FNIEMOP_DEF(iemOp_vmovapd_Vpd_Wpd)
1182{
1183 IEMOP_MNEMONIC2(VEX_RM, VMOVAPD, vmovapd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
1184 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1185 Assert(pVCpu->iem.s.uVexLength <= 1);
1186 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1187 {
1188 /*
1189 * Register, register.
1190 */
1191 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1192 IEM_MC_BEGIN(1, 0);
1193
1194 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1195 IEM_MC_PREPARE_AVX_USAGE();
1196 if (pVCpu->iem.s.uVexLength == 0)
1197 IEM_MC_COPY_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1198 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1199 else
1200 IEM_MC_COPY_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1201 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1202 IEM_MC_ADVANCE_RIP();
1203 IEM_MC_END();
1204 }
1205 else
1206 {
1207 /*
1208 * Register, memory.
1209 */
1210 if (pVCpu->iem.s.uVexLength == 0)
1211 {
1212 IEM_MC_BEGIN(0, 2);
1213 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1214 IEM_MC_LOCAL(RTUINT128U, uSrc);
1215
1216 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1217 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1218 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1219 IEM_MC_PREPARE_AVX_USAGE();
1220
1221 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1222 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1223
1224 IEM_MC_ADVANCE_RIP();
1225 IEM_MC_END();
1226 }
1227 else
1228 {
1229 IEM_MC_BEGIN(0, 2);
1230 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1231 IEM_MC_LOCAL(RTUINT256U, uSrc);
1232
1233 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1234 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1235 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1236 IEM_MC_PREPARE_AVX_USAGE();
1237
1238 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1239 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1240
1241 IEM_MC_ADVANCE_RIP();
1242 IEM_MC_END();
1243 }
1244 }
1245 return VINF_SUCCESS;
1246}
1247
1248/**
1249 * @opmnemonic udvexf30f28
1250 * @opcode 0x28
1251 * @oppfx 0xf3
1252 * @opunused vex.modrm
1253 * @opcpuid avx
1254 * @optest ->
1255 * @opdone
1256 */
1257
1258/**
1259 * @opmnemonic udvexf20f28
1260 * @opcode 0x28
1261 * @oppfx 0xf2
1262 * @opunused vex.modrm
1263 * @opcpuid avx
1264 * @optest ->
1265 * @opdone
1266 */
1267
1268/** Opcode VEX.0F 0x29 - vmovaps Wps, Vps */
1269FNIEMOP_STUB(iemOp_vmovaps_Wps_Vps);
1270//FNIEMOP_DEF(iemOp_vmovaps_Wps_Vps)
1271//{
1272// IEMOP_MNEMONIC(vmovaps_Wps_Vps, "vmovaps Wps,Vps");
1273// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1274// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1275// {
1276// /*
1277// * Register, register.
1278// */
1279// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1280// IEM_MC_BEGIN(0, 0);
1281// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1282// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1283// IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
1284// ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1285// IEM_MC_ADVANCE_RIP();
1286// IEM_MC_END();
1287// }
1288// else
1289// {
1290// /*
1291// * Memory, register.
1292// */
1293// IEM_MC_BEGIN(0, 2);
1294// IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1295// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1296//
1297// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1298// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1299// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1300// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1301//
1302// IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1303// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1304//
1305// IEM_MC_ADVANCE_RIP();
1306// IEM_MC_END();
1307// }
1308// return VINF_SUCCESS;
1309//}
1310
1311/** Opcode VEX.66.0F 0x29 - vmovapd Wpd,Vpd */
1312FNIEMOP_STUB(iemOp_vmovapd_Wpd_Vpd);
1313//FNIEMOP_DEF(iemOp_vmovapd_Wpd_Vpd)
1314//{
1315// IEMOP_MNEMONIC(vmovapd_Wpd_Vpd, "movapd Wpd,Vpd");
1316// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1317// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1318// {
1319// /*
1320// * Register, register.
1321// */
1322// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1323// IEM_MC_BEGIN(0, 0);
1324// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1325// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1326// IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
1327// ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1328// IEM_MC_ADVANCE_RIP();
1329// IEM_MC_END();
1330// }
1331// else
1332// {
1333// /*
1334// * Memory, register.
1335// */
1336// IEM_MC_BEGIN(0, 2);
1337// IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1338// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1339//
1340// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1341// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1342// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1343// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1344//
1345// IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1346// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1347//
1348// IEM_MC_ADVANCE_RIP();
1349// IEM_MC_END();
1350// }
1351// return VINF_SUCCESS;
1352//}
1353
1354/* Opcode VEX.F3.0F 0x29 - invalid */
1355/* Opcode VEX.F2.0F 0x29 - invalid */
1356
1357
1358/** Opcode VEX.0F 0x2a - invalid */
1359/** Opcode VEX.66.0F 0x2a - invalid */
1360/** Opcode VEX.F3.0F 0x2a - vcvtsi2ss Vss, Hss, Ey */
1361FNIEMOP_STUB(iemOp_vcvtsi2ss_Vss_Hss_Ey);
1362/** Opcode VEX.F2.0F 0x2a - vcvtsi2sd Vsd, Hsd, Ey */
1363FNIEMOP_STUB(iemOp_vcvtsi2sd_Vsd_Hsd_Ey);
1364
1365
1366/** Opcode VEX.0F 0x2b - vmovntps Mps, Vps */
1367FNIEMOP_STUB(iemOp_vmovntps_Mps_Vps);
1368//FNIEMOP_DEF(iemOp_vmovntps_Mps_Vps)
1369//{
1370// IEMOP_MNEMONIC(vmovntps_Mps_Vps, "movntps Mps,Vps");
1371// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1372// if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1373// {
1374// /*
1375// * memory, register.
1376// */
1377// IEM_MC_BEGIN(0, 2);
1378// IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1379// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1380//
1381// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1382// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1383// IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1384// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1385//
1386// IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1387// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1388//
1389// IEM_MC_ADVANCE_RIP();
1390// IEM_MC_END();
1391// }
1392// /* The register, register encoding is invalid. */
1393// else
1394// return IEMOP_RAISE_INVALID_OPCODE();
1395// return VINF_SUCCESS;
1396//}
1397
1398/** Opcode VEX.66.0F 0x2b - vmovntpd Mpd, Vpd */
1399FNIEMOP_STUB(iemOp_vmovntpd_Mpd_Vpd);
1400//FNIEMOP_DEF(iemOp_vmovntpd_Mpd_Vpd)
1401//{
1402// IEMOP_MNEMONIC(vmovntpd_Mpd_Vpd, "movntpd Mdq,Vpd");
1403// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1404// if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1405// {
1406// /*
1407// * memory, register.
1408// */
1409// IEM_MC_BEGIN(0, 2);
1410// IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1411// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1412//
1413// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1414// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1415// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1416// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1417//
1418// IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1419// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1420//
1421// IEM_MC_ADVANCE_RIP();
1422// IEM_MC_END();
1423// }
1424// /* The register, register encoding is invalid. */
1425// else
1426// return IEMOP_RAISE_INVALID_OPCODE();
1427// return VINF_SUCCESS;
1428//}
1429/* Opcode VEX.F3.0F 0x2b - invalid */
1430/* Opcode VEX.F2.0F 0x2b - invalid */
1431
1432
1433/* Opcode VEX.0F 0x2c - invalid */
1434/* Opcode VEX.66.0F 0x2c - invalid */
1435/** Opcode VEX.F3.0F 0x2c - vcvttss2si Gy, Wss */
1436FNIEMOP_STUB(iemOp_vcvttss2si_Gy_Wss);
1437/** Opcode VEX.F2.0F 0x2c - vcvttsd2si Gy, Wsd */
1438FNIEMOP_STUB(iemOp_vcvttsd2si_Gy_Wsd);
1439
1440/* Opcode VEX.0F 0x2d - invalid */
1441/* Opcode VEX.66.0F 0x2d - invalid */
1442/** Opcode VEX.F3.0F 0x2d - vcvtss2si Gy, Wss */
1443FNIEMOP_STUB(iemOp_vcvtss2si_Gy_Wss);
1444/** Opcode VEX.F2.0F 0x2d - vcvtsd2si Gy, Wsd */
1445FNIEMOP_STUB(iemOp_vcvtsd2si_Gy_Wsd);
1446
1447/** Opcode VEX.0F 0x2e - vucomiss Vss, Wss */
1448FNIEMOP_STUB(iemOp_vucomiss_Vss_Wss);
1449/** Opcode VEX.66.0F 0x2e - vucomisd Vsd, Wsd */
1450FNIEMOP_STUB(iemOp_vucomisd_Vsd_Wsd);
1451/* Opcode VEX.F3.0F 0x2e - invalid */
1452/* Opcode VEX.F2.0F 0x2e - invalid */
1453
1454/** Opcode VEX.0F 0x2f - vcomiss Vss, Wss */
1455FNIEMOP_STUB(iemOp_vcomiss_Vss_Wss);
1456/** Opcode VEX.66.0F 0x2f - vcomisd Vsd, Wsd */
1457FNIEMOP_STUB(iemOp_vcomisd_Vsd_Wsd);
1458/* Opcode VEX.F3.0F 0x2f - invalid */
1459/* Opcode VEX.F2.0F 0x2f - invalid */
1460
1461/* Opcode VEX.0F 0x30 - invalid */
1462/* Opcode VEX.0F 0x31 - invalid */
1463/* Opcode VEX.0F 0x32 - invalid */
1464/* Opcode VEX.0F 0x33 - invalid */
1465/* Opcode VEX.0F 0x34 - invalid */
1466/* Opcode VEX.0F 0x35 - invalid */
1467/* Opcode VEX.0F 0x36 - invalid */
1468/* Opcode VEX.0F 0x37 - invalid */
1469/* Opcode VEX.0F 0x38 - invalid */
1470/* Opcode VEX.0F 0x39 - invalid */
1471/* Opcode VEX.0F 0x3a - invalid */
1472/* Opcode VEX.0F 0x3b - invalid */
1473/* Opcode VEX.0F 0x3c - invalid */
1474/* Opcode VEX.0F 0x3d - invalid */
1475/* Opcode VEX.0F 0x3e - invalid */
1476/* Opcode VEX.0F 0x3f - invalid */
1477/* Opcode VEX.0F 0x40 - invalid */
1478/* Opcode VEX.0F 0x41 - invalid */
1479/* Opcode VEX.0F 0x42 - invalid */
1480/* Opcode VEX.0F 0x43 - invalid */
1481/* Opcode VEX.0F 0x44 - invalid */
1482/* Opcode VEX.0F 0x45 - invalid */
1483/* Opcode VEX.0F 0x46 - invalid */
1484/* Opcode VEX.0F 0x47 - invalid */
1485/* Opcode VEX.0F 0x48 - invalid */
1486/* Opcode VEX.0F 0x49 - invalid */
1487/* Opcode VEX.0F 0x4a - invalid */
1488/* Opcode VEX.0F 0x4b - invalid */
1489/* Opcode VEX.0F 0x4c - invalid */
1490/* Opcode VEX.0F 0x4d - invalid */
1491/* Opcode VEX.0F 0x4e - invalid */
1492/* Opcode VEX.0F 0x4f - invalid */
1493
1494/** Opcode VEX.0F 0x50 - vmovmskps Gy, Ups */
1495FNIEMOP_STUB(iemOp_vmovmskps_Gy_Ups);
1496/** Opcode VEX.66.0F 0x50 - vmovmskpd Gy,Upd */
1497FNIEMOP_STUB(iemOp_vmovmskpd_Gy_Upd);
1498/* Opcode VEX.F3.0F 0x50 - invalid */
1499/* Opcode VEX.F2.0F 0x50 - invalid */
1500
1501/** Opcode VEX.0F 0x51 - vsqrtps Vps, Wps */
1502FNIEMOP_STUB(iemOp_vsqrtps_Vps_Wps);
1503/** Opcode VEX.66.0F 0x51 - vsqrtpd Vpd, Wpd */
1504FNIEMOP_STUB(iemOp_vsqrtpd_Vpd_Wpd);
1505/** Opcode VEX.F3.0F 0x51 - vsqrtss Vss, Hss, Wss */
1506FNIEMOP_STUB(iemOp_vsqrtss_Vss_Hss_Wss);
1507/** Opcode VEX.F2.0F 0x51 - vsqrtsd Vsd, Hsd, Wsd */
1508FNIEMOP_STUB(iemOp_vsqrtsd_Vsd_Hsd_Wsd);
1509
1510/** Opcode VEX.0F 0x52 - vrsqrtps Vps, Wps */
1511FNIEMOP_STUB(iemOp_vrsqrtps_Vps_Wps);
1512/* Opcode VEX.66.0F 0x52 - invalid */
1513/** Opcode VEX.F3.0F 0x52 - vrsqrtss Vss, Hss, Wss */
1514FNIEMOP_STUB(iemOp_vrsqrtss_Vss_Hss_Wss);
1515/* Opcode VEX.F2.0F 0x52 - invalid */
1516
1517/** Opcode VEX.0F 0x53 - vrcpps Vps, Wps */
1518FNIEMOP_STUB(iemOp_vrcpps_Vps_Wps);
1519/* Opcode VEX.66.0F 0x53 - invalid */
1520/** Opcode VEX.F3.0F 0x53 - vrcpss Vss, Hss, Wss */
1521FNIEMOP_STUB(iemOp_vrcpss_Vss_Hss_Wss);
1522/* Opcode VEX.F2.0F 0x53 - invalid */
1523
1524/** Opcode VEX.0F 0x54 - vandps Vps, Hps, Wps */
1525FNIEMOP_STUB(iemOp_vandps_Vps_Hps_Wps);
1526/** Opcode VEX.66.0F 0x54 - vandpd Vpd, Hpd, Wpd */
1527FNIEMOP_STUB(iemOp_vandpd_Vpd_Hpd_Wpd);
1528/* Opcode VEX.F3.0F 0x54 - invalid */
1529/* Opcode VEX.F2.0F 0x54 - invalid */
1530
1531/** Opcode VEX.0F 0x55 - vandnps Vps, Hps, Wps */
1532FNIEMOP_STUB(iemOp_vandnps_Vps_Hps_Wps);
1533/** Opcode VEX.66.0F 0x55 - vandnpd Vpd, Hpd, Wpd */
1534FNIEMOP_STUB(iemOp_vandnpd_Vpd_Hpd_Wpd);
1535/* Opcode VEX.F3.0F 0x55 - invalid */
1536/* Opcode VEX.F2.0F 0x55 - invalid */
1537
1538/** Opcode VEX.0F 0x56 - vorps Vps, Hps, Wps */
1539FNIEMOP_STUB(iemOp_vorps_Vps_Hps_Wps);
1540/** Opcode VEX.66.0F 0x56 - vorpd Vpd, Hpd, Wpd */
1541FNIEMOP_STUB(iemOp_vorpd_Vpd_Hpd_Wpd);
1542/* Opcode VEX.F3.0F 0x56 - invalid */
1543/* Opcode VEX.F2.0F 0x56 - invalid */
1544
1545/** Opcode VEX.0F 0x57 - vxorps Vps, Hps, Wps */
1546FNIEMOP_STUB(iemOp_vxorps_Vps_Hps_Wps);
1547/** Opcode VEX.66.0F 0x57 - vxorpd Vpd, Hpd, Wpd */
1548FNIEMOP_STUB(iemOp_vxorpd_Vpd_Hpd_Wpd);
1549/* Opcode VEX.F3.0F 0x57 - invalid */
1550/* Opcode VEX.F2.0F 0x57 - invalid */
1551
1552/** Opcode VEX.0F 0x58 - vaddps Vps, Hps, Wps */
1553FNIEMOP_STUB(iemOp_vaddps_Vps_Hps_Wps);
1554/** Opcode VEX.66.0F 0x58 - vaddpd Vpd, Hpd, Wpd */
1555FNIEMOP_STUB(iemOp_vaddpd_Vpd_Hpd_Wpd);
1556/** Opcode VEX.F3.0F 0x58 - vaddss Vss, Hss, Wss */
1557FNIEMOP_STUB(iemOp_vaddss_Vss_Hss_Wss);
1558/** Opcode VEX.F2.0F 0x58 - vaddsd Vsd, Hsd, Wsd */
1559FNIEMOP_STUB(iemOp_vaddsd_Vsd_Hsd_Wsd);
1560
1561/** Opcode VEX.0F 0x59 - vmulps Vps, Hps, Wps */
1562FNIEMOP_STUB(iemOp_vmulps_Vps_Hps_Wps);
1563/** Opcode VEX.66.0F 0x59 - vmulpd Vpd, Hpd, Wpd */
1564FNIEMOP_STUB(iemOp_vmulpd_Vpd_Hpd_Wpd);
1565/** Opcode VEX.F3.0F 0x59 - vmulss Vss, Hss, Wss */
1566FNIEMOP_STUB(iemOp_vmulss_Vss_Hss_Wss);
1567/** Opcode VEX.F2.0F 0x59 - vmulsd Vsd, Hsd, Wsd */
1568FNIEMOP_STUB(iemOp_vmulsd_Vsd_Hsd_Wsd);
1569
1570/** Opcode VEX.0F 0x5a - vcvtps2pd Vpd, Wps */
1571FNIEMOP_STUB(iemOp_vcvtps2pd_Vpd_Wps);
1572/** Opcode VEX.66.0F 0x5a - vcvtpd2ps Vps, Wpd */
1573FNIEMOP_STUB(iemOp_vcvtpd2ps_Vps_Wpd);
1574/** Opcode VEX.F3.0F 0x5a - vcvtss2sd Vsd, Hx, Wss */
1575FNIEMOP_STUB(iemOp_vcvtss2sd_Vsd_Hx_Wss);
1576/** Opcode VEX.F2.0F 0x5a - vcvtsd2ss Vss, Hx, Wsd */
1577FNIEMOP_STUB(iemOp_vcvtsd2ss_Vss_Hx_Wsd);
1578
1579/** Opcode VEX.0F 0x5b - vcvtdq2ps Vps, Wdq */
1580FNIEMOP_STUB(iemOp_vcvtdq2ps_Vps_Wdq);
1581/** Opcode VEX.66.0F 0x5b - vcvtps2dq Vdq, Wps */
1582FNIEMOP_STUB(iemOp_vcvtps2dq_Vdq_Wps);
1583/** Opcode VEX.F3.0F 0x5b - vcvttps2dq Vdq, Wps */
1584FNIEMOP_STUB(iemOp_vcvttps2dq_Vdq_Wps);
1585/* Opcode VEX.F2.0F 0x5b - invalid */
1586
1587/** Opcode VEX.0F 0x5c - vsubps Vps, Hps, Wps */
1588FNIEMOP_STUB(iemOp_vsubps_Vps_Hps_Wps);
1589/** Opcode VEX.66.0F 0x5c - vsubpd Vpd, Hpd, Wpd */
1590FNIEMOP_STUB(iemOp_vsubpd_Vpd_Hpd_Wpd);
1591/** Opcode VEX.F3.0F 0x5c - vsubss Vss, Hss, Wss */
1592FNIEMOP_STUB(iemOp_vsubss_Vss_Hss_Wss);
1593/** Opcode VEX.F2.0F 0x5c - vsubsd Vsd, Hsd, Wsd */
1594FNIEMOP_STUB(iemOp_vsubsd_Vsd_Hsd_Wsd);
1595
1596/** Opcode VEX.0F 0x5d - vminps Vps, Hps, Wps */
1597FNIEMOP_STUB(iemOp_vminps_Vps_Hps_Wps);
1598/** Opcode VEX.66.0F 0x5d - vminpd Vpd, Hpd, Wpd */
1599FNIEMOP_STUB(iemOp_vminpd_Vpd_Hpd_Wpd);
1600/** Opcode VEX.F3.0F 0x5d - vminss Vss, Hss, Wss */
1601FNIEMOP_STUB(iemOp_vminss_Vss_Hss_Wss);
1602/** Opcode VEX.F2.0F 0x5d - vminsd Vsd, Hsd, Wsd */
1603FNIEMOP_STUB(iemOp_vminsd_Vsd_Hsd_Wsd);
1604
1605/** Opcode VEX.0F 0x5e - vdivps Vps, Hps, Wps */
1606FNIEMOP_STUB(iemOp_vdivps_Vps_Hps_Wps);
1607/** Opcode VEX.66.0F 0x5e - vdivpd Vpd, Hpd, Wpd */
1608FNIEMOP_STUB(iemOp_vdivpd_Vpd_Hpd_Wpd);
1609/** Opcode VEX.F3.0F 0x5e - vdivss Vss, Hss, Wss */
1610FNIEMOP_STUB(iemOp_vdivss_Vss_Hss_Wss);
1611/** Opcode VEX.F2.0F 0x5e - vdivsd Vsd, Hsd, Wsd */
1612FNIEMOP_STUB(iemOp_vdivsd_Vsd_Hsd_Wsd);
1613
1614/** Opcode VEX.0F 0x5f - vmaxps Vps, Hps, Wps */
1615FNIEMOP_STUB(iemOp_vmaxps_Vps_Hps_Wps);
1616/** Opcode VEX.66.0F 0x5f - vmaxpd Vpd, Hpd, Wpd */
1617FNIEMOP_STUB(iemOp_vmaxpd_Vpd_Hpd_Wpd);
1618/** Opcode VEX.F3.0F 0x5f - vmaxss Vss, Hss, Wss */
1619FNIEMOP_STUB(iemOp_vmaxss_Vss_Hss_Wss);
1620/** Opcode VEX.F2.0F 0x5f - vmaxsd Vsd, Hsd, Wsd */
1621FNIEMOP_STUB(iemOp_vmaxsd_Vsd_Hsd_Wsd);
1622
1623
1624///**
1625// * Common worker for SSE2 instructions on the forms:
1626// * pxxxx xmm1, xmm2/mem128
1627// *
1628// * The 2nd operand is the first half of a register, which in the memory case
1629// * means a 32-bit memory access for MMX and 128-bit aligned 64-bit or 128-bit
1630// * memory accessed for MMX.
1631// *
1632// * Exceptions type 4.
1633// */
1634//FNIEMOP_DEF_1(iemOpCommonSse_LowLow_To_Full, PCIEMOPMEDIAF1L1, pImpl)
1635//{
1636// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1637// if (!pImpl->pfnU64)
1638// return IEMOP_RAISE_INVALID_OPCODE();
1639// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1640// {
1641// /*
1642// * Register, register.
1643// */
1644// /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
1645// /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
1646// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1647// IEM_MC_BEGIN(2, 0);
1648// IEM_MC_ARG(uint64_t *, pDst, 0);
1649// IEM_MC_ARG(uint32_t const *, pSrc, 1);
1650// IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
1651// IEM_MC_PREPARE_FPU_USAGE();
1652// IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
1653// IEM_MC_REF_MREG_U32_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
1654// IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
1655// IEM_MC_ADVANCE_RIP();
1656// IEM_MC_END();
1657// }
1658// else
1659// {
1660// /*
1661// * Register, memory.
1662// */
1663// IEM_MC_BEGIN(2, 2);
1664// IEM_MC_ARG(uint64_t *, pDst, 0);
1665// IEM_MC_LOCAL(uint32_t, uSrc);
1666// IEM_MC_ARG_LOCAL_REF(uint32_t const *, pSrc, uSrc, 1);
1667// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1668//
1669// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1670// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1671// IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
1672// IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1673//
1674// IEM_MC_PREPARE_FPU_USAGE();
1675// IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
1676// IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
1677//
1678// IEM_MC_ADVANCE_RIP();
1679// IEM_MC_END();
1680// }
1681// return VINF_SUCCESS;
1682//}
1683
1684
1685/* Opcode VEX.0F 0x60 - invalid */
1686
1687/** Opcode VEX.66.0F 0x60 - vpunpcklbw Vx, Hx, W */
1688FNIEMOP_STUB(iemOp_vpunpcklbw_Vx_Hx_Wx);
1689//FNIEMOP_DEF(iemOp_vpunpcklbw_Vx_Hx_Wx)
1690//{
1691// IEMOP_MNEMONIC(vpunpcklbw, "vpunpcklbw Vx, Hx, Wx");
1692// return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklbw);
1693//}
1694
1695/* Opcode VEX.F3.0F 0x60 - invalid */
1696
1697
1698/* Opcode VEX.0F 0x61 - invalid */
1699
1700/** Opcode VEX.66.0F 0x61 - vpunpcklwd Vx, Hx, Wx */
1701FNIEMOP_STUB(iemOp_vpunpcklwd_Vx_Hx_Wx);
1702//FNIEMOP_DEF(iemOp_vpunpcklwd_Vx_Hx_Wx)
1703//{
1704// IEMOP_MNEMONIC(vpunpcklwd, "vpunpcklwd Vx, Hx, Wx");
1705// return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklwd);
1706//}
1707
1708/* Opcode VEX.F3.0F 0x61 - invalid */
1709
1710
1711/* Opcode VEX.0F 0x62 - invalid */
1712
1713/** Opcode VEX.66.0F 0x62 - vpunpckldq Vx, Hx, Wx */
1714FNIEMOP_STUB(iemOp_vpunpckldq_Vx_Hx_Wx);
1715//FNIEMOP_DEF(iemOp_vpunpckldq_Vx_Hx_Wx)
1716//{
1717// IEMOP_MNEMONIC(vpunpckldq, "vpunpckldq Vx, Hx, Wx");
1718// return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpckldq);
1719//}
1720
1721/* Opcode VEX.F3.0F 0x62 - invalid */
1722
1723
1724
1725/* Opcode VEX.0F 0x63 - invalid */
1726/** Opcode VEX.66.0F 0x63 - vpacksswb Vx, Hx, Wx */
1727FNIEMOP_STUB(iemOp_vpacksswb_Vx_Hx_Wx);
1728/* Opcode VEX.F3.0F 0x63 - invalid */
1729
1730/* Opcode VEX.0F 0x64 - invalid */
1731/** Opcode VEX.66.0F 0x64 - vpcmpgtb Vx, Hx, Wx */
1732FNIEMOP_STUB(iemOp_vpcmpgtb_Vx_Hx_Wx);
1733/* Opcode VEX.F3.0F 0x64 - invalid */
1734
1735/* Opcode VEX.0F 0x65 - invalid */
1736/** Opcode VEX.66.0F 0x65 - vpcmpgtw Vx, Hx, Wx */
1737FNIEMOP_STUB(iemOp_vpcmpgtw_Vx_Hx_Wx);
1738/* Opcode VEX.F3.0F 0x65 - invalid */
1739
1740/* Opcode VEX.0F 0x66 - invalid */
1741/** Opcode VEX.66.0F 0x66 - vpcmpgtd Vx, Hx, Wx */
1742FNIEMOP_STUB(iemOp_vpcmpgtd_Vx_Hx_Wx);
1743/* Opcode VEX.F3.0F 0x66 - invalid */
1744
1745/* Opcode VEX.0F 0x67 - invalid */
1746/** Opcode VEX.66.0F 0x67 - vpackuswb Vx, Hx, W */
1747FNIEMOP_STUB(iemOp_vpackuswb_Vx_Hx_W);
1748/* Opcode VEX.F3.0F 0x67 - invalid */
1749
1750
1751///**
1752// * Common worker for SSE2 instructions on the form:
1753// * pxxxx xmm1, xmm2/mem128
1754// *
1755// * The 2nd operand is the second half of a register, which in the memory case
1756// * means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
1757// * where it may read the full 128 bits or only the upper 64 bits.
1758// *
1759// * Exceptions type 4.
1760// */
1761//FNIEMOP_DEF_1(iemOpCommonSse_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
1762//{
1763// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1764// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1765// {
1766// /*
1767// * Register, register.
1768// */
1769// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1770// IEM_MC_BEGIN(2, 0);
1771// IEM_MC_ARG(PRTUINT128U, pDst, 0);
1772// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
1773// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1774// IEM_MC_PREPARE_SSE_USAGE();
1775// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1776// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1777// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
1778// IEM_MC_ADVANCE_RIP();
1779// IEM_MC_END();
1780// }
1781// else
1782// {
1783// /*
1784// * Register, memory.
1785// */
1786// IEM_MC_BEGIN(2, 2);
1787// IEM_MC_ARG(PRTUINT128U, pDst, 0);
1788// IEM_MC_LOCAL(RTUINT128U, uSrc);
1789// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
1790// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1791//
1792// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1793// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1794// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1795// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */
1796//
1797// IEM_MC_PREPARE_SSE_USAGE();
1798// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1799// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
1800//
1801// IEM_MC_ADVANCE_RIP();
1802// IEM_MC_END();
1803// }
1804// return VINF_SUCCESS;
1805//}
1806
1807
1808/* Opcode VEX.0F 0x68 - invalid */
1809
1810/** Opcode VEX.66.0F 0x68 - vpunpckhbw Vx, Hx, Wx */
1811FNIEMOP_STUB(iemOp_vpunpckhbw_Vx_Hx_Wx);
1812//FNIEMOP_DEF(iemOp_vpunpckhbw_Vx_Hx_Wx)
1813//{
1814// IEMOP_MNEMONIC(vpunpckhbw, "vpunpckhbw Vx, Hx, Wx");
1815// return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhbw);
1816//}
1817/* Opcode VEX.F3.0F 0x68 - invalid */
1818
1819
1820/* Opcode VEX.0F 0x69 - invalid */
1821
1822/** Opcode VEX.66.0F 0x69 - vpunpckhwd Vx, Hx, Wx */
1823FNIEMOP_STUB(iemOp_vpunpckhwd_Vx_Hx_Wx);
1824//FNIEMOP_DEF(iemOp_vpunpckhwd_Vx_Hx_Wx)
1825//{
1826// IEMOP_MNEMONIC(vpunpckhwd, "vpunpckhwd Vx, Hx, Wx");
1827// return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhwd);
1828//
1829//}
1830/* Opcode VEX.F3.0F 0x69 - invalid */
1831
1832
1833/* Opcode VEX.0F 0x6a - invalid */
1834
1835/** Opcode VEX.66.0F 0x6a - vpunpckhdq Vx, Hx, W */
1836FNIEMOP_STUB(iemOp_vpunpckhdq_Vx_Hx_W);
1837//FNIEMOP_DEF(iemOp_vpunpckhdq_Vx_Hx_W)
1838//{
1839// IEMOP_MNEMONIC(vpunpckhdq, "vpunpckhdq Vx, Hx, W");
1840// return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhdq);
1841//}
1842/* Opcode VEX.F3.0F 0x6a - invalid */
1843
1844
1845/* Opcode VEX.0F 0x6b - invalid */
1846/** Opcode VEX.66.0F 0x6b - vpackssdw Vx, Hx, Wx */
1847FNIEMOP_STUB(iemOp_vpackssdw_Vx_Hx_Wx);
1848/* Opcode VEX.F3.0F 0x6b - invalid */
1849
1850
1851/* Opcode VEX.0F 0x6c - invalid */
1852
1853/** Opcode VEX.66.0F 0x6c - vpunpcklqdq Vx, Hx, Wx */
1854FNIEMOP_STUB(iemOp_vpunpcklqdq_Vx_Hx_Wx);
1855//FNIEMOP_DEF(iemOp_vpunpcklqdq_Vx_Hx_Wx)
1856//{
1857// IEMOP_MNEMONIC(vpunpcklqdq, "vpunpcklqdq Vx, Hx, Wx");
1858// return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklqdq);
1859//}
1860
1861/* Opcode VEX.F3.0F 0x6c - invalid */
1862/* Opcode VEX.F2.0F 0x6c - invalid */
1863
1864
1865/* Opcode VEX.0F 0x6d - invalid */
1866
1867/** Opcode VEX.66.0F 0x6d - vpunpckhqdq Vx, Hx, W */
1868FNIEMOP_STUB(iemOp_vpunpckhqdq_Vx_Hx_W);
1869//FNIEMOP_DEF(iemOp_vpunpckhqdq_Vx_Hx_W)
1870//{
1871// IEMOP_MNEMONIC(punpckhqdq, "punpckhqdq");
1872// return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhqdq);
1873//}
1874
1875/* Opcode VEX.F3.0F 0x6d - invalid */
1876
1877
1878/* Opcode VEX.0F 0x6e - invalid */
1879
1880/** Opcode VEX.66.0F 0x6e - vmovd/q Vy, Ey */
1881FNIEMOP_STUB(iemOp_vmovd_q_Vy_Ey);
1882//FNIEMOP_DEF(iemOp_vmovd_q_Vy_Ey)
1883//{
1884// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1885// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1886// IEMOP_MNEMONIC(vmovdq_Wq_Eq, "vmovq Wq,Eq");
1887// else
1888// IEMOP_MNEMONIC(vmovdq_Wd_Ed, "vmovd Wd,Ed");
1889// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1890// {
1891// /* XMM, greg*/
1892// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1893// IEM_MC_BEGIN(0, 1);
1894// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1895// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1896// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1897// {
1898// IEM_MC_LOCAL(uint64_t, u64Tmp);
1899// IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1900// IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
1901// }
1902// else
1903// {
1904// IEM_MC_LOCAL(uint32_t, u32Tmp);
1905// IEM_MC_FETCH_GREG_U32(u32Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1906// IEM_MC_STORE_XREG_U32_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
1907// }
1908// IEM_MC_ADVANCE_RIP();
1909// IEM_MC_END();
1910// }
1911// else
1912// {
1913// /* XMM, [mem] */
1914// IEM_MC_BEGIN(0, 2);
1915// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1916// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); /** @todo order */
1917// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
1918// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1919// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1920// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1921// {
1922// IEM_MC_LOCAL(uint64_t, u64Tmp);
1923// IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1924// IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
1925// }
1926// else
1927// {
1928// IEM_MC_LOCAL(uint32_t, u32Tmp);
1929// IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1930// IEM_MC_STORE_XREG_U32_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
1931// }
1932// IEM_MC_ADVANCE_RIP();
1933// IEM_MC_END();
1934// }
1935// return VINF_SUCCESS;
1936//}
1937
1938/* Opcode VEX.F3.0F 0x6e - invalid */
1939
1940
1941/* Opcode VEX.0F 0x6f - invalid */
1942
1943/** Opcode VEX.66.0F 0x6f - vmovdqa Vx, Wx */
1944FNIEMOP_STUB(iemOp_vmovdqa_Vx_Wx);
1945//FNIEMOP_DEF(iemOp_vmovdqa_Vx_Wx)
1946//{
1947// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1948// IEMOP_MNEMONIC(vmovdqa_Vdq_Wdq, "movdqa Vdq,Wdq");
1949// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1950// {
1951// /*
1952// * Register, register.
1953// */
1954// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1955// IEM_MC_BEGIN(0, 0);
1956// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1957// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1958// IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1959// (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1960// IEM_MC_ADVANCE_RIP();
1961// IEM_MC_END();
1962// }
1963// else
1964// {
1965// /*
1966// * Register, memory.
1967// */
1968// IEM_MC_BEGIN(0, 2);
1969// IEM_MC_LOCAL(RTUINT128U, u128Tmp);
1970// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1971//
1972// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1973// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1974// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1975// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1976// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1977// IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u128Tmp);
1978//
1979// IEM_MC_ADVANCE_RIP();
1980// IEM_MC_END();
1981// }
1982// return VINF_SUCCESS;
1983//}
1984
1985/** Opcode VEX.F3.0F 0x6f - vmovdqu Vx, Wx */
1986FNIEMOP_STUB(iemOp_vmovdqu_Vx_Wx);
1987//FNIEMOP_DEF(iemOp_vmovdqu_Vx_Wx)
1988//{
1989// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1990// IEMOP_MNEMONIC(vmovdqu_Vdq_Wdq, "movdqu Vdq,Wdq");
1991// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1992// {
1993// /*
1994// * Register, register.
1995// */
1996// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1997// IEM_MC_BEGIN(0, 0);
1998// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1999// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2000// IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
2001// (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2002// IEM_MC_ADVANCE_RIP();
2003// IEM_MC_END();
2004// }
2005// else
2006// {
2007// /*
2008// * Register, memory.
2009// */
2010// IEM_MC_BEGIN(0, 2);
2011// IEM_MC_LOCAL(RTUINT128U, u128Tmp);
2012// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2013//
2014// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2015// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2016// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2017// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2018// IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2019// IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u128Tmp);
2020//
2021// IEM_MC_ADVANCE_RIP();
2022// IEM_MC_END();
2023// }
2024// return VINF_SUCCESS;
2025//}
2026
2027
2028/* Opcode VEX.0F 0x70 - invalid */
2029
2030/** Opcode VEX.66.0F 0x70 - vpshufd Vx, Wx, Ib */
2031FNIEMOP_STUB(iemOp_vpshufd_Vx_Wx_Ib);
2032//FNIEMOP_DEF(iemOp_vpshufd_Vx_Wx_Ib)
2033//{
2034// IEMOP_MNEMONIC(vpshufd_Vx_Wx_Ib, "vpshufd Vx,Wx,Ib");
2035// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2036// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2037// {
2038// /*
2039// * Register, register.
2040// */
2041// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
2042// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2043//
2044// IEM_MC_BEGIN(3, 0);
2045// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2046// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2047// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
2048// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2049// IEM_MC_PREPARE_SSE_USAGE();
2050// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2051// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2052// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufd, pDst, pSrc, bEvilArg);
2053// IEM_MC_ADVANCE_RIP();
2054// IEM_MC_END();
2055// }
2056// else
2057// {
2058// /*
2059// * Register, memory.
2060// */
2061// IEM_MC_BEGIN(3, 2);
2062// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2063// IEM_MC_LOCAL(RTUINT128U, uSrc);
2064// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
2065// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2066//
2067// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2068// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
2069// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
2070// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2071// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2072//
2073// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2074// IEM_MC_PREPARE_SSE_USAGE();
2075// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2076// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufd, pDst, pSrc, bEvilArg);
2077//
2078// IEM_MC_ADVANCE_RIP();
2079// IEM_MC_END();
2080// }
2081// return VINF_SUCCESS;
2082//}
2083
2084/** Opcode VEX.F3.0F 0x70 - vpshufhw Vx, Wx, Ib */
2085FNIEMOP_STUB(iemOp_vpshufhw_Vx_Wx_Ib);
2086//FNIEMOP_DEF(iemOp_vpshufhw_Vx_Wx_Ib)
2087//{
2088// IEMOP_MNEMONIC(vpshufhw_Vx_Wx_Ib, "vpshufhw Vx,Wx,Ib");
2089// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2090// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2091// {
2092// /*
2093// * Register, register.
2094// */
2095// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
2096// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2097//
2098// IEM_MC_BEGIN(3, 0);
2099// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2100// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2101// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
2102// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2103// IEM_MC_PREPARE_SSE_USAGE();
2104// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2105// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2106// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufhw, pDst, pSrc, bEvilArg);
2107// IEM_MC_ADVANCE_RIP();
2108// IEM_MC_END();
2109// }
2110// else
2111// {
2112// /*
2113// * Register, memory.
2114// */
2115// IEM_MC_BEGIN(3, 2);
2116// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2117// IEM_MC_LOCAL(RTUINT128U, uSrc);
2118// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
2119// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2120//
2121// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2122// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
2123// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
2124// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2125// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2126//
2127// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2128// IEM_MC_PREPARE_SSE_USAGE();
2129// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2130// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufhw, pDst, pSrc, bEvilArg);
2131//
2132// IEM_MC_ADVANCE_RIP();
2133// IEM_MC_END();
2134// }
2135// return VINF_SUCCESS;
2136//}
2137
2138/** Opcode VEX.F2.0F 0x70 - vpshuflw Vx, Wx, Ib */
2139FNIEMOP_STUB(iemOp_vpshuflw_Vx_Wx_Ib);
2140//FNIEMOP_DEF(iemOp_vpshuflw_Vx_Wx_Ib)
2141//{
2142// IEMOP_MNEMONIC(vpshuflw_Vx_Wx_Ib, "vpshuflw Vx,Wx,Ib");
2143// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2144// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2145// {
2146// /*
2147// * Register, register.
2148// */
2149// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
2150// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2151//
2152// IEM_MC_BEGIN(3, 0);
2153// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2154// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2155// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
2156// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2157// IEM_MC_PREPARE_SSE_USAGE();
2158// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2159// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2160// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshuflw, pDst, pSrc, bEvilArg);
2161// IEM_MC_ADVANCE_RIP();
2162// IEM_MC_END();
2163// }
2164// else
2165// {
2166// /*
2167// * Register, memory.
2168// */
2169// IEM_MC_BEGIN(3, 2);
2170// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2171// IEM_MC_LOCAL(RTUINT128U, uSrc);
2172// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
2173// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2174//
2175// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2176// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
2177// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
2178// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2179// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2180//
2181// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2182// IEM_MC_PREPARE_SSE_USAGE();
2183// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2184// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshuflw, pDst, pSrc, bEvilArg);
2185//
2186// IEM_MC_ADVANCE_RIP();
2187// IEM_MC_END();
2188// }
2189// return VINF_SUCCESS;
2190//}
2191
2192
2193/* Opcode VEX.0F 0x71 11/2 - invalid. */
2194/** Opcode VEX.66.0F 0x71 11/2. */
2195FNIEMOP_STUB_1(iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, uint8_t, bRm);
2196
2197/* Opcode VEX.0F 0x71 11/4 - invalid */
2198/** Opcode VEX.66.0F 0x71 11/4. */
2199FNIEMOP_STUB_1(iemOp_VGrp12_vpsraw_Hx_Ux_Ib, uint8_t, bRm);
2200
2201/* Opcode VEX.0F 0x71 11/6 - invalid */
2202/** Opcode VEX.66.0F 0x71 11/6. */
2203FNIEMOP_STUB_1(iemOp_VGrp12_vpsllw_Hx_Ux_Ib, uint8_t, bRm);
2204
2205
2206/**
2207 * VEX Group 12 jump table for register variant.
2208 */
2209IEM_STATIC const PFNIEMOPRM g_apfnVexGroup12RegReg[] =
2210{
2211 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2212 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2213 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2214 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2215 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsraw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2216 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2217 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsllw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2218 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
2219};
2220AssertCompile(RT_ELEMENTS(g_apfnVexGroup12RegReg) == 8*4);
2221
2222
2223/** Opcode VEX.0F 0x71. */
2224FNIEMOP_DEF(iemOp_VGrp12)
2225{
2226 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2227 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2228 /* register, register */
2229 return FNIEMOP_CALL_1(g_apfnVexGroup12RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
2230 + pVCpu->iem.s.idxPrefix], bRm);
2231 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
2232}
2233
2234
2235/* Opcode VEX.0F 0x72 11/2 - invalid. */
2236/** Opcode VEX.66.0F 0x72 11/2. */
2237FNIEMOP_STUB_1(iemOp_VGrp13_vpsrld_Hx_Ux_Ib, uint8_t, bRm);
2238
2239/* Opcode VEX.0F 0x72 11/4 - invalid. */
2240/** Opcode VEX.66.0F 0x72 11/4. */
2241FNIEMOP_STUB_1(iemOp_VGrp13_vpsrad_Hx_Ux_Ib, uint8_t, bRm);
2242
2243/* Opcode VEX.0F 0x72 11/6 - invalid. */
2244/** Opcode VEX.66.0F 0x72 11/6. */
2245FNIEMOP_STUB_1(iemOp_VGrp13_vpslld_Hx_Ux_Ib, uint8_t, bRm);
2246
2247
2248/**
2249 * Group 13 jump table for register variant.
2250 */
2251IEM_STATIC const PFNIEMOPRM g_apfnVexGroup13RegReg[] =
2252{
2253 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2254 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2255 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2256 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2257 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrad_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2258 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2259 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpslld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2260 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
2261};
2262AssertCompile(RT_ELEMENTS(g_apfnVexGroup13RegReg) == 8*4);
2263
2264/** Opcode VEX.0F 0x72. */
2265FNIEMOP_DEF(iemOp_VGrp13)
2266{
2267 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2268 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2269 /* register, register */
2270 return FNIEMOP_CALL_1(g_apfnVexGroup13RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
2271 + pVCpu->iem.s.idxPrefix], bRm);
2272 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
2273}
2274
2275
2276/* Opcode VEX.0F 0x73 11/2 - invalid. */
2277/** Opcode VEX.66.0F 0x73 11/2. */
2278FNIEMOP_STUB_1(iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, uint8_t, bRm);
2279
2280/** Opcode VEX.66.0F 0x73 11/3. */
2281FNIEMOP_STUB_1(iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, uint8_t, bRm);
2282
2283/* Opcode VEX.0F 0x73 11/6 - invalid. */
2284/** Opcode VEX.66.0F 0x73 11/6. */
2285FNIEMOP_STUB_1(iemOp_VGrp14_vpsllq_Hx_Ux_Ib, uint8_t, bRm);
2286
2287/** Opcode VEX.66.0F 0x73 11/7. */
2288FNIEMOP_STUB_1(iemOp_VGrp14_vpslldq_Hx_Ux_Ib, uint8_t, bRm);
2289
2290/**
2291 * Group 14 jump table for register variant.
2292 */
2293IEM_STATIC const PFNIEMOPRM g_apfnVexGroup14RegReg[] =
2294{
2295 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2296 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2297 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2298 /* /3 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2299 /* /4 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2300 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2301 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsllq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2302 /* /7 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpslldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2303};
2304AssertCompile(RT_ELEMENTS(g_apfnVexGroup14RegReg) == 8*4);
2305
2306
2307/** Opcode VEX.0F 0x73. */
2308FNIEMOP_DEF(iemOp_VGrp14)
2309{
2310 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2311 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2312 /* register, register */
2313 return FNIEMOP_CALL_1(g_apfnVexGroup14RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
2314 + pVCpu->iem.s.idxPrefix], bRm);
2315 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
2316}
2317
2318
2319///**
2320// * Common worker for SSE2 instructions on the forms:
2321// * pxxx xmm1, xmm2/mem128
2322// *
2323// * Proper alignment of the 128-bit operand is enforced.
2324// * Exceptions type 4. SSE2 cpuid checks.
2325// */
2326//FNIEMOP_DEF_1(iemOpCommonSse2_FullFull_To_Full, PCIEMOPMEDIAF2, pImpl)
2327//{
2328// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2329// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2330// {
2331// /*
2332// * Register, register.
2333// */
2334// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2335// IEM_MC_BEGIN(2, 0);
2336// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2337// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2338// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2339// IEM_MC_PREPARE_SSE_USAGE();
2340// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2341// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2342// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2343// IEM_MC_ADVANCE_RIP();
2344// IEM_MC_END();
2345// }
2346// else
2347// {
2348// /*
2349// * Register, memory.
2350// */
2351// IEM_MC_BEGIN(2, 2);
2352// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2353// IEM_MC_LOCAL(RTUINT128U, uSrc);
2354// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
2355// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2356//
2357// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2358// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2359// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2360// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2361//
2362// IEM_MC_PREPARE_SSE_USAGE();
2363// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2364// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2365//
2366// IEM_MC_ADVANCE_RIP();
2367// IEM_MC_END();
2368// }
2369// return VINF_SUCCESS;
2370//}
2371
2372
2373/* Opcode VEX.0F 0x74 - invalid */
2374
2375/** Opcode VEX.66.0F 0x74 - vpcmpeqb Vx, Hx, Wx */
2376FNIEMOP_STUB(iemOp_vpcmpeqb_Vx_Hx_Wx);
2377//FNIEMOP_DEF(iemOp_vpcmpeqb_Vx_Hx_Wx)
2378//{
2379// IEMOP_MNEMONIC(vpcmpeqb, "vpcmpeqb");
2380// return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqb);
2381//}
2382
2383/* Opcode VEX.F3.0F 0x74 - invalid */
2384/* Opcode VEX.F2.0F 0x74 - invalid */
2385
2386
2387/* Opcode VEX.0F 0x75 - invalid */
2388
2389/** Opcode VEX.66.0F 0x75 - vpcmpeqw Vx, Hx, Wx */
2390FNIEMOP_STUB(iemOp_vpcmpeqw_Vx_Hx_Wx);
2391//FNIEMOP_DEF(iemOp_vpcmpeqw_Vx_Hx_Wx)
2392//{
2393// IEMOP_MNEMONIC(vpcmpeqw, "vpcmpeqw");
2394// return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqw);
2395//}
2396
2397/* Opcode VEX.F3.0F 0x75 - invalid */
2398/* Opcode VEX.F2.0F 0x75 - invalid */
2399
2400
2401/* Opcode VEX.0F 0x76 - invalid */
2402
2403/** Opcode VEX.66.0F 0x76 - vpcmpeqd Vx, Hx, Wx */
2404FNIEMOP_STUB(iemOp_vpcmpeqd_Vx_Hx_Wx);
2405//FNIEMOP_DEF(iemOp_vpcmpeqd_Vx_Hx_Wx)
2406//{
2407// IEMOP_MNEMONIC(vpcmpeqd, "vpcmpeqd");
2408// return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqd);
2409//}
2410
2411/* Opcode VEX.F3.0F 0x76 - invalid */
2412/* Opcode VEX.F2.0F 0x76 - invalid */
2413
2414
2415/** Opcode VEX.0F 0x77 - vzeroupperv vzeroallv */
2416FNIEMOP_STUB(iemOp_vzeroupperv__vzeroallv);
2417/* Opcode VEX.66.0F 0x77 - invalid */
2418/* Opcode VEX.F3.0F 0x77 - invalid */
2419/* Opcode VEX.F2.0F 0x77 - invalid */
2420
2421/* Opcode VEX.0F 0x78 - invalid */
2422/* Opcode VEX.66.0F 0x78 - invalid */
2423/* Opcode VEX.F3.0F 0x78 - invalid */
2424/* Opcode VEX.F2.0F 0x78 - invalid */
2425
2426/* Opcode VEX.0F 0x79 - invalid */
2427/* Opcode VEX.66.0F 0x79 - invalid */
2428/* Opcode VEX.F3.0F 0x79 - invalid */
2429/* Opcode VEX.F2.0F 0x79 - invalid */
2430
2431/* Opcode VEX.0F 0x7a - invalid */
2432/* Opcode VEX.66.0F 0x7a - invalid */
2433/* Opcode VEX.F3.0F 0x7a - invalid */
2434/* Opcode VEX.F2.0F 0x7a - invalid */
2435
2436/* Opcode VEX.0F 0x7b - invalid */
2437/* Opcode VEX.66.0F 0x7b - invalid */
2438/* Opcode VEX.F3.0F 0x7b - invalid */
2439/* Opcode VEX.F2.0F 0x7b - invalid */
2440
2441/* Opcode VEX.0F 0x7c - invalid */
2442/** Opcode VEX.66.0F 0x7c - vhaddpd Vpd, Hpd, Wpd */
2443FNIEMOP_STUB(iemOp_vhaddpd_Vpd_Hpd_Wpd);
2444/* Opcode VEX.F3.0F 0x7c - invalid */
2445/** Opcode VEX.F2.0F 0x7c - vhaddps Vps, Hps, Wps */
2446FNIEMOP_STUB(iemOp_vhaddps_Vps_Hps_Wps);
2447
2448/* Opcode VEX.0F 0x7d - invalid */
2449/** Opcode VEX.66.0F 0x7d - vhsubpd Vpd, Hpd, Wpd */
2450FNIEMOP_STUB(iemOp_vhsubpd_Vpd_Hpd_Wpd);
2451/* Opcode VEX.F3.0F 0x7d - invalid */
2452/** Opcode VEX.F2.0F 0x7d - vhsubps Vps, Hps, Wps */
2453FNIEMOP_STUB(iemOp_vhsubps_Vps_Hps_Wps);
2454
2455
2456/* Opcode VEX.0F 0x7e - invalid */
2457
2458/** Opcode VEX.66.0F 0x7e - vmovd_q Ey, Vy */
2459FNIEMOP_STUB(iemOp_vmovd_q_Ey_Vy);
2460//FNIEMOP_DEF(iemOp_vmovd_q_Ey_Vy)
2461//{
2462// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2463// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2464// IEMOP_MNEMONIC(vmovq_Eq_Wq, "vmovq Eq,Wq");
2465// else
2466// IEMOP_MNEMONIC(vmovd_Ed_Wd, "vmovd Ed,Wd");
2467// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2468// {
2469// /* greg, XMM */
2470// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2471// IEM_MC_BEGIN(0, 1);
2472// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2473// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2474// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2475// {
2476// IEM_MC_LOCAL(uint64_t, u64Tmp);
2477// IEM_MC_FETCH_XREG_U64(u64Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2478// IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Tmp);
2479// }
2480// else
2481// {
2482// IEM_MC_LOCAL(uint32_t, u32Tmp);
2483// IEM_MC_FETCH_XREG_U32(u32Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2484// IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Tmp);
2485// }
2486// IEM_MC_ADVANCE_RIP();
2487// IEM_MC_END();
2488// }
2489// else
2490// {
2491// /* [mem], XMM */
2492// IEM_MC_BEGIN(0, 2);
2493// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2494// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2495// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
2496// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2497// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2498// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2499// {
2500// IEM_MC_LOCAL(uint64_t, u64Tmp);
2501// IEM_MC_FETCH_XREG_U64(u64Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2502// IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
2503// }
2504// else
2505// {
2506// IEM_MC_LOCAL(uint32_t, u32Tmp);
2507// IEM_MC_FETCH_XREG_U32(u32Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2508// IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
2509// }
2510// IEM_MC_ADVANCE_RIP();
2511// IEM_MC_END();
2512// }
2513// return VINF_SUCCESS;
2514//}
2515
2516/** Opcode VEX.F3.0F 0x7e - vmovq Vq, Wq */
2517FNIEMOP_STUB(iemOp_vmovq_Vq_Wq);
2518/* Opcode VEX.F2.0F 0x7e - invalid */
2519
2520
2521/* Opcode VEX.0F 0x7f - invalid */
2522
2523/** Opcode VEX.66.0F 0x7f - vmovdqa Wx,Vx */
2524FNIEMOP_STUB(iemOp_vmovdqa_Wx_Vx);
2525//FNIEMOP_DEF(iemOp_vmovdqa_Wx_Vx)
2526//{
2527// IEMOP_MNEMONIC(vmovdqa_Wdq_Vdq, "vmovdqa Wx,Vx");
2528// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2529// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2530// {
2531// /*
2532// * Register, register.
2533// */
2534// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2535// IEM_MC_BEGIN(0, 0);
2536// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2537// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2538// IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
2539// ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2540// IEM_MC_ADVANCE_RIP();
2541// IEM_MC_END();
2542// }
2543// else
2544// {
2545// /*
2546// * Register, memory.
2547// */
2548// IEM_MC_BEGIN(0, 2);
2549// IEM_MC_LOCAL(RTUINT128U, u128Tmp);
2550// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2551//
2552// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2553// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2554// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2555// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2556//
2557// IEM_MC_FETCH_XREG_U128(u128Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2558// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
2559//
2560// IEM_MC_ADVANCE_RIP();
2561// IEM_MC_END();
2562// }
2563// return VINF_SUCCESS;
2564//}
2565
2566/** Opcode VEX.F3.0F 0x7f - vmovdqu Wx,Vx */
2567FNIEMOP_STUB(iemOp_vmovdqu_Wx_Vx);
2568//FNIEMOP_DEF(iemOp_vmovdqu_Wx_Vx)
2569//{
2570// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2571// IEMOP_MNEMONIC(vmovdqu_Wdq_Vdq, "vmovdqu Wx,Vx");
2572// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2573// {
2574// /*
2575// * Register, register.
2576// */
2577// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2578// IEM_MC_BEGIN(0, 0);
2579// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2580// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2581// IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
2582// ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2583// IEM_MC_ADVANCE_RIP();
2584// IEM_MC_END();
2585// }
2586// else
2587// {
2588// /*
2589// * Register, memory.
2590// */
2591// IEM_MC_BEGIN(0, 2);
2592// IEM_MC_LOCAL(RTUINT128U, u128Tmp);
2593// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2594//
2595// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2596// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2597// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2598// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2599//
2600// IEM_MC_FETCH_XREG_U128(u128Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2601// IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
2602//
2603// IEM_MC_ADVANCE_RIP();
2604// IEM_MC_END();
2605// }
2606// return VINF_SUCCESS;
2607//}
2608
2609/* Opcode VEX.F2.0F 0x7f - invalid */
2610
2611
2612/* Opcode VEX.0F 0x80 - invalid */
2613/* Opcode VEX.0F 0x81 - invalid */
2614/* Opcode VEX.0F 0x82 - invalid */
2615/* Opcode VEX.0F 0x83 - invalid */
2616/* Opcode VEX.0F 0x84 - invalid */
2617/* Opcode VEX.0F 0x85 - invalid */
2618/* Opcode VEX.0F 0x86 - invalid */
2619/* Opcode VEX.0F 0x87 - invalid */
2620/* Opcode VEX.0F 0x88 - invalid */
2621/* Opcode VEX.0F 0x89 - invalid */
2622/* Opcode VEX.0F 0x8a - invalid */
2623/* Opcode VEX.0F 0x8b - invalid */
2624/* Opcode VEX.0F 0x8c - invalid */
2625/* Opcode VEX.0F 0x8d - invalid */
2626/* Opcode VEX.0F 0x8e - invalid */
2627/* Opcode VEX.0F 0x8f - invalid */
2628/* Opcode VEX.0F 0x90 - invalid */
2629/* Opcode VEX.0F 0x91 - invalid */
2630/* Opcode VEX.0F 0x92 - invalid */
2631/* Opcode VEX.0F 0x93 - invalid */
2632/* Opcode VEX.0F 0x94 - invalid */
2633/* Opcode VEX.0F 0x95 - invalid */
2634/* Opcode VEX.0F 0x96 - invalid */
2635/* Opcode VEX.0F 0x97 - invalid */
2636/* Opcode VEX.0F 0x98 - invalid */
2637/* Opcode VEX.0F 0x99 - invalid */
2638/* Opcode VEX.0F 0x9a - invalid */
2639/* Opcode VEX.0F 0x9b - invalid */
2640/* Opcode VEX.0F 0x9c - invalid */
2641/* Opcode VEX.0F 0x9d - invalid */
2642/* Opcode VEX.0F 0x9e - invalid */
2643/* Opcode VEX.0F 0x9f - invalid */
2644/* Opcode VEX.0F 0xa0 - invalid */
2645/* Opcode VEX.0F 0xa1 - invalid */
2646/* Opcode VEX.0F 0xa2 - invalid */
2647/* Opcode VEX.0F 0xa3 - invalid */
2648/* Opcode VEX.0F 0xa4 - invalid */
2649/* Opcode VEX.0F 0xa5 - invalid */
2650/* Opcode VEX.0F 0xa6 - invalid */
2651/* Opcode VEX.0F 0xa7 - invalid */
2652/* Opcode VEX.0F 0xa8 - invalid */
2653/* Opcode VEX.0F 0xa9 - invalid */
2654/* Opcode VEX.0F 0xaa - invalid */
2655/* Opcode VEX.0F 0xab - invalid */
2656/* Opcode VEX.0F 0xac - invalid */
2657/* Opcode VEX.0F 0xad - invalid */
2658
2659
2660/* Opcode VEX.0F 0xae mem/0 - invalid. */
2661/* Opcode VEX.0F 0xae mem/1 - invalid. */
2662
2663/**
2664 * @ opmaps grp15
2665 * @ opcode !11/2
2666 * @ oppfx none
2667 * @ opcpuid sse
2668 * @ opgroup og_sse_mxcsrsm
2669 * @ opxcpttype 5
2670 * @ optest op1=0 -> mxcsr=0
2671 * @ optest op1=0x2083 -> mxcsr=0x2083
2672 * @ optest op1=0xfffffffe -> value.xcpt=0xd
2673 * @ optest op1=0x2083 cr0|=ts -> value.xcpt=0x7
2674 * @ optest op1=0x2083 cr0|=em -> value.xcpt=0x6
2675 * @ optest op1=0x2083 cr0|=mp -> mxcsr=0x2083
2676 * @ optest op1=0x2083 cr4&~=osfxsr -> value.xcpt=0x6
2677 * @ optest op1=0x2083 cr0|=ts,em -> value.xcpt=0x6
2678 * @ optest op1=0x2083 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
2679 * @ optest op1=0x2083 cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
2680 * @ optest op1=0x2083 cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
2681 */
2682FNIEMOP_STUB_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm);
2683//FNIEMOP_DEF_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm)
2684//{
2685// IEMOP_MNEMONIC1(M_MEM, VLDMXCSR, vldmxcsr, MdRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
2686// if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse)
2687// return IEMOP_RAISE_INVALID_OPCODE();
2688//
2689// IEM_MC_BEGIN(2, 0);
2690// IEM_MC_ARG(uint8_t, iEffSeg, 0);
2691// IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
2692// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
2693// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2694// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2695// IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
2696// IEM_MC_CALL_CIMPL_2(iemCImpl_ldmxcsr, iEffSeg, GCPtrEff);
2697// IEM_MC_END();
2698// return VINF_SUCCESS;
2699//}
2700
2701
2702/**
2703 * @opmaps vexgrp15
2704 * @opcode !11/3
2705 * @oppfx none
2706 * @opcpuid avx
2707 * @opgroup og_avx_mxcsrsm
2708 * @opxcpttype 5
2709 * @optest mxcsr=0 -> op1=0
2710 * @optest mxcsr=0x2083 -> op1=0x2083
2711 * @optest mxcsr=0x2084 cr0|=ts -> value.xcpt=0x7
2712 * @optest !amd / mxcsr=0x2085 cr0|=em -> op1=0x2085
2713 * @optest amd / mxcsr=0x2085 cr0|=em -> value.xcpt=0x6
2714 * @optest mxcsr=0x2086 cr0|=mp -> op1=0x2086
2715 * @optest mxcsr=0x2087 cr4&~=osfxsr -> op1=0x2087
2716 * @optest mxcsr=0x208f cr4&~=osxsave -> value.xcpt=0x6
2717 * @optest mxcsr=0x2087 cr4&~=osfxsr,osxsave -> value.xcpt=0x6
2718 * @optest !amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x7
2719 * @optest amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x6
2720 * @optest !amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> op1=0x2089
2721 * @optest amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
2722 * @optest !amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x7
2723 * @optest amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
2724 * @optest !amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x7
2725 * @optest amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
2726 * @optest !amd / mxcsr=0x208c xcr0&~=all_avx -> value.xcpt=0x6
2727 * @optest amd / mxcsr=0x208c xcr0&~=all_avx -> op1=0x208c
2728 * @optest !amd / mxcsr=0x208d xcr0&~=all_avx_sse -> value.xcpt=0x6
2729 * @optest amd / mxcsr=0x208d xcr0&~=all_avx_sse -> op1=0x208d
2730 * @optest !amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x6
2731 * @optest amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x7
2732 * @optest mxcsr=0x2082 cr0|=ts cr4&~=osxsave -> value.xcpt=0x6
2733 * @optest mxcsr=0x2081 xcr0&~=all_avx cr0|=ts cr4&~=osxsave
2734 * -> value.xcpt=0x6
2735 * @remarks AMD Jaguar CPU (f0x16,m0,s1) \#UD when CR0.EM is set. It also
2736 * doesn't seem to check XCR0[2:1] != 11b. This does not match the
2737 * APMv4 rev 3.17 page 509.
2738 * @todo Test this instruction on AMD Ryzen.
2739 */
2740FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr, uint8_t, bRm)
2741{
2742 IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
2743 IEM_MC_BEGIN(2, 0);
2744 IEM_MC_ARG(uint8_t, iEffSeg, 0);
2745 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
2746 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
2747 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2748 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2749 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
2750 IEM_MC_CALL_CIMPL_2(iemCImpl_vstmxcsr, iEffSeg, GCPtrEff);
2751 IEM_MC_END();
2752 return VINF_SUCCESS;
2753}
2754
2755/* Opcode VEX.0F 0xae mem/4 - invalid. */
2756/* Opcode VEX.0F 0xae mem/5 - invalid. */
2757/* Opcode VEX.0F 0xae mem/6 - invalid. */
2758/* Opcode VEX.0F 0xae mem/7 - invalid. */
2759
2760/* Opcode VEX.0F 0xae 11b/0 - invalid. */
2761/* Opcode VEX.0F 0xae 11b/1 - invalid. */
2762/* Opcode VEX.0F 0xae 11b/2 - invalid. */
2763/* Opcode VEX.0F 0xae 11b/3 - invalid. */
2764/* Opcode VEX.0F 0xae 11b/4 - invalid. */
2765/* Opcode VEX.0F 0xae 11b/5 - invalid. */
2766/* Opcode VEX.0F 0xae 11b/6 - invalid. */
2767/* Opcode VEX.0F 0xae 11b/7 - invalid. */
2768
2769/**
2770 * Vex group 15 jump table for memory variant.
2771 */
2772IEM_STATIC const PFNIEMOPRM g_apfnVexGroup15MemReg[] =
2773{ /* pfx: none, 066h, 0f3h, 0f2h */
2774 /* /0 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2775 /* /1 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2776 /* /2 */ iemOp_VGrp15_vldmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2777 /* /3 */ iemOp_VGrp15_vstmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2778 /* /4 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2779 /* /5 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2780 /* /6 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2781 /* /7 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
2782};
2783AssertCompile(RT_ELEMENTS(g_apfnVexGroup15MemReg) == 8*4);
2784
2785
2786/** Opcode vex. 0xae. */
2787FNIEMOP_DEF(iemOp_VGrp15)
2788{
2789 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2790 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2791 /* register, register */
2792 return FNIEMOP_CALL_1(iemOp_InvalidWithRM, bRm);
2793
2794 /* memory, register */
2795 return FNIEMOP_CALL_1(g_apfnVexGroup15MemReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
2796 + pVCpu->iem.s.idxPrefix], bRm);
2797}
2798
2799
2800/* Opcode VEX.0F 0xaf - invalid. */
2801
2802/* Opcode VEX.0F 0xb0 - invalid. */
2803/* Opcode VEX.0F 0xb1 - invalid. */
2804/* Opcode VEX.0F 0xb2 - invalid. */
2805/* Opcode VEX.0F 0xb2 - invalid. */
2806/* Opcode VEX.0F 0xb3 - invalid. */
2807/* Opcode VEX.0F 0xb4 - invalid. */
2808/* Opcode VEX.0F 0xb5 - invalid. */
2809/* Opcode VEX.0F 0xb6 - invalid. */
2810/* Opcode VEX.0F 0xb7 - invalid. */
2811/* Opcode VEX.0F 0xb8 - invalid. */
2812/* Opcode VEX.0F 0xb9 - invalid. */
2813/* Opcode VEX.0F 0xba - invalid. */
2814/* Opcode VEX.0F 0xbb - invalid. */
2815/* Opcode VEX.0F 0xbc - invalid. */
2816/* Opcode VEX.0F 0xbd - invalid. */
2817/* Opcode VEX.0F 0xbe - invalid. */
2818/* Opcode VEX.0F 0xbf - invalid. */
2819
2820/* Opcode VEX.0F 0xc0 - invalid. */
2821/* Opcode VEX.66.0F 0xc0 - invalid. */
2822/* Opcode VEX.F3.0F 0xc0 - invalid. */
2823/* Opcode VEX.F2.0F 0xc0 - invalid. */
2824
2825/* Opcode VEX.0F 0xc1 - invalid. */
2826/* Opcode VEX.66.0F 0xc1 - invalid. */
2827/* Opcode VEX.F3.0F 0xc1 - invalid. */
2828/* Opcode VEX.F2.0F 0xc1 - invalid. */
2829
2830/** Opcode VEX.0F 0xc2 - vcmpps Vps,Hps,Wps,Ib */
2831FNIEMOP_STUB(iemOp_vcmpps_Vps_Hps_Wps_Ib);
2832/** Opcode VEX.66.0F 0xc2 - vcmppd Vpd,Hpd,Wpd,Ib */
2833FNIEMOP_STUB(iemOp_vcmppd_Vpd_Hpd_Wpd_Ib);
2834/** Opcode VEX.F3.0F 0xc2 - vcmpss Vss,Hss,Wss,Ib */
2835FNIEMOP_STUB(iemOp_vcmpss_Vss_Hss_Wss_Ib);
2836/** Opcode VEX.F2.0F 0xc2 - vcmpsd Vsd,Hsd,Wsd,Ib */
2837FNIEMOP_STUB(iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib);
2838
2839/* Opcode VEX.0F 0xc3 - invalid */
2840/* Opcode VEX.66.0F 0xc3 - invalid */
2841/* Opcode VEX.F3.0F 0xc3 - invalid */
2842/* Opcode VEX.F2.0F 0xc3 - invalid */
2843
2844/* Opcode VEX.0F 0xc4 - invalid */
2845/** Opcode VEX.66.0F 0xc4 - vpinsrw Vdq,Hdq,Ry/Mw,Ib */
2846FNIEMOP_STUB(iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib);
2847/* Opcode VEX.F3.0F 0xc4 - invalid */
2848/* Opcode VEX.F2.0F 0xc4 - invalid */
2849
2850/* Opcode VEX.0F 0xc5 - invlid */
2851/** Opcode VEX.66.0F 0xc5 - vpextrw Gd, Udq, Ib */
2852FNIEMOP_STUB(iemOp_vpextrw_Gd_Udq_Ib);
2853/* Opcode VEX.F3.0F 0xc5 - invalid */
2854/* Opcode VEX.F2.0F 0xc5 - invalid */
2855
2856/** Opcode VEX.0F 0xc6 - vshufps Vps,Hps,Wps,Ib */
2857FNIEMOP_STUB(iemOp_vshufps_Vps_Hps_Wps_Ib);
2858/** Opcode VEX.66.0F 0xc6 - vshufpd Vpd,Hpd,Wpd,Ib */
2859FNIEMOP_STUB(iemOp_vshufpd_Vpd_Hpd_Wpd_Ib);
2860/* Opcode VEX.F3.0F 0xc6 - invalid */
2861/* Opcode VEX.F2.0F 0xc6 - invalid */
2862
2863/* Opcode VEX.0F 0xc7 - invalid */
2864/* Opcode VEX.66.0F 0xc7 - invalid */
2865/* Opcode VEX.F3.0F 0xc7 - invalid */
2866/* Opcode VEX.F2.0F 0xc7 - invalid */
2867
2868/* Opcode VEX.0F 0xc8 - invalid */
2869/* Opcode VEX.0F 0xc9 - invalid */
2870/* Opcode VEX.0F 0xca - invalid */
2871/* Opcode VEX.0F 0xcb - invalid */
2872/* Opcode VEX.0F 0xcc - invalid */
2873/* Opcode VEX.0F 0xcd - invalid */
2874/* Opcode VEX.0F 0xce - invalid */
2875/* Opcode VEX.0F 0xcf - invalid */
2876
2877
2878/* Opcode VEX.0F 0xd0 - invalid */
2879/** Opcode VEX.66.0F 0xd0 - vaddsubpd Vpd, Hpd, Wpd */
2880FNIEMOP_STUB(iemOp_vaddsubpd_Vpd_Hpd_Wpd);
2881/* Opcode VEX.F3.0F 0xd0 - invalid */
2882/** Opcode VEX.F2.0F 0xd0 - vaddsubps Vps, Hps, Wps */
2883FNIEMOP_STUB(iemOp_vaddsubps_Vps_Hps_Wps);
2884
2885/* Opcode VEX.0F 0xd1 - invalid */
2886/** Opcode VEX.66.0F 0xd1 - vpsrlw Vx, Hx, W */
2887FNIEMOP_STUB(iemOp_vpsrlw_Vx_Hx_W);
2888/* Opcode VEX.F3.0F 0xd1 - invalid */
2889/* Opcode VEX.F2.0F 0xd1 - invalid */
2890
2891/* Opcode VEX.0F 0xd2 - invalid */
2892/** Opcode VEX.66.0F 0xd2 - vpsrld Vx, Hx, Wx */
2893FNIEMOP_STUB(iemOp_vpsrld_Vx_Hx_Wx);
2894/* Opcode VEX.F3.0F 0xd2 - invalid */
2895/* Opcode VEX.F2.0F 0xd2 - invalid */
2896
2897/* Opcode VEX.0F 0xd3 - invalid */
2898/** Opcode VEX.66.0F 0xd3 - vpsrlq Vx, Hx, Wx */
2899FNIEMOP_STUB(iemOp_vpsrlq_Vx_Hx_Wx);
2900/* Opcode VEX.F3.0F 0xd3 - invalid */
2901/* Opcode VEX.F2.0F 0xd3 - invalid */
2902
2903/* Opcode VEX.0F 0xd4 - invalid */
2904/** Opcode VEX.66.0F 0xd4 - vpaddq Vx, Hx, W */
2905FNIEMOP_STUB(iemOp_vpaddq_Vx_Hx_W);
2906/* Opcode VEX.F3.0F 0xd4 - invalid */
2907/* Opcode VEX.F2.0F 0xd4 - invalid */
2908
2909/* Opcode VEX.0F 0xd5 - invalid */
2910/** Opcode VEX.66.0F 0xd5 - vpmullw Vx, Hx, Wx */
2911FNIEMOP_STUB(iemOp_vpmullw_Vx_Hx_Wx);
2912/* Opcode VEX.F3.0F 0xd5 - invalid */
2913/* Opcode VEX.F2.0F 0xd5 - invalid */
2914
2915/* Opcode VEX.0F 0xd6 - invalid */
2916
2917/**
2918 * @ opcode 0xd6
2919 * @ oppfx 0x66
2920 * @ opcpuid sse2
2921 * @ opgroup og_sse2_pcksclr_datamove
2922 * @ opxcpttype none
2923 * @ optest op1=-1 op2=2 -> op1=2
2924 * @ optest op1=0 op2=-42 -> op1=-42
2925 */
2926FNIEMOP_STUB(iemOp_vmovq_Wq_Vq);
2927//FNIEMOP_DEF(iemOp_vmovq_Wq_Vq)
2928//{
2929// IEMOP_MNEMONIC2(MR, VMOVQ, vmovq, WqZxReg, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
2930// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2931// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2932// {
2933// /*
2934// * Register, register.
2935// */
2936// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2937// IEM_MC_BEGIN(0, 2);
2938// IEM_MC_LOCAL(uint64_t, uSrc);
2939//
2940// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2941// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2942//
2943// IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2944// IEM_MC_STORE_XREG_U64_ZX_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uSrc);
2945//
2946// IEM_MC_ADVANCE_RIP();
2947// IEM_MC_END();
2948// }
2949// else
2950// {
2951// /*
2952// * Memory, register.
2953// */
2954// IEM_MC_BEGIN(0, 2);
2955// IEM_MC_LOCAL(uint64_t, uSrc);
2956// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2957//
2958// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2959// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2960// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2961// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2962//
2963// IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2964// IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2965//
2966// IEM_MC_ADVANCE_RIP();
2967// IEM_MC_END();
2968// }
2969// return VINF_SUCCESS;
2970//}
2971
2972/* Opcode VEX.F3.0F 0xd6 - invalid */
2973/* Opcode VEX.F2.0F 0xd6 - invalid */
2974
2975
2976/* Opcode VEX.0F 0xd7 - invalid */
2977
2978/** Opcode VEX.66.0F 0xd7 - */
2979FNIEMOP_STUB(iemOp_vpmovmskb_Gd_Ux);
2980//FNIEMOP_DEF(iemOp_vpmovmskb_Gd_Ux)
2981//{
2982// /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
2983// /** @todo testcase: Check that the instruction implicitly clears the high
2984// * bits in 64-bit mode. The REX.W is first necessary when VLMAX > 256
2985// * and opcode modifications are made to work with the whole width (not
2986// * just 128). */
2987// IEMOP_MNEMONIC(vpmovmskb_Gd_Nq, "vpmovmskb Gd, Ux");
2988// /* Docs says register only. */
2989// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2990// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) /** @todo test that this is registers only. */
2991// {
2992// IEMOP_HLP_DECODED_NL_2(OP_PMOVMSKB, IEMOPFORM_RM_REG, OP_PARM_Gd, OP_PARM_Vdq, DISOPTYPE_SSE | DISOPTYPE_HARMLESS);
2993// IEM_MC_BEGIN(2, 0);
2994// IEM_MC_ARG(uint64_t *, pDst, 0);
2995// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2996// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2997// IEM_MC_PREPARE_SSE_USAGE();
2998// IEM_MC_REF_GREG_U64(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2999// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
3000// IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_pmovmskb_u128, pDst, pSrc);
3001// IEM_MC_ADVANCE_RIP();
3002// IEM_MC_END();
3003// return VINF_SUCCESS;
3004// }
3005// return IEMOP_RAISE_INVALID_OPCODE();
3006//}
3007
3008/* Opcode VEX.F3.0F 0xd7 - invalid */
3009/* Opcode VEX.F2.0F 0xd7 - invalid */
3010
3011
3012/* Opcode VEX.0F 0xd8 - invalid */
3013/** Opcode VEX.66.0F 0xd8 - vpsubusb Vx, Hx, W */
3014FNIEMOP_STUB(iemOp_vpsubusb_Vx_Hx_W);
3015/* Opcode VEX.F3.0F 0xd8 - invalid */
3016/* Opcode VEX.F2.0F 0xd8 - invalid */
3017
3018/* Opcode VEX.0F 0xd9 - invalid */
3019/** Opcode VEX.66.0F 0xd9 - vpsubusw Vx, Hx, Wx */
3020FNIEMOP_STUB(iemOp_vpsubusw_Vx_Hx_Wx);
3021/* Opcode VEX.F3.0F 0xd9 - invalid */
3022/* Opcode VEX.F2.0F 0xd9 - invalid */
3023
3024/* Opcode VEX.0F 0xda - invalid */
3025/** Opcode VEX.66.0F 0xda - vpminub Vx, Hx, Wx */
3026FNIEMOP_STUB(iemOp_vpminub_Vx_Hx_Wx);
3027/* Opcode VEX.F3.0F 0xda - invalid */
3028/* Opcode VEX.F2.0F 0xda - invalid */
3029
3030/* Opcode VEX.0F 0xdb - invalid */
3031/** Opcode VEX.66.0F 0xdb - vpand Vx, Hx, W */
3032FNIEMOP_STUB(iemOp_vpand_Vx_Hx_W);
3033/* Opcode VEX.F3.0F 0xdb - invalid */
3034/* Opcode VEX.F2.0F 0xdb - invalid */
3035
3036/* Opcode VEX.0F 0xdc - invalid */
3037/** Opcode VEX.66.0F 0xdc - vpaddusb Vx, Hx, Wx */
3038FNIEMOP_STUB(iemOp_vpaddusb_Vx_Hx_Wx);
3039/* Opcode VEX.F3.0F 0xdc - invalid */
3040/* Opcode VEX.F2.0F 0xdc - invalid */
3041
3042/* Opcode VEX.0F 0xdd - invalid */
3043/** Opcode VEX.66.0F 0xdd - vpaddusw Vx, Hx, Wx */
3044FNIEMOP_STUB(iemOp_vpaddusw_Vx_Hx_Wx);
3045/* Opcode VEX.F3.0F 0xdd - invalid */
3046/* Opcode VEX.F2.0F 0xdd - invalid */
3047
3048/* Opcode VEX.0F 0xde - invalid */
3049/** Opcode VEX.66.0F 0xde - vpmaxub Vx, Hx, W */
3050FNIEMOP_STUB(iemOp_vpmaxub_Vx_Hx_W);
3051/* Opcode VEX.F3.0F 0xde - invalid */
3052/* Opcode VEX.F2.0F 0xde - invalid */
3053
3054/* Opcode VEX.0F 0xdf - invalid */
3055/** Opcode VEX.66.0F 0xdf - vpandn Vx, Hx, Wx */
3056FNIEMOP_STUB(iemOp_vpandn_Vx_Hx_Wx);
3057/* Opcode VEX.F3.0F 0xdf - invalid */
3058/* Opcode VEX.F2.0F 0xdf - invalid */
3059
3060/* Opcode VEX.0F 0xe0 - invalid */
3061/** Opcode VEX.66.0F 0xe0 - vpavgb Vx, Hx, Wx */
3062FNIEMOP_STUB(iemOp_vpavgb_Vx_Hx_Wx);
3063/* Opcode VEX.F3.0F 0xe0 - invalid */
3064/* Opcode VEX.F2.0F 0xe0 - invalid */
3065
3066/* Opcode VEX.0F 0xe1 - invalid */
3067/** Opcode VEX.66.0F 0xe1 - vpsraw Vx, Hx, W */
3068FNIEMOP_STUB(iemOp_vpsraw_Vx_Hx_W);
3069/* Opcode VEX.F3.0F 0xe1 - invalid */
3070/* Opcode VEX.F2.0F 0xe1 - invalid */
3071
3072/* Opcode VEX.0F 0xe2 - invalid */
3073/** Opcode VEX.66.0F 0xe2 - vpsrad Vx, Hx, Wx */
3074FNIEMOP_STUB(iemOp_vpsrad_Vx_Hx_Wx);
3075/* Opcode VEX.F3.0F 0xe2 - invalid */
3076/* Opcode VEX.F2.0F 0xe2 - invalid */
3077
3078/* Opcode VEX.0F 0xe3 - invalid */
3079/** Opcode VEX.66.0F 0xe3 - vpavgw Vx, Hx, Wx */
3080FNIEMOP_STUB(iemOp_vpavgw_Vx_Hx_Wx);
3081/* Opcode VEX.F3.0F 0xe3 - invalid */
3082/* Opcode VEX.F2.0F 0xe3 - invalid */
3083
3084/* Opcode VEX.0F 0xe4 - invalid */
3085/** Opcode VEX.66.0F 0xe4 - vpmulhuw Vx, Hx, W */
3086FNIEMOP_STUB(iemOp_vpmulhuw_Vx_Hx_W);
3087/* Opcode VEX.F3.0F 0xe4 - invalid */
3088/* Opcode VEX.F2.0F 0xe4 - invalid */
3089
3090/* Opcode VEX.0F 0xe5 - invalid */
3091/** Opcode VEX.66.0F 0xe5 - vpmulhw Vx, Hx, Wx */
3092FNIEMOP_STUB(iemOp_vpmulhw_Vx_Hx_Wx);
3093/* Opcode VEX.F3.0F 0xe5 - invalid */
3094/* Opcode VEX.F2.0F 0xe5 - invalid */
3095
3096/* Opcode VEX.0F 0xe6 - invalid */
3097/** Opcode VEX.66.0F 0xe6 - vcvttpd2dq Vx, Wpd */
3098FNIEMOP_STUB(iemOp_vcvttpd2dq_Vx_Wpd);
3099/** Opcode VEX.F3.0F 0xe6 - vcvtdq2pd Vx, Wpd */
3100FNIEMOP_STUB(iemOp_vcvtdq2pd_Vx_Wpd);
3101/** Opcode VEX.F2.0F 0xe6 - vcvtpd2dq Vx, Wpd */
3102FNIEMOP_STUB(iemOp_vcvtpd2dq_Vx_Wpd);
3103
3104
3105/* Opcode VEX.0F 0xe7 - invalid */
3106
3107/** Opcode VEX.66.0F 0xe7 - vmovntdq Mx, Vx */
3108FNIEMOP_STUB(iemOp_vmovntdq_Mx_Vx);
3109//FNIEMOP_DEF(iemOp_vmovntdq_Mx_Vx)
3110//{
3111// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3112// if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
3113// {
3114// /* Register, memory. */
3115// IEMOP_MNEMONIC(vmovntdq_Mx_Vx, "vmovntdq Mx,Vx");
3116// IEM_MC_BEGIN(0, 2);
3117// IEM_MC_LOCAL(RTUINT128U, uSrc);
3118// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3119//
3120// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3121// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3122// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3123// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
3124//
3125// IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
3126// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
3127//
3128// IEM_MC_ADVANCE_RIP();
3129// IEM_MC_END();
3130// return VINF_SUCCESS;
3131// }
3132//
3133// /* The register, register encoding is invalid. */
3134// return IEMOP_RAISE_INVALID_OPCODE();
3135//}
3136
3137/* Opcode VEX.F3.0F 0xe7 - invalid */
3138/* Opcode VEX.F2.0F 0xe7 - invalid */
3139
3140
3141/* Opcode VEX.0F 0xe8 - invalid */
3142/** Opcode VEX.66.0F 0xe8 - vpsubsb Vx, Hx, W */
3143FNIEMOP_STUB(iemOp_vpsubsb_Vx_Hx_W);
3144/* Opcode VEX.F3.0F 0xe8 - invalid */
3145/* Opcode VEX.F2.0F 0xe8 - invalid */
3146
3147/* Opcode VEX.0F 0xe9 - invalid */
3148/** Opcode VEX.66.0F 0xe9 - vpsubsw Vx, Hx, Wx */
3149FNIEMOP_STUB(iemOp_vpsubsw_Vx_Hx_Wx);
3150/* Opcode VEX.F3.0F 0xe9 - invalid */
3151/* Opcode VEX.F2.0F 0xe9 - invalid */
3152
3153/* Opcode VEX.0F 0xea - invalid */
3154/** Opcode VEX.66.0F 0xea - vpminsw Vx, Hx, Wx */
3155FNIEMOP_STUB(iemOp_vpminsw_Vx_Hx_Wx);
3156/* Opcode VEX.F3.0F 0xea - invalid */
3157/* Opcode VEX.F2.0F 0xea - invalid */
3158
3159/* Opcode VEX.0F 0xeb - invalid */
3160/** Opcode VEX.66.0F 0xeb - vpor Vx, Hx, W */
3161FNIEMOP_STUB(iemOp_vpor_Vx_Hx_W);
3162/* Opcode VEX.F3.0F 0xeb - invalid */
3163/* Opcode VEX.F2.0F 0xeb - invalid */
3164
3165/* Opcode VEX.0F 0xec - invalid */
3166/** Opcode VEX.66.0F 0xec - vpaddsb Vx, Hx, Wx */
3167FNIEMOP_STUB(iemOp_vpaddsb_Vx_Hx_Wx);
3168/* Opcode VEX.F3.0F 0xec - invalid */
3169/* Opcode VEX.F2.0F 0xec - invalid */
3170
3171/* Opcode VEX.0F 0xed - invalid */
3172/** Opcode VEX.66.0F 0xed - vpaddsw Vx, Hx, Wx */
3173FNIEMOP_STUB(iemOp_vpaddsw_Vx_Hx_Wx);
3174/* Opcode VEX.F3.0F 0xed - invalid */
3175/* Opcode VEX.F2.0F 0xed - invalid */
3176
3177/* Opcode VEX.0F 0xee - invalid */
3178/** Opcode VEX.66.0F 0xee - vpmaxsw Vx, Hx, W */
3179FNIEMOP_STUB(iemOp_vpmaxsw_Vx_Hx_W);
3180/* Opcode VEX.F3.0F 0xee - invalid */
3181/* Opcode VEX.F2.0F 0xee - invalid */
3182
3183
3184/* Opcode VEX.0F 0xef - invalid */
3185
3186/** Opcode VEX.66.0F 0xef - vpxor Vx, Hx, Wx */
3187FNIEMOP_DEF(iemOp_vpxor_Vx_Hx_Wx)
3188{
3189 IEMOP_MNEMONIC(vpxor, "vpxor");
3190 return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pxor);
3191}
3192
3193/* Opcode VEX.F3.0F 0xef - invalid */
3194/* Opcode VEX.F2.0F 0xef - invalid */
3195
3196/* Opcode VEX.0F 0xf0 - invalid */
3197/* Opcode VEX.66.0F 0xf0 - invalid */
3198/** Opcode VEX.F2.0F 0xf0 - vlddqu Vx, Mx */
3199FNIEMOP_STUB(iemOp_vlddqu_Vx_Mx);
3200
3201/* Opcode VEX.0F 0xf1 - invalid */
3202/** Opcode VEX.66.0F 0xf1 - vpsllw Vx, Hx, W */
3203FNIEMOP_STUB(iemOp_vpsllw_Vx_Hx_W);
3204/* Opcode VEX.F2.0F 0xf1 - invalid */
3205
3206/* Opcode VEX.0F 0xf2 - invalid */
3207/** Opcode VEX.66.0F 0xf2 - vpslld Vx, Hx, Wx */
3208FNIEMOP_STUB(iemOp_vpslld_Vx_Hx_Wx);
3209/* Opcode VEX.F2.0F 0xf2 - invalid */
3210
3211/* Opcode VEX.0F 0xf3 - invalid */
3212/** Opcode VEX.66.0F 0xf3 - vpsllq Vx, Hx, Wx */
3213FNIEMOP_STUB(iemOp_vpsllq_Vx_Hx_Wx);
3214/* Opcode VEX.F2.0F 0xf3 - invalid */
3215
3216/* Opcode VEX.0F 0xf4 - invalid */
3217/** Opcode VEX.66.0F 0xf4 - vpmuludq Vx, Hx, W */
3218FNIEMOP_STUB(iemOp_vpmuludq_Vx_Hx_W);
3219/* Opcode VEX.F2.0F 0xf4 - invalid */
3220
3221/* Opcode VEX.0F 0xf5 - invalid */
3222/** Opcode VEX.66.0F 0xf5 - vpmaddwd Vx, Hx, Wx */
3223FNIEMOP_STUB(iemOp_vpmaddwd_Vx_Hx_Wx);
3224/* Opcode VEX.F2.0F 0xf5 - invalid */
3225
3226/* Opcode VEX.0F 0xf6 - invalid */
3227/** Opcode VEX.66.0F 0xf6 - vpsadbw Vx, Hx, Wx */
3228FNIEMOP_STUB(iemOp_vpsadbw_Vx_Hx_Wx);
3229/* Opcode VEX.F2.0F 0xf6 - invalid */
3230
3231/* Opcode VEX.0F 0xf7 - invalid */
3232/** Opcode VEX.66.0F 0xf7 - vmaskmovdqu Vdq, Udq */
3233FNIEMOP_STUB(iemOp_vmaskmovdqu_Vdq_Udq);
3234/* Opcode VEX.F2.0F 0xf7 - invalid */
3235
3236/* Opcode VEX.0F 0xf8 - invalid */
3237/** Opcode VEX.66.0F 0xf8 - vpsubb Vx, Hx, W */
3238FNIEMOP_STUB(iemOp_vpsubb_Vx_Hx_W);
3239/* Opcode VEX.F2.0F 0xf8 - invalid */
3240
3241/* Opcode VEX.0F 0xf9 - invalid */
3242/** Opcode VEX.66.0F 0xf9 - vpsubw Vx, Hx, Wx */
3243FNIEMOP_STUB(iemOp_vpsubw_Vx_Hx_Wx);
3244/* Opcode VEX.F2.0F 0xf9 - invalid */
3245
3246/* Opcode VEX.0F 0xfa - invalid */
3247/** Opcode VEX.66.0F 0xfa - vpsubd Vx, Hx, Wx */
3248FNIEMOP_STUB(iemOp_vpsubd_Vx_Hx_Wx);
3249/* Opcode VEX.F2.0F 0xfa - invalid */
3250
3251/* Opcode VEX.0F 0xfb - invalid */
3252/** Opcode VEX.66.0F 0xfb - vpsubq Vx, Hx, W */
3253FNIEMOP_STUB(iemOp_vpsubq_Vx_Hx_W);
3254/* Opcode VEX.F2.0F 0xfb - invalid */
3255
3256/* Opcode VEX.0F 0xfc - invalid */
3257/** Opcode VEX.66.0F 0xfc - vpaddb Vx, Hx, Wx */
3258FNIEMOP_STUB(iemOp_vpaddb_Vx_Hx_Wx);
3259/* Opcode VEX.F2.0F 0xfc - invalid */
3260
3261/* Opcode VEX.0F 0xfd - invalid */
3262/** Opcode VEX.66.0F 0xfd - vpaddw Vx, Hx, Wx */
3263FNIEMOP_STUB(iemOp_vpaddw_Vx_Hx_Wx);
3264/* Opcode VEX.F2.0F 0xfd - invalid */
3265
3266/* Opcode VEX.0F 0xfe - invalid */
3267/** Opcode VEX.66.0F 0xfe - vpaddd Vx, Hx, W */
3268FNIEMOP_STUB(iemOp_vpaddd_Vx_Hx_W);
3269/* Opcode VEX.F2.0F 0xfe - invalid */
3270
3271
3272/** Opcode **** 0x0f 0xff - UD0 */
3273FNIEMOP_DEF(iemOp_vud0)
3274{
3275 IEMOP_MNEMONIC(vud0, "vud0");
3276 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3277 {
3278 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
3279#ifndef TST_IEM_CHECK_MC
3280 RTGCPTR GCPtrEff;
3281 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
3282 if (rcStrict != VINF_SUCCESS)
3283 return rcStrict;
3284#endif
3285 IEMOP_HLP_DONE_DECODING();
3286 }
3287 return IEMOP_RAISE_INVALID_OPCODE();
3288}
3289
3290
3291
3292/**
3293 * VEX opcode map \#1.
3294 *
3295 * @sa g_apfnTwoByteMap
3296 */
3297IEM_STATIC const PFNIEMOP g_apfnVexMap1[] =
3298{
3299 /* no prefix, 066h prefix f3h prefix, f2h prefix */
3300 /* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRM),
3301 /* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRM),
3302 /* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRM),
3303 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRM),
3304 /* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRM),
3305 /* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRM),
3306 /* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRM),
3307 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRM),
3308 /* 0x08 */ IEMOP_X4(iemOp_InvalidNeedRM),
3309 /* 0x09 */ IEMOP_X4(iemOp_InvalidNeedRM),
3310 /* 0x0a */ IEMOP_X4(iemOp_InvalidNeedRM),
3311 /* 0x0b */ IEMOP_X4(iemOp_vud2), /* ?? */
3312 /* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
3313 /* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
3314 /* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
3315 /* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
3316
3317 /* 0x10 */ iemOp_vmovups_Vps_Wps, iemOp_vmovupd_Vpd_Wpd, iemOp_vmovss_Vss_Hss_Wss, iemOp_vmovsd_Vsd_Hsd_Wsd,
3318 /* 0x11 */ iemOp_vmovups_Wps_Vps, iemOp_vmovupd_Wpd_Vpd, iemOp_vmovss_Wss_Hss_Vss, iemOp_vmovsd_Wsd_Hsd_Vsd,
3319 /* 0x12 */ iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx, iemOp_vmovddup_Vx_Wx,
3320 /* 0x13 */ iemOp_vmovlps_Mq_Vq, iemOp_vmovlpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3321 /* 0x14 */ iemOp_vunpcklps_Vx_Hx_Wx, iemOp_vunpcklpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3322 /* 0x15 */ iemOp_vunpckhps_Vx_Hx_Wx, iemOp_vunpckhpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3323 /* 0x16 */ iemOp_vmovhpsv1_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq, iemOp_vmovhpdv1_Vdq_Hq_Mq, iemOp_vmovshdup_Vx_Wx, iemOp_InvalidNeedRM,
3324 /* 0x17 */ iemOp_vmovhpsv1_Mq_Vq, iemOp_vmovhpdv1_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3325 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
3326 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
3327 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
3328 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
3329 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRM),
3330 /* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRM),
3331 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRM),
3332 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
3333
3334 /* 0x20 */ IEMOP_X4(iemOp_InvalidNeedRM),
3335 /* 0x21 */ IEMOP_X4(iemOp_InvalidNeedRM),
3336 /* 0x22 */ IEMOP_X4(iemOp_InvalidNeedRM),
3337 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRM),
3338 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRM),
3339 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRM),
3340 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
3341 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
3342 /* 0x28 */ iemOp_vmovaps_Vps_Wps, iemOp_vmovapd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3343 /* 0x29 */ iemOp_vmovaps_Wps_Vps, iemOp_vmovapd_Wpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3344 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtsi2ss_Vss_Hss_Ey, iemOp_vcvtsi2sd_Vsd_Hsd_Ey,
3345 /* 0x2b */ iemOp_vmovntps_Mps_Vps, iemOp_vmovntpd_Mpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3346 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvttss2si_Gy_Wss, iemOp_vcvttsd2si_Gy_Wsd,
3347 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtss2si_Gy_Wss, iemOp_vcvtsd2si_Gy_Wsd,
3348 /* 0x2e */ iemOp_vucomiss_Vss_Wss, iemOp_vucomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3349 /* 0x2f */ iemOp_vcomiss_Vss_Wss, iemOp_vcomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3350
3351 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRM),
3352 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRM),
3353 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRM),
3354 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRM),
3355 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRM),
3356 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRM),
3357 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
3358 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRM),
3359 /* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3360 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3361 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3362 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3363 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3364 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3365 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3366 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3367
3368 /* 0x40 */ IEMOP_X4(iemOp_InvalidNeedRM),
3369 /* 0x41 */ IEMOP_X4(iemOp_InvalidNeedRM),
3370 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
3371 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
3372 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
3373 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
3374 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
3375 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
3376 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
3377 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
3378 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
3379 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
3380 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
3381 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
3382 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
3383 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
3384
3385 /* 0x50 */ iemOp_vmovmskps_Gy_Ups, iemOp_vmovmskpd_Gy_Upd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3386 /* 0x51 */ iemOp_vsqrtps_Vps_Wps, iemOp_vsqrtpd_Vpd_Wpd, iemOp_vsqrtss_Vss_Hss_Wss, iemOp_vsqrtsd_Vsd_Hsd_Wsd,
3387 /* 0x52 */ iemOp_vrsqrtps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrsqrtss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
3388 /* 0x53 */ iemOp_vrcpps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrcpss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
3389 /* 0x54 */ iemOp_vandps_Vps_Hps_Wps, iemOp_vandpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3390 /* 0x55 */ iemOp_vandnps_Vps_Hps_Wps, iemOp_vandnpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3391 /* 0x56 */ iemOp_vorps_Vps_Hps_Wps, iemOp_vorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3392 /* 0x57 */ iemOp_vxorps_Vps_Hps_Wps, iemOp_vxorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3393 /* 0x58 */ iemOp_vaddps_Vps_Hps_Wps, iemOp_vaddpd_Vpd_Hpd_Wpd, iemOp_vaddss_Vss_Hss_Wss, iemOp_vaddsd_Vsd_Hsd_Wsd,
3394 /* 0x59 */ iemOp_vmulps_Vps_Hps_Wps, iemOp_vmulpd_Vpd_Hpd_Wpd, iemOp_vmulss_Vss_Hss_Wss, iemOp_vmulsd_Vsd_Hsd_Wsd,
3395 /* 0x5a */ iemOp_vcvtps2pd_Vpd_Wps, iemOp_vcvtpd2ps_Vps_Wpd, iemOp_vcvtss2sd_Vsd_Hx_Wss, iemOp_vcvtsd2ss_Vss_Hx_Wsd,
3396 /* 0x5b */ iemOp_vcvtdq2ps_Vps_Wdq, iemOp_vcvtps2dq_Vdq_Wps, iemOp_vcvttps2dq_Vdq_Wps, iemOp_InvalidNeedRM,
3397 /* 0x5c */ iemOp_vsubps_Vps_Hps_Wps, iemOp_vsubpd_Vpd_Hpd_Wpd, iemOp_vsubss_Vss_Hss_Wss, iemOp_vsubsd_Vsd_Hsd_Wsd,
3398 /* 0x5d */ iemOp_vminps_Vps_Hps_Wps, iemOp_vminpd_Vpd_Hpd_Wpd, iemOp_vminss_Vss_Hss_Wss, iemOp_vminsd_Vsd_Hsd_Wsd,
3399 /* 0x5e */ iemOp_vdivps_Vps_Hps_Wps, iemOp_vdivpd_Vpd_Hpd_Wpd, iemOp_vdivss_Vss_Hss_Wss, iemOp_vdivsd_Vsd_Hsd_Wsd,
3400 /* 0x5f */ iemOp_vmaxps_Vps_Hps_Wps, iemOp_vmaxpd_Vpd_Hpd_Wpd, iemOp_vmaxss_Vss_Hss_Wss, iemOp_vmaxsd_Vsd_Hsd_Wsd,
3401
3402 /* 0x60 */ iemOp_InvalidNeedRM, iemOp_vpunpcklbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3403 /* 0x61 */ iemOp_InvalidNeedRM, iemOp_vpunpcklwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3404 /* 0x62 */ iemOp_InvalidNeedRM, iemOp_vpunpckldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3405 /* 0x63 */ iemOp_InvalidNeedRM, iemOp_vpacksswb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3406 /* 0x64 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3407 /* 0x65 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3408 /* 0x66 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3409 /* 0x67 */ iemOp_InvalidNeedRM, iemOp_vpackuswb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3410 /* 0x68 */ iemOp_InvalidNeedRM, iemOp_vpunpckhbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3411 /* 0x69 */ iemOp_InvalidNeedRM, iemOp_vpunpckhwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3412 /* 0x6a */ iemOp_InvalidNeedRM, iemOp_vpunpckhdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3413 /* 0x6b */ iemOp_InvalidNeedRM, iemOp_vpackssdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3414 /* 0x6c */ iemOp_InvalidNeedRM, iemOp_vpunpcklqdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3415 /* 0x6d */ iemOp_InvalidNeedRM, iemOp_vpunpckhqdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3416 /* 0x6e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Vy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3417 /* 0x6f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Vx_Wx, iemOp_vmovdqu_Vx_Wx, iemOp_InvalidNeedRM,
3418
3419 /* 0x70 */ iemOp_InvalidNeedRM, iemOp_vpshufd_Vx_Wx_Ib, iemOp_vpshufhw_Vx_Wx_Ib, iemOp_vpshuflw_Vx_Wx_Ib,
3420 /* 0x71 */ iemOp_InvalidNeedRM, iemOp_VGrp12, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3421 /* 0x72 */ iemOp_InvalidNeedRM, iemOp_VGrp13, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3422 /* 0x73 */ iemOp_InvalidNeedRM, iemOp_VGrp14, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3423 /* 0x74 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3424 /* 0x75 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3425 /* 0x76 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3426 /* 0x77 */ iemOp_vzeroupperv__vzeroallv, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3427 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
3428 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
3429 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
3430 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
3431 /* 0x7c */ iemOp_InvalidNeedRM, iemOp_vhaddpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhaddps_Vps_Hps_Wps,
3432 /* 0x7d */ iemOp_InvalidNeedRM, iemOp_vhsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhsubps_Vps_Hps_Wps,
3433 /* 0x7e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Ey_Vy, iemOp_vmovq_Vq_Wq, iemOp_InvalidNeedRM,
3434 /* 0x7f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Wx_Vx, iemOp_vmovdqu_Wx_Vx, iemOp_InvalidNeedRM,
3435
3436 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
3437 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
3438 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
3439 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
3440 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
3441 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
3442 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
3443 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
3444 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
3445 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
3446 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
3447 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
3448 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
3449 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
3450 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
3451 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
3452
3453 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
3454 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
3455 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
3456 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
3457 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
3458 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
3459 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
3460 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
3461 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
3462 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
3463 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
3464 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
3465 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
3466 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
3467 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
3468 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
3469
3470 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3471 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3472 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
3473 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3474 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
3475 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
3476 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
3477 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
3478 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
3479 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
3480 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
3481 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
3482 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
3483 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
3484 /* 0xae */ IEMOP_X4(iemOp_VGrp15),
3485 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
3486
3487 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3488 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3489 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
3490 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3491 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
3492 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
3493 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
3494 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
3495 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
3496 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
3497 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
3498 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
3499 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
3500 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
3501 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
3502 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
3503
3504 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3505 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3506 /* 0xc2 */ iemOp_vcmpps_Vps_Hps_Wps_Ib, iemOp_vcmppd_Vpd_Hpd_Wpd_Ib, iemOp_vcmpss_Vss_Hss_Wss_Ib, iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib,
3507 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3508 /* 0xc4 */ iemOp_InvalidNeedRM, iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
3509 /* 0xc5 */ iemOp_InvalidNeedRM, iemOp_vpextrw_Gd_Udq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
3510 /* 0xc6 */ iemOp_vshufps_Vps_Hps_Wps_Ib, iemOp_vshufpd_Vpd_Hpd_Wpd_Ib, iemOp_InvalidNeedRMImm8,iemOp_InvalidNeedRMImm8,
3511 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
3512 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
3513 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
3514 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
3515 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
3516 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
3517 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
3518 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
3519 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
3520
3521 /* 0xd0 */ iemOp_InvalidNeedRM, iemOp_vaddsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vaddsubps_Vps_Hps_Wps,
3522 /* 0xd1 */ iemOp_InvalidNeedRM, iemOp_vpsrlw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3523 /* 0xd2 */ iemOp_InvalidNeedRM, iemOp_vpsrld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3524 /* 0xd3 */ iemOp_InvalidNeedRM, iemOp_vpsrlq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3525 /* 0xd4 */ iemOp_InvalidNeedRM, iemOp_vpaddq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3526 /* 0xd5 */ iemOp_InvalidNeedRM, iemOp_vpmullw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3527 /* 0xd6 */ iemOp_InvalidNeedRM, iemOp_vmovq_Wq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3528 /* 0xd7 */ iemOp_InvalidNeedRM, iemOp_vpmovmskb_Gd_Ux, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3529 /* 0xd8 */ iemOp_InvalidNeedRM, iemOp_vpsubusb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3530 /* 0xd9 */ iemOp_InvalidNeedRM, iemOp_vpsubusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3531 /* 0xda */ iemOp_InvalidNeedRM, iemOp_vpminub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3532 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vpand_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3533 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vpaddusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3534 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vpaddusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3535 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vpmaxub_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3536 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vpandn_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3537
3538 /* 0xe0 */ iemOp_InvalidNeedRM, iemOp_vpavgb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3539 /* 0xe1 */ iemOp_InvalidNeedRM, iemOp_vpsraw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3540 /* 0xe2 */ iemOp_InvalidNeedRM, iemOp_vpsrad_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3541 /* 0xe3 */ iemOp_InvalidNeedRM, iemOp_vpavgw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3542 /* 0xe4 */ iemOp_InvalidNeedRM, iemOp_vpmulhuw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3543 /* 0xe5 */ iemOp_InvalidNeedRM, iemOp_vpmulhw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3544 /* 0xe6 */ iemOp_InvalidNeedRM, iemOp_vcvttpd2dq_Vx_Wpd, iemOp_vcvtdq2pd_Vx_Wpd, iemOp_vcvtpd2dq_Vx_Wpd,
3545 /* 0xe7 */ iemOp_InvalidNeedRM, iemOp_vmovntdq_Mx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3546 /* 0xe8 */ iemOp_InvalidNeedRM, iemOp_vpsubsb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3547 /* 0xe9 */ iemOp_InvalidNeedRM, iemOp_vpsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3548 /* 0xea */ iemOp_InvalidNeedRM, iemOp_vpminsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3549 /* 0xeb */ iemOp_InvalidNeedRM, iemOp_vpor_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3550 /* 0xec */ iemOp_InvalidNeedRM, iemOp_vpaddsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3551 /* 0xed */ iemOp_InvalidNeedRM, iemOp_vpaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3552 /* 0xee */ iemOp_InvalidNeedRM, iemOp_vpmaxsw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3553 /* 0xef */ iemOp_InvalidNeedRM, iemOp_vpxor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3554
3555 /* 0xf0 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vlddqu_Vx_Mx,
3556 /* 0xf1 */ iemOp_InvalidNeedRM, iemOp_vpsllw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3557 /* 0xf2 */ iemOp_InvalidNeedRM, iemOp_vpslld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3558 /* 0xf3 */ iemOp_InvalidNeedRM, iemOp_vpsllq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3559 /* 0xf4 */ iemOp_InvalidNeedRM, iemOp_vpmuludq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3560 /* 0xf5 */ iemOp_InvalidNeedRM, iemOp_vpmaddwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3561 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_vpsadbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3562 /* 0xf7 */ iemOp_InvalidNeedRM, iemOp_vmaskmovdqu_Vdq_Udq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3563 /* 0xf8 */ iemOp_InvalidNeedRM, iemOp_vpsubb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3564 /* 0xf9 */ iemOp_InvalidNeedRM, iemOp_vpsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3565 /* 0xfa */ iemOp_InvalidNeedRM, iemOp_vpsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3566 /* 0xfb */ iemOp_InvalidNeedRM, iemOp_vpsubq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3567 /* 0xfc */ iemOp_InvalidNeedRM, iemOp_vpaddb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3568 /* 0xfd */ iemOp_InvalidNeedRM, iemOp_vpaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3569 /* 0xfe */ iemOp_InvalidNeedRM, iemOp_vpaddd_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3570 /* 0xff */ IEMOP_X4(iemOp_vud0) /* ?? */
3571};
3572AssertCompile(RT_ELEMENTS(g_apfnVexMap1) == 1024);
3573/** @} */
3574
3575
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