VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h@ 67010

Last change on this file since 67010 was 67010, checked in by vboxsync, 8 years ago

IEM: Implemented vmovdqu Vx,Wx (VEX.F3.0F 6f).
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File size: 145.7 KB
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1/* $Id: IEMAllInstructionsVexMap1.cpp.h 67010 2017-05-22 12:11:21Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstructionsTwoByte0f.cpp.h is a legacy mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2016 Oracle Corporation
11 *
12 * This file is part of VirtualBox Open Source Edition (OSE), as
13 * available from http://www.virtualbox.org. This file is free software;
14 * you can redistribute it and/or modify it under the terms of the GNU
15 * General Public License (GPL) as published by the Free Software
16 * Foundation, in version 2 as it comes in the "COPYING" file of the
17 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19 */
20
21
22/** @name VEX Opcode Map 1
23 * @{
24 */
25
26
27/* Opcode VEX.0F 0x00 - invalid */
28/* Opcode VEX.0F 0x01 - invalid */
29/* Opcode VEX.0F 0x02 - invalid */
30/* Opcode VEX.0F 0x03 - invalid */
31/* Opcode VEX.0F 0x04 - invalid */
32/* Opcode VEX.0F 0x05 - invalid */
33/* Opcode VEX.0F 0x06 - invalid */
34/* Opcode VEX.0F 0x07 - invalid */
35/* Opcode VEX.0F 0x08 - invalid */
36/* Opcode VEX.0F 0x09 - invalid */
37/* Opcode VEX.0F 0x0a - invalid */
38
39/** Opcode VEX.0F 0x0b. */
40FNIEMOP_DEF(iemOp_vud2)
41{
42 IEMOP_MNEMONIC(vud2, "vud2");
43 return IEMOP_RAISE_INVALID_OPCODE();
44}
45
46/* Opcode VEX.0F 0x0c - invalid */
47/* Opcode VEX.0F 0x0d - invalid */
48/* Opcode VEX.0F 0x0e - invalid */
49/* Opcode VEX.0F 0x0f - invalid */
50
51
52/**
53 * @opcode 0x10
54 * @oppfx none
55 * @opcpuid avx
56 * @opgroup og_avx_simdfp_datamove
57 * @opxcpttype 4UA
58 * @optest op1=1 op2=2 -> op1=2
59 * @optest op1=0 op2=-22 -> op1=-22
60 */
61FNIEMOP_DEF(iemOp_vmovups_Vps_Wps)
62{
63 IEMOP_MNEMONIC2(VEX_RM, VMOVUPS, vmovups, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
64 Assert(pVCpu->iem.s.uVexLength <= 1);
65 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
66 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
67 {
68 /*
69 * Register, register.
70 */
71 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
72 IEM_MC_BEGIN(0, 0);
73 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
74 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
75 if (pVCpu->iem.s.uVexLength == 0)
76 IEM_MC_COPY_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
77 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
78 else
79 IEM_MC_COPY_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
80 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
81 IEM_MC_ADVANCE_RIP();
82 IEM_MC_END();
83 }
84 else if (pVCpu->iem.s.uVexLength == 0)
85 {
86 /*
87 * 128-bit: Memory, register.
88 */
89 IEM_MC_BEGIN(0, 2);
90 IEM_MC_LOCAL(RTUINT128U, uSrc);
91 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
92
93 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
94 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
95 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
96 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
97
98 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
99 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
100
101 IEM_MC_ADVANCE_RIP();
102 IEM_MC_END();
103 }
104 else
105 {
106 /*
107 * 256-bit: Memory, register.
108 */
109 IEM_MC_BEGIN(0, 2);
110 IEM_MC_LOCAL(RTUINT256U, uSrc);
111 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
112
113 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
114 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
115 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
116 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
117
118 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
119 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
120
121 IEM_MC_ADVANCE_RIP();
122 IEM_MC_END();
123 }
124 return VINF_SUCCESS;
125}
126
127
128/**
129 * @opcode 0x10
130 * @oppfx 0x66
131 * @opcpuid avx
132 * @opgroup og_avx_simdfp_datamove
133 * @opxcpttype 4UA
134 * @optest op1=1 op2=2 -> op1=2
135 * @optest op1=0 op2=-22 -> op1=-22
136 */
137FNIEMOP_DEF(iemOp_vmovupd_Vpd_Wpd)
138{
139 IEMOP_MNEMONIC2(VEX_RM, VMOVUPD, vmovupd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
140 Assert(pVCpu->iem.s.uVexLength <= 1);
141 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
142 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
143 {
144 /*
145 * Register, register.
146 */
147 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
148 IEM_MC_BEGIN(0, 0);
149 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
150 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
151 if (pVCpu->iem.s.uVexLength == 0)
152 IEM_MC_COPY_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
153 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
154 else
155 IEM_MC_COPY_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
156 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
157 IEM_MC_ADVANCE_RIP();
158 IEM_MC_END();
159 }
160 else if (pVCpu->iem.s.uVexLength == 0)
161 {
162 /*
163 * 128-bit: Memory, register.
164 */
165 IEM_MC_BEGIN(0, 2);
166 IEM_MC_LOCAL(RTUINT128U, uSrc);
167 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
168
169 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
170 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
171 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
172 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
173
174 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
175 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
176
177 IEM_MC_ADVANCE_RIP();
178 IEM_MC_END();
179 }
180 else
181 {
182 /*
183 * 256-bit: Memory, register.
184 */
185 IEM_MC_BEGIN(0, 2);
186 IEM_MC_LOCAL(RTUINT256U, uSrc);
187 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
188
189 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
190 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
191 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
192 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
193
194 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
195 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
196
197 IEM_MC_ADVANCE_RIP();
198 IEM_MC_END();
199 }
200 return VINF_SUCCESS;
201}
202
203
204FNIEMOP_DEF(iemOp_vmovss_Vss_Hss_Wss)
205{
206 Assert(pVCpu->iem.s.uVexLength <= 1);
207 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
208 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
209 {
210 /**
211 * @opcode 0x10
212 * @oppfx 0xf3
213 * @opcodesub 11 mr/reg
214 * @opcpuid avx
215 * @opgroup og_avx_simdfp_datamerge
216 * @opxcpttype 5
217 * @optest op1=1 op2=0 op3=2 -> op1=2
218 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
219 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
220 * @optest op1=3 op2=-2 op3=0x77 -> op1=-8589934473
221 * @note HssHi refers to bits 127:32.
222 */
223 IEMOP_MNEMONIC3(VEX_RVM, VMOVSS, vmovss, Vss_WO, HssHi, Uss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);
224 IEMOP_HLP_DONE_VEX_DECODING();
225 IEM_MC_BEGIN(0, 0);
226
227 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
228 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
229 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
230 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB /*U32*/,
231 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
232 IEM_MC_ADVANCE_RIP();
233 IEM_MC_END();
234 }
235 else
236 {
237 /**
238 * @opdone
239 * @opcode 0x10
240 * @oppfx 0xf3
241 * @opcodesub 11 mr/reg
242 * @opcpuid avx
243 * @opgroup og_avx_simdfp_datamove
244 * @opxcpttype 5
245 * @opfunction iemOp_vmovss_Vss_Hss_Wss
246 * @optest op1=1 op2=2 -> op1=2
247 * @optest op1=0 op2=-22 -> op1=-22
248 */
249 IEMOP_MNEMONIC2(VEX_XM, VMOVSS, vmovss, VssZx_WO, Md, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);
250 IEM_MC_BEGIN(0, 2);
251 IEM_MC_LOCAL(uint32_t, uSrc);
252 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
253
254 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
255 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
256 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
257 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
258
259 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
260 IEM_MC_STORE_YREG_U32_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
261
262 IEM_MC_ADVANCE_RIP();
263 IEM_MC_END();
264 }
265
266 return VINF_SUCCESS;
267}
268
269
270FNIEMOP_DEF(iemOp_vmovsd_Vsd_Hsd_Wsd)
271{
272 Assert(pVCpu->iem.s.uVexLength <= 1);
273 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
274 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
275 {
276 /**
277 * @opcode 0x10
278 * @oppfx 0xf2
279 * @opcodesub 11 mr/reg
280 * @opcpuid avx
281 * @opgroup og_avx_simdfp_datamerge
282 * @opxcpttype 5
283 * @optest op1=1 op2=0 op3=2 -> op1=2
284 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
285 * @optest op1=3 op2=-1 op3=0x77 ->
286 * op1=0xffffffffffffffff0000000000000077
287 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x420000000000000077
288 */
289 IEMOP_MNEMONIC3(VEX_RVM, VMOVSD, vmovsd, Vsd_WO, HsdHi, Usd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);
290 IEMOP_HLP_DONE_VEX_DECODING();
291 IEM_MC_BEGIN(0, 0);
292
293 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
294 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
295 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
296 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB /*U32*/,
297 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
298 IEM_MC_ADVANCE_RIP();
299 IEM_MC_END();
300 }
301 else
302 {
303 /**
304 * @opdone
305 * @opcode 0x10
306 * @oppfx 0xf2
307 * @opcodesub 11 mr/reg
308 * @opcpuid avx
309 * @opgroup og_avx_simdfp_datamove
310 * @opxcpttype 5
311 * @opfunction iemOp_vmovsd_Vsd_Hsd_Wsd
312 * @optest op1=1 op2=2 -> op1=2
313 * @optest op1=0 op2=-22 -> op1=-22
314 */
315 IEMOP_MNEMONIC2(VEX_XM, VMOVSD, vmovsd, VsdZx_WO, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);
316 IEM_MC_BEGIN(0, 2);
317 IEM_MC_LOCAL(uint64_t, uSrc);
318 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
319
320 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
321 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
322 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
323 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
324
325 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
326 IEM_MC_STORE_YREG_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
327
328 IEM_MC_ADVANCE_RIP();
329 IEM_MC_END();
330 }
331
332 return VINF_SUCCESS;
333}
334
335
336/**
337 * @opcode 0x11
338 * @oppfx none
339 * @opcpuid avx
340 * @opgroup og_avx_simdfp_datamove
341 * @opxcpttype 4UA
342 * @optest op1=1 op2=2 -> op1=2
343 * @optest op1=0 op2=-22 -> op1=-22
344 */
345FNIEMOP_DEF(iemOp_vmovups_Wps_Vps)
346{
347 IEMOP_MNEMONIC2(VEX_MR, VMOVUPS, vmovups, Wps_WO, Vps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
348 Assert(pVCpu->iem.s.uVexLength <= 1);
349 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
350 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
351 {
352 /*
353 * Register, register.
354 */
355 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
356 IEM_MC_BEGIN(0, 0);
357 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
358 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
359 if (pVCpu->iem.s.uVexLength == 0)
360 IEM_MC_COPY_YREG_U128_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
361 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
362 else
363 IEM_MC_COPY_YREG_U256_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
364 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
365 IEM_MC_ADVANCE_RIP();
366 IEM_MC_END();
367 }
368 else if (pVCpu->iem.s.uVexLength == 0)
369 {
370 /*
371 * 128-bit: Memory, register.
372 */
373 IEM_MC_BEGIN(0, 2);
374 IEM_MC_LOCAL(RTUINT128U, uSrc);
375 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
376
377 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
378 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
379 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
380 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
381
382 IEM_MC_FETCH_YREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
383 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
384
385 IEM_MC_ADVANCE_RIP();
386 IEM_MC_END();
387 }
388 else
389 {
390 /*
391 * 256-bit: Memory, register.
392 */
393 IEM_MC_BEGIN(0, 2);
394 IEM_MC_LOCAL(RTUINT256U, uSrc);
395 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
396
397 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
398 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
399 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
400 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
401
402 IEM_MC_FETCH_YREG_U256(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
403 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
404
405 IEM_MC_ADVANCE_RIP();
406 IEM_MC_END();
407 }
408 return VINF_SUCCESS;
409}
410
411
412/**
413 * @opcode 0x11
414 * @oppfx 0x66
415 * @opcpuid avx
416 * @opgroup og_avx_simdfp_datamove
417 * @opxcpttype 4UA
418 * @optest op1=1 op2=2 -> op1=2
419 * @optest op1=0 op2=-22 -> op1=-22
420 */
421FNIEMOP_DEF(iemOp_vmovupd_Wpd_Vpd)
422{
423 IEMOP_MNEMONIC2(VEX_MR, VMOVUPD, vmovupd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
424 Assert(pVCpu->iem.s.uVexLength <= 1);
425 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
426 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
427 {
428 /*
429 * Register, register.
430 */
431 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
432 IEM_MC_BEGIN(0, 0);
433 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
434 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
435 if (pVCpu->iem.s.uVexLength == 0)
436 IEM_MC_COPY_YREG_U128_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
437 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
438 else
439 IEM_MC_COPY_YREG_U256_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
440 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
441 IEM_MC_ADVANCE_RIP();
442 IEM_MC_END();
443 }
444 else if (pVCpu->iem.s.uVexLength == 0)
445 {
446 /*
447 * 128-bit: Memory, register.
448 */
449 IEM_MC_BEGIN(0, 2);
450 IEM_MC_LOCAL(RTUINT128U, uSrc);
451 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
452
453 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
454 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
455 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
456 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
457
458 IEM_MC_FETCH_YREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
459 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
460
461 IEM_MC_ADVANCE_RIP();
462 IEM_MC_END();
463 }
464 else
465 {
466 /*
467 * 256-bit: Memory, register.
468 */
469 IEM_MC_BEGIN(0, 2);
470 IEM_MC_LOCAL(RTUINT256U, uSrc);
471 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
472
473 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
474 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
475 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
476 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
477
478 IEM_MC_FETCH_YREG_U256(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
479 IEM_MC_STORE_MEM_U256(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
480
481 IEM_MC_ADVANCE_RIP();
482 IEM_MC_END();
483 }
484 return VINF_SUCCESS;
485}
486
487
488FNIEMOP_DEF(iemOp_vmovss_Wss_Hss_Vss)
489{
490 Assert(pVCpu->iem.s.uVexLength <= 1);
491 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
492 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
493 {
494 /**
495 * @opcode 0x11
496 * @oppfx 0xf3
497 * @opcodesub 11 mr/reg
498 * @opcpuid avx
499 * @opgroup og_avx_simdfp_datamerge
500 * @opxcpttype 5
501 * @optest op1=1 op2=0 op3=2 -> op1=2
502 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffea
503 * @optest op1=3 op2=-1 op3=0x77 -> op1=-4294967177
504 * @optest op1=3 op2=0x42 op3=0x77 -> op1=0x4200000077
505 */
506 IEMOP_MNEMONIC3(VEX_MVR, VMOVSS, vmovss, Uss_WO, HssHi, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);
507 IEMOP_HLP_DONE_VEX_DECODING();
508 IEM_MC_BEGIN(0, 0);
509
510 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
511 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
512 IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB /*U32*/,
513 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
514 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
515 IEM_MC_ADVANCE_RIP();
516 IEM_MC_END();
517 }
518 else
519 {
520 /**
521 * @opdone
522 * @opcode 0x11
523 * @oppfx 0xf3
524 * @opcodesub 11 mr/reg
525 * @opcpuid avx
526 * @opgroup og_avx_simdfp_datamove
527 * @opxcpttype 5
528 * @opfunction iemOp_vmovss_Vss_Hss_Wss
529 * @optest op1=1 op2=2 -> op1=2
530 * @optest op1=0 op2=-22 -> op1=-22
531 */
532 IEMOP_MNEMONIC2(VEX_MR, VMOVSS, vmovss, Md_WO, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);
533 IEM_MC_BEGIN(0, 2);
534 IEM_MC_LOCAL(uint32_t, uSrc);
535 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
536
537 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
538 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
539 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
540 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
541
542 IEM_MC_FETCH_YREG_U32(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
543 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
544
545 IEM_MC_ADVANCE_RIP();
546 IEM_MC_END();
547 }
548
549 return VINF_SUCCESS;
550}
551
552
553FNIEMOP_DEF(iemOp_vmovsd_Wsd_Hsd_Vsd)
554{
555 Assert(pVCpu->iem.s.uVexLength <= 1);
556 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
557 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
558 {
559 /**
560 * @opcode 0x11
561 * @oppfx 0xf2
562 * @opcodesub 11 mr/reg
563 * @opcpuid avx
564 * @opgroup og_avx_simdfp_datamerge
565 * @opxcpttype 5
566 * @optest op1=1 op2=0 op3=2 -> op1=2
567 * @optest op1=0 op2=0 op3=-22 -> op1=0xffffffffffffffea
568 * @optest op1=3 op2=-1 op3=0x77 ->
569 * op1=0xffffffffffffffff0000000000000077
570 * @optest op2=0x42 op3=0x77 -> op1=0x420000000000000077
571 */
572 IEMOP_MNEMONIC3(VEX_MVR, VMOVSD, vmovsd, Usd_WO, HsdHi, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);
573 IEMOP_HLP_DONE_VEX_DECODING();
574 IEM_MC_BEGIN(0, 0);
575
576 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
577 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
578 IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
579 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
580 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/);
581 IEM_MC_ADVANCE_RIP();
582 IEM_MC_END();
583 }
584 else
585 {
586 /**
587 * @opdone
588 * @opcode 0x11
589 * @oppfx 0xf2
590 * @opcodesub 11 mr/reg
591 * @opcpuid avx
592 * @opgroup og_avx_simdfp_datamove
593 * @opxcpttype 5
594 * @opfunction iemOp_vmovsd_Wsd_Hsd_Vsd
595 * @optest op1=1 op2=2 -> op1=2
596 * @optest op1=0 op2=-22 -> op1=-22
597 */
598 IEMOP_MNEMONIC2(VEX_MR, VMOVSD, vmovsd, Mq_WO, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_IGNORES_VEX_L);
599 IEM_MC_BEGIN(0, 2);
600 IEM_MC_LOCAL(uint64_t, uSrc);
601 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
602
603 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
604 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
605 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
606 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
607
608 IEM_MC_FETCH_YREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
609 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
610
611 IEM_MC_ADVANCE_RIP();
612 IEM_MC_END();
613 }
614
615 return VINF_SUCCESS;
616}
617
618
619FNIEMOP_DEF(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps)
620{
621 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
622 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
623 {
624 /**
625 * @opcode 0x12
626 * @opcodesub 11 mr/reg
627 * @oppfx none
628 * @opcpuid avx
629 * @opgroup og_avx_simdfp_datamerge
630 * @opxcpttype 7LZ
631 * @optest op2=0x2200220122022203
632 * op3=0x3304330533063307
633 * -> op1=0x22002201220222033304330533063307
634 * @optest op2=-1 op3=-42 -> op1=-42
635 * @note op3 and op2 are only the 8-byte high XMM register halfs.
636 */
637 IEMOP_MNEMONIC3(VEX_RVM, VMOVHLPS, vmovhlps, Vq_WO, HqHi, UqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
638
639 IEMOP_HLP_DONE_VEX_DECODING_L0();
640 IEM_MC_BEGIN(0, 0);
641
642 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
643 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
644 IEM_MC_MERGE_YREG_U64HI_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
645 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
646 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
647
648 IEM_MC_ADVANCE_RIP();
649 IEM_MC_END();
650 }
651 else
652 {
653 /**
654 * @opdone
655 * @opcode 0x12
656 * @opcodesub !11 mr/reg
657 * @oppfx none
658 * @opcpuid avx
659 * @opgroup og_avx_simdfp_datamove
660 * @opxcpttype 5LZ
661 * @opfunction iemOp_vmovlps_Vq_Hq_Mq__vmovhlps
662 * @optest op1=1 op2=0 op3=0 -> op1=0
663 * @optest op1=0 op2=-1 op3=-1 -> op1=-1
664 * @optest op1=1 op2=2 op3=3 -> op1=0x20000000000000003
665 * @optest op2=-1 op3=0x42 -> op1=0xffffffffffffffff0000000000000042
666 */
667 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPS, vmovlps, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
668
669 IEM_MC_BEGIN(0, 2);
670 IEM_MC_LOCAL(uint64_t, uSrc);
671 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
672
673 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
674 IEMOP_HLP_DONE_VEX_DECODING_L0();
675 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
676 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
677
678 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
679 IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
680 uSrc,
681 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
682
683 IEM_MC_ADVANCE_RIP();
684 IEM_MC_END();
685 }
686 return VINF_SUCCESS;
687}
688
689
690/**
691 * @opcode 0x12
692 * @opcodesub !11 mr/reg
693 * @oppfx 0x66
694 * @opcpuid avx
695 * @opgroup og_avx_pcksclr_datamerge
696 * @opxcpttype 5LZ
697 * @optest op2=0 op3=2 -> op1=2
698 * @optest op2=0x22 op3=0x33 -> op1=0x220000000000000033
699 * @optest op2=0xfffffff0fffffff1 op3=0xeeeeeee8eeeeeee9
700 * -> op1=0xfffffff0fffffff1eeeeeee8eeeeeee9
701 */
702FNIEMOP_DEF(iemOp_vmovlpd_Vq_Hq_Mq)
703{
704 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
705 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
706 {
707 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPD, vmovlpd, Vq_WO, HqHi, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
708
709 IEM_MC_BEGIN(0, 2);
710 IEM_MC_LOCAL(uint64_t, uSrc);
711 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
712
713 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
714 IEMOP_HLP_DONE_VEX_DECODING_L0();
715 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
716 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
717
718 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
719 IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
720 uSrc,
721 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/);
722
723 IEM_MC_ADVANCE_RIP();
724 IEM_MC_END();
725 return VINF_SUCCESS;
726 }
727
728 /**
729 * @opdone
730 * @opmnemonic udvex660f12m3
731 * @opcode 0x12
732 * @opcodesub 11 mr/reg
733 * @oppfx 0x66
734 * @opunused immediate
735 * @opcpuid avx
736 * @optest ->
737 */
738 return IEMOP_RAISE_INVALID_OPCODE();
739}
740
741
742/**
743 * @opcode 0x12
744 * @oppfx 0xf3
745 * @opcpuid avx
746 * @opgroup og_avx_pcksclr_datamove
747 * @opxcpttype 4
748 * @optest vex.l==0 / op1=-1 op2=0xdddddddd00000002eeeeeeee00000001
749 * -> op1=0x00000002000000020000000100000001
750 * @optest vex.l==1 /
751 * op2=0xbbbbbbbb00000004cccccccc00000003dddddddd00000002eeeeeeee00000001
752 * -> op1=0x0000000400000004000000030000000300000002000000020000000100000001
753 */
754FNIEMOP_DEF(iemOp_vmovsldup_Vx_Wx)
755{
756 IEMOP_MNEMONIC2(VEX_RM, VMOVSLDUP, vmovsldup, Vx_WO, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
757 Assert(pVCpu->iem.s.uVexLength <= 1);
758 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
759 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
760 {
761 /*
762 * Register, register.
763 */
764 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
765 if (pVCpu->iem.s.uVexLength == 0)
766 {
767 IEM_MC_BEGIN(2, 0);
768 IEM_MC_ARG(PRTUINT128U, puDst, 0);
769 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
770
771 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
772 IEM_MC_PREPARE_AVX_USAGE();
773
774 IEM_MC_REF_XREG_U128_CONST(puSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
775 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
776 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
777 IEM_MC_CLEAR_YREG_128_UP(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
778
779 IEM_MC_ADVANCE_RIP();
780 IEM_MC_END();
781 }
782 else
783 {
784 IEM_MC_BEGIN(3, 0);
785 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
786 IEM_MC_ARG_CONST(uint8_t, iYRegDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 1);
787 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 2);
788
789 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
790 IEM_MC_PREPARE_AVX_USAGE();
791 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rr, iYRegDst, iYRegSrc);
792
793 IEM_MC_ADVANCE_RIP();
794 IEM_MC_END();
795 }
796 }
797 else
798 {
799 /*
800 * Register, memory.
801 */
802 if (pVCpu->iem.s.uVexLength == 0)
803 {
804 IEM_MC_BEGIN(2, 2);
805 IEM_MC_LOCAL(RTUINT128U, uSrc);
806 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
807 IEM_MC_ARG(PRTUINT128U, puDst, 0);
808 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
809
810 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
811 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
812 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
813 IEM_MC_PREPARE_AVX_USAGE();
814
815 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
816 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
817 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
818 IEM_MC_CLEAR_YREG_128_UP(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
819
820 IEM_MC_ADVANCE_RIP();
821 IEM_MC_END();
822 }
823 else
824 {
825 IEM_MC_BEGIN(3, 2);
826 IEM_MC_LOCAL(RTUINT256U, uSrc);
827 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
828 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
829 IEM_MC_ARG_CONST(uint8_t, iYRegDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 1);
830 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
831
832 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
833 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
834 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
835 IEM_MC_PREPARE_AVX_USAGE();
836
837 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
838 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovsldup_256_rm, iYRegDst, puSrc);
839
840 IEM_MC_ADVANCE_RIP();
841 IEM_MC_END();
842 }
843 }
844 return VINF_SUCCESS;
845}
846
847
848/**
849 * @opcode 0x12
850 * @oppfx 0xf2
851 * @opcpuid avx
852 * @opgroup og_avx_pcksclr_datamove
853 * @opxcpttype 5
854 * @optest vex.l==0 / op2=0xddddddddeeeeeeee2222222211111111
855 * -> op1=0x22222222111111112222222211111111
856 * @optest vex.l==1 / op2=0xbbbbbbbbcccccccc4444444433333333ddddddddeeeeeeee2222222211111111
857 * -> op1=0x4444444433333333444444443333333322222222111111112222222211111111
858 */
859FNIEMOP_DEF(iemOp_vmovddup_Vx_Wx)
860{
861 IEMOP_MNEMONIC2(VEX_RM, VMOVDDUP, vmovddup, Vx_WO, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
862 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
863 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
864 {
865 /*
866 * Register, register.
867 */
868 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
869 if (pVCpu->iem.s.uVexLength == 0)
870 {
871 IEM_MC_BEGIN(2, 0);
872 IEM_MC_ARG(PRTUINT128U, puDst, 0);
873 IEM_MC_ARG(uint64_t, uSrc, 1);
874
875 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
876 IEM_MC_PREPARE_AVX_USAGE();
877
878 IEM_MC_FETCH_XREG_U64(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
879 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
880 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
881 IEM_MC_CLEAR_YREG_128_UP(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
882
883 IEM_MC_ADVANCE_RIP();
884 IEM_MC_END();
885 }
886 else
887 {
888 IEM_MC_BEGIN(3, 0);
889 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
890 IEM_MC_ARG_CONST(uint8_t, iYRegDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 1);
891 IEM_MC_ARG_CONST(uint8_t, iYRegSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 2);
892
893 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
894 IEM_MC_PREPARE_AVX_USAGE();
895 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rr, iYRegDst, iYRegSrc);
896
897 IEM_MC_ADVANCE_RIP();
898 IEM_MC_END();
899 }
900 }
901 else
902 {
903 /*
904 * Register, memory.
905 */
906 if (pVCpu->iem.s.uVexLength == 0)
907 {
908 IEM_MC_BEGIN(2, 2);
909 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
910 IEM_MC_ARG(PRTUINT128U, puDst, 0);
911 IEM_MC_ARG(uint64_t, uSrc, 1);
912
913 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
914 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
915 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
916 IEM_MC_PREPARE_AVX_USAGE();
917
918 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
919 IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
920 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
921 IEM_MC_CLEAR_YREG_128_UP(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
922
923 IEM_MC_ADVANCE_RIP();
924 IEM_MC_END();
925 }
926 else
927 {
928 IEM_MC_BEGIN(3, 2);
929 IEM_MC_LOCAL(RTUINT256U, uSrc);
930 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
931 IEM_MC_IMPLICIT_AVX_AIMPL_ARGS();
932 IEM_MC_ARG_CONST(uint8_t, iYRegDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 1);
933 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc, uSrc, 2);
934
935 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
936 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
937 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
938 IEM_MC_PREPARE_AVX_USAGE();
939
940 IEM_MC_FETCH_MEM_U256(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
941 IEM_MC_CALL_AVX_AIMPL_2(iemAImpl_vmovddup_256_rm, iYRegDst, puSrc);
942
943 IEM_MC_ADVANCE_RIP();
944 IEM_MC_END();
945 }
946 }
947 return VINF_SUCCESS;
948}
949
950
951/**
952 * @opcode 0x13
953 * @opcodesub !11 mr/reg
954 * @oppfx none
955 * @opcpuid avx
956 * @opgroup og_avx_simdfp_datamove
957 * @opxcpttype 5
958 * @optest op1=1 op2=2 -> op1=2
959 * @optest op1=0 op2=-42 -> op1=-42
960 */
961FNIEMOP_DEF(iemOp_vmovlps_Mq_Vq)
962{
963 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
964 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
965 {
966 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPS, vmovlps, Mq_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
967
968 IEM_MC_BEGIN(0, 2);
969 IEM_MC_LOCAL(uint64_t, uSrc);
970 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
971
972 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
973 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
974 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
975 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
976
977 IEM_MC_FETCH_YREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
978 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
979
980 IEM_MC_ADVANCE_RIP();
981 IEM_MC_END();
982 return VINF_SUCCESS;
983 }
984
985 /**
986 * @opdone
987 * @opmnemonic udvex0f13m3
988 * @opcode 0x13
989 * @opcodesub 11 mr/reg
990 * @oppfx none
991 * @opunused immediate
992 * @opcpuid avx
993 * @optest ->
994 */
995 return IEMOP_RAISE_INVALID_OPCODE();
996}
997
998
999/**
1000 * @opcode 0x13
1001 * @opcodesub !11 mr/reg
1002 * @oppfx 0x66
1003 * @opcpuid avx
1004 * @opgroup og_avx_pcksclr_datamove
1005 * @opxcpttype 5
1006 * @optest op1=1 op2=2 -> op1=2
1007 * @optest op1=0 op2=-42 -> op1=-42
1008 */
1009FNIEMOP_DEF(iemOp_vmovlpd_Mq_Vq)
1010{
1011 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1012 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1013 {
1014 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVLPD, vmovlpd, Mq_WO, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO);
1015 IEM_MC_BEGIN(0, 2);
1016 IEM_MC_LOCAL(uint64_t, uSrc);
1017 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1018
1019 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1020 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
1021 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1022 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1023
1024 IEM_MC_FETCH_YREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1025 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1026
1027 IEM_MC_ADVANCE_RIP();
1028 IEM_MC_END();
1029 return VINF_SUCCESS;
1030 }
1031
1032 /**
1033 * @opdone
1034 * @opmnemonic udvex660f13m3
1035 * @opcode 0x13
1036 * @opcodesub 11 mr/reg
1037 * @oppfx 0x66
1038 * @opunused immediate
1039 * @opcpuid avx
1040 * @optest ->
1041 */
1042 return IEMOP_RAISE_INVALID_OPCODE();
1043}
1044
1045/* Opcode VEX.F3.0F 0x13 - invalid */
1046/* Opcode VEX.F2.0F 0x13 - invalid */
1047
1048/** Opcode VEX.0F 0x14 - vunpcklps Vx, Hx, Wx*/
1049FNIEMOP_STUB(iemOp_vunpcklps_Vx_Hx_Wx);
1050/** Opcode VEX.66.0F 0x14 - vunpcklpd Vx,Hx,Wx */
1051FNIEMOP_STUB(iemOp_vunpcklpd_Vx_Hx_Wx);
1052/* Opcode VEX.F3.0F 0x14 - invalid */
1053/* Opcode VEX.F2.0F 0x14 - invalid */
1054/** Opcode VEX.0F 0x15 - vunpckhps Vx, Hx, Wx */
1055FNIEMOP_STUB(iemOp_vunpckhps_Vx_Hx_Wx);
1056/** Opcode VEX.66.0F 0x15 - vunpckhpd Vx,Hx,Wx */
1057FNIEMOP_STUB(iemOp_vunpckhpd_Vx_Hx_Wx);
1058/* Opcode VEX.F3.0F 0x15 - invalid */
1059/* Opcode VEX.F2.0F 0x15 - invalid */
1060/** Opcode VEX.0F 0x16 - vmovhpsv1 Vdq, Hq, Mq vmovlhps Vdq, Hq, Uq */
1061FNIEMOP_STUB(iemOp_vmovhpsv1_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq); //NEXT
1062/** Opcode VEX.66.0F 0x16 - vmovhpdv1 Vdq, Hq, Mq */
1063FNIEMOP_STUB(iemOp_vmovhpdv1_Vdq_Hq_Mq); //NEXT
1064/** Opcode VEX.F3.0F 0x16 - vmovshdup Vx, Wx */
1065FNIEMOP_STUB(iemOp_vmovshdup_Vx_Wx); //NEXT
1066/* Opcode VEX.F2.0F 0x16 - invalid */
1067/** Opcode VEX.0F 0x17 - vmovhpsv1 Mq, Vq */
1068FNIEMOP_STUB(iemOp_vmovhpsv1_Mq_Vq); //NEXT
1069/** Opcode VEX.66.0F 0x17 - vmovhpdv1 Mq, Vq */
1070FNIEMOP_STUB(iemOp_vmovhpdv1_Mq_Vq); //NEXT
1071/* Opcode VEX.F3.0F 0x17 - invalid */
1072/* Opcode VEX.F2.0F 0x17 - invalid */
1073
1074
1075/* Opcode VEX.0F 0x18 - invalid */
1076/* Opcode VEX.0F 0x19 - invalid */
1077/* Opcode VEX.0F 0x1a - invalid */
1078/* Opcode VEX.0F 0x1b - invalid */
1079/* Opcode VEX.0F 0x1c - invalid */
1080/* Opcode VEX.0F 0x1d - invalid */
1081/* Opcode VEX.0F 0x1e - invalid */
1082/* Opcode VEX.0F 0x1f - invalid */
1083
1084/* Opcode VEX.0F 0x20 - invalid */
1085/* Opcode VEX.0F 0x21 - invalid */
1086/* Opcode VEX.0F 0x22 - invalid */
1087/* Opcode VEX.0F 0x23 - invalid */
1088/* Opcode VEX.0F 0x24 - invalid */
1089/* Opcode VEX.0F 0x25 - invalid */
1090/* Opcode VEX.0F 0x26 - invalid */
1091/* Opcode VEX.0F 0x27 - invalid */
1092
1093/**
1094 * @opcode 0x28
1095 * @oppfx none
1096 * @opcpuid avx
1097 * @opgroup og_avx_pcksclr_datamove
1098 * @opxcpttype 1
1099 * @optest op1=1 op2=2 -> op1=2
1100 * @optest op1=0 op2=-42 -> op1=-42
1101 * @note Almost identical to vmovapd.
1102 */
1103FNIEMOP_DEF(iemOp_vmovaps_Vps_Wps)
1104{
1105 IEMOP_MNEMONIC2(VEX_RM, VMOVAPS, vmovaps, Vps_WO, Wps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1106 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1107 Assert(pVCpu->iem.s.uVexLength <= 1);
1108 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1109 {
1110 /*
1111 * Register, register.
1112 */
1113 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1114 IEM_MC_BEGIN(1, 0);
1115
1116 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1117 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1118 if (pVCpu->iem.s.uVexLength == 0)
1119 IEM_MC_COPY_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1120 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1121 else
1122 IEM_MC_COPY_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1123 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1124 IEM_MC_ADVANCE_RIP();
1125 IEM_MC_END();
1126 }
1127 else
1128 {
1129 /*
1130 * Register, memory.
1131 */
1132 if (pVCpu->iem.s.uVexLength == 0)
1133 {
1134 IEM_MC_BEGIN(0, 2);
1135 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1136 IEM_MC_LOCAL(RTUINT128U, uSrc);
1137
1138 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1139 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1140 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1141 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1142
1143 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1144 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1145
1146 IEM_MC_ADVANCE_RIP();
1147 IEM_MC_END();
1148 }
1149 else
1150 {
1151 IEM_MC_BEGIN(0, 2);
1152 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1153 IEM_MC_LOCAL(RTUINT256U, uSrc);
1154
1155 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1156 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1157 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1158 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1159
1160 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1161 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1162
1163 IEM_MC_ADVANCE_RIP();
1164 IEM_MC_END();
1165 }
1166 }
1167 return VINF_SUCCESS;
1168}
1169
1170
1171/**
1172 * @opcode 0x28
1173 * @oppfx 66
1174 * @opcpuid avx
1175 * @opgroup og_avx_pcksclr_datamove
1176 * @opxcpttype 1
1177 * @optest op1=1 op2=2 -> op1=2
1178 * @optest op1=0 op2=-42 -> op1=-42
1179 * @note Almost identical to vmovaps
1180 */
1181FNIEMOP_DEF(iemOp_vmovapd_Vpd_Wpd)
1182{
1183 IEMOP_MNEMONIC2(VEX_RM, VMOVAPD, vmovapd, Vpd_WO, Wpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1184 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1185 Assert(pVCpu->iem.s.uVexLength <= 1);
1186 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1187 {
1188 /*
1189 * Register, register.
1190 */
1191 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1192 IEM_MC_BEGIN(1, 0);
1193
1194 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1195 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1196 if (pVCpu->iem.s.uVexLength == 0)
1197 IEM_MC_COPY_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1198 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1199 else
1200 IEM_MC_COPY_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
1201 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1202 IEM_MC_ADVANCE_RIP();
1203 IEM_MC_END();
1204 }
1205 else
1206 {
1207 /*
1208 * Register, memory.
1209 */
1210 if (pVCpu->iem.s.uVexLength == 0)
1211 {
1212 IEM_MC_BEGIN(0, 2);
1213 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1214 IEM_MC_LOCAL(RTUINT128U, uSrc);
1215
1216 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1217 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1218 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1219 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1220
1221 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1222 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1223
1224 IEM_MC_ADVANCE_RIP();
1225 IEM_MC_END();
1226 }
1227 else
1228 {
1229 IEM_MC_BEGIN(0, 2);
1230 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1231 IEM_MC_LOCAL(RTUINT256U, uSrc);
1232
1233 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1234 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1235 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1236 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1237
1238 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1239 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
1240
1241 IEM_MC_ADVANCE_RIP();
1242 IEM_MC_END();
1243 }
1244 }
1245 return VINF_SUCCESS;
1246}
1247
1248/**
1249 * @opmnemonic udvexf30f28
1250 * @opcode 0x28
1251 * @oppfx 0xf3
1252 * @opunused vex.modrm
1253 * @opcpuid avx
1254 * @optest ->
1255 * @opdone
1256 */
1257
1258/**
1259 * @opmnemonic udvexf20f28
1260 * @opcode 0x28
1261 * @oppfx 0xf2
1262 * @opunused vex.modrm
1263 * @opcpuid avx
1264 * @optest ->
1265 * @opdone
1266 */
1267
1268/**
1269 * @opcode 0x29
1270 * @oppfx none
1271 * @opcpuid avx
1272 * @opgroup og_avx_pcksclr_datamove
1273 * @opxcpttype 1
1274 * @optest op1=1 op2=2 -> op1=2
1275 * @optest op1=0 op2=-42 -> op1=-42
1276 * @note Almost identical to vmovapd.
1277 */
1278FNIEMOP_DEF(iemOp_vmovaps_Wps_Vps)
1279{
1280 IEMOP_MNEMONIC2(VEX_MR, VMOVAPS, vmovaps, Wps_WO, Vps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1281 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1282 Assert(pVCpu->iem.s.uVexLength <= 1);
1283 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1284 {
1285 /*
1286 * Register, register.
1287 */
1288 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1289 IEM_MC_BEGIN(1, 0);
1290
1291 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1292 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1293 if (pVCpu->iem.s.uVexLength == 0)
1294 IEM_MC_COPY_YREG_U128_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
1295 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1296 else
1297 IEM_MC_COPY_YREG_U256_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
1298 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1299 IEM_MC_ADVANCE_RIP();
1300 IEM_MC_END();
1301 }
1302 else
1303 {
1304 /*
1305 * Register, memory.
1306 */
1307 if (pVCpu->iem.s.uVexLength == 0)
1308 {
1309 IEM_MC_BEGIN(0, 2);
1310 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1311 IEM_MC_LOCAL(RTUINT128U, uSrc);
1312
1313 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1314 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1315 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1316 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1317
1318 IEM_MC_FETCH_YREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1319 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1320
1321 IEM_MC_ADVANCE_RIP();
1322 IEM_MC_END();
1323 }
1324 else
1325 {
1326 IEM_MC_BEGIN(0, 2);
1327 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1328 IEM_MC_LOCAL(RTUINT256U, uSrc);
1329
1330 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1331 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1332 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1333 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1334
1335 IEM_MC_FETCH_YREG_U256(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1336 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1337
1338 IEM_MC_ADVANCE_RIP();
1339 IEM_MC_END();
1340 }
1341 }
1342 return VINF_SUCCESS;
1343}
1344
1345/**
1346 * @opcode 0x29
1347 * @oppfx 66
1348 * @opcpuid avx
1349 * @opgroup og_avx_pcksclr_datamove
1350 * @opxcpttype 1
1351 * @optest op1=1 op2=2 -> op1=2
1352 * @optest op1=0 op2=-42 -> op1=-42
1353 * @note Almost identical to vmovaps
1354 */
1355FNIEMOP_DEF(iemOp_vmovapd_Wpd_Vpd)
1356{
1357 IEMOP_MNEMONIC2(VEX_MR, VMOVAPD, vmovapd, Wpd_WO, Vpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1358 Assert(pVCpu->iem.s.uVexLength <= 1);
1359 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1360 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1361 {
1362 /*
1363 * Register, register.
1364 */
1365 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1366 IEM_MC_BEGIN(1, 0);
1367
1368 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1369 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1370 if (pVCpu->iem.s.uVexLength == 0)
1371 IEM_MC_COPY_YREG_U128_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
1372 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1373 else
1374 IEM_MC_COPY_YREG_U256_ZX_VLMAX((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
1375 ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1376 IEM_MC_ADVANCE_RIP();
1377 IEM_MC_END();
1378 }
1379 else
1380 {
1381 /*
1382 * Register, memory.
1383 */
1384 if (pVCpu->iem.s.uVexLength == 0)
1385 {
1386 IEM_MC_BEGIN(0, 2);
1387 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1388 IEM_MC_LOCAL(RTUINT128U, uSrc);
1389
1390 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1391 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1392 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1393 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1394
1395 IEM_MC_FETCH_YREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1396 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1397
1398 IEM_MC_ADVANCE_RIP();
1399 IEM_MC_END();
1400 }
1401 else
1402 {
1403 IEM_MC_BEGIN(0, 2);
1404 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1405 IEM_MC_LOCAL(RTUINT256U, uSrc);
1406
1407 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1408 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1409 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1410 IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ();
1411
1412 IEM_MC_FETCH_YREG_U256(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1413 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1414
1415 IEM_MC_ADVANCE_RIP();
1416 IEM_MC_END();
1417 }
1418 }
1419 return VINF_SUCCESS;
1420}
1421
1422
1423/**
1424 * @opmnemonic udvexf30f29
1425 * @opcode 0x29
1426 * @oppfx 0xf3
1427 * @opunused vex.modrm
1428 * @opcpuid avx
1429 * @optest ->
1430 * @opdone
1431 */
1432
1433/**
1434 * @opmnemonic udvexf20f29
1435 * @opcode 0x29
1436 * @oppfx 0xf2
1437 * @opunused vex.modrm
1438 * @opcpuid avx
1439 * @optest ->
1440 * @opdone
1441 */
1442
1443
1444/** Opcode VEX.0F 0x2a - invalid */
1445/** Opcode VEX.66.0F 0x2a - invalid */
1446/** Opcode VEX.F3.0F 0x2a - vcvtsi2ss Vss, Hss, Ey */
1447FNIEMOP_STUB(iemOp_vcvtsi2ss_Vss_Hss_Ey);
1448/** Opcode VEX.F2.0F 0x2a - vcvtsi2sd Vsd, Hsd, Ey */
1449FNIEMOP_STUB(iemOp_vcvtsi2sd_Vsd_Hsd_Ey);
1450
1451
1452/**
1453 * @opcode 0x2b
1454 * @opcodesub !11 mr/reg
1455 * @oppfx none
1456 * @opcpuid avx
1457 * @opgroup og_avx_cachect
1458 * @opxcpttype 1
1459 * @optest op1=1 op2=2 -> op1=2
1460 * @optest op1=0 op2=-42 -> op1=-42
1461 * @note Identical implementation to vmovntpd
1462 */
1463FNIEMOP_DEF(iemOp_vmovntps_Mps_Vps)
1464{
1465 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPS, vmovntps, Mps_WO, Vps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1466 Assert(pVCpu->iem.s.uVexLength <= 1);
1467 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1468 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1469 {
1470 /*
1471 * memory, register.
1472 */
1473 if (pVCpu->iem.s.uVexLength == 0)
1474 {
1475 IEM_MC_BEGIN(0, 2);
1476 IEM_MC_LOCAL(RTUINT128U, uSrc);
1477 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1478
1479 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1480 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1481 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1482 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1483
1484 IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1485 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1486
1487 IEM_MC_ADVANCE_RIP();
1488 IEM_MC_END();
1489 }
1490 else
1491 {
1492 IEM_MC_BEGIN(0, 2);
1493 IEM_MC_LOCAL(RTUINT256U, uSrc);
1494 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1495
1496 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1497 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1498 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1499 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1500
1501 IEM_MC_FETCH_YREG_U256(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1502 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1503
1504 IEM_MC_ADVANCE_RIP();
1505 IEM_MC_END();
1506 }
1507 }
1508 /* The register, register encoding is invalid. */
1509 else
1510 return IEMOP_RAISE_INVALID_OPCODE();
1511 return VINF_SUCCESS;
1512}
1513
1514/**
1515 * @opcode 0x2b
1516 * @opcodesub !11 mr/reg
1517 * @oppfx 0x66
1518 * @opcpuid avx
1519 * @opgroup og_avx_cachect
1520 * @opxcpttype 1
1521 * @optest op1=1 op2=2 -> op1=2
1522 * @optest op1=0 op2=-42 -> op1=-42
1523 * @note Identical implementation to vmovntps
1524 */
1525FNIEMOP_DEF(iemOp_vmovntpd_Mpd_Vpd)
1526{
1527 IEMOP_MNEMONIC2(VEX_MR_MEM, VMOVNTPD, vmovntpd, Mpd_WO, Vpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
1528 Assert(pVCpu->iem.s.uVexLength <= 1);
1529 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1530 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1531 {
1532 /*
1533 * memory, register.
1534 */
1535 if (pVCpu->iem.s.uVexLength == 0)
1536 {
1537 IEM_MC_BEGIN(0, 2);
1538 IEM_MC_LOCAL(RTUINT128U, uSrc);
1539 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1540
1541 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1542 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1543 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1544 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1545
1546 IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1547 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1548
1549 IEM_MC_ADVANCE_RIP();
1550 IEM_MC_END();
1551 }
1552 else
1553 {
1554 IEM_MC_BEGIN(0, 2);
1555 IEM_MC_LOCAL(RTUINT256U, uSrc);
1556 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1557
1558 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1559 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
1560 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1561 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
1562
1563 IEM_MC_FETCH_YREG_U256(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1564 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1565
1566 IEM_MC_ADVANCE_RIP();
1567 IEM_MC_END();
1568 }
1569 }
1570 /* The register, register encoding is invalid. */
1571 else
1572 return IEMOP_RAISE_INVALID_OPCODE();
1573 return VINF_SUCCESS;
1574}
1575
1576/**
1577 * @opmnemonic udvexf30f2b
1578 * @opcode 0x2b
1579 * @oppfx 0xf3
1580 * @opunused vex.modrm
1581 * @opcpuid avx
1582 * @optest ->
1583 * @opdone
1584 */
1585
1586/**
1587 * @opmnemonic udvexf20f2b
1588 * @opcode 0x2b
1589 * @oppfx 0xf2
1590 * @opunused vex.modrm
1591 * @opcpuid avx
1592 * @optest ->
1593 * @opdone
1594 */
1595
1596
1597/* Opcode VEX.0F 0x2c - invalid */
1598/* Opcode VEX.66.0F 0x2c - invalid */
1599/** Opcode VEX.F3.0F 0x2c - vcvttss2si Gy, Wss */
1600FNIEMOP_STUB(iemOp_vcvttss2si_Gy_Wss);
1601/** Opcode VEX.F2.0F 0x2c - vcvttsd2si Gy, Wsd */
1602FNIEMOP_STUB(iemOp_vcvttsd2si_Gy_Wsd);
1603
1604/* Opcode VEX.0F 0x2d - invalid */
1605/* Opcode VEX.66.0F 0x2d - invalid */
1606/** Opcode VEX.F3.0F 0x2d - vcvtss2si Gy, Wss */
1607FNIEMOP_STUB(iemOp_vcvtss2si_Gy_Wss);
1608/** Opcode VEX.F2.0F 0x2d - vcvtsd2si Gy, Wsd */
1609FNIEMOP_STUB(iemOp_vcvtsd2si_Gy_Wsd);
1610
1611/** Opcode VEX.0F 0x2e - vucomiss Vss, Wss */
1612FNIEMOP_STUB(iemOp_vucomiss_Vss_Wss);
1613/** Opcode VEX.66.0F 0x2e - vucomisd Vsd, Wsd */
1614FNIEMOP_STUB(iemOp_vucomisd_Vsd_Wsd);
1615/* Opcode VEX.F3.0F 0x2e - invalid */
1616/* Opcode VEX.F2.0F 0x2e - invalid */
1617
1618/** Opcode VEX.0F 0x2f - vcomiss Vss, Wss */
1619FNIEMOP_STUB(iemOp_vcomiss_Vss_Wss);
1620/** Opcode VEX.66.0F 0x2f - vcomisd Vsd, Wsd */
1621FNIEMOP_STUB(iemOp_vcomisd_Vsd_Wsd);
1622/* Opcode VEX.F3.0F 0x2f - invalid */
1623/* Opcode VEX.F2.0F 0x2f - invalid */
1624
1625/* Opcode VEX.0F 0x30 - invalid */
1626/* Opcode VEX.0F 0x31 - invalid */
1627/* Opcode VEX.0F 0x32 - invalid */
1628/* Opcode VEX.0F 0x33 - invalid */
1629/* Opcode VEX.0F 0x34 - invalid */
1630/* Opcode VEX.0F 0x35 - invalid */
1631/* Opcode VEX.0F 0x36 - invalid */
1632/* Opcode VEX.0F 0x37 - invalid */
1633/* Opcode VEX.0F 0x38 - invalid */
1634/* Opcode VEX.0F 0x39 - invalid */
1635/* Opcode VEX.0F 0x3a - invalid */
1636/* Opcode VEX.0F 0x3b - invalid */
1637/* Opcode VEX.0F 0x3c - invalid */
1638/* Opcode VEX.0F 0x3d - invalid */
1639/* Opcode VEX.0F 0x3e - invalid */
1640/* Opcode VEX.0F 0x3f - invalid */
1641/* Opcode VEX.0F 0x40 - invalid */
1642/* Opcode VEX.0F 0x41 - invalid */
1643/* Opcode VEX.0F 0x42 - invalid */
1644/* Opcode VEX.0F 0x43 - invalid */
1645/* Opcode VEX.0F 0x44 - invalid */
1646/* Opcode VEX.0F 0x45 - invalid */
1647/* Opcode VEX.0F 0x46 - invalid */
1648/* Opcode VEX.0F 0x47 - invalid */
1649/* Opcode VEX.0F 0x48 - invalid */
1650/* Opcode VEX.0F 0x49 - invalid */
1651/* Opcode VEX.0F 0x4a - invalid */
1652/* Opcode VEX.0F 0x4b - invalid */
1653/* Opcode VEX.0F 0x4c - invalid */
1654/* Opcode VEX.0F 0x4d - invalid */
1655/* Opcode VEX.0F 0x4e - invalid */
1656/* Opcode VEX.0F 0x4f - invalid */
1657
1658/** Opcode VEX.0F 0x50 - vmovmskps Gy, Ups */
1659FNIEMOP_STUB(iemOp_vmovmskps_Gy_Ups);
1660/** Opcode VEX.66.0F 0x50 - vmovmskpd Gy,Upd */
1661FNIEMOP_STUB(iemOp_vmovmskpd_Gy_Upd);
1662/* Opcode VEX.F3.0F 0x50 - invalid */
1663/* Opcode VEX.F2.0F 0x50 - invalid */
1664
1665/** Opcode VEX.0F 0x51 - vsqrtps Vps, Wps */
1666FNIEMOP_STUB(iemOp_vsqrtps_Vps_Wps);
1667/** Opcode VEX.66.0F 0x51 - vsqrtpd Vpd, Wpd */
1668FNIEMOP_STUB(iemOp_vsqrtpd_Vpd_Wpd);
1669/** Opcode VEX.F3.0F 0x51 - vsqrtss Vss, Hss, Wss */
1670FNIEMOP_STUB(iemOp_vsqrtss_Vss_Hss_Wss);
1671/** Opcode VEX.F2.0F 0x51 - vsqrtsd Vsd, Hsd, Wsd */
1672FNIEMOP_STUB(iemOp_vsqrtsd_Vsd_Hsd_Wsd);
1673
1674/** Opcode VEX.0F 0x52 - vrsqrtps Vps, Wps */
1675FNIEMOP_STUB(iemOp_vrsqrtps_Vps_Wps);
1676/* Opcode VEX.66.0F 0x52 - invalid */
1677/** Opcode VEX.F3.0F 0x52 - vrsqrtss Vss, Hss, Wss */
1678FNIEMOP_STUB(iemOp_vrsqrtss_Vss_Hss_Wss);
1679/* Opcode VEX.F2.0F 0x52 - invalid */
1680
1681/** Opcode VEX.0F 0x53 - vrcpps Vps, Wps */
1682FNIEMOP_STUB(iemOp_vrcpps_Vps_Wps);
1683/* Opcode VEX.66.0F 0x53 - invalid */
1684/** Opcode VEX.F3.0F 0x53 - vrcpss Vss, Hss, Wss */
1685FNIEMOP_STUB(iemOp_vrcpss_Vss_Hss_Wss);
1686/* Opcode VEX.F2.0F 0x53 - invalid */
1687
1688/** Opcode VEX.0F 0x54 - vandps Vps, Hps, Wps */
1689FNIEMOP_STUB(iemOp_vandps_Vps_Hps_Wps);
1690/** Opcode VEX.66.0F 0x54 - vandpd Vpd, Hpd, Wpd */
1691FNIEMOP_STUB(iemOp_vandpd_Vpd_Hpd_Wpd);
1692/* Opcode VEX.F3.0F 0x54 - invalid */
1693/* Opcode VEX.F2.0F 0x54 - invalid */
1694
1695/** Opcode VEX.0F 0x55 - vandnps Vps, Hps, Wps */
1696FNIEMOP_STUB(iemOp_vandnps_Vps_Hps_Wps);
1697/** Opcode VEX.66.0F 0x55 - vandnpd Vpd, Hpd, Wpd */
1698FNIEMOP_STUB(iemOp_vandnpd_Vpd_Hpd_Wpd);
1699/* Opcode VEX.F3.0F 0x55 - invalid */
1700/* Opcode VEX.F2.0F 0x55 - invalid */
1701
1702/** Opcode VEX.0F 0x56 - vorps Vps, Hps, Wps */
1703FNIEMOP_STUB(iemOp_vorps_Vps_Hps_Wps);
1704/** Opcode VEX.66.0F 0x56 - vorpd Vpd, Hpd, Wpd */
1705FNIEMOP_STUB(iemOp_vorpd_Vpd_Hpd_Wpd);
1706/* Opcode VEX.F3.0F 0x56 - invalid */
1707/* Opcode VEX.F2.0F 0x56 - invalid */
1708
1709/** Opcode VEX.0F 0x57 - vxorps Vps, Hps, Wps */
1710FNIEMOP_STUB(iemOp_vxorps_Vps_Hps_Wps);
1711/** Opcode VEX.66.0F 0x57 - vxorpd Vpd, Hpd, Wpd */
1712FNIEMOP_STUB(iemOp_vxorpd_Vpd_Hpd_Wpd);
1713/* Opcode VEX.F3.0F 0x57 - invalid */
1714/* Opcode VEX.F2.0F 0x57 - invalid */
1715
1716/** Opcode VEX.0F 0x58 - vaddps Vps, Hps, Wps */
1717FNIEMOP_STUB(iemOp_vaddps_Vps_Hps_Wps);
1718/** Opcode VEX.66.0F 0x58 - vaddpd Vpd, Hpd, Wpd */
1719FNIEMOP_STUB(iemOp_vaddpd_Vpd_Hpd_Wpd);
1720/** Opcode VEX.F3.0F 0x58 - vaddss Vss, Hss, Wss */
1721FNIEMOP_STUB(iemOp_vaddss_Vss_Hss_Wss);
1722/** Opcode VEX.F2.0F 0x58 - vaddsd Vsd, Hsd, Wsd */
1723FNIEMOP_STUB(iemOp_vaddsd_Vsd_Hsd_Wsd);
1724
1725/** Opcode VEX.0F 0x59 - vmulps Vps, Hps, Wps */
1726FNIEMOP_STUB(iemOp_vmulps_Vps_Hps_Wps);
1727/** Opcode VEX.66.0F 0x59 - vmulpd Vpd, Hpd, Wpd */
1728FNIEMOP_STUB(iemOp_vmulpd_Vpd_Hpd_Wpd);
1729/** Opcode VEX.F3.0F 0x59 - vmulss Vss, Hss, Wss */
1730FNIEMOP_STUB(iemOp_vmulss_Vss_Hss_Wss);
1731/** Opcode VEX.F2.0F 0x59 - vmulsd Vsd, Hsd, Wsd */
1732FNIEMOP_STUB(iemOp_vmulsd_Vsd_Hsd_Wsd);
1733
1734/** Opcode VEX.0F 0x5a - vcvtps2pd Vpd, Wps */
1735FNIEMOP_STUB(iemOp_vcvtps2pd_Vpd_Wps);
1736/** Opcode VEX.66.0F 0x5a - vcvtpd2ps Vps, Wpd */
1737FNIEMOP_STUB(iemOp_vcvtpd2ps_Vps_Wpd);
1738/** Opcode VEX.F3.0F 0x5a - vcvtss2sd Vsd, Hx, Wss */
1739FNIEMOP_STUB(iemOp_vcvtss2sd_Vsd_Hx_Wss);
1740/** Opcode VEX.F2.0F 0x5a - vcvtsd2ss Vss, Hx, Wsd */
1741FNIEMOP_STUB(iemOp_vcvtsd2ss_Vss_Hx_Wsd);
1742
1743/** Opcode VEX.0F 0x5b - vcvtdq2ps Vps, Wdq */
1744FNIEMOP_STUB(iemOp_vcvtdq2ps_Vps_Wdq);
1745/** Opcode VEX.66.0F 0x5b - vcvtps2dq Vdq, Wps */
1746FNIEMOP_STUB(iemOp_vcvtps2dq_Vdq_Wps);
1747/** Opcode VEX.F3.0F 0x5b - vcvttps2dq Vdq, Wps */
1748FNIEMOP_STUB(iemOp_vcvttps2dq_Vdq_Wps);
1749/* Opcode VEX.F2.0F 0x5b - invalid */
1750
1751/** Opcode VEX.0F 0x5c - vsubps Vps, Hps, Wps */
1752FNIEMOP_STUB(iemOp_vsubps_Vps_Hps_Wps);
1753/** Opcode VEX.66.0F 0x5c - vsubpd Vpd, Hpd, Wpd */
1754FNIEMOP_STUB(iemOp_vsubpd_Vpd_Hpd_Wpd);
1755/** Opcode VEX.F3.0F 0x5c - vsubss Vss, Hss, Wss */
1756FNIEMOP_STUB(iemOp_vsubss_Vss_Hss_Wss);
1757/** Opcode VEX.F2.0F 0x5c - vsubsd Vsd, Hsd, Wsd */
1758FNIEMOP_STUB(iemOp_vsubsd_Vsd_Hsd_Wsd);
1759
1760/** Opcode VEX.0F 0x5d - vminps Vps, Hps, Wps */
1761FNIEMOP_STUB(iemOp_vminps_Vps_Hps_Wps);
1762/** Opcode VEX.66.0F 0x5d - vminpd Vpd, Hpd, Wpd */
1763FNIEMOP_STUB(iemOp_vminpd_Vpd_Hpd_Wpd);
1764/** Opcode VEX.F3.0F 0x5d - vminss Vss, Hss, Wss */
1765FNIEMOP_STUB(iemOp_vminss_Vss_Hss_Wss);
1766/** Opcode VEX.F2.0F 0x5d - vminsd Vsd, Hsd, Wsd */
1767FNIEMOP_STUB(iemOp_vminsd_Vsd_Hsd_Wsd);
1768
1769/** Opcode VEX.0F 0x5e - vdivps Vps, Hps, Wps */
1770FNIEMOP_STUB(iemOp_vdivps_Vps_Hps_Wps);
1771/** Opcode VEX.66.0F 0x5e - vdivpd Vpd, Hpd, Wpd */
1772FNIEMOP_STUB(iemOp_vdivpd_Vpd_Hpd_Wpd);
1773/** Opcode VEX.F3.0F 0x5e - vdivss Vss, Hss, Wss */
1774FNIEMOP_STUB(iemOp_vdivss_Vss_Hss_Wss);
1775/** Opcode VEX.F2.0F 0x5e - vdivsd Vsd, Hsd, Wsd */
1776FNIEMOP_STUB(iemOp_vdivsd_Vsd_Hsd_Wsd);
1777
1778/** Opcode VEX.0F 0x5f - vmaxps Vps, Hps, Wps */
1779FNIEMOP_STUB(iemOp_vmaxps_Vps_Hps_Wps);
1780/** Opcode VEX.66.0F 0x5f - vmaxpd Vpd, Hpd, Wpd */
1781FNIEMOP_STUB(iemOp_vmaxpd_Vpd_Hpd_Wpd);
1782/** Opcode VEX.F3.0F 0x5f - vmaxss Vss, Hss, Wss */
1783FNIEMOP_STUB(iemOp_vmaxss_Vss_Hss_Wss);
1784/** Opcode VEX.F2.0F 0x5f - vmaxsd Vsd, Hsd, Wsd */
1785FNIEMOP_STUB(iemOp_vmaxsd_Vsd_Hsd_Wsd);
1786
1787
1788///**
1789// * Common worker for SSE2 instructions on the forms:
1790// * pxxxx xmm1, xmm2/mem128
1791// *
1792// * The 2nd operand is the first half of a register, which in the memory case
1793// * means a 32-bit memory access for MMX and 128-bit aligned 64-bit or 128-bit
1794// * memory accessed for MMX.
1795// *
1796// * Exceptions type 4.
1797// */
1798//FNIEMOP_DEF_1(iemOpCommonSse_LowLow_To_Full, PCIEMOPMEDIAF1L1, pImpl)
1799//{
1800// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1801// if (!pImpl->pfnU64)
1802// return IEMOP_RAISE_INVALID_OPCODE();
1803// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1804// {
1805// /*
1806// * Register, register.
1807// */
1808// /** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
1809// /** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
1810// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1811// IEM_MC_BEGIN(2, 0);
1812// IEM_MC_ARG(uint64_t *, pDst, 0);
1813// IEM_MC_ARG(uint32_t const *, pSrc, 1);
1814// IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
1815// IEM_MC_PREPARE_FPU_USAGE();
1816// IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
1817// IEM_MC_REF_MREG_U32_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
1818// IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
1819// IEM_MC_ADVANCE_RIP();
1820// IEM_MC_END();
1821// }
1822// else
1823// {
1824// /*
1825// * Register, memory.
1826// */
1827// IEM_MC_BEGIN(2, 2);
1828// IEM_MC_ARG(uint64_t *, pDst, 0);
1829// IEM_MC_LOCAL(uint32_t, uSrc);
1830// IEM_MC_ARG_LOCAL_REF(uint32_t const *, pSrc, uSrc, 1);
1831// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1832//
1833// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1834// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1835// IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
1836// IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1837//
1838// IEM_MC_PREPARE_FPU_USAGE();
1839// IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
1840// IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
1841//
1842// IEM_MC_ADVANCE_RIP();
1843// IEM_MC_END();
1844// }
1845// return VINF_SUCCESS;
1846//}
1847
1848
1849/* Opcode VEX.0F 0x60 - invalid */
1850
1851/** Opcode VEX.66.0F 0x60 - vpunpcklbw Vx, Hx, W */
1852FNIEMOP_STUB(iemOp_vpunpcklbw_Vx_Hx_Wx);
1853//FNIEMOP_DEF(iemOp_vpunpcklbw_Vx_Hx_Wx)
1854//{
1855// IEMOP_MNEMONIC(vpunpcklbw, "vpunpcklbw Vx, Hx, Wx");
1856// return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklbw);
1857//}
1858
1859/* Opcode VEX.F3.0F 0x60 - invalid */
1860
1861
1862/* Opcode VEX.0F 0x61 - invalid */
1863
1864/** Opcode VEX.66.0F 0x61 - vpunpcklwd Vx, Hx, Wx */
1865FNIEMOP_STUB(iemOp_vpunpcklwd_Vx_Hx_Wx);
1866//FNIEMOP_DEF(iemOp_vpunpcklwd_Vx_Hx_Wx)
1867//{
1868// IEMOP_MNEMONIC(vpunpcklwd, "vpunpcklwd Vx, Hx, Wx");
1869// return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklwd);
1870//}
1871
1872/* Opcode VEX.F3.0F 0x61 - invalid */
1873
1874
1875/* Opcode VEX.0F 0x62 - invalid */
1876
1877/** Opcode VEX.66.0F 0x62 - vpunpckldq Vx, Hx, Wx */
1878FNIEMOP_STUB(iemOp_vpunpckldq_Vx_Hx_Wx);
1879//FNIEMOP_DEF(iemOp_vpunpckldq_Vx_Hx_Wx)
1880//{
1881// IEMOP_MNEMONIC(vpunpckldq, "vpunpckldq Vx, Hx, Wx");
1882// return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpckldq);
1883//}
1884
1885/* Opcode VEX.F3.0F 0x62 - invalid */
1886
1887
1888
1889/* Opcode VEX.0F 0x63 - invalid */
1890/** Opcode VEX.66.0F 0x63 - vpacksswb Vx, Hx, Wx */
1891FNIEMOP_STUB(iemOp_vpacksswb_Vx_Hx_Wx);
1892/* Opcode VEX.F3.0F 0x63 - invalid */
1893
1894/* Opcode VEX.0F 0x64 - invalid */
1895/** Opcode VEX.66.0F 0x64 - vpcmpgtb Vx, Hx, Wx */
1896FNIEMOP_STUB(iemOp_vpcmpgtb_Vx_Hx_Wx);
1897/* Opcode VEX.F3.0F 0x64 - invalid */
1898
1899/* Opcode VEX.0F 0x65 - invalid */
1900/** Opcode VEX.66.0F 0x65 - vpcmpgtw Vx, Hx, Wx */
1901FNIEMOP_STUB(iemOp_vpcmpgtw_Vx_Hx_Wx);
1902/* Opcode VEX.F3.0F 0x65 - invalid */
1903
1904/* Opcode VEX.0F 0x66 - invalid */
1905/** Opcode VEX.66.0F 0x66 - vpcmpgtd Vx, Hx, Wx */
1906FNIEMOP_STUB(iemOp_vpcmpgtd_Vx_Hx_Wx);
1907/* Opcode VEX.F3.0F 0x66 - invalid */
1908
1909/* Opcode VEX.0F 0x67 - invalid */
1910/** Opcode VEX.66.0F 0x67 - vpackuswb Vx, Hx, W */
1911FNIEMOP_STUB(iemOp_vpackuswb_Vx_Hx_W);
1912/* Opcode VEX.F3.0F 0x67 - invalid */
1913
1914
1915///**
1916// * Common worker for SSE2 instructions on the form:
1917// * pxxxx xmm1, xmm2/mem128
1918// *
1919// * The 2nd operand is the second half of a register, which in the memory case
1920// * means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
1921// * where it may read the full 128 bits or only the upper 64 bits.
1922// *
1923// * Exceptions type 4.
1924// */
1925//FNIEMOP_DEF_1(iemOpCommonSse_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
1926//{
1927// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1928// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1929// {
1930// /*
1931// * Register, register.
1932// */
1933// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1934// IEM_MC_BEGIN(2, 0);
1935// IEM_MC_ARG(PRTUINT128U, pDst, 0);
1936// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
1937// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1938// IEM_MC_PREPARE_SSE_USAGE();
1939// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1940// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
1941// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
1942// IEM_MC_ADVANCE_RIP();
1943// IEM_MC_END();
1944// }
1945// else
1946// {
1947// /*
1948// * Register, memory.
1949// */
1950// IEM_MC_BEGIN(2, 2);
1951// IEM_MC_ARG(PRTUINT128U, pDst, 0);
1952// IEM_MC_LOCAL(RTUINT128U, uSrc);
1953// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
1954// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1955//
1956// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1957// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1958// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1959// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */
1960//
1961// IEM_MC_PREPARE_SSE_USAGE();
1962// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
1963// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
1964//
1965// IEM_MC_ADVANCE_RIP();
1966// IEM_MC_END();
1967// }
1968// return VINF_SUCCESS;
1969//}
1970
1971
1972/* Opcode VEX.0F 0x68 - invalid */
1973
1974/** Opcode VEX.66.0F 0x68 - vpunpckhbw Vx, Hx, Wx */
1975FNIEMOP_STUB(iemOp_vpunpckhbw_Vx_Hx_Wx);
1976//FNIEMOP_DEF(iemOp_vpunpckhbw_Vx_Hx_Wx)
1977//{
1978// IEMOP_MNEMONIC(vpunpckhbw, "vpunpckhbw Vx, Hx, Wx");
1979// return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhbw);
1980//}
1981/* Opcode VEX.F3.0F 0x68 - invalid */
1982
1983
1984/* Opcode VEX.0F 0x69 - invalid */
1985
1986/** Opcode VEX.66.0F 0x69 - vpunpckhwd Vx, Hx, Wx */
1987FNIEMOP_STUB(iemOp_vpunpckhwd_Vx_Hx_Wx);
1988//FNIEMOP_DEF(iemOp_vpunpckhwd_Vx_Hx_Wx)
1989//{
1990// IEMOP_MNEMONIC(vpunpckhwd, "vpunpckhwd Vx, Hx, Wx");
1991// return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhwd);
1992//
1993//}
1994/* Opcode VEX.F3.0F 0x69 - invalid */
1995
1996
1997/* Opcode VEX.0F 0x6a - invalid */
1998
1999/** Opcode VEX.66.0F 0x6a - vpunpckhdq Vx, Hx, W */
2000FNIEMOP_STUB(iemOp_vpunpckhdq_Vx_Hx_W);
2001//FNIEMOP_DEF(iemOp_vpunpckhdq_Vx_Hx_W)
2002//{
2003// IEMOP_MNEMONIC(vpunpckhdq, "vpunpckhdq Vx, Hx, W");
2004// return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhdq);
2005//}
2006/* Opcode VEX.F3.0F 0x6a - invalid */
2007
2008
2009/* Opcode VEX.0F 0x6b - invalid */
2010/** Opcode VEX.66.0F 0x6b - vpackssdw Vx, Hx, Wx */
2011FNIEMOP_STUB(iemOp_vpackssdw_Vx_Hx_Wx);
2012/* Opcode VEX.F3.0F 0x6b - invalid */
2013
2014
2015/* Opcode VEX.0F 0x6c - invalid */
2016
2017/** Opcode VEX.66.0F 0x6c - vpunpcklqdq Vx, Hx, Wx */
2018FNIEMOP_STUB(iemOp_vpunpcklqdq_Vx_Hx_Wx);
2019//FNIEMOP_DEF(iemOp_vpunpcklqdq_Vx_Hx_Wx)
2020//{
2021// IEMOP_MNEMONIC(vpunpcklqdq, "vpunpcklqdq Vx, Hx, Wx");
2022// return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklqdq);
2023//}
2024
2025/* Opcode VEX.F3.0F 0x6c - invalid */
2026/* Opcode VEX.F2.0F 0x6c - invalid */
2027
2028
2029/* Opcode VEX.0F 0x6d - invalid */
2030
2031/** Opcode VEX.66.0F 0x6d - vpunpckhqdq Vx, Hx, W */
2032FNIEMOP_STUB(iemOp_vpunpckhqdq_Vx_Hx_W);
2033//FNIEMOP_DEF(iemOp_vpunpckhqdq_Vx_Hx_W)
2034//{
2035// IEMOP_MNEMONIC(punpckhqdq, "punpckhqdq");
2036// return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhqdq);
2037//}
2038
2039/* Opcode VEX.F3.0F 0x6d - invalid */
2040
2041
2042/* Opcode VEX.0F 0x6e - invalid */
2043
2044FNIEMOP_DEF(iemOp_vmovd_q_Vy_Ey)
2045{
2046 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2047 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2048 {
2049 /**
2050 * @opcode 0x6e
2051 * @opcodesub rex.w=1
2052 * @oppfx 0x66
2053 * @opcpuid avx
2054 * @opgroup og_avx_simdint_datamov
2055 * @opxcpttype 5
2056 * @optest 64-bit / op1=1 op2=2 -> op1=2
2057 * @optest 64-bit / op1=0 op2=-42 -> op1=-42
2058 */
2059 IEMOP_MNEMONIC2(VEX_RM, VMOVQ, vmovq, Vq_WO, Eq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX);
2060 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2061 {
2062 /* XMM, greg64 */
2063 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2064 IEM_MC_BEGIN(0, 1);
2065 IEM_MC_LOCAL(uint64_t, u64Tmp);
2066
2067 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2068 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2069
2070 IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2071 IEM_MC_STORE_YREG_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
2072
2073 IEM_MC_ADVANCE_RIP();
2074 IEM_MC_END();
2075 }
2076 else
2077 {
2078 /* XMM, [mem64] */
2079 IEM_MC_BEGIN(0, 2);
2080 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2081 IEM_MC_LOCAL(uint64_t, u64Tmp);
2082
2083 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2084 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2085 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2086 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2087
2088 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2089 IEM_MC_STORE_YREG_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u64Tmp);
2090
2091 IEM_MC_ADVANCE_RIP();
2092 IEM_MC_END();
2093 }
2094 }
2095 else
2096 {
2097 /**
2098 * @opdone
2099 * @opcode 0x6e
2100 * @opcodesub rex.w=0
2101 * @oppfx 0x66
2102 * @opcpuid avx
2103 * @opgroup og_avx_simdint_datamov
2104 * @opxcpttype 5
2105 * @opfunction iemOp_vmovd_q_Vy_Ey
2106 * @optest op1=1 op2=2 -> op1=2
2107 * @optest op1=0 op2=-42 -> op1=-42
2108 */
2109 IEMOP_MNEMONIC2(VEX_RM, VMOVD, vmovd, Vd_WO, Ed, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OZ_PFX);
2110 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2111 {
2112 /* XMM, greg32 */
2113 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2114 IEM_MC_BEGIN(0, 1);
2115 IEM_MC_LOCAL(uint32_t, u32Tmp);
2116
2117 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2118 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2119
2120 IEM_MC_FETCH_GREG_U32(u32Tmp, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2121 IEM_MC_STORE_YREG_U32_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
2122
2123 IEM_MC_ADVANCE_RIP();
2124 IEM_MC_END();
2125 }
2126 else
2127 {
2128 /* XMM, [mem32] */
2129 IEM_MC_BEGIN(0, 2);
2130 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2131 IEM_MC_LOCAL(uint32_t, u32Tmp);
2132
2133 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2134 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
2135 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2136 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2137
2138 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2139 IEM_MC_STORE_YREG_U32_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u32Tmp);
2140
2141 IEM_MC_ADVANCE_RIP();
2142 IEM_MC_END();
2143 }
2144 }
2145 return VINF_SUCCESS;
2146}
2147
2148
2149/* Opcode VEX.F3.0F 0x6e - invalid */
2150
2151
2152/* Opcode VEX.0F 0x6f - invalid */
2153
2154/**
2155 * @opcode 0x6f
2156 * @oppfx 0x66
2157 * @opcpuid avx
2158 * @opgroup og_avx_simdint_datamove
2159 * @opxcpttype 1
2160 * @optest op1=1 op2=2 -> op1=2
2161 * @optest op1=0 op2=-42 -> op1=-42
2162 */
2163FNIEMOP_DEF(iemOp_vmovdqa_Vx_Wx)
2164{
2165 IEMOP_MNEMONIC2(VEX_RM, VMOVDQA, vmovdqa, Vx_WO, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
2166 Assert(pVCpu->iem.s.uVexLength <= 1);
2167 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2168 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2169 {
2170 /*
2171 * Register, register.
2172 */
2173 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2174 IEM_MC_BEGIN(0, 0);
2175
2176 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2177 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2178 if (pVCpu->iem.s.uVexLength == 0)
2179 IEM_MC_COPY_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
2180 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2181 else
2182 IEM_MC_COPY_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
2183 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2184 IEM_MC_ADVANCE_RIP();
2185 IEM_MC_END();
2186 }
2187 else if (pVCpu->iem.s.uVexLength == 0)
2188 {
2189 /*
2190 * Register, memory128.
2191 */
2192 IEM_MC_BEGIN(0, 2);
2193 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
2194 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2195
2196 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2197 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2198 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2199 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2200
2201 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2202 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u128Tmp);
2203
2204 IEM_MC_ADVANCE_RIP();
2205 IEM_MC_END();
2206 }
2207 else
2208 {
2209 /*
2210 * Register, memory256.
2211 */
2212 IEM_MC_BEGIN(0, 2);
2213 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
2214 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2215
2216 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2217 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2218 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2219 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2220
2221 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2222 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u256Tmp);
2223
2224 IEM_MC_ADVANCE_RIP();
2225 IEM_MC_END();
2226 }
2227 return VINF_SUCCESS;
2228}
2229
2230/**
2231 * @opcode 0x6f
2232 * @oppfx 0xf3
2233 * @opcpuid avx
2234 * @opgroup og_avx_simdint_datamove
2235 * @opxcpttype 4UA
2236 * @optest op1=1 op2=2 -> op1=2
2237 * @optest op1=0 op2=-42 -> op1=-42
2238 */
2239FNIEMOP_DEF(iemOp_vmovdqu_Vx_Wx)
2240{
2241 IEMOP_MNEMONIC2(VEX_RM, VMOVDQU, vmovdqu, Vx_WO, Wx, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
2242 Assert(pVCpu->iem.s.uVexLength <= 1);
2243 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2244 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2245 {
2246 /*
2247 * Register, register.
2248 */
2249 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2250 IEM_MC_BEGIN(0, 0);
2251
2252 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2253 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2254 if (pVCpu->iem.s.uVexLength == 0)
2255 IEM_MC_COPY_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
2256 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2257 else
2258 IEM_MC_COPY_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg,
2259 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2260 IEM_MC_ADVANCE_RIP();
2261 IEM_MC_END();
2262 }
2263 else if (pVCpu->iem.s.uVexLength == 0)
2264 {
2265 /*
2266 * Register, memory128.
2267 */
2268 IEM_MC_BEGIN(0, 2);
2269 IEM_MC_LOCAL(RTUINT128U, u128Tmp);
2270 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2271
2272 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2273 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2274 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2275 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2276
2277 IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2278 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u128Tmp);
2279
2280 IEM_MC_ADVANCE_RIP();
2281 IEM_MC_END();
2282 }
2283 else
2284 {
2285 /*
2286 * Register, memory256.
2287 */
2288 IEM_MC_BEGIN(0, 2);
2289 IEM_MC_LOCAL(RTUINT256U, u256Tmp);
2290 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2291
2292 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2293 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
2294 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
2295 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
2296
2297 IEM_MC_FETCH_MEM_U256(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2298 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, u256Tmp);
2299
2300 IEM_MC_ADVANCE_RIP();
2301 IEM_MC_END();
2302 }
2303 return VINF_SUCCESS;
2304}
2305
2306
2307/* Opcode VEX.0F 0x70 - invalid */
2308
2309/** Opcode VEX.66.0F 0x70 - vpshufd Vx, Wx, Ib */
2310FNIEMOP_STUB(iemOp_vpshufd_Vx_Wx_Ib);
2311//FNIEMOP_DEF(iemOp_vpshufd_Vx_Wx_Ib)
2312//{
2313// IEMOP_MNEMONIC(vpshufd_Vx_Wx_Ib, "vpshufd Vx,Wx,Ib");
2314// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2315// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2316// {
2317// /*
2318// * Register, register.
2319// */
2320// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
2321// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2322//
2323// IEM_MC_BEGIN(3, 0);
2324// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2325// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2326// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
2327// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2328// IEM_MC_PREPARE_SSE_USAGE();
2329// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2330// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2331// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufd, pDst, pSrc, bEvilArg);
2332// IEM_MC_ADVANCE_RIP();
2333// IEM_MC_END();
2334// }
2335// else
2336// {
2337// /*
2338// * Register, memory.
2339// */
2340// IEM_MC_BEGIN(3, 2);
2341// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2342// IEM_MC_LOCAL(RTUINT128U, uSrc);
2343// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
2344// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2345//
2346// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2347// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
2348// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
2349// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2350// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2351//
2352// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2353// IEM_MC_PREPARE_SSE_USAGE();
2354// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2355// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufd, pDst, pSrc, bEvilArg);
2356//
2357// IEM_MC_ADVANCE_RIP();
2358// IEM_MC_END();
2359// }
2360// return VINF_SUCCESS;
2361//}
2362
2363/** Opcode VEX.F3.0F 0x70 - vpshufhw Vx, Wx, Ib */
2364FNIEMOP_STUB(iemOp_vpshufhw_Vx_Wx_Ib);
2365//FNIEMOP_DEF(iemOp_vpshufhw_Vx_Wx_Ib)
2366//{
2367// IEMOP_MNEMONIC(vpshufhw_Vx_Wx_Ib, "vpshufhw Vx,Wx,Ib");
2368// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2369// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2370// {
2371// /*
2372// * Register, register.
2373// */
2374// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
2375// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2376//
2377// IEM_MC_BEGIN(3, 0);
2378// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2379// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2380// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
2381// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2382// IEM_MC_PREPARE_SSE_USAGE();
2383// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2384// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2385// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufhw, pDst, pSrc, bEvilArg);
2386// IEM_MC_ADVANCE_RIP();
2387// IEM_MC_END();
2388// }
2389// else
2390// {
2391// /*
2392// * Register, memory.
2393// */
2394// IEM_MC_BEGIN(3, 2);
2395// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2396// IEM_MC_LOCAL(RTUINT128U, uSrc);
2397// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
2398// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2399//
2400// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2401// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
2402// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
2403// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2404// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2405//
2406// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2407// IEM_MC_PREPARE_SSE_USAGE();
2408// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2409// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufhw, pDst, pSrc, bEvilArg);
2410//
2411// IEM_MC_ADVANCE_RIP();
2412// IEM_MC_END();
2413// }
2414// return VINF_SUCCESS;
2415//}
2416
2417/** Opcode VEX.F2.0F 0x70 - vpshuflw Vx, Wx, Ib */
2418FNIEMOP_STUB(iemOp_vpshuflw_Vx_Wx_Ib);
2419//FNIEMOP_DEF(iemOp_vpshuflw_Vx_Wx_Ib)
2420//{
2421// IEMOP_MNEMONIC(vpshuflw_Vx_Wx_Ib, "vpshuflw Vx,Wx,Ib");
2422// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2423// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2424// {
2425// /*
2426// * Register, register.
2427// */
2428// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
2429// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2430//
2431// IEM_MC_BEGIN(3, 0);
2432// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2433// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2434// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
2435// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2436// IEM_MC_PREPARE_SSE_USAGE();
2437// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2438// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2439// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshuflw, pDst, pSrc, bEvilArg);
2440// IEM_MC_ADVANCE_RIP();
2441// IEM_MC_END();
2442// }
2443// else
2444// {
2445// /*
2446// * Register, memory.
2447// */
2448// IEM_MC_BEGIN(3, 2);
2449// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2450// IEM_MC_LOCAL(RTUINT128U, uSrc);
2451// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
2452// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2453//
2454// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2455// uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
2456// IEM_MC_ARG_CONST(uint8_t, bEvilArg, /*=*/ bEvil, 2);
2457// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2458// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2459//
2460// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2461// IEM_MC_PREPARE_SSE_USAGE();
2462// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2463// IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshuflw, pDst, pSrc, bEvilArg);
2464//
2465// IEM_MC_ADVANCE_RIP();
2466// IEM_MC_END();
2467// }
2468// return VINF_SUCCESS;
2469//}
2470
2471
2472/* Opcode VEX.0F 0x71 11/2 - invalid. */
2473/** Opcode VEX.66.0F 0x71 11/2. */
2474FNIEMOP_STUB_1(iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, uint8_t, bRm);
2475
2476/* Opcode VEX.0F 0x71 11/4 - invalid */
2477/** Opcode VEX.66.0F 0x71 11/4. */
2478FNIEMOP_STUB_1(iemOp_VGrp12_vpsraw_Hx_Ux_Ib, uint8_t, bRm);
2479
2480/* Opcode VEX.0F 0x71 11/6 - invalid */
2481/** Opcode VEX.66.0F 0x71 11/6. */
2482FNIEMOP_STUB_1(iemOp_VGrp12_vpsllw_Hx_Ux_Ib, uint8_t, bRm);
2483
2484
2485/**
2486 * VEX Group 12 jump table for register variant.
2487 */
2488IEM_STATIC const PFNIEMOPRM g_apfnVexGroup12RegReg[] =
2489{
2490 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2491 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2492 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2493 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2494 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsraw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2495 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2496 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp12_vpsllw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2497 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
2498};
2499AssertCompile(RT_ELEMENTS(g_apfnVexGroup12RegReg) == 8*4);
2500
2501
2502/** Opcode VEX.0F 0x71. */
2503FNIEMOP_DEF(iemOp_VGrp12)
2504{
2505 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2506 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2507 /* register, register */
2508 return FNIEMOP_CALL_1(g_apfnVexGroup12RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
2509 + pVCpu->iem.s.idxPrefix], bRm);
2510 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
2511}
2512
2513
2514/* Opcode VEX.0F 0x72 11/2 - invalid. */
2515/** Opcode VEX.66.0F 0x72 11/2. */
2516FNIEMOP_STUB_1(iemOp_VGrp13_vpsrld_Hx_Ux_Ib, uint8_t, bRm);
2517
2518/* Opcode VEX.0F 0x72 11/4 - invalid. */
2519/** Opcode VEX.66.0F 0x72 11/4. */
2520FNIEMOP_STUB_1(iemOp_VGrp13_vpsrad_Hx_Ux_Ib, uint8_t, bRm);
2521
2522/* Opcode VEX.0F 0x72 11/6 - invalid. */
2523/** Opcode VEX.66.0F 0x72 11/6. */
2524FNIEMOP_STUB_1(iemOp_VGrp13_vpslld_Hx_Ux_Ib, uint8_t, bRm);
2525
2526
2527/**
2528 * Group 13 jump table for register variant.
2529 */
2530IEM_STATIC const PFNIEMOPRM g_apfnVexGroup13RegReg[] =
2531{
2532 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2533 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2534 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2535 /* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2536 /* /4 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpsrad_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2537 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2538 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp13_vpslld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2539 /* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
2540};
2541AssertCompile(RT_ELEMENTS(g_apfnVexGroup13RegReg) == 8*4);
2542
2543/** Opcode VEX.0F 0x72. */
2544FNIEMOP_DEF(iemOp_VGrp13)
2545{
2546 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2547 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2548 /* register, register */
2549 return FNIEMOP_CALL_1(g_apfnVexGroup13RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
2550 + pVCpu->iem.s.idxPrefix], bRm);
2551 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
2552}
2553
2554
2555/* Opcode VEX.0F 0x73 11/2 - invalid. */
2556/** Opcode VEX.66.0F 0x73 11/2. */
2557FNIEMOP_STUB_1(iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, uint8_t, bRm);
2558
2559/** Opcode VEX.66.0F 0x73 11/3. */
2560FNIEMOP_STUB_1(iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, uint8_t, bRm);
2561
2562/* Opcode VEX.0F 0x73 11/6 - invalid. */
2563/** Opcode VEX.66.0F 0x73 11/6. */
2564FNIEMOP_STUB_1(iemOp_VGrp14_vpsllq_Hx_Ux_Ib, uint8_t, bRm);
2565
2566/** Opcode VEX.66.0F 0x73 11/7. */
2567FNIEMOP_STUB_1(iemOp_VGrp14_vpslldq_Hx_Ux_Ib, uint8_t, bRm);
2568
2569/**
2570 * Group 14 jump table for register variant.
2571 */
2572IEM_STATIC const PFNIEMOPRM g_apfnVexGroup14RegReg[] =
2573{
2574 /* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2575 /* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2576 /* /2 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2577 /* /3 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsrldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2578 /* /4 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2579 /* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
2580 /* /6 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpsllq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2581 /* /7 */ iemOp_InvalidWithRMNeedImm8, iemOp_VGrp14_vpslldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
2582};
2583AssertCompile(RT_ELEMENTS(g_apfnVexGroup14RegReg) == 8*4);
2584
2585
2586/** Opcode VEX.0F 0x73. */
2587FNIEMOP_DEF(iemOp_VGrp14)
2588{
2589 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2590 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2591 /* register, register */
2592 return FNIEMOP_CALL_1(g_apfnVexGroup14RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
2593 + pVCpu->iem.s.idxPrefix], bRm);
2594 return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
2595}
2596
2597
2598///**
2599// * Common worker for SSE2 instructions on the forms:
2600// * pxxx xmm1, xmm2/mem128
2601// *
2602// * Proper alignment of the 128-bit operand is enforced.
2603// * Exceptions type 4. SSE2 cpuid checks.
2604// */
2605//FNIEMOP_DEF_1(iemOpCommonSse2_FullFull_To_Full, PCIEMOPMEDIAF2, pImpl)
2606//{
2607// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2608// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2609// {
2610// /*
2611// * Register, register.
2612// */
2613// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2614// IEM_MC_BEGIN(2, 0);
2615// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2616// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2617// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2618// IEM_MC_PREPARE_SSE_USAGE();
2619// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2620// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
2621// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2622// IEM_MC_ADVANCE_RIP();
2623// IEM_MC_END();
2624// }
2625// else
2626// {
2627// /*
2628// * Register, memory.
2629// */
2630// IEM_MC_BEGIN(2, 2);
2631// IEM_MC_ARG(PRTUINT128U, pDst, 0);
2632// IEM_MC_LOCAL(RTUINT128U, uSrc);
2633// IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
2634// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2635//
2636// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2637// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2638// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2639// IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2640//
2641// IEM_MC_PREPARE_SSE_USAGE();
2642// IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2643// IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2644//
2645// IEM_MC_ADVANCE_RIP();
2646// IEM_MC_END();
2647// }
2648// return VINF_SUCCESS;
2649//}
2650
2651
2652/* Opcode VEX.0F 0x74 - invalid */
2653
2654/** Opcode VEX.66.0F 0x74 - vpcmpeqb Vx, Hx, Wx */
2655FNIEMOP_STUB(iemOp_vpcmpeqb_Vx_Hx_Wx);
2656//FNIEMOP_DEF(iemOp_vpcmpeqb_Vx_Hx_Wx)
2657//{
2658// IEMOP_MNEMONIC(vpcmpeqb, "vpcmpeqb");
2659// return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqb);
2660//}
2661
2662/* Opcode VEX.F3.0F 0x74 - invalid */
2663/* Opcode VEX.F2.0F 0x74 - invalid */
2664
2665
2666/* Opcode VEX.0F 0x75 - invalid */
2667
2668/** Opcode VEX.66.0F 0x75 - vpcmpeqw Vx, Hx, Wx */
2669FNIEMOP_STUB(iemOp_vpcmpeqw_Vx_Hx_Wx);
2670//FNIEMOP_DEF(iemOp_vpcmpeqw_Vx_Hx_Wx)
2671//{
2672// IEMOP_MNEMONIC(vpcmpeqw, "vpcmpeqw");
2673// return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqw);
2674//}
2675
2676/* Opcode VEX.F3.0F 0x75 - invalid */
2677/* Opcode VEX.F2.0F 0x75 - invalid */
2678
2679
2680/* Opcode VEX.0F 0x76 - invalid */
2681
2682/** Opcode VEX.66.0F 0x76 - vpcmpeqd Vx, Hx, Wx */
2683FNIEMOP_STUB(iemOp_vpcmpeqd_Vx_Hx_Wx);
2684//FNIEMOP_DEF(iemOp_vpcmpeqd_Vx_Hx_Wx)
2685//{
2686// IEMOP_MNEMONIC(vpcmpeqd, "vpcmpeqd");
2687// return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqd);
2688//}
2689
2690/* Opcode VEX.F3.0F 0x76 - invalid */
2691/* Opcode VEX.F2.0F 0x76 - invalid */
2692
2693
2694/** Opcode VEX.0F 0x77 - vzeroupperv vzeroallv */
2695FNIEMOP_STUB(iemOp_vzeroupperv__vzeroallv);
2696/* Opcode VEX.66.0F 0x77 - invalid */
2697/* Opcode VEX.F3.0F 0x77 - invalid */
2698/* Opcode VEX.F2.0F 0x77 - invalid */
2699
2700/* Opcode VEX.0F 0x78 - invalid */
2701/* Opcode VEX.66.0F 0x78 - invalid */
2702/* Opcode VEX.F3.0F 0x78 - invalid */
2703/* Opcode VEX.F2.0F 0x78 - invalid */
2704
2705/* Opcode VEX.0F 0x79 - invalid */
2706/* Opcode VEX.66.0F 0x79 - invalid */
2707/* Opcode VEX.F3.0F 0x79 - invalid */
2708/* Opcode VEX.F2.0F 0x79 - invalid */
2709
2710/* Opcode VEX.0F 0x7a - invalid */
2711/* Opcode VEX.66.0F 0x7a - invalid */
2712/* Opcode VEX.F3.0F 0x7a - invalid */
2713/* Opcode VEX.F2.0F 0x7a - invalid */
2714
2715/* Opcode VEX.0F 0x7b - invalid */
2716/* Opcode VEX.66.0F 0x7b - invalid */
2717/* Opcode VEX.F3.0F 0x7b - invalid */
2718/* Opcode VEX.F2.0F 0x7b - invalid */
2719
2720/* Opcode VEX.0F 0x7c - invalid */
2721/** Opcode VEX.66.0F 0x7c - vhaddpd Vpd, Hpd, Wpd */
2722FNIEMOP_STUB(iemOp_vhaddpd_Vpd_Hpd_Wpd);
2723/* Opcode VEX.F3.0F 0x7c - invalid */
2724/** Opcode VEX.F2.0F 0x7c - vhaddps Vps, Hps, Wps */
2725FNIEMOP_STUB(iemOp_vhaddps_Vps_Hps_Wps);
2726
2727/* Opcode VEX.0F 0x7d - invalid */
2728/** Opcode VEX.66.0F 0x7d - vhsubpd Vpd, Hpd, Wpd */
2729FNIEMOP_STUB(iemOp_vhsubpd_Vpd_Hpd_Wpd);
2730/* Opcode VEX.F3.0F 0x7d - invalid */
2731/** Opcode VEX.F2.0F 0x7d - vhsubps Vps, Hps, Wps */
2732FNIEMOP_STUB(iemOp_vhsubps_Vps_Hps_Wps);
2733
2734
2735/* Opcode VEX.0F 0x7e - invalid */
2736
2737/** Opcode VEX.66.0F 0x7e - vmovd_q Ey, Vy */
2738FNIEMOP_STUB(iemOp_vmovd_q_Ey_Vy);
2739//FNIEMOP_DEF(iemOp_vmovd_q_Ey_Vy)
2740//{
2741// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2742// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2743// IEMOP_MNEMONIC(vmovq_Eq_Wq, "vmovq Eq,Wq");
2744// else
2745// IEMOP_MNEMONIC(vmovd_Ed_Wd, "vmovd Ed,Wd");
2746// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2747// {
2748// /* greg, XMM */
2749// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2750// IEM_MC_BEGIN(0, 1);
2751// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2752// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2753// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2754// {
2755// IEM_MC_LOCAL(uint64_t, u64Tmp);
2756// IEM_MC_FETCH_XREG_U64(u64Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2757// IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u64Tmp);
2758// }
2759// else
2760// {
2761// IEM_MC_LOCAL(uint32_t, u32Tmp);
2762// IEM_MC_FETCH_XREG_U32(u32Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2763// IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, u32Tmp);
2764// }
2765// IEM_MC_ADVANCE_RIP();
2766// IEM_MC_END();
2767// }
2768// else
2769// {
2770// /* [mem], XMM */
2771// IEM_MC_BEGIN(0, 2);
2772// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2773// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2774// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
2775// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2776// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2777// if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2778// {
2779// IEM_MC_LOCAL(uint64_t, u64Tmp);
2780// IEM_MC_FETCH_XREG_U64(u64Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2781// IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
2782// }
2783// else
2784// {
2785// IEM_MC_LOCAL(uint32_t, u32Tmp);
2786// IEM_MC_FETCH_XREG_U32(u32Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2787// IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
2788// }
2789// IEM_MC_ADVANCE_RIP();
2790// IEM_MC_END();
2791// }
2792// return VINF_SUCCESS;
2793//}
2794
2795/** Opcode VEX.F3.0F 0x7e - vmovq Vq, Wq */
2796FNIEMOP_STUB(iemOp_vmovq_Vq_Wq);
2797/* Opcode VEX.F2.0F 0x7e - invalid */
2798
2799
2800/* Opcode VEX.0F 0x7f - invalid */
2801
2802/** Opcode VEX.66.0F 0x7f - vmovdqa Wx,Vx */
2803FNIEMOP_STUB(iemOp_vmovdqa_Wx_Vx);
2804//FNIEMOP_DEF(iemOp_vmovdqa_Wx_Vx)
2805//{
2806// IEMOP_MNEMONIC(vmovdqa_Wdq_Vdq, "vmovdqa Wx,Vx");
2807// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2808// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2809// {
2810// /*
2811// * Register, register.
2812// */
2813// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2814// IEM_MC_BEGIN(0, 0);
2815// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2816// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2817// IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
2818// ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2819// IEM_MC_ADVANCE_RIP();
2820// IEM_MC_END();
2821// }
2822// else
2823// {
2824// /*
2825// * Register, memory.
2826// */
2827// IEM_MC_BEGIN(0, 2);
2828// IEM_MC_LOCAL(RTUINT128U, u128Tmp);
2829// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2830//
2831// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2832// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2833// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2834// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2835//
2836// IEM_MC_FETCH_XREG_U128(u128Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2837// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
2838//
2839// IEM_MC_ADVANCE_RIP();
2840// IEM_MC_END();
2841// }
2842// return VINF_SUCCESS;
2843//}
2844
2845/** Opcode VEX.F3.0F 0x7f - vmovdqu Wx,Vx */
2846FNIEMOP_STUB(iemOp_vmovdqu_Wx_Vx);
2847//FNIEMOP_DEF(iemOp_vmovdqu_Wx_Vx)
2848//{
2849// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2850// IEMOP_MNEMONIC(vmovdqu_Wdq_Vdq, "vmovdqu Wx,Vx");
2851// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2852// {
2853// /*
2854// * Register, register.
2855// */
2856// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2857// IEM_MC_BEGIN(0, 0);
2858// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2859// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2860// IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB,
2861// ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2862// IEM_MC_ADVANCE_RIP();
2863// IEM_MC_END();
2864// }
2865// else
2866// {
2867// /*
2868// * Register, memory.
2869// */
2870// IEM_MC_BEGIN(0, 2);
2871// IEM_MC_LOCAL(RTUINT128U, u128Tmp);
2872// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2873//
2874// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2875// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2876// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2877// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2878//
2879// IEM_MC_FETCH_XREG_U128(u128Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
2880// IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
2881//
2882// IEM_MC_ADVANCE_RIP();
2883// IEM_MC_END();
2884// }
2885// return VINF_SUCCESS;
2886//}
2887
2888/* Opcode VEX.F2.0F 0x7f - invalid */
2889
2890
2891/* Opcode VEX.0F 0x80 - invalid */
2892/* Opcode VEX.0F 0x81 - invalid */
2893/* Opcode VEX.0F 0x82 - invalid */
2894/* Opcode VEX.0F 0x83 - invalid */
2895/* Opcode VEX.0F 0x84 - invalid */
2896/* Opcode VEX.0F 0x85 - invalid */
2897/* Opcode VEX.0F 0x86 - invalid */
2898/* Opcode VEX.0F 0x87 - invalid */
2899/* Opcode VEX.0F 0x88 - invalid */
2900/* Opcode VEX.0F 0x89 - invalid */
2901/* Opcode VEX.0F 0x8a - invalid */
2902/* Opcode VEX.0F 0x8b - invalid */
2903/* Opcode VEX.0F 0x8c - invalid */
2904/* Opcode VEX.0F 0x8d - invalid */
2905/* Opcode VEX.0F 0x8e - invalid */
2906/* Opcode VEX.0F 0x8f - invalid */
2907/* Opcode VEX.0F 0x90 - invalid */
2908/* Opcode VEX.0F 0x91 - invalid */
2909/* Opcode VEX.0F 0x92 - invalid */
2910/* Opcode VEX.0F 0x93 - invalid */
2911/* Opcode VEX.0F 0x94 - invalid */
2912/* Opcode VEX.0F 0x95 - invalid */
2913/* Opcode VEX.0F 0x96 - invalid */
2914/* Opcode VEX.0F 0x97 - invalid */
2915/* Opcode VEX.0F 0x98 - invalid */
2916/* Opcode VEX.0F 0x99 - invalid */
2917/* Opcode VEX.0F 0x9a - invalid */
2918/* Opcode VEX.0F 0x9b - invalid */
2919/* Opcode VEX.0F 0x9c - invalid */
2920/* Opcode VEX.0F 0x9d - invalid */
2921/* Opcode VEX.0F 0x9e - invalid */
2922/* Opcode VEX.0F 0x9f - invalid */
2923/* Opcode VEX.0F 0xa0 - invalid */
2924/* Opcode VEX.0F 0xa1 - invalid */
2925/* Opcode VEX.0F 0xa2 - invalid */
2926/* Opcode VEX.0F 0xa3 - invalid */
2927/* Opcode VEX.0F 0xa4 - invalid */
2928/* Opcode VEX.0F 0xa5 - invalid */
2929/* Opcode VEX.0F 0xa6 - invalid */
2930/* Opcode VEX.0F 0xa7 - invalid */
2931/* Opcode VEX.0F 0xa8 - invalid */
2932/* Opcode VEX.0F 0xa9 - invalid */
2933/* Opcode VEX.0F 0xaa - invalid */
2934/* Opcode VEX.0F 0xab - invalid */
2935/* Opcode VEX.0F 0xac - invalid */
2936/* Opcode VEX.0F 0xad - invalid */
2937
2938
2939/* Opcode VEX.0F 0xae mem/0 - invalid. */
2940/* Opcode VEX.0F 0xae mem/1 - invalid. */
2941
2942/**
2943 * @ opmaps grp15
2944 * @ opcode !11/2
2945 * @ oppfx none
2946 * @ opcpuid sse
2947 * @ opgroup og_sse_mxcsrsm
2948 * @ opxcpttype 5
2949 * @ optest op1=0 -> mxcsr=0
2950 * @ optest op1=0x2083 -> mxcsr=0x2083
2951 * @ optest op1=0xfffffffe -> value.xcpt=0xd
2952 * @ optest op1=0x2083 cr0|=ts -> value.xcpt=0x7
2953 * @ optest op1=0x2083 cr0|=em -> value.xcpt=0x6
2954 * @ optest op1=0x2083 cr0|=mp -> mxcsr=0x2083
2955 * @ optest op1=0x2083 cr4&~=osfxsr -> value.xcpt=0x6
2956 * @ optest op1=0x2083 cr0|=ts,em -> value.xcpt=0x6
2957 * @ optest op1=0x2083 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
2958 * @ optest op1=0x2083 cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
2959 * @ optest op1=0x2083 cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
2960 */
2961FNIEMOP_STUB_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm);
2962//FNIEMOP_DEF_1(iemOp_VGrp15_vldmxcsr, uint8_t, bRm)
2963//{
2964// IEMOP_MNEMONIC1(M_MEM, VLDMXCSR, vldmxcsr, MdRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
2965// if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse)
2966// return IEMOP_RAISE_INVALID_OPCODE();
2967//
2968// IEM_MC_BEGIN(2, 0);
2969// IEM_MC_ARG(uint8_t, iEffSeg, 0);
2970// IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
2971// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
2972// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2973// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
2974// IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
2975// IEM_MC_CALL_CIMPL_2(iemCImpl_ldmxcsr, iEffSeg, GCPtrEff);
2976// IEM_MC_END();
2977// return VINF_SUCCESS;
2978//}
2979
2980
2981/**
2982 * @opmaps vexgrp15
2983 * @opcode !11/3
2984 * @oppfx none
2985 * @opcpuid avx
2986 * @opgroup og_avx_mxcsrsm
2987 * @opxcpttype 5
2988 * @optest mxcsr=0 -> op1=0
2989 * @optest mxcsr=0x2083 -> op1=0x2083
2990 * @optest mxcsr=0x2084 cr0|=ts -> value.xcpt=0x7
2991 * @optest !amd / mxcsr=0x2085 cr0|=em -> op1=0x2085
2992 * @optest amd / mxcsr=0x2085 cr0|=em -> value.xcpt=0x6
2993 * @optest mxcsr=0x2086 cr0|=mp -> op1=0x2086
2994 * @optest mxcsr=0x2087 cr4&~=osfxsr -> op1=0x2087
2995 * @optest mxcsr=0x208f cr4&~=osxsave -> value.xcpt=0x6
2996 * @optest mxcsr=0x2087 cr4&~=osfxsr,osxsave -> value.xcpt=0x6
2997 * @optest !amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x7
2998 * @optest amd / mxcsr=0x2088 cr0|=ts,em -> value.xcpt=0x6
2999 * @optest !amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> op1=0x2089
3000 * @optest amd / mxcsr=0x2089 cr0|=em cr4&~=osfxsr -> value.xcpt=0x6
3001 * @optest !amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x7
3002 * @optest amd / mxcsr=0x208a cr0|=ts,em cr4&~=osfxsr -> value.xcpt=0x6
3003 * @optest !amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x7
3004 * @optest amd / mxcsr=0x208b cr0|=ts,em,mp cr4&~=osfxsr -> value.xcpt=0x6
3005 * @optest !amd / mxcsr=0x208c xcr0&~=all_avx -> value.xcpt=0x6
3006 * @optest amd / mxcsr=0x208c xcr0&~=all_avx -> op1=0x208c
3007 * @optest !amd / mxcsr=0x208d xcr0&~=all_avx_sse -> value.xcpt=0x6
3008 * @optest amd / mxcsr=0x208d xcr0&~=all_avx_sse -> op1=0x208d
3009 * @optest !amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x6
3010 * @optest amd / mxcsr=0x208e xcr0&~=all_avx cr0|=ts -> value.xcpt=0x7
3011 * @optest mxcsr=0x2082 cr0|=ts cr4&~=osxsave -> value.xcpt=0x6
3012 * @optest mxcsr=0x2081 xcr0&~=all_avx cr0|=ts cr4&~=osxsave
3013 * -> value.xcpt=0x6
3014 * @remarks AMD Jaguar CPU (f0x16,m0,s1) \#UD when CR0.EM is set. It also
3015 * doesn't seem to check XCR0[2:1] != 11b. This does not match the
3016 * APMv4 rev 3.17 page 509.
3017 * @todo Test this instruction on AMD Ryzen.
3018 */
3019FNIEMOP_DEF_1(iemOp_VGrp15_vstmxcsr, uint8_t, bRm)
3020{
3021 IEMOP_MNEMONIC1(VEX_M_MEM, VSTMXCSR, vstmxcsr, Md_WO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
3022 IEM_MC_BEGIN(2, 0);
3023 IEM_MC_ARG(uint8_t, iEffSeg, 0);
3024 IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
3025 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
3026 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
3027 IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
3028 IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
3029 IEM_MC_CALL_CIMPL_2(iemCImpl_vstmxcsr, iEffSeg, GCPtrEff);
3030 IEM_MC_END();
3031 return VINF_SUCCESS;
3032}
3033
3034/* Opcode VEX.0F 0xae mem/4 - invalid. */
3035/* Opcode VEX.0F 0xae mem/5 - invalid. */
3036/* Opcode VEX.0F 0xae mem/6 - invalid. */
3037/* Opcode VEX.0F 0xae mem/7 - invalid. */
3038
3039/* Opcode VEX.0F 0xae 11b/0 - invalid. */
3040/* Opcode VEX.0F 0xae 11b/1 - invalid. */
3041/* Opcode VEX.0F 0xae 11b/2 - invalid. */
3042/* Opcode VEX.0F 0xae 11b/3 - invalid. */
3043/* Opcode VEX.0F 0xae 11b/4 - invalid. */
3044/* Opcode VEX.0F 0xae 11b/5 - invalid. */
3045/* Opcode VEX.0F 0xae 11b/6 - invalid. */
3046/* Opcode VEX.0F 0xae 11b/7 - invalid. */
3047
3048/**
3049 * Vex group 15 jump table for memory variant.
3050 */
3051IEM_STATIC const PFNIEMOPRM g_apfnVexGroup15MemReg[] =
3052{ /* pfx: none, 066h, 0f3h, 0f2h */
3053 /* /0 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3054 /* /1 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3055 /* /2 */ iemOp_VGrp15_vldmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3056 /* /3 */ iemOp_VGrp15_vstmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3057 /* /4 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3058 /* /5 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3059 /* /6 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3060 /* /7 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
3061};
3062AssertCompile(RT_ELEMENTS(g_apfnVexGroup15MemReg) == 8*4);
3063
3064
3065/** Opcode vex. 0xae. */
3066FNIEMOP_DEF(iemOp_VGrp15)
3067{
3068 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3069 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3070 /* register, register */
3071 return FNIEMOP_CALL_1(iemOp_InvalidWithRM, bRm);
3072
3073 /* memory, register */
3074 return FNIEMOP_CALL_1(g_apfnVexGroup15MemReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
3075 + pVCpu->iem.s.idxPrefix], bRm);
3076}
3077
3078
3079/* Opcode VEX.0F 0xaf - invalid. */
3080
3081/* Opcode VEX.0F 0xb0 - invalid. */
3082/* Opcode VEX.0F 0xb1 - invalid. */
3083/* Opcode VEX.0F 0xb2 - invalid. */
3084/* Opcode VEX.0F 0xb2 - invalid. */
3085/* Opcode VEX.0F 0xb3 - invalid. */
3086/* Opcode VEX.0F 0xb4 - invalid. */
3087/* Opcode VEX.0F 0xb5 - invalid. */
3088/* Opcode VEX.0F 0xb6 - invalid. */
3089/* Opcode VEX.0F 0xb7 - invalid. */
3090/* Opcode VEX.0F 0xb8 - invalid. */
3091/* Opcode VEX.0F 0xb9 - invalid. */
3092/* Opcode VEX.0F 0xba - invalid. */
3093/* Opcode VEX.0F 0xbb - invalid. */
3094/* Opcode VEX.0F 0xbc - invalid. */
3095/* Opcode VEX.0F 0xbd - invalid. */
3096/* Opcode VEX.0F 0xbe - invalid. */
3097/* Opcode VEX.0F 0xbf - invalid. */
3098
3099/* Opcode VEX.0F 0xc0 - invalid. */
3100/* Opcode VEX.66.0F 0xc0 - invalid. */
3101/* Opcode VEX.F3.0F 0xc0 - invalid. */
3102/* Opcode VEX.F2.0F 0xc0 - invalid. */
3103
3104/* Opcode VEX.0F 0xc1 - invalid. */
3105/* Opcode VEX.66.0F 0xc1 - invalid. */
3106/* Opcode VEX.F3.0F 0xc1 - invalid. */
3107/* Opcode VEX.F2.0F 0xc1 - invalid. */
3108
3109/** Opcode VEX.0F 0xc2 - vcmpps Vps,Hps,Wps,Ib */
3110FNIEMOP_STUB(iemOp_vcmpps_Vps_Hps_Wps_Ib);
3111/** Opcode VEX.66.0F 0xc2 - vcmppd Vpd,Hpd,Wpd,Ib */
3112FNIEMOP_STUB(iemOp_vcmppd_Vpd_Hpd_Wpd_Ib);
3113/** Opcode VEX.F3.0F 0xc2 - vcmpss Vss,Hss,Wss,Ib */
3114FNIEMOP_STUB(iemOp_vcmpss_Vss_Hss_Wss_Ib);
3115/** Opcode VEX.F2.0F 0xc2 - vcmpsd Vsd,Hsd,Wsd,Ib */
3116FNIEMOP_STUB(iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib);
3117
3118/* Opcode VEX.0F 0xc3 - invalid */
3119/* Opcode VEX.66.0F 0xc3 - invalid */
3120/* Opcode VEX.F3.0F 0xc3 - invalid */
3121/* Opcode VEX.F2.0F 0xc3 - invalid */
3122
3123/* Opcode VEX.0F 0xc4 - invalid */
3124/** Opcode VEX.66.0F 0xc4 - vpinsrw Vdq,Hdq,Ry/Mw,Ib */
3125FNIEMOP_STUB(iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib);
3126/* Opcode VEX.F3.0F 0xc4 - invalid */
3127/* Opcode VEX.F2.0F 0xc4 - invalid */
3128
3129/* Opcode VEX.0F 0xc5 - invlid */
3130/** Opcode VEX.66.0F 0xc5 - vpextrw Gd, Udq, Ib */
3131FNIEMOP_STUB(iemOp_vpextrw_Gd_Udq_Ib);
3132/* Opcode VEX.F3.0F 0xc5 - invalid */
3133/* Opcode VEX.F2.0F 0xc5 - invalid */
3134
3135/** Opcode VEX.0F 0xc6 - vshufps Vps,Hps,Wps,Ib */
3136FNIEMOP_STUB(iemOp_vshufps_Vps_Hps_Wps_Ib);
3137/** Opcode VEX.66.0F 0xc6 - vshufpd Vpd,Hpd,Wpd,Ib */
3138FNIEMOP_STUB(iemOp_vshufpd_Vpd_Hpd_Wpd_Ib);
3139/* Opcode VEX.F3.0F 0xc6 - invalid */
3140/* Opcode VEX.F2.0F 0xc6 - invalid */
3141
3142/* Opcode VEX.0F 0xc7 - invalid */
3143/* Opcode VEX.66.0F 0xc7 - invalid */
3144/* Opcode VEX.F3.0F 0xc7 - invalid */
3145/* Opcode VEX.F2.0F 0xc7 - invalid */
3146
3147/* Opcode VEX.0F 0xc8 - invalid */
3148/* Opcode VEX.0F 0xc9 - invalid */
3149/* Opcode VEX.0F 0xca - invalid */
3150/* Opcode VEX.0F 0xcb - invalid */
3151/* Opcode VEX.0F 0xcc - invalid */
3152/* Opcode VEX.0F 0xcd - invalid */
3153/* Opcode VEX.0F 0xce - invalid */
3154/* Opcode VEX.0F 0xcf - invalid */
3155
3156
3157/* Opcode VEX.0F 0xd0 - invalid */
3158/** Opcode VEX.66.0F 0xd0 - vaddsubpd Vpd, Hpd, Wpd */
3159FNIEMOP_STUB(iemOp_vaddsubpd_Vpd_Hpd_Wpd);
3160/* Opcode VEX.F3.0F 0xd0 - invalid */
3161/** Opcode VEX.F2.0F 0xd0 - vaddsubps Vps, Hps, Wps */
3162FNIEMOP_STUB(iemOp_vaddsubps_Vps_Hps_Wps);
3163
3164/* Opcode VEX.0F 0xd1 - invalid */
3165/** Opcode VEX.66.0F 0xd1 - vpsrlw Vx, Hx, W */
3166FNIEMOP_STUB(iemOp_vpsrlw_Vx_Hx_W);
3167/* Opcode VEX.F3.0F 0xd1 - invalid */
3168/* Opcode VEX.F2.0F 0xd1 - invalid */
3169
3170/* Opcode VEX.0F 0xd2 - invalid */
3171/** Opcode VEX.66.0F 0xd2 - vpsrld Vx, Hx, Wx */
3172FNIEMOP_STUB(iemOp_vpsrld_Vx_Hx_Wx);
3173/* Opcode VEX.F3.0F 0xd2 - invalid */
3174/* Opcode VEX.F2.0F 0xd2 - invalid */
3175
3176/* Opcode VEX.0F 0xd3 - invalid */
3177/** Opcode VEX.66.0F 0xd3 - vpsrlq Vx, Hx, Wx */
3178FNIEMOP_STUB(iemOp_vpsrlq_Vx_Hx_Wx);
3179/* Opcode VEX.F3.0F 0xd3 - invalid */
3180/* Opcode VEX.F2.0F 0xd3 - invalid */
3181
3182/* Opcode VEX.0F 0xd4 - invalid */
3183/** Opcode VEX.66.0F 0xd4 - vpaddq Vx, Hx, W */
3184FNIEMOP_STUB(iemOp_vpaddq_Vx_Hx_W);
3185/* Opcode VEX.F3.0F 0xd4 - invalid */
3186/* Opcode VEX.F2.0F 0xd4 - invalid */
3187
3188/* Opcode VEX.0F 0xd5 - invalid */
3189/** Opcode VEX.66.0F 0xd5 - vpmullw Vx, Hx, Wx */
3190FNIEMOP_STUB(iemOp_vpmullw_Vx_Hx_Wx);
3191/* Opcode VEX.F3.0F 0xd5 - invalid */
3192/* Opcode VEX.F2.0F 0xd5 - invalid */
3193
3194/* Opcode VEX.0F 0xd6 - invalid */
3195
3196/**
3197 * @ opcode 0xd6
3198 * @ oppfx 0x66
3199 * @ opcpuid sse2
3200 * @ opgroup og_sse2_pcksclr_datamove
3201 * @ opxcpttype none
3202 * @ optest op1=-1 op2=2 -> op1=2
3203 * @ optest op1=0 op2=-42 -> op1=-42
3204 */
3205FNIEMOP_STUB(iemOp_vmovq_Wq_Vq);
3206//FNIEMOP_DEF(iemOp_vmovq_Wq_Vq)
3207//{
3208// IEMOP_MNEMONIC2(MR, VMOVQ, vmovq, WqZxReg, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
3209// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3210// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3211// {
3212// /*
3213// * Register, register.
3214// */
3215// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3216// IEM_MC_BEGIN(0, 2);
3217// IEM_MC_LOCAL(uint64_t, uSrc);
3218//
3219// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3220// IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3221//
3222// IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
3223// IEM_MC_STORE_XREG_U64_ZX_U128((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, uSrc);
3224//
3225// IEM_MC_ADVANCE_RIP();
3226// IEM_MC_END();
3227// }
3228// else
3229// {
3230// /*
3231// * Memory, register.
3232// */
3233// IEM_MC_BEGIN(0, 2);
3234// IEM_MC_LOCAL(uint64_t, uSrc);
3235// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3236//
3237// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3238// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3239// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3240// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
3241//
3242// IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
3243// IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
3244//
3245// IEM_MC_ADVANCE_RIP();
3246// IEM_MC_END();
3247// }
3248// return VINF_SUCCESS;
3249//}
3250
3251/* Opcode VEX.F3.0F 0xd6 - invalid */
3252/* Opcode VEX.F2.0F 0xd6 - invalid */
3253
3254
3255/* Opcode VEX.0F 0xd7 - invalid */
3256
3257/** Opcode VEX.66.0F 0xd7 - */
3258FNIEMOP_STUB(iemOp_vpmovmskb_Gd_Ux);
3259//FNIEMOP_DEF(iemOp_vpmovmskb_Gd_Ux)
3260//{
3261// /* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
3262// /** @todo testcase: Check that the instruction implicitly clears the high
3263// * bits in 64-bit mode. The REX.W is first necessary when VLMAX > 256
3264// * and opcode modifications are made to work with the whole width (not
3265// * just 128). */
3266// IEMOP_MNEMONIC(vpmovmskb_Gd_Nq, "vpmovmskb Gd, Ux");
3267// /* Docs says register only. */
3268// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3269// if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) /** @todo test that this is registers only. */
3270// {
3271// IEMOP_HLP_DECODED_NL_2(OP_PMOVMSKB, IEMOPFORM_RM_REG, OP_PARM_Gd, OP_PARM_Vdq, DISOPTYPE_SSE | DISOPTYPE_HARMLESS);
3272// IEM_MC_BEGIN(2, 0);
3273// IEM_MC_ARG(uint64_t *, pDst, 0);
3274// IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
3275// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3276// IEM_MC_PREPARE_SSE_USAGE();
3277// IEM_MC_REF_GREG_U64(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
3278// IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
3279// IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_pmovmskb_u128, pDst, pSrc);
3280// IEM_MC_ADVANCE_RIP();
3281// IEM_MC_END();
3282// return VINF_SUCCESS;
3283// }
3284// return IEMOP_RAISE_INVALID_OPCODE();
3285//}
3286
3287/* Opcode VEX.F3.0F 0xd7 - invalid */
3288/* Opcode VEX.F2.0F 0xd7 - invalid */
3289
3290
3291/* Opcode VEX.0F 0xd8 - invalid */
3292/** Opcode VEX.66.0F 0xd8 - vpsubusb Vx, Hx, W */
3293FNIEMOP_STUB(iemOp_vpsubusb_Vx_Hx_W);
3294/* Opcode VEX.F3.0F 0xd8 - invalid */
3295/* Opcode VEX.F2.0F 0xd8 - invalid */
3296
3297/* Opcode VEX.0F 0xd9 - invalid */
3298/** Opcode VEX.66.0F 0xd9 - vpsubusw Vx, Hx, Wx */
3299FNIEMOP_STUB(iemOp_vpsubusw_Vx_Hx_Wx);
3300/* Opcode VEX.F3.0F 0xd9 - invalid */
3301/* Opcode VEX.F2.0F 0xd9 - invalid */
3302
3303/* Opcode VEX.0F 0xda - invalid */
3304/** Opcode VEX.66.0F 0xda - vpminub Vx, Hx, Wx */
3305FNIEMOP_STUB(iemOp_vpminub_Vx_Hx_Wx);
3306/* Opcode VEX.F3.0F 0xda - invalid */
3307/* Opcode VEX.F2.0F 0xda - invalid */
3308
3309/* Opcode VEX.0F 0xdb - invalid */
3310/** Opcode VEX.66.0F 0xdb - vpand Vx, Hx, W */
3311FNIEMOP_STUB(iemOp_vpand_Vx_Hx_W);
3312/* Opcode VEX.F3.0F 0xdb - invalid */
3313/* Opcode VEX.F2.0F 0xdb - invalid */
3314
3315/* Opcode VEX.0F 0xdc - invalid */
3316/** Opcode VEX.66.0F 0xdc - vpaddusb Vx, Hx, Wx */
3317FNIEMOP_STUB(iemOp_vpaddusb_Vx_Hx_Wx);
3318/* Opcode VEX.F3.0F 0xdc - invalid */
3319/* Opcode VEX.F2.0F 0xdc - invalid */
3320
3321/* Opcode VEX.0F 0xdd - invalid */
3322/** Opcode VEX.66.0F 0xdd - vpaddusw Vx, Hx, Wx */
3323FNIEMOP_STUB(iemOp_vpaddusw_Vx_Hx_Wx);
3324/* Opcode VEX.F3.0F 0xdd - invalid */
3325/* Opcode VEX.F2.0F 0xdd - invalid */
3326
3327/* Opcode VEX.0F 0xde - invalid */
3328/** Opcode VEX.66.0F 0xde - vpmaxub Vx, Hx, W */
3329FNIEMOP_STUB(iemOp_vpmaxub_Vx_Hx_W);
3330/* Opcode VEX.F3.0F 0xde - invalid */
3331/* Opcode VEX.F2.0F 0xde - invalid */
3332
3333/* Opcode VEX.0F 0xdf - invalid */
3334/** Opcode VEX.66.0F 0xdf - vpandn Vx, Hx, Wx */
3335FNIEMOP_STUB(iemOp_vpandn_Vx_Hx_Wx);
3336/* Opcode VEX.F3.0F 0xdf - invalid */
3337/* Opcode VEX.F2.0F 0xdf - invalid */
3338
3339/* Opcode VEX.0F 0xe0 - invalid */
3340/** Opcode VEX.66.0F 0xe0 - vpavgb Vx, Hx, Wx */
3341FNIEMOP_STUB(iemOp_vpavgb_Vx_Hx_Wx);
3342/* Opcode VEX.F3.0F 0xe0 - invalid */
3343/* Opcode VEX.F2.0F 0xe0 - invalid */
3344
3345/* Opcode VEX.0F 0xe1 - invalid */
3346/** Opcode VEX.66.0F 0xe1 - vpsraw Vx, Hx, W */
3347FNIEMOP_STUB(iemOp_vpsraw_Vx_Hx_W);
3348/* Opcode VEX.F3.0F 0xe1 - invalid */
3349/* Opcode VEX.F2.0F 0xe1 - invalid */
3350
3351/* Opcode VEX.0F 0xe2 - invalid */
3352/** Opcode VEX.66.0F 0xe2 - vpsrad Vx, Hx, Wx */
3353FNIEMOP_STUB(iemOp_vpsrad_Vx_Hx_Wx);
3354/* Opcode VEX.F3.0F 0xe2 - invalid */
3355/* Opcode VEX.F2.0F 0xe2 - invalid */
3356
3357/* Opcode VEX.0F 0xe3 - invalid */
3358/** Opcode VEX.66.0F 0xe3 - vpavgw Vx, Hx, Wx */
3359FNIEMOP_STUB(iemOp_vpavgw_Vx_Hx_Wx);
3360/* Opcode VEX.F3.0F 0xe3 - invalid */
3361/* Opcode VEX.F2.0F 0xe3 - invalid */
3362
3363/* Opcode VEX.0F 0xe4 - invalid */
3364/** Opcode VEX.66.0F 0xe4 - vpmulhuw Vx, Hx, W */
3365FNIEMOP_STUB(iemOp_vpmulhuw_Vx_Hx_W);
3366/* Opcode VEX.F3.0F 0xe4 - invalid */
3367/* Opcode VEX.F2.0F 0xe4 - invalid */
3368
3369/* Opcode VEX.0F 0xe5 - invalid */
3370/** Opcode VEX.66.0F 0xe5 - vpmulhw Vx, Hx, Wx */
3371FNIEMOP_STUB(iemOp_vpmulhw_Vx_Hx_Wx);
3372/* Opcode VEX.F3.0F 0xe5 - invalid */
3373/* Opcode VEX.F2.0F 0xe5 - invalid */
3374
3375/* Opcode VEX.0F 0xe6 - invalid */
3376/** Opcode VEX.66.0F 0xe6 - vcvttpd2dq Vx, Wpd */
3377FNIEMOP_STUB(iemOp_vcvttpd2dq_Vx_Wpd);
3378/** Opcode VEX.F3.0F 0xe6 - vcvtdq2pd Vx, Wpd */
3379FNIEMOP_STUB(iemOp_vcvtdq2pd_Vx_Wpd);
3380/** Opcode VEX.F2.0F 0xe6 - vcvtpd2dq Vx, Wpd */
3381FNIEMOP_STUB(iemOp_vcvtpd2dq_Vx_Wpd);
3382
3383
3384/* Opcode VEX.0F 0xe7 - invalid */
3385
3386/** Opcode VEX.66.0F 0xe7 - vmovntdq Mx, Vx */
3387FNIEMOP_STUB(iemOp_vmovntdq_Mx_Vx);
3388//FNIEMOP_DEF(iemOp_vmovntdq_Mx_Vx)
3389//{
3390// uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3391// if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
3392// {
3393// /* Register, memory. */
3394// IEMOP_MNEMONIC(vmovntdq_Mx_Vx, "vmovntdq Mx,Vx");
3395// IEM_MC_BEGIN(0, 2);
3396// IEM_MC_LOCAL(RTUINT128U, uSrc);
3397// IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3398//
3399// IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3400// IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3401// IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3402// IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
3403//
3404// IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg);
3405// IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
3406//
3407// IEM_MC_ADVANCE_RIP();
3408// IEM_MC_END();
3409// return VINF_SUCCESS;
3410// }
3411//
3412// /* The register, register encoding is invalid. */
3413// return IEMOP_RAISE_INVALID_OPCODE();
3414//}
3415
3416/* Opcode VEX.F3.0F 0xe7 - invalid */
3417/* Opcode VEX.F2.0F 0xe7 - invalid */
3418
3419
3420/* Opcode VEX.0F 0xe8 - invalid */
3421/** Opcode VEX.66.0F 0xe8 - vpsubsb Vx, Hx, W */
3422FNIEMOP_STUB(iemOp_vpsubsb_Vx_Hx_W);
3423/* Opcode VEX.F3.0F 0xe8 - invalid */
3424/* Opcode VEX.F2.0F 0xe8 - invalid */
3425
3426/* Opcode VEX.0F 0xe9 - invalid */
3427/** Opcode VEX.66.0F 0xe9 - vpsubsw Vx, Hx, Wx */
3428FNIEMOP_STUB(iemOp_vpsubsw_Vx_Hx_Wx);
3429/* Opcode VEX.F3.0F 0xe9 - invalid */
3430/* Opcode VEX.F2.0F 0xe9 - invalid */
3431
3432/* Opcode VEX.0F 0xea - invalid */
3433/** Opcode VEX.66.0F 0xea - vpminsw Vx, Hx, Wx */
3434FNIEMOP_STUB(iemOp_vpminsw_Vx_Hx_Wx);
3435/* Opcode VEX.F3.0F 0xea - invalid */
3436/* Opcode VEX.F2.0F 0xea - invalid */
3437
3438/* Opcode VEX.0F 0xeb - invalid */
3439/** Opcode VEX.66.0F 0xeb - vpor Vx, Hx, W */
3440FNIEMOP_STUB(iemOp_vpor_Vx_Hx_W);
3441/* Opcode VEX.F3.0F 0xeb - invalid */
3442/* Opcode VEX.F2.0F 0xeb - invalid */
3443
3444/* Opcode VEX.0F 0xec - invalid */
3445/** Opcode VEX.66.0F 0xec - vpaddsb Vx, Hx, Wx */
3446FNIEMOP_STUB(iemOp_vpaddsb_Vx_Hx_Wx);
3447/* Opcode VEX.F3.0F 0xec - invalid */
3448/* Opcode VEX.F2.0F 0xec - invalid */
3449
3450/* Opcode VEX.0F 0xed - invalid */
3451/** Opcode VEX.66.0F 0xed - vpaddsw Vx, Hx, Wx */
3452FNIEMOP_STUB(iemOp_vpaddsw_Vx_Hx_Wx);
3453/* Opcode VEX.F3.0F 0xed - invalid */
3454/* Opcode VEX.F2.0F 0xed - invalid */
3455
3456/* Opcode VEX.0F 0xee - invalid */
3457/** Opcode VEX.66.0F 0xee - vpmaxsw Vx, Hx, W */
3458FNIEMOP_STUB(iemOp_vpmaxsw_Vx_Hx_W);
3459/* Opcode VEX.F3.0F 0xee - invalid */
3460/* Opcode VEX.F2.0F 0xee - invalid */
3461
3462
3463/* Opcode VEX.0F 0xef - invalid */
3464
3465/** Opcode VEX.66.0F 0xef - vpxor Vx, Hx, Wx */
3466FNIEMOP_DEF(iemOp_vpxor_Vx_Hx_Wx)
3467{
3468 IEMOP_MNEMONIC(vpxor, "vpxor");
3469 return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pxor);
3470}
3471
3472/* Opcode VEX.F3.0F 0xef - invalid */
3473/* Opcode VEX.F2.0F 0xef - invalid */
3474
3475/* Opcode VEX.0F 0xf0 - invalid */
3476/* Opcode VEX.66.0F 0xf0 - invalid */
3477/** Opcode VEX.F2.0F 0xf0 - vlddqu Vx, Mx */
3478FNIEMOP_STUB(iemOp_vlddqu_Vx_Mx);
3479
3480/* Opcode VEX.0F 0xf1 - invalid */
3481/** Opcode VEX.66.0F 0xf1 - vpsllw Vx, Hx, W */
3482FNIEMOP_STUB(iemOp_vpsllw_Vx_Hx_W);
3483/* Opcode VEX.F2.0F 0xf1 - invalid */
3484
3485/* Opcode VEX.0F 0xf2 - invalid */
3486/** Opcode VEX.66.0F 0xf2 - vpslld Vx, Hx, Wx */
3487FNIEMOP_STUB(iemOp_vpslld_Vx_Hx_Wx);
3488/* Opcode VEX.F2.0F 0xf2 - invalid */
3489
3490/* Opcode VEX.0F 0xf3 - invalid */
3491/** Opcode VEX.66.0F 0xf3 - vpsllq Vx, Hx, Wx */
3492FNIEMOP_STUB(iemOp_vpsllq_Vx_Hx_Wx);
3493/* Opcode VEX.F2.0F 0xf3 - invalid */
3494
3495/* Opcode VEX.0F 0xf4 - invalid */
3496/** Opcode VEX.66.0F 0xf4 - vpmuludq Vx, Hx, W */
3497FNIEMOP_STUB(iemOp_vpmuludq_Vx_Hx_W);
3498/* Opcode VEX.F2.0F 0xf4 - invalid */
3499
3500/* Opcode VEX.0F 0xf5 - invalid */
3501/** Opcode VEX.66.0F 0xf5 - vpmaddwd Vx, Hx, Wx */
3502FNIEMOP_STUB(iemOp_vpmaddwd_Vx_Hx_Wx);
3503/* Opcode VEX.F2.0F 0xf5 - invalid */
3504
3505/* Opcode VEX.0F 0xf6 - invalid */
3506/** Opcode VEX.66.0F 0xf6 - vpsadbw Vx, Hx, Wx */
3507FNIEMOP_STUB(iemOp_vpsadbw_Vx_Hx_Wx);
3508/* Opcode VEX.F2.0F 0xf6 - invalid */
3509
3510/* Opcode VEX.0F 0xf7 - invalid */
3511/** Opcode VEX.66.0F 0xf7 - vmaskmovdqu Vdq, Udq */
3512FNIEMOP_STUB(iemOp_vmaskmovdqu_Vdq_Udq);
3513/* Opcode VEX.F2.0F 0xf7 - invalid */
3514
3515/* Opcode VEX.0F 0xf8 - invalid */
3516/** Opcode VEX.66.0F 0xf8 - vpsubb Vx, Hx, W */
3517FNIEMOP_STUB(iemOp_vpsubb_Vx_Hx_W);
3518/* Opcode VEX.F2.0F 0xf8 - invalid */
3519
3520/* Opcode VEX.0F 0xf9 - invalid */
3521/** Opcode VEX.66.0F 0xf9 - vpsubw Vx, Hx, Wx */
3522FNIEMOP_STUB(iemOp_vpsubw_Vx_Hx_Wx);
3523/* Opcode VEX.F2.0F 0xf9 - invalid */
3524
3525/* Opcode VEX.0F 0xfa - invalid */
3526/** Opcode VEX.66.0F 0xfa - vpsubd Vx, Hx, Wx */
3527FNIEMOP_STUB(iemOp_vpsubd_Vx_Hx_Wx);
3528/* Opcode VEX.F2.0F 0xfa - invalid */
3529
3530/* Opcode VEX.0F 0xfb - invalid */
3531/** Opcode VEX.66.0F 0xfb - vpsubq Vx, Hx, W */
3532FNIEMOP_STUB(iemOp_vpsubq_Vx_Hx_W);
3533/* Opcode VEX.F2.0F 0xfb - invalid */
3534
3535/* Opcode VEX.0F 0xfc - invalid */
3536/** Opcode VEX.66.0F 0xfc - vpaddb Vx, Hx, Wx */
3537FNIEMOP_STUB(iemOp_vpaddb_Vx_Hx_Wx);
3538/* Opcode VEX.F2.0F 0xfc - invalid */
3539
3540/* Opcode VEX.0F 0xfd - invalid */
3541/** Opcode VEX.66.0F 0xfd - vpaddw Vx, Hx, Wx */
3542FNIEMOP_STUB(iemOp_vpaddw_Vx_Hx_Wx);
3543/* Opcode VEX.F2.0F 0xfd - invalid */
3544
3545/* Opcode VEX.0F 0xfe - invalid */
3546/** Opcode VEX.66.0F 0xfe - vpaddd Vx, Hx, W */
3547FNIEMOP_STUB(iemOp_vpaddd_Vx_Hx_W);
3548/* Opcode VEX.F2.0F 0xfe - invalid */
3549
3550
3551/** Opcode **** 0x0f 0xff - UD0 */
3552FNIEMOP_DEF(iemOp_vud0)
3553{
3554 IEMOP_MNEMONIC(vud0, "vud0");
3555 if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3556 {
3557 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
3558#ifndef TST_IEM_CHECK_MC
3559 RTGCPTR GCPtrEff;
3560 VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
3561 if (rcStrict != VINF_SUCCESS)
3562 return rcStrict;
3563#endif
3564 IEMOP_HLP_DONE_DECODING();
3565 }
3566 return IEMOP_RAISE_INVALID_OPCODE();
3567}
3568
3569
3570
3571/**
3572 * VEX opcode map \#1.
3573 *
3574 * @sa g_apfnTwoByteMap
3575 */
3576IEM_STATIC const PFNIEMOP g_apfnVexMap1[] =
3577{
3578 /* no prefix, 066h prefix f3h prefix, f2h prefix */
3579 /* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRM),
3580 /* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRM),
3581 /* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRM),
3582 /* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRM),
3583 /* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRM),
3584 /* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRM),
3585 /* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRM),
3586 /* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRM),
3587 /* 0x08 */ IEMOP_X4(iemOp_InvalidNeedRM),
3588 /* 0x09 */ IEMOP_X4(iemOp_InvalidNeedRM),
3589 /* 0x0a */ IEMOP_X4(iemOp_InvalidNeedRM),
3590 /* 0x0b */ IEMOP_X4(iemOp_vud2), /* ?? */
3591 /* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
3592 /* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
3593 /* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
3594 /* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
3595
3596 /* 0x10 */ iemOp_vmovups_Vps_Wps, iemOp_vmovupd_Vpd_Wpd, iemOp_vmovss_Vss_Hss_Wss, iemOp_vmovsd_Vsd_Hsd_Wsd,
3597 /* 0x11 */ iemOp_vmovups_Wps_Vps, iemOp_vmovupd_Wpd_Vpd, iemOp_vmovss_Wss_Hss_Vss, iemOp_vmovsd_Wsd_Hsd_Vsd,
3598 /* 0x12 */ iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx, iemOp_vmovddup_Vx_Wx,
3599 /* 0x13 */ iemOp_vmovlps_Mq_Vq, iemOp_vmovlpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3600 /* 0x14 */ iemOp_vunpcklps_Vx_Hx_Wx, iemOp_vunpcklpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3601 /* 0x15 */ iemOp_vunpckhps_Vx_Hx_Wx, iemOp_vunpckhpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3602 /* 0x16 */ iemOp_vmovhpsv1_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq, iemOp_vmovhpdv1_Vdq_Hq_Mq, iemOp_vmovshdup_Vx_Wx, iemOp_InvalidNeedRM,
3603 /* 0x17 */ iemOp_vmovhpsv1_Mq_Vq, iemOp_vmovhpdv1_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3604 /* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
3605 /* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
3606 /* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
3607 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
3608 /* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRM),
3609 /* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRM),
3610 /* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRM),
3611 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
3612
3613 /* 0x20 */ IEMOP_X4(iemOp_InvalidNeedRM),
3614 /* 0x21 */ IEMOP_X4(iemOp_InvalidNeedRM),
3615 /* 0x22 */ IEMOP_X4(iemOp_InvalidNeedRM),
3616 /* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRM),
3617 /* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRM),
3618 /* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRM),
3619 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
3620 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
3621 /* 0x28 */ iemOp_vmovaps_Vps_Wps, iemOp_vmovapd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3622 /* 0x29 */ iemOp_vmovaps_Wps_Vps, iemOp_vmovapd_Wpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3623 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtsi2ss_Vss_Hss_Ey, iemOp_vcvtsi2sd_Vsd_Hsd_Ey,
3624 /* 0x2b */ iemOp_vmovntps_Mps_Vps, iemOp_vmovntpd_Mpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3625 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvttss2si_Gy_Wss, iemOp_vcvttsd2si_Gy_Wsd,
3626 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtss2si_Gy_Wss, iemOp_vcvtsd2si_Gy_Wsd,
3627 /* 0x2e */ iemOp_vucomiss_Vss_Wss, iemOp_vucomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3628 /* 0x2f */ iemOp_vcomiss_Vss_Wss, iemOp_vcomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3629
3630 /* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRM),
3631 /* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRM),
3632 /* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRM),
3633 /* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRM),
3634 /* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRM),
3635 /* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRM),
3636 /* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
3637 /* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRM),
3638 /* 0x38 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3639 /* 0x39 */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3640 /* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3641 /* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3642 /* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3643 /* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3644 /* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3645 /* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRM), /** @todo check that there is no escape table stuff here */
3646
3647 /* 0x40 */ IEMOP_X4(iemOp_InvalidNeedRM),
3648 /* 0x41 */ IEMOP_X4(iemOp_InvalidNeedRM),
3649 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
3650 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
3651 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
3652 /* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
3653 /* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
3654 /* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
3655 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
3656 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
3657 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
3658 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
3659 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
3660 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
3661 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
3662 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
3663
3664 /* 0x50 */ iemOp_vmovmskps_Gy_Ups, iemOp_vmovmskpd_Gy_Upd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3665 /* 0x51 */ iemOp_vsqrtps_Vps_Wps, iemOp_vsqrtpd_Vpd_Wpd, iemOp_vsqrtss_Vss_Hss_Wss, iemOp_vsqrtsd_Vsd_Hsd_Wsd,
3666 /* 0x52 */ iemOp_vrsqrtps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrsqrtss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
3667 /* 0x53 */ iemOp_vrcpps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrcpss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
3668 /* 0x54 */ iemOp_vandps_Vps_Hps_Wps, iemOp_vandpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3669 /* 0x55 */ iemOp_vandnps_Vps_Hps_Wps, iemOp_vandnpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3670 /* 0x56 */ iemOp_vorps_Vps_Hps_Wps, iemOp_vorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3671 /* 0x57 */ iemOp_vxorps_Vps_Hps_Wps, iemOp_vxorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3672 /* 0x58 */ iemOp_vaddps_Vps_Hps_Wps, iemOp_vaddpd_Vpd_Hpd_Wpd, iemOp_vaddss_Vss_Hss_Wss, iemOp_vaddsd_Vsd_Hsd_Wsd,
3673 /* 0x59 */ iemOp_vmulps_Vps_Hps_Wps, iemOp_vmulpd_Vpd_Hpd_Wpd, iemOp_vmulss_Vss_Hss_Wss, iemOp_vmulsd_Vsd_Hsd_Wsd,
3674 /* 0x5a */ iemOp_vcvtps2pd_Vpd_Wps, iemOp_vcvtpd2ps_Vps_Wpd, iemOp_vcvtss2sd_Vsd_Hx_Wss, iemOp_vcvtsd2ss_Vss_Hx_Wsd,
3675 /* 0x5b */ iemOp_vcvtdq2ps_Vps_Wdq, iemOp_vcvtps2dq_Vdq_Wps, iemOp_vcvttps2dq_Vdq_Wps, iemOp_InvalidNeedRM,
3676 /* 0x5c */ iemOp_vsubps_Vps_Hps_Wps, iemOp_vsubpd_Vpd_Hpd_Wpd, iemOp_vsubss_Vss_Hss_Wss, iemOp_vsubsd_Vsd_Hsd_Wsd,
3677 /* 0x5d */ iemOp_vminps_Vps_Hps_Wps, iemOp_vminpd_Vpd_Hpd_Wpd, iemOp_vminss_Vss_Hss_Wss, iemOp_vminsd_Vsd_Hsd_Wsd,
3678 /* 0x5e */ iemOp_vdivps_Vps_Hps_Wps, iemOp_vdivpd_Vpd_Hpd_Wpd, iemOp_vdivss_Vss_Hss_Wss, iemOp_vdivsd_Vsd_Hsd_Wsd,
3679 /* 0x5f */ iemOp_vmaxps_Vps_Hps_Wps, iemOp_vmaxpd_Vpd_Hpd_Wpd, iemOp_vmaxss_Vss_Hss_Wss, iemOp_vmaxsd_Vsd_Hsd_Wsd,
3680
3681 /* 0x60 */ iemOp_InvalidNeedRM, iemOp_vpunpcklbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3682 /* 0x61 */ iemOp_InvalidNeedRM, iemOp_vpunpcklwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3683 /* 0x62 */ iemOp_InvalidNeedRM, iemOp_vpunpckldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3684 /* 0x63 */ iemOp_InvalidNeedRM, iemOp_vpacksswb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3685 /* 0x64 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3686 /* 0x65 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3687 /* 0x66 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3688 /* 0x67 */ iemOp_InvalidNeedRM, iemOp_vpackuswb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3689 /* 0x68 */ iemOp_InvalidNeedRM, iemOp_vpunpckhbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3690 /* 0x69 */ iemOp_InvalidNeedRM, iemOp_vpunpckhwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3691 /* 0x6a */ iemOp_InvalidNeedRM, iemOp_vpunpckhdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3692 /* 0x6b */ iemOp_InvalidNeedRM, iemOp_vpackssdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3693 /* 0x6c */ iemOp_InvalidNeedRM, iemOp_vpunpcklqdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3694 /* 0x6d */ iemOp_InvalidNeedRM, iemOp_vpunpckhqdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3695 /* 0x6e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Vy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3696 /* 0x6f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Vx_Wx, iemOp_vmovdqu_Vx_Wx, iemOp_InvalidNeedRM,
3697
3698 /* 0x70 */ iemOp_InvalidNeedRM, iemOp_vpshufd_Vx_Wx_Ib, iemOp_vpshufhw_Vx_Wx_Ib, iemOp_vpshuflw_Vx_Wx_Ib,
3699 /* 0x71 */ iemOp_InvalidNeedRM, iemOp_VGrp12, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3700 /* 0x72 */ iemOp_InvalidNeedRM, iemOp_VGrp13, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3701 /* 0x73 */ iemOp_InvalidNeedRM, iemOp_VGrp14, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3702 /* 0x74 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3703 /* 0x75 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3704 /* 0x76 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3705 /* 0x77 */ iemOp_vzeroupperv__vzeroallv, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3706 /* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
3707 /* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
3708 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
3709 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
3710 /* 0x7c */ iemOp_InvalidNeedRM, iemOp_vhaddpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhaddps_Vps_Hps_Wps,
3711 /* 0x7d */ iemOp_InvalidNeedRM, iemOp_vhsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhsubps_Vps_Hps_Wps,
3712 /* 0x7e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Ey_Vy, iemOp_vmovq_Vq_Wq, iemOp_InvalidNeedRM,
3713 /* 0x7f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Wx_Vx, iemOp_vmovdqu_Wx_Vx, iemOp_InvalidNeedRM,
3714
3715 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
3716 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
3717 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
3718 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
3719 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
3720 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
3721 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
3722 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
3723 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
3724 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
3725 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
3726 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
3727 /* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
3728 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
3729 /* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
3730 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
3731
3732 /* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
3733 /* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
3734 /* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
3735 /* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
3736 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
3737 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
3738 /* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
3739 /* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
3740 /* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
3741 /* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
3742 /* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
3743 /* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
3744 /* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
3745 /* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
3746 /* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
3747 /* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
3748
3749 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3750 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3751 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
3752 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3753 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
3754 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
3755 /* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
3756 /* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
3757 /* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
3758 /* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
3759 /* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
3760 /* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
3761 /* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
3762 /* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
3763 /* 0xae */ IEMOP_X4(iemOp_VGrp15),
3764 /* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
3765
3766 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3767 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3768 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
3769 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3770 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
3771 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
3772 /* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
3773 /* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
3774 /* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
3775 /* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
3776 /* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
3777 /* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
3778 /* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
3779 /* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
3780 /* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
3781 /* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
3782
3783 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
3784 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
3785 /* 0xc2 */ iemOp_vcmpps_Vps_Hps_Wps_Ib, iemOp_vcmppd_Vpd_Hpd_Wpd_Ib, iemOp_vcmpss_Vss_Hss_Wss_Ib, iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib,
3786 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
3787 /* 0xc4 */ iemOp_InvalidNeedRM, iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
3788 /* 0xc5 */ iemOp_InvalidNeedRM, iemOp_vpextrw_Gd_Udq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
3789 /* 0xc6 */ iemOp_vshufps_Vps_Hps_Wps_Ib, iemOp_vshufpd_Vpd_Hpd_Wpd_Ib, iemOp_InvalidNeedRMImm8,iemOp_InvalidNeedRMImm8,
3790 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
3791 /* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
3792 /* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
3793 /* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
3794 /* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
3795 /* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
3796 /* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
3797 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
3798 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
3799
3800 /* 0xd0 */ iemOp_InvalidNeedRM, iemOp_vaddsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vaddsubps_Vps_Hps_Wps,
3801 /* 0xd1 */ iemOp_InvalidNeedRM, iemOp_vpsrlw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3802 /* 0xd2 */ iemOp_InvalidNeedRM, iemOp_vpsrld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3803 /* 0xd3 */ iemOp_InvalidNeedRM, iemOp_vpsrlq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3804 /* 0xd4 */ iemOp_InvalidNeedRM, iemOp_vpaddq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3805 /* 0xd5 */ iemOp_InvalidNeedRM, iemOp_vpmullw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3806 /* 0xd6 */ iemOp_InvalidNeedRM, iemOp_vmovq_Wq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3807 /* 0xd7 */ iemOp_InvalidNeedRM, iemOp_vpmovmskb_Gd_Ux, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3808 /* 0xd8 */ iemOp_InvalidNeedRM, iemOp_vpsubusb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3809 /* 0xd9 */ iemOp_InvalidNeedRM, iemOp_vpsubusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3810 /* 0xda */ iemOp_InvalidNeedRM, iemOp_vpminub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3811 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vpand_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3812 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vpaddusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3813 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vpaddusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3814 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vpmaxub_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3815 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vpandn_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3816
3817 /* 0xe0 */ iemOp_InvalidNeedRM, iemOp_vpavgb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3818 /* 0xe1 */ iemOp_InvalidNeedRM, iemOp_vpsraw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3819 /* 0xe2 */ iemOp_InvalidNeedRM, iemOp_vpsrad_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3820 /* 0xe3 */ iemOp_InvalidNeedRM, iemOp_vpavgw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3821 /* 0xe4 */ iemOp_InvalidNeedRM, iemOp_vpmulhuw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3822 /* 0xe5 */ iemOp_InvalidNeedRM, iemOp_vpmulhw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3823 /* 0xe6 */ iemOp_InvalidNeedRM, iemOp_vcvttpd2dq_Vx_Wpd, iemOp_vcvtdq2pd_Vx_Wpd, iemOp_vcvtpd2dq_Vx_Wpd,
3824 /* 0xe7 */ iemOp_InvalidNeedRM, iemOp_vmovntdq_Mx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3825 /* 0xe8 */ iemOp_InvalidNeedRM, iemOp_vpsubsb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3826 /* 0xe9 */ iemOp_InvalidNeedRM, iemOp_vpsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3827 /* 0xea */ iemOp_InvalidNeedRM, iemOp_vpminsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3828 /* 0xeb */ iemOp_InvalidNeedRM, iemOp_vpor_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3829 /* 0xec */ iemOp_InvalidNeedRM, iemOp_vpaddsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3830 /* 0xed */ iemOp_InvalidNeedRM, iemOp_vpaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3831 /* 0xee */ iemOp_InvalidNeedRM, iemOp_vpmaxsw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3832 /* 0xef */ iemOp_InvalidNeedRM, iemOp_vpxor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3833
3834 /* 0xf0 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vlddqu_Vx_Mx,
3835 /* 0xf1 */ iemOp_InvalidNeedRM, iemOp_vpsllw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3836 /* 0xf2 */ iemOp_InvalidNeedRM, iemOp_vpslld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3837 /* 0xf3 */ iemOp_InvalidNeedRM, iemOp_vpsllq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3838 /* 0xf4 */ iemOp_InvalidNeedRM, iemOp_vpmuludq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3839 /* 0xf5 */ iemOp_InvalidNeedRM, iemOp_vpmaddwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3840 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_vpsadbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3841 /* 0xf7 */ iemOp_InvalidNeedRM, iemOp_vmaskmovdqu_Vdq_Udq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3842 /* 0xf8 */ iemOp_InvalidNeedRM, iemOp_vpsubb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3843 /* 0xf9 */ iemOp_InvalidNeedRM, iemOp_vpsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3844 /* 0xfa */ iemOp_InvalidNeedRM, iemOp_vpsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3845 /* 0xfb */ iemOp_InvalidNeedRM, iemOp_vpsubq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3846 /* 0xfc */ iemOp_InvalidNeedRM, iemOp_vpaddb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3847 /* 0xfd */ iemOp_InvalidNeedRM, iemOp_vpaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3848 /* 0xfe */ iemOp_InvalidNeedRM, iemOp_vpaddd_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
3849 /* 0xff */ IEMOP_X4(iemOp_vud0) /* ?? */
3850};
3851AssertCompile(RT_ELEMENTS(g_apfnVexMap1) == 1024);
3852/** @} */
3853
3854
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