VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h@ 100567

Last change on this file since 100567 was 100567, checked in by vboxsync, 17 months ago

VMM/IEM: Implement vbroadcast{ss,sd,f128} instruction emulation, bugref:9898
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1/* $Id: IEMAllInstructionsVexMap2.cpp.h 100567 2023-07-13 19:19:33Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstructionsThree0f38.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/** @name VEX Opcode Map 2
33 * @{
34 */
35
36/* Opcode VEX.0F38 0x00 - invalid. */
37
38
39/** Opcode VEX.66.0F38 0x00. */
40FNIEMOP_DEF(iemOp_vpshufb_Vx_Hx_Wx)
41{
42 IEMOP_MNEMONIC3(VEX_RVM, VPSHUFB, vpshufb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
43 IEMOPMEDIAF3_INIT_VARS(vpshufb);
44 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
45}
46
47
48/* Opcode VEX.0F38 0x01 - invalid. */
49
50
51/** Opcode VEX.66.0F38 0x01. */
52FNIEMOP_DEF(iemOp_vphaddw_Vx_Hx_Wx)
53{
54 IEMOP_MNEMONIC3(VEX_RVM, VPHADDW, vphaddw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
55 IEMOPMEDIAOPTF3_INIT_VARS(vphaddw);
56 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
57}
58
59
60/* Opcode VEX.0F38 0x02 - invalid. */
61
62
63/** Opcode VEX.66.0F38 0x02. */
64FNIEMOP_DEF(iemOp_vphaddd_Vx_Hx_Wx)
65{
66 IEMOP_MNEMONIC3(VEX_RVM, VPHADDD, vphaddd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
67 IEMOPMEDIAOPTF3_INIT_VARS(vphaddd);
68 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
69}
70
71
72/* Opcode VEX.0F38 0x03 - invalid. */
73
74
75/** Opcode VEX.66.0F38 0x03. */
76FNIEMOP_DEF(iemOp_vphaddsw_Vx_Hx_Wx)
77{
78 IEMOP_MNEMONIC3(VEX_RVM, VPHADDSW, vphaddsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
79 IEMOPMEDIAOPTF3_INIT_VARS(vphaddsw);
80 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
81}
82
83
84/* Opcode VEX.0F38 0x04 - invalid. */
85
86
87/** Opcode VEX.66.0F38 0x04. */
88FNIEMOP_DEF(iemOp_vpmaddubsw_Vx_Hx_Wx)
89{
90 IEMOP_MNEMONIC3(VEX_RVM, VPMADDUBSW, vpmaddubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
91 IEMOPMEDIAOPTF3_INIT_VARS(vpmaddubsw);
92 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
93}
94
95
96/* Opcode VEX.0F38 0x05 - invalid. */
97
98
99/** Opcode VEX.66.0F38 0x05. */
100FNIEMOP_DEF(iemOp_vphsubw_Vx_Hx_Wx)
101{
102 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBW, vphsubw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
103 IEMOPMEDIAOPTF3_INIT_VARS(vphsubw);
104 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
105}
106
107
108/* Opcode VEX.0F38 0x06 - invalid. */
109
110
111/** Opcode VEX.66.0F38 0x06. */
112FNIEMOP_DEF(iemOp_vphsubd_Vx_Hx_Wx)
113{
114 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBD, vphsubd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
115 IEMOPMEDIAOPTF3_INIT_VARS(vphsubd);
116 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
117}
118
119
120/* Opcode VEX.0F38 0x07 - invalid. */
121
122
123/** Opcode VEX.66.0F38 0x07. */
124FNIEMOP_DEF(iemOp_vphsubsw_Vx_Hx_Wx)
125{
126 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBSW, vphsubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
127 IEMOPMEDIAOPTF3_INIT_VARS(vphsubsw);
128 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
129}
130
131
132/* Opcode VEX.0F38 0x08 - invalid. */
133
134
135/** Opcode VEX.66.0F38 0x08. */
136FNIEMOP_DEF(iemOp_vpsignb_Vx_Hx_Wx)
137{
138 IEMOP_MNEMONIC3(VEX_RVM, VPSIGNB, vpsignb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
139 IEMOPMEDIAOPTF3_INIT_VARS(vpsignb);
140 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
141}
142
143
144/* Opcode VEX.0F38 0x09 - invalid. */
145
146
147/** Opcode VEX.66.0F38 0x09. */
148FNIEMOP_DEF(iemOp_vpsignw_Vx_Hx_Wx)
149{
150 IEMOP_MNEMONIC3(VEX_RVM, VPSIGNW, vpsignw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
151 IEMOPMEDIAOPTF3_INIT_VARS(vpsignw);
152 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
153}
154
155
156/* Opcode VEX.0F38 0x0a - invalid. */
157
158
159/** Opcode VEX.66.0F38 0x0a. */
160FNIEMOP_DEF(iemOp_vpsignd_Vx_Hx_Wx)
161{
162 IEMOP_MNEMONIC3(VEX_RVM, VPSIGND, vpsignd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
163 IEMOPMEDIAOPTF3_INIT_VARS(vpsignd);
164 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
165}
166
167
168/* Opcode VEX.0F38 0x0b - invalid. */
169
170
171/** Opcode VEX.66.0F38 0x0b. */
172FNIEMOP_DEF(iemOp_vpmulhrsw_Vx_Hx_Wx)
173{
174 IEMOP_MNEMONIC3(VEX_RVM, VPMULHRSW, vpmulhrsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
175 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhrsw);
176 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
177}
178
179
180/* Opcode VEX.0F38 0x0c - invalid. */
181/** Opcode VEX.66.0F38 0x0c. */
182FNIEMOP_STUB(iemOp_vpermilps_Vx_Hx_Wx);
183/* Opcode VEX.0F38 0x0d - invalid. */
184/** Opcode VEX.66.0F38 0x0d. */
185FNIEMOP_STUB(iemOp_vpermilpd_Vx_Hx_Wx);
186/* Opcode VEX.0F38 0x0e - invalid. */
187/** Opcode VEX.66.0F38 0x0e. */
188FNIEMOP_STUB(iemOp_vtestps_Vx_Wx);
189/* Opcode VEX.0F38 0x0f - invalid. */
190/** Opcode VEX.66.0F38 0x0f. */
191FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx);
192
193
194/* Opcode VEX.0F38 0x10 - invalid */
195/* Opcode VEX.66.0F38 0x10 - invalid (legacy only). */
196/* Opcode VEX.0F38 0x11 - invalid */
197/* Opcode VEX.66.0F38 0x11 - invalid */
198/* Opcode VEX.0F38 0x12 - invalid */
199/* Opcode VEX.66.0F38 0x12 - invalid */
200/* Opcode VEX.0F38 0x13 - invalid */
201/* Opcode VEX.66.0F38 0x13 - invalid (vex only). */
202/* Opcode VEX.0F38 0x14 - invalid */
203/* Opcode VEX.66.0F38 0x14 - invalid (legacy only). */
204/* Opcode VEX.0F38 0x15 - invalid */
205/* Opcode VEX.66.0F38 0x15 - invalid (legacy only). */
206/* Opcode VEX.0F38 0x16 - invalid */
207/** Opcode VEX.66.0F38 0x16. */
208FNIEMOP_STUB(iemOp_vpermps_Vqq_Hqq_Wqq);
209/* Opcode VEX.0F38 0x17 - invalid */
210
211
212/** Opcode VEX.66.0F38 0x17 - invalid */
213FNIEMOP_DEF(iemOp_vptest_Vx_Wx)
214{
215 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
216 if (IEM_IS_MODRM_REG_MODE(bRm))
217 {
218 /*
219 * Register, register.
220 */
221 if (pVCpu->iem.s.uVexLength)
222 {
223 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
224 IEM_MC_BEGIN(3, 2);
225 IEM_MC_LOCAL(RTUINT256U, uSrc1);
226 IEM_MC_LOCAL(RTUINT256U, uSrc2);
227 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
228 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
229 IEM_MC_ARG(uint32_t *, pEFlags, 2);
230 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
231 IEM_MC_PREPARE_AVX_USAGE();
232 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
233 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
234 IEM_MC_REF_EFLAGS(pEFlags);
235 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
236 puSrc1, puSrc2, pEFlags);
237 IEM_MC_ADVANCE_RIP_AND_FINISH();
238 IEM_MC_END();
239 }
240 else
241 {
242 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
243 IEM_MC_BEGIN(3, 0);
244 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
245 IEM_MC_ARG(PCRTUINT128U, puSrc2, 1);
246 IEM_MC_ARG(uint32_t *, pEFlags, 2);
247 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
248 IEM_MC_PREPARE_AVX_USAGE();
249 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
250 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
251 IEM_MC_REF_EFLAGS(pEFlags);
252 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
253 IEM_MC_ADVANCE_RIP_AND_FINISH();
254 IEM_MC_END();
255 }
256 }
257 else
258 {
259 /*
260 * Register, memory.
261 */
262 if (pVCpu->iem.s.uVexLength)
263 {
264 IEM_MC_BEGIN(3, 3);
265 IEM_MC_LOCAL(RTUINT256U, uSrc1);
266 IEM_MC_LOCAL(RTUINT256U, uSrc2);
267 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
268 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
269 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
270 IEM_MC_ARG(uint32_t *, pEFlags, 2);
271
272 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
273 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
274 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
275 IEM_MC_PREPARE_AVX_USAGE();
276
277 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
278 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
279 IEM_MC_REF_EFLAGS(pEFlags);
280 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
281 puSrc1, puSrc2, pEFlags);
282
283 IEM_MC_ADVANCE_RIP_AND_FINISH();
284 IEM_MC_END();
285 }
286 else
287 {
288 IEM_MC_BEGIN(3, 2);
289 IEM_MC_LOCAL(RTUINT128U, uSrc2);
290 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
291 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
292 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1);
293 IEM_MC_ARG(uint32_t *, pEFlags, 2);
294
295 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
296 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
297 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
298 IEM_MC_PREPARE_AVX_USAGE();
299
300 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
301 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
302 IEM_MC_REF_EFLAGS(pEFlags);
303 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
304
305 IEM_MC_ADVANCE_RIP_AND_FINISH();
306 IEM_MC_END();
307 }
308 }
309}
310
311
312/* Opcode VEX.0F38 0x18 - invalid */
313
314
315/** Opcode VEX.66.0F38 0x18. */
316FNIEMOP_DEF(iemOp_vbroadcastss_Vx_Wd)
317{
318 IEMOP_MNEMONIC2(VEX_RM, VBROADCASTSS, vbroadcastss, Vx, Wx, DISOPTYPE_HARMLESS, 0);
319 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
320 if (IEM_IS_MODRM_REG_MODE(bRm))
321 {
322 /*
323 * Register, register.
324 */
325 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
326 if (pVCpu->iem.s.uVexLength)
327 {
328 IEM_MC_BEGIN(0, 1);
329 IEM_MC_LOCAL(uint32_t, uSrc);
330
331 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
332 IEM_MC_PREPARE_AVX_USAGE();
333
334 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
335 IEM_MC_STORE_YREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc);
336 IEM_MC_STORE_YREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc);
337 IEM_MC_STORE_YREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc);
338 IEM_MC_STORE_YREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc);
339 IEM_MC_STORE_YREGHI_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc);
340 IEM_MC_STORE_YREGHI_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc);
341 IEM_MC_STORE_YREGHI_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc);
342 IEM_MC_STORE_YREGHI_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc);
343
344 IEM_MC_ADVANCE_RIP_AND_FINISH();
345 IEM_MC_END();
346 }
347 else
348 {
349 IEM_MC_BEGIN(0, 1);
350 IEM_MC_LOCAL(uint32_t, uSrc);
351
352 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
353 IEM_MC_PREPARE_AVX_USAGE();
354 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
355 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc);
356 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc);
357 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc);
358 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc);
359 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
360
361 IEM_MC_ADVANCE_RIP_AND_FINISH();
362 IEM_MC_END();
363 }
364 }
365 else
366 {
367 /*
368 * Register, memory.
369 */
370 if (pVCpu->iem.s.uVexLength)
371 {
372 IEM_MC_BEGIN(0, 2);
373 IEM_MC_LOCAL(uint32_t, uSrc);
374 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
375
376 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
377 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
378 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
379 IEM_MC_PREPARE_AVX_USAGE();
380
381 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
382 IEM_MC_STORE_YREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc);
383 IEM_MC_STORE_YREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc);
384 IEM_MC_STORE_YREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc);
385 IEM_MC_STORE_YREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc);
386 IEM_MC_STORE_YREGHI_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc);
387 IEM_MC_STORE_YREGHI_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc);
388 IEM_MC_STORE_YREGHI_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc);
389 IEM_MC_STORE_YREGHI_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc);
390
391 IEM_MC_ADVANCE_RIP_AND_FINISH();
392 IEM_MC_END();
393 }
394 else
395 {
396 IEM_MC_BEGIN(3, 3);
397 IEM_MC_LOCAL(uint32_t, uSrc);
398 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
399
400 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
401 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
402 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
403 IEM_MC_PREPARE_AVX_USAGE();
404
405 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
406 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc);
407 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc);
408 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 2, uSrc);
409 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc);
410 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
411
412 IEM_MC_ADVANCE_RIP_AND_FINISH();
413 IEM_MC_END();
414 }
415 }
416}
417
418
419/* Opcode VEX.0F38 0x19 - invalid */
420
421
422/** Opcode VEX.66.0F38 0x19. */
423FNIEMOP_DEF(iemOp_vbroadcastsd_Vqq_Wq)
424{
425 IEMOP_MNEMONIC2(VEX_RM, VBROADCASTSD, vbroadcastsd, Vx, Wx, DISOPTYPE_HARMLESS, 0);
426 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
427 if (IEM_IS_MODRM_REG_MODE(bRm))
428 {
429 /*
430 * Register, register.
431 */
432 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
433 if (pVCpu->iem.s.uVexLength)
434 {
435 IEM_MC_BEGIN(0, 1);
436 IEM_MC_LOCAL(uint64_t, uSrc);
437
438 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
439 IEM_MC_PREPARE_AVX_USAGE();
440
441 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
442 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc);
443 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc);
444 IEM_MC_STORE_YREGHI_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc);
445 IEM_MC_STORE_YREGHI_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc);
446
447 IEM_MC_ADVANCE_RIP_AND_FINISH();
448 IEM_MC_END();
449 }
450 else
451 {
452 IEM_MC_BEGIN(0, 1);
453 IEM_MC_LOCAL(uint64_t, uSrc);
454
455 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
456 IEM_MC_PREPARE_AVX_USAGE();
457 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0);
458 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc);
459 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc);
460 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm));
461
462 IEM_MC_ADVANCE_RIP_AND_FINISH();
463 IEM_MC_END();
464 }
465 }
466 else
467 {
468 /*
469 * Register, memory.
470 */
471 IEM_MC_BEGIN(0, 2);
472 IEM_MC_LOCAL(uint64_t, uSrc);
473 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
474
475 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
476 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx);
477 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
478 IEM_MC_PREPARE_AVX_USAGE();
479
480 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
481 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc);
482 IEM_MC_STORE_YREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc);
483 IEM_MC_STORE_YREGHI_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0, uSrc);
484 IEM_MC_STORE_YREGHI_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1, uSrc);
485
486 IEM_MC_ADVANCE_RIP_AND_FINISH();
487 IEM_MC_END();
488 }
489}
490
491
492/* Opcode VEX.0F38 0x1a - invalid */
493
494
495/** Opcode VEX.66.0F38 0x1a. */
496FNIEMOP_DEF(iemOp_vbroadcastf128_Vqq_Mdq)
497{
498 IEMOP_MNEMONIC2(VEX_RM, VBROADCASTF128, vbroadcastf128, Vx, Wx, DISOPTYPE_HARMLESS, 0);
499 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
500 if (IEM_IS_MODRM_REG_MODE(bRm))
501 {
502 /*
503 * No register, register.
504 */
505 IEMOP_RAISE_INVALID_OPCODE_RET();
506 }
507 else
508 {
509 /*
510 * Register, memory.
511 */
512 IEM_MC_BEGIN(0, 2);
513 IEM_MC_LOCAL(RTUINT128U, uSrc);
514 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
515
516 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
517 IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(fAvx);
518 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
519 IEM_MC_PREPARE_AVX_USAGE();
520
521 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
522 IEM_MC_STORE_YREG_BROADCAST_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
523
524 IEM_MC_ADVANCE_RIP_AND_FINISH();
525 IEM_MC_END();
526 }
527}
528
529
530/* Opcode VEX.0F38 0x1b - invalid */
531/* Opcode VEX.66.0F38 0x1b - invalid */
532/* Opcode VEX.0F38 0x1c - invalid. */
533
534
535/** Opcode VEX.66.0F38 0x1c. */
536FNIEMOP_DEF(iemOp_vpabsb_Vx_Wx)
537{
538 IEMOP_MNEMONIC2(VEX_RM, VPABSB, vpabsb, Vx, Wx, DISOPTYPE_HARMLESS, 0);
539 IEMOPMEDIAOPTF2_INIT_VARS(vpabsb);
540 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
541}
542
543
544/* Opcode VEX.0F38 0x1d - invalid. */
545
546
547/** Opcode VEX.66.0F38 0x1d. */
548FNIEMOP_DEF(iemOp_vpabsw_Vx_Wx)
549{
550 IEMOP_MNEMONIC2(VEX_RM, VPABSW, vpabsw, Vx, Wx, DISOPTYPE_HARMLESS, 0);
551 IEMOPMEDIAOPTF2_INIT_VARS(vpabsw);
552 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
553}
554
555/* Opcode VEX.0F38 0x1e - invalid. */
556
557
558/** Opcode VEX.66.0F38 0x1e. */
559FNIEMOP_DEF(iemOp_vpabsd_Vx_Wx)
560{
561 IEMOP_MNEMONIC2(VEX_RM, VPABSD, vpabsd, Vx, Wx, DISOPTYPE_HARMLESS, 0);
562 IEMOPMEDIAOPTF2_INIT_VARS(vpabsd);
563 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
564}
565
566
567/* Opcode VEX.0F38 0x1f - invalid */
568/* Opcode VEX.66.0F38 0x1f - invalid */
569
570
571/** Body for the vpmov{s,z}x* instructions. */
572#define IEMOP_BODY_VPMOV_S_Z(a_Instr, a_SrcWidth) \
573 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
574 if (IEM_IS_MODRM_REG_MODE(bRm)) \
575 { \
576 /* \
577 * Register, register. \
578 */ \
579 if (pVCpu->iem.s.uVexLength) \
580 { \
581 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2); \
582 IEM_MC_BEGIN(2, 1); \
583 IEM_MC_LOCAL(RTUINT256U, uDst); \
584 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
585 IEM_MC_ARG(PCRTUINT128U, puSrc, 1); \
586 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
587 IEM_MC_PREPARE_AVX_USAGE(); \
588 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
589 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
590 iemAImpl_ ## a_Instr ## _u256_fallback), \
591 puDst, puSrc); \
592 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
593 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
594 IEM_MC_END(); \
595 } \
596 else \
597 { \
598 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx); \
599 IEM_MC_BEGIN(2, 0); \
600 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
601 IEM_MC_ARG(uint64_t, uSrc, 1); \
602 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
603 IEM_MC_PREPARE_AVX_USAGE(); \
604 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
605 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /* a_iQword*/); \
606 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
607 iemAImpl_## a_Instr ## _u128_fallback), \
608 puDst, uSrc); \
609 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
610 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
611 IEM_MC_END(); \
612 } \
613 } \
614 else \
615 { \
616 /* \
617 * Register, memory. \
618 */ \
619 if (pVCpu->iem.s.uVexLength) \
620 { \
621 IEM_MC_BEGIN(2, 3); \
622 IEM_MC_LOCAL(RTUINT256U, uDst); \
623 IEM_MC_LOCAL(RTUINT128U, uSrc); \
624 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
625 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
626 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1); \
627 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
628 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2); \
629 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
630 IEM_MC_PREPARE_AVX_USAGE(); \
631 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
632 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
633 iemAImpl_ ## a_Instr ## _u256_fallback), \
634 puDst, puSrc); \
635 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
636 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
637 IEM_MC_END(); \
638 } \
639 else \
640 { \
641 IEM_MC_BEGIN(2, 1); \
642 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
643 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
644 IEM_MC_ARG(uint ## a_SrcWidth ##_t, uSrc, 1); \
645 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
646 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx); \
647 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); \
648 IEM_MC_PREPARE_AVX_USAGE(); \
649 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
650 IEM_MC_FETCH_MEM_U ## a_SrcWidth (uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
651 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
652 iemAImpl_ ## a_Instr ## _u128_fallback), \
653 puDst, uSrc); \
654 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
655 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
656 IEM_MC_END(); \
657 } \
658 } \
659 (void)0
660
661/** Opcode VEX.66.0F38 0x20. */
662FNIEMOP_DEF(iemOp_vpmovsxbw_Vx_UxMq)
663{
664 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
665 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBW, vpmovsxbw, Vx, Wq, DISOPTYPE_HARMLESS, 0);
666 IEMOP_BODY_VPMOV_S_Z(vpmovsxbw, 64);
667}
668
669
670/** Opcode VEX.66.0F38 0x21. */
671FNIEMOP_DEF(iemOp_vpmovsxbd_Vx_UxMd)
672{
673 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
674 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBD, vpmovsxbd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
675 IEMOP_BODY_VPMOV_S_Z(vpmovsxbd, 32);
676}
677
678
679/** Opcode VEX.66.0F38 0x22. */
680FNIEMOP_DEF(iemOp_vpmovsxbq_Vx_UxMw)
681{
682 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
683 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBQ, vpmovsxbq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
684 IEMOP_BODY_VPMOV_S_Z(vpmovsxbq, 16);
685}
686
687
688/** Opcode VEX.66.0F38 0x23. */
689FNIEMOP_DEF(iemOp_vpmovsxwd_Vx_UxMq)
690{
691 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
692 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXWD, vpmovsxwd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
693 IEMOP_BODY_VPMOV_S_Z(vpmovsxwd, 64);
694}
695
696
697/** Opcode VEX.66.0F38 0x24. */
698FNIEMOP_DEF(iemOp_vpmovsxwq_Vx_UxMd)
699{
700 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
701 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXWQ, vpmovsxwq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
702 IEMOP_BODY_VPMOV_S_Z(vpmovsxwq, 32);
703}
704
705
706/** Opcode VEX.66.0F38 0x25. */
707FNIEMOP_DEF(iemOp_vpmovsxdq_Vx_UxMq)
708{
709 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
710 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXDQ, vpmovsxdq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
711 IEMOP_BODY_VPMOV_S_Z(vpmovsxdq, 64);
712}
713
714
715/* Opcode VEX.66.0F38 0x26 - invalid */
716/* Opcode VEX.66.0F38 0x27 - invalid */
717
718
719/** Opcode VEX.66.0F38 0x28. */
720FNIEMOP_DEF(iemOp_vpmuldq_Vx_Hx_Wx)
721{
722 IEMOP_MNEMONIC3(VEX_RVM, VPMULDQ, vpmuldq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
723 IEMOPMEDIAOPTF3_INIT_VARS(vpmuldq);
724 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
725}
726
727
728/** Opcode VEX.66.0F38 0x29. */
729FNIEMOP_DEF(iemOp_vpcmpeqq_Vx_Hx_Wx)
730{
731 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQQ, vpcmpeqq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
732 IEMOPMEDIAF3_INIT_VARS(vpcmpeqq);
733 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
734}
735
736
737FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
738{
739 Assert(pVCpu->iem.s.uVexLength <= 1);
740 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
741 if (IEM_IS_MODRM_MEM_MODE(bRm))
742 {
743 if (pVCpu->iem.s.uVexLength == 0)
744 {
745 /**
746 * @opcode 0x2a
747 * @opcodesub !11 mr/reg vex.l=0
748 * @oppfx 0x66
749 * @opcpuid avx
750 * @opgroup og_avx_cachect
751 * @opxcpttype 1
752 * @optest op1=-1 op2=2 -> op1=2
753 * @optest op1=0 op2=-42 -> op1=-42
754 */
755 /* 128-bit: Memory, register. */
756 IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
757 DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
758 IEM_MC_BEGIN(0, 2);
759 IEM_MC_LOCAL(RTUINT128U, uSrc);
760 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
761
762 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
763 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx);
764 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
765 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
766
767 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
768 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
769
770 IEM_MC_ADVANCE_RIP_AND_FINISH();
771 IEM_MC_END();
772 }
773 else
774 {
775 /**
776 * @opdone
777 * @opcode 0x2a
778 * @opcodesub !11 mr/reg vex.l=1
779 * @oppfx 0x66
780 * @opcpuid avx2
781 * @opgroup og_avx2_cachect
782 * @opxcpttype 1
783 * @optest op1=-1 op2=2 -> op1=2
784 * @optest op1=0 op2=-42 -> op1=-42
785 */
786 /* 256-bit: Memory, register. */
787 IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
788 DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES);
789 IEM_MC_BEGIN(0, 2);
790 IEM_MC_LOCAL(RTUINT256U, uSrc);
791 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
792
793 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
794 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2);
795 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
796 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
797
798 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
799 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
800
801 IEM_MC_ADVANCE_RIP_AND_FINISH();
802 IEM_MC_END();
803 }
804 }
805
806 /**
807 * @opdone
808 * @opmnemonic udvex660f382arg
809 * @opcode 0x2a
810 * @opcodesub 11 mr/reg
811 * @oppfx 0x66
812 * @opunused immediate
813 * @opcpuid avx
814 * @optest ->
815 */
816 else
817 IEMOP_RAISE_INVALID_OPCODE_RET();
818}
819
820
821/** Opcode VEX.66.0F38 0x2b. */
822FNIEMOP_DEF(iemOp_vpackusdw_Vx_Hx_Wx)
823{
824 IEMOP_MNEMONIC3(VEX_RVM, VPACKUSDW, vpackusdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
825 IEMOPMEDIAOPTF3_INIT_VARS( vpackusdw);
826 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
827}
828
829
830/** Opcode VEX.66.0F38 0x2c. */
831FNIEMOP_STUB(iemOp_vmaskmovps_Vx_Hx_Mx);
832/** Opcode VEX.66.0F38 0x2d. */
833FNIEMOP_STUB(iemOp_vmaskmovpd_Vx_Hx_Mx);
834/** Opcode VEX.66.0F38 0x2e. */
835FNIEMOP_STUB(iemOp_vmaskmovps_Mx_Hx_Vx);
836/** Opcode VEX.66.0F38 0x2f. */
837FNIEMOP_STUB(iemOp_vmaskmovpd_Mx_Hx_Vx);
838
839
840/** Opcode VEX.66.0F38 0x30. */
841FNIEMOP_DEF(iemOp_vpmovzxbw_Vx_UxMq)
842{
843 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
844 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBW, vpmovzxbw, Vx, Wq, DISOPTYPE_HARMLESS, 0);
845 IEMOP_BODY_VPMOV_S_Z(vpmovzxbw, 64);
846}
847
848
849/** Opcode VEX.66.0F38 0x31. */
850FNIEMOP_DEF(iemOp_vpmovzxbd_Vx_UxMd)
851{
852 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
853 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBD, vpmovzxbd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
854 IEMOP_BODY_VPMOV_S_Z(vpmovzxbd, 32);
855}
856
857
858/** Opcode VEX.66.0F38 0x32. */
859FNIEMOP_DEF(iemOp_vpmovzxbq_Vx_UxMw)
860{
861 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
862 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBQ, vpmovzxbq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
863 IEMOP_BODY_VPMOV_S_Z(vpmovzxbq, 16);
864}
865
866
867/** Opcode VEX.66.0F38 0x33. */
868FNIEMOP_DEF(iemOp_vpmovzxwd_Vx_UxMq)
869{
870 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
871 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXWD, vpmovzxwd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
872 IEMOP_BODY_VPMOV_S_Z(vpmovzxwd, 64);
873}
874
875
876/** Opcode VEX.66.0F38 0x34. */
877FNIEMOP_DEF(iemOp_vpmovzxwq_Vx_UxMd)
878{
879 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
880 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXWQ, vpmovzxwq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
881 IEMOP_BODY_VPMOV_S_Z(vpmovzxwq, 32);
882}
883
884
885/** Opcode VEX.66.0F38 0x35. */
886FNIEMOP_DEF(iemOp_vpmovzxdq_Vx_UxMq)
887{
888 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
889 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXDQ, vpmovzxdq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
890 IEMOP_BODY_VPMOV_S_Z(vpmovzxdq, 64);
891}
892
893
894/* Opcode VEX.66.0F38 0x36. */
895FNIEMOP_STUB(iemOp_vpermd_Vqq_Hqq_Wqq);
896
897
898/** Opcode VEX.66.0F38 0x37. */
899FNIEMOP_DEF(iemOp_vpcmpgtq_Vx_Hx_Wx)
900{
901 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTQ, vpcmpgtq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
902 IEMOPMEDIAF3_INIT_VARS(vpcmpgtq);
903 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
904}
905
906
907/** Opcode VEX.66.0F38 0x38. */
908FNIEMOP_DEF(iemOp_vpminsb_Vx_Hx_Wx)
909{
910 IEMOP_MNEMONIC3(VEX_RVM, VPMINSB, vpminsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
911 IEMOPMEDIAF3_INIT_VARS(vpminsb);
912 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
913}
914
915
916/** Opcode VEX.66.0F38 0x39. */
917FNIEMOP_DEF(iemOp_vpminsd_Vx_Hx_Wx)
918{
919 IEMOP_MNEMONIC3(VEX_RVM, VPMINSD, vpminsd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
920 IEMOPMEDIAF3_INIT_VARS(vpminsd);
921 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
922}
923
924
925/** Opcode VEX.66.0F38 0x3a. */
926FNIEMOP_DEF(iemOp_vpminuw_Vx_Hx_Wx)
927{
928 IEMOP_MNEMONIC3(VEX_RVM, VPMINUW, vpminuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
929 IEMOPMEDIAF3_INIT_VARS(vpminuw);
930 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
931}
932
933
934/** Opcode VEX.66.0F38 0x3b. */
935FNIEMOP_DEF(iemOp_vpminud_Vx_Hx_Wx)
936{
937 IEMOP_MNEMONIC3(VEX_RVM, VPMINUD, vpminud, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
938 IEMOPMEDIAF3_INIT_VARS(vpminud);
939 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
940}
941
942
943/** Opcode VEX.66.0F38 0x3c. */
944FNIEMOP_DEF(iemOp_vpmaxsb_Vx_Hx_Wx)
945{
946 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSB, vpmaxsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
947 IEMOPMEDIAF3_INIT_VARS(vpmaxsb);
948 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
949}
950
951
952/** Opcode VEX.66.0F38 0x3d. */
953FNIEMOP_DEF(iemOp_vpmaxsd_Vx_Hx_Wx)
954{
955 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSD, vpmaxsd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
956 IEMOPMEDIAF3_INIT_VARS(vpmaxsd);
957 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
958}
959
960
961/** Opcode VEX.66.0F38 0x3e. */
962FNIEMOP_DEF(iemOp_vpmaxuw_Vx_Hx_Wx)
963{
964 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUW, vpmaxuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
965 IEMOPMEDIAF3_INIT_VARS(vpmaxuw);
966 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
967}
968
969
970/** Opcode VEX.66.0F38 0x3f. */
971FNIEMOP_DEF(iemOp_vpmaxud_Vx_Hx_Wx)
972{
973 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUD, vpmaxud, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
974 IEMOPMEDIAF3_INIT_VARS(vpmaxud);
975 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
976}
977
978
979/** Opcode VEX.66.0F38 0x40. */
980FNIEMOP_DEF(iemOp_vpmulld_Vx_Hx_Wx)
981{
982 IEMOP_MNEMONIC3(VEX_RVM, VPMULLD, vpmulld, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
983 IEMOPMEDIAOPTF3_INIT_VARS(vpmulld);
984 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
985}
986
987
988/** Opcode VEX.66.0F38 0x41. */
989FNIEMOP_DEF(iemOp_vphminposuw_Vdq_Wdq)
990{
991 IEMOP_MNEMONIC2(VEX_RM, VPHMINPOSUW, vphminposuw, Vdq, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
992 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
993 if (IEM_IS_MODRM_REG_MODE(bRm))
994 {
995 /*
996 * Register, register.
997 */
998 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
999 IEM_MC_BEGIN(2, 0);
1000 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1001 IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1002 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1003 IEM_MC_PREPARE_AVX_USAGE();
1004 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1005 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm));
1006 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback),
1007 puDst, puSrc);
1008 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1009 IEM_MC_ADVANCE_RIP_AND_FINISH();
1010 IEM_MC_END();
1011 }
1012 else
1013 {
1014 /*
1015 * Register, memory.
1016 */
1017 IEM_MC_BEGIN(2, 2);
1018 IEM_MC_LOCAL(RTUINT128U, uSrc);
1019 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1020 IEM_MC_ARG(PRTUINT128U, puDst, 0);
1021 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1022
1023 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1024 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fAvx);
1025 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
1026 IEM_MC_PREPARE_AVX_USAGE();
1027
1028 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1029 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1030 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback),
1031 puDst, puSrc);
1032 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
1033
1034 IEM_MC_ADVANCE_RIP_AND_FINISH();
1035 IEM_MC_END();
1036 }
1037}
1038
1039
1040/* Opcode VEX.66.0F38 0x42 - invalid. */
1041/* Opcode VEX.66.0F38 0x43 - invalid. */
1042/* Opcode VEX.66.0F38 0x44 - invalid. */
1043/** Opcode VEX.66.0F38 0x45. */
1044FNIEMOP_STUB(iemOp_vpsrlvd_q_Vx_Hx_Wx);
1045/** Opcode VEX.66.0F38 0x46. */
1046FNIEMOP_STUB(iemOp_vsravd_Vx_Hx_Wx);
1047/** Opcode VEX.66.0F38 0x47. */
1048FNIEMOP_STUB(iemOp_vpsllvd_q_Vx_Hx_Wx);
1049/* Opcode VEX.66.0F38 0x48 - invalid. */
1050/* Opcode VEX.66.0F38 0x49 - invalid. */
1051/* Opcode VEX.66.0F38 0x4a - invalid. */
1052/* Opcode VEX.66.0F38 0x4b - invalid. */
1053/* Opcode VEX.66.0F38 0x4c - invalid. */
1054/* Opcode VEX.66.0F38 0x4d - invalid. */
1055/* Opcode VEX.66.0F38 0x4e - invalid. */
1056/* Opcode VEX.66.0F38 0x4f - invalid. */
1057
1058/* Opcode VEX.66.0F38 0x50 - invalid. */
1059/* Opcode VEX.66.0F38 0x51 - invalid. */
1060/* Opcode VEX.66.0F38 0x52 - invalid. */
1061/* Opcode VEX.66.0F38 0x53 - invalid. */
1062/* Opcode VEX.66.0F38 0x54 - invalid. */
1063/* Opcode VEX.66.0F38 0x55 - invalid. */
1064/* Opcode VEX.66.0F38 0x56 - invalid. */
1065/* Opcode VEX.66.0F38 0x57 - invalid. */
1066/** Opcode VEX.66.0F38 0x58. */
1067FNIEMOP_STUB(iemOp_vpbroadcastd_Vx_Wx);
1068/** Opcode VEX.66.0F38 0x59. */
1069FNIEMOP_STUB(iemOp_vpbroadcastq_Vx_Wx);
1070/** Opcode VEX.66.0F38 0x5a. */
1071FNIEMOP_STUB(iemOp_vbroadcasti128_Vqq_Mdq);
1072/* Opcode VEX.66.0F38 0x5b - invalid. */
1073/* Opcode VEX.66.0F38 0x5c - invalid. */
1074/* Opcode VEX.66.0F38 0x5d - invalid. */
1075/* Opcode VEX.66.0F38 0x5e - invalid. */
1076/* Opcode VEX.66.0F38 0x5f - invalid. */
1077
1078/* Opcode VEX.66.0F38 0x60 - invalid. */
1079/* Opcode VEX.66.0F38 0x61 - invalid. */
1080/* Opcode VEX.66.0F38 0x62 - invalid. */
1081/* Opcode VEX.66.0F38 0x63 - invalid. */
1082/* Opcode VEX.66.0F38 0x64 - invalid. */
1083/* Opcode VEX.66.0F38 0x65 - invalid. */
1084/* Opcode VEX.66.0F38 0x66 - invalid. */
1085/* Opcode VEX.66.0F38 0x67 - invalid. */
1086/* Opcode VEX.66.0F38 0x68 - invalid. */
1087/* Opcode VEX.66.0F38 0x69 - invalid. */
1088/* Opcode VEX.66.0F38 0x6a - invalid. */
1089/* Opcode VEX.66.0F38 0x6b - invalid. */
1090/* Opcode VEX.66.0F38 0x6c - invalid. */
1091/* Opcode VEX.66.0F38 0x6d - invalid. */
1092/* Opcode VEX.66.0F38 0x6e - invalid. */
1093/* Opcode VEX.66.0F38 0x6f - invalid. */
1094
1095/* Opcode VEX.66.0F38 0x70 - invalid. */
1096/* Opcode VEX.66.0F38 0x71 - invalid. */
1097/* Opcode VEX.66.0F38 0x72 - invalid. */
1098/* Opcode VEX.66.0F38 0x73 - invalid. */
1099/* Opcode VEX.66.0F38 0x74 - invalid. */
1100/* Opcode VEX.66.0F38 0x75 - invalid. */
1101/* Opcode VEX.66.0F38 0x76 - invalid. */
1102/* Opcode VEX.66.0F38 0x77 - invalid. */
1103/** Opcode VEX.66.0F38 0x78. */
1104FNIEMOP_STUB(iemOp_vpbroadcastb_Vx_Wx);
1105/** Opcode VEX.66.0F38 0x79. */
1106FNIEMOP_STUB(iemOp_vpbroadcastw_Vx_Wx);
1107/* Opcode VEX.66.0F38 0x7a - invalid. */
1108/* Opcode VEX.66.0F38 0x7b - invalid. */
1109/* Opcode VEX.66.0F38 0x7c - invalid. */
1110/* Opcode VEX.66.0F38 0x7d - invalid. */
1111/* Opcode VEX.66.0F38 0x7e - invalid. */
1112/* Opcode VEX.66.0F38 0x7f - invalid. */
1113
1114/* Opcode VEX.66.0F38 0x80 - invalid (legacy only). */
1115/* Opcode VEX.66.0F38 0x81 - invalid (legacy only). */
1116/* Opcode VEX.66.0F38 0x82 - invalid (legacy only). */
1117/* Opcode VEX.66.0F38 0x83 - invalid. */
1118/* Opcode VEX.66.0F38 0x84 - invalid. */
1119/* Opcode VEX.66.0F38 0x85 - invalid. */
1120/* Opcode VEX.66.0F38 0x86 - invalid. */
1121/* Opcode VEX.66.0F38 0x87 - invalid. */
1122/* Opcode VEX.66.0F38 0x88 - invalid. */
1123/* Opcode VEX.66.0F38 0x89 - invalid. */
1124/* Opcode VEX.66.0F38 0x8a - invalid. */
1125/* Opcode VEX.66.0F38 0x8b - invalid. */
1126/** Opcode VEX.66.0F38 0x8c. */
1127FNIEMOP_STUB(iemOp_vpmaskmovd_q_Vx_Hx_Mx);
1128/* Opcode VEX.66.0F38 0x8d - invalid. */
1129/** Opcode VEX.66.0F38 0x8e. */
1130FNIEMOP_STUB(iemOp_vpmaskmovd_q_Mx_Vx_Hx);
1131/* Opcode VEX.66.0F38 0x8f - invalid. */
1132
1133/** Opcode VEX.66.0F38 0x90 (vex only). */
1134FNIEMOP_STUB(iemOp_vgatherdd_q_Vx_Hx_Wx);
1135/** Opcode VEX.66.0F38 0x91 (vex only). */
1136FNIEMOP_STUB(iemOp_vgatherqd_q_Vx_Hx_Wx);
1137/** Opcode VEX.66.0F38 0x92 (vex only). */
1138FNIEMOP_STUB(iemOp_vgatherdps_d_Vx_Hx_Wx);
1139/** Opcode VEX.66.0F38 0x93 (vex only). */
1140FNIEMOP_STUB(iemOp_vgatherqps_d_Vx_Hx_Wx);
1141/* Opcode VEX.66.0F38 0x94 - invalid. */
1142/* Opcode VEX.66.0F38 0x95 - invalid. */
1143/** Opcode VEX.66.0F38 0x96 (vex only). */
1144FNIEMOP_STUB(iemOp_vfmaddsub132ps_q_Vx_Hx_Wx);
1145/** Opcode VEX.66.0F38 0x97 (vex only). */
1146FNIEMOP_STUB(iemOp_vfmsubadd132ps_d_Vx_Hx_Wx);
1147/** Opcode VEX.66.0F38 0x98 (vex only). */
1148FNIEMOP_STUB(iemOp_vfmadd132ps_d_Vx_Hx_Wx);
1149/** Opcode VEX.66.0F38 0x99 (vex only). */
1150FNIEMOP_STUB(iemOp_vfmadd132ss_d_Vx_Hx_Wx);
1151/** Opcode VEX.66.0F38 0x9a (vex only). */
1152FNIEMOP_STUB(iemOp_vfmsub132ps_d_Vx_Hx_Wx);
1153/** Opcode VEX.66.0F38 0x9b (vex only). */
1154FNIEMOP_STUB(iemOp_vfmsub132ss_d_Vx_Hx_Wx);
1155/** Opcode VEX.66.0F38 0x9c (vex only). */
1156FNIEMOP_STUB(iemOp_vfnmadd132ps_d_Vx_Hx_Wx);
1157/** Opcode VEX.66.0F38 0x9d (vex only). */
1158FNIEMOP_STUB(iemOp_vfnmadd132ss_d_Vx_Hx_Wx);
1159/** Opcode VEX.66.0F38 0x9e (vex only). */
1160FNIEMOP_STUB(iemOp_vfnmsub132ps_d_Vx_Hx_Wx);
1161/** Opcode VEX.66.0F38 0x9f (vex only). */
1162FNIEMOP_STUB(iemOp_vfnmsub132ss_d_Vx_Hx_Wx);
1163
1164/* Opcode VEX.66.0F38 0xa0 - invalid. */
1165/* Opcode VEX.66.0F38 0xa1 - invalid. */
1166/* Opcode VEX.66.0F38 0xa2 - invalid. */
1167/* Opcode VEX.66.0F38 0xa3 - invalid. */
1168/* Opcode VEX.66.0F38 0xa4 - invalid. */
1169/* Opcode VEX.66.0F38 0xa5 - invalid. */
1170/** Opcode VEX.66.0F38 0xa6 (vex only). */
1171FNIEMOP_STUB(iemOp_vfmaddsub213ps_d_Vx_Hx_Wx);
1172/** Opcode VEX.66.0F38 0xa7 (vex only). */
1173FNIEMOP_STUB(iemOp_vfmsubadd213ps_d_Vx_Hx_Wx);
1174/** Opcode VEX.66.0F38 0xa8 (vex only). */
1175FNIEMOP_STUB(iemOp_vfmadd213ps_d_Vx_Hx_Wx);
1176/** Opcode VEX.66.0F38 0xa9 (vex only). */
1177FNIEMOP_STUB(iemOp_vfmadd213ss_d_Vx_Hx_Wx);
1178/** Opcode VEX.66.0F38 0xaa (vex only). */
1179FNIEMOP_STUB(iemOp_vfmsub213ps_d_Vx_Hx_Wx);
1180/** Opcode VEX.66.0F38 0xab (vex only). */
1181FNIEMOP_STUB(iemOp_vfmsub213ss_d_Vx_Hx_Wx);
1182/** Opcode VEX.66.0F38 0xac (vex only). */
1183FNIEMOP_STUB(iemOp_vfnmadd213ps_d_Vx_Hx_Wx);
1184/** Opcode VEX.66.0F38 0xad (vex only). */
1185FNIEMOP_STUB(iemOp_vfnmadd213ss_d_Vx_Hx_Wx);
1186/** Opcode VEX.66.0F38 0xae (vex only). */
1187FNIEMOP_STUB(iemOp_vfnmsub213ps_d_Vx_Hx_Wx);
1188/** Opcode VEX.66.0F38 0xaf (vex only). */
1189FNIEMOP_STUB(iemOp_vfnmsub213ss_d_Vx_Hx_Wx);
1190
1191/* Opcode VEX.66.0F38 0xb0 - invalid. */
1192/* Opcode VEX.66.0F38 0xb1 - invalid. */
1193/* Opcode VEX.66.0F38 0xb2 - invalid. */
1194/* Opcode VEX.66.0F38 0xb3 - invalid. */
1195/* Opcode VEX.66.0F38 0xb4 - invalid. */
1196/* Opcode VEX.66.0F38 0xb5 - invalid. */
1197/** Opcode VEX.66.0F38 0xb6 (vex only). */
1198FNIEMOP_STUB(iemOp_vfmaddsub231ps_d_Vx_Hx_Wx);
1199/** Opcode VEX.66.0F38 0xb7 (vex only). */
1200FNIEMOP_STUB(iemOp_vfmsubadd231ps_d_Vx_Hx_Wx);
1201/** Opcode VEX.66.0F38 0xb8 (vex only). */
1202FNIEMOP_STUB(iemOp_vfmadd231ps_d_Vx_Hx_Wx);
1203/** Opcode VEX.66.0F38 0xb9 (vex only). */
1204FNIEMOP_STUB(iemOp_vfmadd231ss_d_Vx_Hx_Wx);
1205/** Opcode VEX.66.0F38 0xba (vex only). */
1206FNIEMOP_STUB(iemOp_vfmsub231ps_d_Vx_Hx_Wx);
1207/** Opcode VEX.66.0F38 0xbb (vex only). */
1208FNIEMOP_STUB(iemOp_vfmsub231ss_d_Vx_Hx_Wx);
1209/** Opcode VEX.66.0F38 0xbc (vex only). */
1210FNIEMOP_STUB(iemOp_vfnmadd231ps_d_Vx_Hx_Wx);
1211/** Opcode VEX.66.0F38 0xbd (vex only). */
1212FNIEMOP_STUB(iemOp_vfnmadd231ss_d_Vx_Hx_Wx);
1213/** Opcode VEX.66.0F38 0xbe (vex only). */
1214FNIEMOP_STUB(iemOp_vfnmsub231ps_d_Vx_Hx_Wx);
1215/** Opcode VEX.66.0F38 0xbf (vex only). */
1216FNIEMOP_STUB(iemOp_vfnmsub231ss_d_Vx_Hx_Wx);
1217
1218/* Opcode VEX.0F38 0xc0 - invalid. */
1219/* Opcode VEX.66.0F38 0xc0 - invalid. */
1220/* Opcode VEX.0F38 0xc1 - invalid. */
1221/* Opcode VEX.66.0F38 0xc1 - invalid. */
1222/* Opcode VEX.0F38 0xc2 - invalid. */
1223/* Opcode VEX.66.0F38 0xc2 - invalid. */
1224/* Opcode VEX.0F38 0xc3 - invalid. */
1225/* Opcode VEX.66.0F38 0xc3 - invalid. */
1226/* Opcode VEX.0F38 0xc4 - invalid. */
1227/* Opcode VEX.66.0F38 0xc4 - invalid. */
1228/* Opcode VEX.0F38 0xc5 - invalid. */
1229/* Opcode VEX.66.0F38 0xc5 - invalid. */
1230/* Opcode VEX.0F38 0xc6 - invalid. */
1231/* Opcode VEX.66.0F38 0xc6 - invalid. */
1232/* Opcode VEX.0F38 0xc7 - invalid. */
1233/* Opcode VEX.66.0F38 0xc7 - invalid. */
1234/** Opcode VEX.0F38 0xc8. */
1235FNIEMOP_STUB(iemOp_vsha1nexte_Vdq_Wdq);
1236/* Opcode VEX.66.0F38 0xc8 - invalid. */
1237/** Opcode VEX.0F38 0xc9. */
1238FNIEMOP_STUB(iemOp_vsha1msg1_Vdq_Wdq);
1239/* Opcode VEX.66.0F38 0xc9 - invalid. */
1240/** Opcode VEX.0F38 0xca. */
1241FNIEMOP_STUB(iemOp_vsha1msg2_Vdq_Wdq);
1242/* Opcode VEX.66.0F38 0xca - invalid. */
1243/** Opcode VEX.0F38 0xcb. */
1244FNIEMOP_STUB(iemOp_vsha256rnds2_Vdq_Wdq);
1245/* Opcode VEX.66.0F38 0xcb - invalid. */
1246/** Opcode VEX.0F38 0xcc. */
1247FNIEMOP_STUB(iemOp_vsha256msg1_Vdq_Wdq);
1248/* Opcode VEX.66.0F38 0xcc - invalid. */
1249/** Opcode VEX.0F38 0xcd. */
1250FNIEMOP_STUB(iemOp_vsha256msg2_Vdq_Wdq);
1251/* Opcode VEX.66.0F38 0xcd - invalid. */
1252/* Opcode VEX.0F38 0xce - invalid. */
1253/* Opcode VEX.66.0F38 0xce - invalid. */
1254/* Opcode VEX.0F38 0xcf - invalid. */
1255/* Opcode VEX.66.0F38 0xcf - invalid. */
1256
1257/* Opcode VEX.66.0F38 0xd0 - invalid. */
1258/* Opcode VEX.66.0F38 0xd1 - invalid. */
1259/* Opcode VEX.66.0F38 0xd2 - invalid. */
1260/* Opcode VEX.66.0F38 0xd3 - invalid. */
1261/* Opcode VEX.66.0F38 0xd4 - invalid. */
1262/* Opcode VEX.66.0F38 0xd5 - invalid. */
1263/* Opcode VEX.66.0F38 0xd6 - invalid. */
1264/* Opcode VEX.66.0F38 0xd7 - invalid. */
1265/* Opcode VEX.66.0F38 0xd8 - invalid. */
1266/* Opcode VEX.66.0F38 0xd9 - invalid. */
1267/* Opcode VEX.66.0F38 0xda - invalid. */
1268/** Opcode VEX.66.0F38 0xdb. */
1269FNIEMOP_STUB(iemOp_vaesimc_Vdq_Wdq);
1270/** Opcode VEX.66.0F38 0xdc. */
1271FNIEMOP_STUB(iemOp_vaesenc_Vdq_Wdq);
1272/** Opcode VEX.66.0F38 0xdd. */
1273FNIEMOP_STUB(iemOp_vaesenclast_Vdq_Wdq);
1274/** Opcode VEX.66.0F38 0xde. */
1275FNIEMOP_STUB(iemOp_vaesdec_Vdq_Wdq);
1276/** Opcode VEX.66.0F38 0xdf. */
1277FNIEMOP_STUB(iemOp_vaesdeclast_Vdq_Wdq);
1278
1279/* Opcode VEX.66.0F38 0xe0 - invalid. */
1280/* Opcode VEX.66.0F38 0xe1 - invalid. */
1281/* Opcode VEX.66.0F38 0xe2 - invalid. */
1282/* Opcode VEX.66.0F38 0xe3 - invalid. */
1283/* Opcode VEX.66.0F38 0xe4 - invalid. */
1284/* Opcode VEX.66.0F38 0xe5 - invalid. */
1285/* Opcode VEX.66.0F38 0xe6 - invalid. */
1286/* Opcode VEX.66.0F38 0xe7 - invalid. */
1287/* Opcode VEX.66.0F38 0xe8 - invalid. */
1288/* Opcode VEX.66.0F38 0xe9 - invalid. */
1289/* Opcode VEX.66.0F38 0xea - invalid. */
1290/* Opcode VEX.66.0F38 0xeb - invalid. */
1291/* Opcode VEX.66.0F38 0xec - invalid. */
1292/* Opcode VEX.66.0F38 0xed - invalid. */
1293/* Opcode VEX.66.0F38 0xee - invalid. */
1294/* Opcode VEX.66.0F38 0xef - invalid. */
1295
1296
1297/* Opcode VEX.0F38 0xf0 - invalid (legacy only). */
1298/* Opcode VEX.66.0F38 0xf0 - invalid (legacy only). */
1299/* Opcode VEX.F3.0F38 0xf0 - invalid. */
1300/* Opcode VEX.F2.0F38 0xf0 - invalid (legacy only). */
1301
1302/* Opcode VEX.0F38 0xf1 - invalid (legacy only). */
1303/* Opcode VEX.66.0F38 0xf1 - invalid (legacy only). */
1304/* Opcode VEX.F3.0F38 0xf1 - invalid. */
1305/* Opcode VEX.F2.0F38 0xf1 - invalid (legacy only). */
1306
1307/** Opcode VEX.0F38 0xf2 - ANDN (vex only). */
1308FNIEMOP_DEF(iemOp_andn_Gy_By_Ey)
1309{
1310 IEMOP_MNEMONIC3(VEX_RVM, ANDN, andn, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1311 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_PF);
1312 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1313 if (IEM_IS_MODRM_REG_MODE(bRm))
1314 {
1315 /*
1316 * Register, register.
1317 */
1318 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
1319 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1320 {
1321 IEM_MC_BEGIN(4, 0);
1322 IEM_MC_ARG(uint64_t *, pDst, 0);
1323 IEM_MC_ARG(uint64_t, uSrc1, 1);
1324 IEM_MC_ARG(uint64_t, uSrc2, 2);
1325 IEM_MC_ARG(uint32_t *, pEFlags, 3);
1326 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1327 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1328 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1329 IEM_MC_REF_EFLAGS(pEFlags);
1330 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
1331 pDst, uSrc1, uSrc2, pEFlags);
1332 IEM_MC_ADVANCE_RIP_AND_FINISH();
1333 IEM_MC_END();
1334 }
1335 else
1336 {
1337 IEM_MC_BEGIN(4, 0);
1338 IEM_MC_ARG(uint32_t *, pDst, 0);
1339 IEM_MC_ARG(uint32_t, uSrc1, 1);
1340 IEM_MC_ARG(uint32_t, uSrc2, 2);
1341 IEM_MC_ARG(uint32_t *, pEFlags, 3);
1342 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1343 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1344 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1345 IEM_MC_REF_EFLAGS(pEFlags);
1346 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
1347 pDst, uSrc1, uSrc2, pEFlags);
1348 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
1349 IEM_MC_ADVANCE_RIP_AND_FINISH();
1350 IEM_MC_END();
1351 }
1352 }
1353 else
1354 {
1355 /*
1356 * Register, memory.
1357 */
1358 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1359 {
1360 IEM_MC_BEGIN(4, 1);
1361 IEM_MC_ARG(uint64_t *, pDst, 0);
1362 IEM_MC_ARG(uint64_t, uSrc1, 1);
1363 IEM_MC_ARG(uint64_t, uSrc2, 2);
1364 IEM_MC_ARG(uint32_t *, pEFlags, 3);
1365 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1366 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1367 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
1368 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1369 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1370 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1371 IEM_MC_REF_EFLAGS(pEFlags);
1372 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
1373 pDst, uSrc1, uSrc2, pEFlags);
1374 IEM_MC_ADVANCE_RIP_AND_FINISH();
1375 IEM_MC_END();
1376 }
1377 else
1378 {
1379 IEM_MC_BEGIN(4, 1);
1380 IEM_MC_ARG(uint32_t *, pDst, 0);
1381 IEM_MC_ARG(uint32_t, uSrc1, 1);
1382 IEM_MC_ARG(uint32_t, uSrc2, 2);
1383 IEM_MC_ARG(uint32_t *, pEFlags, 3);
1384 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1385 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1386 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1);
1387 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1388 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1389 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1390 IEM_MC_REF_EFLAGS(pEFlags);
1391 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
1392 pDst, uSrc1, uSrc2, pEFlags);
1393 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
1394 IEM_MC_ADVANCE_RIP_AND_FINISH();
1395 IEM_MC_END();
1396 }
1397 }
1398}
1399
1400/* Opcode VEX.66.0F38 0xf2 - invalid. */
1401/* Opcode VEX.F3.0F38 0xf2 - invalid. */
1402/* Opcode VEX.F2.0F38 0xf2 - invalid. */
1403
1404
1405/* Opcode VEX.0F38 0xf3 - invalid. */
1406/* Opcode VEX.66.0F38 0xf3 - invalid. */
1407
1408/* Opcode VEX.F3.0F38 0xf3 /0 - invalid. */
1409
1410/** Body for the vex group 17 instructions. */
1411#define IEMOP_BODY_By_Ey(a_Instr) \
1412 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_PF); \
1413 if (IEM_IS_MODRM_REG_MODE(bRm)) \
1414 { \
1415 /* \
1416 * Register, register. \
1417 */ \
1418 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
1419 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1420 { \
1421 IEM_MC_BEGIN(3, 0); \
1422 IEM_MC_ARG(uint64_t *, pDst, 0); \
1423 IEM_MC_ARG(uint64_t, uSrc, 1); \
1424 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1425 IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1426 IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1427 IEM_MC_REF_EFLAGS(pEFlags); \
1428 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
1429 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
1430 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1431 IEM_MC_END(); \
1432 } \
1433 else \
1434 { \
1435 IEM_MC_BEGIN(3, 0); \
1436 IEM_MC_ARG(uint32_t *, pDst, 0); \
1437 IEM_MC_ARG(uint32_t, uSrc, 1); \
1438 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1439 IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1440 IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1441 IEM_MC_REF_EFLAGS(pEFlags); \
1442 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
1443 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
1444 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1445 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1446 IEM_MC_END(); \
1447 } \
1448 } \
1449 else \
1450 { \
1451 /* \
1452 * Register, memory. \
1453 */ \
1454 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1455 { \
1456 IEM_MC_BEGIN(3, 1); \
1457 IEM_MC_ARG(uint64_t *, pDst, 0); \
1458 IEM_MC_ARG(uint64_t, uSrc, 1); \
1459 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1460 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1461 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1462 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
1463 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1464 IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1465 IEM_MC_REF_EFLAGS(pEFlags); \
1466 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
1467 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
1468 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1469 IEM_MC_END(); \
1470 } \
1471 else \
1472 { \
1473 IEM_MC_BEGIN(3, 1); \
1474 IEM_MC_ARG(uint32_t *, pDst, 0); \
1475 IEM_MC_ARG(uint32_t, uSrc, 1); \
1476 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1477 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1478 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1479 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi1); \
1480 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1481 IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1482 IEM_MC_REF_EFLAGS(pEFlags); \
1483 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
1484 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
1485 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1486 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1487 IEM_MC_END(); \
1488 } \
1489 } \
1490 (void)0
1491
1492
1493/* Opcode VEX.F3.0F38 0xf3 /1. */
1494/** @opcode /1
1495 * @opmaps vexgrp17 */
1496FNIEMOP_DEF_1(iemOp_VGrp17_blsr_By_Ey, uint8_t, bRm)
1497{
1498 IEMOP_MNEMONIC2(VEX_VM, BLSR, blsr, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1499 IEMOP_BODY_By_Ey(blsr);
1500}
1501
1502
1503/* Opcode VEX.F3.0F38 0xf3 /2. */
1504/** @opcode /2
1505 * @opmaps vexgrp17 */
1506FNIEMOP_DEF_1(iemOp_VGrp17_blsmsk_By_Ey, uint8_t, bRm)
1507{
1508 IEMOP_MNEMONIC2(VEX_VM, BLSMSK, blsmsk, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1509 IEMOP_BODY_By_Ey(blsmsk);
1510}
1511
1512
1513/* Opcode VEX.F3.0F38 0xf3 /3. */
1514/** @opcode /3
1515 * @opmaps vexgrp17 */
1516FNIEMOP_DEF_1(iemOp_VGrp17_blsi_By_Ey, uint8_t, bRm)
1517{
1518 IEMOP_MNEMONIC2(VEX_VM, BLSI, blsi, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1519 IEMOP_BODY_By_Ey(blsi);
1520}
1521
1522
1523/* Opcode VEX.F3.0F38 0xf3 /4 - invalid. */
1524/* Opcode VEX.F3.0F38 0xf3 /5 - invalid. */
1525/* Opcode VEX.F3.0F38 0xf3 /6 - invalid. */
1526/* Opcode VEX.F3.0F38 0xf3 /7 - invalid. */
1527
1528/**
1529 * Group 17 jump table for the VEX.F3 variant.
1530 */
1531IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =
1532{
1533 /* /0 */ iemOp_InvalidWithRM,
1534 /* /1 */ iemOp_VGrp17_blsr_By_Ey,
1535 /* /2 */ iemOp_VGrp17_blsmsk_By_Ey,
1536 /* /3 */ iemOp_VGrp17_blsi_By_Ey,
1537 /* /4 */ iemOp_InvalidWithRM,
1538 /* /5 */ iemOp_InvalidWithRM,
1539 /* /6 */ iemOp_InvalidWithRM,
1540 /* /7 */ iemOp_InvalidWithRM
1541};
1542AssertCompile(RT_ELEMENTS(g_apfnVexGroup17_f3) == 8);
1543
1544/** Opcode VEX.F3.0F38 0xf3 - invalid (vex only - group 17). */
1545FNIEMOP_DEF(iemOp_VGrp17_f3)
1546{
1547 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1548 return FNIEMOP_CALL_1(g_apfnVexGroup17_f3[IEM_GET_MODRM_REG_8(bRm)], bRm);
1549}
1550
1551/* Opcode VEX.F2.0F38 0xf3 - invalid (vex only - group 17). */
1552
1553
1554/* Opcode VEX.0F38 0xf4 - invalid. */
1555/* Opcode VEX.66.0F38 0xf4 - invalid. */
1556/* Opcode VEX.F3.0F38 0xf4 - invalid. */
1557/* Opcode VEX.F2.0F38 0xf4 - invalid. */
1558
1559/** Body for BZHI, BEXTR, ++; assumes VEX.L must be 0. */
1560#define IEMOP_BODY_Gy_Ey_By(a_Instr, a_fFeatureMember, a_fUndefFlags) \
1561 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
1562 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1563 if (IEM_IS_MODRM_REG_MODE(bRm)) \
1564 { \
1565 /* \
1566 * Register, register. \
1567 */ \
1568 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
1569 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1570 { \
1571 IEM_MC_BEGIN(4, 0); \
1572 IEM_MC_ARG(uint64_t *, pDst, 0); \
1573 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1574 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1575 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1576 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1577 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1578 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1579 IEM_MC_REF_EFLAGS(pEFlags); \
1580 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1581 iemAImpl_ ## a_Instr ## _u64_fallback), \
1582 pDst, uSrc1, uSrc2, pEFlags); \
1583 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1584 IEM_MC_END(); \
1585 } \
1586 else \
1587 { \
1588 IEM_MC_BEGIN(4, 0); \
1589 IEM_MC_ARG(uint32_t *, pDst, 0); \
1590 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1591 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1592 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1593 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1594 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1595 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1596 IEM_MC_REF_EFLAGS(pEFlags); \
1597 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1598 iemAImpl_ ## a_Instr ## _u32_fallback), \
1599 pDst, uSrc1, uSrc2, pEFlags); \
1600 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1601 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1602 IEM_MC_END(); \
1603 } \
1604 } \
1605 else \
1606 { \
1607 /* \
1608 * Register, memory. \
1609 */ \
1610 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1611 { \
1612 IEM_MC_BEGIN(4, 1); \
1613 IEM_MC_ARG(uint64_t *, pDst, 0); \
1614 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1615 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1616 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1617 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1618 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1619 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
1620 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1621 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1622 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1623 IEM_MC_REF_EFLAGS(pEFlags); \
1624 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1625 iemAImpl_ ## a_Instr ## _u64_fallback), \
1626 pDst, uSrc1, uSrc2, pEFlags); \
1627 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1628 IEM_MC_END(); \
1629 } \
1630 else \
1631 { \
1632 IEM_MC_BEGIN(4, 1); \
1633 IEM_MC_ARG(uint32_t *, pDst, 0); \
1634 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1635 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1636 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1637 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1638 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1639 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
1640 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1641 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1642 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1643 IEM_MC_REF_EFLAGS(pEFlags); \
1644 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1645 iemAImpl_ ## a_Instr ## _u32_fallback), \
1646 pDst, uSrc1, uSrc2, pEFlags); \
1647 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1648 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1649 IEM_MC_END(); \
1650 } \
1651 } \
1652 (void)0
1653
1654/** Body for SARX, SHLX, SHRX; assumes VEX.L must be 0. */
1655#define IEMOP_BODY_Gy_Ey_By_NoEflags(a_Instr, a_fFeatureMember, a_fUndefFlags) \
1656 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
1657 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1658 if (IEM_IS_MODRM_REG_MODE(bRm)) \
1659 { \
1660 /* \
1661 * Register, register. \
1662 */ \
1663 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
1664 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1665 { \
1666 IEM_MC_BEGIN(3, 0); \
1667 IEM_MC_ARG(uint64_t *, pDst, 0); \
1668 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1669 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1670 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1671 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1672 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1673 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1674 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1675 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1676 IEM_MC_END(); \
1677 } \
1678 else \
1679 { \
1680 IEM_MC_BEGIN(3, 0); \
1681 IEM_MC_ARG(uint32_t *, pDst, 0); \
1682 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1683 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1684 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1685 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1686 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1687 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1688 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1689 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1690 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1691 IEM_MC_END(); \
1692 } \
1693 } \
1694 else \
1695 { \
1696 /* \
1697 * Register, memory. \
1698 */ \
1699 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1700 { \
1701 IEM_MC_BEGIN(3, 1); \
1702 IEM_MC_ARG(uint64_t *, pDst, 0); \
1703 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1704 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1705 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1706 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1707 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
1708 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1709 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1710 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1711 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1712 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1713 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1714 IEM_MC_END(); \
1715 } \
1716 else \
1717 { \
1718 IEM_MC_BEGIN(3, 1); \
1719 IEM_MC_ARG(uint32_t *, pDst, 0); \
1720 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1721 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1722 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1723 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1724 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
1725 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1726 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1727 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1728 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1729 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1730 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1731 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1732 IEM_MC_END(); \
1733 } \
1734 } \
1735 (void)0
1736
1737/** Opcode VEX.0F38 0xf5 (vex only). */
1738FNIEMOP_DEF(iemOp_bzhi_Gy_Ey_By)
1739{
1740 IEMOP_MNEMONIC3(VEX_RMV, BZHI, bzhi, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1741 IEMOP_BODY_Gy_Ey_By(bzhi, fBmi2, X86_EFL_AF | X86_EFL_PF);
1742}
1743
1744/* Opcode VEX.66.0F38 0xf5 - invalid. */
1745
1746/** Body for PDEP and PEXT (similar to ANDN, except no EFLAGS). */
1747#define IEMOP_BODY_Gy_By_Ey_NoEflags(a_Instr, a_fFeatureMember) \
1748 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1749 if (IEM_IS_MODRM_REG_MODE(bRm)) \
1750 { \
1751 /* \
1752 * Register, register. \
1753 */ \
1754 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
1755 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1756 { \
1757 IEM_MC_BEGIN(3, 0); \
1758 IEM_MC_ARG(uint64_t *, pDst, 0); \
1759 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1760 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1761 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1762 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1763 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1764 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1765 iemAImpl_ ## a_Instr ## _u64, \
1766 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1767 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1768 IEM_MC_END(); \
1769 } \
1770 else \
1771 { \
1772 IEM_MC_BEGIN(3, 0); \
1773 IEM_MC_ARG(uint32_t *, pDst, 0); \
1774 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1775 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1776 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1777 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1778 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1779 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1780 iemAImpl_ ## a_Instr ## _u32, \
1781 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1782 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1783 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1784 IEM_MC_END(); \
1785 } \
1786 } \
1787 else \
1788 { \
1789 /* \
1790 * Register, memory. \
1791 */ \
1792 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1793 { \
1794 IEM_MC_BEGIN(3, 1); \
1795 IEM_MC_ARG(uint64_t *, pDst, 0); \
1796 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1797 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1798 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1799 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1800 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
1801 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1802 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1803 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1804 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1805 iemAImpl_ ## a_Instr ## _u64, \
1806 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1807 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1808 IEM_MC_END(); \
1809 } \
1810 else \
1811 { \
1812 IEM_MC_BEGIN(3, 1); \
1813 IEM_MC_ARG(uint32_t *, pDst, 0); \
1814 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1815 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1816 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1817 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1818 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeatureMember); \
1819 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1820 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1821 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1822 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1823 iemAImpl_ ## a_Instr ## _u32, \
1824 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1825 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1826 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
1827 IEM_MC_END(); \
1828 } \
1829 } \
1830 (void)0
1831
1832
1833/** Opcode VEX.F3.0F38 0xf5 (vex only). */
1834FNIEMOP_DEF(iemOp_pext_Gy_By_Ey)
1835{
1836 IEMOP_MNEMONIC3(VEX_RVM, PEXT, pext, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1837 IEMOP_BODY_Gy_By_Ey_NoEflags(pext, fBmi2);
1838}
1839
1840
1841/** Opcode VEX.F2.0F38 0xf5 (vex only). */
1842FNIEMOP_DEF(iemOp_pdep_Gy_By_Ey)
1843{
1844 IEMOP_MNEMONIC3(VEX_RVM, PDEP, pdep, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1845 IEMOP_BODY_Gy_By_Ey_NoEflags(pdep, fBmi2);
1846}
1847
1848
1849/* Opcode VEX.0F38 0xf6 - invalid. */
1850/* Opcode VEX.66.0F38 0xf6 - invalid (legacy only). */
1851/* Opcode VEX.F3.0F38 0xf6 - invalid (legacy only). */
1852
1853
1854/** Opcode VEX.F2.0F38 0xf6 (vex only) */
1855FNIEMOP_DEF(iemOp_mulx_By_Gy_rDX_Ey)
1856{
1857 IEMOP_MNEMONIC4(VEX_RVM, MULX, mulx, Gy, By, Ey, rDX, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1858 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1859 if (IEM_IS_MODRM_REG_MODE(bRm))
1860 {
1861 /*
1862 * Register, register.
1863 */
1864 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
1865 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1866 {
1867 IEM_MC_BEGIN(4, 0);
1868 IEM_MC_ARG(uint64_t *, pDst1, 0);
1869 IEM_MC_ARG(uint64_t *, pDst2, 1);
1870 IEM_MC_ARG(uint64_t, uSrc1, 2);
1871 IEM_MC_ARG(uint64_t, uSrc2, 3);
1872 IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1873 IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1874 IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1875 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1876 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1877 pDst1, pDst2, uSrc1, uSrc2);
1878 IEM_MC_ADVANCE_RIP_AND_FINISH();
1879 IEM_MC_END();
1880 }
1881 else
1882 {
1883 IEM_MC_BEGIN(4, 0);
1884 IEM_MC_ARG(uint32_t *, pDst1, 0);
1885 IEM_MC_ARG(uint32_t *, pDst2, 1);
1886 IEM_MC_ARG(uint32_t, uSrc1, 2);
1887 IEM_MC_ARG(uint32_t, uSrc2, 3);
1888 IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1889 IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1890 IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1891 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1892 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1893 pDst1, pDst2, uSrc1, uSrc2);
1894 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1895 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1896 IEM_MC_ADVANCE_RIP_AND_FINISH();
1897 IEM_MC_END();
1898 }
1899 }
1900 else
1901 {
1902 /*
1903 * Register, memory.
1904 */
1905 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1906 {
1907 IEM_MC_BEGIN(4, 1);
1908 IEM_MC_ARG(uint64_t *, pDst1, 0);
1909 IEM_MC_ARG(uint64_t *, pDst2, 1);
1910 IEM_MC_ARG(uint64_t, uSrc1, 2);
1911 IEM_MC_ARG(uint64_t, uSrc2, 3);
1912 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1913 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1914 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
1915 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1916 IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1917 IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1918 IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1919 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1920 pDst1, pDst2, uSrc1, uSrc2);
1921 IEM_MC_ADVANCE_RIP_AND_FINISH();
1922 IEM_MC_END();
1923 }
1924 else
1925 {
1926 IEM_MC_BEGIN(4, 1);
1927 IEM_MC_ARG(uint32_t *, pDst1, 0);
1928 IEM_MC_ARG(uint32_t *, pDst2, 1);
1929 IEM_MC_ARG(uint32_t, uSrc1, 2);
1930 IEM_MC_ARG(uint32_t, uSrc2, 3);
1931 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1932 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1933 IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fBmi2);
1934 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1935 IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1936 IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1937 IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1938 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1939 pDst1, pDst2, uSrc1, uSrc2);
1940 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1941 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1942 IEM_MC_ADVANCE_RIP_AND_FINISH();
1943 IEM_MC_END();
1944 }
1945 }
1946}
1947
1948
1949/** Opcode VEX.0F38 0xf7 (vex only). */
1950FNIEMOP_DEF(iemOp_bextr_Gy_Ey_By)
1951{
1952 IEMOP_MNEMONIC3(VEX_RMV, BEXTR, bextr, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1953 IEMOP_BODY_Gy_Ey_By(bextr, fBmi1, X86_EFL_SF | X86_EFL_AF | X86_EFL_PF);
1954}
1955
1956
1957/** Opcode VEX.66.0F38 0xf7 (vex only). */
1958FNIEMOP_DEF(iemOp_shlx_Gy_Ey_By)
1959{
1960 IEMOP_MNEMONIC3(VEX_RMV, SHLX, shlx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1961 IEMOP_BODY_Gy_Ey_By_NoEflags(shlx, fBmi2, 0);
1962}
1963
1964
1965/** Opcode VEX.F3.0F38 0xf7 (vex only). */
1966FNIEMOP_DEF(iemOp_sarx_Gy_Ey_By)
1967{
1968 IEMOP_MNEMONIC3(VEX_RMV, SARX, sarx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1969 IEMOP_BODY_Gy_Ey_By_NoEflags(sarx, fBmi2, 0);
1970}
1971
1972
1973/** Opcode VEX.F2.0F38 0xf7 (vex only). */
1974FNIEMOP_DEF(iemOp_shrx_Gy_Ey_By)
1975{
1976 IEMOP_MNEMONIC3(VEX_RMV, SHRX, shrx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1977 IEMOP_BODY_Gy_Ey_By_NoEflags(shrx, fBmi2, 0);
1978}
1979
1980/* Opcode VEX.0F38 0xf8 - invalid. */
1981/* Opcode VEX.66.0F38 0xf8 - invalid. */
1982/* Opcode VEX.F3.0F38 0xf8 - invalid. */
1983/* Opcode VEX.F2.0F38 0xf8 - invalid. */
1984
1985/* Opcode VEX.0F38 0xf9 - invalid. */
1986/* Opcode VEX.66.0F38 0xf9 - invalid. */
1987/* Opcode VEX.F3.0F38 0xf9 - invalid. */
1988/* Opcode VEX.F2.0F38 0xf9 - invalid. */
1989
1990/* Opcode VEX.0F38 0xfa - invalid. */
1991/* Opcode VEX.66.0F38 0xfa - invalid. */
1992/* Opcode VEX.F3.0F38 0xfa - invalid. */
1993/* Opcode VEX.F2.0F38 0xfa - invalid. */
1994
1995/* Opcode VEX.0F38 0xfb - invalid. */
1996/* Opcode VEX.66.0F38 0xfb - invalid. */
1997/* Opcode VEX.F3.0F38 0xfb - invalid. */
1998/* Opcode VEX.F2.0F38 0xfb - invalid. */
1999
2000/* Opcode VEX.0F38 0xfc - invalid. */
2001/* Opcode VEX.66.0F38 0xfc - invalid. */
2002/* Opcode VEX.F3.0F38 0xfc - invalid. */
2003/* Opcode VEX.F2.0F38 0xfc - invalid. */
2004
2005/* Opcode VEX.0F38 0xfd - invalid. */
2006/* Opcode VEX.66.0F38 0xfd - invalid. */
2007/* Opcode VEX.F3.0F38 0xfd - invalid. */
2008/* Opcode VEX.F2.0F38 0xfd - invalid. */
2009
2010/* Opcode VEX.0F38 0xfe - invalid. */
2011/* Opcode VEX.66.0F38 0xfe - invalid. */
2012/* Opcode VEX.F3.0F38 0xfe - invalid. */
2013/* Opcode VEX.F2.0F38 0xfe - invalid. */
2014
2015/* Opcode VEX.0F38 0xff - invalid. */
2016/* Opcode VEX.66.0F38 0xff - invalid. */
2017/* Opcode VEX.F3.0F38 0xff - invalid. */
2018/* Opcode VEX.F2.0F38 0xff - invalid. */
2019
2020
2021/**
2022 * VEX opcode map \#2.
2023 *
2024 * @sa g_apfnThreeByte0f38
2025 */
2026IEM_STATIC const PFNIEMOP g_apfnVexMap2[] =
2027{
2028 /* no prefix, 066h prefix f3h prefix, f2h prefix */
2029 /* 0x00 */ iemOp_InvalidNeedRM, iemOp_vpshufb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2030 /* 0x01 */ iemOp_InvalidNeedRM, iemOp_vphaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2031 /* 0x02 */ iemOp_InvalidNeedRM, iemOp_vphaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2032 /* 0x03 */ iemOp_InvalidNeedRM, iemOp_vphaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2033 /* 0x04 */ iemOp_InvalidNeedRM, iemOp_vpmaddubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2034 /* 0x05 */ iemOp_InvalidNeedRM, iemOp_vphsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2035 /* 0x06 */ iemOp_InvalidNeedRM, iemOp_vphsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2036 /* 0x07 */ iemOp_InvalidNeedRM, iemOp_vphsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2037 /* 0x08 */ iemOp_InvalidNeedRM, iemOp_vpsignb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2038 /* 0x09 */ iemOp_InvalidNeedRM, iemOp_vpsignw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2039 /* 0x0a */ iemOp_InvalidNeedRM, iemOp_vpsignd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2040 /* 0x0b */ iemOp_InvalidNeedRM, iemOp_vpmulhrsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2041 /* 0x0c */ iemOp_InvalidNeedRM, iemOp_vpermilps_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2042 /* 0x0d */ iemOp_InvalidNeedRM, iemOp_vpermilpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2043 /* 0x0e */ iemOp_InvalidNeedRM, iemOp_vtestps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2044 /* 0x0f */ iemOp_InvalidNeedRM, iemOp_vtestpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2045
2046 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRM),
2047 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
2048 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
2049 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
2050 /* 0x14 */ IEMOP_X4(iemOp_InvalidNeedRM),
2051 /* 0x15 */ IEMOP_X4(iemOp_InvalidNeedRM),
2052 /* 0x16 */ iemOp_InvalidNeedRM, iemOp_vpermps_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2053 /* 0x17 */ iemOp_InvalidNeedRM, iemOp_vptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2054 /* 0x18 */ iemOp_InvalidNeedRM, iemOp_vbroadcastss_Vx_Wd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2055 /* 0x19 */ iemOp_InvalidNeedRM, iemOp_vbroadcastsd_Vqq_Wq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2056 /* 0x1a */ iemOp_InvalidNeedRM, iemOp_vbroadcastf128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2057 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
2058 /* 0x1c */ iemOp_InvalidNeedRM, iemOp_vpabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2059 /* 0x1d */ iemOp_InvalidNeedRM, iemOp_vpabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2060 /* 0x1e */ iemOp_InvalidNeedRM, iemOp_vpabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2061 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
2062
2063 /* 0x20 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2064 /* 0x21 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2065 /* 0x22 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2066 /* 0x23 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2067 /* 0x24 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2068 /* 0x25 */ iemOp_InvalidNeedRM, iemOp_vpmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2069 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
2070 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
2071 /* 0x28 */ iemOp_InvalidNeedRM, iemOp_vpmuldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2072 /* 0x29 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2073 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_vmovntdqa_Vx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2074 /* 0x2b */ iemOp_InvalidNeedRM, iemOp_vpackusdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2075 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2076 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2077 /* 0x2e */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2078 /* 0x2f */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2079
2080 /* 0x30 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2081 /* 0x31 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2082 /* 0x32 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2083 /* 0x33 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2084 /* 0x34 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2085 /* 0x35 */ iemOp_InvalidNeedRM, iemOp_vpmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2086 /* 0x36 */ iemOp_InvalidNeedRM, iemOp_vpermd_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2087 /* 0x37 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2088 /* 0x38 */ iemOp_InvalidNeedRM, iemOp_vpminsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2089 /* 0x39 */ iemOp_InvalidNeedRM, iemOp_vpminsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2090 /* 0x3a */ iemOp_InvalidNeedRM, iemOp_vpminuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2091 /* 0x3b */ iemOp_InvalidNeedRM, iemOp_vpminud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2092 /* 0x3c */ iemOp_InvalidNeedRM, iemOp_vpmaxsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2093 /* 0x3d */ iemOp_InvalidNeedRM, iemOp_vpmaxsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2094 /* 0x3e */ iemOp_InvalidNeedRM, iemOp_vpmaxuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2095 /* 0x3f */ iemOp_InvalidNeedRM, iemOp_vpmaxud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2096
2097 /* 0x40 */ iemOp_InvalidNeedRM, iemOp_vpmulld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2098 /* 0x41 */ iemOp_InvalidNeedRM, iemOp_vphminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2099 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
2100 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
2101 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
2102 /* 0x45 */ iemOp_InvalidNeedRM, iemOp_vpsrlvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2103 /* 0x46 */ iemOp_InvalidNeedRM, iemOp_vsravd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2104 /* 0x47 */ iemOp_InvalidNeedRM, iemOp_vpsllvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2105 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
2106 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
2107 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
2108 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
2109 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
2110 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
2111 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
2112 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
2113
2114 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
2115 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
2116 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
2117 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
2118 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
2119 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
2120 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
2121 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
2122 /* 0x58 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2123 /* 0x59 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2124 /* 0x5a */ iemOp_InvalidNeedRM, iemOp_vbroadcasti128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2125 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
2126 /* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
2127 /* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
2128 /* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
2129 /* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
2130
2131 /* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
2132 /* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
2133 /* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
2134 /* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
2135 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
2136 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
2137 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
2138 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
2139 /* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
2140 /* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
2141 /* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
2142 /* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
2143 /* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
2144 /* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
2145 /* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
2146 /* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
2147
2148 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
2149 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
2150 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
2151 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
2152 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
2153 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
2154 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
2155 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
2156 /* 0x78 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2157 /* 0x79 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2158 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
2159 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
2160 /* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
2161 /* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
2162 /* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
2163 /* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
2164
2165 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
2166 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
2167 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
2168 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
2169 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
2170 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
2171 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
2172 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
2173 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
2174 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
2175 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
2176 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
2177 /* 0x8c */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2178 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
2179 /* 0x8e */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Mx_Vx_Hx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2180 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
2181
2182 /* 0x90 */ iemOp_InvalidNeedRM, iemOp_vgatherdd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2183 /* 0x91 */ iemOp_InvalidNeedRM, iemOp_vgatherqd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2184 /* 0x92 */ iemOp_InvalidNeedRM, iemOp_vgatherdps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2185 /* 0x93 */ iemOp_InvalidNeedRM, iemOp_vgatherqps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2186 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
2187 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
2188 /* 0x96 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub132ps_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2189 /* 0x97 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2190 /* 0x98 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2191 /* 0x99 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2192 /* 0x9a */ iemOp_InvalidNeedRM, iemOp_vfmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2193 /* 0x9b */ iemOp_InvalidNeedRM, iemOp_vfmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2194 /* 0x9c */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2195 /* 0x9d */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2196 /* 0x9e */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2197 /* 0x9f */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2198
2199 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2200 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2201 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2202 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2203 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2204 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2205 /* 0xa6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2206 /* 0xa7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2207 /* 0xa8 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2208 /* 0xa9 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2209 /* 0xaa */ iemOp_InvalidNeedRM, iemOp_vfmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2210 /* 0xab */ iemOp_InvalidNeedRM, iemOp_vfmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2211 /* 0xac */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2212 /* 0xad */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2213 /* 0xae */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2214 /* 0xaf */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2215
2216 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2217 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2218 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2219 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2220 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2221 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2222 /* 0xb6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2223 /* 0xb7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2224 /* 0xb8 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2225 /* 0xb9 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2226 /* 0xba */ iemOp_InvalidNeedRM, iemOp_vfmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2227 /* 0xbb */ iemOp_InvalidNeedRM, iemOp_vfmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2228 /* 0xbc */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2229 /* 0xbd */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2230 /* 0xbe */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2231 /* 0xbf */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2232
2233 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2234 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2235 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2236 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2237 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2238 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2239 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2240 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2241 /* 0xc8 */ iemOp_vsha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2242 /* 0xc9 */ iemOp_vsha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2243 /* 0xca */ iemOp_vsha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2244 /* 0xcb */ iemOp_vsha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2245 /* 0xcc */ iemOp_vsha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2246 /* 0xcd */ iemOp_vsha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2247 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
2248 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
2249
2250 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2251 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2252 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2253 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2254 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2255 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2256 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2257 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2258 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2259 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2260 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
2261 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vaesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2262 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vaesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2263 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vaesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2264 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vaesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2265 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vaesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2266
2267 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2268 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2269 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2270 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2271 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2272 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2273 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2274 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2275 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2276 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2277 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
2278 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
2279 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
2280 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
2281 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
2282 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
2283
2284 /* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2285 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2286 /* 0xf2 */ iemOp_andn_Gy_By_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2287 /* 0xf3 */ iemOp_VGrp17_f3, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2288 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2289 /* 0xf5 */ iemOp_bzhi_Gy_Ey_By, iemOp_InvalidNeedRM, iemOp_pext_Gy_By_Ey, iemOp_pdep_Gy_By_Ey,
2290 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_mulx_By_Gy_rDX_Ey,
2291 /* 0xf7 */ iemOp_bextr_Gy_Ey_By, iemOp_shlx_Gy_Ey_By, iemOp_sarx_Gy_Ey_By, iemOp_shrx_Gy_Ey_By,
2292 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2293 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2294 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
2295 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
2296 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
2297 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
2298 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
2299 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
2300};
2301AssertCompile(RT_ELEMENTS(g_apfnVexMap2) == 1024);
2302
2303/** @} */
2304
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