VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h@ 95308

Last change on this file since 95308 was 95308, checked in by vboxsync, 2 years ago

VMM/IEM: Implemented ANDN, BEXTR, SHLX, SARX, SHRX, RORX, TZCNT, and LZCNT. Fixed long-mod bug in 32-bit version of BSR and BSF (would clear the upper 32 bits of the destination register when ZF=1). bugref:9898

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File size: 57.4 KB
Line 
1/* $Id: IEMAllInstructionsVexMap2.cpp.h 95308 2022-06-19 20:40:26Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstructionsThree0f38.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2022 Oracle Corporation
11 *
12 * This file is part of VirtualBox Open Source Edition (OSE), as
13 * available from http://www.virtualbox.org. This file is free software;
14 * you can redistribute it and/or modify it under the terms of the GNU
15 * General Public License (GPL) as published by the Free Software
16 * Foundation, in version 2 as it comes in the "COPYING" file of the
17 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19 */
20
21
22/** @name VEX Opcode Map 2
23 * @{
24 */
25
26/* Opcode VEX.0F38 0x00 - invalid. */
27/** Opcode VEX.66.0F38 0x00. */
28FNIEMOP_STUB(iemOp_vpshufb_Vx_Hx_Wx);
29/* Opcode VEX.0F38 0x01 - invalid. */
30/** Opcode VEX.66.0F38 0x01. */
31FNIEMOP_STUB(iemOp_vphaddw_Vx_Hx_Wx);
32/* Opcode VEX.0F38 0x02 - invalid. */
33/** Opcode VEX.66.0F38 0x02. */
34FNIEMOP_STUB(iemOp_vphaddd_Vx_Hx_Wx);
35/* Opcode VEX.0F38 0x03 - invalid. */
36/** Opcode VEX.66.0F38 0x03. */
37FNIEMOP_STUB(iemOp_vphaddsw_Vx_Hx_Wx);
38/* Opcode VEX.0F38 0x04 - invalid. */
39/** Opcode VEX.66.0F38 0x04. */
40FNIEMOP_STUB(iemOp_vpmaddubsw_Vx_Hx_Wx);
41/* Opcode VEX.0F38 0x05 - invalid. */
42/** Opcode VEX.66.0F38 0x05. */
43FNIEMOP_STUB(iemOp_vphsubw_Vx_Hx_Wx);
44/* Opcode VEX.0F38 0x06 - invalid. */
45/** Opcode VEX.66.0F38 0x06. */
46FNIEMOP_STUB(iemOp_vphsubdq_Vx_Hx_Wx);
47/* Opcode VEX.0F38 0x07 - invalid. */
48/** Opcode VEX.66.0F38 0x07. */
49FNIEMOP_STUB(iemOp_vphsubsw_Vx_Hx_Wx);
50/* Opcode VEX.0F38 0x08 - invalid. */
51/** Opcode VEX.66.0F38 0x08. */
52FNIEMOP_STUB(iemOp_vpsignb_Vx_Hx_Wx);
53/* Opcode VEX.0F38 0x09 - invalid. */
54/** Opcode VEX.66.0F38 0x09. */
55FNIEMOP_STUB(iemOp_vpsignw_Vx_Hx_Wx);
56/* Opcode VEX.0F38 0x0a - invalid. */
57/** Opcode VEX.66.0F38 0x0a. */
58FNIEMOP_STUB(iemOp_vpsignd_Vx_Hx_Wx);
59/* Opcode VEX.0F38 0x0b - invalid. */
60/** Opcode VEX.66.0F38 0x0b. */
61FNIEMOP_STUB(iemOp_vpmulhrsw_Vx_Hx_Wx);
62/* Opcode VEX.0F38 0x0c - invalid. */
63/** Opcode VEX.66.0F38 0x0c. */
64FNIEMOP_STUB(iemOp_vpermilps_Vx_Hx_Wx);
65/* Opcode VEX.0F38 0x0d - invalid. */
66/** Opcode VEX.66.0F38 0x0d. */
67FNIEMOP_STUB(iemOp_vpermilpd_Vx_Hx_Wx);
68/* Opcode VEX.0F38 0x0e - invalid. */
69/** Opcode VEX.66.0F38 0x0e. */
70FNIEMOP_STUB(iemOp_vtestps_Vx_Wx);
71/* Opcode VEX.0F38 0x0f - invalid. */
72/** Opcode VEX.66.0F38 0x0f. */
73FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx);
74
75
76/* Opcode VEX.0F38 0x10 - invalid */
77/* Opcode VEX.66.0F38 0x10 - invalid (legacy only). */
78/* Opcode VEX.0F38 0x11 - invalid */
79/* Opcode VEX.66.0F38 0x11 - invalid */
80/* Opcode VEX.0F38 0x12 - invalid */
81/* Opcode VEX.66.0F38 0x12 - invalid */
82/* Opcode VEX.0F38 0x13 - invalid */
83/* Opcode VEX.66.0F38 0x13 - invalid (vex only). */
84/* Opcode VEX.0F38 0x14 - invalid */
85/* Opcode VEX.66.0F38 0x14 - invalid (legacy only). */
86/* Opcode VEX.0F38 0x15 - invalid */
87/* Opcode VEX.66.0F38 0x15 - invalid (legacy only). */
88/* Opcode VEX.0F38 0x16 - invalid */
89/** Opcode VEX.66.0F38 0x16. */
90FNIEMOP_STUB(iemOp_vpermps_Vqq_Hqq_Wqq);
91/* Opcode VEX.0F38 0x17 - invalid */
92/** Opcode VEX.66.0F38 0x17 - invalid */
93FNIEMOP_STUB(iemOp_vptest_Vx_Wx);
94/* Opcode VEX.0F38 0x18 - invalid */
95/** Opcode VEX.66.0F38 0x18. */
96FNIEMOP_STUB(iemOp_vbroadcastss_Vx_Wd);
97/* Opcode VEX.0F38 0x19 - invalid */
98/** Opcode VEX.66.0F38 0x19. */
99FNIEMOP_STUB(iemOp_vbroadcastsd_Vqq_Wq);
100/* Opcode VEX.0F38 0x1a - invalid */
101/** Opcode VEX.66.0F38 0x1a. */
102FNIEMOP_STUB(iemOp_vbroadcastf128_Vqq_Mdq);
103/* Opcode VEX.0F38 0x1b - invalid */
104/* Opcode VEX.66.0F38 0x1b - invalid */
105/* Opcode VEX.0F38 0x1c - invalid. */
106/** Opcode VEX.66.0F38 0x1c. */
107FNIEMOP_STUB(iemOp_vpabsb_Vx_Wx);
108/* Opcode VEX.0F38 0x1d - invalid. */
109/** Opcode VEX.66.0F38 0x1d. */
110FNIEMOP_STUB(iemOp_vpabsw_Vx_Wx);
111/* Opcode VEX.0F38 0x1e - invalid. */
112/** Opcode VEX.66.0F38 0x1e. */
113FNIEMOP_STUB(iemOp_vpabsd_Vx_Wx);
114/* Opcode VEX.0F38 0x1f - invalid */
115/* Opcode VEX.66.0F38 0x1f - invalid */
116
117
118/** Opcode VEX.66.0F38 0x20. */
119FNIEMOP_STUB(iemOp_vpmovsxbw_Vx_UxMq);
120/** Opcode VEX.66.0F38 0x21. */
121FNIEMOP_STUB(iemOp_vpmovsxbd_Vx_UxMd);
122/** Opcode VEX.66.0F38 0x22. */
123FNIEMOP_STUB(iemOp_vpmovsxbq_Vx_UxMw);
124/** Opcode VEX.66.0F38 0x23. */
125FNIEMOP_STUB(iemOp_vpmovsxwd_Vx_UxMq);
126/** Opcode VEX.66.0F38 0x24. */
127FNIEMOP_STUB(iemOp_vpmovsxwq_Vx_UxMd);
128/** Opcode VEX.66.0F38 0x25. */
129FNIEMOP_STUB(iemOp_vpmovsxdq_Vx_UxMq);
130/* Opcode VEX.66.0F38 0x26 - invalid */
131/* Opcode VEX.66.0F38 0x27 - invalid */
132/** Opcode VEX.66.0F38 0x28. */
133FNIEMOP_STUB(iemOp_vpmuldq_Vx_Hx_Wx);
134/** Opcode VEX.66.0F38 0x29. */
135FNIEMOP_STUB(iemOp_vpcmpeqq_Vx_Hx_Wx);
136
137
138FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
139{
140 Assert(pVCpu->iem.s.uVexLength <= 1);
141 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
142 if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
143 {
144 if (pVCpu->iem.s.uVexLength == 0)
145 {
146 /**
147 * @opcode 0x2a
148 * @opcodesub !11 mr/reg vex.l=0
149 * @oppfx 0x66
150 * @opcpuid avx
151 * @opgroup og_avx_cachect
152 * @opxcpttype 1
153 * @optest op1=-1 op2=2 -> op1=2
154 * @optest op1=0 op2=-42 -> op1=-42
155 */
156 /* 128-bit: Memory, register. */
157 IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
158 DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
159 IEM_MC_BEGIN(0, 2);
160 IEM_MC_LOCAL(RTUINT128U, uSrc);
161 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
162
163 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
164 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
165 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
166 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
167
168 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
169 IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
170
171 IEM_MC_ADVANCE_RIP();
172 IEM_MC_END();
173 }
174 else
175 {
176 /**
177 * @opdone
178 * @opcode 0x2a
179 * @opcodesub !11 mr/reg vex.l=1
180 * @oppfx 0x66
181 * @opcpuid avx2
182 * @opgroup og_avx2_cachect
183 * @opxcpttype 1
184 * @optest op1=-1 op2=2 -> op1=2
185 * @optest op1=0 op2=-42 -> op1=-42
186 */
187 /* 256-bit: Memory, register. */
188 IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
189 DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
190 IEM_MC_BEGIN(0, 2);
191 IEM_MC_LOCAL(RTUINT256U, uSrc);
192 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
193
194 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
195 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
196 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
197 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
198
199 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
200 IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
201
202 IEM_MC_ADVANCE_RIP();
203 IEM_MC_END();
204 }
205 return VINF_SUCCESS;
206 }
207
208 /**
209 * @opdone
210 * @opmnemonic udvex660f382arg
211 * @opcode 0x2a
212 * @opcodesub 11 mr/reg
213 * @oppfx 0x66
214 * @opunused immediate
215 * @opcpuid avx
216 * @optest ->
217 */
218 return IEMOP_RAISE_INVALID_OPCODE();
219
220}
221
222
223/** Opcode VEX.66.0F38 0x2b. */
224FNIEMOP_STUB(iemOp_vpackusdw_Vx_Hx_Wx);
225/** Opcode VEX.66.0F38 0x2c. */
226FNIEMOP_STUB(iemOp_vmaskmovps_Vx_Hx_Mx);
227/** Opcode VEX.66.0F38 0x2d. */
228FNIEMOP_STUB(iemOp_vmaskmovpd_Vx_Hx_Mx);
229/** Opcode VEX.66.0F38 0x2e. */
230FNIEMOP_STUB(iemOp_vmaskmovps_Mx_Hx_Vx);
231/** Opcode VEX.66.0F38 0x2f. */
232FNIEMOP_STUB(iemOp_vmaskmovpd_Mx_Hx_Vx);
233
234/** Opcode VEX.66.0F38 0x30. */
235FNIEMOP_STUB(iemOp_vpmovzxbw_Vx_UxMq);
236/** Opcode VEX.66.0F38 0x31. */
237FNIEMOP_STUB(iemOp_vpmovzxbd_Vx_UxMd);
238/** Opcode VEX.66.0F38 0x32. */
239FNIEMOP_STUB(iemOp_vpmovzxbq_Vx_UxMw);
240/** Opcode VEX.66.0F38 0x33. */
241FNIEMOP_STUB(iemOp_vpmovzxwd_Vx_UxMq);
242/** Opcode VEX.66.0F38 0x34. */
243FNIEMOP_STUB(iemOp_vpmovzxwq_Vx_UxMd);
244/** Opcode VEX.66.0F38 0x35. */
245FNIEMOP_STUB(iemOp_vpmovzxdq_Vx_UxMq);
246/* Opcode VEX.66.0F38 0x36. */
247FNIEMOP_STUB(iemOp_vpermd_Vqq_Hqq_Wqq);
248/** Opcode VEX.66.0F38 0x37. */
249FNIEMOP_STUB(iemOp_vpcmpgtq_Vx_Hx_Wx);
250/** Opcode VEX.66.0F38 0x38. */
251FNIEMOP_STUB(iemOp_vpminsb_Vx_Hx_Wx);
252/** Opcode VEX.66.0F38 0x39. */
253FNIEMOP_STUB(iemOp_vpminsd_Vx_Hx_Wx);
254/** Opcode VEX.66.0F38 0x3a. */
255FNIEMOP_STUB(iemOp_vpminuw_Vx_Hx_Wx);
256/** Opcode VEX.66.0F38 0x3b. */
257FNIEMOP_STUB(iemOp_vpminud_Vx_Hx_Wx);
258/** Opcode VEX.66.0F38 0x3c. */
259FNIEMOP_STUB(iemOp_vpmaxsb_Vx_Hx_Wx);
260/** Opcode VEX.66.0F38 0x3d. */
261FNIEMOP_STUB(iemOp_vpmaxsd_Vx_Hx_Wx);
262/** Opcode VEX.66.0F38 0x3e. */
263FNIEMOP_STUB(iemOp_vpmaxuw_Vx_Hx_Wx);
264/** Opcode VEX.66.0F38 0x3f. */
265FNIEMOP_STUB(iemOp_vpmaxud_Vx_Hx_Wx);
266
267
268/** Opcode VEX.66.0F38 0x40. */
269FNIEMOP_STUB(iemOp_vpmulld_Vx_Hx_Wx);
270/** Opcode VEX.66.0F38 0x41. */
271FNIEMOP_STUB(iemOp_vphminposuw_Vdq_Wdq);
272/* Opcode VEX.66.0F38 0x42 - invalid. */
273/* Opcode VEX.66.0F38 0x43 - invalid. */
274/* Opcode VEX.66.0F38 0x44 - invalid. */
275/** Opcode VEX.66.0F38 0x45. */
276FNIEMOP_STUB(iemOp_vpsrlvd_q_Vx_Hx_Wx);
277/** Opcode VEX.66.0F38 0x46. */
278FNIEMOP_STUB(iemOp_vsravd_Vx_Hx_Wx);
279/** Opcode VEX.66.0F38 0x47. */
280FNIEMOP_STUB(iemOp_vpsllvd_q_Vx_Hx_Wx);
281/* Opcode VEX.66.0F38 0x48 - invalid. */
282/* Opcode VEX.66.0F38 0x49 - invalid. */
283/* Opcode VEX.66.0F38 0x4a - invalid. */
284/* Opcode VEX.66.0F38 0x4b - invalid. */
285/* Opcode VEX.66.0F38 0x4c - invalid. */
286/* Opcode VEX.66.0F38 0x4d - invalid. */
287/* Opcode VEX.66.0F38 0x4e - invalid. */
288/* Opcode VEX.66.0F38 0x4f - invalid. */
289
290/* Opcode VEX.66.0F38 0x50 - invalid. */
291/* Opcode VEX.66.0F38 0x51 - invalid. */
292/* Opcode VEX.66.0F38 0x52 - invalid. */
293/* Opcode VEX.66.0F38 0x53 - invalid. */
294/* Opcode VEX.66.0F38 0x54 - invalid. */
295/* Opcode VEX.66.0F38 0x55 - invalid. */
296/* Opcode VEX.66.0F38 0x56 - invalid. */
297/* Opcode VEX.66.0F38 0x57 - invalid. */
298/** Opcode VEX.66.0F38 0x58. */
299FNIEMOP_STUB(iemOp_vpbroadcastd_Vx_Wx);
300/** Opcode VEX.66.0F38 0x59. */
301FNIEMOP_STUB(iemOp_vpbroadcastq_Vx_Wx);
302/** Opcode VEX.66.0F38 0x5a. */
303FNIEMOP_STUB(iemOp_vbroadcasti128_Vqq_Mdq);
304/* Opcode VEX.66.0F38 0x5b - invalid. */
305/* Opcode VEX.66.0F38 0x5c - invalid. */
306/* Opcode VEX.66.0F38 0x5d - invalid. */
307/* Opcode VEX.66.0F38 0x5e - invalid. */
308/* Opcode VEX.66.0F38 0x5f - invalid. */
309
310/* Opcode VEX.66.0F38 0x60 - invalid. */
311/* Opcode VEX.66.0F38 0x61 - invalid. */
312/* Opcode VEX.66.0F38 0x62 - invalid. */
313/* Opcode VEX.66.0F38 0x63 - invalid. */
314/* Opcode VEX.66.0F38 0x64 - invalid. */
315/* Opcode VEX.66.0F38 0x65 - invalid. */
316/* Opcode VEX.66.0F38 0x66 - invalid. */
317/* Opcode VEX.66.0F38 0x67 - invalid. */
318/* Opcode VEX.66.0F38 0x68 - invalid. */
319/* Opcode VEX.66.0F38 0x69 - invalid. */
320/* Opcode VEX.66.0F38 0x6a - invalid. */
321/* Opcode VEX.66.0F38 0x6b - invalid. */
322/* Opcode VEX.66.0F38 0x6c - invalid. */
323/* Opcode VEX.66.0F38 0x6d - invalid. */
324/* Opcode VEX.66.0F38 0x6e - invalid. */
325/* Opcode VEX.66.0F38 0x6f - invalid. */
326
327/* Opcode VEX.66.0F38 0x70 - invalid. */
328/* Opcode VEX.66.0F38 0x71 - invalid. */
329/* Opcode VEX.66.0F38 0x72 - invalid. */
330/* Opcode VEX.66.0F38 0x73 - invalid. */
331/* Opcode VEX.66.0F38 0x74 - invalid. */
332/* Opcode VEX.66.0F38 0x75 - invalid. */
333/* Opcode VEX.66.0F38 0x76 - invalid. */
334/* Opcode VEX.66.0F38 0x77 - invalid. */
335/** Opcode VEX.66.0F38 0x78. */
336FNIEMOP_STUB(iemOp_vpboardcastb_Vx_Wx);
337/** Opcode VEX.66.0F38 0x79. */
338FNIEMOP_STUB(iemOp_vpboardcastw_Vx_Wx);
339/* Opcode VEX.66.0F38 0x7a - invalid. */
340/* Opcode VEX.66.0F38 0x7b - invalid. */
341/* Opcode VEX.66.0F38 0x7c - invalid. */
342/* Opcode VEX.66.0F38 0x7d - invalid. */
343/* Opcode VEX.66.0F38 0x7e - invalid. */
344/* Opcode VEX.66.0F38 0x7f - invalid. */
345
346/* Opcode VEX.66.0F38 0x80 - invalid (legacy only). */
347/* Opcode VEX.66.0F38 0x81 - invalid (legacy only). */
348/* Opcode VEX.66.0F38 0x82 - invalid (legacy only). */
349/* Opcode VEX.66.0F38 0x83 - invalid. */
350/* Opcode VEX.66.0F38 0x84 - invalid. */
351/* Opcode VEX.66.0F38 0x85 - invalid. */
352/* Opcode VEX.66.0F38 0x86 - invalid. */
353/* Opcode VEX.66.0F38 0x87 - invalid. */
354/* Opcode VEX.66.0F38 0x88 - invalid. */
355/* Opcode VEX.66.0F38 0x89 - invalid. */
356/* Opcode VEX.66.0F38 0x8a - invalid. */
357/* Opcode VEX.66.0F38 0x8b - invalid. */
358/** Opcode VEX.66.0F38 0x8c. */
359FNIEMOP_STUB(iemOp_vpmaskmovd_q_Vx_Hx_Mx);
360/* Opcode VEX.66.0F38 0x8d - invalid. */
361/** Opcode VEX.66.0F38 0x8e. */
362FNIEMOP_STUB(iemOp_vpmaskmovd_q_Mx_Vx_Hx);
363/* Opcode VEX.66.0F38 0x8f - invalid. */
364
365/** Opcode VEX.66.0F38 0x90 (vex only). */
366FNIEMOP_STUB(iemOp_vgatherdd_q_Vx_Hx_Wx);
367/** Opcode VEX.66.0F38 0x91 (vex only). */
368FNIEMOP_STUB(iemOp_vgatherqd_q_Vx_Hx_Wx);
369/** Opcode VEX.66.0F38 0x92 (vex only). */
370FNIEMOP_STUB(iemOp_vgatherdps_d_Vx_Hx_Wx);
371/** Opcode VEX.66.0F38 0x93 (vex only). */
372FNIEMOP_STUB(iemOp_vgatherqps_d_Vx_Hx_Wx);
373/* Opcode VEX.66.0F38 0x94 - invalid. */
374/* Opcode VEX.66.0F38 0x95 - invalid. */
375/** Opcode VEX.66.0F38 0x96 (vex only). */
376FNIEMOP_STUB(iemOp_vfmaddsub132ps_q_Vx_Hx_Wx);
377/** Opcode VEX.66.0F38 0x97 (vex only). */
378FNIEMOP_STUB(iemOp_vfmsubadd132ps_d_Vx_Hx_Wx);
379/** Opcode VEX.66.0F38 0x98 (vex only). */
380FNIEMOP_STUB(iemOp_vfmadd132ps_d_Vx_Hx_Wx);
381/** Opcode VEX.66.0F38 0x99 (vex only). */
382FNIEMOP_STUB(iemOp_vfmadd132ss_d_Vx_Hx_Wx);
383/** Opcode VEX.66.0F38 0x9a (vex only). */
384FNIEMOP_STUB(iemOp_vfmsub132ps_d_Vx_Hx_Wx);
385/** Opcode VEX.66.0F38 0x9b (vex only). */
386FNIEMOP_STUB(iemOp_vfmsub132ss_d_Vx_Hx_Wx);
387/** Opcode VEX.66.0F38 0x9c (vex only). */
388FNIEMOP_STUB(iemOp_vfnmadd132ps_d_Vx_Hx_Wx);
389/** Opcode VEX.66.0F38 0x9d (vex only). */
390FNIEMOP_STUB(iemOp_vfnmadd132ss_d_Vx_Hx_Wx);
391/** Opcode VEX.66.0F38 0x9e (vex only). */
392FNIEMOP_STUB(iemOp_vfnmsub132ps_d_Vx_Hx_Wx);
393/** Opcode VEX.66.0F38 0x9f (vex only). */
394FNIEMOP_STUB(iemOp_vfnmsub132ss_d_Vx_Hx_Wx);
395
396/* Opcode VEX.66.0F38 0xa0 - invalid. */
397/* Opcode VEX.66.0F38 0xa1 - invalid. */
398/* Opcode VEX.66.0F38 0xa2 - invalid. */
399/* Opcode VEX.66.0F38 0xa3 - invalid. */
400/* Opcode VEX.66.0F38 0xa4 - invalid. */
401/* Opcode VEX.66.0F38 0xa5 - invalid. */
402/** Opcode VEX.66.0F38 0xa6 (vex only). */
403FNIEMOP_STUB(iemOp_vfmaddsub213ps_d_Vx_Hx_Wx);
404/** Opcode VEX.66.0F38 0xa7 (vex only). */
405FNIEMOP_STUB(iemOp_vfmsubadd213ps_d_Vx_Hx_Wx);
406/** Opcode VEX.66.0F38 0xa8 (vex only). */
407FNIEMOP_STUB(iemOp_vfmadd213ps_d_Vx_Hx_Wx);
408/** Opcode VEX.66.0F38 0xa9 (vex only). */
409FNIEMOP_STUB(iemOp_vfmadd213ss_d_Vx_Hx_Wx);
410/** Opcode VEX.66.0F38 0xaa (vex only). */
411FNIEMOP_STUB(iemOp_vfmsub213ps_d_Vx_Hx_Wx);
412/** Opcode VEX.66.0F38 0xab (vex only). */
413FNIEMOP_STUB(iemOp_vfmsub213ss_d_Vx_Hx_Wx);
414/** Opcode VEX.66.0F38 0xac (vex only). */
415FNIEMOP_STUB(iemOp_vfnmadd213ps_d_Vx_Hx_Wx);
416/** Opcode VEX.66.0F38 0xad (vex only). */
417FNIEMOP_STUB(iemOp_vfnmadd213ss_d_Vx_Hx_Wx);
418/** Opcode VEX.66.0F38 0xae (vex only). */
419FNIEMOP_STUB(iemOp_vfnmsub213ps_d_Vx_Hx_Wx);
420/** Opcode VEX.66.0F38 0xaf (vex only). */
421FNIEMOP_STUB(iemOp_vfnmsub213ss_d_Vx_Hx_Wx);
422
423/* Opcode VEX.66.0F38 0xb0 - invalid. */
424/* Opcode VEX.66.0F38 0xb1 - invalid. */
425/* Opcode VEX.66.0F38 0xb2 - invalid. */
426/* Opcode VEX.66.0F38 0xb3 - invalid. */
427/* Opcode VEX.66.0F38 0xb4 - invalid. */
428/* Opcode VEX.66.0F38 0xb5 - invalid. */
429/** Opcode VEX.66.0F38 0xb6 (vex only). */
430FNIEMOP_STUB(iemOp_vfmaddsub231ps_d_Vx_Hx_Wx);
431/** Opcode VEX.66.0F38 0xb7 (vex only). */
432FNIEMOP_STUB(iemOp_vfmsubadd231ps_d_Vx_Hx_Wx);
433/** Opcode VEX.66.0F38 0xb8 (vex only). */
434FNIEMOP_STUB(iemOp_vfmadd231ps_d_Vx_Hx_Wx);
435/** Opcode VEX.66.0F38 0xb9 (vex only). */
436FNIEMOP_STUB(iemOp_vfmadd231ss_d_Vx_Hx_Wx);
437/** Opcode VEX.66.0F38 0xba (vex only). */
438FNIEMOP_STUB(iemOp_vfmsub231ps_d_Vx_Hx_Wx);
439/** Opcode VEX.66.0F38 0xbb (vex only). */
440FNIEMOP_STUB(iemOp_vfmsub231ss_d_Vx_Hx_Wx);
441/** Opcode VEX.66.0F38 0xbc (vex only). */
442FNIEMOP_STUB(iemOp_vfnmadd231ps_d_Vx_Hx_Wx);
443/** Opcode VEX.66.0F38 0xbd (vex only). */
444FNIEMOP_STUB(iemOp_vfnmadd231ss_d_Vx_Hx_Wx);
445/** Opcode VEX.66.0F38 0xbe (vex only). */
446FNIEMOP_STUB(iemOp_vfnmsub231ps_d_Vx_Hx_Wx);
447/** Opcode VEX.66.0F38 0xbf (vex only). */
448FNIEMOP_STUB(iemOp_vfnmsub231ss_d_Vx_Hx_Wx);
449
450/* Opcode VEX.0F38 0xc0 - invalid. */
451/* Opcode VEX.66.0F38 0xc0 - invalid. */
452/* Opcode VEX.0F38 0xc1 - invalid. */
453/* Opcode VEX.66.0F38 0xc1 - invalid. */
454/* Opcode VEX.0F38 0xc2 - invalid. */
455/* Opcode VEX.66.0F38 0xc2 - invalid. */
456/* Opcode VEX.0F38 0xc3 - invalid. */
457/* Opcode VEX.66.0F38 0xc3 - invalid. */
458/* Opcode VEX.0F38 0xc4 - invalid. */
459/* Opcode VEX.66.0F38 0xc4 - invalid. */
460/* Opcode VEX.0F38 0xc5 - invalid. */
461/* Opcode VEX.66.0F38 0xc5 - invalid. */
462/* Opcode VEX.0F38 0xc6 - invalid. */
463/* Opcode VEX.66.0F38 0xc6 - invalid. */
464/* Opcode VEX.0F38 0xc7 - invalid. */
465/* Opcode VEX.66.0F38 0xc7 - invalid. */
466/** Opcode VEX.0F38 0xc8. */
467FNIEMOP_STUB(iemOp_vsha1nexte_Vdq_Wdq);
468/* Opcode VEX.66.0F38 0xc8 - invalid. */
469/** Opcode VEX.0F38 0xc9. */
470FNIEMOP_STUB(iemOp_vsha1msg1_Vdq_Wdq);
471/* Opcode VEX.66.0F38 0xc9 - invalid. */
472/** Opcode VEX.0F38 0xca. */
473FNIEMOP_STUB(iemOp_vsha1msg2_Vdq_Wdq);
474/* Opcode VEX.66.0F38 0xca - invalid. */
475/** Opcode VEX.0F38 0xcb. */
476FNIEMOP_STUB(iemOp_vsha256rnds2_Vdq_Wdq);
477/* Opcode VEX.66.0F38 0xcb - invalid. */
478/** Opcode VEX.0F38 0xcc. */
479FNIEMOP_STUB(iemOp_vsha256msg1_Vdq_Wdq);
480/* Opcode VEX.66.0F38 0xcc - invalid. */
481/** Opcode VEX.0F38 0xcd. */
482FNIEMOP_STUB(iemOp_vsha256msg2_Vdq_Wdq);
483/* Opcode VEX.66.0F38 0xcd - invalid. */
484/* Opcode VEX.0F38 0xce - invalid. */
485/* Opcode VEX.66.0F38 0xce - invalid. */
486/* Opcode VEX.0F38 0xcf - invalid. */
487/* Opcode VEX.66.0F38 0xcf - invalid. */
488
489/* Opcode VEX.66.0F38 0xd0 - invalid. */
490/* Opcode VEX.66.0F38 0xd1 - invalid. */
491/* Opcode VEX.66.0F38 0xd2 - invalid. */
492/* Opcode VEX.66.0F38 0xd3 - invalid. */
493/* Opcode VEX.66.0F38 0xd4 - invalid. */
494/* Opcode VEX.66.0F38 0xd5 - invalid. */
495/* Opcode VEX.66.0F38 0xd6 - invalid. */
496/* Opcode VEX.66.0F38 0xd7 - invalid. */
497/* Opcode VEX.66.0F38 0xd8 - invalid. */
498/* Opcode VEX.66.0F38 0xd9 - invalid. */
499/* Opcode VEX.66.0F38 0xda - invalid. */
500/** Opcode VEX.66.0F38 0xdb. */
501FNIEMOP_STUB(iemOp_vaesimc_Vdq_Wdq);
502/** Opcode VEX.66.0F38 0xdc. */
503FNIEMOP_STUB(iemOp_vaesenc_Vdq_Wdq);
504/** Opcode VEX.66.0F38 0xdd. */
505FNIEMOP_STUB(iemOp_vaesenclast_Vdq_Wdq);
506/** Opcode VEX.66.0F38 0xde. */
507FNIEMOP_STUB(iemOp_vaesdec_Vdq_Wdq);
508/** Opcode VEX.66.0F38 0xdf. */
509FNIEMOP_STUB(iemOp_vaesdeclast_Vdq_Wdq);
510
511/* Opcode VEX.66.0F38 0xe0 - invalid. */
512/* Opcode VEX.66.0F38 0xe1 - invalid. */
513/* Opcode VEX.66.0F38 0xe2 - invalid. */
514/* Opcode VEX.66.0F38 0xe3 - invalid. */
515/* Opcode VEX.66.0F38 0xe4 - invalid. */
516/* Opcode VEX.66.0F38 0xe5 - invalid. */
517/* Opcode VEX.66.0F38 0xe6 - invalid. */
518/* Opcode VEX.66.0F38 0xe7 - invalid. */
519/* Opcode VEX.66.0F38 0xe8 - invalid. */
520/* Opcode VEX.66.0F38 0xe9 - invalid. */
521/* Opcode VEX.66.0F38 0xea - invalid. */
522/* Opcode VEX.66.0F38 0xeb - invalid. */
523/* Opcode VEX.66.0F38 0xec - invalid. */
524/* Opcode VEX.66.0F38 0xed - invalid. */
525/* Opcode VEX.66.0F38 0xee - invalid. */
526/* Opcode VEX.66.0F38 0xef - invalid. */
527
528
529/* Opcode VEX.0F38 0xf0 - invalid (legacy only). */
530/* Opcode VEX.66.0F38 0xf0 - invalid (legacy only). */
531/* Opcode VEX.F3.0F38 0xf0 - invalid. */
532/* Opcode VEX.F2.0F38 0xf0 - invalid (legacy only). */
533
534/* Opcode VEX.0F38 0xf1 - invalid (legacy only). */
535/* Opcode VEX.66.0F38 0xf1 - invalid (legacy only). */
536/* Opcode VEX.F3.0F38 0xf1 - invalid. */
537/* Opcode VEX.F2.0F38 0xf1 - invalid (legacy only). */
538
539/** Opcode VEX.0F38 0xf2 - ANDN (vex only). */
540FNIEMOP_DEF(iemOp_andn_Gy_By_Ey)
541{
542 IEMOP_MNEMONIC3(VEX_RVM, ANDN, andn, Gy, By, Ey, DISOPTYPE_HARMLESS, 0);
543 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1)
544 return iemOp_InvalidNeedRM(pVCpu);
545 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_PF);
546 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
547 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
548 {
549 /*
550 * Register, register.
551 */
552 IEMOP_HLP_DONE_VEX_DECODING();
553 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
554 {
555 IEM_MC_BEGIN(4, 0);
556 IEM_MC_ARG(uint64_t *, pDst, 0);
557 IEM_MC_ARG(uint64_t, uSrc1, 1);
558 IEM_MC_ARG(uint64_t, uSrc2, 2);
559 IEM_MC_ARG(uint32_t *, pEFlags, 3);
560 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
561 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
562 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
563 IEM_MC_REF_EFLAGS(pEFlags);
564 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
565 pDst, uSrc1, uSrc2, pEFlags);
566 IEM_MC_ADVANCE_RIP();
567 IEM_MC_END();
568 }
569 else
570 {
571 IEM_MC_BEGIN(4, 0);
572 IEM_MC_ARG(uint32_t *, pDst, 0);
573 IEM_MC_ARG(uint32_t, uSrc1, 1);
574 IEM_MC_ARG(uint32_t, uSrc2, 2);
575 IEM_MC_ARG(uint32_t *, pEFlags, 3);
576 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
577 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
578 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
579 IEM_MC_REF_EFLAGS(pEFlags);
580 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
581 pDst, uSrc1, uSrc2, pEFlags);
582 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
583 IEM_MC_ADVANCE_RIP();
584 IEM_MC_END();
585 }
586 }
587 else
588 {
589 /*
590 * Register, memory.
591 */
592 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
593 {
594 IEM_MC_BEGIN(4, 1);
595 IEM_MC_ARG(uint64_t *, pDst, 0);
596 IEM_MC_ARG(uint64_t, uSrc1, 1);
597 IEM_MC_ARG(uint64_t, uSrc2, 2);
598 IEM_MC_ARG(uint32_t *, pEFlags, 3);
599 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
600 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
601 IEMOP_HLP_DONE_VEX_DECODING();
602 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
603 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
604 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
605 IEM_MC_REF_EFLAGS(pEFlags);
606 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
607 pDst, uSrc1, uSrc2, pEFlags);
608 IEM_MC_ADVANCE_RIP();
609 IEM_MC_END();
610 }
611 else
612 {
613 IEM_MC_BEGIN(4, 1);
614 IEM_MC_ARG(uint32_t *, pDst, 0);
615 IEM_MC_ARG(uint32_t, uSrc1, 1);
616 IEM_MC_ARG(uint32_t, uSrc2, 2);
617 IEM_MC_ARG(uint32_t *, pEFlags, 3);
618 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
619 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
620 IEMOP_HLP_DONE_VEX_DECODING();
621 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
622 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
623 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
624 IEM_MC_REF_EFLAGS(pEFlags);
625 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
626 pDst, uSrc1, uSrc2, pEFlags);
627 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
628 IEM_MC_ADVANCE_RIP();
629 IEM_MC_END();
630 }
631 }
632 return VINF_SUCCESS;
633}
634
635/* Opcode VEX.66.0F38 0xf2 - invalid. */
636/* Opcode VEX.F3.0F38 0xf2 - invalid. */
637/* Opcode VEX.F2.0F38 0xf2 - invalid. */
638
639
640/* Opcode VEX.0F38 0xf3 - invalid. */
641/* Opcode VEX.66.0F38 0xf3 - invalid. */
642
643/* Opcode VEX.F3.0F38 0xf3 /0 - invalid). */
644/* Opcode VEX.F3.0F38 0xf3 /1). */
645FNIEMOP_STUB_1(iemOp_VGrp17_blsr_By_Ey, uint8_t, bRm);
646/* Opcode VEX.F3.0F38 0xf3 /2). */
647FNIEMOP_STUB_1(iemOp_VGrp17_blsmsk_By_Ey, uint8_t, bRm);
648/* Opcode VEX.F3.0F38 0xf3 /3). */
649FNIEMOP_STUB_1(iemOp_VGrp17_blsi_By_Ey, uint8_t, bRm);
650/* Opcode VEX.F3.0F38 0xf3 /4 - invalid). */
651/* Opcode VEX.F3.0F38 0xf3 /5 - invalid). */
652/* Opcode VEX.F3.0F38 0xf3 /6 - invalid). */
653/* Opcode VEX.F3.0F38 0xf3 /7 - invalid). */
654
655/**
656 * Group 17 jump table for the VEX.F3 variant.
657 */
658IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =
659{
660 /* /0 */ iemOp_InvalidWithRM,
661 /* /1 */ iemOp_VGrp17_blsr_By_Ey,
662 /* /2 */ iemOp_VGrp17_blsmsk_By_Ey,
663 /* /3 */ iemOp_VGrp17_blsi_By_Ey,
664 /* /4 */ iemOp_InvalidWithRM,
665 /* /5 */ iemOp_InvalidWithRM,
666 /* /6 */ iemOp_InvalidWithRM,
667 /* /7 */ iemOp_InvalidWithRM
668};
669AssertCompile(RT_ELEMENTS(g_apfnVexGroup17_f3) == 8);
670
671/** Opcode VEX.F3.0F38 0xf3 - invalid (vex only - group 17). */
672FNIEMOP_DEF(iemOp_VGrp17_f3)
673{
674 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
675 return FNIEMOP_CALL_1(g_apfnVexGroup17_f3[((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)], bRm);
676}
677
678/* Opcode VEX.F2.0F38 0xf3 - invalid (vex only - group 17). */
679
680
681/* Opcode VEX.0F38 0xf4 - invalid. */
682/* Opcode VEX.66.0F38 0xf4 - invalid. */
683/* Opcode VEX.F3.0F38 0xf4 - invalid. */
684/* Opcode VEX.F2.0F38 0xf4 - invalid. */
685
686#define IEMOP_BODY_Gy_Ey_By(a_Instr, a_fFeatureMember, a_fUndefFlags) \
687 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
688 return iemOp_InvalidNeedRM(pVCpu); \
689 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
690 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
691 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) \
692 { \
693 /* \
694 * Register, register. \
695 */ \
696 IEMOP_HLP_DONE_VEX_DECODING(); \
697 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
698 { \
699 IEM_MC_BEGIN(4, 0); \
700 IEM_MC_ARG(uint64_t *, pDst, 0); \
701 IEM_MC_ARG(uint64_t, uSrc1, 1); \
702 IEM_MC_ARG(uint64_t, uSrc2, 2); \
703 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
704 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
705 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
706 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
707 IEM_MC_REF_EFLAGS(pEFlags); \
708 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
709 iemAImpl_ ## a_Instr ## _u64_fallback), \
710 pDst, uSrc1, uSrc2, pEFlags); \
711 IEM_MC_ADVANCE_RIP(); \
712 IEM_MC_END(); \
713 } \
714 else \
715 { \
716 IEM_MC_BEGIN(4, 0); \
717 IEM_MC_ARG(uint32_t *, pDst, 0); \
718 IEM_MC_ARG(uint32_t, uSrc1, 1); \
719 IEM_MC_ARG(uint32_t, uSrc2, 2); \
720 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
721 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
722 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
723 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
724 IEM_MC_REF_EFLAGS(pEFlags); \
725 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
726 iemAImpl_ ## a_Instr ## _u32_fallback), \
727 pDst, uSrc1, uSrc2, pEFlags); \
728 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
729 IEM_MC_ADVANCE_RIP(); \
730 IEM_MC_END(); \
731 } \
732 } \
733 else \
734 { \
735 /* \
736 * Register, memory. \
737 */ \
738 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
739 { \
740 IEM_MC_BEGIN(4, 1); \
741 IEM_MC_ARG(uint64_t *, pDst, 0); \
742 IEM_MC_ARG(uint64_t, uSrc1, 1); \
743 IEM_MC_ARG(uint64_t, uSrc2, 2); \
744 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
745 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
746 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
747 IEMOP_HLP_DONE_VEX_DECODING(); \
748 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
749 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
750 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
751 IEM_MC_REF_EFLAGS(pEFlags); \
752 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
753 iemAImpl_ ## a_Instr ## _u64_fallback), \
754 pDst, uSrc1, uSrc2, pEFlags); \
755 IEM_MC_ADVANCE_RIP(); \
756 IEM_MC_END(); \
757 } \
758 else \
759 { \
760 IEM_MC_BEGIN(4, 1); \
761 IEM_MC_ARG(uint32_t *, pDst, 0); \
762 IEM_MC_ARG(uint32_t, uSrc1, 1); \
763 IEM_MC_ARG(uint32_t, uSrc2, 2); \
764 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
765 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
766 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
767 IEMOP_HLP_DONE_VEX_DECODING(); \
768 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
769 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
770 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
771 IEM_MC_REF_EFLAGS(pEFlags); \
772 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
773 iemAImpl_ ## a_Instr ## _u32_fallback), \
774 pDst, uSrc1, uSrc2, pEFlags); \
775 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
776 IEM_MC_ADVANCE_RIP(); \
777 IEM_MC_END(); \
778 } \
779 } \
780 return VINF_SUCCESS
781
782#define IEMOP_BODY_Gy_Ey_By_NoEflags(a_Instr, a_fFeatureMember, a_fUndefFlags) \
783 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
784 return iemOp_InvalidNeedRM(pVCpu); \
785 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
786 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
787 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) \
788 { \
789 /* \
790 * Register, register. \
791 */ \
792 IEMOP_HLP_DONE_VEX_DECODING(); \
793 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
794 { \
795 IEM_MC_BEGIN(3, 0); \
796 IEM_MC_ARG(uint64_t *, pDst, 0); \
797 IEM_MC_ARG(uint64_t, uSrc1, 1); \
798 IEM_MC_ARG(uint64_t, uSrc2, 2); \
799 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
800 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
801 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
802 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
803 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
804 IEM_MC_ADVANCE_RIP(); \
805 IEM_MC_END(); \
806 } \
807 else \
808 { \
809 IEM_MC_BEGIN(3, 0); \
810 IEM_MC_ARG(uint32_t *, pDst, 0); \
811 IEM_MC_ARG(uint32_t, uSrc1, 1); \
812 IEM_MC_ARG(uint32_t, uSrc2, 2); \
813 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
814 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
815 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
816 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
817 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
818 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
819 IEM_MC_ADVANCE_RIP(); \
820 IEM_MC_END(); \
821 } \
822 } \
823 else \
824 { \
825 /* \
826 * Register, memory. \
827 */ \
828 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
829 { \
830 IEM_MC_BEGIN(3, 1); \
831 IEM_MC_ARG(uint64_t *, pDst, 0); \
832 IEM_MC_ARG(uint64_t, uSrc1, 1); \
833 IEM_MC_ARG(uint64_t, uSrc2, 2); \
834 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
835 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
836 IEMOP_HLP_DONE_VEX_DECODING(); \
837 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
838 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
839 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
840 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
841 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
842 IEM_MC_ADVANCE_RIP(); \
843 IEM_MC_END(); \
844 } \
845 else \
846 { \
847 IEM_MC_BEGIN(3, 1); \
848 IEM_MC_ARG(uint32_t *, pDst, 0); \
849 IEM_MC_ARG(uint32_t, uSrc1, 1); \
850 IEM_MC_ARG(uint32_t, uSrc2, 2); \
851 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
852 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
853 IEMOP_HLP_DONE_VEX_DECODING(); \
854 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
855 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
856 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
857 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
858 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
859 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
860 IEM_MC_ADVANCE_RIP(); \
861 IEM_MC_END(); \
862 } \
863 } \
864 return VINF_SUCCESS
865
866/** Opcode VEX.0F38 0xf5 (vex only). */
867FNIEMOP_STUB(iemOp_bzhi_Gy_Ey_By);
868/* Opcode VEX.66.0F38 0xf5 - invalid. */
869/** Opcode VEX.F3.0F38 0xf5 (vex only). */
870FNIEMOP_STUB(iemOp_pext_Gy_By_Ey);
871/** Opcode VEX.F2.0F38 0xf5 (vex only). */
872FNIEMOP_STUB(iemOp_pdep_Gy_By_Ey);
873
874/* Opcode VEX.0F38 0xf6 - invalid. */
875/* Opcode VEX.66.0F38 0xf6 - invalid (legacy only). */
876/* Opcode VEX.F3.0F38 0xf6 - invalid (legacy only). */
877/* Opcode VEX.F2.0F38 0xf6 - invalid (vex only). */
878FNIEMOP_STUB(iemOp_mulx_By_Gy_rDX_Ey);
879
880
881/** Opcode VEX.0F38 0xf7 (vex only). */
882FNIEMOP_DEF(iemOp_bextr_Gy_Ey_By)
883{
884 IEMOP_MNEMONIC3(VEX_RMV, BEXTR, bextr, Gy, Ey, By, DISOPTYPE_HARMLESS, 0);
885 IEMOP_BODY_Gy_Ey_By(bextr, fBmi1, X86_EFL_SF | X86_EFL_AF | X86_EFL_PF);
886}
887
888
889/** Opcode VEX.66.0F38 0xf7 (vex only). */
890FNIEMOP_DEF(iemOp_shlx_Gy_Ey_By)
891{
892 IEMOP_MNEMONIC3(VEX_RMV, SHLX, shlx, Gy, Ey, By, DISOPTYPE_HARMLESS, 0);
893 IEMOP_BODY_Gy_Ey_By_NoEflags(shlx, fBmi2, 0);
894}
895
896
897/** Opcode VEX.F3.0F38 0xf7 (vex only). */
898FNIEMOP_DEF(iemOp_sarx_Gy_Ey_By)
899{
900 IEMOP_MNEMONIC3(VEX_RMV, SARX, sarx, Gy, Ey, By, DISOPTYPE_HARMLESS, 0);
901 IEMOP_BODY_Gy_Ey_By_NoEflags(sarx, fBmi2, 0);
902}
903
904
905/** Opcode VEX.F2.0F38 0xf7 (vex only). */
906FNIEMOP_DEF(iemOp_shrx_Gy_Ey_By)
907{
908 IEMOP_MNEMONIC3(VEX_RMV, SHRX, shrx, Gy, Ey, By, DISOPTYPE_HARMLESS, 0);
909 IEMOP_BODY_Gy_Ey_By_NoEflags(shrx, fBmi2, 0);
910}
911
912/* Opcode VEX.0F38 0xf8 - invalid. */
913/* Opcode VEX.66.0F38 0xf8 - invalid. */
914/* Opcode VEX.F3.0F38 0xf8 - invalid. */
915/* Opcode VEX.F2.0F38 0xf8 - invalid. */
916
917/* Opcode VEX.0F38 0xf9 - invalid. */
918/* Opcode VEX.66.0F38 0xf9 - invalid. */
919/* Opcode VEX.F3.0F38 0xf9 - invalid. */
920/* Opcode VEX.F2.0F38 0xf9 - invalid. */
921
922/* Opcode VEX.0F38 0xfa - invalid. */
923/* Opcode VEX.66.0F38 0xfa - invalid. */
924/* Opcode VEX.F3.0F38 0xfa - invalid. */
925/* Opcode VEX.F2.0F38 0xfa - invalid. */
926
927/* Opcode VEX.0F38 0xfb - invalid. */
928/* Opcode VEX.66.0F38 0xfb - invalid. */
929/* Opcode VEX.F3.0F38 0xfb - invalid. */
930/* Opcode VEX.F2.0F38 0xfb - invalid. */
931
932/* Opcode VEX.0F38 0xfc - invalid. */
933/* Opcode VEX.66.0F38 0xfc - invalid. */
934/* Opcode VEX.F3.0F38 0xfc - invalid. */
935/* Opcode VEX.F2.0F38 0xfc - invalid. */
936
937/* Opcode VEX.0F38 0xfd - invalid. */
938/* Opcode VEX.66.0F38 0xfd - invalid. */
939/* Opcode VEX.F3.0F38 0xfd - invalid. */
940/* Opcode VEX.F2.0F38 0xfd - invalid. */
941
942/* Opcode VEX.0F38 0xfe - invalid. */
943/* Opcode VEX.66.0F38 0xfe - invalid. */
944/* Opcode VEX.F3.0F38 0xfe - invalid. */
945/* Opcode VEX.F2.0F38 0xfe - invalid. */
946
947/* Opcode VEX.0F38 0xff - invalid. */
948/* Opcode VEX.66.0F38 0xff - invalid. */
949/* Opcode VEX.F3.0F38 0xff - invalid. */
950/* Opcode VEX.F2.0F38 0xff - invalid. */
951
952
953/**
954 * VEX opcode map \#2.
955 *
956 * @sa g_apfnThreeByte0f38
957 */
958IEM_STATIC const PFNIEMOP g_apfnVexMap2[] =
959{
960 /* no prefix, 066h prefix f3h prefix, f2h prefix */
961 /* 0x00 */ iemOp_InvalidNeedRM, iemOp_vpshufb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
962 /* 0x01 */ iemOp_InvalidNeedRM, iemOp_vphaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
963 /* 0x02 */ iemOp_InvalidNeedRM, iemOp_vphaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
964 /* 0x03 */ iemOp_InvalidNeedRM, iemOp_vphaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
965 /* 0x04 */ iemOp_InvalidNeedRM, iemOp_vpmaddubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
966 /* 0x05 */ iemOp_InvalidNeedRM, iemOp_vphsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
967 /* 0x06 */ iemOp_InvalidNeedRM, iemOp_vphsubdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
968 /* 0x07 */ iemOp_InvalidNeedRM, iemOp_vphsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
969 /* 0x08 */ iemOp_InvalidNeedRM, iemOp_vpsignb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
970 /* 0x09 */ iemOp_InvalidNeedRM, iemOp_vpsignw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
971 /* 0x0a */ iemOp_InvalidNeedRM, iemOp_vpsignd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
972 /* 0x0b */ iemOp_InvalidNeedRM, iemOp_vpmulhrsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
973 /* 0x0c */ iemOp_InvalidNeedRM, iemOp_vpermilps_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
974 /* 0x0d */ iemOp_InvalidNeedRM, iemOp_vpermilpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
975 /* 0x0e */ iemOp_InvalidNeedRM, iemOp_vtestps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
976 /* 0x0f */ iemOp_InvalidNeedRM, iemOp_vtestpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
977
978 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRM),
979 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
980 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
981 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
982 /* 0x14 */ IEMOP_X4(iemOp_InvalidNeedRM),
983 /* 0x15 */ IEMOP_X4(iemOp_InvalidNeedRM),
984 /* 0x16 */ iemOp_InvalidNeedRM, iemOp_vpermps_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
985 /* 0x17 */ iemOp_InvalidNeedRM, iemOp_vptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
986 /* 0x18 */ iemOp_InvalidNeedRM, iemOp_vbroadcastss_Vx_Wd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
987 /* 0x19 */ iemOp_InvalidNeedRM, iemOp_vbroadcastsd_Vqq_Wq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
988 /* 0x1a */ iemOp_InvalidNeedRM, iemOp_vbroadcastf128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
989 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
990 /* 0x1c */ iemOp_InvalidNeedRM, iemOp_vpabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
991 /* 0x1d */ iemOp_InvalidNeedRM, iemOp_vpabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
992 /* 0x1e */ iemOp_InvalidNeedRM, iemOp_vpabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
993 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
994
995 /* 0x20 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
996 /* 0x21 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
997 /* 0x22 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
998 /* 0x23 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
999 /* 0x24 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1000 /* 0x25 */ iemOp_InvalidNeedRM, iemOp_vpmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1001 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
1002 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
1003 /* 0x28 */ iemOp_InvalidNeedRM, iemOp_vpmuldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1004 /* 0x29 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1005 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_vmovntdqa_Vx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1006 /* 0x2b */ iemOp_InvalidNeedRM, iemOp_vpackusdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1007 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1008 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1009 /* 0x2e */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1010 /* 0x2f */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1011
1012 /* 0x30 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1013 /* 0x31 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1014 /* 0x32 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1015 /* 0x33 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1016 /* 0x34 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1017 /* 0x35 */ iemOp_InvalidNeedRM, iemOp_vpmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1018 /* 0x36 */ iemOp_InvalidNeedRM, iemOp_vpermd_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1019 /* 0x37 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1020 /* 0x38 */ iemOp_InvalidNeedRM, iemOp_vpminsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1021 /* 0x39 */ iemOp_InvalidNeedRM, iemOp_vpminsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1022 /* 0x3a */ iemOp_InvalidNeedRM, iemOp_vpminuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1023 /* 0x3b */ iemOp_InvalidNeedRM, iemOp_vpminud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1024 /* 0x3c */ iemOp_InvalidNeedRM, iemOp_vpmaxsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1025 /* 0x3d */ iemOp_InvalidNeedRM, iemOp_vpmaxsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1026 /* 0x3e */ iemOp_InvalidNeedRM, iemOp_vpmaxuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1027 /* 0x3f */ iemOp_InvalidNeedRM, iemOp_vpmaxud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1028
1029 /* 0x40 */ iemOp_InvalidNeedRM, iemOp_vpmulld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1030 /* 0x41 */ iemOp_InvalidNeedRM, iemOp_vphminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1031 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
1032 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
1033 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
1034 /* 0x45 */ iemOp_InvalidNeedRM, iemOp_vpsrlvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1035 /* 0x46 */ iemOp_InvalidNeedRM, iemOp_vsravd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1036 /* 0x47 */ iemOp_InvalidNeedRM, iemOp_vpsllvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1037 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
1038 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
1039 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
1040 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
1041 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
1042 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
1043 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
1044 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
1045
1046 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
1047 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
1048 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
1049 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
1050 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
1051 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
1052 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
1053 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
1054 /* 0x58 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1055 /* 0x59 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1056 /* 0x5a */ iemOp_InvalidNeedRM, iemOp_vbroadcasti128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1057 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
1058 /* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
1059 /* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
1060 /* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
1061 /* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
1062
1063 /* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
1064 /* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
1065 /* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
1066 /* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
1067 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
1068 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
1069 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
1070 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
1071 /* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
1072 /* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
1073 /* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
1074 /* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
1075 /* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
1076 /* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
1077 /* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
1078 /* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
1079
1080 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
1081 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
1082 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
1083 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
1084 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
1085 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
1086 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
1087 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
1088 /* 0x78 */ iemOp_InvalidNeedRM, iemOp_vpboardcastb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1089 /* 0x79 */ iemOp_InvalidNeedRM, iemOp_vpboardcastw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1090 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
1091 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
1092 /* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
1093 /* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
1094 /* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
1095 /* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
1096
1097 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
1098 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
1099 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
1100 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
1101 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
1102 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
1103 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
1104 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
1105 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
1106 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
1107 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
1108 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
1109 /* 0x8c */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1110 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
1111 /* 0x8e */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Mx_Vx_Hx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1112 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
1113
1114 /* 0x90 */ iemOp_InvalidNeedRM, iemOp_vgatherdd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1115 /* 0x91 */ iemOp_InvalidNeedRM, iemOp_vgatherqd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1116 /* 0x92 */ iemOp_InvalidNeedRM, iemOp_vgatherdps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1117 /* 0x93 */ iemOp_InvalidNeedRM, iemOp_vgatherqps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1118 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
1119 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
1120 /* 0x96 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub132ps_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1121 /* 0x97 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1122 /* 0x98 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1123 /* 0x99 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1124 /* 0x9a */ iemOp_InvalidNeedRM, iemOp_vfmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1125 /* 0x9b */ iemOp_InvalidNeedRM, iemOp_vfmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1126 /* 0x9c */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1127 /* 0x9d */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1128 /* 0x9e */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1129 /* 0x9f */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1130
1131 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1132 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1133 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1134 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1135 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1136 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1137 /* 0xa6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1138 /* 0xa7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1139 /* 0xa8 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1140 /* 0xa9 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1141 /* 0xaa */ iemOp_InvalidNeedRM, iemOp_vfmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1142 /* 0xab */ iemOp_InvalidNeedRM, iemOp_vfmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1143 /* 0xac */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1144 /* 0xad */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1145 /* 0xae */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1146 /* 0xaf */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1147
1148 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1149 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1150 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1151 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1152 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1153 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1154 /* 0xb6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1155 /* 0xb7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1156 /* 0xb8 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1157 /* 0xb9 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1158 /* 0xba */ iemOp_InvalidNeedRM, iemOp_vfmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1159 /* 0xbb */ iemOp_InvalidNeedRM, iemOp_vfmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1160 /* 0xbc */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1161 /* 0xbd */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1162 /* 0xbe */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1163 /* 0xbf */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1164
1165 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1166 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1167 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1168 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1169 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1170 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1171 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1172 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1173 /* 0xc8 */ iemOp_vsha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1174 /* 0xc9 */ iemOp_vsha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1175 /* 0xca */ iemOp_vsha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1176 /* 0xcb */ iemOp_vsha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1177 /* 0xcc */ iemOp_vsha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1178 /* 0xcd */ iemOp_vsha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1179 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
1180 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
1181
1182 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1183 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1184 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1185 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1186 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1187 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1188 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1189 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1190 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1191 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1192 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
1193 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vaesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1194 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vaesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1195 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vaesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1196 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vaesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1197 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vaesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1198
1199 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1200 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1201 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1202 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1203 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1204 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1205 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1206 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1207 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1208 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1209 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
1210 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
1211 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
1212 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
1213 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
1214 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
1215
1216 /* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1217 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1218 /* 0xf2 */ iemOp_andn_Gy_By_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1219 /* 0xf3 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_VGrp17_f3, iemOp_InvalidNeedRM,
1220 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1221 /* 0xf5 */ iemOp_bzhi_Gy_Ey_By, iemOp_InvalidNeedRM, iemOp_pext_Gy_By_Ey, iemOp_pdep_Gy_By_Ey,
1222 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_mulx_By_Gy_rDX_Ey,
1223 /* 0xf7 */ iemOp_bextr_Gy_Ey_By, iemOp_shlx_Gy_Ey_By, iemOp_sarx_Gy_Ey_By, iemOp_shrx_Gy_Ey_By,
1224 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1225 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1226 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
1227 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
1228 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
1229 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
1230 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
1231 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
1232};
1233AssertCompile(RT_ELEMENTS(g_apfnVexMap2) == 1024);
1234
1235/** @} */
1236
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