IEMAllInstructionsVexMap2.cpp.h@ 95345

Last change on this file since 95345 was 95345, checked in by vboxsync, 3 years ago
VMM/IEM: Implemented the PDEP and PEXT instructions. bugref:9898
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 67.0 KB

Line
1	/* $Id: IEMAllInstructionsVexMap2.cpp.h 95345 2022-06-22 16:15:23Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation.
4	*
5	* @remarks IEMAllInstructionsThree0f38.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/** @name VEX Opcode Map 2
23	* @{
24	*/
25
26	/* Opcode VEX.0F38 0x00 - invalid. */
27	/** Opcode VEX.66.0F38 0x00. */
28	FNIEMOP_STUB(iemOp_vpshufb_Vx_Hx_Wx);
29	/* Opcode VEX.0F38 0x01 - invalid. */
30	/** Opcode VEX.66.0F38 0x01. */
31	FNIEMOP_STUB(iemOp_vphaddw_Vx_Hx_Wx);
32	/* Opcode VEX.0F38 0x02 - invalid. */
33	/** Opcode VEX.66.0F38 0x02. */
34	FNIEMOP_STUB(iemOp_vphaddd_Vx_Hx_Wx);
35	/* Opcode VEX.0F38 0x03 - invalid. */
36	/** Opcode VEX.66.0F38 0x03. */
37	FNIEMOP_STUB(iemOp_vphaddsw_Vx_Hx_Wx);
38	/* Opcode VEX.0F38 0x04 - invalid. */
39	/** Opcode VEX.66.0F38 0x04. */
40	FNIEMOP_STUB(iemOp_vpmaddubsw_Vx_Hx_Wx);
41	/* Opcode VEX.0F38 0x05 - invalid. */
42	/** Opcode VEX.66.0F38 0x05. */
43	FNIEMOP_STUB(iemOp_vphsubw_Vx_Hx_Wx);
44	/* Opcode VEX.0F38 0x06 - invalid. */
45	/** Opcode VEX.66.0F38 0x06. */
46	FNIEMOP_STUB(iemOp_vphsubdq_Vx_Hx_Wx);
47	/* Opcode VEX.0F38 0x07 - invalid. */
48	/** Opcode VEX.66.0F38 0x07. */
49	FNIEMOP_STUB(iemOp_vphsubsw_Vx_Hx_Wx);
50	/* Opcode VEX.0F38 0x08 - invalid. */
51	/** Opcode VEX.66.0F38 0x08. */
52	FNIEMOP_STUB(iemOp_vpsignb_Vx_Hx_Wx);
53	/* Opcode VEX.0F38 0x09 - invalid. */
54	/** Opcode VEX.66.0F38 0x09. */
55	FNIEMOP_STUB(iemOp_vpsignw_Vx_Hx_Wx);
56	/* Opcode VEX.0F38 0x0a - invalid. */
57	/** Opcode VEX.66.0F38 0x0a. */
58	FNIEMOP_STUB(iemOp_vpsignd_Vx_Hx_Wx);
59	/* Opcode VEX.0F38 0x0b - invalid. */
60	/** Opcode VEX.66.0F38 0x0b. */
61	FNIEMOP_STUB(iemOp_vpmulhrsw_Vx_Hx_Wx);
62	/* Opcode VEX.0F38 0x0c - invalid. */
63	/** Opcode VEX.66.0F38 0x0c. */
64	FNIEMOP_STUB(iemOp_vpermilps_Vx_Hx_Wx);
65	/* Opcode VEX.0F38 0x0d - invalid. */
66	/** Opcode VEX.66.0F38 0x0d. */
67	FNIEMOP_STUB(iemOp_vpermilpd_Vx_Hx_Wx);
68	/* Opcode VEX.0F38 0x0e - invalid. */
69	/** Opcode VEX.66.0F38 0x0e. */
70	FNIEMOP_STUB(iemOp_vtestps_Vx_Wx);
71	/* Opcode VEX.0F38 0x0f - invalid. */
72	/** Opcode VEX.66.0F38 0x0f. */
73	FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx);
74
75
76	/* Opcode VEX.0F38 0x10 - invalid */
77	/* Opcode VEX.66.0F38 0x10 - invalid (legacy only). */
78	/* Opcode VEX.0F38 0x11 - invalid */
79	/* Opcode VEX.66.0F38 0x11 - invalid */
80	/* Opcode VEX.0F38 0x12 - invalid */
81	/* Opcode VEX.66.0F38 0x12 - invalid */
82	/* Opcode VEX.0F38 0x13 - invalid */
83	/* Opcode VEX.66.0F38 0x13 - invalid (vex only). */
84	/* Opcode VEX.0F38 0x14 - invalid */
85	/* Opcode VEX.66.0F38 0x14 - invalid (legacy only). */
86	/* Opcode VEX.0F38 0x15 - invalid */
87	/* Opcode VEX.66.0F38 0x15 - invalid (legacy only). */
88	/* Opcode VEX.0F38 0x16 - invalid */
89	/** Opcode VEX.66.0F38 0x16. */
90	FNIEMOP_STUB(iemOp_vpermps_Vqq_Hqq_Wqq);
91	/* Opcode VEX.0F38 0x17 - invalid */
92	/** Opcode VEX.66.0F38 0x17 - invalid */
93	FNIEMOP_STUB(iemOp_vptest_Vx_Wx);
94	/* Opcode VEX.0F38 0x18 - invalid */
95	/** Opcode VEX.66.0F38 0x18. */
96	FNIEMOP_STUB(iemOp_vbroadcastss_Vx_Wd);
97	/* Opcode VEX.0F38 0x19 - invalid */
98	/** Opcode VEX.66.0F38 0x19. */
99	FNIEMOP_STUB(iemOp_vbroadcastsd_Vqq_Wq);
100	/* Opcode VEX.0F38 0x1a - invalid */
101	/** Opcode VEX.66.0F38 0x1a. */
102	FNIEMOP_STUB(iemOp_vbroadcastf128_Vqq_Mdq);
103	/* Opcode VEX.0F38 0x1b - invalid */
104	/* Opcode VEX.66.0F38 0x1b - invalid */
105	/* Opcode VEX.0F38 0x1c - invalid. */
106	/** Opcode VEX.66.0F38 0x1c. */
107	FNIEMOP_STUB(iemOp_vpabsb_Vx_Wx);
108	/* Opcode VEX.0F38 0x1d - invalid. */
109	/** Opcode VEX.66.0F38 0x1d. */
110	FNIEMOP_STUB(iemOp_vpabsw_Vx_Wx);
111	/* Opcode VEX.0F38 0x1e - invalid. */
112	/** Opcode VEX.66.0F38 0x1e. */
113	FNIEMOP_STUB(iemOp_vpabsd_Vx_Wx);
114	/* Opcode VEX.0F38 0x1f - invalid */
115	/* Opcode VEX.66.0F38 0x1f - invalid */
116
117
118	/** Opcode VEX.66.0F38 0x20. */
119	FNIEMOP_STUB(iemOp_vpmovsxbw_Vx_UxMq);
120	/** Opcode VEX.66.0F38 0x21. */
121	FNIEMOP_STUB(iemOp_vpmovsxbd_Vx_UxMd);
122	/** Opcode VEX.66.0F38 0x22. */
123	FNIEMOP_STUB(iemOp_vpmovsxbq_Vx_UxMw);
124	/** Opcode VEX.66.0F38 0x23. */
125	FNIEMOP_STUB(iemOp_vpmovsxwd_Vx_UxMq);
126	/** Opcode VEX.66.0F38 0x24. */
127	FNIEMOP_STUB(iemOp_vpmovsxwq_Vx_UxMd);
128	/** Opcode VEX.66.0F38 0x25. */
129	FNIEMOP_STUB(iemOp_vpmovsxdq_Vx_UxMq);
130	/* Opcode VEX.66.0F38 0x26 - invalid */
131	/* Opcode VEX.66.0F38 0x27 - invalid */
132	/** Opcode VEX.66.0F38 0x28. */
133	FNIEMOP_STUB(iemOp_vpmuldq_Vx_Hx_Wx);
134	/** Opcode VEX.66.0F38 0x29. */
135	FNIEMOP_STUB(iemOp_vpcmpeqq_Vx_Hx_Wx);
136
137
138	FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
139	{
140	Assert(pVCpu->iem.s.uVexLength <= 1);
141	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
142	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
143	{
144	if (pVCpu->iem.s.uVexLength == 0)
145	{
146	/**
147	* @opcode 0x2a
148	* @opcodesub !11 mr/reg vex.l=0
149	* @oppfx 0x66
150	* @opcpuid avx
151	* @opgroup og_avx_cachect
152	* @opxcpttype 1
153	* @optest op1=-1 op2=2 -> op1=2
154	* @optest op1=0 op2=-42 -> op1=-42
155	*/
156	/* 128-bit: Memory, register. */
157	IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
158	DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
159	IEM_MC_BEGIN(0, 2);
160	IEM_MC_LOCAL(RTUINT128U, uSrc);
161	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
162
163	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
164	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
165	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
166	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
167
168	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
169	IEM_MC_STORE_YREG_U128_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, uSrc);
170
171	IEM_MC_ADVANCE_RIP();
172	IEM_MC_END();
173	}
174	else
175	{
176	/**
177	* @opdone
178	* @opcode 0x2a
179	* @opcodesub !11 mr/reg vex.l=1
180	* @oppfx 0x66
181	* @opcpuid avx2
182	* @opgroup og_avx2_cachect
183	* @opxcpttype 1
184	* @optest op1=-1 op2=2 -> op1=2
185	* @optest op1=0 op2=-42 -> op1=-42
186	*/
187	/* 256-bit: Memory, register. */
188	IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
189	DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
190	IEM_MC_BEGIN(0, 2);
191	IEM_MC_LOCAL(RTUINT256U, uSrc);
192	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
193
194	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
195	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
196	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
197	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
198
199	IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
200	IEM_MC_STORE_YREG_U256_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, uSrc);
201
202	IEM_MC_ADVANCE_RIP();
203	IEM_MC_END();
204	}
205	return VINF_SUCCESS;
206	}
207
208	/**
209	* @opdone
210	* @opmnemonic udvex660f382arg
211	* @opcode 0x2a
212	* @opcodesub 11 mr/reg
213	* @oppfx 0x66
214	* @opunused immediate
215	* @opcpuid avx
216	* @optest ->
217	*/
218	return IEMOP_RAISE_INVALID_OPCODE();
219
220	}
221
222
223	/** Opcode VEX.66.0F38 0x2b. */
224	FNIEMOP_STUB(iemOp_vpackusdw_Vx_Hx_Wx);
225	/** Opcode VEX.66.0F38 0x2c. */
226	FNIEMOP_STUB(iemOp_vmaskmovps_Vx_Hx_Mx);
227	/** Opcode VEX.66.0F38 0x2d. */
228	FNIEMOP_STUB(iemOp_vmaskmovpd_Vx_Hx_Mx);
229	/** Opcode VEX.66.0F38 0x2e. */
230	FNIEMOP_STUB(iemOp_vmaskmovps_Mx_Hx_Vx);
231	/** Opcode VEX.66.0F38 0x2f. */
232	FNIEMOP_STUB(iemOp_vmaskmovpd_Mx_Hx_Vx);
233
234	/** Opcode VEX.66.0F38 0x30. */
235	FNIEMOP_STUB(iemOp_vpmovzxbw_Vx_UxMq);
236	/** Opcode VEX.66.0F38 0x31. */
237	FNIEMOP_STUB(iemOp_vpmovzxbd_Vx_UxMd);
238	/** Opcode VEX.66.0F38 0x32. */
239	FNIEMOP_STUB(iemOp_vpmovzxbq_Vx_UxMw);
240	/** Opcode VEX.66.0F38 0x33. */
241	FNIEMOP_STUB(iemOp_vpmovzxwd_Vx_UxMq);
242	/** Opcode VEX.66.0F38 0x34. */
243	FNIEMOP_STUB(iemOp_vpmovzxwq_Vx_UxMd);
244	/** Opcode VEX.66.0F38 0x35. */
245	FNIEMOP_STUB(iemOp_vpmovzxdq_Vx_UxMq);
246	/* Opcode VEX.66.0F38 0x36. */
247	FNIEMOP_STUB(iemOp_vpermd_Vqq_Hqq_Wqq);
248	/** Opcode VEX.66.0F38 0x37. */
249	FNIEMOP_STUB(iemOp_vpcmpgtq_Vx_Hx_Wx);
250	/** Opcode VEX.66.0F38 0x38. */
251	FNIEMOP_STUB(iemOp_vpminsb_Vx_Hx_Wx);
252	/** Opcode VEX.66.0F38 0x39. */
253	FNIEMOP_STUB(iemOp_vpminsd_Vx_Hx_Wx);
254	/** Opcode VEX.66.0F38 0x3a. */
255	FNIEMOP_STUB(iemOp_vpminuw_Vx_Hx_Wx);
256	/** Opcode VEX.66.0F38 0x3b. */
257	FNIEMOP_STUB(iemOp_vpminud_Vx_Hx_Wx);
258	/** Opcode VEX.66.0F38 0x3c. */
259	FNIEMOP_STUB(iemOp_vpmaxsb_Vx_Hx_Wx);
260	/** Opcode VEX.66.0F38 0x3d. */
261	FNIEMOP_STUB(iemOp_vpmaxsd_Vx_Hx_Wx);
262	/** Opcode VEX.66.0F38 0x3e. */
263	FNIEMOP_STUB(iemOp_vpmaxuw_Vx_Hx_Wx);
264	/** Opcode VEX.66.0F38 0x3f. */
265	FNIEMOP_STUB(iemOp_vpmaxud_Vx_Hx_Wx);
266
267
268	/** Opcode VEX.66.0F38 0x40. */
269	FNIEMOP_STUB(iemOp_vpmulld_Vx_Hx_Wx);
270	/** Opcode VEX.66.0F38 0x41. */
271	FNIEMOP_STUB(iemOp_vphminposuw_Vdq_Wdq);
272	/* Opcode VEX.66.0F38 0x42 - invalid. */
273	/* Opcode VEX.66.0F38 0x43 - invalid. */
274	/* Opcode VEX.66.0F38 0x44 - invalid. */
275	/** Opcode VEX.66.0F38 0x45. */
276	FNIEMOP_STUB(iemOp_vpsrlvd_q_Vx_Hx_Wx);
277	/** Opcode VEX.66.0F38 0x46. */
278	FNIEMOP_STUB(iemOp_vsravd_Vx_Hx_Wx);
279	/** Opcode VEX.66.0F38 0x47. */
280	FNIEMOP_STUB(iemOp_vpsllvd_q_Vx_Hx_Wx);
281	/* Opcode VEX.66.0F38 0x48 - invalid. */
282	/* Opcode VEX.66.0F38 0x49 - invalid. */
283	/* Opcode VEX.66.0F38 0x4a - invalid. */
284	/* Opcode VEX.66.0F38 0x4b - invalid. */
285	/* Opcode VEX.66.0F38 0x4c - invalid. */
286	/* Opcode VEX.66.0F38 0x4d - invalid. */
287	/* Opcode VEX.66.0F38 0x4e - invalid. */
288	/* Opcode VEX.66.0F38 0x4f - invalid. */
289
290	/* Opcode VEX.66.0F38 0x50 - invalid. */
291	/* Opcode VEX.66.0F38 0x51 - invalid. */
292	/* Opcode VEX.66.0F38 0x52 - invalid. */
293	/* Opcode VEX.66.0F38 0x53 - invalid. */
294	/* Opcode VEX.66.0F38 0x54 - invalid. */
295	/* Opcode VEX.66.0F38 0x55 - invalid. */
296	/* Opcode VEX.66.0F38 0x56 - invalid. */
297	/* Opcode VEX.66.0F38 0x57 - invalid. */
298	/** Opcode VEX.66.0F38 0x58. */
299	FNIEMOP_STUB(iemOp_vpbroadcastd_Vx_Wx);
300	/** Opcode VEX.66.0F38 0x59. */
301	FNIEMOP_STUB(iemOp_vpbroadcastq_Vx_Wx);
302	/** Opcode VEX.66.0F38 0x5a. */
303	FNIEMOP_STUB(iemOp_vbroadcasti128_Vqq_Mdq);
304	/* Opcode VEX.66.0F38 0x5b - invalid. */
305	/* Opcode VEX.66.0F38 0x5c - invalid. */
306	/* Opcode VEX.66.0F38 0x5d - invalid. */
307	/* Opcode VEX.66.0F38 0x5e - invalid. */
308	/* Opcode VEX.66.0F38 0x5f - invalid. */
309
310	/* Opcode VEX.66.0F38 0x60 - invalid. */
311	/* Opcode VEX.66.0F38 0x61 - invalid. */
312	/* Opcode VEX.66.0F38 0x62 - invalid. */
313	/* Opcode VEX.66.0F38 0x63 - invalid. */
314	/* Opcode VEX.66.0F38 0x64 - invalid. */
315	/* Opcode VEX.66.0F38 0x65 - invalid. */
316	/* Opcode VEX.66.0F38 0x66 - invalid. */
317	/* Opcode VEX.66.0F38 0x67 - invalid. */
318	/* Opcode VEX.66.0F38 0x68 - invalid. */
319	/* Opcode VEX.66.0F38 0x69 - invalid. */
320	/* Opcode VEX.66.0F38 0x6a - invalid. */
321	/* Opcode VEX.66.0F38 0x6b - invalid. */
322	/* Opcode VEX.66.0F38 0x6c - invalid. */
323	/* Opcode VEX.66.0F38 0x6d - invalid. */
324	/* Opcode VEX.66.0F38 0x6e - invalid. */
325	/* Opcode VEX.66.0F38 0x6f - invalid. */
326
327	/* Opcode VEX.66.0F38 0x70 - invalid. */
328	/* Opcode VEX.66.0F38 0x71 - invalid. */
329	/* Opcode VEX.66.0F38 0x72 - invalid. */
330	/* Opcode VEX.66.0F38 0x73 - invalid. */
331	/* Opcode VEX.66.0F38 0x74 - invalid. */
332	/* Opcode VEX.66.0F38 0x75 - invalid. */
333	/* Opcode VEX.66.0F38 0x76 - invalid. */
334	/* Opcode VEX.66.0F38 0x77 - invalid. */
335	/** Opcode VEX.66.0F38 0x78. */
336	FNIEMOP_STUB(iemOp_vpboardcastb_Vx_Wx);
337	/** Opcode VEX.66.0F38 0x79. */
338	FNIEMOP_STUB(iemOp_vpboardcastw_Vx_Wx);
339	/* Opcode VEX.66.0F38 0x7a - invalid. */
340	/* Opcode VEX.66.0F38 0x7b - invalid. */
341	/* Opcode VEX.66.0F38 0x7c - invalid. */
342	/* Opcode VEX.66.0F38 0x7d - invalid. */
343	/* Opcode VEX.66.0F38 0x7e - invalid. */
344	/* Opcode VEX.66.0F38 0x7f - invalid. */
345
346	/* Opcode VEX.66.0F38 0x80 - invalid (legacy only). */
347	/* Opcode VEX.66.0F38 0x81 - invalid (legacy only). */
348	/* Opcode VEX.66.0F38 0x82 - invalid (legacy only). */
349	/* Opcode VEX.66.0F38 0x83 - invalid. */
350	/* Opcode VEX.66.0F38 0x84 - invalid. */
351	/* Opcode VEX.66.0F38 0x85 - invalid. */
352	/* Opcode VEX.66.0F38 0x86 - invalid. */
353	/* Opcode VEX.66.0F38 0x87 - invalid. */
354	/* Opcode VEX.66.0F38 0x88 - invalid. */
355	/* Opcode VEX.66.0F38 0x89 - invalid. */
356	/* Opcode VEX.66.0F38 0x8a - invalid. */
357	/* Opcode VEX.66.0F38 0x8b - invalid. */
358	/** Opcode VEX.66.0F38 0x8c. */
359	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Vx_Hx_Mx);
360	/* Opcode VEX.66.0F38 0x8d - invalid. */
361	/** Opcode VEX.66.0F38 0x8e. */
362	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Mx_Vx_Hx);
363	/* Opcode VEX.66.0F38 0x8f - invalid. */
364
365	/** Opcode VEX.66.0F38 0x90 (vex only). */
366	FNIEMOP_STUB(iemOp_vgatherdd_q_Vx_Hx_Wx);
367	/** Opcode VEX.66.0F38 0x91 (vex only). */
368	FNIEMOP_STUB(iemOp_vgatherqd_q_Vx_Hx_Wx);
369	/** Opcode VEX.66.0F38 0x92 (vex only). */
370	FNIEMOP_STUB(iemOp_vgatherdps_d_Vx_Hx_Wx);
371	/** Opcode VEX.66.0F38 0x93 (vex only). */
372	FNIEMOP_STUB(iemOp_vgatherqps_d_Vx_Hx_Wx);
373	/* Opcode VEX.66.0F38 0x94 - invalid. */
374	/* Opcode VEX.66.0F38 0x95 - invalid. */
375	/** Opcode VEX.66.0F38 0x96 (vex only). */
376	FNIEMOP_STUB(iemOp_vfmaddsub132ps_q_Vx_Hx_Wx);
377	/** Opcode VEX.66.0F38 0x97 (vex only). */
378	FNIEMOP_STUB(iemOp_vfmsubadd132ps_d_Vx_Hx_Wx);
379	/** Opcode VEX.66.0F38 0x98 (vex only). */
380	FNIEMOP_STUB(iemOp_vfmadd132ps_d_Vx_Hx_Wx);
381	/** Opcode VEX.66.0F38 0x99 (vex only). */
382	FNIEMOP_STUB(iemOp_vfmadd132ss_d_Vx_Hx_Wx);
383	/** Opcode VEX.66.0F38 0x9a (vex only). */
384	FNIEMOP_STUB(iemOp_vfmsub132ps_d_Vx_Hx_Wx);
385	/** Opcode VEX.66.0F38 0x9b (vex only). */
386	FNIEMOP_STUB(iemOp_vfmsub132ss_d_Vx_Hx_Wx);
387	/** Opcode VEX.66.0F38 0x9c (vex only). */
388	FNIEMOP_STUB(iemOp_vfnmadd132ps_d_Vx_Hx_Wx);
389	/** Opcode VEX.66.0F38 0x9d (vex only). */
390	FNIEMOP_STUB(iemOp_vfnmadd132ss_d_Vx_Hx_Wx);
391	/** Opcode VEX.66.0F38 0x9e (vex only). */
392	FNIEMOP_STUB(iemOp_vfnmsub132ps_d_Vx_Hx_Wx);
393	/** Opcode VEX.66.0F38 0x9f (vex only). */
394	FNIEMOP_STUB(iemOp_vfnmsub132ss_d_Vx_Hx_Wx);
395
396	/* Opcode VEX.66.0F38 0xa0 - invalid. */
397	/* Opcode VEX.66.0F38 0xa1 - invalid. */
398	/* Opcode VEX.66.0F38 0xa2 - invalid. */
399	/* Opcode VEX.66.0F38 0xa3 - invalid. */
400	/* Opcode VEX.66.0F38 0xa4 - invalid. */
401	/* Opcode VEX.66.0F38 0xa5 - invalid. */
402	/** Opcode VEX.66.0F38 0xa6 (vex only). */
403	FNIEMOP_STUB(iemOp_vfmaddsub213ps_d_Vx_Hx_Wx);
404	/** Opcode VEX.66.0F38 0xa7 (vex only). */
405	FNIEMOP_STUB(iemOp_vfmsubadd213ps_d_Vx_Hx_Wx);
406	/** Opcode VEX.66.0F38 0xa8 (vex only). */
407	FNIEMOP_STUB(iemOp_vfmadd213ps_d_Vx_Hx_Wx);
408	/** Opcode VEX.66.0F38 0xa9 (vex only). */
409	FNIEMOP_STUB(iemOp_vfmadd213ss_d_Vx_Hx_Wx);
410	/** Opcode VEX.66.0F38 0xaa (vex only). */
411	FNIEMOP_STUB(iemOp_vfmsub213ps_d_Vx_Hx_Wx);
412	/** Opcode VEX.66.0F38 0xab (vex only). */
413	FNIEMOP_STUB(iemOp_vfmsub213ss_d_Vx_Hx_Wx);
414	/** Opcode VEX.66.0F38 0xac (vex only). */
415	FNIEMOP_STUB(iemOp_vfnmadd213ps_d_Vx_Hx_Wx);
416	/** Opcode VEX.66.0F38 0xad (vex only). */
417	FNIEMOP_STUB(iemOp_vfnmadd213ss_d_Vx_Hx_Wx);
418	/** Opcode VEX.66.0F38 0xae (vex only). */
419	FNIEMOP_STUB(iemOp_vfnmsub213ps_d_Vx_Hx_Wx);
420	/** Opcode VEX.66.0F38 0xaf (vex only). */
421	FNIEMOP_STUB(iemOp_vfnmsub213ss_d_Vx_Hx_Wx);
422
423	/* Opcode VEX.66.0F38 0xb0 - invalid. */
424	/* Opcode VEX.66.0F38 0xb1 - invalid. */
425	/* Opcode VEX.66.0F38 0xb2 - invalid. */
426	/* Opcode VEX.66.0F38 0xb3 - invalid. */
427	/* Opcode VEX.66.0F38 0xb4 - invalid. */
428	/* Opcode VEX.66.0F38 0xb5 - invalid. */
429	/** Opcode VEX.66.0F38 0xb6 (vex only). */
430	FNIEMOP_STUB(iemOp_vfmaddsub231ps_d_Vx_Hx_Wx);
431	/** Opcode VEX.66.0F38 0xb7 (vex only). */
432	FNIEMOP_STUB(iemOp_vfmsubadd231ps_d_Vx_Hx_Wx);
433	/** Opcode VEX.66.0F38 0xb8 (vex only). */
434	FNIEMOP_STUB(iemOp_vfmadd231ps_d_Vx_Hx_Wx);
435	/** Opcode VEX.66.0F38 0xb9 (vex only). */
436	FNIEMOP_STUB(iemOp_vfmadd231ss_d_Vx_Hx_Wx);
437	/** Opcode VEX.66.0F38 0xba (vex only). */
438	FNIEMOP_STUB(iemOp_vfmsub231ps_d_Vx_Hx_Wx);
439	/** Opcode VEX.66.0F38 0xbb (vex only). */
440	FNIEMOP_STUB(iemOp_vfmsub231ss_d_Vx_Hx_Wx);
441	/** Opcode VEX.66.0F38 0xbc (vex only). */
442	FNIEMOP_STUB(iemOp_vfnmadd231ps_d_Vx_Hx_Wx);
443	/** Opcode VEX.66.0F38 0xbd (vex only). */
444	FNIEMOP_STUB(iemOp_vfnmadd231ss_d_Vx_Hx_Wx);
445	/** Opcode VEX.66.0F38 0xbe (vex only). */
446	FNIEMOP_STUB(iemOp_vfnmsub231ps_d_Vx_Hx_Wx);
447	/** Opcode VEX.66.0F38 0xbf (vex only). */
448	FNIEMOP_STUB(iemOp_vfnmsub231ss_d_Vx_Hx_Wx);
449
450	/* Opcode VEX.0F38 0xc0 - invalid. */
451	/* Opcode VEX.66.0F38 0xc0 - invalid. */
452	/* Opcode VEX.0F38 0xc1 - invalid. */
453	/* Opcode VEX.66.0F38 0xc1 - invalid. */
454	/* Opcode VEX.0F38 0xc2 - invalid. */
455	/* Opcode VEX.66.0F38 0xc2 - invalid. */
456	/* Opcode VEX.0F38 0xc3 - invalid. */
457	/* Opcode VEX.66.0F38 0xc3 - invalid. */
458	/* Opcode VEX.0F38 0xc4 - invalid. */
459	/* Opcode VEX.66.0F38 0xc4 - invalid. */
460	/* Opcode VEX.0F38 0xc5 - invalid. */
461	/* Opcode VEX.66.0F38 0xc5 - invalid. */
462	/* Opcode VEX.0F38 0xc6 - invalid. */
463	/* Opcode VEX.66.0F38 0xc6 - invalid. */
464	/* Opcode VEX.0F38 0xc7 - invalid. */
465	/* Opcode VEX.66.0F38 0xc7 - invalid. */
466	/** Opcode VEX.0F38 0xc8. */
467	FNIEMOP_STUB(iemOp_vsha1nexte_Vdq_Wdq);
468	/* Opcode VEX.66.0F38 0xc8 - invalid. */
469	/** Opcode VEX.0F38 0xc9. */
470	FNIEMOP_STUB(iemOp_vsha1msg1_Vdq_Wdq);
471	/* Opcode VEX.66.0F38 0xc9 - invalid. */
472	/** Opcode VEX.0F38 0xca. */
473	FNIEMOP_STUB(iemOp_vsha1msg2_Vdq_Wdq);
474	/* Opcode VEX.66.0F38 0xca - invalid. */
475	/** Opcode VEX.0F38 0xcb. */
476	FNIEMOP_STUB(iemOp_vsha256rnds2_Vdq_Wdq);
477	/* Opcode VEX.66.0F38 0xcb - invalid. */
478	/** Opcode VEX.0F38 0xcc. */
479	FNIEMOP_STUB(iemOp_vsha256msg1_Vdq_Wdq);
480	/* Opcode VEX.66.0F38 0xcc - invalid. */
481	/** Opcode VEX.0F38 0xcd. */
482	FNIEMOP_STUB(iemOp_vsha256msg2_Vdq_Wdq);
483	/* Opcode VEX.66.0F38 0xcd - invalid. */
484	/* Opcode VEX.0F38 0xce - invalid. */
485	/* Opcode VEX.66.0F38 0xce - invalid. */
486	/* Opcode VEX.0F38 0xcf - invalid. */
487	/* Opcode VEX.66.0F38 0xcf - invalid. */
488
489	/* Opcode VEX.66.0F38 0xd0 - invalid. */
490	/* Opcode VEX.66.0F38 0xd1 - invalid. */
491	/* Opcode VEX.66.0F38 0xd2 - invalid. */
492	/* Opcode VEX.66.0F38 0xd3 - invalid. */
493	/* Opcode VEX.66.0F38 0xd4 - invalid. */
494	/* Opcode VEX.66.0F38 0xd5 - invalid. */
495	/* Opcode VEX.66.0F38 0xd6 - invalid. */
496	/* Opcode VEX.66.0F38 0xd7 - invalid. */
497	/* Opcode VEX.66.0F38 0xd8 - invalid. */
498	/* Opcode VEX.66.0F38 0xd9 - invalid. */
499	/* Opcode VEX.66.0F38 0xda - invalid. */
500	/** Opcode VEX.66.0F38 0xdb. */
501	FNIEMOP_STUB(iemOp_vaesimc_Vdq_Wdq);
502	/** Opcode VEX.66.0F38 0xdc. */
503	FNIEMOP_STUB(iemOp_vaesenc_Vdq_Wdq);
504	/** Opcode VEX.66.0F38 0xdd. */
505	FNIEMOP_STUB(iemOp_vaesenclast_Vdq_Wdq);
506	/** Opcode VEX.66.0F38 0xde. */
507	FNIEMOP_STUB(iemOp_vaesdec_Vdq_Wdq);
508	/** Opcode VEX.66.0F38 0xdf. */
509	FNIEMOP_STUB(iemOp_vaesdeclast_Vdq_Wdq);
510
511	/* Opcode VEX.66.0F38 0xe0 - invalid. */
512	/* Opcode VEX.66.0F38 0xe1 - invalid. */
513	/* Opcode VEX.66.0F38 0xe2 - invalid. */
514	/* Opcode VEX.66.0F38 0xe3 - invalid. */
515	/* Opcode VEX.66.0F38 0xe4 - invalid. */
516	/* Opcode VEX.66.0F38 0xe5 - invalid. */
517	/* Opcode VEX.66.0F38 0xe6 - invalid. */
518	/* Opcode VEX.66.0F38 0xe7 - invalid. */
519	/* Opcode VEX.66.0F38 0xe8 - invalid. */
520	/* Opcode VEX.66.0F38 0xe9 - invalid. */
521	/* Opcode VEX.66.0F38 0xea - invalid. */
522	/* Opcode VEX.66.0F38 0xeb - invalid. */
523	/* Opcode VEX.66.0F38 0xec - invalid. */
524	/* Opcode VEX.66.0F38 0xed - invalid. */
525	/* Opcode VEX.66.0F38 0xee - invalid. */
526	/* Opcode VEX.66.0F38 0xef - invalid. */
527
528
529	/* Opcode VEX.0F38 0xf0 - invalid (legacy only). */
530	/* Opcode VEX.66.0F38 0xf0 - invalid (legacy only). */
531	/* Opcode VEX.F3.0F38 0xf0 - invalid. */
532	/* Opcode VEX.F2.0F38 0xf0 - invalid (legacy only). */
533
534	/* Opcode VEX.0F38 0xf1 - invalid (legacy only). */
535	/* Opcode VEX.66.0F38 0xf1 - invalid (legacy only). */
536	/* Opcode VEX.F3.0F38 0xf1 - invalid. */
537	/* Opcode VEX.F2.0F38 0xf1 - invalid (legacy only). */
538
539	/** Opcode VEX.0F38 0xf2 - ANDN (vex only). */
540	FNIEMOP_DEF(iemOp_andn_Gy_By_Ey)
541	{
542	IEMOP_MNEMONIC3(VEX_RVM, ANDN, andn, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
543	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1)
544	return iemOp_InvalidNeedRM(pVCpu);
545	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF);
546	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
547	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
548	{
549	/*
550	* Register, register.
551	*/
552	IEMOP_HLP_DONE_VEX_DECODING_L0();
553	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
554	{
555	IEM_MC_BEGIN(4, 0);
556	IEM_MC_ARG(uint64_t *, pDst, 0);
557	IEM_MC_ARG(uint64_t, uSrc1, 1);
558	IEM_MC_ARG(uint64_t, uSrc2, 2);
559	IEM_MC_ARG(uint32_t *, pEFlags, 3);
560	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
561	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
562	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
563	IEM_MC_REF_EFLAGS(pEFlags);
564	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
565	pDst, uSrc1, uSrc2, pEFlags);
566	IEM_MC_ADVANCE_RIP();
567	IEM_MC_END();
568	}
569	else
570	{
571	IEM_MC_BEGIN(4, 0);
572	IEM_MC_ARG(uint32_t *, pDst, 0);
573	IEM_MC_ARG(uint32_t, uSrc1, 1);
574	IEM_MC_ARG(uint32_t, uSrc2, 2);
575	IEM_MC_ARG(uint32_t *, pEFlags, 3);
576	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
577	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
578	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
579	IEM_MC_REF_EFLAGS(pEFlags);
580	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
581	pDst, uSrc1, uSrc2, pEFlags);
582	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
583	IEM_MC_ADVANCE_RIP();
584	IEM_MC_END();
585	}
586	}
587	else
588	{
589	/*
590	* Register, memory.
591	*/
592	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
593	{
594	IEM_MC_BEGIN(4, 1);
595	IEM_MC_ARG(uint64_t *, pDst, 0);
596	IEM_MC_ARG(uint64_t, uSrc1, 1);
597	IEM_MC_ARG(uint64_t, uSrc2, 2);
598	IEM_MC_ARG(uint32_t *, pEFlags, 3);
599	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
600	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
601	IEMOP_HLP_DONE_VEX_DECODING_L0();
602	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
603	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
604	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
605	IEM_MC_REF_EFLAGS(pEFlags);
606	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
607	pDst, uSrc1, uSrc2, pEFlags);
608	IEM_MC_ADVANCE_RIP();
609	IEM_MC_END();
610	}
611	else
612	{
613	IEM_MC_BEGIN(4, 1);
614	IEM_MC_ARG(uint32_t *, pDst, 0);
615	IEM_MC_ARG(uint32_t, uSrc1, 1);
616	IEM_MC_ARG(uint32_t, uSrc2, 2);
617	IEM_MC_ARG(uint32_t *, pEFlags, 3);
618	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
619	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
620	IEMOP_HLP_DONE_VEX_DECODING_L0();
621	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
622	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
623	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
624	IEM_MC_REF_EFLAGS(pEFlags);
625	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
626	pDst, uSrc1, uSrc2, pEFlags);
627	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
628	IEM_MC_ADVANCE_RIP();
629	IEM_MC_END();
630	}
631	}
632	return VINF_SUCCESS;
633	}
634
635	/* Opcode VEX.66.0F38 0xf2 - invalid. */
636	/* Opcode VEX.F3.0F38 0xf2 - invalid. */
637	/* Opcode VEX.F2.0F38 0xf2 - invalid. */
638
639
640	/* Opcode VEX.0F38 0xf3 - invalid. */
641	/* Opcode VEX.66.0F38 0xf3 - invalid. */
642
643	/* Opcode VEX.F3.0F38 0xf3 /0 - invalid. */
644
645	/** Body for the vex group 17 instructions. */
646	#define IEMOP_BODY_By_Ey(a_Instr) \
647	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1) \
648	return iemOp_InvalidWithRM(pVCpu, bRm); /* decode memory variant? */ \
649	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF); \
650	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) \
651	{ \
652	/* \
653	* Register, register. \
654	*/ \
655	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
656	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
657	{ \
658	IEM_MC_BEGIN(3, 0); \
659	IEM_MC_ARG(uint64_t *, pDst, 0); \
660	IEM_MC_ARG(uint64_t, uSrc, 1); \
661	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
662	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
663	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
664	IEM_MC_REF_EFLAGS(pEFlags); \
665	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
666	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
667	IEM_MC_ADVANCE_RIP(); \
668	IEM_MC_END(); \
669	} \
670	else \
671	{ \
672	IEM_MC_BEGIN(3, 0); \
673	IEM_MC_ARG(uint32_t *, pDst, 0); \
674	IEM_MC_ARG(uint32_t, uSrc, 1); \
675	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
676	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
677	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
678	IEM_MC_REF_EFLAGS(pEFlags); \
679	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
680	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
681	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
682	IEM_MC_ADVANCE_RIP(); \
683	IEM_MC_END(); \
684	} \
685	} \
686	else \
687	{ \
688	/* \
689	* Register, memory. \
690	*/ \
691	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
692	{ \
693	IEM_MC_BEGIN(3, 1); \
694	IEM_MC_ARG(uint64_t *, pDst, 0); \
695	IEM_MC_ARG(uint64_t, uSrc, 1); \
696	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
697	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
698	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
699	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
700	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
701	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
702	IEM_MC_REF_EFLAGS(pEFlags); \
703	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
704	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
705	IEM_MC_ADVANCE_RIP(); \
706	IEM_MC_END(); \
707	} \
708	else \
709	{ \
710	IEM_MC_BEGIN(3, 1); \
711	IEM_MC_ARG(uint32_t *, pDst, 0); \
712	IEM_MC_ARG(uint32_t, uSrc, 1); \
713	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
714	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
715	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
716	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
717	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
718	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
719	IEM_MC_REF_EFLAGS(pEFlags); \
720	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
721	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
722	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
723	IEM_MC_ADVANCE_RIP(); \
724	IEM_MC_END(); \
725	} \
726	} \
727	return VINF_SUCCESS
728
729
730	/* Opcode VEX.F3.0F38 0xf3 /1. */
731	/** @opcode /1
732	* @opmaps vexgrp17 */
733	FNIEMOP_DEF_1(iemOp_VGrp17_blsr_By_Ey, uint8_t, bRm)
734	{
735	IEMOP_MNEMONIC2(VEX_VM, BLSR, blsr, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
736	IEMOP_BODY_By_Ey(blsr);
737	}
738
739
740	/* Opcode VEX.F3.0F38 0xf3 /2. */
741	/** @opcode /2
742	* @opmaps vexgrp17 */
743	FNIEMOP_DEF_1(iemOp_VGrp17_blsmsk_By_Ey, uint8_t, bRm)
744	{
745	IEMOP_MNEMONIC2(VEX_VM, BLSMSK, blsmsk, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
746	IEMOP_BODY_By_Ey(blsmsk);
747	}
748
749
750	/* Opcode VEX.F3.0F38 0xf3 /3. */
751	/** @opcode /3
752	* @opmaps vexgrp17 */
753	FNIEMOP_DEF_1(iemOp_VGrp17_blsi_By_Ey, uint8_t, bRm)
754	{
755	IEMOP_MNEMONIC2(VEX_VM, BLSI, blsi, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
756	IEMOP_BODY_By_Ey(blsi);
757	}
758
759
760	/* Opcode VEX.F3.0F38 0xf3 /4 - invalid. */
761	/* Opcode VEX.F3.0F38 0xf3 /5 - invalid. */
762	/* Opcode VEX.F3.0F38 0xf3 /6 - invalid. */
763	/* Opcode VEX.F3.0F38 0xf3 /7 - invalid. */
764
765	/**
766	* Group 17 jump table for the VEX.F3 variant.
767	*/
768	IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =
769	{
770	/* /0 */ iemOp_InvalidWithRM,
771	/* /1 */ iemOp_VGrp17_blsr_By_Ey,
772	/* /2 */ iemOp_VGrp17_blsmsk_By_Ey,
773	/* /3 */ iemOp_VGrp17_blsi_By_Ey,
774	/* /4 */ iemOp_InvalidWithRM,
775	/* /5 */ iemOp_InvalidWithRM,
776	/* /6 */ iemOp_InvalidWithRM,
777	/* /7 */ iemOp_InvalidWithRM
778	};
779	AssertCompile(RT_ELEMENTS(g_apfnVexGroup17_f3) == 8);
780
781	/** Opcode VEX.F3.0F38 0xf3 - invalid (vex only - group 17). */
782	FNIEMOP_DEF(iemOp_VGrp17_f3)
783	{
784	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
785	return FNIEMOP_CALL_1(g_apfnVexGroup17_f3[((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)], bRm);
786	}
787
788	/* Opcode VEX.F2.0F38 0xf3 - invalid (vex only - group 17). */
789
790
791	/* Opcode VEX.0F38 0xf4 - invalid. */
792	/* Opcode VEX.66.0F38 0xf4 - invalid. */
793	/* Opcode VEX.F3.0F38 0xf4 - invalid. */
794	/* Opcode VEX.F2.0F38 0xf4 - invalid. */
795
796	/** Body for BZHI, BEXTR, ++; assumes VEX.L must be 0. */
797	#define IEMOP_BODY_Gy_Ey_By(a_Instr, a_fFeatureMember, a_fUndefFlags) \
798	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
799	return iemOp_InvalidNeedRM(pVCpu); \
800	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
801	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
802	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) \
803	{ \
804	/* \
805	* Register, register. \
806	*/ \
807	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
808	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
809	{ \
810	IEM_MC_BEGIN(4, 0); \
811	IEM_MC_ARG(uint64_t *, pDst, 0); \
812	IEM_MC_ARG(uint64_t, uSrc1, 1); \
813	IEM_MC_ARG(uint64_t, uSrc2, 2); \
814	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
815	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
816	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
817	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
818	IEM_MC_REF_EFLAGS(pEFlags); \
819	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
820	iemAImpl_ ## a_Instr ## _u64_fallback), \
821	pDst, uSrc1, uSrc2, pEFlags); \
822	IEM_MC_ADVANCE_RIP(); \
823	IEM_MC_END(); \
824	} \
825	else \
826	{ \
827	IEM_MC_BEGIN(4, 0); \
828	IEM_MC_ARG(uint32_t *, pDst, 0); \
829	IEM_MC_ARG(uint32_t, uSrc1, 1); \
830	IEM_MC_ARG(uint32_t, uSrc2, 2); \
831	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
832	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
833	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
834	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
835	IEM_MC_REF_EFLAGS(pEFlags); \
836	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
837	iemAImpl_ ## a_Instr ## _u32_fallback), \
838	pDst, uSrc1, uSrc2, pEFlags); \
839	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
840	IEM_MC_ADVANCE_RIP(); \
841	IEM_MC_END(); \
842	} \
843	} \
844	else \
845	{ \
846	/* \
847	* Register, memory. \
848	*/ \
849	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
850	{ \
851	IEM_MC_BEGIN(4, 1); \
852	IEM_MC_ARG(uint64_t *, pDst, 0); \
853	IEM_MC_ARG(uint64_t, uSrc1, 1); \
854	IEM_MC_ARG(uint64_t, uSrc2, 2); \
855	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
856	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
857	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
858	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
859	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
860	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
861	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
862	IEM_MC_REF_EFLAGS(pEFlags); \
863	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
864	iemAImpl_ ## a_Instr ## _u64_fallback), \
865	pDst, uSrc1, uSrc2, pEFlags); \
866	IEM_MC_ADVANCE_RIP(); \
867	IEM_MC_END(); \
868	} \
869	else \
870	{ \
871	IEM_MC_BEGIN(4, 1); \
872	IEM_MC_ARG(uint32_t *, pDst, 0); \
873	IEM_MC_ARG(uint32_t, uSrc1, 1); \
874	IEM_MC_ARG(uint32_t, uSrc2, 2); \
875	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
876	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
877	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
878	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
879	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
880	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
881	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
882	IEM_MC_REF_EFLAGS(pEFlags); \
883	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
884	iemAImpl_ ## a_Instr ## _u32_fallback), \
885	pDst, uSrc1, uSrc2, pEFlags); \
886	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
887	IEM_MC_ADVANCE_RIP(); \
888	IEM_MC_END(); \
889	} \
890	} \
891	return VINF_SUCCESS
892
893	/** Body for SARX, SHLX, SHRX; assumes VEX.L must be 0. */
894	#define IEMOP_BODY_Gy_Ey_By_NoEflags(a_Instr, a_fFeatureMember, a_fUndefFlags) \
895	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
896	return iemOp_InvalidNeedRM(pVCpu); \
897	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
898	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
899	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) \
900	{ \
901	/* \
902	* Register, register. \
903	*/ \
904	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
905	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
906	{ \
907	IEM_MC_BEGIN(3, 0); \
908	IEM_MC_ARG(uint64_t *, pDst, 0); \
909	IEM_MC_ARG(uint64_t, uSrc1, 1); \
910	IEM_MC_ARG(uint64_t, uSrc2, 2); \
911	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
912	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
913	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
914	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
915	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
916	IEM_MC_ADVANCE_RIP(); \
917	IEM_MC_END(); \
918	} \
919	else \
920	{ \
921	IEM_MC_BEGIN(3, 0); \
922	IEM_MC_ARG(uint32_t *, pDst, 0); \
923	IEM_MC_ARG(uint32_t, uSrc1, 1); \
924	IEM_MC_ARG(uint32_t, uSrc2, 2); \
925	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
926	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
927	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
928	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
929	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
930	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
931	IEM_MC_ADVANCE_RIP(); \
932	IEM_MC_END(); \
933	} \
934	} \
935	else \
936	{ \
937	/* \
938	* Register, memory. \
939	*/ \
940	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
941	{ \
942	IEM_MC_BEGIN(3, 1); \
943	IEM_MC_ARG(uint64_t *, pDst, 0); \
944	IEM_MC_ARG(uint64_t, uSrc1, 1); \
945	IEM_MC_ARG(uint64_t, uSrc2, 2); \
946	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
947	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
948	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
949	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
950	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
951	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
952	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
953	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
954	IEM_MC_ADVANCE_RIP(); \
955	IEM_MC_END(); \
956	} \
957	else \
958	{ \
959	IEM_MC_BEGIN(3, 1); \
960	IEM_MC_ARG(uint32_t *, pDst, 0); \
961	IEM_MC_ARG(uint32_t, uSrc1, 1); \
962	IEM_MC_ARG(uint32_t, uSrc2, 2); \
963	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
964	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
965	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
966	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
967	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
968	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
969	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
970	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
971	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
972	IEM_MC_ADVANCE_RIP(); \
973	IEM_MC_END(); \
974	} \
975	} \
976	return VINF_SUCCESS
977
978	/** Opcode VEX.0F38 0xf5 (vex only). */
979	FNIEMOP_DEF(iemOp_bzhi_Gy_Ey_By)
980	{
981	IEMOP_MNEMONIC3(VEX_RMV, BZHI, bzhi, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
982	IEMOP_BODY_Gy_Ey_By(bzhi, fBmi2, X86_EFL_AF \| X86_EFL_PF);
983	}
984
985	/* Opcode VEX.66.0F38 0xf5 - invalid. */
986
987	/** Body for PDEP and PEXT (similar to ANDN, except no EFLAGS). */
988	#define IEMOP_BODY_Gy_By_Ey_NoEflags(a_Instr, a_fFeatureMember) \
989	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
990	return iemOp_InvalidNeedRM(pVCpu); \
991	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
992	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) \
993	{ \
994	/* \
995	* Register, register. \
996	*/ \
997	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
998	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
999	{ \
1000	IEM_MC_BEGIN(3, 0); \
1001	IEM_MC_ARG(uint64_t *, pDst, 0); \
1002	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1003	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1004	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1005	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1006	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1007	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1008	iemAImpl_ ## a_Instr ## _u64, \
1009	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1010	IEM_MC_ADVANCE_RIP(); \
1011	IEM_MC_END(); \
1012	} \
1013	else \
1014	{ \
1015	IEM_MC_BEGIN(3, 0); \
1016	IEM_MC_ARG(uint32_t *, pDst, 0); \
1017	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1018	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1019	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1020	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1021	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1022	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1023	iemAImpl_ ## a_Instr ## _u32, \
1024	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1025	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1026	IEM_MC_ADVANCE_RIP(); \
1027	IEM_MC_END(); \
1028	} \
1029	} \
1030	else \
1031	{ \
1032	/* \
1033	* Register, memory. \
1034	*/ \
1035	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1036	{ \
1037	IEM_MC_BEGIN(3, 1); \
1038	IEM_MC_ARG(uint64_t *, pDst, 0); \
1039	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1040	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1041	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1042	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1043	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1044	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1045	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1046	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1047	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1048	iemAImpl_ ## a_Instr ## _u64, \
1049	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1050	IEM_MC_ADVANCE_RIP(); \
1051	IEM_MC_END(); \
1052	} \
1053	else \
1054	{ \
1055	IEM_MC_BEGIN(3, 1); \
1056	IEM_MC_ARG(uint32_t *, pDst, 0); \
1057	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1058	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1059	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1060	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1061	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1062	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1063	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1064	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1065	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1066	iemAImpl_ ## a_Instr ## _u32, \
1067	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1068	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1069	IEM_MC_ADVANCE_RIP(); \
1070	IEM_MC_END(); \
1071	} \
1072	} \
1073	return VINF_SUCCESS;
1074
1075
1076	/** Opcode VEX.F3.0F38 0xf5 (vex only). */
1077	FNIEMOP_DEF(iemOp_pext_Gy_By_Ey)
1078	{
1079	IEMOP_MNEMONIC3(VEX_RVM, PEXT, pext, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1080	IEMOP_BODY_Gy_By_Ey_NoEflags(pext, fBmi2);
1081	}
1082
1083
1084	/** Opcode VEX.F2.0F38 0xf5 (vex only). */
1085	FNIEMOP_DEF(iemOp_pdep_Gy_By_Ey)
1086	{
1087	IEMOP_MNEMONIC3(VEX_RVM, PDEP, pdep, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1088	IEMOP_BODY_Gy_By_Ey_NoEflags(pdep, fBmi2);
1089	}
1090
1091
1092	/* Opcode VEX.0F38 0xf6 - invalid. */
1093	/* Opcode VEX.66.0F38 0xf6 - invalid (legacy only). */
1094	/* Opcode VEX.F3.0F38 0xf6 - invalid (legacy only). */
1095	/* Opcode VEX.F2.0F38 0xf6 - invalid (vex only). */
1096	FNIEMOP_STUB(iemOp_mulx_By_Gy_rDX_Ey);
1097
1098
1099	/** Opcode VEX.0F38 0xf7 (vex only). */
1100	FNIEMOP_DEF(iemOp_bextr_Gy_Ey_By)
1101	{
1102	IEMOP_MNEMONIC3(VEX_RMV, BEXTR, bextr, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1103	IEMOP_BODY_Gy_Ey_By(bextr, fBmi1, X86_EFL_SF \| X86_EFL_AF \| X86_EFL_PF);
1104	}
1105
1106
1107	/** Opcode VEX.66.0F38 0xf7 (vex only). */
1108	FNIEMOP_DEF(iemOp_shlx_Gy_Ey_By)
1109	{
1110	IEMOP_MNEMONIC3(VEX_RMV, SHLX, shlx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1111	IEMOP_BODY_Gy_Ey_By_NoEflags(shlx, fBmi2, 0);
1112	}
1113
1114
1115	/** Opcode VEX.F3.0F38 0xf7 (vex only). */
1116	FNIEMOP_DEF(iemOp_sarx_Gy_Ey_By)
1117	{
1118	IEMOP_MNEMONIC3(VEX_RMV, SARX, sarx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1119	IEMOP_BODY_Gy_Ey_By_NoEflags(sarx, fBmi2, 0);
1120	}
1121
1122
1123	/** Opcode VEX.F2.0F38 0xf7 (vex only). */
1124	FNIEMOP_DEF(iemOp_shrx_Gy_Ey_By)
1125	{
1126	IEMOP_MNEMONIC3(VEX_RMV, SHRX, shrx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1127	IEMOP_BODY_Gy_Ey_By_NoEflags(shrx, fBmi2, 0);
1128	}
1129
1130	/* Opcode VEX.0F38 0xf8 - invalid. */
1131	/* Opcode VEX.66.0F38 0xf8 - invalid. */
1132	/* Opcode VEX.F3.0F38 0xf8 - invalid. */
1133	/* Opcode VEX.F2.0F38 0xf8 - invalid. */
1134
1135	/* Opcode VEX.0F38 0xf9 - invalid. */
1136	/* Opcode VEX.66.0F38 0xf9 - invalid. */
1137	/* Opcode VEX.F3.0F38 0xf9 - invalid. */
1138	/* Opcode VEX.F2.0F38 0xf9 - invalid. */
1139
1140	/* Opcode VEX.0F38 0xfa - invalid. */
1141	/* Opcode VEX.66.0F38 0xfa - invalid. */
1142	/* Opcode VEX.F3.0F38 0xfa - invalid. */
1143	/* Opcode VEX.F2.0F38 0xfa - invalid. */
1144
1145	/* Opcode VEX.0F38 0xfb - invalid. */
1146	/* Opcode VEX.66.0F38 0xfb - invalid. */
1147	/* Opcode VEX.F3.0F38 0xfb - invalid. */
1148	/* Opcode VEX.F2.0F38 0xfb - invalid. */
1149
1150	/* Opcode VEX.0F38 0xfc - invalid. */
1151	/* Opcode VEX.66.0F38 0xfc - invalid. */
1152	/* Opcode VEX.F3.0F38 0xfc - invalid. */
1153	/* Opcode VEX.F2.0F38 0xfc - invalid. */
1154
1155	/* Opcode VEX.0F38 0xfd - invalid. */
1156	/* Opcode VEX.66.0F38 0xfd - invalid. */
1157	/* Opcode VEX.F3.0F38 0xfd - invalid. */
1158	/* Opcode VEX.F2.0F38 0xfd - invalid. */
1159
1160	/* Opcode VEX.0F38 0xfe - invalid. */
1161	/* Opcode VEX.66.0F38 0xfe - invalid. */
1162	/* Opcode VEX.F3.0F38 0xfe - invalid. */
1163	/* Opcode VEX.F2.0F38 0xfe - invalid. */
1164
1165	/* Opcode VEX.0F38 0xff - invalid. */
1166	/* Opcode VEX.66.0F38 0xff - invalid. */
1167	/* Opcode VEX.F3.0F38 0xff - invalid. */
1168	/* Opcode VEX.F2.0F38 0xff - invalid. */
1169
1170
1171	/**
1172	* VEX opcode map \#2.
1173	*
1174	* @sa g_apfnThreeByte0f38
1175	*/
1176	IEM_STATIC const PFNIEMOP g_apfnVexMap2[] =
1177	{
1178	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1179	/* 0x00 */ iemOp_InvalidNeedRM, iemOp_vpshufb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1180	/* 0x01 */ iemOp_InvalidNeedRM, iemOp_vphaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1181	/* 0x02 */ iemOp_InvalidNeedRM, iemOp_vphaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1182	/* 0x03 */ iemOp_InvalidNeedRM, iemOp_vphaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1183	/* 0x04 */ iemOp_InvalidNeedRM, iemOp_vpmaddubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1184	/* 0x05 */ iemOp_InvalidNeedRM, iemOp_vphsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1185	/* 0x06 */ iemOp_InvalidNeedRM, iemOp_vphsubdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1186	/* 0x07 */ iemOp_InvalidNeedRM, iemOp_vphsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1187	/* 0x08 */ iemOp_InvalidNeedRM, iemOp_vpsignb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1188	/* 0x09 */ iemOp_InvalidNeedRM, iemOp_vpsignw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1189	/* 0x0a */ iemOp_InvalidNeedRM, iemOp_vpsignd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1190	/* 0x0b */ iemOp_InvalidNeedRM, iemOp_vpmulhrsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1191	/* 0x0c */ iemOp_InvalidNeedRM, iemOp_vpermilps_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1192	/* 0x0d */ iemOp_InvalidNeedRM, iemOp_vpermilpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1193	/* 0x0e */ iemOp_InvalidNeedRM, iemOp_vtestps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1194	/* 0x0f */ iemOp_InvalidNeedRM, iemOp_vtestpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1195
1196	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRM),
1197	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
1198	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
1199	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
1200	/* 0x14 */ IEMOP_X4(iemOp_InvalidNeedRM),
1201	/* 0x15 */ IEMOP_X4(iemOp_InvalidNeedRM),
1202	/* 0x16 */ iemOp_InvalidNeedRM, iemOp_vpermps_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1203	/* 0x17 */ iemOp_InvalidNeedRM, iemOp_vptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1204	/* 0x18 */ iemOp_InvalidNeedRM, iemOp_vbroadcastss_Vx_Wd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1205	/* 0x19 */ iemOp_InvalidNeedRM, iemOp_vbroadcastsd_Vqq_Wq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1206	/* 0x1a */ iemOp_InvalidNeedRM, iemOp_vbroadcastf128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1207	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
1208	/* 0x1c */ iemOp_InvalidNeedRM, iemOp_vpabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1209	/* 0x1d */ iemOp_InvalidNeedRM, iemOp_vpabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1210	/* 0x1e */ iemOp_InvalidNeedRM, iemOp_vpabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1211	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
1212
1213	/* 0x20 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1214	/* 0x21 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1215	/* 0x22 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1216	/* 0x23 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1217	/* 0x24 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1218	/* 0x25 */ iemOp_InvalidNeedRM, iemOp_vpmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1219	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
1220	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
1221	/* 0x28 */ iemOp_InvalidNeedRM, iemOp_vpmuldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1222	/* 0x29 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1223	/* 0x2a */ iemOp_InvalidNeedRM, iemOp_vmovntdqa_Vx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1224	/* 0x2b */ iemOp_InvalidNeedRM, iemOp_vpackusdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1225	/* 0x2c */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1226	/* 0x2d */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1227	/* 0x2e */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1228	/* 0x2f */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1229
1230	/* 0x30 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1231	/* 0x31 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1232	/* 0x32 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1233	/* 0x33 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1234	/* 0x34 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1235	/* 0x35 */ iemOp_InvalidNeedRM, iemOp_vpmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1236	/* 0x36 */ iemOp_InvalidNeedRM, iemOp_vpermd_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1237	/* 0x37 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1238	/* 0x38 */ iemOp_InvalidNeedRM, iemOp_vpminsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1239	/* 0x39 */ iemOp_InvalidNeedRM, iemOp_vpminsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1240	/* 0x3a */ iemOp_InvalidNeedRM, iemOp_vpminuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1241	/* 0x3b */ iemOp_InvalidNeedRM, iemOp_vpminud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1242	/* 0x3c */ iemOp_InvalidNeedRM, iemOp_vpmaxsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1243	/* 0x3d */ iemOp_InvalidNeedRM, iemOp_vpmaxsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1244	/* 0x3e */ iemOp_InvalidNeedRM, iemOp_vpmaxuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1245	/* 0x3f */ iemOp_InvalidNeedRM, iemOp_vpmaxud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1246
1247	/* 0x40 */ iemOp_InvalidNeedRM, iemOp_vpmulld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1248	/* 0x41 */ iemOp_InvalidNeedRM, iemOp_vphminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1249	/* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
1250	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
1251	/* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
1252	/* 0x45 */ iemOp_InvalidNeedRM, iemOp_vpsrlvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1253	/* 0x46 */ iemOp_InvalidNeedRM, iemOp_vsravd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1254	/* 0x47 */ iemOp_InvalidNeedRM, iemOp_vpsllvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1255	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
1256	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
1257	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
1258	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
1259	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
1260	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
1261	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
1262	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
1263
1264	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
1265	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
1266	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
1267	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
1268	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
1269	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
1270	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
1271	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
1272	/* 0x58 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1273	/* 0x59 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1274	/* 0x5a */ iemOp_InvalidNeedRM, iemOp_vbroadcasti128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1275	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
1276	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
1277	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
1278	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
1279	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
1280
1281	/* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
1282	/* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
1283	/* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
1284	/* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
1285	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
1286	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
1287	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
1288	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
1289	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
1290	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
1291	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
1292	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
1293	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
1294	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
1295	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
1296	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
1297
1298	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
1299	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
1300	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
1301	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
1302	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
1303	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
1304	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
1305	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
1306	/* 0x78 */ iemOp_InvalidNeedRM, iemOp_vpboardcastb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1307	/* 0x79 */ iemOp_InvalidNeedRM, iemOp_vpboardcastw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1308	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
1309	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
1310	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
1311	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
1312	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
1313	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
1314
1315	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
1316	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
1317	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
1318	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
1319	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
1320	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
1321	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
1322	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
1323	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
1324	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
1325	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
1326	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
1327	/* 0x8c */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1328	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
1329	/* 0x8e */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Mx_Vx_Hx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1330	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
1331
1332	/* 0x90 */ iemOp_InvalidNeedRM, iemOp_vgatherdd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1333	/* 0x91 */ iemOp_InvalidNeedRM, iemOp_vgatherqd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1334	/* 0x92 */ iemOp_InvalidNeedRM, iemOp_vgatherdps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1335	/* 0x93 */ iemOp_InvalidNeedRM, iemOp_vgatherqps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1336	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
1337	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
1338	/* 0x96 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub132ps_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1339	/* 0x97 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1340	/* 0x98 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1341	/* 0x99 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1342	/* 0x9a */ iemOp_InvalidNeedRM, iemOp_vfmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1343	/* 0x9b */ iemOp_InvalidNeedRM, iemOp_vfmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1344	/* 0x9c */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1345	/* 0x9d */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1346	/* 0x9e */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1347	/* 0x9f */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1348
1349	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1350	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1351	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1352	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1353	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1354	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1355	/* 0xa6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1356	/* 0xa7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1357	/* 0xa8 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1358	/* 0xa9 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1359	/* 0xaa */ iemOp_InvalidNeedRM, iemOp_vfmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1360	/* 0xab */ iemOp_InvalidNeedRM, iemOp_vfmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1361	/* 0xac */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1362	/* 0xad */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1363	/* 0xae */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1364	/* 0xaf */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1365
1366	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1367	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1368	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1369	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1370	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1371	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1372	/* 0xb6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1373	/* 0xb7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1374	/* 0xb8 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1375	/* 0xb9 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1376	/* 0xba */ iemOp_InvalidNeedRM, iemOp_vfmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1377	/* 0xbb */ iemOp_InvalidNeedRM, iemOp_vfmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1378	/* 0xbc */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1379	/* 0xbd */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1380	/* 0xbe */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1381	/* 0xbf */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1382
1383	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1384	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1385	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1386	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1387	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1388	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1389	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1390	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1391	/* 0xc8 */ iemOp_vsha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1392	/* 0xc9 */ iemOp_vsha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1393	/* 0xca */ iemOp_vsha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1394	/* 0xcb */ iemOp_vsha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1395	/* 0xcc */ iemOp_vsha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1396	/* 0xcd */ iemOp_vsha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1397	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
1398	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
1399
1400	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1401	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1402	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1403	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1404	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1405	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1406	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1407	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1408	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1409	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1410	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
1411	/* 0xdb */ iemOp_InvalidNeedRM, iemOp_vaesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1412	/* 0xdc */ iemOp_InvalidNeedRM, iemOp_vaesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1413	/* 0xdd */ iemOp_InvalidNeedRM, iemOp_vaesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1414	/* 0xde */ iemOp_InvalidNeedRM, iemOp_vaesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1415	/* 0xdf */ iemOp_InvalidNeedRM, iemOp_vaesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1416
1417	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1418	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1419	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1420	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1421	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1422	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1423	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1424	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1425	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1426	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1427	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
1428	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
1429	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
1430	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
1431	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
1432	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
1433
1434	/* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1435	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1436	/* 0xf2 */ iemOp_andn_Gy_By_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1437	/* 0xf3 */ iemOp_VGrp17_f3, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1438	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1439	/* 0xf5 */ iemOp_bzhi_Gy_Ey_By, iemOp_InvalidNeedRM, iemOp_pext_Gy_By_Ey, iemOp_pdep_Gy_By_Ey,
1440	/* 0xf6 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_mulx_By_Gy_rDX_Ey,
1441	/* 0xf7 */ iemOp_bextr_Gy_Ey_By, iemOp_shlx_Gy_Ey_By, iemOp_sarx_Gy_Ey_By, iemOp_shrx_Gy_Ey_By,
1442	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1443	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1444	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
1445	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
1446	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
1447	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
1448	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
1449	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
1450	};
1451	AssertCompile(RT_ELEMENTS(g_apfnVexMap2) == 1024);
1452
1453	/** @} */
1454

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h@ 95345

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