IEMAllInstructionsVexMap2.cpp.h@ 95517

Last change on this file since 95517 was 95517, checked in by vboxsync, 2 years ago
VMM/IEM: Simplified IEMOPMEDIAF3 and IEMOPMEDIAOPTF3 function table creation, moving most of them into the functions where they are used. Exceptions are 4 tables used by multiple decoder functions. bugref:9898
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 71.7 KB

Line
1	/* $Id: IEMAllInstructionsVexMap2.cpp.h 95517 2022-07-05 15:01:42Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation.
4	*
5	* @remarks IEMAllInstructionsThree0f38.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/** @name VEX Opcode Map 2
23	* @{
24	*/
25
26	/* Opcode VEX.0F38 0x00 - invalid. */
27
28
29	/** Opcode VEX.66.0F38 0x00. */
30	FNIEMOP_DEF(iemOp_vpshufb_Vx_Hx_Wx)
31	{
32	IEMOP_MNEMONIC3(VEX_RVM, VPSHUFB, vpshufb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
33	IEMOPMEDIAF3_INIT_VARS(vpshufb);
34	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
35	}
36
37
38	/* Opcode VEX.0F38 0x01 - invalid. */
39	/** Opcode VEX.66.0F38 0x01. */
40	FNIEMOP_STUB(iemOp_vphaddw_Vx_Hx_Wx);
41	/* Opcode VEX.0F38 0x02 - invalid. */
42	/** Opcode VEX.66.0F38 0x02. */
43	FNIEMOP_STUB(iemOp_vphaddd_Vx_Hx_Wx);
44	/* Opcode VEX.0F38 0x03 - invalid. */
45	/** Opcode VEX.66.0F38 0x03. */
46	FNIEMOP_STUB(iemOp_vphaddsw_Vx_Hx_Wx);
47	/* Opcode VEX.0F38 0x04 - invalid. */
48	/** Opcode VEX.66.0F38 0x04. */
49	FNIEMOP_STUB(iemOp_vpmaddubsw_Vx_Hx_Wx);
50	/* Opcode VEX.0F38 0x05 - invalid. */
51	/** Opcode VEX.66.0F38 0x05. */
52	FNIEMOP_STUB(iemOp_vphsubw_Vx_Hx_Wx);
53	/* Opcode VEX.0F38 0x06 - invalid. */
54	/** Opcode VEX.66.0F38 0x06. */
55	FNIEMOP_STUB(iemOp_vphsubdq_Vx_Hx_Wx);
56	/* Opcode VEX.0F38 0x07 - invalid. */
57	/** Opcode VEX.66.0F38 0x07. */
58	FNIEMOP_STUB(iemOp_vphsubsw_Vx_Hx_Wx);
59	/* Opcode VEX.0F38 0x08 - invalid. */
60	/** Opcode VEX.66.0F38 0x08. */
61	FNIEMOP_STUB(iemOp_vpsignb_Vx_Hx_Wx);
62	/* Opcode VEX.0F38 0x09 - invalid. */
63	/** Opcode VEX.66.0F38 0x09. */
64	FNIEMOP_STUB(iemOp_vpsignw_Vx_Hx_Wx);
65	/* Opcode VEX.0F38 0x0a - invalid. */
66	/** Opcode VEX.66.0F38 0x0a. */
67	FNIEMOP_STUB(iemOp_vpsignd_Vx_Hx_Wx);
68	/* Opcode VEX.0F38 0x0b - invalid. */
69	/** Opcode VEX.66.0F38 0x0b. */
70	FNIEMOP_STUB(iemOp_vpmulhrsw_Vx_Hx_Wx);
71	/* Opcode VEX.0F38 0x0c - invalid. */
72	/** Opcode VEX.66.0F38 0x0c. */
73	FNIEMOP_STUB(iemOp_vpermilps_Vx_Hx_Wx);
74	/* Opcode VEX.0F38 0x0d - invalid. */
75	/** Opcode VEX.66.0F38 0x0d. */
76	FNIEMOP_STUB(iemOp_vpermilpd_Vx_Hx_Wx);
77	/* Opcode VEX.0F38 0x0e - invalid. */
78	/** Opcode VEX.66.0F38 0x0e. */
79	FNIEMOP_STUB(iemOp_vtestps_Vx_Wx);
80	/* Opcode VEX.0F38 0x0f - invalid. */
81	/** Opcode VEX.66.0F38 0x0f. */
82	FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx);
83
84
85	/* Opcode VEX.0F38 0x10 - invalid */
86	/* Opcode VEX.66.0F38 0x10 - invalid (legacy only). */
87	/* Opcode VEX.0F38 0x11 - invalid */
88	/* Opcode VEX.66.0F38 0x11 - invalid */
89	/* Opcode VEX.0F38 0x12 - invalid */
90	/* Opcode VEX.66.0F38 0x12 - invalid */
91	/* Opcode VEX.0F38 0x13 - invalid */
92	/* Opcode VEX.66.0F38 0x13 - invalid (vex only). */
93	/* Opcode VEX.0F38 0x14 - invalid */
94	/* Opcode VEX.66.0F38 0x14 - invalid (legacy only). */
95	/* Opcode VEX.0F38 0x15 - invalid */
96	/* Opcode VEX.66.0F38 0x15 - invalid (legacy only). */
97	/* Opcode VEX.0F38 0x16 - invalid */
98	/** Opcode VEX.66.0F38 0x16. */
99	FNIEMOP_STUB(iemOp_vpermps_Vqq_Hqq_Wqq);
100	/* Opcode VEX.0F38 0x17 - invalid */
101	/** Opcode VEX.66.0F38 0x17 - invalid */
102	FNIEMOP_STUB(iemOp_vptest_Vx_Wx);
103	/* Opcode VEX.0F38 0x18 - invalid */
104	/** Opcode VEX.66.0F38 0x18. */
105	FNIEMOP_STUB(iemOp_vbroadcastss_Vx_Wd);
106	/* Opcode VEX.0F38 0x19 - invalid */
107	/** Opcode VEX.66.0F38 0x19. */
108	FNIEMOP_STUB(iemOp_vbroadcastsd_Vqq_Wq);
109	/* Opcode VEX.0F38 0x1a - invalid */
110	/** Opcode VEX.66.0F38 0x1a. */
111	FNIEMOP_STUB(iemOp_vbroadcastf128_Vqq_Mdq);
112	/* Opcode VEX.0F38 0x1b - invalid */
113	/* Opcode VEX.66.0F38 0x1b - invalid */
114	/* Opcode VEX.0F38 0x1c - invalid. */
115	/** Opcode VEX.66.0F38 0x1c. */
116	FNIEMOP_STUB(iemOp_vpabsb_Vx_Wx);
117	/* Opcode VEX.0F38 0x1d - invalid. */
118	/** Opcode VEX.66.0F38 0x1d. */
119	FNIEMOP_STUB(iemOp_vpabsw_Vx_Wx);
120	/* Opcode VEX.0F38 0x1e - invalid. */
121	/** Opcode VEX.66.0F38 0x1e. */
122	FNIEMOP_STUB(iemOp_vpabsd_Vx_Wx);
123	/* Opcode VEX.0F38 0x1f - invalid */
124	/* Opcode VEX.66.0F38 0x1f - invalid */
125
126
127	/** Opcode VEX.66.0F38 0x20. */
128	FNIEMOP_STUB(iemOp_vpmovsxbw_Vx_UxMq);
129	/** Opcode VEX.66.0F38 0x21. */
130	FNIEMOP_STUB(iemOp_vpmovsxbd_Vx_UxMd);
131	/** Opcode VEX.66.0F38 0x22. */
132	FNIEMOP_STUB(iemOp_vpmovsxbq_Vx_UxMw);
133	/** Opcode VEX.66.0F38 0x23. */
134	FNIEMOP_STUB(iemOp_vpmovsxwd_Vx_UxMq);
135	/** Opcode VEX.66.0F38 0x24. */
136	FNIEMOP_STUB(iemOp_vpmovsxwq_Vx_UxMd);
137	/** Opcode VEX.66.0F38 0x25. */
138	FNIEMOP_STUB(iemOp_vpmovsxdq_Vx_UxMq);
139	/* Opcode VEX.66.0F38 0x26 - invalid */
140	/* Opcode VEX.66.0F38 0x27 - invalid */
141	/** Opcode VEX.66.0F38 0x28. */
142	FNIEMOP_STUB(iemOp_vpmuldq_Vx_Hx_Wx);
143
144
145	/** Opcode VEX.66.0F38 0x29. */
146	FNIEMOP_DEF(iemOp_vpcmpeqq_Vx_Hx_Wx)
147	{
148	IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQQ, vpcmpeqq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
149	IEMOPMEDIAF3_INIT_VARS(vpcmpeqq);
150	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
151	}
152
153
154	FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
155	{
156	Assert(pVCpu->iem.s.uVexLength <= 1);
157	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
158	if (IEM_IS_MODRM_MEM_MODE(bRm))
159	{
160	if (pVCpu->iem.s.uVexLength == 0)
161	{
162	/**
163	* @opcode 0x2a
164	* @opcodesub !11 mr/reg vex.l=0
165	* @oppfx 0x66
166	* @opcpuid avx
167	* @opgroup og_avx_cachect
168	* @opxcpttype 1
169	* @optest op1=-1 op2=2 -> op1=2
170	* @optest op1=0 op2=-42 -> op1=-42
171	*/
172	/* 128-bit: Memory, register. */
173	IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
174	DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
175	IEM_MC_BEGIN(0, 2);
176	IEM_MC_LOCAL(RTUINT128U, uSrc);
177	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
178
179	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
180	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
181	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
182	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
183
184	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
185	IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
186
187	IEM_MC_ADVANCE_RIP();
188	IEM_MC_END();
189	}
190	else
191	{
192	/**
193	* @opdone
194	* @opcode 0x2a
195	* @opcodesub !11 mr/reg vex.l=1
196	* @oppfx 0x66
197	* @opcpuid avx2
198	* @opgroup og_avx2_cachect
199	* @opxcpttype 1
200	* @optest op1=-1 op2=2 -> op1=2
201	* @optest op1=0 op2=-42 -> op1=-42
202	*/
203	/* 256-bit: Memory, register. */
204	IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
205	DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
206	IEM_MC_BEGIN(0, 2);
207	IEM_MC_LOCAL(RTUINT256U, uSrc);
208	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
209
210	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
211	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
212	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
213	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
214
215	IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
216	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
217
218	IEM_MC_ADVANCE_RIP();
219	IEM_MC_END();
220	}
221	return VINF_SUCCESS;
222	}
223
224	/**
225	* @opdone
226	* @opmnemonic udvex660f382arg
227	* @opcode 0x2a
228	* @opcodesub 11 mr/reg
229	* @oppfx 0x66
230	* @opunused immediate
231	* @opcpuid avx
232	* @optest ->
233	*/
234	return IEMOP_RAISE_INVALID_OPCODE();
235
236	}
237
238
239	/** Opcode VEX.66.0F38 0x2b. */
240	FNIEMOP_STUB(iemOp_vpackusdw_Vx_Hx_Wx);
241	/** Opcode VEX.66.0F38 0x2c. */
242	FNIEMOP_STUB(iemOp_vmaskmovps_Vx_Hx_Mx);
243	/** Opcode VEX.66.0F38 0x2d. */
244	FNIEMOP_STUB(iemOp_vmaskmovpd_Vx_Hx_Mx);
245	/** Opcode VEX.66.0F38 0x2e. */
246	FNIEMOP_STUB(iemOp_vmaskmovps_Mx_Hx_Vx);
247	/** Opcode VEX.66.0F38 0x2f. */
248	FNIEMOP_STUB(iemOp_vmaskmovpd_Mx_Hx_Vx);
249
250	/** Opcode VEX.66.0F38 0x30. */
251	FNIEMOP_STUB(iemOp_vpmovzxbw_Vx_UxMq);
252	/** Opcode VEX.66.0F38 0x31. */
253	FNIEMOP_STUB(iemOp_vpmovzxbd_Vx_UxMd);
254	/** Opcode VEX.66.0F38 0x32. */
255	FNIEMOP_STUB(iemOp_vpmovzxbq_Vx_UxMw);
256	/** Opcode VEX.66.0F38 0x33. */
257	FNIEMOP_STUB(iemOp_vpmovzxwd_Vx_UxMq);
258	/** Opcode VEX.66.0F38 0x34. */
259	FNIEMOP_STUB(iemOp_vpmovzxwq_Vx_UxMd);
260	/** Opcode VEX.66.0F38 0x35. */
261	FNIEMOP_STUB(iemOp_vpmovzxdq_Vx_UxMq);
262	/* Opcode VEX.66.0F38 0x36. */
263	FNIEMOP_STUB(iemOp_vpermd_Vqq_Hqq_Wqq);
264
265
266	/** Opcode VEX.66.0F38 0x37. */
267	FNIEMOP_DEF(iemOp_vpcmpgtq_Vx_Hx_Wx)
268	{
269	IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTQ, vpcmpgtq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
270	IEMOPMEDIAF3_INIT_VARS(vpcmpgtq);
271	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
272	}
273
274
275	/** Opcode VEX.66.0F38 0x38. */
276	FNIEMOP_STUB(iemOp_vpminsb_Vx_Hx_Wx);
277	/** Opcode VEX.66.0F38 0x39. */
278	FNIEMOP_STUB(iemOp_vpminsd_Vx_Hx_Wx);
279	/** Opcode VEX.66.0F38 0x3a. */
280	FNIEMOP_STUB(iemOp_vpminuw_Vx_Hx_Wx);
281	/** Opcode VEX.66.0F38 0x3b. */
282	FNIEMOP_STUB(iemOp_vpminud_Vx_Hx_Wx);
283	/** Opcode VEX.66.0F38 0x3c. */
284	FNIEMOP_STUB(iemOp_vpmaxsb_Vx_Hx_Wx);
285	/** Opcode VEX.66.0F38 0x3d. */
286	FNIEMOP_STUB(iemOp_vpmaxsd_Vx_Hx_Wx);
287	/** Opcode VEX.66.0F38 0x3e. */
288	FNIEMOP_STUB(iemOp_vpmaxuw_Vx_Hx_Wx);
289	/** Opcode VEX.66.0F38 0x3f. */
290	FNIEMOP_STUB(iemOp_vpmaxud_Vx_Hx_Wx);
291
292
293	/** Opcode VEX.66.0F38 0x40. */
294	FNIEMOP_STUB(iemOp_vpmulld_Vx_Hx_Wx);
295	/** Opcode VEX.66.0F38 0x41. */
296	FNIEMOP_STUB(iemOp_vphminposuw_Vdq_Wdq);
297	/* Opcode VEX.66.0F38 0x42 - invalid. */
298	/* Opcode VEX.66.0F38 0x43 - invalid. */
299	/* Opcode VEX.66.0F38 0x44 - invalid. */
300	/** Opcode VEX.66.0F38 0x45. */
301	FNIEMOP_STUB(iemOp_vpsrlvd_q_Vx_Hx_Wx);
302	/** Opcode VEX.66.0F38 0x46. */
303	FNIEMOP_STUB(iemOp_vsravd_Vx_Hx_Wx);
304	/** Opcode VEX.66.0F38 0x47. */
305	FNIEMOP_STUB(iemOp_vpsllvd_q_Vx_Hx_Wx);
306	/* Opcode VEX.66.0F38 0x48 - invalid. */
307	/* Opcode VEX.66.0F38 0x49 - invalid. */
308	/* Opcode VEX.66.0F38 0x4a - invalid. */
309	/* Opcode VEX.66.0F38 0x4b - invalid. */
310	/* Opcode VEX.66.0F38 0x4c - invalid. */
311	/* Opcode VEX.66.0F38 0x4d - invalid. */
312	/* Opcode VEX.66.0F38 0x4e - invalid. */
313	/* Opcode VEX.66.0F38 0x4f - invalid. */
314
315	/* Opcode VEX.66.0F38 0x50 - invalid. */
316	/* Opcode VEX.66.0F38 0x51 - invalid. */
317	/* Opcode VEX.66.0F38 0x52 - invalid. */
318	/* Opcode VEX.66.0F38 0x53 - invalid. */
319	/* Opcode VEX.66.0F38 0x54 - invalid. */
320	/* Opcode VEX.66.0F38 0x55 - invalid. */
321	/* Opcode VEX.66.0F38 0x56 - invalid. */
322	/* Opcode VEX.66.0F38 0x57 - invalid. */
323	/** Opcode VEX.66.0F38 0x58. */
324	FNIEMOP_STUB(iemOp_vpbroadcastd_Vx_Wx);
325	/** Opcode VEX.66.0F38 0x59. */
326	FNIEMOP_STUB(iemOp_vpbroadcastq_Vx_Wx);
327	/** Opcode VEX.66.0F38 0x5a. */
328	FNIEMOP_STUB(iemOp_vbroadcasti128_Vqq_Mdq);
329	/* Opcode VEX.66.0F38 0x5b - invalid. */
330	/* Opcode VEX.66.0F38 0x5c - invalid. */
331	/* Opcode VEX.66.0F38 0x5d - invalid. */
332	/* Opcode VEX.66.0F38 0x5e - invalid. */
333	/* Opcode VEX.66.0F38 0x5f - invalid. */
334
335	/* Opcode VEX.66.0F38 0x60 - invalid. */
336	/* Opcode VEX.66.0F38 0x61 - invalid. */
337	/* Opcode VEX.66.0F38 0x62 - invalid. */
338	/* Opcode VEX.66.0F38 0x63 - invalid. */
339	/* Opcode VEX.66.0F38 0x64 - invalid. */
340	/* Opcode VEX.66.0F38 0x65 - invalid. */
341	/* Opcode VEX.66.0F38 0x66 - invalid. */
342	/* Opcode VEX.66.0F38 0x67 - invalid. */
343	/* Opcode VEX.66.0F38 0x68 - invalid. */
344	/* Opcode VEX.66.0F38 0x69 - invalid. */
345	/* Opcode VEX.66.0F38 0x6a - invalid. */
346	/* Opcode VEX.66.0F38 0x6b - invalid. */
347	/* Opcode VEX.66.0F38 0x6c - invalid. */
348	/* Opcode VEX.66.0F38 0x6d - invalid. */
349	/* Opcode VEX.66.0F38 0x6e - invalid. */
350	/* Opcode VEX.66.0F38 0x6f - invalid. */
351
352	/* Opcode VEX.66.0F38 0x70 - invalid. */
353	/* Opcode VEX.66.0F38 0x71 - invalid. */
354	/* Opcode VEX.66.0F38 0x72 - invalid. */
355	/* Opcode VEX.66.0F38 0x73 - invalid. */
356	/* Opcode VEX.66.0F38 0x74 - invalid. */
357	/* Opcode VEX.66.0F38 0x75 - invalid. */
358	/* Opcode VEX.66.0F38 0x76 - invalid. */
359	/* Opcode VEX.66.0F38 0x77 - invalid. */
360	/** Opcode VEX.66.0F38 0x78. */
361	FNIEMOP_STUB(iemOp_vpboardcastb_Vx_Wx);
362	/** Opcode VEX.66.0F38 0x79. */
363	FNIEMOP_STUB(iemOp_vpboardcastw_Vx_Wx);
364	/* Opcode VEX.66.0F38 0x7a - invalid. */
365	/* Opcode VEX.66.0F38 0x7b - invalid. */
366	/* Opcode VEX.66.0F38 0x7c - invalid. */
367	/* Opcode VEX.66.0F38 0x7d - invalid. */
368	/* Opcode VEX.66.0F38 0x7e - invalid. */
369	/* Opcode VEX.66.0F38 0x7f - invalid. */
370
371	/* Opcode VEX.66.0F38 0x80 - invalid (legacy only). */
372	/* Opcode VEX.66.0F38 0x81 - invalid (legacy only). */
373	/* Opcode VEX.66.0F38 0x82 - invalid (legacy only). */
374	/* Opcode VEX.66.0F38 0x83 - invalid. */
375	/* Opcode VEX.66.0F38 0x84 - invalid. */
376	/* Opcode VEX.66.0F38 0x85 - invalid. */
377	/* Opcode VEX.66.0F38 0x86 - invalid. */
378	/* Opcode VEX.66.0F38 0x87 - invalid. */
379	/* Opcode VEX.66.0F38 0x88 - invalid. */
380	/* Opcode VEX.66.0F38 0x89 - invalid. */
381	/* Opcode VEX.66.0F38 0x8a - invalid. */
382	/* Opcode VEX.66.0F38 0x8b - invalid. */
383	/** Opcode VEX.66.0F38 0x8c. */
384	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Vx_Hx_Mx);
385	/* Opcode VEX.66.0F38 0x8d - invalid. */
386	/** Opcode VEX.66.0F38 0x8e. */
387	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Mx_Vx_Hx);
388	/* Opcode VEX.66.0F38 0x8f - invalid. */
389
390	/** Opcode VEX.66.0F38 0x90 (vex only). */
391	FNIEMOP_STUB(iemOp_vgatherdd_q_Vx_Hx_Wx);
392	/** Opcode VEX.66.0F38 0x91 (vex only). */
393	FNIEMOP_STUB(iemOp_vgatherqd_q_Vx_Hx_Wx);
394	/** Opcode VEX.66.0F38 0x92 (vex only). */
395	FNIEMOP_STUB(iemOp_vgatherdps_d_Vx_Hx_Wx);
396	/** Opcode VEX.66.0F38 0x93 (vex only). */
397	FNIEMOP_STUB(iemOp_vgatherqps_d_Vx_Hx_Wx);
398	/* Opcode VEX.66.0F38 0x94 - invalid. */
399	/* Opcode VEX.66.0F38 0x95 - invalid. */
400	/** Opcode VEX.66.0F38 0x96 (vex only). */
401	FNIEMOP_STUB(iemOp_vfmaddsub132ps_q_Vx_Hx_Wx);
402	/** Opcode VEX.66.0F38 0x97 (vex only). */
403	FNIEMOP_STUB(iemOp_vfmsubadd132ps_d_Vx_Hx_Wx);
404	/** Opcode VEX.66.0F38 0x98 (vex only). */
405	FNIEMOP_STUB(iemOp_vfmadd132ps_d_Vx_Hx_Wx);
406	/** Opcode VEX.66.0F38 0x99 (vex only). */
407	FNIEMOP_STUB(iemOp_vfmadd132ss_d_Vx_Hx_Wx);
408	/** Opcode VEX.66.0F38 0x9a (vex only). */
409	FNIEMOP_STUB(iemOp_vfmsub132ps_d_Vx_Hx_Wx);
410	/** Opcode VEX.66.0F38 0x9b (vex only). */
411	FNIEMOP_STUB(iemOp_vfmsub132ss_d_Vx_Hx_Wx);
412	/** Opcode VEX.66.0F38 0x9c (vex only). */
413	FNIEMOP_STUB(iemOp_vfnmadd132ps_d_Vx_Hx_Wx);
414	/** Opcode VEX.66.0F38 0x9d (vex only). */
415	FNIEMOP_STUB(iemOp_vfnmadd132ss_d_Vx_Hx_Wx);
416	/** Opcode VEX.66.0F38 0x9e (vex only). */
417	FNIEMOP_STUB(iemOp_vfnmsub132ps_d_Vx_Hx_Wx);
418	/** Opcode VEX.66.0F38 0x9f (vex only). */
419	FNIEMOP_STUB(iemOp_vfnmsub132ss_d_Vx_Hx_Wx);
420
421	/* Opcode VEX.66.0F38 0xa0 - invalid. */
422	/* Opcode VEX.66.0F38 0xa1 - invalid. */
423	/* Opcode VEX.66.0F38 0xa2 - invalid. */
424	/* Opcode VEX.66.0F38 0xa3 - invalid. */
425	/* Opcode VEX.66.0F38 0xa4 - invalid. */
426	/* Opcode VEX.66.0F38 0xa5 - invalid. */
427	/** Opcode VEX.66.0F38 0xa6 (vex only). */
428	FNIEMOP_STUB(iemOp_vfmaddsub213ps_d_Vx_Hx_Wx);
429	/** Opcode VEX.66.0F38 0xa7 (vex only). */
430	FNIEMOP_STUB(iemOp_vfmsubadd213ps_d_Vx_Hx_Wx);
431	/** Opcode VEX.66.0F38 0xa8 (vex only). */
432	FNIEMOP_STUB(iemOp_vfmadd213ps_d_Vx_Hx_Wx);
433	/** Opcode VEX.66.0F38 0xa9 (vex only). */
434	FNIEMOP_STUB(iemOp_vfmadd213ss_d_Vx_Hx_Wx);
435	/** Opcode VEX.66.0F38 0xaa (vex only). */
436	FNIEMOP_STUB(iemOp_vfmsub213ps_d_Vx_Hx_Wx);
437	/** Opcode VEX.66.0F38 0xab (vex only). */
438	FNIEMOP_STUB(iemOp_vfmsub213ss_d_Vx_Hx_Wx);
439	/** Opcode VEX.66.0F38 0xac (vex only). */
440	FNIEMOP_STUB(iemOp_vfnmadd213ps_d_Vx_Hx_Wx);
441	/** Opcode VEX.66.0F38 0xad (vex only). */
442	FNIEMOP_STUB(iemOp_vfnmadd213ss_d_Vx_Hx_Wx);
443	/** Opcode VEX.66.0F38 0xae (vex only). */
444	FNIEMOP_STUB(iemOp_vfnmsub213ps_d_Vx_Hx_Wx);
445	/** Opcode VEX.66.0F38 0xaf (vex only). */
446	FNIEMOP_STUB(iemOp_vfnmsub213ss_d_Vx_Hx_Wx);
447
448	/* Opcode VEX.66.0F38 0xb0 - invalid. */
449	/* Opcode VEX.66.0F38 0xb1 - invalid. */
450	/* Opcode VEX.66.0F38 0xb2 - invalid. */
451	/* Opcode VEX.66.0F38 0xb3 - invalid. */
452	/* Opcode VEX.66.0F38 0xb4 - invalid. */
453	/* Opcode VEX.66.0F38 0xb5 - invalid. */
454	/** Opcode VEX.66.0F38 0xb6 (vex only). */
455	FNIEMOP_STUB(iemOp_vfmaddsub231ps_d_Vx_Hx_Wx);
456	/** Opcode VEX.66.0F38 0xb7 (vex only). */
457	FNIEMOP_STUB(iemOp_vfmsubadd231ps_d_Vx_Hx_Wx);
458	/** Opcode VEX.66.0F38 0xb8 (vex only). */
459	FNIEMOP_STUB(iemOp_vfmadd231ps_d_Vx_Hx_Wx);
460	/** Opcode VEX.66.0F38 0xb9 (vex only). */
461	FNIEMOP_STUB(iemOp_vfmadd231ss_d_Vx_Hx_Wx);
462	/** Opcode VEX.66.0F38 0xba (vex only). */
463	FNIEMOP_STUB(iemOp_vfmsub231ps_d_Vx_Hx_Wx);
464	/** Opcode VEX.66.0F38 0xbb (vex only). */
465	FNIEMOP_STUB(iemOp_vfmsub231ss_d_Vx_Hx_Wx);
466	/** Opcode VEX.66.0F38 0xbc (vex only). */
467	FNIEMOP_STUB(iemOp_vfnmadd231ps_d_Vx_Hx_Wx);
468	/** Opcode VEX.66.0F38 0xbd (vex only). */
469	FNIEMOP_STUB(iemOp_vfnmadd231ss_d_Vx_Hx_Wx);
470	/** Opcode VEX.66.0F38 0xbe (vex only). */
471	FNIEMOP_STUB(iemOp_vfnmsub231ps_d_Vx_Hx_Wx);
472	/** Opcode VEX.66.0F38 0xbf (vex only). */
473	FNIEMOP_STUB(iemOp_vfnmsub231ss_d_Vx_Hx_Wx);
474
475	/* Opcode VEX.0F38 0xc0 - invalid. */
476	/* Opcode VEX.66.0F38 0xc0 - invalid. */
477	/* Opcode VEX.0F38 0xc1 - invalid. */
478	/* Opcode VEX.66.0F38 0xc1 - invalid. */
479	/* Opcode VEX.0F38 0xc2 - invalid. */
480	/* Opcode VEX.66.0F38 0xc2 - invalid. */
481	/* Opcode VEX.0F38 0xc3 - invalid. */
482	/* Opcode VEX.66.0F38 0xc3 - invalid. */
483	/* Opcode VEX.0F38 0xc4 - invalid. */
484	/* Opcode VEX.66.0F38 0xc4 - invalid. */
485	/* Opcode VEX.0F38 0xc5 - invalid. */
486	/* Opcode VEX.66.0F38 0xc5 - invalid. */
487	/* Opcode VEX.0F38 0xc6 - invalid. */
488	/* Opcode VEX.66.0F38 0xc6 - invalid. */
489	/* Opcode VEX.0F38 0xc7 - invalid. */
490	/* Opcode VEX.66.0F38 0xc7 - invalid. */
491	/** Opcode VEX.0F38 0xc8. */
492	FNIEMOP_STUB(iemOp_vsha1nexte_Vdq_Wdq);
493	/* Opcode VEX.66.0F38 0xc8 - invalid. */
494	/** Opcode VEX.0F38 0xc9. */
495	FNIEMOP_STUB(iemOp_vsha1msg1_Vdq_Wdq);
496	/* Opcode VEX.66.0F38 0xc9 - invalid. */
497	/** Opcode VEX.0F38 0xca. */
498	FNIEMOP_STUB(iemOp_vsha1msg2_Vdq_Wdq);
499	/* Opcode VEX.66.0F38 0xca - invalid. */
500	/** Opcode VEX.0F38 0xcb. */
501	FNIEMOP_STUB(iemOp_vsha256rnds2_Vdq_Wdq);
502	/* Opcode VEX.66.0F38 0xcb - invalid. */
503	/** Opcode VEX.0F38 0xcc. */
504	FNIEMOP_STUB(iemOp_vsha256msg1_Vdq_Wdq);
505	/* Opcode VEX.66.0F38 0xcc - invalid. */
506	/** Opcode VEX.0F38 0xcd. */
507	FNIEMOP_STUB(iemOp_vsha256msg2_Vdq_Wdq);
508	/* Opcode VEX.66.0F38 0xcd - invalid. */
509	/* Opcode VEX.0F38 0xce - invalid. */
510	/* Opcode VEX.66.0F38 0xce - invalid. */
511	/* Opcode VEX.0F38 0xcf - invalid. */
512	/* Opcode VEX.66.0F38 0xcf - invalid. */
513
514	/* Opcode VEX.66.0F38 0xd0 - invalid. */
515	/* Opcode VEX.66.0F38 0xd1 - invalid. */
516	/* Opcode VEX.66.0F38 0xd2 - invalid. */
517	/* Opcode VEX.66.0F38 0xd3 - invalid. */
518	/* Opcode VEX.66.0F38 0xd4 - invalid. */
519	/* Opcode VEX.66.0F38 0xd5 - invalid. */
520	/* Opcode VEX.66.0F38 0xd6 - invalid. */
521	/* Opcode VEX.66.0F38 0xd7 - invalid. */
522	/* Opcode VEX.66.0F38 0xd8 - invalid. */
523	/* Opcode VEX.66.0F38 0xd9 - invalid. */
524	/* Opcode VEX.66.0F38 0xda - invalid. */
525	/** Opcode VEX.66.0F38 0xdb. */
526	FNIEMOP_STUB(iemOp_vaesimc_Vdq_Wdq);
527	/** Opcode VEX.66.0F38 0xdc. */
528	FNIEMOP_STUB(iemOp_vaesenc_Vdq_Wdq);
529	/** Opcode VEX.66.0F38 0xdd. */
530	FNIEMOP_STUB(iemOp_vaesenclast_Vdq_Wdq);
531	/** Opcode VEX.66.0F38 0xde. */
532	FNIEMOP_STUB(iemOp_vaesdec_Vdq_Wdq);
533	/** Opcode VEX.66.0F38 0xdf. */
534	FNIEMOP_STUB(iemOp_vaesdeclast_Vdq_Wdq);
535
536	/* Opcode VEX.66.0F38 0xe0 - invalid. */
537	/* Opcode VEX.66.0F38 0xe1 - invalid. */
538	/* Opcode VEX.66.0F38 0xe2 - invalid. */
539	/* Opcode VEX.66.0F38 0xe3 - invalid. */
540	/* Opcode VEX.66.0F38 0xe4 - invalid. */
541	/* Opcode VEX.66.0F38 0xe5 - invalid. */
542	/* Opcode VEX.66.0F38 0xe6 - invalid. */
543	/* Opcode VEX.66.0F38 0xe7 - invalid. */
544	/* Opcode VEX.66.0F38 0xe8 - invalid. */
545	/* Opcode VEX.66.0F38 0xe9 - invalid. */
546	/* Opcode VEX.66.0F38 0xea - invalid. */
547	/* Opcode VEX.66.0F38 0xeb - invalid. */
548	/* Opcode VEX.66.0F38 0xec - invalid. */
549	/* Opcode VEX.66.0F38 0xed - invalid. */
550	/* Opcode VEX.66.0F38 0xee - invalid. */
551	/* Opcode VEX.66.0F38 0xef - invalid. */
552
553
554	/* Opcode VEX.0F38 0xf0 - invalid (legacy only). */
555	/* Opcode VEX.66.0F38 0xf0 - invalid (legacy only). */
556	/* Opcode VEX.F3.0F38 0xf0 - invalid. */
557	/* Opcode VEX.F2.0F38 0xf0 - invalid (legacy only). */
558
559	/* Opcode VEX.0F38 0xf1 - invalid (legacy only). */
560	/* Opcode VEX.66.0F38 0xf1 - invalid (legacy only). */
561	/* Opcode VEX.F3.0F38 0xf1 - invalid. */
562	/* Opcode VEX.F2.0F38 0xf1 - invalid (legacy only). */
563
564	/** Opcode VEX.0F38 0xf2 - ANDN (vex only). */
565	FNIEMOP_DEF(iemOp_andn_Gy_By_Ey)
566	{
567	IEMOP_MNEMONIC3(VEX_RVM, ANDN, andn, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
568	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1)
569	return iemOp_InvalidNeedRM(pVCpu);
570	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF);
571	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
572	if (IEM_IS_MODRM_REG_MODE(bRm))
573	{
574	/*
575	* Register, register.
576	*/
577	IEMOP_HLP_DONE_VEX_DECODING_L0();
578	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
579	{
580	IEM_MC_BEGIN(4, 0);
581	IEM_MC_ARG(uint64_t *, pDst, 0);
582	IEM_MC_ARG(uint64_t, uSrc1, 1);
583	IEM_MC_ARG(uint64_t, uSrc2, 2);
584	IEM_MC_ARG(uint32_t *, pEFlags, 3);
585	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
586	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
587	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
588	IEM_MC_REF_EFLAGS(pEFlags);
589	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
590	pDst, uSrc1, uSrc2, pEFlags);
591	IEM_MC_ADVANCE_RIP();
592	IEM_MC_END();
593	}
594	else
595	{
596	IEM_MC_BEGIN(4, 0);
597	IEM_MC_ARG(uint32_t *, pDst, 0);
598	IEM_MC_ARG(uint32_t, uSrc1, 1);
599	IEM_MC_ARG(uint32_t, uSrc2, 2);
600	IEM_MC_ARG(uint32_t *, pEFlags, 3);
601	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
602	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
603	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
604	IEM_MC_REF_EFLAGS(pEFlags);
605	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
606	pDst, uSrc1, uSrc2, pEFlags);
607	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
608	IEM_MC_ADVANCE_RIP();
609	IEM_MC_END();
610	}
611	}
612	else
613	{
614	/*
615	* Register, memory.
616	*/
617	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
618	{
619	IEM_MC_BEGIN(4, 1);
620	IEM_MC_ARG(uint64_t *, pDst, 0);
621	IEM_MC_ARG(uint64_t, uSrc1, 1);
622	IEM_MC_ARG(uint64_t, uSrc2, 2);
623	IEM_MC_ARG(uint32_t *, pEFlags, 3);
624	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
625	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
626	IEMOP_HLP_DONE_VEX_DECODING_L0();
627	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
628	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
629	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
630	IEM_MC_REF_EFLAGS(pEFlags);
631	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
632	pDst, uSrc1, uSrc2, pEFlags);
633	IEM_MC_ADVANCE_RIP();
634	IEM_MC_END();
635	}
636	else
637	{
638	IEM_MC_BEGIN(4, 1);
639	IEM_MC_ARG(uint32_t *, pDst, 0);
640	IEM_MC_ARG(uint32_t, uSrc1, 1);
641	IEM_MC_ARG(uint32_t, uSrc2, 2);
642	IEM_MC_ARG(uint32_t *, pEFlags, 3);
643	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
644	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
645	IEMOP_HLP_DONE_VEX_DECODING_L0();
646	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
647	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
648	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
649	IEM_MC_REF_EFLAGS(pEFlags);
650	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
651	pDst, uSrc1, uSrc2, pEFlags);
652	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
653	IEM_MC_ADVANCE_RIP();
654	IEM_MC_END();
655	}
656	}
657	return VINF_SUCCESS;
658	}
659
660	/* Opcode VEX.66.0F38 0xf2 - invalid. */
661	/* Opcode VEX.F3.0F38 0xf2 - invalid. */
662	/* Opcode VEX.F2.0F38 0xf2 - invalid. */
663
664
665	/* Opcode VEX.0F38 0xf3 - invalid. */
666	/* Opcode VEX.66.0F38 0xf3 - invalid. */
667
668	/* Opcode VEX.F3.0F38 0xf3 /0 - invalid. */
669
670	/** Body for the vex group 17 instructions. */
671	#define IEMOP_BODY_By_Ey(a_Instr) \
672	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1) \
673	return iemOp_InvalidWithRM(pVCpu, bRm); /* decode memory variant? */ \
674	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF); \
675	if (IEM_IS_MODRM_REG_MODE(bRm)) \
676	{ \
677	/* \
678	* Register, register. \
679	*/ \
680	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
681	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
682	{ \
683	IEM_MC_BEGIN(3, 0); \
684	IEM_MC_ARG(uint64_t *, pDst, 0); \
685	IEM_MC_ARG(uint64_t, uSrc, 1); \
686	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
687	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
688	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
689	IEM_MC_REF_EFLAGS(pEFlags); \
690	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
691	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
692	IEM_MC_ADVANCE_RIP(); \
693	IEM_MC_END(); \
694	} \
695	else \
696	{ \
697	IEM_MC_BEGIN(3, 0); \
698	IEM_MC_ARG(uint32_t *, pDst, 0); \
699	IEM_MC_ARG(uint32_t, uSrc, 1); \
700	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
701	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
702	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
703	IEM_MC_REF_EFLAGS(pEFlags); \
704	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
705	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
706	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
707	IEM_MC_ADVANCE_RIP(); \
708	IEM_MC_END(); \
709	} \
710	} \
711	else \
712	{ \
713	/* \
714	* Register, memory. \
715	*/ \
716	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
717	{ \
718	IEM_MC_BEGIN(3, 1); \
719	IEM_MC_ARG(uint64_t *, pDst, 0); \
720	IEM_MC_ARG(uint64_t, uSrc, 1); \
721	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
722	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
723	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
724	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
725	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
726	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
727	IEM_MC_REF_EFLAGS(pEFlags); \
728	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
729	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
730	IEM_MC_ADVANCE_RIP(); \
731	IEM_MC_END(); \
732	} \
733	else \
734	{ \
735	IEM_MC_BEGIN(3, 1); \
736	IEM_MC_ARG(uint32_t *, pDst, 0); \
737	IEM_MC_ARG(uint32_t, uSrc, 1); \
738	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
739	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
740	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
741	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
742	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
743	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
744	IEM_MC_REF_EFLAGS(pEFlags); \
745	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
746	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
747	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
748	IEM_MC_ADVANCE_RIP(); \
749	IEM_MC_END(); \
750	} \
751	} \
752	return VINF_SUCCESS
753
754
755	/* Opcode VEX.F3.0F38 0xf3 /1. */
756	/** @opcode /1
757	* @opmaps vexgrp17 */
758	FNIEMOP_DEF_1(iemOp_VGrp17_blsr_By_Ey, uint8_t, bRm)
759	{
760	IEMOP_MNEMONIC2(VEX_VM, BLSR, blsr, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
761	IEMOP_BODY_By_Ey(blsr);
762	}
763
764
765	/* Opcode VEX.F3.0F38 0xf3 /2. */
766	/** @opcode /2
767	* @opmaps vexgrp17 */
768	FNIEMOP_DEF_1(iemOp_VGrp17_blsmsk_By_Ey, uint8_t, bRm)
769	{
770	IEMOP_MNEMONIC2(VEX_VM, BLSMSK, blsmsk, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
771	IEMOP_BODY_By_Ey(blsmsk);
772	}
773
774
775	/* Opcode VEX.F3.0F38 0xf3 /3. */
776	/** @opcode /3
777	* @opmaps vexgrp17 */
778	FNIEMOP_DEF_1(iemOp_VGrp17_blsi_By_Ey, uint8_t, bRm)
779	{
780	IEMOP_MNEMONIC2(VEX_VM, BLSI, blsi, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
781	IEMOP_BODY_By_Ey(blsi);
782	}
783
784
785	/* Opcode VEX.F3.0F38 0xf3 /4 - invalid. */
786	/* Opcode VEX.F3.0F38 0xf3 /5 - invalid. */
787	/* Opcode VEX.F3.0F38 0xf3 /6 - invalid. */
788	/* Opcode VEX.F3.0F38 0xf3 /7 - invalid. */
789
790	/**
791	* Group 17 jump table for the VEX.F3 variant.
792	*/
793	IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =
794	{
795	/* /0 */ iemOp_InvalidWithRM,
796	/* /1 */ iemOp_VGrp17_blsr_By_Ey,
797	/* /2 */ iemOp_VGrp17_blsmsk_By_Ey,
798	/* /3 */ iemOp_VGrp17_blsi_By_Ey,
799	/* /4 */ iemOp_InvalidWithRM,
800	/* /5 */ iemOp_InvalidWithRM,
801	/* /6 */ iemOp_InvalidWithRM,
802	/* /7 */ iemOp_InvalidWithRM
803	};
804	AssertCompile(RT_ELEMENTS(g_apfnVexGroup17_f3) == 8);
805
806	/** Opcode VEX.F3.0F38 0xf3 - invalid (vex only - group 17). */
807	FNIEMOP_DEF(iemOp_VGrp17_f3)
808	{
809	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
810	return FNIEMOP_CALL_1(g_apfnVexGroup17_f3[IEM_GET_MODRM_REG_8(bRm)], bRm);
811	}
812
813	/* Opcode VEX.F2.0F38 0xf3 - invalid (vex only - group 17). */
814
815
816	/* Opcode VEX.0F38 0xf4 - invalid. */
817	/* Opcode VEX.66.0F38 0xf4 - invalid. */
818	/* Opcode VEX.F3.0F38 0xf4 - invalid. */
819	/* Opcode VEX.F2.0F38 0xf4 - invalid. */
820
821	/** Body for BZHI, BEXTR, ++; assumes VEX.L must be 0. */
822	#define IEMOP_BODY_Gy_Ey_By(a_Instr, a_fFeatureMember, a_fUndefFlags) \
823	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
824	return iemOp_InvalidNeedRM(pVCpu); \
825	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
826	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
827	if (IEM_IS_MODRM_REG_MODE(bRm)) \
828	{ \
829	/* \
830	* Register, register. \
831	*/ \
832	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
833	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
834	{ \
835	IEM_MC_BEGIN(4, 0); \
836	IEM_MC_ARG(uint64_t *, pDst, 0); \
837	IEM_MC_ARG(uint64_t, uSrc1, 1); \
838	IEM_MC_ARG(uint64_t, uSrc2, 2); \
839	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
840	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
841	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
842	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
843	IEM_MC_REF_EFLAGS(pEFlags); \
844	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
845	iemAImpl_ ## a_Instr ## _u64_fallback), \
846	pDst, uSrc1, uSrc2, pEFlags); \
847	IEM_MC_ADVANCE_RIP(); \
848	IEM_MC_END(); \
849	} \
850	else \
851	{ \
852	IEM_MC_BEGIN(4, 0); \
853	IEM_MC_ARG(uint32_t *, pDst, 0); \
854	IEM_MC_ARG(uint32_t, uSrc1, 1); \
855	IEM_MC_ARG(uint32_t, uSrc2, 2); \
856	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
857	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
858	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
859	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
860	IEM_MC_REF_EFLAGS(pEFlags); \
861	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
862	iemAImpl_ ## a_Instr ## _u32_fallback), \
863	pDst, uSrc1, uSrc2, pEFlags); \
864	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
865	IEM_MC_ADVANCE_RIP(); \
866	IEM_MC_END(); \
867	} \
868	} \
869	else \
870	{ \
871	/* \
872	* Register, memory. \
873	*/ \
874	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
875	{ \
876	IEM_MC_BEGIN(4, 1); \
877	IEM_MC_ARG(uint64_t *, pDst, 0); \
878	IEM_MC_ARG(uint64_t, uSrc1, 1); \
879	IEM_MC_ARG(uint64_t, uSrc2, 2); \
880	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
881	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
882	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
883	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
884	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
885	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
886	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
887	IEM_MC_REF_EFLAGS(pEFlags); \
888	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
889	iemAImpl_ ## a_Instr ## _u64_fallback), \
890	pDst, uSrc1, uSrc2, pEFlags); \
891	IEM_MC_ADVANCE_RIP(); \
892	IEM_MC_END(); \
893	} \
894	else \
895	{ \
896	IEM_MC_BEGIN(4, 1); \
897	IEM_MC_ARG(uint32_t *, pDst, 0); \
898	IEM_MC_ARG(uint32_t, uSrc1, 1); \
899	IEM_MC_ARG(uint32_t, uSrc2, 2); \
900	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
901	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
902	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
903	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
904	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
905	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
906	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
907	IEM_MC_REF_EFLAGS(pEFlags); \
908	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
909	iemAImpl_ ## a_Instr ## _u32_fallback), \
910	pDst, uSrc1, uSrc2, pEFlags); \
911	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
912	IEM_MC_ADVANCE_RIP(); \
913	IEM_MC_END(); \
914	} \
915	} \
916	return VINF_SUCCESS
917
918	/** Body for SARX, SHLX, SHRX; assumes VEX.L must be 0. */
919	#define IEMOP_BODY_Gy_Ey_By_NoEflags(a_Instr, a_fFeatureMember, a_fUndefFlags) \
920	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
921	return iemOp_InvalidNeedRM(pVCpu); \
922	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
923	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
924	if (IEM_IS_MODRM_REG_MODE(bRm)) \
925	{ \
926	/* \
927	* Register, register. \
928	*/ \
929	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
930	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
931	{ \
932	IEM_MC_BEGIN(3, 0); \
933	IEM_MC_ARG(uint64_t *, pDst, 0); \
934	IEM_MC_ARG(uint64_t, uSrc1, 1); \
935	IEM_MC_ARG(uint64_t, uSrc2, 2); \
936	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
937	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
938	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
939	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
940	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
941	IEM_MC_ADVANCE_RIP(); \
942	IEM_MC_END(); \
943	} \
944	else \
945	{ \
946	IEM_MC_BEGIN(3, 0); \
947	IEM_MC_ARG(uint32_t *, pDst, 0); \
948	IEM_MC_ARG(uint32_t, uSrc1, 1); \
949	IEM_MC_ARG(uint32_t, uSrc2, 2); \
950	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
951	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
952	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
953	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
954	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
955	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
956	IEM_MC_ADVANCE_RIP(); \
957	IEM_MC_END(); \
958	} \
959	} \
960	else \
961	{ \
962	/* \
963	* Register, memory. \
964	*/ \
965	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
966	{ \
967	IEM_MC_BEGIN(3, 1); \
968	IEM_MC_ARG(uint64_t *, pDst, 0); \
969	IEM_MC_ARG(uint64_t, uSrc1, 1); \
970	IEM_MC_ARG(uint64_t, uSrc2, 2); \
971	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
972	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
973	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
974	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
975	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
976	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
977	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
978	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
979	IEM_MC_ADVANCE_RIP(); \
980	IEM_MC_END(); \
981	} \
982	else \
983	{ \
984	IEM_MC_BEGIN(3, 1); \
985	IEM_MC_ARG(uint32_t *, pDst, 0); \
986	IEM_MC_ARG(uint32_t, uSrc1, 1); \
987	IEM_MC_ARG(uint32_t, uSrc2, 2); \
988	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
989	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
990	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
991	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
992	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
993	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
994	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
995	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
996	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
997	IEM_MC_ADVANCE_RIP(); \
998	IEM_MC_END(); \
999	} \
1000	} \
1001	return VINF_SUCCESS
1002
1003	/** Opcode VEX.0F38 0xf5 (vex only). */
1004	FNIEMOP_DEF(iemOp_bzhi_Gy_Ey_By)
1005	{
1006	IEMOP_MNEMONIC3(VEX_RMV, BZHI, bzhi, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1007	IEMOP_BODY_Gy_Ey_By(bzhi, fBmi2, X86_EFL_AF \| X86_EFL_PF);
1008	}
1009
1010	/* Opcode VEX.66.0F38 0xf5 - invalid. */
1011
1012	/** Body for PDEP and PEXT (similar to ANDN, except no EFLAGS). */
1013	#define IEMOP_BODY_Gy_By_Ey_NoEflags(a_Instr, a_fFeatureMember) \
1014	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
1015	return iemOp_InvalidNeedRM(pVCpu); \
1016	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1017	if (IEM_IS_MODRM_REG_MODE(bRm)) \
1018	{ \
1019	/* \
1020	* Register, register. \
1021	*/ \
1022	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1023	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1024	{ \
1025	IEM_MC_BEGIN(3, 0); \
1026	IEM_MC_ARG(uint64_t *, pDst, 0); \
1027	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1028	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1029	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1030	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1031	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1032	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1033	iemAImpl_ ## a_Instr ## _u64, \
1034	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1035	IEM_MC_ADVANCE_RIP(); \
1036	IEM_MC_END(); \
1037	} \
1038	else \
1039	{ \
1040	IEM_MC_BEGIN(3, 0); \
1041	IEM_MC_ARG(uint32_t *, pDst, 0); \
1042	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1043	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1044	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1045	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1046	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1047	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1048	iemAImpl_ ## a_Instr ## _u32, \
1049	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1050	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1051	IEM_MC_ADVANCE_RIP(); \
1052	IEM_MC_END(); \
1053	} \
1054	} \
1055	else \
1056	{ \
1057	/* \
1058	* Register, memory. \
1059	*/ \
1060	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1061	{ \
1062	IEM_MC_BEGIN(3, 1); \
1063	IEM_MC_ARG(uint64_t *, pDst, 0); \
1064	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1065	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1066	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1067	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1068	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1069	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1070	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1071	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1072	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1073	iemAImpl_ ## a_Instr ## _u64, \
1074	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1075	IEM_MC_ADVANCE_RIP(); \
1076	IEM_MC_END(); \
1077	} \
1078	else \
1079	{ \
1080	IEM_MC_BEGIN(3, 1); \
1081	IEM_MC_ARG(uint32_t *, pDst, 0); \
1082	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1083	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1084	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1085	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1086	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1087	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1088	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1089	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1090	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1091	iemAImpl_ ## a_Instr ## _u32, \
1092	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1093	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1094	IEM_MC_ADVANCE_RIP(); \
1095	IEM_MC_END(); \
1096	} \
1097	} \
1098	return VINF_SUCCESS;
1099
1100
1101	/** Opcode VEX.F3.0F38 0xf5 (vex only). */
1102	FNIEMOP_DEF(iemOp_pext_Gy_By_Ey)
1103	{
1104	IEMOP_MNEMONIC3(VEX_RVM, PEXT, pext, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1105	IEMOP_BODY_Gy_By_Ey_NoEflags(pext, fBmi2);
1106	}
1107
1108
1109	/** Opcode VEX.F2.0F38 0xf5 (vex only). */
1110	FNIEMOP_DEF(iemOp_pdep_Gy_By_Ey)
1111	{
1112	IEMOP_MNEMONIC3(VEX_RVM, PDEP, pdep, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1113	IEMOP_BODY_Gy_By_Ey_NoEflags(pdep, fBmi2);
1114	}
1115
1116
1117	/* Opcode VEX.0F38 0xf6 - invalid. */
1118	/* Opcode VEX.66.0F38 0xf6 - invalid (legacy only). */
1119	/* Opcode VEX.F3.0F38 0xf6 - invalid (legacy only). */
1120
1121
1122	/** Opcode VEX.F2.0F38 0xf6 (vex only) */
1123	FNIEMOP_DEF(iemOp_mulx_By_Gy_rDX_Ey)
1124	{
1125	IEMOP_MNEMONIC4(VEX_RVM, MULX, mulx, Gy, By, Ey, rDX, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1126	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi2)
1127	return iemOp_InvalidNeedRM(pVCpu);
1128	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1129	if (IEM_IS_MODRM_REG_MODE(bRm))
1130	{
1131	/*
1132	* Register, register.
1133	*/
1134	IEMOP_HLP_DONE_VEX_DECODING_L0();
1135	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1136	{
1137	IEM_MC_BEGIN(4, 0);
1138	IEM_MC_ARG(uint64_t *, pDst1, 0);
1139	IEM_MC_ARG(uint64_t *, pDst2, 1);
1140	IEM_MC_ARG(uint64_t, uSrc1, 2);
1141	IEM_MC_ARG(uint64_t, uSrc2, 3);
1142	IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1143	IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1144	IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1145	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1146	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1147	pDst1, pDst2, uSrc1, uSrc2);
1148	IEM_MC_ADVANCE_RIP();
1149	IEM_MC_END();
1150	}
1151	else
1152	{
1153	IEM_MC_BEGIN(4, 0);
1154	IEM_MC_ARG(uint32_t *, pDst1, 0);
1155	IEM_MC_ARG(uint32_t *, pDst2, 1);
1156	IEM_MC_ARG(uint32_t, uSrc1, 2);
1157	IEM_MC_ARG(uint32_t, uSrc2, 3);
1158	IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1159	IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1160	IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1161	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1162	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1163	pDst1, pDst2, uSrc1, uSrc2);
1164	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1165	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1166	IEM_MC_ADVANCE_RIP();
1167	IEM_MC_END();
1168	}
1169	}
1170	else
1171	{
1172	/*
1173	* Register, memory.
1174	*/
1175	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1176	{
1177	IEM_MC_BEGIN(4, 1);
1178	IEM_MC_ARG(uint64_t *, pDst1, 0);
1179	IEM_MC_ARG(uint64_t *, pDst2, 1);
1180	IEM_MC_ARG(uint64_t, uSrc1, 2);
1181	IEM_MC_ARG(uint64_t, uSrc2, 3);
1182	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1183	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1184	IEMOP_HLP_DONE_VEX_DECODING_L0();
1185	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1186	IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1187	IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1188	IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1189	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1190	pDst1, pDst2, uSrc1, uSrc2);
1191	IEM_MC_ADVANCE_RIP();
1192	IEM_MC_END();
1193	}
1194	else
1195	{
1196	IEM_MC_BEGIN(4, 1);
1197	IEM_MC_ARG(uint32_t *, pDst1, 0);
1198	IEM_MC_ARG(uint32_t *, pDst2, 1);
1199	IEM_MC_ARG(uint32_t, uSrc1, 2);
1200	IEM_MC_ARG(uint32_t, uSrc2, 3);
1201	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1202	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1203	IEMOP_HLP_DONE_VEX_DECODING_L0();
1204	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1205	IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1206	IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1207	IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1208	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1209	pDst1, pDst2, uSrc1, uSrc2);
1210	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1211	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1212	IEM_MC_ADVANCE_RIP();
1213	IEM_MC_END();
1214	}
1215	}
1216	return VINF_SUCCESS;
1217	}
1218
1219
1220	/** Opcode VEX.0F38 0xf7 (vex only). */
1221	FNIEMOP_DEF(iemOp_bextr_Gy_Ey_By)
1222	{
1223	IEMOP_MNEMONIC3(VEX_RMV, BEXTR, bextr, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1224	IEMOP_BODY_Gy_Ey_By(bextr, fBmi1, X86_EFL_SF \| X86_EFL_AF \| X86_EFL_PF);
1225	}
1226
1227
1228	/** Opcode VEX.66.0F38 0xf7 (vex only). */
1229	FNIEMOP_DEF(iemOp_shlx_Gy_Ey_By)
1230	{
1231	IEMOP_MNEMONIC3(VEX_RMV, SHLX, shlx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1232	IEMOP_BODY_Gy_Ey_By_NoEflags(shlx, fBmi2, 0);
1233	}
1234
1235
1236	/** Opcode VEX.F3.0F38 0xf7 (vex only). */
1237	FNIEMOP_DEF(iemOp_sarx_Gy_Ey_By)
1238	{
1239	IEMOP_MNEMONIC3(VEX_RMV, SARX, sarx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1240	IEMOP_BODY_Gy_Ey_By_NoEflags(sarx, fBmi2, 0);
1241	}
1242
1243
1244	/** Opcode VEX.F2.0F38 0xf7 (vex only). */
1245	FNIEMOP_DEF(iemOp_shrx_Gy_Ey_By)
1246	{
1247	IEMOP_MNEMONIC3(VEX_RMV, SHRX, shrx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1248	IEMOP_BODY_Gy_Ey_By_NoEflags(shrx, fBmi2, 0);
1249	}
1250
1251	/* Opcode VEX.0F38 0xf8 - invalid. */
1252	/* Opcode VEX.66.0F38 0xf8 - invalid. */
1253	/* Opcode VEX.F3.0F38 0xf8 - invalid. */
1254	/* Opcode VEX.F2.0F38 0xf8 - invalid. */
1255
1256	/* Opcode VEX.0F38 0xf9 - invalid. */
1257	/* Opcode VEX.66.0F38 0xf9 - invalid. */
1258	/* Opcode VEX.F3.0F38 0xf9 - invalid. */
1259	/* Opcode VEX.F2.0F38 0xf9 - invalid. */
1260
1261	/* Opcode VEX.0F38 0xfa - invalid. */
1262	/* Opcode VEX.66.0F38 0xfa - invalid. */
1263	/* Opcode VEX.F3.0F38 0xfa - invalid. */
1264	/* Opcode VEX.F2.0F38 0xfa - invalid. */
1265
1266	/* Opcode VEX.0F38 0xfb - invalid. */
1267	/* Opcode VEX.66.0F38 0xfb - invalid. */
1268	/* Opcode VEX.F3.0F38 0xfb - invalid. */
1269	/* Opcode VEX.F2.0F38 0xfb - invalid. */
1270
1271	/* Opcode VEX.0F38 0xfc - invalid. */
1272	/* Opcode VEX.66.0F38 0xfc - invalid. */
1273	/* Opcode VEX.F3.0F38 0xfc - invalid. */
1274	/* Opcode VEX.F2.0F38 0xfc - invalid. */
1275
1276	/* Opcode VEX.0F38 0xfd - invalid. */
1277	/* Opcode VEX.66.0F38 0xfd - invalid. */
1278	/* Opcode VEX.F3.0F38 0xfd - invalid. */
1279	/* Opcode VEX.F2.0F38 0xfd - invalid. */
1280
1281	/* Opcode VEX.0F38 0xfe - invalid. */
1282	/* Opcode VEX.66.0F38 0xfe - invalid. */
1283	/* Opcode VEX.F3.0F38 0xfe - invalid. */
1284	/* Opcode VEX.F2.0F38 0xfe - invalid. */
1285
1286	/* Opcode VEX.0F38 0xff - invalid. */
1287	/* Opcode VEX.66.0F38 0xff - invalid. */
1288	/* Opcode VEX.F3.0F38 0xff - invalid. */
1289	/* Opcode VEX.F2.0F38 0xff - invalid. */
1290
1291
1292	/**
1293	* VEX opcode map \#2.
1294	*
1295	* @sa g_apfnThreeByte0f38
1296	*/
1297	IEM_STATIC const PFNIEMOP g_apfnVexMap2[] =
1298	{
1299	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1300	/* 0x00 */ iemOp_InvalidNeedRM, iemOp_vpshufb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1301	/* 0x01 */ iemOp_InvalidNeedRM, iemOp_vphaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1302	/* 0x02 */ iemOp_InvalidNeedRM, iemOp_vphaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1303	/* 0x03 */ iemOp_InvalidNeedRM, iemOp_vphaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1304	/* 0x04 */ iemOp_InvalidNeedRM, iemOp_vpmaddubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1305	/* 0x05 */ iemOp_InvalidNeedRM, iemOp_vphsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1306	/* 0x06 */ iemOp_InvalidNeedRM, iemOp_vphsubdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1307	/* 0x07 */ iemOp_InvalidNeedRM, iemOp_vphsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1308	/* 0x08 */ iemOp_InvalidNeedRM, iemOp_vpsignb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1309	/* 0x09 */ iemOp_InvalidNeedRM, iemOp_vpsignw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1310	/* 0x0a */ iemOp_InvalidNeedRM, iemOp_vpsignd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1311	/* 0x0b */ iemOp_InvalidNeedRM, iemOp_vpmulhrsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1312	/* 0x0c */ iemOp_InvalidNeedRM, iemOp_vpermilps_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1313	/* 0x0d */ iemOp_InvalidNeedRM, iemOp_vpermilpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1314	/* 0x0e */ iemOp_InvalidNeedRM, iemOp_vtestps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1315	/* 0x0f */ iemOp_InvalidNeedRM, iemOp_vtestpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1316
1317	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRM),
1318	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
1319	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
1320	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
1321	/* 0x14 */ IEMOP_X4(iemOp_InvalidNeedRM),
1322	/* 0x15 */ IEMOP_X4(iemOp_InvalidNeedRM),
1323	/* 0x16 */ iemOp_InvalidNeedRM, iemOp_vpermps_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1324	/* 0x17 */ iemOp_InvalidNeedRM, iemOp_vptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1325	/* 0x18 */ iemOp_InvalidNeedRM, iemOp_vbroadcastss_Vx_Wd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1326	/* 0x19 */ iemOp_InvalidNeedRM, iemOp_vbroadcastsd_Vqq_Wq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1327	/* 0x1a */ iemOp_InvalidNeedRM, iemOp_vbroadcastf128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1328	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
1329	/* 0x1c */ iemOp_InvalidNeedRM, iemOp_vpabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1330	/* 0x1d */ iemOp_InvalidNeedRM, iemOp_vpabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1331	/* 0x1e */ iemOp_InvalidNeedRM, iemOp_vpabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1332	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
1333
1334	/* 0x20 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1335	/* 0x21 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1336	/* 0x22 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1337	/* 0x23 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1338	/* 0x24 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1339	/* 0x25 */ iemOp_InvalidNeedRM, iemOp_vpmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1340	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
1341	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
1342	/* 0x28 */ iemOp_InvalidNeedRM, iemOp_vpmuldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1343	/* 0x29 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1344	/* 0x2a */ iemOp_InvalidNeedRM, iemOp_vmovntdqa_Vx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1345	/* 0x2b */ iemOp_InvalidNeedRM, iemOp_vpackusdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1346	/* 0x2c */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1347	/* 0x2d */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1348	/* 0x2e */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1349	/* 0x2f */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1350
1351	/* 0x30 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1352	/* 0x31 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1353	/* 0x32 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1354	/* 0x33 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1355	/* 0x34 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1356	/* 0x35 */ iemOp_InvalidNeedRM, iemOp_vpmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1357	/* 0x36 */ iemOp_InvalidNeedRM, iemOp_vpermd_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1358	/* 0x37 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1359	/* 0x38 */ iemOp_InvalidNeedRM, iemOp_vpminsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1360	/* 0x39 */ iemOp_InvalidNeedRM, iemOp_vpminsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1361	/* 0x3a */ iemOp_InvalidNeedRM, iemOp_vpminuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1362	/* 0x3b */ iemOp_InvalidNeedRM, iemOp_vpminud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1363	/* 0x3c */ iemOp_InvalidNeedRM, iemOp_vpmaxsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1364	/* 0x3d */ iemOp_InvalidNeedRM, iemOp_vpmaxsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1365	/* 0x3e */ iemOp_InvalidNeedRM, iemOp_vpmaxuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1366	/* 0x3f */ iemOp_InvalidNeedRM, iemOp_vpmaxud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1367
1368	/* 0x40 */ iemOp_InvalidNeedRM, iemOp_vpmulld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1369	/* 0x41 */ iemOp_InvalidNeedRM, iemOp_vphminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1370	/* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
1371	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
1372	/* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
1373	/* 0x45 */ iemOp_InvalidNeedRM, iemOp_vpsrlvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1374	/* 0x46 */ iemOp_InvalidNeedRM, iemOp_vsravd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1375	/* 0x47 */ iemOp_InvalidNeedRM, iemOp_vpsllvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1376	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
1377	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
1378	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
1379	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
1380	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
1381	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
1382	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
1383	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
1384
1385	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
1386	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
1387	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
1388	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
1389	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
1390	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
1391	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
1392	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
1393	/* 0x58 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1394	/* 0x59 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1395	/* 0x5a */ iemOp_InvalidNeedRM, iemOp_vbroadcasti128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1396	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
1397	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
1398	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
1399	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
1400	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
1401
1402	/* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
1403	/* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
1404	/* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
1405	/* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
1406	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
1407	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
1408	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
1409	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
1410	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
1411	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
1412	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
1413	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
1414	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
1415	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
1416	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
1417	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
1418
1419	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
1420	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
1421	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
1422	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
1423	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
1424	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
1425	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
1426	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
1427	/* 0x78 */ iemOp_InvalidNeedRM, iemOp_vpboardcastb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1428	/* 0x79 */ iemOp_InvalidNeedRM, iemOp_vpboardcastw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1429	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
1430	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
1431	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
1432	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
1433	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
1434	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
1435
1436	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
1437	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
1438	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
1439	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
1440	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
1441	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
1442	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
1443	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
1444	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
1445	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
1446	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
1447	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
1448	/* 0x8c */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1449	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
1450	/* 0x8e */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Mx_Vx_Hx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1451	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
1452
1453	/* 0x90 */ iemOp_InvalidNeedRM, iemOp_vgatherdd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1454	/* 0x91 */ iemOp_InvalidNeedRM, iemOp_vgatherqd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1455	/* 0x92 */ iemOp_InvalidNeedRM, iemOp_vgatherdps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1456	/* 0x93 */ iemOp_InvalidNeedRM, iemOp_vgatherqps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1457	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
1458	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
1459	/* 0x96 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub132ps_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1460	/* 0x97 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1461	/* 0x98 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1462	/* 0x99 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1463	/* 0x9a */ iemOp_InvalidNeedRM, iemOp_vfmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1464	/* 0x9b */ iemOp_InvalidNeedRM, iemOp_vfmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1465	/* 0x9c */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1466	/* 0x9d */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1467	/* 0x9e */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1468	/* 0x9f */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1469
1470	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1471	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1472	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1473	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1474	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1475	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1476	/* 0xa6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1477	/* 0xa7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1478	/* 0xa8 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1479	/* 0xa9 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1480	/* 0xaa */ iemOp_InvalidNeedRM, iemOp_vfmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1481	/* 0xab */ iemOp_InvalidNeedRM, iemOp_vfmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1482	/* 0xac */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1483	/* 0xad */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1484	/* 0xae */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1485	/* 0xaf */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1486
1487	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1488	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1489	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1490	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1491	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1492	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1493	/* 0xb6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1494	/* 0xb7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1495	/* 0xb8 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1496	/* 0xb9 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1497	/* 0xba */ iemOp_InvalidNeedRM, iemOp_vfmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1498	/* 0xbb */ iemOp_InvalidNeedRM, iemOp_vfmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1499	/* 0xbc */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1500	/* 0xbd */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1501	/* 0xbe */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1502	/* 0xbf */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1503
1504	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1505	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1506	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1507	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1508	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1509	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1510	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1511	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1512	/* 0xc8 */ iemOp_vsha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1513	/* 0xc9 */ iemOp_vsha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1514	/* 0xca */ iemOp_vsha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1515	/* 0xcb */ iemOp_vsha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1516	/* 0xcc */ iemOp_vsha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1517	/* 0xcd */ iemOp_vsha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1518	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
1519	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
1520
1521	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1522	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1523	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1524	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1525	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1526	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1527	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1528	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1529	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1530	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1531	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
1532	/* 0xdb */ iemOp_InvalidNeedRM, iemOp_vaesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1533	/* 0xdc */ iemOp_InvalidNeedRM, iemOp_vaesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1534	/* 0xdd */ iemOp_InvalidNeedRM, iemOp_vaesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1535	/* 0xde */ iemOp_InvalidNeedRM, iemOp_vaesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1536	/* 0xdf */ iemOp_InvalidNeedRM, iemOp_vaesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1537
1538	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1539	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1540	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1541	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1542	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1543	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1544	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1545	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1546	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1547	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1548	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
1549	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
1550	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
1551	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
1552	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
1553	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
1554
1555	/* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1556	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1557	/* 0xf2 */ iemOp_andn_Gy_By_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1558	/* 0xf3 */ iemOp_VGrp17_f3, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1559	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1560	/* 0xf5 */ iemOp_bzhi_Gy_Ey_By, iemOp_InvalidNeedRM, iemOp_pext_Gy_By_Ey, iemOp_pdep_Gy_By_Ey,
1561	/* 0xf6 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_mulx_By_Gy_rDX_Ey,
1562	/* 0xf7 */ iemOp_bextr_Gy_Ey_By, iemOp_shlx_Gy_Ey_By, iemOp_sarx_Gy_Ey_By, iemOp_shrx_Gy_Ey_By,
1563	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1564	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1565	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
1566	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
1567	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
1568	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
1569	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
1570	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
1571	};
1572	AssertCompile(RT_ELEMENTS(g_apfnVexMap2) == 1024);
1573
1574	/** @} */
1575

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h@ 95517

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