IEMAllInstructionsVexMap2.cpp.h@ 95524

Last change on this file since 95524 was 95524, checked in by vboxsync, 3 years ago
VMM/IEM: Set some diasm flags.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 72.0 KB

Line
1	/* $Id: IEMAllInstructionsVexMap2.cpp.h 95524 2022-07-05 23:53:48Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation.
4	*
5	* @remarks IEMAllInstructionsThree0f38.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/** @name VEX Opcode Map 2
23	* @{
24	*/
25
26	/* Opcode VEX.0F38 0x00 - invalid. */
27
28
29	/** Opcode VEX.66.0F38 0x00. */
30	FNIEMOP_DEF(iemOp_vpshufb_Vx_Hx_Wx)
31	{
32	IEMOP_MNEMONIC3(VEX_RVM, VPSHUFB, vpshufb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
33	IEMOPMEDIAF3_INIT_VARS(vpshufb);
34	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
35	}
36
37
38	/* Opcode VEX.0F38 0x01 - invalid. */
39	/** Opcode VEX.66.0F38 0x01. */
40	FNIEMOP_STUB(iemOp_vphaddw_Vx_Hx_Wx);
41	/* Opcode VEX.0F38 0x02 - invalid. */
42	/** Opcode VEX.66.0F38 0x02. */
43	FNIEMOP_STUB(iemOp_vphaddd_Vx_Hx_Wx);
44	/* Opcode VEX.0F38 0x03 - invalid. */
45	/** Opcode VEX.66.0F38 0x03. */
46	FNIEMOP_STUB(iemOp_vphaddsw_Vx_Hx_Wx);
47	/* Opcode VEX.0F38 0x04 - invalid. */
48	/** Opcode VEX.66.0F38 0x04. */
49	FNIEMOP_STUB(iemOp_vpmaddubsw_Vx_Hx_Wx);
50	/* Opcode VEX.0F38 0x05 - invalid. */
51	/** Opcode VEX.66.0F38 0x05. */
52	FNIEMOP_STUB(iemOp_vphsubw_Vx_Hx_Wx);
53	/* Opcode VEX.0F38 0x06 - invalid. */
54	/** Opcode VEX.66.0F38 0x06. */
55	FNIEMOP_STUB(iemOp_vphsubdq_Vx_Hx_Wx);
56	/* Opcode VEX.0F38 0x07 - invalid. */
57	/** Opcode VEX.66.0F38 0x07. */
58	FNIEMOP_STUB(iemOp_vphsubsw_Vx_Hx_Wx);
59	/* Opcode VEX.0F38 0x08 - invalid. */
60	/** Opcode VEX.66.0F38 0x08. */
61	FNIEMOP_STUB(iemOp_vpsignb_Vx_Hx_Wx);
62	/* Opcode VEX.0F38 0x09 - invalid. */
63	/** Opcode VEX.66.0F38 0x09. */
64	FNIEMOP_STUB(iemOp_vpsignw_Vx_Hx_Wx);
65	/* Opcode VEX.0F38 0x0a - invalid. */
66	/** Opcode VEX.66.0F38 0x0a. */
67	FNIEMOP_STUB(iemOp_vpsignd_Vx_Hx_Wx);
68	/* Opcode VEX.0F38 0x0b - invalid. */
69	/** Opcode VEX.66.0F38 0x0b. */
70	FNIEMOP_STUB(iemOp_vpmulhrsw_Vx_Hx_Wx);
71	/* Opcode VEX.0F38 0x0c - invalid. */
72	/** Opcode VEX.66.0F38 0x0c. */
73	FNIEMOP_STUB(iemOp_vpermilps_Vx_Hx_Wx);
74	/* Opcode VEX.0F38 0x0d - invalid. */
75	/** Opcode VEX.66.0F38 0x0d. */
76	FNIEMOP_STUB(iemOp_vpermilpd_Vx_Hx_Wx);
77	/* Opcode VEX.0F38 0x0e - invalid. */
78	/** Opcode VEX.66.0F38 0x0e. */
79	FNIEMOP_STUB(iemOp_vtestps_Vx_Wx);
80	/* Opcode VEX.0F38 0x0f - invalid. */
81	/** Opcode VEX.66.0F38 0x0f. */
82	FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx);
83
84
85	/* Opcode VEX.0F38 0x10 - invalid */
86	/* Opcode VEX.66.0F38 0x10 - invalid (legacy only). */
87	/* Opcode VEX.0F38 0x11 - invalid */
88	/* Opcode VEX.66.0F38 0x11 - invalid */
89	/* Opcode VEX.0F38 0x12 - invalid */
90	/* Opcode VEX.66.0F38 0x12 - invalid */
91	/* Opcode VEX.0F38 0x13 - invalid */
92	/* Opcode VEX.66.0F38 0x13 - invalid (vex only). */
93	/* Opcode VEX.0F38 0x14 - invalid */
94	/* Opcode VEX.66.0F38 0x14 - invalid (legacy only). */
95	/* Opcode VEX.0F38 0x15 - invalid */
96	/* Opcode VEX.66.0F38 0x15 - invalid (legacy only). */
97	/* Opcode VEX.0F38 0x16 - invalid */
98	/** Opcode VEX.66.0F38 0x16. */
99	FNIEMOP_STUB(iemOp_vpermps_Vqq_Hqq_Wqq);
100	/* Opcode VEX.0F38 0x17 - invalid */
101	/** Opcode VEX.66.0F38 0x17 - invalid */
102	FNIEMOP_STUB(iemOp_vptest_Vx_Wx);
103	/* Opcode VEX.0F38 0x18 - invalid */
104	/** Opcode VEX.66.0F38 0x18. */
105	FNIEMOP_STUB(iemOp_vbroadcastss_Vx_Wd);
106	/* Opcode VEX.0F38 0x19 - invalid */
107	/** Opcode VEX.66.0F38 0x19. */
108	FNIEMOP_STUB(iemOp_vbroadcastsd_Vqq_Wq);
109	/* Opcode VEX.0F38 0x1a - invalid */
110	/** Opcode VEX.66.0F38 0x1a. */
111	FNIEMOP_STUB(iemOp_vbroadcastf128_Vqq_Mdq);
112	/* Opcode VEX.0F38 0x1b - invalid */
113	/* Opcode VEX.66.0F38 0x1b - invalid */
114	/* Opcode VEX.0F38 0x1c - invalid. */
115	/** Opcode VEX.66.0F38 0x1c. */
116	FNIEMOP_STUB(iemOp_vpabsb_Vx_Wx);
117	/* Opcode VEX.0F38 0x1d - invalid. */
118	/** Opcode VEX.66.0F38 0x1d. */
119	FNIEMOP_STUB(iemOp_vpabsw_Vx_Wx);
120	/* Opcode VEX.0F38 0x1e - invalid. */
121	/** Opcode VEX.66.0F38 0x1e. */
122	FNIEMOP_STUB(iemOp_vpabsd_Vx_Wx);
123	/* Opcode VEX.0F38 0x1f - invalid */
124	/* Opcode VEX.66.0F38 0x1f - invalid */
125
126
127	/** Opcode VEX.66.0F38 0x20. */
128	FNIEMOP_STUB(iemOp_vpmovsxbw_Vx_UxMq);
129	/** Opcode VEX.66.0F38 0x21. */
130	FNIEMOP_STUB(iemOp_vpmovsxbd_Vx_UxMd);
131	/** Opcode VEX.66.0F38 0x22. */
132	FNIEMOP_STUB(iemOp_vpmovsxbq_Vx_UxMw);
133	/** Opcode VEX.66.0F38 0x23. */
134	FNIEMOP_STUB(iemOp_vpmovsxwd_Vx_UxMq);
135	/** Opcode VEX.66.0F38 0x24. */
136	FNIEMOP_STUB(iemOp_vpmovsxwq_Vx_UxMd);
137	/** Opcode VEX.66.0F38 0x25. */
138	FNIEMOP_STUB(iemOp_vpmovsxdq_Vx_UxMq);
139	/* Opcode VEX.66.0F38 0x26 - invalid */
140	/* Opcode VEX.66.0F38 0x27 - invalid */
141	/** Opcode VEX.66.0F38 0x28. */
142	FNIEMOP_STUB(iemOp_vpmuldq_Vx_Hx_Wx);
143
144
145	/** Opcode VEX.66.0F38 0x29. */
146	FNIEMOP_DEF(iemOp_vpcmpeqq_Vx_Hx_Wx)
147	{
148	IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQQ, vpcmpeqq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
149	IEMOPMEDIAF3_INIT_VARS(vpcmpeqq);
150	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
151	}
152
153
154	FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
155	{
156	Assert(pVCpu->iem.s.uVexLength <= 1);
157	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
158	if (IEM_IS_MODRM_MEM_MODE(bRm))
159	{
160	if (pVCpu->iem.s.uVexLength == 0)
161	{
162	/**
163	* @opcode 0x2a
164	* @opcodesub !11 mr/reg vex.l=0
165	* @oppfx 0x66
166	* @opcpuid avx
167	* @opgroup og_avx_cachect
168	* @opxcpttype 1
169	* @optest op1=-1 op2=2 -> op1=2
170	* @optest op1=0 op2=-42 -> op1=-42
171	*/
172	/* 128-bit: Memory, register. */
173	IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
174	DISOPTYPE_HARMLESS \| DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
175	IEM_MC_BEGIN(0, 2);
176	IEM_MC_LOCAL(RTUINT128U, uSrc);
177	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
178
179	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
180	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
181	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
182	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
183
184	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
185	IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
186
187	IEM_MC_ADVANCE_RIP();
188	IEM_MC_END();
189	}
190	else
191	{
192	/**
193	* @opdone
194	* @opcode 0x2a
195	* @opcodesub !11 mr/reg vex.l=1
196	* @oppfx 0x66
197	* @opcpuid avx2
198	* @opgroup og_avx2_cachect
199	* @opxcpttype 1
200	* @optest op1=-1 op2=2 -> op1=2
201	* @optest op1=0 op2=-42 -> op1=-42
202	*/
203	/* 256-bit: Memory, register. */
204	IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
205	DISOPTYPE_HARMLESS \| DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
206	IEM_MC_BEGIN(0, 2);
207	IEM_MC_LOCAL(RTUINT256U, uSrc);
208	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
209
210	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
211	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
212	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
213	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
214
215	IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
216	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
217
218	IEM_MC_ADVANCE_RIP();
219	IEM_MC_END();
220	}
221	return VINF_SUCCESS;
222	}
223
224	/**
225	* @opdone
226	* @opmnemonic udvex660f382arg
227	* @opcode 0x2a
228	* @opcodesub 11 mr/reg
229	* @oppfx 0x66
230	* @opunused immediate
231	* @opcpuid avx
232	* @optest ->
233	*/
234	return IEMOP_RAISE_INVALID_OPCODE();
235	}
236
237
238	/** Opcode VEX.66.0F38 0x2b. */
239	FNIEMOP_DEF(iemOp_vpackusdw_Vx_Hx_Wx)
240	{
241	IEMOP_MNEMONIC3(VEX_RVM, VPACKUSDW, vpackusdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_AVX, 0);
242	IEMOPMEDIAOPTF3_INIT_VARS( vpackusdw);
243	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
244	}
245
246
247	/** Opcode VEX.66.0F38 0x2c. */
248	FNIEMOP_STUB(iemOp_vmaskmovps_Vx_Hx_Mx);
249	/** Opcode VEX.66.0F38 0x2d. */
250	FNIEMOP_STUB(iemOp_vmaskmovpd_Vx_Hx_Mx);
251	/** Opcode VEX.66.0F38 0x2e. */
252	FNIEMOP_STUB(iemOp_vmaskmovps_Mx_Hx_Vx);
253	/** Opcode VEX.66.0F38 0x2f. */
254	FNIEMOP_STUB(iemOp_vmaskmovpd_Mx_Hx_Vx);
255
256	/** Opcode VEX.66.0F38 0x30. */
257	FNIEMOP_STUB(iemOp_vpmovzxbw_Vx_UxMq);
258	/** Opcode VEX.66.0F38 0x31. */
259	FNIEMOP_STUB(iemOp_vpmovzxbd_Vx_UxMd);
260	/** Opcode VEX.66.0F38 0x32. */
261	FNIEMOP_STUB(iemOp_vpmovzxbq_Vx_UxMw);
262	/** Opcode VEX.66.0F38 0x33. */
263	FNIEMOP_STUB(iemOp_vpmovzxwd_Vx_UxMq);
264	/** Opcode VEX.66.0F38 0x34. */
265	FNIEMOP_STUB(iemOp_vpmovzxwq_Vx_UxMd);
266	/** Opcode VEX.66.0F38 0x35. */
267	FNIEMOP_STUB(iemOp_vpmovzxdq_Vx_UxMq);
268	/* Opcode VEX.66.0F38 0x36. */
269	FNIEMOP_STUB(iemOp_vpermd_Vqq_Hqq_Wqq);
270
271
272	/** Opcode VEX.66.0F38 0x37. */
273	FNIEMOP_DEF(iemOp_vpcmpgtq_Vx_Hx_Wx)
274	{
275	IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTQ, vpcmpgtq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
276	IEMOPMEDIAF3_INIT_VARS(vpcmpgtq);
277	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
278	}
279
280
281	/** Opcode VEX.66.0F38 0x38. */
282	FNIEMOP_STUB(iemOp_vpminsb_Vx_Hx_Wx);
283	/** Opcode VEX.66.0F38 0x39. */
284	FNIEMOP_STUB(iemOp_vpminsd_Vx_Hx_Wx);
285	/** Opcode VEX.66.0F38 0x3a. */
286	FNIEMOP_STUB(iemOp_vpminuw_Vx_Hx_Wx);
287	/** Opcode VEX.66.0F38 0x3b. */
288	FNIEMOP_STUB(iemOp_vpminud_Vx_Hx_Wx);
289	/** Opcode VEX.66.0F38 0x3c. */
290	FNIEMOP_STUB(iemOp_vpmaxsb_Vx_Hx_Wx);
291	/** Opcode VEX.66.0F38 0x3d. */
292	FNIEMOP_STUB(iemOp_vpmaxsd_Vx_Hx_Wx);
293	/** Opcode VEX.66.0F38 0x3e. */
294	FNIEMOP_STUB(iemOp_vpmaxuw_Vx_Hx_Wx);
295	/** Opcode VEX.66.0F38 0x3f. */
296	FNIEMOP_STUB(iemOp_vpmaxud_Vx_Hx_Wx);
297
298
299	/** Opcode VEX.66.0F38 0x40. */
300	FNIEMOP_STUB(iemOp_vpmulld_Vx_Hx_Wx);
301	/** Opcode VEX.66.0F38 0x41. */
302	FNIEMOP_STUB(iemOp_vphminposuw_Vdq_Wdq);
303	/* Opcode VEX.66.0F38 0x42 - invalid. */
304	/* Opcode VEX.66.0F38 0x43 - invalid. */
305	/* Opcode VEX.66.0F38 0x44 - invalid. */
306	/** Opcode VEX.66.0F38 0x45. */
307	FNIEMOP_STUB(iemOp_vpsrlvd_q_Vx_Hx_Wx);
308	/** Opcode VEX.66.0F38 0x46. */
309	FNIEMOP_STUB(iemOp_vsravd_Vx_Hx_Wx);
310	/** Opcode VEX.66.0F38 0x47. */
311	FNIEMOP_STUB(iemOp_vpsllvd_q_Vx_Hx_Wx);
312	/* Opcode VEX.66.0F38 0x48 - invalid. */
313	/* Opcode VEX.66.0F38 0x49 - invalid. */
314	/* Opcode VEX.66.0F38 0x4a - invalid. */
315	/* Opcode VEX.66.0F38 0x4b - invalid. */
316	/* Opcode VEX.66.0F38 0x4c - invalid. */
317	/* Opcode VEX.66.0F38 0x4d - invalid. */
318	/* Opcode VEX.66.0F38 0x4e - invalid. */
319	/* Opcode VEX.66.0F38 0x4f - invalid. */
320
321	/* Opcode VEX.66.0F38 0x50 - invalid. */
322	/* Opcode VEX.66.0F38 0x51 - invalid. */
323	/* Opcode VEX.66.0F38 0x52 - invalid. */
324	/* Opcode VEX.66.0F38 0x53 - invalid. */
325	/* Opcode VEX.66.0F38 0x54 - invalid. */
326	/* Opcode VEX.66.0F38 0x55 - invalid. */
327	/* Opcode VEX.66.0F38 0x56 - invalid. */
328	/* Opcode VEX.66.0F38 0x57 - invalid. */
329	/** Opcode VEX.66.0F38 0x58. */
330	FNIEMOP_STUB(iemOp_vpbroadcastd_Vx_Wx);
331	/** Opcode VEX.66.0F38 0x59. */
332	FNIEMOP_STUB(iemOp_vpbroadcastq_Vx_Wx);
333	/** Opcode VEX.66.0F38 0x5a. */
334	FNIEMOP_STUB(iemOp_vbroadcasti128_Vqq_Mdq);
335	/* Opcode VEX.66.0F38 0x5b - invalid. */
336	/* Opcode VEX.66.0F38 0x5c - invalid. */
337	/* Opcode VEX.66.0F38 0x5d - invalid. */
338	/* Opcode VEX.66.0F38 0x5e - invalid. */
339	/* Opcode VEX.66.0F38 0x5f - invalid. */
340
341	/* Opcode VEX.66.0F38 0x60 - invalid. */
342	/* Opcode VEX.66.0F38 0x61 - invalid. */
343	/* Opcode VEX.66.0F38 0x62 - invalid. */
344	/* Opcode VEX.66.0F38 0x63 - invalid. */
345	/* Opcode VEX.66.0F38 0x64 - invalid. */
346	/* Opcode VEX.66.0F38 0x65 - invalid. */
347	/* Opcode VEX.66.0F38 0x66 - invalid. */
348	/* Opcode VEX.66.0F38 0x67 - invalid. */
349	/* Opcode VEX.66.0F38 0x68 - invalid. */
350	/* Opcode VEX.66.0F38 0x69 - invalid. */
351	/* Opcode VEX.66.0F38 0x6a - invalid. */
352	/* Opcode VEX.66.0F38 0x6b - invalid. */
353	/* Opcode VEX.66.0F38 0x6c - invalid. */
354	/* Opcode VEX.66.0F38 0x6d - invalid. */
355	/* Opcode VEX.66.0F38 0x6e - invalid. */
356	/* Opcode VEX.66.0F38 0x6f - invalid. */
357
358	/* Opcode VEX.66.0F38 0x70 - invalid. */
359	/* Opcode VEX.66.0F38 0x71 - invalid. */
360	/* Opcode VEX.66.0F38 0x72 - invalid. */
361	/* Opcode VEX.66.0F38 0x73 - invalid. */
362	/* Opcode VEX.66.0F38 0x74 - invalid. */
363	/* Opcode VEX.66.0F38 0x75 - invalid. */
364	/* Opcode VEX.66.0F38 0x76 - invalid. */
365	/* Opcode VEX.66.0F38 0x77 - invalid. */
366	/** Opcode VEX.66.0F38 0x78. */
367	FNIEMOP_STUB(iemOp_vpboardcastb_Vx_Wx);
368	/** Opcode VEX.66.0F38 0x79. */
369	FNIEMOP_STUB(iemOp_vpboardcastw_Vx_Wx);
370	/* Opcode VEX.66.0F38 0x7a - invalid. */
371	/* Opcode VEX.66.0F38 0x7b - invalid. */
372	/* Opcode VEX.66.0F38 0x7c - invalid. */
373	/* Opcode VEX.66.0F38 0x7d - invalid. */
374	/* Opcode VEX.66.0F38 0x7e - invalid. */
375	/* Opcode VEX.66.0F38 0x7f - invalid. */
376
377	/* Opcode VEX.66.0F38 0x80 - invalid (legacy only). */
378	/* Opcode VEX.66.0F38 0x81 - invalid (legacy only). */
379	/* Opcode VEX.66.0F38 0x82 - invalid (legacy only). */
380	/* Opcode VEX.66.0F38 0x83 - invalid. */
381	/* Opcode VEX.66.0F38 0x84 - invalid. */
382	/* Opcode VEX.66.0F38 0x85 - invalid. */
383	/* Opcode VEX.66.0F38 0x86 - invalid. */
384	/* Opcode VEX.66.0F38 0x87 - invalid. */
385	/* Opcode VEX.66.0F38 0x88 - invalid. */
386	/* Opcode VEX.66.0F38 0x89 - invalid. */
387	/* Opcode VEX.66.0F38 0x8a - invalid. */
388	/* Opcode VEX.66.0F38 0x8b - invalid. */
389	/** Opcode VEX.66.0F38 0x8c. */
390	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Vx_Hx_Mx);
391	/* Opcode VEX.66.0F38 0x8d - invalid. */
392	/** Opcode VEX.66.0F38 0x8e. */
393	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Mx_Vx_Hx);
394	/* Opcode VEX.66.0F38 0x8f - invalid. */
395
396	/** Opcode VEX.66.0F38 0x90 (vex only). */
397	FNIEMOP_STUB(iemOp_vgatherdd_q_Vx_Hx_Wx);
398	/** Opcode VEX.66.0F38 0x91 (vex only). */
399	FNIEMOP_STUB(iemOp_vgatherqd_q_Vx_Hx_Wx);
400	/** Opcode VEX.66.0F38 0x92 (vex only). */
401	FNIEMOP_STUB(iemOp_vgatherdps_d_Vx_Hx_Wx);
402	/** Opcode VEX.66.0F38 0x93 (vex only). */
403	FNIEMOP_STUB(iemOp_vgatherqps_d_Vx_Hx_Wx);
404	/* Opcode VEX.66.0F38 0x94 - invalid. */
405	/* Opcode VEX.66.0F38 0x95 - invalid. */
406	/** Opcode VEX.66.0F38 0x96 (vex only). */
407	FNIEMOP_STUB(iemOp_vfmaddsub132ps_q_Vx_Hx_Wx);
408	/** Opcode VEX.66.0F38 0x97 (vex only). */
409	FNIEMOP_STUB(iemOp_vfmsubadd132ps_d_Vx_Hx_Wx);
410	/** Opcode VEX.66.0F38 0x98 (vex only). */
411	FNIEMOP_STUB(iemOp_vfmadd132ps_d_Vx_Hx_Wx);
412	/** Opcode VEX.66.0F38 0x99 (vex only). */
413	FNIEMOP_STUB(iemOp_vfmadd132ss_d_Vx_Hx_Wx);
414	/** Opcode VEX.66.0F38 0x9a (vex only). */
415	FNIEMOP_STUB(iemOp_vfmsub132ps_d_Vx_Hx_Wx);
416	/** Opcode VEX.66.0F38 0x9b (vex only). */
417	FNIEMOP_STUB(iemOp_vfmsub132ss_d_Vx_Hx_Wx);
418	/** Opcode VEX.66.0F38 0x9c (vex only). */
419	FNIEMOP_STUB(iemOp_vfnmadd132ps_d_Vx_Hx_Wx);
420	/** Opcode VEX.66.0F38 0x9d (vex only). */
421	FNIEMOP_STUB(iemOp_vfnmadd132ss_d_Vx_Hx_Wx);
422	/** Opcode VEX.66.0F38 0x9e (vex only). */
423	FNIEMOP_STUB(iemOp_vfnmsub132ps_d_Vx_Hx_Wx);
424	/** Opcode VEX.66.0F38 0x9f (vex only). */
425	FNIEMOP_STUB(iemOp_vfnmsub132ss_d_Vx_Hx_Wx);
426
427	/* Opcode VEX.66.0F38 0xa0 - invalid. */
428	/* Opcode VEX.66.0F38 0xa1 - invalid. */
429	/* Opcode VEX.66.0F38 0xa2 - invalid. */
430	/* Opcode VEX.66.0F38 0xa3 - invalid. */
431	/* Opcode VEX.66.0F38 0xa4 - invalid. */
432	/* Opcode VEX.66.0F38 0xa5 - invalid. */
433	/** Opcode VEX.66.0F38 0xa6 (vex only). */
434	FNIEMOP_STUB(iemOp_vfmaddsub213ps_d_Vx_Hx_Wx);
435	/** Opcode VEX.66.0F38 0xa7 (vex only). */
436	FNIEMOP_STUB(iemOp_vfmsubadd213ps_d_Vx_Hx_Wx);
437	/** Opcode VEX.66.0F38 0xa8 (vex only). */
438	FNIEMOP_STUB(iemOp_vfmadd213ps_d_Vx_Hx_Wx);
439	/** Opcode VEX.66.0F38 0xa9 (vex only). */
440	FNIEMOP_STUB(iemOp_vfmadd213ss_d_Vx_Hx_Wx);
441	/** Opcode VEX.66.0F38 0xaa (vex only). */
442	FNIEMOP_STUB(iemOp_vfmsub213ps_d_Vx_Hx_Wx);
443	/** Opcode VEX.66.0F38 0xab (vex only). */
444	FNIEMOP_STUB(iemOp_vfmsub213ss_d_Vx_Hx_Wx);
445	/** Opcode VEX.66.0F38 0xac (vex only). */
446	FNIEMOP_STUB(iemOp_vfnmadd213ps_d_Vx_Hx_Wx);
447	/** Opcode VEX.66.0F38 0xad (vex only). */
448	FNIEMOP_STUB(iemOp_vfnmadd213ss_d_Vx_Hx_Wx);
449	/** Opcode VEX.66.0F38 0xae (vex only). */
450	FNIEMOP_STUB(iemOp_vfnmsub213ps_d_Vx_Hx_Wx);
451	/** Opcode VEX.66.0F38 0xaf (vex only). */
452	FNIEMOP_STUB(iemOp_vfnmsub213ss_d_Vx_Hx_Wx);
453
454	/* Opcode VEX.66.0F38 0xb0 - invalid. */
455	/* Opcode VEX.66.0F38 0xb1 - invalid. */
456	/* Opcode VEX.66.0F38 0xb2 - invalid. */
457	/* Opcode VEX.66.0F38 0xb3 - invalid. */
458	/* Opcode VEX.66.0F38 0xb4 - invalid. */
459	/* Opcode VEX.66.0F38 0xb5 - invalid. */
460	/** Opcode VEX.66.0F38 0xb6 (vex only). */
461	FNIEMOP_STUB(iemOp_vfmaddsub231ps_d_Vx_Hx_Wx);
462	/** Opcode VEX.66.0F38 0xb7 (vex only). */
463	FNIEMOP_STUB(iemOp_vfmsubadd231ps_d_Vx_Hx_Wx);
464	/** Opcode VEX.66.0F38 0xb8 (vex only). */
465	FNIEMOP_STUB(iemOp_vfmadd231ps_d_Vx_Hx_Wx);
466	/** Opcode VEX.66.0F38 0xb9 (vex only). */
467	FNIEMOP_STUB(iemOp_vfmadd231ss_d_Vx_Hx_Wx);
468	/** Opcode VEX.66.0F38 0xba (vex only). */
469	FNIEMOP_STUB(iemOp_vfmsub231ps_d_Vx_Hx_Wx);
470	/** Opcode VEX.66.0F38 0xbb (vex only). */
471	FNIEMOP_STUB(iemOp_vfmsub231ss_d_Vx_Hx_Wx);
472	/** Opcode VEX.66.0F38 0xbc (vex only). */
473	FNIEMOP_STUB(iemOp_vfnmadd231ps_d_Vx_Hx_Wx);
474	/** Opcode VEX.66.0F38 0xbd (vex only). */
475	FNIEMOP_STUB(iemOp_vfnmadd231ss_d_Vx_Hx_Wx);
476	/** Opcode VEX.66.0F38 0xbe (vex only). */
477	FNIEMOP_STUB(iemOp_vfnmsub231ps_d_Vx_Hx_Wx);
478	/** Opcode VEX.66.0F38 0xbf (vex only). */
479	FNIEMOP_STUB(iemOp_vfnmsub231ss_d_Vx_Hx_Wx);
480
481	/* Opcode VEX.0F38 0xc0 - invalid. */
482	/* Opcode VEX.66.0F38 0xc0 - invalid. */
483	/* Opcode VEX.0F38 0xc1 - invalid. */
484	/* Opcode VEX.66.0F38 0xc1 - invalid. */
485	/* Opcode VEX.0F38 0xc2 - invalid. */
486	/* Opcode VEX.66.0F38 0xc2 - invalid. */
487	/* Opcode VEX.0F38 0xc3 - invalid. */
488	/* Opcode VEX.66.0F38 0xc3 - invalid. */
489	/* Opcode VEX.0F38 0xc4 - invalid. */
490	/* Opcode VEX.66.0F38 0xc4 - invalid. */
491	/* Opcode VEX.0F38 0xc5 - invalid. */
492	/* Opcode VEX.66.0F38 0xc5 - invalid. */
493	/* Opcode VEX.0F38 0xc6 - invalid. */
494	/* Opcode VEX.66.0F38 0xc6 - invalid. */
495	/* Opcode VEX.0F38 0xc7 - invalid. */
496	/* Opcode VEX.66.0F38 0xc7 - invalid. */
497	/** Opcode VEX.0F38 0xc8. */
498	FNIEMOP_STUB(iemOp_vsha1nexte_Vdq_Wdq);
499	/* Opcode VEX.66.0F38 0xc8 - invalid. */
500	/** Opcode VEX.0F38 0xc9. */
501	FNIEMOP_STUB(iemOp_vsha1msg1_Vdq_Wdq);
502	/* Opcode VEX.66.0F38 0xc9 - invalid. */
503	/** Opcode VEX.0F38 0xca. */
504	FNIEMOP_STUB(iemOp_vsha1msg2_Vdq_Wdq);
505	/* Opcode VEX.66.0F38 0xca - invalid. */
506	/** Opcode VEX.0F38 0xcb. */
507	FNIEMOP_STUB(iemOp_vsha256rnds2_Vdq_Wdq);
508	/* Opcode VEX.66.0F38 0xcb - invalid. */
509	/** Opcode VEX.0F38 0xcc. */
510	FNIEMOP_STUB(iemOp_vsha256msg1_Vdq_Wdq);
511	/* Opcode VEX.66.0F38 0xcc - invalid. */
512	/** Opcode VEX.0F38 0xcd. */
513	FNIEMOP_STUB(iemOp_vsha256msg2_Vdq_Wdq);
514	/* Opcode VEX.66.0F38 0xcd - invalid. */
515	/* Opcode VEX.0F38 0xce - invalid. */
516	/* Opcode VEX.66.0F38 0xce - invalid. */
517	/* Opcode VEX.0F38 0xcf - invalid. */
518	/* Opcode VEX.66.0F38 0xcf - invalid. */
519
520	/* Opcode VEX.66.0F38 0xd0 - invalid. */
521	/* Opcode VEX.66.0F38 0xd1 - invalid. */
522	/* Opcode VEX.66.0F38 0xd2 - invalid. */
523	/* Opcode VEX.66.0F38 0xd3 - invalid. */
524	/* Opcode VEX.66.0F38 0xd4 - invalid. */
525	/* Opcode VEX.66.0F38 0xd5 - invalid. */
526	/* Opcode VEX.66.0F38 0xd6 - invalid. */
527	/* Opcode VEX.66.0F38 0xd7 - invalid. */
528	/* Opcode VEX.66.0F38 0xd8 - invalid. */
529	/* Opcode VEX.66.0F38 0xd9 - invalid. */
530	/* Opcode VEX.66.0F38 0xda - invalid. */
531	/** Opcode VEX.66.0F38 0xdb. */
532	FNIEMOP_STUB(iemOp_vaesimc_Vdq_Wdq);
533	/** Opcode VEX.66.0F38 0xdc. */
534	FNIEMOP_STUB(iemOp_vaesenc_Vdq_Wdq);
535	/** Opcode VEX.66.0F38 0xdd. */
536	FNIEMOP_STUB(iemOp_vaesenclast_Vdq_Wdq);
537	/** Opcode VEX.66.0F38 0xde. */
538	FNIEMOP_STUB(iemOp_vaesdec_Vdq_Wdq);
539	/** Opcode VEX.66.0F38 0xdf. */
540	FNIEMOP_STUB(iemOp_vaesdeclast_Vdq_Wdq);
541
542	/* Opcode VEX.66.0F38 0xe0 - invalid. */
543	/* Opcode VEX.66.0F38 0xe1 - invalid. */
544	/* Opcode VEX.66.0F38 0xe2 - invalid. */
545	/* Opcode VEX.66.0F38 0xe3 - invalid. */
546	/* Opcode VEX.66.0F38 0xe4 - invalid. */
547	/* Opcode VEX.66.0F38 0xe5 - invalid. */
548	/* Opcode VEX.66.0F38 0xe6 - invalid. */
549	/* Opcode VEX.66.0F38 0xe7 - invalid. */
550	/* Opcode VEX.66.0F38 0xe8 - invalid. */
551	/* Opcode VEX.66.0F38 0xe9 - invalid. */
552	/* Opcode VEX.66.0F38 0xea - invalid. */
553	/* Opcode VEX.66.0F38 0xeb - invalid. */
554	/* Opcode VEX.66.0F38 0xec - invalid. */
555	/* Opcode VEX.66.0F38 0xed - invalid. */
556	/* Opcode VEX.66.0F38 0xee - invalid. */
557	/* Opcode VEX.66.0F38 0xef - invalid. */
558
559
560	/* Opcode VEX.0F38 0xf0 - invalid (legacy only). */
561	/* Opcode VEX.66.0F38 0xf0 - invalid (legacy only). */
562	/* Opcode VEX.F3.0F38 0xf0 - invalid. */
563	/* Opcode VEX.F2.0F38 0xf0 - invalid (legacy only). */
564
565	/* Opcode VEX.0F38 0xf1 - invalid (legacy only). */
566	/* Opcode VEX.66.0F38 0xf1 - invalid (legacy only). */
567	/* Opcode VEX.F3.0F38 0xf1 - invalid. */
568	/* Opcode VEX.F2.0F38 0xf1 - invalid (legacy only). */
569
570	/** Opcode VEX.0F38 0xf2 - ANDN (vex only). */
571	FNIEMOP_DEF(iemOp_andn_Gy_By_Ey)
572	{
573	IEMOP_MNEMONIC3(VEX_RVM, ANDN, andn, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
574	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1)
575	return iemOp_InvalidNeedRM(pVCpu);
576	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF);
577	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
578	if (IEM_IS_MODRM_REG_MODE(bRm))
579	{
580	/*
581	* Register, register.
582	*/
583	IEMOP_HLP_DONE_VEX_DECODING_L0();
584	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
585	{
586	IEM_MC_BEGIN(4, 0);
587	IEM_MC_ARG(uint64_t *, pDst, 0);
588	IEM_MC_ARG(uint64_t, uSrc1, 1);
589	IEM_MC_ARG(uint64_t, uSrc2, 2);
590	IEM_MC_ARG(uint32_t *, pEFlags, 3);
591	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
592	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
593	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
594	IEM_MC_REF_EFLAGS(pEFlags);
595	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
596	pDst, uSrc1, uSrc2, pEFlags);
597	IEM_MC_ADVANCE_RIP();
598	IEM_MC_END();
599	}
600	else
601	{
602	IEM_MC_BEGIN(4, 0);
603	IEM_MC_ARG(uint32_t *, pDst, 0);
604	IEM_MC_ARG(uint32_t, uSrc1, 1);
605	IEM_MC_ARG(uint32_t, uSrc2, 2);
606	IEM_MC_ARG(uint32_t *, pEFlags, 3);
607	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
608	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
609	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
610	IEM_MC_REF_EFLAGS(pEFlags);
611	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
612	pDst, uSrc1, uSrc2, pEFlags);
613	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
614	IEM_MC_ADVANCE_RIP();
615	IEM_MC_END();
616	}
617	}
618	else
619	{
620	/*
621	* Register, memory.
622	*/
623	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
624	{
625	IEM_MC_BEGIN(4, 1);
626	IEM_MC_ARG(uint64_t *, pDst, 0);
627	IEM_MC_ARG(uint64_t, uSrc1, 1);
628	IEM_MC_ARG(uint64_t, uSrc2, 2);
629	IEM_MC_ARG(uint32_t *, pEFlags, 3);
630	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
631	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
632	IEMOP_HLP_DONE_VEX_DECODING_L0();
633	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
634	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
635	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
636	IEM_MC_REF_EFLAGS(pEFlags);
637	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
638	pDst, uSrc1, uSrc2, pEFlags);
639	IEM_MC_ADVANCE_RIP();
640	IEM_MC_END();
641	}
642	else
643	{
644	IEM_MC_BEGIN(4, 1);
645	IEM_MC_ARG(uint32_t *, pDst, 0);
646	IEM_MC_ARG(uint32_t, uSrc1, 1);
647	IEM_MC_ARG(uint32_t, uSrc2, 2);
648	IEM_MC_ARG(uint32_t *, pEFlags, 3);
649	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
650	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
651	IEMOP_HLP_DONE_VEX_DECODING_L0();
652	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
653	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
654	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
655	IEM_MC_REF_EFLAGS(pEFlags);
656	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
657	pDst, uSrc1, uSrc2, pEFlags);
658	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
659	IEM_MC_ADVANCE_RIP();
660	IEM_MC_END();
661	}
662	}
663	return VINF_SUCCESS;
664	}
665
666	/* Opcode VEX.66.0F38 0xf2 - invalid. */
667	/* Opcode VEX.F3.0F38 0xf2 - invalid. */
668	/* Opcode VEX.F2.0F38 0xf2 - invalid. */
669
670
671	/* Opcode VEX.0F38 0xf3 - invalid. */
672	/* Opcode VEX.66.0F38 0xf3 - invalid. */
673
674	/* Opcode VEX.F3.0F38 0xf3 /0 - invalid. */
675
676	/** Body for the vex group 17 instructions. */
677	#define IEMOP_BODY_By_Ey(a_Instr) \
678	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1) \
679	return iemOp_InvalidWithRM(pVCpu, bRm); /* decode memory variant? */ \
680	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF); \
681	if (IEM_IS_MODRM_REG_MODE(bRm)) \
682	{ \
683	/* \
684	* Register, register. \
685	*/ \
686	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
687	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
688	{ \
689	IEM_MC_BEGIN(3, 0); \
690	IEM_MC_ARG(uint64_t *, pDst, 0); \
691	IEM_MC_ARG(uint64_t, uSrc, 1); \
692	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
693	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
694	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
695	IEM_MC_REF_EFLAGS(pEFlags); \
696	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
697	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
698	IEM_MC_ADVANCE_RIP(); \
699	IEM_MC_END(); \
700	} \
701	else \
702	{ \
703	IEM_MC_BEGIN(3, 0); \
704	IEM_MC_ARG(uint32_t *, pDst, 0); \
705	IEM_MC_ARG(uint32_t, uSrc, 1); \
706	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
707	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
708	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
709	IEM_MC_REF_EFLAGS(pEFlags); \
710	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
711	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
712	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
713	IEM_MC_ADVANCE_RIP(); \
714	IEM_MC_END(); \
715	} \
716	} \
717	else \
718	{ \
719	/* \
720	* Register, memory. \
721	*/ \
722	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
723	{ \
724	IEM_MC_BEGIN(3, 1); \
725	IEM_MC_ARG(uint64_t *, pDst, 0); \
726	IEM_MC_ARG(uint64_t, uSrc, 1); \
727	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
728	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
729	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
730	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
731	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
732	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
733	IEM_MC_REF_EFLAGS(pEFlags); \
734	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
735	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
736	IEM_MC_ADVANCE_RIP(); \
737	IEM_MC_END(); \
738	} \
739	else \
740	{ \
741	IEM_MC_BEGIN(3, 1); \
742	IEM_MC_ARG(uint32_t *, pDst, 0); \
743	IEM_MC_ARG(uint32_t, uSrc, 1); \
744	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
745	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
746	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
747	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
748	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
749	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
750	IEM_MC_REF_EFLAGS(pEFlags); \
751	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
752	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
753	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
754	IEM_MC_ADVANCE_RIP(); \
755	IEM_MC_END(); \
756	} \
757	} \
758	return VINF_SUCCESS
759
760
761	/* Opcode VEX.F3.0F38 0xf3 /1. */
762	/** @opcode /1
763	* @opmaps vexgrp17 */
764	FNIEMOP_DEF_1(iemOp_VGrp17_blsr_By_Ey, uint8_t, bRm)
765	{
766	IEMOP_MNEMONIC2(VEX_VM, BLSR, blsr, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
767	IEMOP_BODY_By_Ey(blsr);
768	}
769
770
771	/* Opcode VEX.F3.0F38 0xf3 /2. */
772	/** @opcode /2
773	* @opmaps vexgrp17 */
774	FNIEMOP_DEF_1(iemOp_VGrp17_blsmsk_By_Ey, uint8_t, bRm)
775	{
776	IEMOP_MNEMONIC2(VEX_VM, BLSMSK, blsmsk, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
777	IEMOP_BODY_By_Ey(blsmsk);
778	}
779
780
781	/* Opcode VEX.F3.0F38 0xf3 /3. */
782	/** @opcode /3
783	* @opmaps vexgrp17 */
784	FNIEMOP_DEF_1(iemOp_VGrp17_blsi_By_Ey, uint8_t, bRm)
785	{
786	IEMOP_MNEMONIC2(VEX_VM, BLSI, blsi, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
787	IEMOP_BODY_By_Ey(blsi);
788	}
789
790
791	/* Opcode VEX.F3.0F38 0xf3 /4 - invalid. */
792	/* Opcode VEX.F3.0F38 0xf3 /5 - invalid. */
793	/* Opcode VEX.F3.0F38 0xf3 /6 - invalid. */
794	/* Opcode VEX.F3.0F38 0xf3 /7 - invalid. */
795
796	/**
797	* Group 17 jump table for the VEX.F3 variant.
798	*/
799	IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =
800	{
801	/* /0 */ iemOp_InvalidWithRM,
802	/* /1 */ iemOp_VGrp17_blsr_By_Ey,
803	/* /2 */ iemOp_VGrp17_blsmsk_By_Ey,
804	/* /3 */ iemOp_VGrp17_blsi_By_Ey,
805	/* /4 */ iemOp_InvalidWithRM,
806	/* /5 */ iemOp_InvalidWithRM,
807	/* /6 */ iemOp_InvalidWithRM,
808	/* /7 */ iemOp_InvalidWithRM
809	};
810	AssertCompile(RT_ELEMENTS(g_apfnVexGroup17_f3) == 8);
811
812	/** Opcode VEX.F3.0F38 0xf3 - invalid (vex only - group 17). */
813	FNIEMOP_DEF(iemOp_VGrp17_f3)
814	{
815	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
816	return FNIEMOP_CALL_1(g_apfnVexGroup17_f3[IEM_GET_MODRM_REG_8(bRm)], bRm);
817	}
818
819	/* Opcode VEX.F2.0F38 0xf3 - invalid (vex only - group 17). */
820
821
822	/* Opcode VEX.0F38 0xf4 - invalid. */
823	/* Opcode VEX.66.0F38 0xf4 - invalid. */
824	/* Opcode VEX.F3.0F38 0xf4 - invalid. */
825	/* Opcode VEX.F2.0F38 0xf4 - invalid. */
826
827	/** Body for BZHI, BEXTR, ++; assumes VEX.L must be 0. */
828	#define IEMOP_BODY_Gy_Ey_By(a_Instr, a_fFeatureMember, a_fUndefFlags) \
829	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
830	return iemOp_InvalidNeedRM(pVCpu); \
831	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
832	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
833	if (IEM_IS_MODRM_REG_MODE(bRm)) \
834	{ \
835	/* \
836	* Register, register. \
837	*/ \
838	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
839	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
840	{ \
841	IEM_MC_BEGIN(4, 0); \
842	IEM_MC_ARG(uint64_t *, pDst, 0); \
843	IEM_MC_ARG(uint64_t, uSrc1, 1); \
844	IEM_MC_ARG(uint64_t, uSrc2, 2); \
845	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
846	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
847	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
848	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
849	IEM_MC_REF_EFLAGS(pEFlags); \
850	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
851	iemAImpl_ ## a_Instr ## _u64_fallback), \
852	pDst, uSrc1, uSrc2, pEFlags); \
853	IEM_MC_ADVANCE_RIP(); \
854	IEM_MC_END(); \
855	} \
856	else \
857	{ \
858	IEM_MC_BEGIN(4, 0); \
859	IEM_MC_ARG(uint32_t *, pDst, 0); \
860	IEM_MC_ARG(uint32_t, uSrc1, 1); \
861	IEM_MC_ARG(uint32_t, uSrc2, 2); \
862	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
863	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
864	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
865	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
866	IEM_MC_REF_EFLAGS(pEFlags); \
867	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
868	iemAImpl_ ## a_Instr ## _u32_fallback), \
869	pDst, uSrc1, uSrc2, pEFlags); \
870	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
871	IEM_MC_ADVANCE_RIP(); \
872	IEM_MC_END(); \
873	} \
874	} \
875	else \
876	{ \
877	/* \
878	* Register, memory. \
879	*/ \
880	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
881	{ \
882	IEM_MC_BEGIN(4, 1); \
883	IEM_MC_ARG(uint64_t *, pDst, 0); \
884	IEM_MC_ARG(uint64_t, uSrc1, 1); \
885	IEM_MC_ARG(uint64_t, uSrc2, 2); \
886	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
887	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
888	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
889	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
890	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
891	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
892	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
893	IEM_MC_REF_EFLAGS(pEFlags); \
894	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
895	iemAImpl_ ## a_Instr ## _u64_fallback), \
896	pDst, uSrc1, uSrc2, pEFlags); \
897	IEM_MC_ADVANCE_RIP(); \
898	IEM_MC_END(); \
899	} \
900	else \
901	{ \
902	IEM_MC_BEGIN(4, 1); \
903	IEM_MC_ARG(uint32_t *, pDst, 0); \
904	IEM_MC_ARG(uint32_t, uSrc1, 1); \
905	IEM_MC_ARG(uint32_t, uSrc2, 2); \
906	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
907	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
908	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
909	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
910	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
911	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
912	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
913	IEM_MC_REF_EFLAGS(pEFlags); \
914	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
915	iemAImpl_ ## a_Instr ## _u32_fallback), \
916	pDst, uSrc1, uSrc2, pEFlags); \
917	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
918	IEM_MC_ADVANCE_RIP(); \
919	IEM_MC_END(); \
920	} \
921	} \
922	return VINF_SUCCESS
923
924	/** Body for SARX, SHLX, SHRX; assumes VEX.L must be 0. */
925	#define IEMOP_BODY_Gy_Ey_By_NoEflags(a_Instr, a_fFeatureMember, a_fUndefFlags) \
926	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
927	return iemOp_InvalidNeedRM(pVCpu); \
928	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
929	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
930	if (IEM_IS_MODRM_REG_MODE(bRm)) \
931	{ \
932	/* \
933	* Register, register. \
934	*/ \
935	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
936	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
937	{ \
938	IEM_MC_BEGIN(3, 0); \
939	IEM_MC_ARG(uint64_t *, pDst, 0); \
940	IEM_MC_ARG(uint64_t, uSrc1, 1); \
941	IEM_MC_ARG(uint64_t, uSrc2, 2); \
942	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
943	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
944	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
945	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
946	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
947	IEM_MC_ADVANCE_RIP(); \
948	IEM_MC_END(); \
949	} \
950	else \
951	{ \
952	IEM_MC_BEGIN(3, 0); \
953	IEM_MC_ARG(uint32_t *, pDst, 0); \
954	IEM_MC_ARG(uint32_t, uSrc1, 1); \
955	IEM_MC_ARG(uint32_t, uSrc2, 2); \
956	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
957	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
958	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
959	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
960	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
961	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
962	IEM_MC_ADVANCE_RIP(); \
963	IEM_MC_END(); \
964	} \
965	} \
966	else \
967	{ \
968	/* \
969	* Register, memory. \
970	*/ \
971	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
972	{ \
973	IEM_MC_BEGIN(3, 1); \
974	IEM_MC_ARG(uint64_t *, pDst, 0); \
975	IEM_MC_ARG(uint64_t, uSrc1, 1); \
976	IEM_MC_ARG(uint64_t, uSrc2, 2); \
977	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
978	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
979	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
980	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
981	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
982	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
983	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
984	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
985	IEM_MC_ADVANCE_RIP(); \
986	IEM_MC_END(); \
987	} \
988	else \
989	{ \
990	IEM_MC_BEGIN(3, 1); \
991	IEM_MC_ARG(uint32_t *, pDst, 0); \
992	IEM_MC_ARG(uint32_t, uSrc1, 1); \
993	IEM_MC_ARG(uint32_t, uSrc2, 2); \
994	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
995	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
996	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
997	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
998	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
999	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1000	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1001	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1002	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1003	IEM_MC_ADVANCE_RIP(); \
1004	IEM_MC_END(); \
1005	} \
1006	} \
1007	return VINF_SUCCESS
1008
1009	/** Opcode VEX.0F38 0xf5 (vex only). */
1010	FNIEMOP_DEF(iemOp_bzhi_Gy_Ey_By)
1011	{
1012	IEMOP_MNEMONIC3(VEX_RMV, BZHI, bzhi, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1013	IEMOP_BODY_Gy_Ey_By(bzhi, fBmi2, X86_EFL_AF \| X86_EFL_PF);
1014	}
1015
1016	/* Opcode VEX.66.0F38 0xf5 - invalid. */
1017
1018	/** Body for PDEP and PEXT (similar to ANDN, except no EFLAGS). */
1019	#define IEMOP_BODY_Gy_By_Ey_NoEflags(a_Instr, a_fFeatureMember) \
1020	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
1021	return iemOp_InvalidNeedRM(pVCpu); \
1022	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1023	if (IEM_IS_MODRM_REG_MODE(bRm)) \
1024	{ \
1025	/* \
1026	* Register, register. \
1027	*/ \
1028	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1029	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1030	{ \
1031	IEM_MC_BEGIN(3, 0); \
1032	IEM_MC_ARG(uint64_t *, pDst, 0); \
1033	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1034	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1035	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1036	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1037	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1038	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1039	iemAImpl_ ## a_Instr ## _u64, \
1040	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1041	IEM_MC_ADVANCE_RIP(); \
1042	IEM_MC_END(); \
1043	} \
1044	else \
1045	{ \
1046	IEM_MC_BEGIN(3, 0); \
1047	IEM_MC_ARG(uint32_t *, pDst, 0); \
1048	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1049	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1050	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1051	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1052	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1053	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1054	iemAImpl_ ## a_Instr ## _u32, \
1055	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1056	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1057	IEM_MC_ADVANCE_RIP(); \
1058	IEM_MC_END(); \
1059	} \
1060	} \
1061	else \
1062	{ \
1063	/* \
1064	* Register, memory. \
1065	*/ \
1066	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1067	{ \
1068	IEM_MC_BEGIN(3, 1); \
1069	IEM_MC_ARG(uint64_t *, pDst, 0); \
1070	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1071	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1072	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1073	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1074	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1075	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1076	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1077	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1078	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1079	iemAImpl_ ## a_Instr ## _u64, \
1080	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1081	IEM_MC_ADVANCE_RIP(); \
1082	IEM_MC_END(); \
1083	} \
1084	else \
1085	{ \
1086	IEM_MC_BEGIN(3, 1); \
1087	IEM_MC_ARG(uint32_t *, pDst, 0); \
1088	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1089	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1090	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1091	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1092	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1093	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1094	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1095	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1096	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1097	iemAImpl_ ## a_Instr ## _u32, \
1098	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1099	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1100	IEM_MC_ADVANCE_RIP(); \
1101	IEM_MC_END(); \
1102	} \
1103	} \
1104	return VINF_SUCCESS;
1105
1106
1107	/** Opcode VEX.F3.0F38 0xf5 (vex only). */
1108	FNIEMOP_DEF(iemOp_pext_Gy_By_Ey)
1109	{
1110	IEMOP_MNEMONIC3(VEX_RVM, PEXT, pext, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1111	IEMOP_BODY_Gy_By_Ey_NoEflags(pext, fBmi2);
1112	}
1113
1114
1115	/** Opcode VEX.F2.0F38 0xf5 (vex only). */
1116	FNIEMOP_DEF(iemOp_pdep_Gy_By_Ey)
1117	{
1118	IEMOP_MNEMONIC3(VEX_RVM, PDEP, pdep, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1119	IEMOP_BODY_Gy_By_Ey_NoEflags(pdep, fBmi2);
1120	}
1121
1122
1123	/* Opcode VEX.0F38 0xf6 - invalid. */
1124	/* Opcode VEX.66.0F38 0xf6 - invalid (legacy only). */
1125	/* Opcode VEX.F3.0F38 0xf6 - invalid (legacy only). */
1126
1127
1128	/** Opcode VEX.F2.0F38 0xf6 (vex only) */
1129	FNIEMOP_DEF(iemOp_mulx_By_Gy_rDX_Ey)
1130	{
1131	IEMOP_MNEMONIC4(VEX_RVM, MULX, mulx, Gy, By, Ey, rDX, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1132	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi2)
1133	return iemOp_InvalidNeedRM(pVCpu);
1134	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1135	if (IEM_IS_MODRM_REG_MODE(bRm))
1136	{
1137	/*
1138	* Register, register.
1139	*/
1140	IEMOP_HLP_DONE_VEX_DECODING_L0();
1141	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1142	{
1143	IEM_MC_BEGIN(4, 0);
1144	IEM_MC_ARG(uint64_t *, pDst1, 0);
1145	IEM_MC_ARG(uint64_t *, pDst2, 1);
1146	IEM_MC_ARG(uint64_t, uSrc1, 2);
1147	IEM_MC_ARG(uint64_t, uSrc2, 3);
1148	IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1149	IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1150	IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1151	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1152	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1153	pDst1, pDst2, uSrc1, uSrc2);
1154	IEM_MC_ADVANCE_RIP();
1155	IEM_MC_END();
1156	}
1157	else
1158	{
1159	IEM_MC_BEGIN(4, 0);
1160	IEM_MC_ARG(uint32_t *, pDst1, 0);
1161	IEM_MC_ARG(uint32_t *, pDst2, 1);
1162	IEM_MC_ARG(uint32_t, uSrc1, 2);
1163	IEM_MC_ARG(uint32_t, uSrc2, 3);
1164	IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1165	IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1166	IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1167	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1168	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1169	pDst1, pDst2, uSrc1, uSrc2);
1170	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1171	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1172	IEM_MC_ADVANCE_RIP();
1173	IEM_MC_END();
1174	}
1175	}
1176	else
1177	{
1178	/*
1179	* Register, memory.
1180	*/
1181	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1182	{
1183	IEM_MC_BEGIN(4, 1);
1184	IEM_MC_ARG(uint64_t *, pDst1, 0);
1185	IEM_MC_ARG(uint64_t *, pDst2, 1);
1186	IEM_MC_ARG(uint64_t, uSrc1, 2);
1187	IEM_MC_ARG(uint64_t, uSrc2, 3);
1188	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1189	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1190	IEMOP_HLP_DONE_VEX_DECODING_L0();
1191	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1192	IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1193	IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1194	IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1195	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1196	pDst1, pDst2, uSrc1, uSrc2);
1197	IEM_MC_ADVANCE_RIP();
1198	IEM_MC_END();
1199	}
1200	else
1201	{
1202	IEM_MC_BEGIN(4, 1);
1203	IEM_MC_ARG(uint32_t *, pDst1, 0);
1204	IEM_MC_ARG(uint32_t *, pDst2, 1);
1205	IEM_MC_ARG(uint32_t, uSrc1, 2);
1206	IEM_MC_ARG(uint32_t, uSrc2, 3);
1207	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1208	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1209	IEMOP_HLP_DONE_VEX_DECODING_L0();
1210	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1211	IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1212	IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1213	IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1214	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1215	pDst1, pDst2, uSrc1, uSrc2);
1216	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1217	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1218	IEM_MC_ADVANCE_RIP();
1219	IEM_MC_END();
1220	}
1221	}
1222	return VINF_SUCCESS;
1223	}
1224
1225
1226	/** Opcode VEX.0F38 0xf7 (vex only). */
1227	FNIEMOP_DEF(iemOp_bextr_Gy_Ey_By)
1228	{
1229	IEMOP_MNEMONIC3(VEX_RMV, BEXTR, bextr, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1230	IEMOP_BODY_Gy_Ey_By(bextr, fBmi1, X86_EFL_SF \| X86_EFL_AF \| X86_EFL_PF);
1231	}
1232
1233
1234	/** Opcode VEX.66.0F38 0xf7 (vex only). */
1235	FNIEMOP_DEF(iemOp_shlx_Gy_Ey_By)
1236	{
1237	IEMOP_MNEMONIC3(VEX_RMV, SHLX, shlx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1238	IEMOP_BODY_Gy_Ey_By_NoEflags(shlx, fBmi2, 0);
1239	}
1240
1241
1242	/** Opcode VEX.F3.0F38 0xf7 (vex only). */
1243	FNIEMOP_DEF(iemOp_sarx_Gy_Ey_By)
1244	{
1245	IEMOP_MNEMONIC3(VEX_RMV, SARX, sarx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1246	IEMOP_BODY_Gy_Ey_By_NoEflags(sarx, fBmi2, 0);
1247	}
1248
1249
1250	/** Opcode VEX.F2.0F38 0xf7 (vex only). */
1251	FNIEMOP_DEF(iemOp_shrx_Gy_Ey_By)
1252	{
1253	IEMOP_MNEMONIC3(VEX_RMV, SHRX, shrx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1254	IEMOP_BODY_Gy_Ey_By_NoEflags(shrx, fBmi2, 0);
1255	}
1256
1257	/* Opcode VEX.0F38 0xf8 - invalid. */
1258	/* Opcode VEX.66.0F38 0xf8 - invalid. */
1259	/* Opcode VEX.F3.0F38 0xf8 - invalid. */
1260	/* Opcode VEX.F2.0F38 0xf8 - invalid. */
1261
1262	/* Opcode VEX.0F38 0xf9 - invalid. */
1263	/* Opcode VEX.66.0F38 0xf9 - invalid. */
1264	/* Opcode VEX.F3.0F38 0xf9 - invalid. */
1265	/* Opcode VEX.F2.0F38 0xf9 - invalid. */
1266
1267	/* Opcode VEX.0F38 0xfa - invalid. */
1268	/* Opcode VEX.66.0F38 0xfa - invalid. */
1269	/* Opcode VEX.F3.0F38 0xfa - invalid. */
1270	/* Opcode VEX.F2.0F38 0xfa - invalid. */
1271
1272	/* Opcode VEX.0F38 0xfb - invalid. */
1273	/* Opcode VEX.66.0F38 0xfb - invalid. */
1274	/* Opcode VEX.F3.0F38 0xfb - invalid. */
1275	/* Opcode VEX.F2.0F38 0xfb - invalid. */
1276
1277	/* Opcode VEX.0F38 0xfc - invalid. */
1278	/* Opcode VEX.66.0F38 0xfc - invalid. */
1279	/* Opcode VEX.F3.0F38 0xfc - invalid. */
1280	/* Opcode VEX.F2.0F38 0xfc - invalid. */
1281
1282	/* Opcode VEX.0F38 0xfd - invalid. */
1283	/* Opcode VEX.66.0F38 0xfd - invalid. */
1284	/* Opcode VEX.F3.0F38 0xfd - invalid. */
1285	/* Opcode VEX.F2.0F38 0xfd - invalid. */
1286
1287	/* Opcode VEX.0F38 0xfe - invalid. */
1288	/* Opcode VEX.66.0F38 0xfe - invalid. */
1289	/* Opcode VEX.F3.0F38 0xfe - invalid. */
1290	/* Opcode VEX.F2.0F38 0xfe - invalid. */
1291
1292	/* Opcode VEX.0F38 0xff - invalid. */
1293	/* Opcode VEX.66.0F38 0xff - invalid. */
1294	/* Opcode VEX.F3.0F38 0xff - invalid. */
1295	/* Opcode VEX.F2.0F38 0xff - invalid. */
1296
1297
1298	/**
1299	* VEX opcode map \#2.
1300	*
1301	* @sa g_apfnThreeByte0f38
1302	*/
1303	IEM_STATIC const PFNIEMOP g_apfnVexMap2[] =
1304	{
1305	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1306	/* 0x00 */ iemOp_InvalidNeedRM, iemOp_vpshufb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1307	/* 0x01 */ iemOp_InvalidNeedRM, iemOp_vphaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1308	/* 0x02 */ iemOp_InvalidNeedRM, iemOp_vphaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1309	/* 0x03 */ iemOp_InvalidNeedRM, iemOp_vphaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1310	/* 0x04 */ iemOp_InvalidNeedRM, iemOp_vpmaddubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1311	/* 0x05 */ iemOp_InvalidNeedRM, iemOp_vphsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1312	/* 0x06 */ iemOp_InvalidNeedRM, iemOp_vphsubdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1313	/* 0x07 */ iemOp_InvalidNeedRM, iemOp_vphsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1314	/* 0x08 */ iemOp_InvalidNeedRM, iemOp_vpsignb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1315	/* 0x09 */ iemOp_InvalidNeedRM, iemOp_vpsignw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1316	/* 0x0a */ iemOp_InvalidNeedRM, iemOp_vpsignd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1317	/* 0x0b */ iemOp_InvalidNeedRM, iemOp_vpmulhrsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1318	/* 0x0c */ iemOp_InvalidNeedRM, iemOp_vpermilps_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1319	/* 0x0d */ iemOp_InvalidNeedRM, iemOp_vpermilpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1320	/* 0x0e */ iemOp_InvalidNeedRM, iemOp_vtestps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1321	/* 0x0f */ iemOp_InvalidNeedRM, iemOp_vtestpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1322
1323	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRM),
1324	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
1325	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
1326	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
1327	/* 0x14 */ IEMOP_X4(iemOp_InvalidNeedRM),
1328	/* 0x15 */ IEMOP_X4(iemOp_InvalidNeedRM),
1329	/* 0x16 */ iemOp_InvalidNeedRM, iemOp_vpermps_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1330	/* 0x17 */ iemOp_InvalidNeedRM, iemOp_vptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1331	/* 0x18 */ iemOp_InvalidNeedRM, iemOp_vbroadcastss_Vx_Wd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1332	/* 0x19 */ iemOp_InvalidNeedRM, iemOp_vbroadcastsd_Vqq_Wq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1333	/* 0x1a */ iemOp_InvalidNeedRM, iemOp_vbroadcastf128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1334	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
1335	/* 0x1c */ iemOp_InvalidNeedRM, iemOp_vpabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1336	/* 0x1d */ iemOp_InvalidNeedRM, iemOp_vpabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1337	/* 0x1e */ iemOp_InvalidNeedRM, iemOp_vpabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1338	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
1339
1340	/* 0x20 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1341	/* 0x21 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1342	/* 0x22 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1343	/* 0x23 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1344	/* 0x24 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1345	/* 0x25 */ iemOp_InvalidNeedRM, iemOp_vpmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1346	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
1347	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
1348	/* 0x28 */ iemOp_InvalidNeedRM, iemOp_vpmuldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1349	/* 0x29 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1350	/* 0x2a */ iemOp_InvalidNeedRM, iemOp_vmovntdqa_Vx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1351	/* 0x2b */ iemOp_InvalidNeedRM, iemOp_vpackusdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1352	/* 0x2c */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1353	/* 0x2d */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1354	/* 0x2e */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1355	/* 0x2f */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1356
1357	/* 0x30 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1358	/* 0x31 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1359	/* 0x32 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1360	/* 0x33 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1361	/* 0x34 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1362	/* 0x35 */ iemOp_InvalidNeedRM, iemOp_vpmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1363	/* 0x36 */ iemOp_InvalidNeedRM, iemOp_vpermd_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1364	/* 0x37 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1365	/* 0x38 */ iemOp_InvalidNeedRM, iemOp_vpminsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1366	/* 0x39 */ iemOp_InvalidNeedRM, iemOp_vpminsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1367	/* 0x3a */ iemOp_InvalidNeedRM, iemOp_vpminuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1368	/* 0x3b */ iemOp_InvalidNeedRM, iemOp_vpminud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1369	/* 0x3c */ iemOp_InvalidNeedRM, iemOp_vpmaxsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1370	/* 0x3d */ iemOp_InvalidNeedRM, iemOp_vpmaxsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1371	/* 0x3e */ iemOp_InvalidNeedRM, iemOp_vpmaxuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1372	/* 0x3f */ iemOp_InvalidNeedRM, iemOp_vpmaxud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1373
1374	/* 0x40 */ iemOp_InvalidNeedRM, iemOp_vpmulld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1375	/* 0x41 */ iemOp_InvalidNeedRM, iemOp_vphminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1376	/* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
1377	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
1378	/* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
1379	/* 0x45 */ iemOp_InvalidNeedRM, iemOp_vpsrlvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1380	/* 0x46 */ iemOp_InvalidNeedRM, iemOp_vsravd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1381	/* 0x47 */ iemOp_InvalidNeedRM, iemOp_vpsllvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1382	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
1383	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
1384	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
1385	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
1386	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
1387	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
1388	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
1389	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
1390
1391	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
1392	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
1393	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
1394	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
1395	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
1396	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
1397	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
1398	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
1399	/* 0x58 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1400	/* 0x59 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1401	/* 0x5a */ iemOp_InvalidNeedRM, iemOp_vbroadcasti128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1402	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
1403	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
1404	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
1405	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
1406	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
1407
1408	/* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
1409	/* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
1410	/* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
1411	/* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
1412	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
1413	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
1414	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
1415	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
1416	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
1417	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
1418	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
1419	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
1420	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
1421	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
1422	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
1423	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
1424
1425	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
1426	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
1427	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
1428	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
1429	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
1430	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
1431	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
1432	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
1433	/* 0x78 */ iemOp_InvalidNeedRM, iemOp_vpboardcastb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1434	/* 0x79 */ iemOp_InvalidNeedRM, iemOp_vpboardcastw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1435	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
1436	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
1437	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
1438	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
1439	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
1440	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
1441
1442	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
1443	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
1444	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
1445	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
1446	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
1447	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
1448	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
1449	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
1450	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
1451	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
1452	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
1453	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
1454	/* 0x8c */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1455	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
1456	/* 0x8e */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Mx_Vx_Hx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1457	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
1458
1459	/* 0x90 */ iemOp_InvalidNeedRM, iemOp_vgatherdd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1460	/* 0x91 */ iemOp_InvalidNeedRM, iemOp_vgatherqd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1461	/* 0x92 */ iemOp_InvalidNeedRM, iemOp_vgatherdps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1462	/* 0x93 */ iemOp_InvalidNeedRM, iemOp_vgatherqps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1463	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
1464	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
1465	/* 0x96 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub132ps_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1466	/* 0x97 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1467	/* 0x98 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1468	/* 0x99 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1469	/* 0x9a */ iemOp_InvalidNeedRM, iemOp_vfmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1470	/* 0x9b */ iemOp_InvalidNeedRM, iemOp_vfmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1471	/* 0x9c */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1472	/* 0x9d */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1473	/* 0x9e */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1474	/* 0x9f */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1475
1476	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1477	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1478	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1479	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1480	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1481	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1482	/* 0xa6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1483	/* 0xa7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1484	/* 0xa8 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1485	/* 0xa9 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1486	/* 0xaa */ iemOp_InvalidNeedRM, iemOp_vfmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1487	/* 0xab */ iemOp_InvalidNeedRM, iemOp_vfmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1488	/* 0xac */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1489	/* 0xad */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1490	/* 0xae */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1491	/* 0xaf */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1492
1493	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1494	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1495	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1496	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1497	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1498	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1499	/* 0xb6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1500	/* 0xb7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1501	/* 0xb8 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1502	/* 0xb9 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1503	/* 0xba */ iemOp_InvalidNeedRM, iemOp_vfmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1504	/* 0xbb */ iemOp_InvalidNeedRM, iemOp_vfmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1505	/* 0xbc */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1506	/* 0xbd */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1507	/* 0xbe */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1508	/* 0xbf */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1509
1510	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1511	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1512	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1513	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1514	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1515	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1516	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1517	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1518	/* 0xc8 */ iemOp_vsha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1519	/* 0xc9 */ iemOp_vsha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1520	/* 0xca */ iemOp_vsha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1521	/* 0xcb */ iemOp_vsha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1522	/* 0xcc */ iemOp_vsha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1523	/* 0xcd */ iemOp_vsha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1524	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
1525	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
1526
1527	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1528	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1529	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1530	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1531	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1532	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1533	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1534	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1535	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1536	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1537	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
1538	/* 0xdb */ iemOp_InvalidNeedRM, iemOp_vaesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1539	/* 0xdc */ iemOp_InvalidNeedRM, iemOp_vaesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1540	/* 0xdd */ iemOp_InvalidNeedRM, iemOp_vaesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1541	/* 0xde */ iemOp_InvalidNeedRM, iemOp_vaesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1542	/* 0xdf */ iemOp_InvalidNeedRM, iemOp_vaesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1543
1544	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1545	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1546	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1547	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1548	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1549	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1550	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1551	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1552	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1553	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1554	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
1555	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
1556	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
1557	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
1558	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
1559	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
1560
1561	/* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1562	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1563	/* 0xf2 */ iemOp_andn_Gy_By_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1564	/* 0xf3 */ iemOp_VGrp17_f3, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1565	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1566	/* 0xf5 */ iemOp_bzhi_Gy_Ey_By, iemOp_InvalidNeedRM, iemOp_pext_Gy_By_Ey, iemOp_pdep_Gy_By_Ey,
1567	/* 0xf6 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_mulx_By_Gy_rDX_Ey,
1568	/* 0xf7 */ iemOp_bextr_Gy_Ey_By, iemOp_shlx_Gy_Ey_By, iemOp_sarx_Gy_Ey_By, iemOp_shrx_Gy_Ey_By,
1569	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1570	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1571	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
1572	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
1573	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
1574	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
1575	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
1576	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
1577	};
1578	AssertCompile(RT_ELEMENTS(g_apfnVexMap2) == 1024);
1579
1580	/** @} */
1581

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h@ 95524

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