IEMAllInstructionsVexMap2.cpp.h@ 95578

Last change on this file since 95578 was 95578, checked in by vboxsync, 2 years ago
VMM/IEM: [v]ptest. bugref:9898
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1	/* $Id: IEMAllInstructionsVexMap2.cpp.h 95578 2022-07-09 00:09:50Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation.
4	*
5	* @remarks IEMAllInstructionsThree0f38.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/** @name VEX Opcode Map 2
23	* @{
24	*/
25
26	/* Opcode VEX.0F38 0x00 - invalid. */
27
28
29	/** Opcode VEX.66.0F38 0x00. */
30	FNIEMOP_DEF(iemOp_vpshufb_Vx_Hx_Wx)
31	{
32	IEMOP_MNEMONIC3(VEX_RVM, VPSHUFB, vpshufb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
33	IEMOPMEDIAF3_INIT_VARS(vpshufb);
34	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
35	}
36
37
38	/* Opcode VEX.0F38 0x01 - invalid. */
39	/** Opcode VEX.66.0F38 0x01. */
40	FNIEMOP_STUB(iemOp_vphaddw_Vx_Hx_Wx);
41	/* Opcode VEX.0F38 0x02 - invalid. */
42	/** Opcode VEX.66.0F38 0x02. */
43	FNIEMOP_STUB(iemOp_vphaddd_Vx_Hx_Wx);
44	/* Opcode VEX.0F38 0x03 - invalid. */
45	/** Opcode VEX.66.0F38 0x03. */
46	FNIEMOP_STUB(iemOp_vphaddsw_Vx_Hx_Wx);
47	/* Opcode VEX.0F38 0x04 - invalid. */
48	/** Opcode VEX.66.0F38 0x04. */
49	FNIEMOP_STUB(iemOp_vpmaddubsw_Vx_Hx_Wx);
50	/* Opcode VEX.0F38 0x05 - invalid. */
51	/** Opcode VEX.66.0F38 0x05. */
52	FNIEMOP_STUB(iemOp_vphsubw_Vx_Hx_Wx);
53	/* Opcode VEX.0F38 0x06 - invalid. */
54	/** Opcode VEX.66.0F38 0x06. */
55	FNIEMOP_STUB(iemOp_vphsubdq_Vx_Hx_Wx);
56	/* Opcode VEX.0F38 0x07 - invalid. */
57	/** Opcode VEX.66.0F38 0x07. */
58	FNIEMOP_STUB(iemOp_vphsubsw_Vx_Hx_Wx);
59	/* Opcode VEX.0F38 0x08 - invalid. */
60	/** Opcode VEX.66.0F38 0x08. */
61	FNIEMOP_STUB(iemOp_vpsignb_Vx_Hx_Wx);
62	/* Opcode VEX.0F38 0x09 - invalid. */
63	/** Opcode VEX.66.0F38 0x09. */
64	FNIEMOP_STUB(iemOp_vpsignw_Vx_Hx_Wx);
65	/* Opcode VEX.0F38 0x0a - invalid. */
66	/** Opcode VEX.66.0F38 0x0a. */
67	FNIEMOP_STUB(iemOp_vpsignd_Vx_Hx_Wx);
68	/* Opcode VEX.0F38 0x0b - invalid. */
69	/** Opcode VEX.66.0F38 0x0b. */
70	FNIEMOP_STUB(iemOp_vpmulhrsw_Vx_Hx_Wx);
71	/* Opcode VEX.0F38 0x0c - invalid. */
72	/** Opcode VEX.66.0F38 0x0c. */
73	FNIEMOP_STUB(iemOp_vpermilps_Vx_Hx_Wx);
74	/* Opcode VEX.0F38 0x0d - invalid. */
75	/** Opcode VEX.66.0F38 0x0d. */
76	FNIEMOP_STUB(iemOp_vpermilpd_Vx_Hx_Wx);
77	/* Opcode VEX.0F38 0x0e - invalid. */
78	/** Opcode VEX.66.0F38 0x0e. */
79	FNIEMOP_STUB(iemOp_vtestps_Vx_Wx);
80	/* Opcode VEX.0F38 0x0f - invalid. */
81	/** Opcode VEX.66.0F38 0x0f. */
82	FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx);
83
84
85	/* Opcode VEX.0F38 0x10 - invalid */
86	/* Opcode VEX.66.0F38 0x10 - invalid (legacy only). */
87	/* Opcode VEX.0F38 0x11 - invalid */
88	/* Opcode VEX.66.0F38 0x11 - invalid */
89	/* Opcode VEX.0F38 0x12 - invalid */
90	/* Opcode VEX.66.0F38 0x12 - invalid */
91	/* Opcode VEX.0F38 0x13 - invalid */
92	/* Opcode VEX.66.0F38 0x13 - invalid (vex only). */
93	/* Opcode VEX.0F38 0x14 - invalid */
94	/* Opcode VEX.66.0F38 0x14 - invalid (legacy only). */
95	/* Opcode VEX.0F38 0x15 - invalid */
96	/* Opcode VEX.66.0F38 0x15 - invalid (legacy only). */
97	/* Opcode VEX.0F38 0x16 - invalid */
98	/** Opcode VEX.66.0F38 0x16. */
99	FNIEMOP_STUB(iemOp_vpermps_Vqq_Hqq_Wqq);
100	/* Opcode VEX.0F38 0x17 - invalid */
101
102
103	/** Opcode VEX.66.0F38 0x17 - invalid */
104	FNIEMOP_DEF(iemOp_vptest_Vx_Wx)
105	{
106	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
107	if (IEM_IS_MODRM_REG_MODE(bRm))
108	{
109	/*
110	* Register, register.
111	*/
112	if (pVCpu->iem.s.uVexLength)
113	{
114	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
115	IEM_MC_BEGIN(3, 2);
116	IEM_MC_LOCAL(RTUINT256U, uSrc1);
117	IEM_MC_LOCAL(RTUINT256U, uSrc2);
118	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
119	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
120	IEM_MC_ARG(uint32_t *, pEFlags, 2);
121	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
122	IEM_MC_PREPARE_AVX_USAGE();
123	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
124	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
125	IEM_MC_REF_EFLAGS(pEFlags);
126	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
127	puSrc1, puSrc2, pEFlags);
128	IEM_MC_ADVANCE_RIP();
129	IEM_MC_END();
130	}
131	else
132	{
133	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
134	IEM_MC_BEGIN(3, 0);
135	IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
136	IEM_MC_ARG(PCRTUINT128U, puSrc2, 1);
137	IEM_MC_ARG(uint32_t *, pEFlags, 2);
138	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
139	IEM_MC_PREPARE_AVX_USAGE();
140	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
141	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
142	IEM_MC_REF_EFLAGS(pEFlags);
143	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
144	IEM_MC_ADVANCE_RIP();
145	IEM_MC_END();
146	}
147	}
148	else
149	{
150	/*
151	* Register, memory.
152	*/
153	if (pVCpu->iem.s.uVexLength)
154	{
155	IEM_MC_BEGIN(3, 3);
156	IEM_MC_LOCAL(RTUINT256U, uSrc1);
157	IEM_MC_LOCAL(RTUINT256U, uSrc2);
158	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
159	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
160	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
161	IEM_MC_ARG(uint32_t *, pEFlags, 2);
162
163	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
164	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
165	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
166	IEM_MC_PREPARE_AVX_USAGE();
167
168	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
169	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
170	IEM_MC_REF_EFLAGS(pEFlags);
171	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
172	puSrc1, puSrc2, pEFlags);
173
174	IEM_MC_ADVANCE_RIP();
175	IEM_MC_END();
176	}
177	else
178	{
179	IEM_MC_BEGIN(3, 2);
180	IEM_MC_LOCAL(RTUINT128U, uSrc2);
181	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
182	IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
183	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1);
184	IEM_MC_ARG(uint32_t *, pEFlags, 2);
185
186	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
187	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
188	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
189	IEM_MC_PREPARE_AVX_USAGE();
190
191	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
192	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
193	IEM_MC_REF_EFLAGS(pEFlags);
194	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
195
196	IEM_MC_ADVANCE_RIP();
197	IEM_MC_END();
198	}
199	}
200	return VINF_SUCCESS;
201
202	}
203
204
205	/* Opcode VEX.0F38 0x18 - invalid */
206	/** Opcode VEX.66.0F38 0x18. */
207	FNIEMOP_STUB(iemOp_vbroadcastss_Vx_Wd);
208	/* Opcode VEX.0F38 0x19 - invalid */
209	/** Opcode VEX.66.0F38 0x19. */
210	FNIEMOP_STUB(iemOp_vbroadcastsd_Vqq_Wq);
211	/* Opcode VEX.0F38 0x1a - invalid */
212	/** Opcode VEX.66.0F38 0x1a. */
213	FNIEMOP_STUB(iemOp_vbroadcastf128_Vqq_Mdq);
214	/* Opcode VEX.0F38 0x1b - invalid */
215	/* Opcode VEX.66.0F38 0x1b - invalid */
216	/* Opcode VEX.0F38 0x1c - invalid. */
217	/** Opcode VEX.66.0F38 0x1c. */
218	FNIEMOP_STUB(iemOp_vpabsb_Vx_Wx);
219	/* Opcode VEX.0F38 0x1d - invalid. */
220	/** Opcode VEX.66.0F38 0x1d. */
221	FNIEMOP_STUB(iemOp_vpabsw_Vx_Wx);
222	/* Opcode VEX.0F38 0x1e - invalid. */
223	/** Opcode VEX.66.0F38 0x1e. */
224	FNIEMOP_STUB(iemOp_vpabsd_Vx_Wx);
225	/* Opcode VEX.0F38 0x1f - invalid */
226	/* Opcode VEX.66.0F38 0x1f - invalid */
227
228
229	/** Opcode VEX.66.0F38 0x20. */
230	FNIEMOP_STUB(iemOp_vpmovsxbw_Vx_UxMq);
231	/** Opcode VEX.66.0F38 0x21. */
232	FNIEMOP_STUB(iemOp_vpmovsxbd_Vx_UxMd);
233	/** Opcode VEX.66.0F38 0x22. */
234	FNIEMOP_STUB(iemOp_vpmovsxbq_Vx_UxMw);
235	/** Opcode VEX.66.0F38 0x23. */
236	FNIEMOP_STUB(iemOp_vpmovsxwd_Vx_UxMq);
237	/** Opcode VEX.66.0F38 0x24. */
238	FNIEMOP_STUB(iemOp_vpmovsxwq_Vx_UxMd);
239	/** Opcode VEX.66.0F38 0x25. */
240	FNIEMOP_STUB(iemOp_vpmovsxdq_Vx_UxMq);
241	/* Opcode VEX.66.0F38 0x26 - invalid */
242	/* Opcode VEX.66.0F38 0x27 - invalid */
243	/** Opcode VEX.66.0F38 0x28. */
244	FNIEMOP_STUB(iemOp_vpmuldq_Vx_Hx_Wx);
245
246
247	/** Opcode VEX.66.0F38 0x29. */
248	FNIEMOP_DEF(iemOp_vpcmpeqq_Vx_Hx_Wx)
249	{
250	IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQQ, vpcmpeqq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
251	IEMOPMEDIAF3_INIT_VARS(vpcmpeqq);
252	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
253	}
254
255
256	FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
257	{
258	Assert(pVCpu->iem.s.uVexLength <= 1);
259	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
260	if (IEM_IS_MODRM_MEM_MODE(bRm))
261	{
262	if (pVCpu->iem.s.uVexLength == 0)
263	{
264	/**
265	* @opcode 0x2a
266	* @opcodesub !11 mr/reg vex.l=0
267	* @oppfx 0x66
268	* @opcpuid avx
269	* @opgroup og_avx_cachect
270	* @opxcpttype 1
271	* @optest op1=-1 op2=2 -> op1=2
272	* @optest op1=0 op2=-42 -> op1=-42
273	*/
274	/* 128-bit: Memory, register. */
275	IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
276	DISOPTYPE_HARMLESS \| DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
277	IEM_MC_BEGIN(0, 2);
278	IEM_MC_LOCAL(RTUINT128U, uSrc);
279	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
280
281	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
282	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
283	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
284	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
285
286	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
287	IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
288
289	IEM_MC_ADVANCE_RIP();
290	IEM_MC_END();
291	}
292	else
293	{
294	/**
295	* @opdone
296	* @opcode 0x2a
297	* @opcodesub !11 mr/reg vex.l=1
298	* @oppfx 0x66
299	* @opcpuid avx2
300	* @opgroup og_avx2_cachect
301	* @opxcpttype 1
302	* @optest op1=-1 op2=2 -> op1=2
303	* @optest op1=0 op2=-42 -> op1=-42
304	*/
305	/* 256-bit: Memory, register. */
306	IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
307	DISOPTYPE_HARMLESS \| DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
308	IEM_MC_BEGIN(0, 2);
309	IEM_MC_LOCAL(RTUINT256U, uSrc);
310	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
311
312	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
313	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
314	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
315	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
316
317	IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
318	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
319
320	IEM_MC_ADVANCE_RIP();
321	IEM_MC_END();
322	}
323	return VINF_SUCCESS;
324	}
325
326	/**
327	* @opdone
328	* @opmnemonic udvex660f382arg
329	* @opcode 0x2a
330	* @opcodesub 11 mr/reg
331	* @oppfx 0x66
332	* @opunused immediate
333	* @opcpuid avx
334	* @optest ->
335	*/
336	return IEMOP_RAISE_INVALID_OPCODE();
337	}
338
339
340	/** Opcode VEX.66.0F38 0x2b. */
341	FNIEMOP_DEF(iemOp_vpackusdw_Vx_Hx_Wx)
342	{
343	IEMOP_MNEMONIC3(VEX_RVM, VPACKUSDW, vpackusdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_AVX, 0);
344	IEMOPMEDIAOPTF3_INIT_VARS( vpackusdw);
345	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
346	}
347
348
349	/** Opcode VEX.66.0F38 0x2c. */
350	FNIEMOP_STUB(iemOp_vmaskmovps_Vx_Hx_Mx);
351	/** Opcode VEX.66.0F38 0x2d. */
352	FNIEMOP_STUB(iemOp_vmaskmovpd_Vx_Hx_Mx);
353	/** Opcode VEX.66.0F38 0x2e. */
354	FNIEMOP_STUB(iemOp_vmaskmovps_Mx_Hx_Vx);
355	/** Opcode VEX.66.0F38 0x2f. */
356	FNIEMOP_STUB(iemOp_vmaskmovpd_Mx_Hx_Vx);
357
358	/** Opcode VEX.66.0F38 0x30. */
359	FNIEMOP_STUB(iemOp_vpmovzxbw_Vx_UxMq);
360	/** Opcode VEX.66.0F38 0x31. */
361	FNIEMOP_STUB(iemOp_vpmovzxbd_Vx_UxMd);
362	/** Opcode VEX.66.0F38 0x32. */
363	FNIEMOP_STUB(iemOp_vpmovzxbq_Vx_UxMw);
364	/** Opcode VEX.66.0F38 0x33. */
365	FNIEMOP_STUB(iemOp_vpmovzxwd_Vx_UxMq);
366	/** Opcode VEX.66.0F38 0x34. */
367	FNIEMOP_STUB(iemOp_vpmovzxwq_Vx_UxMd);
368	/** Opcode VEX.66.0F38 0x35. */
369	FNIEMOP_STUB(iemOp_vpmovzxdq_Vx_UxMq);
370	/* Opcode VEX.66.0F38 0x36. */
371	FNIEMOP_STUB(iemOp_vpermd_Vqq_Hqq_Wqq);
372
373
374	/** Opcode VEX.66.0F38 0x37. */
375	FNIEMOP_DEF(iemOp_vpcmpgtq_Vx_Hx_Wx)
376	{
377	IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTQ, vpcmpgtq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
378	IEMOPMEDIAF3_INIT_VARS(vpcmpgtq);
379	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
380	}
381
382
383	/** Opcode VEX.66.0F38 0x38. */
384	FNIEMOP_STUB(iemOp_vpminsb_Vx_Hx_Wx);
385	/** Opcode VEX.66.0F38 0x39. */
386	FNIEMOP_STUB(iemOp_vpminsd_Vx_Hx_Wx);
387	/** Opcode VEX.66.0F38 0x3a. */
388	FNIEMOP_STUB(iemOp_vpminuw_Vx_Hx_Wx);
389	/** Opcode VEX.66.0F38 0x3b. */
390	FNIEMOP_STUB(iemOp_vpminud_Vx_Hx_Wx);
391	/** Opcode VEX.66.0F38 0x3c. */
392	FNIEMOP_STUB(iemOp_vpmaxsb_Vx_Hx_Wx);
393	/** Opcode VEX.66.0F38 0x3d. */
394	FNIEMOP_STUB(iemOp_vpmaxsd_Vx_Hx_Wx);
395	/** Opcode VEX.66.0F38 0x3e. */
396	FNIEMOP_STUB(iemOp_vpmaxuw_Vx_Hx_Wx);
397	/** Opcode VEX.66.0F38 0x3f. */
398	FNIEMOP_STUB(iemOp_vpmaxud_Vx_Hx_Wx);
399
400
401	/** Opcode VEX.66.0F38 0x40. */
402	FNIEMOP_STUB(iemOp_vpmulld_Vx_Hx_Wx);
403	/** Opcode VEX.66.0F38 0x41. */
404	FNIEMOP_STUB(iemOp_vphminposuw_Vdq_Wdq);
405	/* Opcode VEX.66.0F38 0x42 - invalid. */
406	/* Opcode VEX.66.0F38 0x43 - invalid. */
407	/* Opcode VEX.66.0F38 0x44 - invalid. */
408	/** Opcode VEX.66.0F38 0x45. */
409	FNIEMOP_STUB(iemOp_vpsrlvd_q_Vx_Hx_Wx);
410	/** Opcode VEX.66.0F38 0x46. */
411	FNIEMOP_STUB(iemOp_vsravd_Vx_Hx_Wx);
412	/** Opcode VEX.66.0F38 0x47. */
413	FNIEMOP_STUB(iemOp_vpsllvd_q_Vx_Hx_Wx);
414	/* Opcode VEX.66.0F38 0x48 - invalid. */
415	/* Opcode VEX.66.0F38 0x49 - invalid. */
416	/* Opcode VEX.66.0F38 0x4a - invalid. */
417	/* Opcode VEX.66.0F38 0x4b - invalid. */
418	/* Opcode VEX.66.0F38 0x4c - invalid. */
419	/* Opcode VEX.66.0F38 0x4d - invalid. */
420	/* Opcode VEX.66.0F38 0x4e - invalid. */
421	/* Opcode VEX.66.0F38 0x4f - invalid. */
422
423	/* Opcode VEX.66.0F38 0x50 - invalid. */
424	/* Opcode VEX.66.0F38 0x51 - invalid. */
425	/* Opcode VEX.66.0F38 0x52 - invalid. */
426	/* Opcode VEX.66.0F38 0x53 - invalid. */
427	/* Opcode VEX.66.0F38 0x54 - invalid. */
428	/* Opcode VEX.66.0F38 0x55 - invalid. */
429	/* Opcode VEX.66.0F38 0x56 - invalid. */
430	/* Opcode VEX.66.0F38 0x57 - invalid. */
431	/** Opcode VEX.66.0F38 0x58. */
432	FNIEMOP_STUB(iemOp_vpbroadcastd_Vx_Wx);
433	/** Opcode VEX.66.0F38 0x59. */
434	FNIEMOP_STUB(iemOp_vpbroadcastq_Vx_Wx);
435	/** Opcode VEX.66.0F38 0x5a. */
436	FNIEMOP_STUB(iemOp_vbroadcasti128_Vqq_Mdq);
437	/* Opcode VEX.66.0F38 0x5b - invalid. */
438	/* Opcode VEX.66.0F38 0x5c - invalid. */
439	/* Opcode VEX.66.0F38 0x5d - invalid. */
440	/* Opcode VEX.66.0F38 0x5e - invalid. */
441	/* Opcode VEX.66.0F38 0x5f - invalid. */
442
443	/* Opcode VEX.66.0F38 0x60 - invalid. */
444	/* Opcode VEX.66.0F38 0x61 - invalid. */
445	/* Opcode VEX.66.0F38 0x62 - invalid. */
446	/* Opcode VEX.66.0F38 0x63 - invalid. */
447	/* Opcode VEX.66.0F38 0x64 - invalid. */
448	/* Opcode VEX.66.0F38 0x65 - invalid. */
449	/* Opcode VEX.66.0F38 0x66 - invalid. */
450	/* Opcode VEX.66.0F38 0x67 - invalid. */
451	/* Opcode VEX.66.0F38 0x68 - invalid. */
452	/* Opcode VEX.66.0F38 0x69 - invalid. */
453	/* Opcode VEX.66.0F38 0x6a - invalid. */
454	/* Opcode VEX.66.0F38 0x6b - invalid. */
455	/* Opcode VEX.66.0F38 0x6c - invalid. */
456	/* Opcode VEX.66.0F38 0x6d - invalid. */
457	/* Opcode VEX.66.0F38 0x6e - invalid. */
458	/* Opcode VEX.66.0F38 0x6f - invalid. */
459
460	/* Opcode VEX.66.0F38 0x70 - invalid. */
461	/* Opcode VEX.66.0F38 0x71 - invalid. */
462	/* Opcode VEX.66.0F38 0x72 - invalid. */
463	/* Opcode VEX.66.0F38 0x73 - invalid. */
464	/* Opcode VEX.66.0F38 0x74 - invalid. */
465	/* Opcode VEX.66.0F38 0x75 - invalid. */
466	/* Opcode VEX.66.0F38 0x76 - invalid. */
467	/* Opcode VEX.66.0F38 0x77 - invalid. */
468	/** Opcode VEX.66.0F38 0x78. */
469	FNIEMOP_STUB(iemOp_vpboardcastb_Vx_Wx);
470	/** Opcode VEX.66.0F38 0x79. */
471	FNIEMOP_STUB(iemOp_vpboardcastw_Vx_Wx);
472	/* Opcode VEX.66.0F38 0x7a - invalid. */
473	/* Opcode VEX.66.0F38 0x7b - invalid. */
474	/* Opcode VEX.66.0F38 0x7c - invalid. */
475	/* Opcode VEX.66.0F38 0x7d - invalid. */
476	/* Opcode VEX.66.0F38 0x7e - invalid. */
477	/* Opcode VEX.66.0F38 0x7f - invalid. */
478
479	/* Opcode VEX.66.0F38 0x80 - invalid (legacy only). */
480	/* Opcode VEX.66.0F38 0x81 - invalid (legacy only). */
481	/* Opcode VEX.66.0F38 0x82 - invalid (legacy only). */
482	/* Opcode VEX.66.0F38 0x83 - invalid. */
483	/* Opcode VEX.66.0F38 0x84 - invalid. */
484	/* Opcode VEX.66.0F38 0x85 - invalid. */
485	/* Opcode VEX.66.0F38 0x86 - invalid. */
486	/* Opcode VEX.66.0F38 0x87 - invalid. */
487	/* Opcode VEX.66.0F38 0x88 - invalid. */
488	/* Opcode VEX.66.0F38 0x89 - invalid. */
489	/* Opcode VEX.66.0F38 0x8a - invalid. */
490	/* Opcode VEX.66.0F38 0x8b - invalid. */
491	/** Opcode VEX.66.0F38 0x8c. */
492	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Vx_Hx_Mx);
493	/* Opcode VEX.66.0F38 0x8d - invalid. */
494	/** Opcode VEX.66.0F38 0x8e. */
495	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Mx_Vx_Hx);
496	/* Opcode VEX.66.0F38 0x8f - invalid. */
497
498	/** Opcode VEX.66.0F38 0x90 (vex only). */
499	FNIEMOP_STUB(iemOp_vgatherdd_q_Vx_Hx_Wx);
500	/** Opcode VEX.66.0F38 0x91 (vex only). */
501	FNIEMOP_STUB(iemOp_vgatherqd_q_Vx_Hx_Wx);
502	/** Opcode VEX.66.0F38 0x92 (vex only). */
503	FNIEMOP_STUB(iemOp_vgatherdps_d_Vx_Hx_Wx);
504	/** Opcode VEX.66.0F38 0x93 (vex only). */
505	FNIEMOP_STUB(iemOp_vgatherqps_d_Vx_Hx_Wx);
506	/* Opcode VEX.66.0F38 0x94 - invalid. */
507	/* Opcode VEX.66.0F38 0x95 - invalid. */
508	/** Opcode VEX.66.0F38 0x96 (vex only). */
509	FNIEMOP_STUB(iemOp_vfmaddsub132ps_q_Vx_Hx_Wx);
510	/** Opcode VEX.66.0F38 0x97 (vex only). */
511	FNIEMOP_STUB(iemOp_vfmsubadd132ps_d_Vx_Hx_Wx);
512	/** Opcode VEX.66.0F38 0x98 (vex only). */
513	FNIEMOP_STUB(iemOp_vfmadd132ps_d_Vx_Hx_Wx);
514	/** Opcode VEX.66.0F38 0x99 (vex only). */
515	FNIEMOP_STUB(iemOp_vfmadd132ss_d_Vx_Hx_Wx);
516	/** Opcode VEX.66.0F38 0x9a (vex only). */
517	FNIEMOP_STUB(iemOp_vfmsub132ps_d_Vx_Hx_Wx);
518	/** Opcode VEX.66.0F38 0x9b (vex only). */
519	FNIEMOP_STUB(iemOp_vfmsub132ss_d_Vx_Hx_Wx);
520	/** Opcode VEX.66.0F38 0x9c (vex only). */
521	FNIEMOP_STUB(iemOp_vfnmadd132ps_d_Vx_Hx_Wx);
522	/** Opcode VEX.66.0F38 0x9d (vex only). */
523	FNIEMOP_STUB(iemOp_vfnmadd132ss_d_Vx_Hx_Wx);
524	/** Opcode VEX.66.0F38 0x9e (vex only). */
525	FNIEMOP_STUB(iemOp_vfnmsub132ps_d_Vx_Hx_Wx);
526	/** Opcode VEX.66.0F38 0x9f (vex only). */
527	FNIEMOP_STUB(iemOp_vfnmsub132ss_d_Vx_Hx_Wx);
528
529	/* Opcode VEX.66.0F38 0xa0 - invalid. */
530	/* Opcode VEX.66.0F38 0xa1 - invalid. */
531	/* Opcode VEX.66.0F38 0xa2 - invalid. */
532	/* Opcode VEX.66.0F38 0xa3 - invalid. */
533	/* Opcode VEX.66.0F38 0xa4 - invalid. */
534	/* Opcode VEX.66.0F38 0xa5 - invalid. */
535	/** Opcode VEX.66.0F38 0xa6 (vex only). */
536	FNIEMOP_STUB(iemOp_vfmaddsub213ps_d_Vx_Hx_Wx);
537	/** Opcode VEX.66.0F38 0xa7 (vex only). */
538	FNIEMOP_STUB(iemOp_vfmsubadd213ps_d_Vx_Hx_Wx);
539	/** Opcode VEX.66.0F38 0xa8 (vex only). */
540	FNIEMOP_STUB(iemOp_vfmadd213ps_d_Vx_Hx_Wx);
541	/** Opcode VEX.66.0F38 0xa9 (vex only). */
542	FNIEMOP_STUB(iemOp_vfmadd213ss_d_Vx_Hx_Wx);
543	/** Opcode VEX.66.0F38 0xaa (vex only). */
544	FNIEMOP_STUB(iemOp_vfmsub213ps_d_Vx_Hx_Wx);
545	/** Opcode VEX.66.0F38 0xab (vex only). */
546	FNIEMOP_STUB(iemOp_vfmsub213ss_d_Vx_Hx_Wx);
547	/** Opcode VEX.66.0F38 0xac (vex only). */
548	FNIEMOP_STUB(iemOp_vfnmadd213ps_d_Vx_Hx_Wx);
549	/** Opcode VEX.66.0F38 0xad (vex only). */
550	FNIEMOP_STUB(iemOp_vfnmadd213ss_d_Vx_Hx_Wx);
551	/** Opcode VEX.66.0F38 0xae (vex only). */
552	FNIEMOP_STUB(iemOp_vfnmsub213ps_d_Vx_Hx_Wx);
553	/** Opcode VEX.66.0F38 0xaf (vex only). */
554	FNIEMOP_STUB(iemOp_vfnmsub213ss_d_Vx_Hx_Wx);
555
556	/* Opcode VEX.66.0F38 0xb0 - invalid. */
557	/* Opcode VEX.66.0F38 0xb1 - invalid. */
558	/* Opcode VEX.66.0F38 0xb2 - invalid. */
559	/* Opcode VEX.66.0F38 0xb3 - invalid. */
560	/* Opcode VEX.66.0F38 0xb4 - invalid. */
561	/* Opcode VEX.66.0F38 0xb5 - invalid. */
562	/** Opcode VEX.66.0F38 0xb6 (vex only). */
563	FNIEMOP_STUB(iemOp_vfmaddsub231ps_d_Vx_Hx_Wx);
564	/** Opcode VEX.66.0F38 0xb7 (vex only). */
565	FNIEMOP_STUB(iemOp_vfmsubadd231ps_d_Vx_Hx_Wx);
566	/** Opcode VEX.66.0F38 0xb8 (vex only). */
567	FNIEMOP_STUB(iemOp_vfmadd231ps_d_Vx_Hx_Wx);
568	/** Opcode VEX.66.0F38 0xb9 (vex only). */
569	FNIEMOP_STUB(iemOp_vfmadd231ss_d_Vx_Hx_Wx);
570	/** Opcode VEX.66.0F38 0xba (vex only). */
571	FNIEMOP_STUB(iemOp_vfmsub231ps_d_Vx_Hx_Wx);
572	/** Opcode VEX.66.0F38 0xbb (vex only). */
573	FNIEMOP_STUB(iemOp_vfmsub231ss_d_Vx_Hx_Wx);
574	/** Opcode VEX.66.0F38 0xbc (vex only). */
575	FNIEMOP_STUB(iemOp_vfnmadd231ps_d_Vx_Hx_Wx);
576	/** Opcode VEX.66.0F38 0xbd (vex only). */
577	FNIEMOP_STUB(iemOp_vfnmadd231ss_d_Vx_Hx_Wx);
578	/** Opcode VEX.66.0F38 0xbe (vex only). */
579	FNIEMOP_STUB(iemOp_vfnmsub231ps_d_Vx_Hx_Wx);
580	/** Opcode VEX.66.0F38 0xbf (vex only). */
581	FNIEMOP_STUB(iemOp_vfnmsub231ss_d_Vx_Hx_Wx);
582
583	/* Opcode VEX.0F38 0xc0 - invalid. */
584	/* Opcode VEX.66.0F38 0xc0 - invalid. */
585	/* Opcode VEX.0F38 0xc1 - invalid. */
586	/* Opcode VEX.66.0F38 0xc1 - invalid. */
587	/* Opcode VEX.0F38 0xc2 - invalid. */
588	/* Opcode VEX.66.0F38 0xc2 - invalid. */
589	/* Opcode VEX.0F38 0xc3 - invalid. */
590	/* Opcode VEX.66.0F38 0xc3 - invalid. */
591	/* Opcode VEX.0F38 0xc4 - invalid. */
592	/* Opcode VEX.66.0F38 0xc4 - invalid. */
593	/* Opcode VEX.0F38 0xc5 - invalid. */
594	/* Opcode VEX.66.0F38 0xc5 - invalid. */
595	/* Opcode VEX.0F38 0xc6 - invalid. */
596	/* Opcode VEX.66.0F38 0xc6 - invalid. */
597	/* Opcode VEX.0F38 0xc7 - invalid. */
598	/* Opcode VEX.66.0F38 0xc7 - invalid. */
599	/** Opcode VEX.0F38 0xc8. */
600	FNIEMOP_STUB(iemOp_vsha1nexte_Vdq_Wdq);
601	/* Opcode VEX.66.0F38 0xc8 - invalid. */
602	/** Opcode VEX.0F38 0xc9. */
603	FNIEMOP_STUB(iemOp_vsha1msg1_Vdq_Wdq);
604	/* Opcode VEX.66.0F38 0xc9 - invalid. */
605	/** Opcode VEX.0F38 0xca. */
606	FNIEMOP_STUB(iemOp_vsha1msg2_Vdq_Wdq);
607	/* Opcode VEX.66.0F38 0xca - invalid. */
608	/** Opcode VEX.0F38 0xcb. */
609	FNIEMOP_STUB(iemOp_vsha256rnds2_Vdq_Wdq);
610	/* Opcode VEX.66.0F38 0xcb - invalid. */
611	/** Opcode VEX.0F38 0xcc. */
612	FNIEMOP_STUB(iemOp_vsha256msg1_Vdq_Wdq);
613	/* Opcode VEX.66.0F38 0xcc - invalid. */
614	/** Opcode VEX.0F38 0xcd. */
615	FNIEMOP_STUB(iemOp_vsha256msg2_Vdq_Wdq);
616	/* Opcode VEX.66.0F38 0xcd - invalid. */
617	/* Opcode VEX.0F38 0xce - invalid. */
618	/* Opcode VEX.66.0F38 0xce - invalid. */
619	/* Opcode VEX.0F38 0xcf - invalid. */
620	/* Opcode VEX.66.0F38 0xcf - invalid. */
621
622	/* Opcode VEX.66.0F38 0xd0 - invalid. */
623	/* Opcode VEX.66.0F38 0xd1 - invalid. */
624	/* Opcode VEX.66.0F38 0xd2 - invalid. */
625	/* Opcode VEX.66.0F38 0xd3 - invalid. */
626	/* Opcode VEX.66.0F38 0xd4 - invalid. */
627	/* Opcode VEX.66.0F38 0xd5 - invalid. */
628	/* Opcode VEX.66.0F38 0xd6 - invalid. */
629	/* Opcode VEX.66.0F38 0xd7 - invalid. */
630	/* Opcode VEX.66.0F38 0xd8 - invalid. */
631	/* Opcode VEX.66.0F38 0xd9 - invalid. */
632	/* Opcode VEX.66.0F38 0xda - invalid. */
633	/** Opcode VEX.66.0F38 0xdb. */
634	FNIEMOP_STUB(iemOp_vaesimc_Vdq_Wdq);
635	/** Opcode VEX.66.0F38 0xdc. */
636	FNIEMOP_STUB(iemOp_vaesenc_Vdq_Wdq);
637	/** Opcode VEX.66.0F38 0xdd. */
638	FNIEMOP_STUB(iemOp_vaesenclast_Vdq_Wdq);
639	/** Opcode VEX.66.0F38 0xde. */
640	FNIEMOP_STUB(iemOp_vaesdec_Vdq_Wdq);
641	/** Opcode VEX.66.0F38 0xdf. */
642	FNIEMOP_STUB(iemOp_vaesdeclast_Vdq_Wdq);
643
644	/* Opcode VEX.66.0F38 0xe0 - invalid. */
645	/* Opcode VEX.66.0F38 0xe1 - invalid. */
646	/* Opcode VEX.66.0F38 0xe2 - invalid. */
647	/* Opcode VEX.66.0F38 0xe3 - invalid. */
648	/* Opcode VEX.66.0F38 0xe4 - invalid. */
649	/* Opcode VEX.66.0F38 0xe5 - invalid. */
650	/* Opcode VEX.66.0F38 0xe6 - invalid. */
651	/* Opcode VEX.66.0F38 0xe7 - invalid. */
652	/* Opcode VEX.66.0F38 0xe8 - invalid. */
653	/* Opcode VEX.66.0F38 0xe9 - invalid. */
654	/* Opcode VEX.66.0F38 0xea - invalid. */
655	/* Opcode VEX.66.0F38 0xeb - invalid. */
656	/* Opcode VEX.66.0F38 0xec - invalid. */
657	/* Opcode VEX.66.0F38 0xed - invalid. */
658	/* Opcode VEX.66.0F38 0xee - invalid. */
659	/* Opcode VEX.66.0F38 0xef - invalid. */
660
661
662	/* Opcode VEX.0F38 0xf0 - invalid (legacy only). */
663	/* Opcode VEX.66.0F38 0xf0 - invalid (legacy only). */
664	/* Opcode VEX.F3.0F38 0xf0 - invalid. */
665	/* Opcode VEX.F2.0F38 0xf0 - invalid (legacy only). */
666
667	/* Opcode VEX.0F38 0xf1 - invalid (legacy only). */
668	/* Opcode VEX.66.0F38 0xf1 - invalid (legacy only). */
669	/* Opcode VEX.F3.0F38 0xf1 - invalid. */
670	/* Opcode VEX.F2.0F38 0xf1 - invalid (legacy only). */
671
672	/** Opcode VEX.0F38 0xf2 - ANDN (vex only). */
673	FNIEMOP_DEF(iemOp_andn_Gy_By_Ey)
674	{
675	IEMOP_MNEMONIC3(VEX_RVM, ANDN, andn, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
676	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1)
677	return iemOp_InvalidNeedRM(pVCpu);
678	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF);
679	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
680	if (IEM_IS_MODRM_REG_MODE(bRm))
681	{
682	/*
683	* Register, register.
684	*/
685	IEMOP_HLP_DONE_VEX_DECODING_L0();
686	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
687	{
688	IEM_MC_BEGIN(4, 0);
689	IEM_MC_ARG(uint64_t *, pDst, 0);
690	IEM_MC_ARG(uint64_t, uSrc1, 1);
691	IEM_MC_ARG(uint64_t, uSrc2, 2);
692	IEM_MC_ARG(uint32_t *, pEFlags, 3);
693	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
694	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
695	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
696	IEM_MC_REF_EFLAGS(pEFlags);
697	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
698	pDst, uSrc1, uSrc2, pEFlags);
699	IEM_MC_ADVANCE_RIP();
700	IEM_MC_END();
701	}
702	else
703	{
704	IEM_MC_BEGIN(4, 0);
705	IEM_MC_ARG(uint32_t *, pDst, 0);
706	IEM_MC_ARG(uint32_t, uSrc1, 1);
707	IEM_MC_ARG(uint32_t, uSrc2, 2);
708	IEM_MC_ARG(uint32_t *, pEFlags, 3);
709	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
710	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
711	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
712	IEM_MC_REF_EFLAGS(pEFlags);
713	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
714	pDst, uSrc1, uSrc2, pEFlags);
715	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
716	IEM_MC_ADVANCE_RIP();
717	IEM_MC_END();
718	}
719	}
720	else
721	{
722	/*
723	* Register, memory.
724	*/
725	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
726	{
727	IEM_MC_BEGIN(4, 1);
728	IEM_MC_ARG(uint64_t *, pDst, 0);
729	IEM_MC_ARG(uint64_t, uSrc1, 1);
730	IEM_MC_ARG(uint64_t, uSrc2, 2);
731	IEM_MC_ARG(uint32_t *, pEFlags, 3);
732	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
733	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
734	IEMOP_HLP_DONE_VEX_DECODING_L0();
735	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
736	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
737	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
738	IEM_MC_REF_EFLAGS(pEFlags);
739	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
740	pDst, uSrc1, uSrc2, pEFlags);
741	IEM_MC_ADVANCE_RIP();
742	IEM_MC_END();
743	}
744	else
745	{
746	IEM_MC_BEGIN(4, 1);
747	IEM_MC_ARG(uint32_t *, pDst, 0);
748	IEM_MC_ARG(uint32_t, uSrc1, 1);
749	IEM_MC_ARG(uint32_t, uSrc2, 2);
750	IEM_MC_ARG(uint32_t *, pEFlags, 3);
751	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
752	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
753	IEMOP_HLP_DONE_VEX_DECODING_L0();
754	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
755	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
756	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
757	IEM_MC_REF_EFLAGS(pEFlags);
758	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
759	pDst, uSrc1, uSrc2, pEFlags);
760	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
761	IEM_MC_ADVANCE_RIP();
762	IEM_MC_END();
763	}
764	}
765	return VINF_SUCCESS;
766	}
767
768	/* Opcode VEX.66.0F38 0xf2 - invalid. */
769	/* Opcode VEX.F3.0F38 0xf2 - invalid. */
770	/* Opcode VEX.F2.0F38 0xf2 - invalid. */
771
772
773	/* Opcode VEX.0F38 0xf3 - invalid. */
774	/* Opcode VEX.66.0F38 0xf3 - invalid. */
775
776	/* Opcode VEX.F3.0F38 0xf3 /0 - invalid. */
777
778	/** Body for the vex group 17 instructions. */
779	#define IEMOP_BODY_By_Ey(a_Instr) \
780	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1) \
781	return iemOp_InvalidWithRM(pVCpu, bRm); /* decode memory variant? */ \
782	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF); \
783	if (IEM_IS_MODRM_REG_MODE(bRm)) \
784	{ \
785	/* \
786	* Register, register. \
787	*/ \
788	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
789	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
790	{ \
791	IEM_MC_BEGIN(3, 0); \
792	IEM_MC_ARG(uint64_t *, pDst, 0); \
793	IEM_MC_ARG(uint64_t, uSrc, 1); \
794	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
795	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
796	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
797	IEM_MC_REF_EFLAGS(pEFlags); \
798	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
799	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
800	IEM_MC_ADVANCE_RIP(); \
801	IEM_MC_END(); \
802	} \
803	else \
804	{ \
805	IEM_MC_BEGIN(3, 0); \
806	IEM_MC_ARG(uint32_t *, pDst, 0); \
807	IEM_MC_ARG(uint32_t, uSrc, 1); \
808	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
809	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
810	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
811	IEM_MC_REF_EFLAGS(pEFlags); \
812	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
813	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
814	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
815	IEM_MC_ADVANCE_RIP(); \
816	IEM_MC_END(); \
817	} \
818	} \
819	else \
820	{ \
821	/* \
822	* Register, memory. \
823	*/ \
824	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
825	{ \
826	IEM_MC_BEGIN(3, 1); \
827	IEM_MC_ARG(uint64_t *, pDst, 0); \
828	IEM_MC_ARG(uint64_t, uSrc, 1); \
829	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
830	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
831	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
832	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
833	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
834	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
835	IEM_MC_REF_EFLAGS(pEFlags); \
836	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
837	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
838	IEM_MC_ADVANCE_RIP(); \
839	IEM_MC_END(); \
840	} \
841	else \
842	{ \
843	IEM_MC_BEGIN(3, 1); \
844	IEM_MC_ARG(uint32_t *, pDst, 0); \
845	IEM_MC_ARG(uint32_t, uSrc, 1); \
846	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
847	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
848	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
849	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
850	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
851	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
852	IEM_MC_REF_EFLAGS(pEFlags); \
853	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
854	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
855	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
856	IEM_MC_ADVANCE_RIP(); \
857	IEM_MC_END(); \
858	} \
859	} \
860	return VINF_SUCCESS
861
862
863	/* Opcode VEX.F3.0F38 0xf3 /1. */
864	/** @opcode /1
865	* @opmaps vexgrp17 */
866	FNIEMOP_DEF_1(iemOp_VGrp17_blsr_By_Ey, uint8_t, bRm)
867	{
868	IEMOP_MNEMONIC2(VEX_VM, BLSR, blsr, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
869	IEMOP_BODY_By_Ey(blsr);
870	}
871
872
873	/* Opcode VEX.F3.0F38 0xf3 /2. */
874	/** @opcode /2
875	* @opmaps vexgrp17 */
876	FNIEMOP_DEF_1(iemOp_VGrp17_blsmsk_By_Ey, uint8_t, bRm)
877	{
878	IEMOP_MNEMONIC2(VEX_VM, BLSMSK, blsmsk, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
879	IEMOP_BODY_By_Ey(blsmsk);
880	}
881
882
883	/* Opcode VEX.F3.0F38 0xf3 /3. */
884	/** @opcode /3
885	* @opmaps vexgrp17 */
886	FNIEMOP_DEF_1(iemOp_VGrp17_blsi_By_Ey, uint8_t, bRm)
887	{
888	IEMOP_MNEMONIC2(VEX_VM, BLSI, blsi, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
889	IEMOP_BODY_By_Ey(blsi);
890	}
891
892
893	/* Opcode VEX.F3.0F38 0xf3 /4 - invalid. */
894	/* Opcode VEX.F3.0F38 0xf3 /5 - invalid. */
895	/* Opcode VEX.F3.0F38 0xf3 /6 - invalid. */
896	/* Opcode VEX.F3.0F38 0xf3 /7 - invalid. */
897
898	/**
899	* Group 17 jump table for the VEX.F3 variant.
900	*/
901	IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =
902	{
903	/* /0 */ iemOp_InvalidWithRM,
904	/* /1 */ iemOp_VGrp17_blsr_By_Ey,
905	/* /2 */ iemOp_VGrp17_blsmsk_By_Ey,
906	/* /3 */ iemOp_VGrp17_blsi_By_Ey,
907	/* /4 */ iemOp_InvalidWithRM,
908	/* /5 */ iemOp_InvalidWithRM,
909	/* /6 */ iemOp_InvalidWithRM,
910	/* /7 */ iemOp_InvalidWithRM
911	};
912	AssertCompile(RT_ELEMENTS(g_apfnVexGroup17_f3) == 8);
913
914	/** Opcode VEX.F3.0F38 0xf3 - invalid (vex only - group 17). */
915	FNIEMOP_DEF(iemOp_VGrp17_f3)
916	{
917	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
918	return FNIEMOP_CALL_1(g_apfnVexGroup17_f3[IEM_GET_MODRM_REG_8(bRm)], bRm);
919	}
920
921	/* Opcode VEX.F2.0F38 0xf3 - invalid (vex only - group 17). */
922
923
924	/* Opcode VEX.0F38 0xf4 - invalid. */
925	/* Opcode VEX.66.0F38 0xf4 - invalid. */
926	/* Opcode VEX.F3.0F38 0xf4 - invalid. */
927	/* Opcode VEX.F2.0F38 0xf4 - invalid. */
928
929	/** Body for BZHI, BEXTR, ++; assumes VEX.L must be 0. */
930	#define IEMOP_BODY_Gy_Ey_By(a_Instr, a_fFeatureMember, a_fUndefFlags) \
931	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
932	return iemOp_InvalidNeedRM(pVCpu); \
933	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
934	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
935	if (IEM_IS_MODRM_REG_MODE(bRm)) \
936	{ \
937	/* \
938	* Register, register. \
939	*/ \
940	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
941	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
942	{ \
943	IEM_MC_BEGIN(4, 0); \
944	IEM_MC_ARG(uint64_t *, pDst, 0); \
945	IEM_MC_ARG(uint64_t, uSrc1, 1); \
946	IEM_MC_ARG(uint64_t, uSrc2, 2); \
947	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
948	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
949	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
950	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
951	IEM_MC_REF_EFLAGS(pEFlags); \
952	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
953	iemAImpl_ ## a_Instr ## _u64_fallback), \
954	pDst, uSrc1, uSrc2, pEFlags); \
955	IEM_MC_ADVANCE_RIP(); \
956	IEM_MC_END(); \
957	} \
958	else \
959	{ \
960	IEM_MC_BEGIN(4, 0); \
961	IEM_MC_ARG(uint32_t *, pDst, 0); \
962	IEM_MC_ARG(uint32_t, uSrc1, 1); \
963	IEM_MC_ARG(uint32_t, uSrc2, 2); \
964	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
965	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
966	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
967	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
968	IEM_MC_REF_EFLAGS(pEFlags); \
969	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
970	iemAImpl_ ## a_Instr ## _u32_fallback), \
971	pDst, uSrc1, uSrc2, pEFlags); \
972	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
973	IEM_MC_ADVANCE_RIP(); \
974	IEM_MC_END(); \
975	} \
976	} \
977	else \
978	{ \
979	/* \
980	* Register, memory. \
981	*/ \
982	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
983	{ \
984	IEM_MC_BEGIN(4, 1); \
985	IEM_MC_ARG(uint64_t *, pDst, 0); \
986	IEM_MC_ARG(uint64_t, uSrc1, 1); \
987	IEM_MC_ARG(uint64_t, uSrc2, 2); \
988	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
989	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
990	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
991	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
992	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
993	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
994	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
995	IEM_MC_REF_EFLAGS(pEFlags); \
996	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
997	iemAImpl_ ## a_Instr ## _u64_fallback), \
998	pDst, uSrc1, uSrc2, pEFlags); \
999	IEM_MC_ADVANCE_RIP(); \
1000	IEM_MC_END(); \
1001	} \
1002	else \
1003	{ \
1004	IEM_MC_BEGIN(4, 1); \
1005	IEM_MC_ARG(uint32_t *, pDst, 0); \
1006	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1007	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1008	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1009	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1010	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1011	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1012	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1013	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1014	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1015	IEM_MC_REF_EFLAGS(pEFlags); \
1016	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1017	iemAImpl_ ## a_Instr ## _u32_fallback), \
1018	pDst, uSrc1, uSrc2, pEFlags); \
1019	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1020	IEM_MC_ADVANCE_RIP(); \
1021	IEM_MC_END(); \
1022	} \
1023	} \
1024	return VINF_SUCCESS
1025
1026	/** Body for SARX, SHLX, SHRX; assumes VEX.L must be 0. */
1027	#define IEMOP_BODY_Gy_Ey_By_NoEflags(a_Instr, a_fFeatureMember, a_fUndefFlags) \
1028	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
1029	return iemOp_InvalidNeedRM(pVCpu); \
1030	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
1031	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1032	if (IEM_IS_MODRM_REG_MODE(bRm)) \
1033	{ \
1034	/* \
1035	* Register, register. \
1036	*/ \
1037	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1038	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1039	{ \
1040	IEM_MC_BEGIN(3, 0); \
1041	IEM_MC_ARG(uint64_t *, pDst, 0); \
1042	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1043	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1044	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1045	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1046	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1047	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1048	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1049	IEM_MC_ADVANCE_RIP(); \
1050	IEM_MC_END(); \
1051	} \
1052	else \
1053	{ \
1054	IEM_MC_BEGIN(3, 0); \
1055	IEM_MC_ARG(uint32_t *, pDst, 0); \
1056	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1057	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1058	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1059	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1060	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1061	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1062	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1063	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1064	IEM_MC_ADVANCE_RIP(); \
1065	IEM_MC_END(); \
1066	} \
1067	} \
1068	else \
1069	{ \
1070	/* \
1071	* Register, memory. \
1072	*/ \
1073	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1074	{ \
1075	IEM_MC_BEGIN(3, 1); \
1076	IEM_MC_ARG(uint64_t *, pDst, 0); \
1077	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1078	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1079	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1080	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1081	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1082	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1083	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1084	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1085	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1086	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1087	IEM_MC_ADVANCE_RIP(); \
1088	IEM_MC_END(); \
1089	} \
1090	else \
1091	{ \
1092	IEM_MC_BEGIN(3, 1); \
1093	IEM_MC_ARG(uint32_t *, pDst, 0); \
1094	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1095	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1096	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1097	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1098	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1099	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1100	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1101	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1102	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1103	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1104	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1105	IEM_MC_ADVANCE_RIP(); \
1106	IEM_MC_END(); \
1107	} \
1108	} \
1109	return VINF_SUCCESS
1110
1111	/** Opcode VEX.0F38 0xf5 (vex only). */
1112	FNIEMOP_DEF(iemOp_bzhi_Gy_Ey_By)
1113	{
1114	IEMOP_MNEMONIC3(VEX_RMV, BZHI, bzhi, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1115	IEMOP_BODY_Gy_Ey_By(bzhi, fBmi2, X86_EFL_AF \| X86_EFL_PF);
1116	}
1117
1118	/* Opcode VEX.66.0F38 0xf5 - invalid. */
1119
1120	/** Body for PDEP and PEXT (similar to ANDN, except no EFLAGS). */
1121	#define IEMOP_BODY_Gy_By_Ey_NoEflags(a_Instr, a_fFeatureMember) \
1122	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
1123	return iemOp_InvalidNeedRM(pVCpu); \
1124	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1125	if (IEM_IS_MODRM_REG_MODE(bRm)) \
1126	{ \
1127	/* \
1128	* Register, register. \
1129	*/ \
1130	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1131	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1132	{ \
1133	IEM_MC_BEGIN(3, 0); \
1134	IEM_MC_ARG(uint64_t *, pDst, 0); \
1135	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1136	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1137	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1138	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1139	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1140	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1141	iemAImpl_ ## a_Instr ## _u64, \
1142	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1143	IEM_MC_ADVANCE_RIP(); \
1144	IEM_MC_END(); \
1145	} \
1146	else \
1147	{ \
1148	IEM_MC_BEGIN(3, 0); \
1149	IEM_MC_ARG(uint32_t *, pDst, 0); \
1150	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1151	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1152	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1153	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1154	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1155	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1156	iemAImpl_ ## a_Instr ## _u32, \
1157	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1158	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1159	IEM_MC_ADVANCE_RIP(); \
1160	IEM_MC_END(); \
1161	} \
1162	} \
1163	else \
1164	{ \
1165	/* \
1166	* Register, memory. \
1167	*/ \
1168	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1169	{ \
1170	IEM_MC_BEGIN(3, 1); \
1171	IEM_MC_ARG(uint64_t *, pDst, 0); \
1172	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1173	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1174	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1175	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1176	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1177	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1178	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1179	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1180	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1181	iemAImpl_ ## a_Instr ## _u64, \
1182	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1183	IEM_MC_ADVANCE_RIP(); \
1184	IEM_MC_END(); \
1185	} \
1186	else \
1187	{ \
1188	IEM_MC_BEGIN(3, 1); \
1189	IEM_MC_ARG(uint32_t *, pDst, 0); \
1190	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1191	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1192	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1193	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1194	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1195	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1196	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1197	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1198	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1199	iemAImpl_ ## a_Instr ## _u32, \
1200	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1201	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1202	IEM_MC_ADVANCE_RIP(); \
1203	IEM_MC_END(); \
1204	} \
1205	} \
1206	return VINF_SUCCESS;
1207
1208
1209	/** Opcode VEX.F3.0F38 0xf5 (vex only). */
1210	FNIEMOP_DEF(iemOp_pext_Gy_By_Ey)
1211	{
1212	IEMOP_MNEMONIC3(VEX_RVM, PEXT, pext, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1213	IEMOP_BODY_Gy_By_Ey_NoEflags(pext, fBmi2);
1214	}
1215
1216
1217	/** Opcode VEX.F2.0F38 0xf5 (vex only). */
1218	FNIEMOP_DEF(iemOp_pdep_Gy_By_Ey)
1219	{
1220	IEMOP_MNEMONIC3(VEX_RVM, PDEP, pdep, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1221	IEMOP_BODY_Gy_By_Ey_NoEflags(pdep, fBmi2);
1222	}
1223
1224
1225	/* Opcode VEX.0F38 0xf6 - invalid. */
1226	/* Opcode VEX.66.0F38 0xf6 - invalid (legacy only). */
1227	/* Opcode VEX.F3.0F38 0xf6 - invalid (legacy only). */
1228
1229
1230	/** Opcode VEX.F2.0F38 0xf6 (vex only) */
1231	FNIEMOP_DEF(iemOp_mulx_By_Gy_rDX_Ey)
1232	{
1233	IEMOP_MNEMONIC4(VEX_RVM, MULX, mulx, Gy, By, Ey, rDX, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1234	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi2)
1235	return iemOp_InvalidNeedRM(pVCpu);
1236	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1237	if (IEM_IS_MODRM_REG_MODE(bRm))
1238	{
1239	/*
1240	* Register, register.
1241	*/
1242	IEMOP_HLP_DONE_VEX_DECODING_L0();
1243	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1244	{
1245	IEM_MC_BEGIN(4, 0);
1246	IEM_MC_ARG(uint64_t *, pDst1, 0);
1247	IEM_MC_ARG(uint64_t *, pDst2, 1);
1248	IEM_MC_ARG(uint64_t, uSrc1, 2);
1249	IEM_MC_ARG(uint64_t, uSrc2, 3);
1250	IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1251	IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1252	IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1253	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1254	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1255	pDst1, pDst2, uSrc1, uSrc2);
1256	IEM_MC_ADVANCE_RIP();
1257	IEM_MC_END();
1258	}
1259	else
1260	{
1261	IEM_MC_BEGIN(4, 0);
1262	IEM_MC_ARG(uint32_t *, pDst1, 0);
1263	IEM_MC_ARG(uint32_t *, pDst2, 1);
1264	IEM_MC_ARG(uint32_t, uSrc1, 2);
1265	IEM_MC_ARG(uint32_t, uSrc2, 3);
1266	IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1267	IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1268	IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1269	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1270	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1271	pDst1, pDst2, uSrc1, uSrc2);
1272	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1273	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1274	IEM_MC_ADVANCE_RIP();
1275	IEM_MC_END();
1276	}
1277	}
1278	else
1279	{
1280	/*
1281	* Register, memory.
1282	*/
1283	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1284	{
1285	IEM_MC_BEGIN(4, 1);
1286	IEM_MC_ARG(uint64_t *, pDst1, 0);
1287	IEM_MC_ARG(uint64_t *, pDst2, 1);
1288	IEM_MC_ARG(uint64_t, uSrc1, 2);
1289	IEM_MC_ARG(uint64_t, uSrc2, 3);
1290	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1291	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1292	IEMOP_HLP_DONE_VEX_DECODING_L0();
1293	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1294	IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1295	IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1296	IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1297	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1298	pDst1, pDst2, uSrc1, uSrc2);
1299	IEM_MC_ADVANCE_RIP();
1300	IEM_MC_END();
1301	}
1302	else
1303	{
1304	IEM_MC_BEGIN(4, 1);
1305	IEM_MC_ARG(uint32_t *, pDst1, 0);
1306	IEM_MC_ARG(uint32_t *, pDst2, 1);
1307	IEM_MC_ARG(uint32_t, uSrc1, 2);
1308	IEM_MC_ARG(uint32_t, uSrc2, 3);
1309	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1310	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1311	IEMOP_HLP_DONE_VEX_DECODING_L0();
1312	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1313	IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1314	IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1315	IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1316	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1317	pDst1, pDst2, uSrc1, uSrc2);
1318	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1319	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1320	IEM_MC_ADVANCE_RIP();
1321	IEM_MC_END();
1322	}
1323	}
1324	return VINF_SUCCESS;
1325	}
1326
1327
1328	/** Opcode VEX.0F38 0xf7 (vex only). */
1329	FNIEMOP_DEF(iemOp_bextr_Gy_Ey_By)
1330	{
1331	IEMOP_MNEMONIC3(VEX_RMV, BEXTR, bextr, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1332	IEMOP_BODY_Gy_Ey_By(bextr, fBmi1, X86_EFL_SF \| X86_EFL_AF \| X86_EFL_PF);
1333	}
1334
1335
1336	/** Opcode VEX.66.0F38 0xf7 (vex only). */
1337	FNIEMOP_DEF(iemOp_shlx_Gy_Ey_By)
1338	{
1339	IEMOP_MNEMONIC3(VEX_RMV, SHLX, shlx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1340	IEMOP_BODY_Gy_Ey_By_NoEflags(shlx, fBmi2, 0);
1341	}
1342
1343
1344	/** Opcode VEX.F3.0F38 0xf7 (vex only). */
1345	FNIEMOP_DEF(iemOp_sarx_Gy_Ey_By)
1346	{
1347	IEMOP_MNEMONIC3(VEX_RMV, SARX, sarx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1348	IEMOP_BODY_Gy_Ey_By_NoEflags(sarx, fBmi2, 0);
1349	}
1350
1351
1352	/** Opcode VEX.F2.0F38 0xf7 (vex only). */
1353	FNIEMOP_DEF(iemOp_shrx_Gy_Ey_By)
1354	{
1355	IEMOP_MNEMONIC3(VEX_RMV, SHRX, shrx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1356	IEMOP_BODY_Gy_Ey_By_NoEflags(shrx, fBmi2, 0);
1357	}
1358
1359	/* Opcode VEX.0F38 0xf8 - invalid. */
1360	/* Opcode VEX.66.0F38 0xf8 - invalid. */
1361	/* Opcode VEX.F3.0F38 0xf8 - invalid. */
1362	/* Opcode VEX.F2.0F38 0xf8 - invalid. */
1363
1364	/* Opcode VEX.0F38 0xf9 - invalid. */
1365	/* Opcode VEX.66.0F38 0xf9 - invalid. */
1366	/* Opcode VEX.F3.0F38 0xf9 - invalid. */
1367	/* Opcode VEX.F2.0F38 0xf9 - invalid. */
1368
1369	/* Opcode VEX.0F38 0xfa - invalid. */
1370	/* Opcode VEX.66.0F38 0xfa - invalid. */
1371	/* Opcode VEX.F3.0F38 0xfa - invalid. */
1372	/* Opcode VEX.F2.0F38 0xfa - invalid. */
1373
1374	/* Opcode VEX.0F38 0xfb - invalid. */
1375	/* Opcode VEX.66.0F38 0xfb - invalid. */
1376	/* Opcode VEX.F3.0F38 0xfb - invalid. */
1377	/* Opcode VEX.F2.0F38 0xfb - invalid. */
1378
1379	/* Opcode VEX.0F38 0xfc - invalid. */
1380	/* Opcode VEX.66.0F38 0xfc - invalid. */
1381	/* Opcode VEX.F3.0F38 0xfc - invalid. */
1382	/* Opcode VEX.F2.0F38 0xfc - invalid. */
1383
1384	/* Opcode VEX.0F38 0xfd - invalid. */
1385	/* Opcode VEX.66.0F38 0xfd - invalid. */
1386	/* Opcode VEX.F3.0F38 0xfd - invalid. */
1387	/* Opcode VEX.F2.0F38 0xfd - invalid. */
1388
1389	/* Opcode VEX.0F38 0xfe - invalid. */
1390	/* Opcode VEX.66.0F38 0xfe - invalid. */
1391	/* Opcode VEX.F3.0F38 0xfe - invalid. */
1392	/* Opcode VEX.F2.0F38 0xfe - invalid. */
1393
1394	/* Opcode VEX.0F38 0xff - invalid. */
1395	/* Opcode VEX.66.0F38 0xff - invalid. */
1396	/* Opcode VEX.F3.0F38 0xff - invalid. */
1397	/* Opcode VEX.F2.0F38 0xff - invalid. */
1398
1399
1400	/**
1401	* VEX opcode map \#2.
1402	*
1403	* @sa g_apfnThreeByte0f38
1404	*/
1405	IEM_STATIC const PFNIEMOP g_apfnVexMap2[] =
1406	{
1407	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1408	/* 0x00 */ iemOp_InvalidNeedRM, iemOp_vpshufb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1409	/* 0x01 */ iemOp_InvalidNeedRM, iemOp_vphaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1410	/* 0x02 */ iemOp_InvalidNeedRM, iemOp_vphaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1411	/* 0x03 */ iemOp_InvalidNeedRM, iemOp_vphaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1412	/* 0x04 */ iemOp_InvalidNeedRM, iemOp_vpmaddubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1413	/* 0x05 */ iemOp_InvalidNeedRM, iemOp_vphsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1414	/* 0x06 */ iemOp_InvalidNeedRM, iemOp_vphsubdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1415	/* 0x07 */ iemOp_InvalidNeedRM, iemOp_vphsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1416	/* 0x08 */ iemOp_InvalidNeedRM, iemOp_vpsignb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1417	/* 0x09 */ iemOp_InvalidNeedRM, iemOp_vpsignw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1418	/* 0x0a */ iemOp_InvalidNeedRM, iemOp_vpsignd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1419	/* 0x0b */ iemOp_InvalidNeedRM, iemOp_vpmulhrsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1420	/* 0x0c */ iemOp_InvalidNeedRM, iemOp_vpermilps_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1421	/* 0x0d */ iemOp_InvalidNeedRM, iemOp_vpermilpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1422	/* 0x0e */ iemOp_InvalidNeedRM, iemOp_vtestps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1423	/* 0x0f */ iemOp_InvalidNeedRM, iemOp_vtestpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1424
1425	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRM),
1426	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
1427	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
1428	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
1429	/* 0x14 */ IEMOP_X4(iemOp_InvalidNeedRM),
1430	/* 0x15 */ IEMOP_X4(iemOp_InvalidNeedRM),
1431	/* 0x16 */ iemOp_InvalidNeedRM, iemOp_vpermps_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1432	/* 0x17 */ iemOp_InvalidNeedRM, iemOp_vptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1433	/* 0x18 */ iemOp_InvalidNeedRM, iemOp_vbroadcastss_Vx_Wd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1434	/* 0x19 */ iemOp_InvalidNeedRM, iemOp_vbroadcastsd_Vqq_Wq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1435	/* 0x1a */ iemOp_InvalidNeedRM, iemOp_vbroadcastf128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1436	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
1437	/* 0x1c */ iemOp_InvalidNeedRM, iemOp_vpabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1438	/* 0x1d */ iemOp_InvalidNeedRM, iemOp_vpabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1439	/* 0x1e */ iemOp_InvalidNeedRM, iemOp_vpabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1440	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
1441
1442	/* 0x20 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1443	/* 0x21 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1444	/* 0x22 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1445	/* 0x23 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1446	/* 0x24 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1447	/* 0x25 */ iemOp_InvalidNeedRM, iemOp_vpmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1448	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
1449	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
1450	/* 0x28 */ iemOp_InvalidNeedRM, iemOp_vpmuldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1451	/* 0x29 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1452	/* 0x2a */ iemOp_InvalidNeedRM, iemOp_vmovntdqa_Vx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1453	/* 0x2b */ iemOp_InvalidNeedRM, iemOp_vpackusdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1454	/* 0x2c */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1455	/* 0x2d */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1456	/* 0x2e */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1457	/* 0x2f */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1458
1459	/* 0x30 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1460	/* 0x31 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1461	/* 0x32 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1462	/* 0x33 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1463	/* 0x34 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1464	/* 0x35 */ iemOp_InvalidNeedRM, iemOp_vpmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1465	/* 0x36 */ iemOp_InvalidNeedRM, iemOp_vpermd_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1466	/* 0x37 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1467	/* 0x38 */ iemOp_InvalidNeedRM, iemOp_vpminsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1468	/* 0x39 */ iemOp_InvalidNeedRM, iemOp_vpminsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1469	/* 0x3a */ iemOp_InvalidNeedRM, iemOp_vpminuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1470	/* 0x3b */ iemOp_InvalidNeedRM, iemOp_vpminud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1471	/* 0x3c */ iemOp_InvalidNeedRM, iemOp_vpmaxsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1472	/* 0x3d */ iemOp_InvalidNeedRM, iemOp_vpmaxsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1473	/* 0x3e */ iemOp_InvalidNeedRM, iemOp_vpmaxuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1474	/* 0x3f */ iemOp_InvalidNeedRM, iemOp_vpmaxud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1475
1476	/* 0x40 */ iemOp_InvalidNeedRM, iemOp_vpmulld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1477	/* 0x41 */ iemOp_InvalidNeedRM, iemOp_vphminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1478	/* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
1479	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
1480	/* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
1481	/* 0x45 */ iemOp_InvalidNeedRM, iemOp_vpsrlvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1482	/* 0x46 */ iemOp_InvalidNeedRM, iemOp_vsravd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1483	/* 0x47 */ iemOp_InvalidNeedRM, iemOp_vpsllvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1484	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
1485	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
1486	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
1487	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
1488	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
1489	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
1490	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
1491	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
1492
1493	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
1494	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
1495	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
1496	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
1497	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
1498	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
1499	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
1500	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
1501	/* 0x58 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1502	/* 0x59 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1503	/* 0x5a */ iemOp_InvalidNeedRM, iemOp_vbroadcasti128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1504	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
1505	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
1506	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
1507	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
1508	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
1509
1510	/* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
1511	/* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
1512	/* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
1513	/* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
1514	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
1515	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
1516	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
1517	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
1518	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
1519	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
1520	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
1521	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
1522	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
1523	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
1524	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
1525	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
1526
1527	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
1528	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
1529	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
1530	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
1531	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
1532	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
1533	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
1534	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
1535	/* 0x78 */ iemOp_InvalidNeedRM, iemOp_vpboardcastb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1536	/* 0x79 */ iemOp_InvalidNeedRM, iemOp_vpboardcastw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1537	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
1538	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
1539	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
1540	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
1541	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
1542	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
1543
1544	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
1545	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
1546	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
1547	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
1548	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
1549	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
1550	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
1551	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
1552	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
1553	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
1554	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
1555	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
1556	/* 0x8c */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1557	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
1558	/* 0x8e */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Mx_Vx_Hx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1559	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
1560
1561	/* 0x90 */ iemOp_InvalidNeedRM, iemOp_vgatherdd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1562	/* 0x91 */ iemOp_InvalidNeedRM, iemOp_vgatherqd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1563	/* 0x92 */ iemOp_InvalidNeedRM, iemOp_vgatherdps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1564	/* 0x93 */ iemOp_InvalidNeedRM, iemOp_vgatherqps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1565	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
1566	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
1567	/* 0x96 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub132ps_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1568	/* 0x97 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1569	/* 0x98 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1570	/* 0x99 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1571	/* 0x9a */ iemOp_InvalidNeedRM, iemOp_vfmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1572	/* 0x9b */ iemOp_InvalidNeedRM, iemOp_vfmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1573	/* 0x9c */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1574	/* 0x9d */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1575	/* 0x9e */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1576	/* 0x9f */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1577
1578	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1579	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1580	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1581	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1582	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1583	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1584	/* 0xa6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1585	/* 0xa7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1586	/* 0xa8 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1587	/* 0xa9 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1588	/* 0xaa */ iemOp_InvalidNeedRM, iemOp_vfmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1589	/* 0xab */ iemOp_InvalidNeedRM, iemOp_vfmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1590	/* 0xac */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1591	/* 0xad */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1592	/* 0xae */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1593	/* 0xaf */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1594
1595	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1596	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1597	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1598	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1599	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1600	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1601	/* 0xb6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1602	/* 0xb7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1603	/* 0xb8 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1604	/* 0xb9 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1605	/* 0xba */ iemOp_InvalidNeedRM, iemOp_vfmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1606	/* 0xbb */ iemOp_InvalidNeedRM, iemOp_vfmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1607	/* 0xbc */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1608	/* 0xbd */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1609	/* 0xbe */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1610	/* 0xbf */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1611
1612	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1613	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1614	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1615	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1616	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1617	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1618	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1619	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1620	/* 0xc8 */ iemOp_vsha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1621	/* 0xc9 */ iemOp_vsha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1622	/* 0xca */ iemOp_vsha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1623	/* 0xcb */ iemOp_vsha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1624	/* 0xcc */ iemOp_vsha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1625	/* 0xcd */ iemOp_vsha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1626	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
1627	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
1628
1629	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1630	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1631	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1632	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1633	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1634	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1635	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1636	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1637	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1638	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1639	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
1640	/* 0xdb */ iemOp_InvalidNeedRM, iemOp_vaesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1641	/* 0xdc */ iemOp_InvalidNeedRM, iemOp_vaesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1642	/* 0xdd */ iemOp_InvalidNeedRM, iemOp_vaesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1643	/* 0xde */ iemOp_InvalidNeedRM, iemOp_vaesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1644	/* 0xdf */ iemOp_InvalidNeedRM, iemOp_vaesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1645
1646	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1647	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1648	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1649	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1650	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1651	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1652	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1653	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1654	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1655	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1656	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
1657	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
1658	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
1659	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
1660	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
1661	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
1662
1663	/* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1664	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1665	/* 0xf2 */ iemOp_andn_Gy_By_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1666	/* 0xf3 */ iemOp_VGrp17_f3, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1667	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1668	/* 0xf5 */ iemOp_bzhi_Gy_Ey_By, iemOp_InvalidNeedRM, iemOp_pext_Gy_By_Ey, iemOp_pdep_Gy_By_Ey,
1669	/* 0xf6 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_mulx_By_Gy_rDX_Ey,
1670	/* 0xf7 */ iemOp_bextr_Gy_Ey_By, iemOp_shlx_Gy_Ey_By, iemOp_sarx_Gy_Ey_By, iemOp_shrx_Gy_Ey_By,
1671	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1672	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1673	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
1674	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
1675	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
1676	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
1677	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
1678	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
1679	};
1680	AssertCompile(RT_ELEMENTS(g_apfnVexMap2) == 1024);
1681
1682	/** @} */
1683

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h@ 95578

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