IEMAllInstructionsVexMap2.cpp.h@ 96002

Last change on this file since 96002 was 96002, checked in by vboxsync, 2 years ago
VMM/IEM: Implement missing [v]pmaxu{w,d} variants, bugref:9898
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File size: 76.3 KB

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1	/* $Id: IEMAllInstructionsVexMap2.cpp.h 96002 2022-08-03 17:20:27Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation.
4	*
5	* @remarks IEMAllInstructionsThree0f38.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/** @name VEX Opcode Map 2
23	* @{
24	*/
25
26	/* Opcode VEX.0F38 0x00 - invalid. */
27
28
29	/** Opcode VEX.66.0F38 0x00. */
30	FNIEMOP_DEF(iemOp_vpshufb_Vx_Hx_Wx)
31	{
32	IEMOP_MNEMONIC3(VEX_RVM, VPSHUFB, vpshufb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
33	IEMOPMEDIAF3_INIT_VARS(vpshufb);
34	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
35	}
36
37
38	/* Opcode VEX.0F38 0x01 - invalid. */
39	/** Opcode VEX.66.0F38 0x01. */
40	FNIEMOP_STUB(iemOp_vphaddw_Vx_Hx_Wx);
41	/* Opcode VEX.0F38 0x02 - invalid. */
42	/** Opcode VEX.66.0F38 0x02. */
43	FNIEMOP_STUB(iemOp_vphaddd_Vx_Hx_Wx);
44	/* Opcode VEX.0F38 0x03 - invalid. */
45	/** Opcode VEX.66.0F38 0x03. */
46	FNIEMOP_STUB(iemOp_vphaddsw_Vx_Hx_Wx);
47	/* Opcode VEX.0F38 0x04 - invalid. */
48	/** Opcode VEX.66.0F38 0x04. */
49	FNIEMOP_STUB(iemOp_vpmaddubsw_Vx_Hx_Wx);
50	/* Opcode VEX.0F38 0x05 - invalid. */
51	/** Opcode VEX.66.0F38 0x05. */
52	FNIEMOP_STUB(iemOp_vphsubw_Vx_Hx_Wx);
53	/* Opcode VEX.0F38 0x06 - invalid. */
54	/** Opcode VEX.66.0F38 0x06. */
55	FNIEMOP_STUB(iemOp_vphsubdq_Vx_Hx_Wx);
56	/* Opcode VEX.0F38 0x07 - invalid. */
57	/** Opcode VEX.66.0F38 0x07. */
58	FNIEMOP_STUB(iemOp_vphsubsw_Vx_Hx_Wx);
59	/* Opcode VEX.0F38 0x08 - invalid. */
60	/** Opcode VEX.66.0F38 0x08. */
61	FNIEMOP_STUB(iemOp_vpsignb_Vx_Hx_Wx);
62	/* Opcode VEX.0F38 0x09 - invalid. */
63	/** Opcode VEX.66.0F38 0x09. */
64	FNIEMOP_STUB(iemOp_vpsignw_Vx_Hx_Wx);
65	/* Opcode VEX.0F38 0x0a - invalid. */
66	/** Opcode VEX.66.0F38 0x0a. */
67	FNIEMOP_STUB(iemOp_vpsignd_Vx_Hx_Wx);
68	/* Opcode VEX.0F38 0x0b - invalid. */
69	/** Opcode VEX.66.0F38 0x0b. */
70	FNIEMOP_STUB(iemOp_vpmulhrsw_Vx_Hx_Wx);
71	/* Opcode VEX.0F38 0x0c - invalid. */
72	/** Opcode VEX.66.0F38 0x0c. */
73	FNIEMOP_STUB(iemOp_vpermilps_Vx_Hx_Wx);
74	/* Opcode VEX.0F38 0x0d - invalid. */
75	/** Opcode VEX.66.0F38 0x0d. */
76	FNIEMOP_STUB(iemOp_vpermilpd_Vx_Hx_Wx);
77	/* Opcode VEX.0F38 0x0e - invalid. */
78	/** Opcode VEX.66.0F38 0x0e. */
79	FNIEMOP_STUB(iemOp_vtestps_Vx_Wx);
80	/* Opcode VEX.0F38 0x0f - invalid. */
81	/** Opcode VEX.66.0F38 0x0f. */
82	FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx);
83
84
85	/* Opcode VEX.0F38 0x10 - invalid */
86	/* Opcode VEX.66.0F38 0x10 - invalid (legacy only). */
87	/* Opcode VEX.0F38 0x11 - invalid */
88	/* Opcode VEX.66.0F38 0x11 - invalid */
89	/* Opcode VEX.0F38 0x12 - invalid */
90	/* Opcode VEX.66.0F38 0x12 - invalid */
91	/* Opcode VEX.0F38 0x13 - invalid */
92	/* Opcode VEX.66.0F38 0x13 - invalid (vex only). */
93	/* Opcode VEX.0F38 0x14 - invalid */
94	/* Opcode VEX.66.0F38 0x14 - invalid (legacy only). */
95	/* Opcode VEX.0F38 0x15 - invalid */
96	/* Opcode VEX.66.0F38 0x15 - invalid (legacy only). */
97	/* Opcode VEX.0F38 0x16 - invalid */
98	/** Opcode VEX.66.0F38 0x16. */
99	FNIEMOP_STUB(iemOp_vpermps_Vqq_Hqq_Wqq);
100	/* Opcode VEX.0F38 0x17 - invalid */
101
102
103	/** Opcode VEX.66.0F38 0x17 - invalid */
104	FNIEMOP_DEF(iemOp_vptest_Vx_Wx)
105	{
106	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
107	if (IEM_IS_MODRM_REG_MODE(bRm))
108	{
109	/*
110	* Register, register.
111	*/
112	if (pVCpu->iem.s.uVexLength)
113	{
114	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
115	IEM_MC_BEGIN(3, 2);
116	IEM_MC_LOCAL(RTUINT256U, uSrc1);
117	IEM_MC_LOCAL(RTUINT256U, uSrc2);
118	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
119	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
120	IEM_MC_ARG(uint32_t *, pEFlags, 2);
121	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
122	IEM_MC_PREPARE_AVX_USAGE();
123	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
124	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
125	IEM_MC_REF_EFLAGS(pEFlags);
126	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
127	puSrc1, puSrc2, pEFlags);
128	IEM_MC_ADVANCE_RIP();
129	IEM_MC_END();
130	}
131	else
132	{
133	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
134	IEM_MC_BEGIN(3, 0);
135	IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
136	IEM_MC_ARG(PCRTUINT128U, puSrc2, 1);
137	IEM_MC_ARG(uint32_t *, pEFlags, 2);
138	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
139	IEM_MC_PREPARE_AVX_USAGE();
140	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
141	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
142	IEM_MC_REF_EFLAGS(pEFlags);
143	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
144	IEM_MC_ADVANCE_RIP();
145	IEM_MC_END();
146	}
147	}
148	else
149	{
150	/*
151	* Register, memory.
152	*/
153	if (pVCpu->iem.s.uVexLength)
154	{
155	IEM_MC_BEGIN(3, 3);
156	IEM_MC_LOCAL(RTUINT256U, uSrc1);
157	IEM_MC_LOCAL(RTUINT256U, uSrc2);
158	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
159	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
160	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
161	IEM_MC_ARG(uint32_t *, pEFlags, 2);
162
163	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
164	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
165	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
166	IEM_MC_PREPARE_AVX_USAGE();
167
168	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
169	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
170	IEM_MC_REF_EFLAGS(pEFlags);
171	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
172	puSrc1, puSrc2, pEFlags);
173
174	IEM_MC_ADVANCE_RIP();
175	IEM_MC_END();
176	}
177	else
178	{
179	IEM_MC_BEGIN(3, 2);
180	IEM_MC_LOCAL(RTUINT128U, uSrc2);
181	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
182	IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
183	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1);
184	IEM_MC_ARG(uint32_t *, pEFlags, 2);
185
186	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
187	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
188	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
189	IEM_MC_PREPARE_AVX_USAGE();
190
191	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
192	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
193	IEM_MC_REF_EFLAGS(pEFlags);
194	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
195
196	IEM_MC_ADVANCE_RIP();
197	IEM_MC_END();
198	}
199	}
200	return VINF_SUCCESS;
201
202	}
203
204
205	/* Opcode VEX.0F38 0x18 - invalid */
206	/** Opcode VEX.66.0F38 0x18. */
207	FNIEMOP_STUB(iemOp_vbroadcastss_Vx_Wd);
208	/* Opcode VEX.0F38 0x19 - invalid */
209	/** Opcode VEX.66.0F38 0x19. */
210	FNIEMOP_STUB(iemOp_vbroadcastsd_Vqq_Wq);
211	/* Opcode VEX.0F38 0x1a - invalid */
212	/** Opcode VEX.66.0F38 0x1a. */
213	FNIEMOP_STUB(iemOp_vbroadcastf128_Vqq_Mdq);
214	/* Opcode VEX.0F38 0x1b - invalid */
215	/* Opcode VEX.66.0F38 0x1b - invalid */
216	/* Opcode VEX.0F38 0x1c - invalid. */
217	/** Opcode VEX.66.0F38 0x1c. */
218	FNIEMOP_STUB(iemOp_vpabsb_Vx_Wx);
219	/* Opcode VEX.0F38 0x1d - invalid. */
220	/** Opcode VEX.66.0F38 0x1d. */
221	FNIEMOP_STUB(iemOp_vpabsw_Vx_Wx);
222	/* Opcode VEX.0F38 0x1e - invalid. */
223	/** Opcode VEX.66.0F38 0x1e. */
224	FNIEMOP_STUB(iemOp_vpabsd_Vx_Wx);
225	/* Opcode VEX.0F38 0x1f - invalid */
226	/* Opcode VEX.66.0F38 0x1f - invalid */
227
228
229	/** Opcode VEX.66.0F38 0x20. */
230	FNIEMOP_STUB(iemOp_vpmovsxbw_Vx_UxMq);
231	/** Opcode VEX.66.0F38 0x21. */
232	FNIEMOP_STUB(iemOp_vpmovsxbd_Vx_UxMd);
233	/** Opcode VEX.66.0F38 0x22. */
234	FNIEMOP_STUB(iemOp_vpmovsxbq_Vx_UxMw);
235	/** Opcode VEX.66.0F38 0x23. */
236	FNIEMOP_STUB(iemOp_vpmovsxwd_Vx_UxMq);
237	/** Opcode VEX.66.0F38 0x24. */
238	FNIEMOP_STUB(iemOp_vpmovsxwq_Vx_UxMd);
239	/** Opcode VEX.66.0F38 0x25. */
240	FNIEMOP_STUB(iemOp_vpmovsxdq_Vx_UxMq);
241	/* Opcode VEX.66.0F38 0x26 - invalid */
242	/* Opcode VEX.66.0F38 0x27 - invalid */
243	/** Opcode VEX.66.0F38 0x28. */
244	FNIEMOP_STUB(iemOp_vpmuldq_Vx_Hx_Wx);
245
246
247	/** Opcode VEX.66.0F38 0x29. */
248	FNIEMOP_DEF(iemOp_vpcmpeqq_Vx_Hx_Wx)
249	{
250	IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQQ, vpcmpeqq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
251	IEMOPMEDIAF3_INIT_VARS(vpcmpeqq);
252	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
253	}
254
255
256	FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
257	{
258	Assert(pVCpu->iem.s.uVexLength <= 1);
259	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
260	if (IEM_IS_MODRM_MEM_MODE(bRm))
261	{
262	if (pVCpu->iem.s.uVexLength == 0)
263	{
264	/**
265	* @opcode 0x2a
266	* @opcodesub !11 mr/reg vex.l=0
267	* @oppfx 0x66
268	* @opcpuid avx
269	* @opgroup og_avx_cachect
270	* @opxcpttype 1
271	* @optest op1=-1 op2=2 -> op1=2
272	* @optest op1=0 op2=-42 -> op1=-42
273	*/
274	/* 128-bit: Memory, register. */
275	IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
276	DISOPTYPE_HARMLESS \| DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
277	IEM_MC_BEGIN(0, 2);
278	IEM_MC_LOCAL(RTUINT128U, uSrc);
279	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
280
281	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
282	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
283	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
284	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
285
286	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
287	IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
288
289	IEM_MC_ADVANCE_RIP();
290	IEM_MC_END();
291	}
292	else
293	{
294	/**
295	* @opdone
296	* @opcode 0x2a
297	* @opcodesub !11 mr/reg vex.l=1
298	* @oppfx 0x66
299	* @opcpuid avx2
300	* @opgroup og_avx2_cachect
301	* @opxcpttype 1
302	* @optest op1=-1 op2=2 -> op1=2
303	* @optest op1=0 op2=-42 -> op1=-42
304	*/
305	/* 256-bit: Memory, register. */
306	IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
307	DISOPTYPE_HARMLESS \| DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
308	IEM_MC_BEGIN(0, 2);
309	IEM_MC_LOCAL(RTUINT256U, uSrc);
310	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
311
312	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
313	IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
314	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
315	IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
316
317	IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
318	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
319
320	IEM_MC_ADVANCE_RIP();
321	IEM_MC_END();
322	}
323	return VINF_SUCCESS;
324	}
325
326	/**
327	* @opdone
328	* @opmnemonic udvex660f382arg
329	* @opcode 0x2a
330	* @opcodesub 11 mr/reg
331	* @oppfx 0x66
332	* @opunused immediate
333	* @opcpuid avx
334	* @optest ->
335	*/
336	return IEMOP_RAISE_INVALID_OPCODE();
337	}
338
339
340	/** Opcode VEX.66.0F38 0x2b. */
341	FNIEMOP_DEF(iemOp_vpackusdw_Vx_Hx_Wx)
342	{
343	IEMOP_MNEMONIC3(VEX_RVM, VPACKUSDW, vpackusdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS \| DISOPTYPE_AVX, 0);
344	IEMOPMEDIAOPTF3_INIT_VARS( vpackusdw);
345	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
346	}
347
348
349	/** Opcode VEX.66.0F38 0x2c. */
350	FNIEMOP_STUB(iemOp_vmaskmovps_Vx_Hx_Mx);
351	/** Opcode VEX.66.0F38 0x2d. */
352	FNIEMOP_STUB(iemOp_vmaskmovpd_Vx_Hx_Mx);
353	/** Opcode VEX.66.0F38 0x2e. */
354	FNIEMOP_STUB(iemOp_vmaskmovps_Mx_Hx_Vx);
355	/** Opcode VEX.66.0F38 0x2f. */
356	FNIEMOP_STUB(iemOp_vmaskmovpd_Mx_Hx_Vx);
357
358	/** Opcode VEX.66.0F38 0x30. */
359	FNIEMOP_STUB(iemOp_vpmovzxbw_Vx_UxMq);
360	/** Opcode VEX.66.0F38 0x31. */
361	FNIEMOP_STUB(iemOp_vpmovzxbd_Vx_UxMd);
362	/** Opcode VEX.66.0F38 0x32. */
363	FNIEMOP_STUB(iemOp_vpmovzxbq_Vx_UxMw);
364	/** Opcode VEX.66.0F38 0x33. */
365	FNIEMOP_STUB(iemOp_vpmovzxwd_Vx_UxMq);
366	/** Opcode VEX.66.0F38 0x34. */
367	FNIEMOP_STUB(iemOp_vpmovzxwq_Vx_UxMd);
368	/** Opcode VEX.66.0F38 0x35. */
369	FNIEMOP_STUB(iemOp_vpmovzxdq_Vx_UxMq);
370	/* Opcode VEX.66.0F38 0x36. */
371	FNIEMOP_STUB(iemOp_vpermd_Vqq_Hqq_Wqq);
372
373
374	/** Opcode VEX.66.0F38 0x37. */
375	FNIEMOP_DEF(iemOp_vpcmpgtq_Vx_Hx_Wx)
376	{
377	IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTQ, vpcmpgtq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
378	IEMOPMEDIAF3_INIT_VARS(vpcmpgtq);
379	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
380	}
381
382
383	/** Opcode VEX.66.0F38 0x38. */
384	FNIEMOP_STUB(iemOp_vpminsb_Vx_Hx_Wx);
385	/** Opcode VEX.66.0F38 0x39. */
386	FNIEMOP_STUB(iemOp_vpminsd_Vx_Hx_Wx);
387	/** Opcode VEX.66.0F38 0x3a. */
388	FNIEMOP_STUB(iemOp_vpminuw_Vx_Hx_Wx);
389	/** Opcode VEX.66.0F38 0x3b. */
390	FNIEMOP_STUB(iemOp_vpminud_Vx_Hx_Wx);
391	/** Opcode VEX.66.0F38 0x3c. */
392	FNIEMOP_STUB(iemOp_vpmaxsb_Vx_Hx_Wx);
393	/** Opcode VEX.66.0F38 0x3d. */
394	FNIEMOP_STUB(iemOp_vpmaxsd_Vx_Hx_Wx);
395
396
397	/** Opcode VEX.66.0F38 0x3e. */
398	FNIEMOP_DEF(iemOp_vpmaxuw_Vx_Hx_Wx)
399	{
400	IEMOP_MNEMONIC3(VEX_RVM, VPMAXUW, vpmaxuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
401	IEMOPMEDIAF3_INIT_VARS(vpmaxuw);
402	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
403	}
404
405
406	/** Opcode VEX.66.0F38 0x3f. */
407	FNIEMOP_DEF(iemOp_vpmaxud_Vx_Hx_Wx)
408	{
409	IEMOP_MNEMONIC3(VEX_RVM, VPMAXUD, vpmaxud, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
410	IEMOPMEDIAF3_INIT_VARS(vpmaxud);
411	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
412	}
413
414
415	/** Opcode VEX.66.0F38 0x40. */
416	FNIEMOP_STUB(iemOp_vpmulld_Vx_Hx_Wx);
417	/** Opcode VEX.66.0F38 0x41. */
418	FNIEMOP_STUB(iemOp_vphminposuw_Vdq_Wdq);
419	/* Opcode VEX.66.0F38 0x42 - invalid. */
420	/* Opcode VEX.66.0F38 0x43 - invalid. */
421	/* Opcode VEX.66.0F38 0x44 - invalid. */
422	/** Opcode VEX.66.0F38 0x45. */
423	FNIEMOP_STUB(iemOp_vpsrlvd_q_Vx_Hx_Wx);
424	/** Opcode VEX.66.0F38 0x46. */
425	FNIEMOP_STUB(iemOp_vsravd_Vx_Hx_Wx);
426	/** Opcode VEX.66.0F38 0x47. */
427	FNIEMOP_STUB(iemOp_vpsllvd_q_Vx_Hx_Wx);
428	/* Opcode VEX.66.0F38 0x48 - invalid. */
429	/* Opcode VEX.66.0F38 0x49 - invalid. */
430	/* Opcode VEX.66.0F38 0x4a - invalid. */
431	/* Opcode VEX.66.0F38 0x4b - invalid. */
432	/* Opcode VEX.66.0F38 0x4c - invalid. */
433	/* Opcode VEX.66.0F38 0x4d - invalid. */
434	/* Opcode VEX.66.0F38 0x4e - invalid. */
435	/* Opcode VEX.66.0F38 0x4f - invalid. */
436
437	/* Opcode VEX.66.0F38 0x50 - invalid. */
438	/* Opcode VEX.66.0F38 0x51 - invalid. */
439	/* Opcode VEX.66.0F38 0x52 - invalid. */
440	/* Opcode VEX.66.0F38 0x53 - invalid. */
441	/* Opcode VEX.66.0F38 0x54 - invalid. */
442	/* Opcode VEX.66.0F38 0x55 - invalid. */
443	/* Opcode VEX.66.0F38 0x56 - invalid. */
444	/* Opcode VEX.66.0F38 0x57 - invalid. */
445	/** Opcode VEX.66.0F38 0x58. */
446	FNIEMOP_STUB(iemOp_vpbroadcastd_Vx_Wx);
447	/** Opcode VEX.66.0F38 0x59. */
448	FNIEMOP_STUB(iemOp_vpbroadcastq_Vx_Wx);
449	/** Opcode VEX.66.0F38 0x5a. */
450	FNIEMOP_STUB(iemOp_vbroadcasti128_Vqq_Mdq);
451	/* Opcode VEX.66.0F38 0x5b - invalid. */
452	/* Opcode VEX.66.0F38 0x5c - invalid. */
453	/* Opcode VEX.66.0F38 0x5d - invalid. */
454	/* Opcode VEX.66.0F38 0x5e - invalid. */
455	/* Opcode VEX.66.0F38 0x5f - invalid. */
456
457	/* Opcode VEX.66.0F38 0x60 - invalid. */
458	/* Opcode VEX.66.0F38 0x61 - invalid. */
459	/* Opcode VEX.66.0F38 0x62 - invalid. */
460	/* Opcode VEX.66.0F38 0x63 - invalid. */
461	/* Opcode VEX.66.0F38 0x64 - invalid. */
462	/* Opcode VEX.66.0F38 0x65 - invalid. */
463	/* Opcode VEX.66.0F38 0x66 - invalid. */
464	/* Opcode VEX.66.0F38 0x67 - invalid. */
465	/* Opcode VEX.66.0F38 0x68 - invalid. */
466	/* Opcode VEX.66.0F38 0x69 - invalid. */
467	/* Opcode VEX.66.0F38 0x6a - invalid. */
468	/* Opcode VEX.66.0F38 0x6b - invalid. */
469	/* Opcode VEX.66.0F38 0x6c - invalid. */
470	/* Opcode VEX.66.0F38 0x6d - invalid. */
471	/* Opcode VEX.66.0F38 0x6e - invalid. */
472	/* Opcode VEX.66.0F38 0x6f - invalid. */
473
474	/* Opcode VEX.66.0F38 0x70 - invalid. */
475	/* Opcode VEX.66.0F38 0x71 - invalid. */
476	/* Opcode VEX.66.0F38 0x72 - invalid. */
477	/* Opcode VEX.66.0F38 0x73 - invalid. */
478	/* Opcode VEX.66.0F38 0x74 - invalid. */
479	/* Opcode VEX.66.0F38 0x75 - invalid. */
480	/* Opcode VEX.66.0F38 0x76 - invalid. */
481	/* Opcode VEX.66.0F38 0x77 - invalid. */
482	/** Opcode VEX.66.0F38 0x78. */
483	FNIEMOP_STUB(iemOp_vpboardcastb_Vx_Wx);
484	/** Opcode VEX.66.0F38 0x79. */
485	FNIEMOP_STUB(iemOp_vpboardcastw_Vx_Wx);
486	/* Opcode VEX.66.0F38 0x7a - invalid. */
487	/* Opcode VEX.66.0F38 0x7b - invalid. */
488	/* Opcode VEX.66.0F38 0x7c - invalid. */
489	/* Opcode VEX.66.0F38 0x7d - invalid. */
490	/* Opcode VEX.66.0F38 0x7e - invalid. */
491	/* Opcode VEX.66.0F38 0x7f - invalid. */
492
493	/* Opcode VEX.66.0F38 0x80 - invalid (legacy only). */
494	/* Opcode VEX.66.0F38 0x81 - invalid (legacy only). */
495	/* Opcode VEX.66.0F38 0x82 - invalid (legacy only). */
496	/* Opcode VEX.66.0F38 0x83 - invalid. */
497	/* Opcode VEX.66.0F38 0x84 - invalid. */
498	/* Opcode VEX.66.0F38 0x85 - invalid. */
499	/* Opcode VEX.66.0F38 0x86 - invalid. */
500	/* Opcode VEX.66.0F38 0x87 - invalid. */
501	/* Opcode VEX.66.0F38 0x88 - invalid. */
502	/* Opcode VEX.66.0F38 0x89 - invalid. */
503	/* Opcode VEX.66.0F38 0x8a - invalid. */
504	/* Opcode VEX.66.0F38 0x8b - invalid. */
505	/** Opcode VEX.66.0F38 0x8c. */
506	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Vx_Hx_Mx);
507	/* Opcode VEX.66.0F38 0x8d - invalid. */
508	/** Opcode VEX.66.0F38 0x8e. */
509	FNIEMOP_STUB(iemOp_vpmaskmovd_q_Mx_Vx_Hx);
510	/* Opcode VEX.66.0F38 0x8f - invalid. */
511
512	/** Opcode VEX.66.0F38 0x90 (vex only). */
513	FNIEMOP_STUB(iemOp_vgatherdd_q_Vx_Hx_Wx);
514	/** Opcode VEX.66.0F38 0x91 (vex only). */
515	FNIEMOP_STUB(iemOp_vgatherqd_q_Vx_Hx_Wx);
516	/** Opcode VEX.66.0F38 0x92 (vex only). */
517	FNIEMOP_STUB(iemOp_vgatherdps_d_Vx_Hx_Wx);
518	/** Opcode VEX.66.0F38 0x93 (vex only). */
519	FNIEMOP_STUB(iemOp_vgatherqps_d_Vx_Hx_Wx);
520	/* Opcode VEX.66.0F38 0x94 - invalid. */
521	/* Opcode VEX.66.0F38 0x95 - invalid. */
522	/** Opcode VEX.66.0F38 0x96 (vex only). */
523	FNIEMOP_STUB(iemOp_vfmaddsub132ps_q_Vx_Hx_Wx);
524	/** Opcode VEX.66.0F38 0x97 (vex only). */
525	FNIEMOP_STUB(iemOp_vfmsubadd132ps_d_Vx_Hx_Wx);
526	/** Opcode VEX.66.0F38 0x98 (vex only). */
527	FNIEMOP_STUB(iemOp_vfmadd132ps_d_Vx_Hx_Wx);
528	/** Opcode VEX.66.0F38 0x99 (vex only). */
529	FNIEMOP_STUB(iemOp_vfmadd132ss_d_Vx_Hx_Wx);
530	/** Opcode VEX.66.0F38 0x9a (vex only). */
531	FNIEMOP_STUB(iemOp_vfmsub132ps_d_Vx_Hx_Wx);
532	/** Opcode VEX.66.0F38 0x9b (vex only). */
533	FNIEMOP_STUB(iemOp_vfmsub132ss_d_Vx_Hx_Wx);
534	/** Opcode VEX.66.0F38 0x9c (vex only). */
535	FNIEMOP_STUB(iemOp_vfnmadd132ps_d_Vx_Hx_Wx);
536	/** Opcode VEX.66.0F38 0x9d (vex only). */
537	FNIEMOP_STUB(iemOp_vfnmadd132ss_d_Vx_Hx_Wx);
538	/** Opcode VEX.66.0F38 0x9e (vex only). */
539	FNIEMOP_STUB(iemOp_vfnmsub132ps_d_Vx_Hx_Wx);
540	/** Opcode VEX.66.0F38 0x9f (vex only). */
541	FNIEMOP_STUB(iemOp_vfnmsub132ss_d_Vx_Hx_Wx);
542
543	/* Opcode VEX.66.0F38 0xa0 - invalid. */
544	/* Opcode VEX.66.0F38 0xa1 - invalid. */
545	/* Opcode VEX.66.0F38 0xa2 - invalid. */
546	/* Opcode VEX.66.0F38 0xa3 - invalid. */
547	/* Opcode VEX.66.0F38 0xa4 - invalid. */
548	/* Opcode VEX.66.0F38 0xa5 - invalid. */
549	/** Opcode VEX.66.0F38 0xa6 (vex only). */
550	FNIEMOP_STUB(iemOp_vfmaddsub213ps_d_Vx_Hx_Wx);
551	/** Opcode VEX.66.0F38 0xa7 (vex only). */
552	FNIEMOP_STUB(iemOp_vfmsubadd213ps_d_Vx_Hx_Wx);
553	/** Opcode VEX.66.0F38 0xa8 (vex only). */
554	FNIEMOP_STUB(iemOp_vfmadd213ps_d_Vx_Hx_Wx);
555	/** Opcode VEX.66.0F38 0xa9 (vex only). */
556	FNIEMOP_STUB(iemOp_vfmadd213ss_d_Vx_Hx_Wx);
557	/** Opcode VEX.66.0F38 0xaa (vex only). */
558	FNIEMOP_STUB(iemOp_vfmsub213ps_d_Vx_Hx_Wx);
559	/** Opcode VEX.66.0F38 0xab (vex only). */
560	FNIEMOP_STUB(iemOp_vfmsub213ss_d_Vx_Hx_Wx);
561	/** Opcode VEX.66.0F38 0xac (vex only). */
562	FNIEMOP_STUB(iemOp_vfnmadd213ps_d_Vx_Hx_Wx);
563	/** Opcode VEX.66.0F38 0xad (vex only). */
564	FNIEMOP_STUB(iemOp_vfnmadd213ss_d_Vx_Hx_Wx);
565	/** Opcode VEX.66.0F38 0xae (vex only). */
566	FNIEMOP_STUB(iemOp_vfnmsub213ps_d_Vx_Hx_Wx);
567	/** Opcode VEX.66.0F38 0xaf (vex only). */
568	FNIEMOP_STUB(iemOp_vfnmsub213ss_d_Vx_Hx_Wx);
569
570	/* Opcode VEX.66.0F38 0xb0 - invalid. */
571	/* Opcode VEX.66.0F38 0xb1 - invalid. */
572	/* Opcode VEX.66.0F38 0xb2 - invalid. */
573	/* Opcode VEX.66.0F38 0xb3 - invalid. */
574	/* Opcode VEX.66.0F38 0xb4 - invalid. */
575	/* Opcode VEX.66.0F38 0xb5 - invalid. */
576	/** Opcode VEX.66.0F38 0xb6 (vex only). */
577	FNIEMOP_STUB(iemOp_vfmaddsub231ps_d_Vx_Hx_Wx);
578	/** Opcode VEX.66.0F38 0xb7 (vex only). */
579	FNIEMOP_STUB(iemOp_vfmsubadd231ps_d_Vx_Hx_Wx);
580	/** Opcode VEX.66.0F38 0xb8 (vex only). */
581	FNIEMOP_STUB(iemOp_vfmadd231ps_d_Vx_Hx_Wx);
582	/** Opcode VEX.66.0F38 0xb9 (vex only). */
583	FNIEMOP_STUB(iemOp_vfmadd231ss_d_Vx_Hx_Wx);
584	/** Opcode VEX.66.0F38 0xba (vex only). */
585	FNIEMOP_STUB(iemOp_vfmsub231ps_d_Vx_Hx_Wx);
586	/** Opcode VEX.66.0F38 0xbb (vex only). */
587	FNIEMOP_STUB(iemOp_vfmsub231ss_d_Vx_Hx_Wx);
588	/** Opcode VEX.66.0F38 0xbc (vex only). */
589	FNIEMOP_STUB(iemOp_vfnmadd231ps_d_Vx_Hx_Wx);
590	/** Opcode VEX.66.0F38 0xbd (vex only). */
591	FNIEMOP_STUB(iemOp_vfnmadd231ss_d_Vx_Hx_Wx);
592	/** Opcode VEX.66.0F38 0xbe (vex only). */
593	FNIEMOP_STUB(iemOp_vfnmsub231ps_d_Vx_Hx_Wx);
594	/** Opcode VEX.66.0F38 0xbf (vex only). */
595	FNIEMOP_STUB(iemOp_vfnmsub231ss_d_Vx_Hx_Wx);
596
597	/* Opcode VEX.0F38 0xc0 - invalid. */
598	/* Opcode VEX.66.0F38 0xc0 - invalid. */
599	/* Opcode VEX.0F38 0xc1 - invalid. */
600	/* Opcode VEX.66.0F38 0xc1 - invalid. */
601	/* Opcode VEX.0F38 0xc2 - invalid. */
602	/* Opcode VEX.66.0F38 0xc2 - invalid. */
603	/* Opcode VEX.0F38 0xc3 - invalid. */
604	/* Opcode VEX.66.0F38 0xc3 - invalid. */
605	/* Opcode VEX.0F38 0xc4 - invalid. */
606	/* Opcode VEX.66.0F38 0xc4 - invalid. */
607	/* Opcode VEX.0F38 0xc5 - invalid. */
608	/* Opcode VEX.66.0F38 0xc5 - invalid. */
609	/* Opcode VEX.0F38 0xc6 - invalid. */
610	/* Opcode VEX.66.0F38 0xc6 - invalid. */
611	/* Opcode VEX.0F38 0xc7 - invalid. */
612	/* Opcode VEX.66.0F38 0xc7 - invalid. */
613	/** Opcode VEX.0F38 0xc8. */
614	FNIEMOP_STUB(iemOp_vsha1nexte_Vdq_Wdq);
615	/* Opcode VEX.66.0F38 0xc8 - invalid. */
616	/** Opcode VEX.0F38 0xc9. */
617	FNIEMOP_STUB(iemOp_vsha1msg1_Vdq_Wdq);
618	/* Opcode VEX.66.0F38 0xc9 - invalid. */
619	/** Opcode VEX.0F38 0xca. */
620	FNIEMOP_STUB(iemOp_vsha1msg2_Vdq_Wdq);
621	/* Opcode VEX.66.0F38 0xca - invalid. */
622	/** Opcode VEX.0F38 0xcb. */
623	FNIEMOP_STUB(iemOp_vsha256rnds2_Vdq_Wdq);
624	/* Opcode VEX.66.0F38 0xcb - invalid. */
625	/** Opcode VEX.0F38 0xcc. */
626	FNIEMOP_STUB(iemOp_vsha256msg1_Vdq_Wdq);
627	/* Opcode VEX.66.0F38 0xcc - invalid. */
628	/** Opcode VEX.0F38 0xcd. */
629	FNIEMOP_STUB(iemOp_vsha256msg2_Vdq_Wdq);
630	/* Opcode VEX.66.0F38 0xcd - invalid. */
631	/* Opcode VEX.0F38 0xce - invalid. */
632	/* Opcode VEX.66.0F38 0xce - invalid. */
633	/* Opcode VEX.0F38 0xcf - invalid. */
634	/* Opcode VEX.66.0F38 0xcf - invalid. */
635
636	/* Opcode VEX.66.0F38 0xd0 - invalid. */
637	/* Opcode VEX.66.0F38 0xd1 - invalid. */
638	/* Opcode VEX.66.0F38 0xd2 - invalid. */
639	/* Opcode VEX.66.0F38 0xd3 - invalid. */
640	/* Opcode VEX.66.0F38 0xd4 - invalid. */
641	/* Opcode VEX.66.0F38 0xd5 - invalid. */
642	/* Opcode VEX.66.0F38 0xd6 - invalid. */
643	/* Opcode VEX.66.0F38 0xd7 - invalid. */
644	/* Opcode VEX.66.0F38 0xd8 - invalid. */
645	/* Opcode VEX.66.0F38 0xd9 - invalid. */
646	/* Opcode VEX.66.0F38 0xda - invalid. */
647	/** Opcode VEX.66.0F38 0xdb. */
648	FNIEMOP_STUB(iemOp_vaesimc_Vdq_Wdq);
649	/** Opcode VEX.66.0F38 0xdc. */
650	FNIEMOP_STUB(iemOp_vaesenc_Vdq_Wdq);
651	/** Opcode VEX.66.0F38 0xdd. */
652	FNIEMOP_STUB(iemOp_vaesenclast_Vdq_Wdq);
653	/** Opcode VEX.66.0F38 0xde. */
654	FNIEMOP_STUB(iemOp_vaesdec_Vdq_Wdq);
655	/** Opcode VEX.66.0F38 0xdf. */
656	FNIEMOP_STUB(iemOp_vaesdeclast_Vdq_Wdq);
657
658	/* Opcode VEX.66.0F38 0xe0 - invalid. */
659	/* Opcode VEX.66.0F38 0xe1 - invalid. */
660	/* Opcode VEX.66.0F38 0xe2 - invalid. */
661	/* Opcode VEX.66.0F38 0xe3 - invalid. */
662	/* Opcode VEX.66.0F38 0xe4 - invalid. */
663	/* Opcode VEX.66.0F38 0xe5 - invalid. */
664	/* Opcode VEX.66.0F38 0xe6 - invalid. */
665	/* Opcode VEX.66.0F38 0xe7 - invalid. */
666	/* Opcode VEX.66.0F38 0xe8 - invalid. */
667	/* Opcode VEX.66.0F38 0xe9 - invalid. */
668	/* Opcode VEX.66.0F38 0xea - invalid. */
669	/* Opcode VEX.66.0F38 0xeb - invalid. */
670	/* Opcode VEX.66.0F38 0xec - invalid. */
671	/* Opcode VEX.66.0F38 0xed - invalid. */
672	/* Opcode VEX.66.0F38 0xee - invalid. */
673	/* Opcode VEX.66.0F38 0xef - invalid. */
674
675
676	/* Opcode VEX.0F38 0xf0 - invalid (legacy only). */
677	/* Opcode VEX.66.0F38 0xf0 - invalid (legacy only). */
678	/* Opcode VEX.F3.0F38 0xf0 - invalid. */
679	/* Opcode VEX.F2.0F38 0xf0 - invalid (legacy only). */
680
681	/* Opcode VEX.0F38 0xf1 - invalid (legacy only). */
682	/* Opcode VEX.66.0F38 0xf1 - invalid (legacy only). */
683	/* Opcode VEX.F3.0F38 0xf1 - invalid. */
684	/* Opcode VEX.F2.0F38 0xf1 - invalid (legacy only). */
685
686	/** Opcode VEX.0F38 0xf2 - ANDN (vex only). */
687	FNIEMOP_DEF(iemOp_andn_Gy_By_Ey)
688	{
689	IEMOP_MNEMONIC3(VEX_RVM, ANDN, andn, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
690	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1)
691	return iemOp_InvalidNeedRM(pVCpu);
692	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF);
693	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
694	if (IEM_IS_MODRM_REG_MODE(bRm))
695	{
696	/*
697	* Register, register.
698	*/
699	IEMOP_HLP_DONE_VEX_DECODING_L0();
700	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
701	{
702	IEM_MC_BEGIN(4, 0);
703	IEM_MC_ARG(uint64_t *, pDst, 0);
704	IEM_MC_ARG(uint64_t, uSrc1, 1);
705	IEM_MC_ARG(uint64_t, uSrc2, 2);
706	IEM_MC_ARG(uint32_t *, pEFlags, 3);
707	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
708	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
709	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
710	IEM_MC_REF_EFLAGS(pEFlags);
711	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
712	pDst, uSrc1, uSrc2, pEFlags);
713	IEM_MC_ADVANCE_RIP();
714	IEM_MC_END();
715	}
716	else
717	{
718	IEM_MC_BEGIN(4, 0);
719	IEM_MC_ARG(uint32_t *, pDst, 0);
720	IEM_MC_ARG(uint32_t, uSrc1, 1);
721	IEM_MC_ARG(uint32_t, uSrc2, 2);
722	IEM_MC_ARG(uint32_t *, pEFlags, 3);
723	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
724	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
725	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
726	IEM_MC_REF_EFLAGS(pEFlags);
727	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
728	pDst, uSrc1, uSrc2, pEFlags);
729	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
730	IEM_MC_ADVANCE_RIP();
731	IEM_MC_END();
732	}
733	}
734	else
735	{
736	/*
737	* Register, memory.
738	*/
739	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
740	{
741	IEM_MC_BEGIN(4, 1);
742	IEM_MC_ARG(uint64_t *, pDst, 0);
743	IEM_MC_ARG(uint64_t, uSrc1, 1);
744	IEM_MC_ARG(uint64_t, uSrc2, 2);
745	IEM_MC_ARG(uint32_t *, pEFlags, 3);
746	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
747	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
748	IEMOP_HLP_DONE_VEX_DECODING_L0();
749	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
750	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
751	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
752	IEM_MC_REF_EFLAGS(pEFlags);
753	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
754	pDst, uSrc1, uSrc2, pEFlags);
755	IEM_MC_ADVANCE_RIP();
756	IEM_MC_END();
757	}
758	else
759	{
760	IEM_MC_BEGIN(4, 1);
761	IEM_MC_ARG(uint32_t *, pDst, 0);
762	IEM_MC_ARG(uint32_t, uSrc1, 1);
763	IEM_MC_ARG(uint32_t, uSrc2, 2);
764	IEM_MC_ARG(uint32_t *, pEFlags, 3);
765	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
766	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
767	IEMOP_HLP_DONE_VEX_DECODING_L0();
768	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
769	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
770	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
771	IEM_MC_REF_EFLAGS(pEFlags);
772	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
773	pDst, uSrc1, uSrc2, pEFlags);
774	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
775	IEM_MC_ADVANCE_RIP();
776	IEM_MC_END();
777	}
778	}
779	return VINF_SUCCESS;
780	}
781
782	/* Opcode VEX.66.0F38 0xf2 - invalid. */
783	/* Opcode VEX.F3.0F38 0xf2 - invalid. */
784	/* Opcode VEX.F2.0F38 0xf2 - invalid. */
785
786
787	/* Opcode VEX.0F38 0xf3 - invalid. */
788	/* Opcode VEX.66.0F38 0xf3 - invalid. */
789
790	/* Opcode VEX.F3.0F38 0xf3 /0 - invalid. */
791
792	/** Body for the vex group 17 instructions. */
793	#define IEMOP_BODY_By_Ey(a_Instr) \
794	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1) \
795	return iemOp_InvalidWithRM(pVCpu, bRm); /* decode memory variant? */ \
796	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_PF); \
797	if (IEM_IS_MODRM_REG_MODE(bRm)) \
798	{ \
799	/* \
800	* Register, register. \
801	*/ \
802	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
803	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
804	{ \
805	IEM_MC_BEGIN(3, 0); \
806	IEM_MC_ARG(uint64_t *, pDst, 0); \
807	IEM_MC_ARG(uint64_t, uSrc, 1); \
808	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
809	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
810	IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
811	IEM_MC_REF_EFLAGS(pEFlags); \
812	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
813	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
814	IEM_MC_ADVANCE_RIP(); \
815	IEM_MC_END(); \
816	} \
817	else \
818	{ \
819	IEM_MC_BEGIN(3, 0); \
820	IEM_MC_ARG(uint32_t *, pDst, 0); \
821	IEM_MC_ARG(uint32_t, uSrc, 1); \
822	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
823	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
824	IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
825	IEM_MC_REF_EFLAGS(pEFlags); \
826	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
827	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
828	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
829	IEM_MC_ADVANCE_RIP(); \
830	IEM_MC_END(); \
831	} \
832	} \
833	else \
834	{ \
835	/* \
836	* Register, memory. \
837	*/ \
838	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
839	{ \
840	IEM_MC_BEGIN(3, 1); \
841	IEM_MC_ARG(uint64_t *, pDst, 0); \
842	IEM_MC_ARG(uint64_t, uSrc, 1); \
843	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
844	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
845	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
846	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
847	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
848	IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
849	IEM_MC_REF_EFLAGS(pEFlags); \
850	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
851	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
852	IEM_MC_ADVANCE_RIP(); \
853	IEM_MC_END(); \
854	} \
855	else \
856	{ \
857	IEM_MC_BEGIN(3, 1); \
858	IEM_MC_ARG(uint32_t *, pDst, 0); \
859	IEM_MC_ARG(uint32_t, uSrc, 1); \
860	IEM_MC_ARG(uint32_t *, pEFlags, 2); \
861	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
862	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
863	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
864	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
865	IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
866	IEM_MC_REF_EFLAGS(pEFlags); \
867	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
868	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
869	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
870	IEM_MC_ADVANCE_RIP(); \
871	IEM_MC_END(); \
872	} \
873	} \
874	return VINF_SUCCESS
875
876
877	/* Opcode VEX.F3.0F38 0xf3 /1. */
878	/** @opcode /1
879	* @opmaps vexgrp17 */
880	FNIEMOP_DEF_1(iemOp_VGrp17_blsr_By_Ey, uint8_t, bRm)
881	{
882	IEMOP_MNEMONIC2(VEX_VM, BLSR, blsr, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
883	IEMOP_BODY_By_Ey(blsr);
884	}
885
886
887	/* Opcode VEX.F3.0F38 0xf3 /2. */
888	/** @opcode /2
889	* @opmaps vexgrp17 */
890	FNIEMOP_DEF_1(iemOp_VGrp17_blsmsk_By_Ey, uint8_t, bRm)
891	{
892	IEMOP_MNEMONIC2(VEX_VM, BLSMSK, blsmsk, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
893	IEMOP_BODY_By_Ey(blsmsk);
894	}
895
896
897	/* Opcode VEX.F3.0F38 0xf3 /3. */
898	/** @opcode /3
899	* @opmaps vexgrp17 */
900	FNIEMOP_DEF_1(iemOp_VGrp17_blsi_By_Ey, uint8_t, bRm)
901	{
902	IEMOP_MNEMONIC2(VEX_VM, BLSI, blsi, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
903	IEMOP_BODY_By_Ey(blsi);
904	}
905
906
907	/* Opcode VEX.F3.0F38 0xf3 /4 - invalid. */
908	/* Opcode VEX.F3.0F38 0xf3 /5 - invalid. */
909	/* Opcode VEX.F3.0F38 0xf3 /6 - invalid. */
910	/* Opcode VEX.F3.0F38 0xf3 /7 - invalid. */
911
912	/**
913	* Group 17 jump table for the VEX.F3 variant.
914	*/
915	IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =
916	{
917	/* /0 */ iemOp_InvalidWithRM,
918	/* /1 */ iemOp_VGrp17_blsr_By_Ey,
919	/* /2 */ iemOp_VGrp17_blsmsk_By_Ey,
920	/* /3 */ iemOp_VGrp17_blsi_By_Ey,
921	/* /4 */ iemOp_InvalidWithRM,
922	/* /5 */ iemOp_InvalidWithRM,
923	/* /6 */ iemOp_InvalidWithRM,
924	/* /7 */ iemOp_InvalidWithRM
925	};
926	AssertCompile(RT_ELEMENTS(g_apfnVexGroup17_f3) == 8);
927
928	/** Opcode VEX.F3.0F38 0xf3 - invalid (vex only - group 17). */
929	FNIEMOP_DEF(iemOp_VGrp17_f3)
930	{
931	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
932	return FNIEMOP_CALL_1(g_apfnVexGroup17_f3[IEM_GET_MODRM_REG_8(bRm)], bRm);
933	}
934
935	/* Opcode VEX.F2.0F38 0xf3 - invalid (vex only - group 17). */
936
937
938	/* Opcode VEX.0F38 0xf4 - invalid. */
939	/* Opcode VEX.66.0F38 0xf4 - invalid. */
940	/* Opcode VEX.F3.0F38 0xf4 - invalid. */
941	/* Opcode VEX.F2.0F38 0xf4 - invalid. */
942
943	/** Body for BZHI, BEXTR, ++; assumes VEX.L must be 0. */
944	#define IEMOP_BODY_Gy_Ey_By(a_Instr, a_fFeatureMember, a_fUndefFlags) \
945	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
946	return iemOp_InvalidNeedRM(pVCpu); \
947	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
948	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
949	if (IEM_IS_MODRM_REG_MODE(bRm)) \
950	{ \
951	/* \
952	* Register, register. \
953	*/ \
954	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
955	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
956	{ \
957	IEM_MC_BEGIN(4, 0); \
958	IEM_MC_ARG(uint64_t *, pDst, 0); \
959	IEM_MC_ARG(uint64_t, uSrc1, 1); \
960	IEM_MC_ARG(uint64_t, uSrc2, 2); \
961	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
962	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
963	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
964	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
965	IEM_MC_REF_EFLAGS(pEFlags); \
966	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
967	iemAImpl_ ## a_Instr ## _u64_fallback), \
968	pDst, uSrc1, uSrc2, pEFlags); \
969	IEM_MC_ADVANCE_RIP(); \
970	IEM_MC_END(); \
971	} \
972	else \
973	{ \
974	IEM_MC_BEGIN(4, 0); \
975	IEM_MC_ARG(uint32_t *, pDst, 0); \
976	IEM_MC_ARG(uint32_t, uSrc1, 1); \
977	IEM_MC_ARG(uint32_t, uSrc2, 2); \
978	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
979	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
980	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
981	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
982	IEM_MC_REF_EFLAGS(pEFlags); \
983	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
984	iemAImpl_ ## a_Instr ## _u32_fallback), \
985	pDst, uSrc1, uSrc2, pEFlags); \
986	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
987	IEM_MC_ADVANCE_RIP(); \
988	IEM_MC_END(); \
989	} \
990	} \
991	else \
992	{ \
993	/* \
994	* Register, memory. \
995	*/ \
996	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
997	{ \
998	IEM_MC_BEGIN(4, 1); \
999	IEM_MC_ARG(uint64_t *, pDst, 0); \
1000	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1001	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1002	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1003	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1004	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1005	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1006	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1007	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1008	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1009	IEM_MC_REF_EFLAGS(pEFlags); \
1010	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1011	iemAImpl_ ## a_Instr ## _u64_fallback), \
1012	pDst, uSrc1, uSrc2, pEFlags); \
1013	IEM_MC_ADVANCE_RIP(); \
1014	IEM_MC_END(); \
1015	} \
1016	else \
1017	{ \
1018	IEM_MC_BEGIN(4, 1); \
1019	IEM_MC_ARG(uint32_t *, pDst, 0); \
1020	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1021	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1022	IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1023	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1024	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1025	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1026	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1027	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1028	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1029	IEM_MC_REF_EFLAGS(pEFlags); \
1030	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1031	iemAImpl_ ## a_Instr ## _u32_fallback), \
1032	pDst, uSrc1, uSrc2, pEFlags); \
1033	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1034	IEM_MC_ADVANCE_RIP(); \
1035	IEM_MC_END(); \
1036	} \
1037	} \
1038	return VINF_SUCCESS
1039
1040	/** Body for SARX, SHLX, SHRX; assumes VEX.L must be 0. */
1041	#define IEMOP_BODY_Gy_Ey_By_NoEflags(a_Instr, a_fFeatureMember, a_fUndefFlags) \
1042	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
1043	return iemOp_InvalidNeedRM(pVCpu); \
1044	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
1045	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1046	if (IEM_IS_MODRM_REG_MODE(bRm)) \
1047	{ \
1048	/* \
1049	* Register, register. \
1050	*/ \
1051	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1052	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1053	{ \
1054	IEM_MC_BEGIN(3, 0); \
1055	IEM_MC_ARG(uint64_t *, pDst, 0); \
1056	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1057	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1058	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1059	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1060	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1061	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1062	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1063	IEM_MC_ADVANCE_RIP(); \
1064	IEM_MC_END(); \
1065	} \
1066	else \
1067	{ \
1068	IEM_MC_BEGIN(3, 0); \
1069	IEM_MC_ARG(uint32_t *, pDst, 0); \
1070	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1071	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1072	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1073	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1074	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1075	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1076	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1077	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1078	IEM_MC_ADVANCE_RIP(); \
1079	IEM_MC_END(); \
1080	} \
1081	} \
1082	else \
1083	{ \
1084	/* \
1085	* Register, memory. \
1086	*/ \
1087	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1088	{ \
1089	IEM_MC_BEGIN(3, 1); \
1090	IEM_MC_ARG(uint64_t *, pDst, 0); \
1091	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1092	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1093	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1094	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1095	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1096	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1097	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1098	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1099	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1100	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1101	IEM_MC_ADVANCE_RIP(); \
1102	IEM_MC_END(); \
1103	} \
1104	else \
1105	{ \
1106	IEM_MC_BEGIN(3, 1); \
1107	IEM_MC_ARG(uint32_t *, pDst, 0); \
1108	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1109	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1110	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1111	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1112	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1113	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1114	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1115	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1116	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1117	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1118	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1119	IEM_MC_ADVANCE_RIP(); \
1120	IEM_MC_END(); \
1121	} \
1122	} \
1123	return VINF_SUCCESS
1124
1125	/** Opcode VEX.0F38 0xf5 (vex only). */
1126	FNIEMOP_DEF(iemOp_bzhi_Gy_Ey_By)
1127	{
1128	IEMOP_MNEMONIC3(VEX_RMV, BZHI, bzhi, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1129	IEMOP_BODY_Gy_Ey_By(bzhi, fBmi2, X86_EFL_AF \| X86_EFL_PF);
1130	}
1131
1132	/* Opcode VEX.66.0F38 0xf5 - invalid. */
1133
1134	/** Body for PDEP and PEXT (similar to ANDN, except no EFLAGS). */
1135	#define IEMOP_BODY_Gy_By_Ey_NoEflags(a_Instr, a_fFeatureMember) \
1136	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
1137	return iemOp_InvalidNeedRM(pVCpu); \
1138	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1139	if (IEM_IS_MODRM_REG_MODE(bRm)) \
1140	{ \
1141	/* \
1142	* Register, register. \
1143	*/ \
1144	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1145	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1146	{ \
1147	IEM_MC_BEGIN(3, 0); \
1148	IEM_MC_ARG(uint64_t *, pDst, 0); \
1149	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1150	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1151	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1152	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1153	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1154	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1155	iemAImpl_ ## a_Instr ## _u64, \
1156	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1157	IEM_MC_ADVANCE_RIP(); \
1158	IEM_MC_END(); \
1159	} \
1160	else \
1161	{ \
1162	IEM_MC_BEGIN(3, 0); \
1163	IEM_MC_ARG(uint32_t *, pDst, 0); \
1164	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1165	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1166	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1167	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1168	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1169	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1170	iemAImpl_ ## a_Instr ## _u32, \
1171	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1172	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1173	IEM_MC_ADVANCE_RIP(); \
1174	IEM_MC_END(); \
1175	} \
1176	} \
1177	else \
1178	{ \
1179	/* \
1180	* Register, memory. \
1181	*/ \
1182	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1183	{ \
1184	IEM_MC_BEGIN(3, 1); \
1185	IEM_MC_ARG(uint64_t *, pDst, 0); \
1186	IEM_MC_ARG(uint64_t, uSrc1, 1); \
1187	IEM_MC_ARG(uint64_t, uSrc2, 2); \
1188	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1189	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1190	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1191	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1192	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1193	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1194	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1195	iemAImpl_ ## a_Instr ## _u64, \
1196	iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1197	IEM_MC_ADVANCE_RIP(); \
1198	IEM_MC_END(); \
1199	} \
1200	else \
1201	{ \
1202	IEM_MC_BEGIN(3, 1); \
1203	IEM_MC_ARG(uint32_t *, pDst, 0); \
1204	IEM_MC_ARG(uint32_t, uSrc1, 1); \
1205	IEM_MC_ARG(uint32_t, uSrc2, 2); \
1206	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1207	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1208	IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1209	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1210	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1211	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1212	IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1213	iemAImpl_ ## a_Instr ## _u32, \
1214	iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1215	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1216	IEM_MC_ADVANCE_RIP(); \
1217	IEM_MC_END(); \
1218	} \
1219	} \
1220	return VINF_SUCCESS;
1221
1222
1223	/** Opcode VEX.F3.0F38 0xf5 (vex only). */
1224	FNIEMOP_DEF(iemOp_pext_Gy_By_Ey)
1225	{
1226	IEMOP_MNEMONIC3(VEX_RVM, PEXT, pext, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1227	IEMOP_BODY_Gy_By_Ey_NoEflags(pext, fBmi2);
1228	}
1229
1230
1231	/** Opcode VEX.F2.0F38 0xf5 (vex only). */
1232	FNIEMOP_DEF(iemOp_pdep_Gy_By_Ey)
1233	{
1234	IEMOP_MNEMONIC3(VEX_RVM, PDEP, pdep, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1235	IEMOP_BODY_Gy_By_Ey_NoEflags(pdep, fBmi2);
1236	}
1237
1238
1239	/* Opcode VEX.0F38 0xf6 - invalid. */
1240	/* Opcode VEX.66.0F38 0xf6 - invalid (legacy only). */
1241	/* Opcode VEX.F3.0F38 0xf6 - invalid (legacy only). */
1242
1243
1244	/** Opcode VEX.F2.0F38 0xf6 (vex only) */
1245	FNIEMOP_DEF(iemOp_mulx_By_Gy_rDX_Ey)
1246	{
1247	IEMOP_MNEMONIC4(VEX_RVM, MULX, mulx, Gy, By, Ey, rDX, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1248	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi2)
1249	return iemOp_InvalidNeedRM(pVCpu);
1250	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1251	if (IEM_IS_MODRM_REG_MODE(bRm))
1252	{
1253	/*
1254	* Register, register.
1255	*/
1256	IEMOP_HLP_DONE_VEX_DECODING_L0();
1257	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1258	{
1259	IEM_MC_BEGIN(4, 0);
1260	IEM_MC_ARG(uint64_t *, pDst1, 0);
1261	IEM_MC_ARG(uint64_t *, pDst2, 1);
1262	IEM_MC_ARG(uint64_t, uSrc1, 2);
1263	IEM_MC_ARG(uint64_t, uSrc2, 3);
1264	IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1265	IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1266	IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1267	IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1268	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1269	pDst1, pDst2, uSrc1, uSrc2);
1270	IEM_MC_ADVANCE_RIP();
1271	IEM_MC_END();
1272	}
1273	else
1274	{
1275	IEM_MC_BEGIN(4, 0);
1276	IEM_MC_ARG(uint32_t *, pDst1, 0);
1277	IEM_MC_ARG(uint32_t *, pDst2, 1);
1278	IEM_MC_ARG(uint32_t, uSrc1, 2);
1279	IEM_MC_ARG(uint32_t, uSrc2, 3);
1280	IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1281	IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1282	IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1283	IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1284	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1285	pDst1, pDst2, uSrc1, uSrc2);
1286	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1287	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1288	IEM_MC_ADVANCE_RIP();
1289	IEM_MC_END();
1290	}
1291	}
1292	else
1293	{
1294	/*
1295	* Register, memory.
1296	*/
1297	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1298	{
1299	IEM_MC_BEGIN(4, 1);
1300	IEM_MC_ARG(uint64_t *, pDst1, 0);
1301	IEM_MC_ARG(uint64_t *, pDst2, 1);
1302	IEM_MC_ARG(uint64_t, uSrc1, 2);
1303	IEM_MC_ARG(uint64_t, uSrc2, 3);
1304	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1305	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1306	IEMOP_HLP_DONE_VEX_DECODING_L0();
1307	IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1308	IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1309	IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1310	IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1311	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1312	pDst1, pDst2, uSrc1, uSrc2);
1313	IEM_MC_ADVANCE_RIP();
1314	IEM_MC_END();
1315	}
1316	else
1317	{
1318	IEM_MC_BEGIN(4, 1);
1319	IEM_MC_ARG(uint32_t *, pDst1, 0);
1320	IEM_MC_ARG(uint32_t *, pDst2, 1);
1321	IEM_MC_ARG(uint32_t, uSrc1, 2);
1322	IEM_MC_ARG(uint32_t, uSrc2, 3);
1323	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1324	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1325	IEMOP_HLP_DONE_VEX_DECODING_L0();
1326	IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1327	IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1328	IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1329	IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1330	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1331	pDst1, pDst2, uSrc1, uSrc2);
1332	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1333	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1334	IEM_MC_ADVANCE_RIP();
1335	IEM_MC_END();
1336	}
1337	}
1338	return VINF_SUCCESS;
1339	}
1340
1341
1342	/** Opcode VEX.0F38 0xf7 (vex only). */
1343	FNIEMOP_DEF(iemOp_bextr_Gy_Ey_By)
1344	{
1345	IEMOP_MNEMONIC3(VEX_RMV, BEXTR, bextr, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1346	IEMOP_BODY_Gy_Ey_By(bextr, fBmi1, X86_EFL_SF \| X86_EFL_AF \| X86_EFL_PF);
1347	}
1348
1349
1350	/** Opcode VEX.66.0F38 0xf7 (vex only). */
1351	FNIEMOP_DEF(iemOp_shlx_Gy_Ey_By)
1352	{
1353	IEMOP_MNEMONIC3(VEX_RMV, SHLX, shlx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1354	IEMOP_BODY_Gy_Ey_By_NoEflags(shlx, fBmi2, 0);
1355	}
1356
1357
1358	/** Opcode VEX.F3.0F38 0xf7 (vex only). */
1359	FNIEMOP_DEF(iemOp_sarx_Gy_Ey_By)
1360	{
1361	IEMOP_MNEMONIC3(VEX_RMV, SARX, sarx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1362	IEMOP_BODY_Gy_Ey_By_NoEflags(sarx, fBmi2, 0);
1363	}
1364
1365
1366	/** Opcode VEX.F2.0F38 0xf7 (vex only). */
1367	FNIEMOP_DEF(iemOp_shrx_Gy_Ey_By)
1368	{
1369	IEMOP_MNEMONIC3(VEX_RMV, SHRX, shrx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1370	IEMOP_BODY_Gy_Ey_By_NoEflags(shrx, fBmi2, 0);
1371	}
1372
1373	/* Opcode VEX.0F38 0xf8 - invalid. */
1374	/* Opcode VEX.66.0F38 0xf8 - invalid. */
1375	/* Opcode VEX.F3.0F38 0xf8 - invalid. */
1376	/* Opcode VEX.F2.0F38 0xf8 - invalid. */
1377
1378	/* Opcode VEX.0F38 0xf9 - invalid. */
1379	/* Opcode VEX.66.0F38 0xf9 - invalid. */
1380	/* Opcode VEX.F3.0F38 0xf9 - invalid. */
1381	/* Opcode VEX.F2.0F38 0xf9 - invalid. */
1382
1383	/* Opcode VEX.0F38 0xfa - invalid. */
1384	/* Opcode VEX.66.0F38 0xfa - invalid. */
1385	/* Opcode VEX.F3.0F38 0xfa - invalid. */
1386	/* Opcode VEX.F2.0F38 0xfa - invalid. */
1387
1388	/* Opcode VEX.0F38 0xfb - invalid. */
1389	/* Opcode VEX.66.0F38 0xfb - invalid. */
1390	/* Opcode VEX.F3.0F38 0xfb - invalid. */
1391	/* Opcode VEX.F2.0F38 0xfb - invalid. */
1392
1393	/* Opcode VEX.0F38 0xfc - invalid. */
1394	/* Opcode VEX.66.0F38 0xfc - invalid. */
1395	/* Opcode VEX.F3.0F38 0xfc - invalid. */
1396	/* Opcode VEX.F2.0F38 0xfc - invalid. */
1397
1398	/* Opcode VEX.0F38 0xfd - invalid. */
1399	/* Opcode VEX.66.0F38 0xfd - invalid. */
1400	/* Opcode VEX.F3.0F38 0xfd - invalid. */
1401	/* Opcode VEX.F2.0F38 0xfd - invalid. */
1402
1403	/* Opcode VEX.0F38 0xfe - invalid. */
1404	/* Opcode VEX.66.0F38 0xfe - invalid. */
1405	/* Opcode VEX.F3.0F38 0xfe - invalid. */
1406	/* Opcode VEX.F2.0F38 0xfe - invalid. */
1407
1408	/* Opcode VEX.0F38 0xff - invalid. */
1409	/* Opcode VEX.66.0F38 0xff - invalid. */
1410	/* Opcode VEX.F3.0F38 0xff - invalid. */
1411	/* Opcode VEX.F2.0F38 0xff - invalid. */
1412
1413
1414	/**
1415	* VEX opcode map \#2.
1416	*
1417	* @sa g_apfnThreeByte0f38
1418	*/
1419	IEM_STATIC const PFNIEMOP g_apfnVexMap2[] =
1420	{
1421	/* no prefix, 066h prefix f3h prefix, f2h prefix */
1422	/* 0x00 */ iemOp_InvalidNeedRM, iemOp_vpshufb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1423	/* 0x01 */ iemOp_InvalidNeedRM, iemOp_vphaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1424	/* 0x02 */ iemOp_InvalidNeedRM, iemOp_vphaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1425	/* 0x03 */ iemOp_InvalidNeedRM, iemOp_vphaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1426	/* 0x04 */ iemOp_InvalidNeedRM, iemOp_vpmaddubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1427	/* 0x05 */ iemOp_InvalidNeedRM, iemOp_vphsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1428	/* 0x06 */ iemOp_InvalidNeedRM, iemOp_vphsubdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1429	/* 0x07 */ iemOp_InvalidNeedRM, iemOp_vphsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1430	/* 0x08 */ iemOp_InvalidNeedRM, iemOp_vpsignb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1431	/* 0x09 */ iemOp_InvalidNeedRM, iemOp_vpsignw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1432	/* 0x0a */ iemOp_InvalidNeedRM, iemOp_vpsignd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1433	/* 0x0b */ iemOp_InvalidNeedRM, iemOp_vpmulhrsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1434	/* 0x0c */ iemOp_InvalidNeedRM, iemOp_vpermilps_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1435	/* 0x0d */ iemOp_InvalidNeedRM, iemOp_vpermilpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1436	/* 0x0e */ iemOp_InvalidNeedRM, iemOp_vtestps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1437	/* 0x0f */ iemOp_InvalidNeedRM, iemOp_vtestpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1438
1439	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRM),
1440	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
1441	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
1442	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
1443	/* 0x14 */ IEMOP_X4(iemOp_InvalidNeedRM),
1444	/* 0x15 */ IEMOP_X4(iemOp_InvalidNeedRM),
1445	/* 0x16 */ iemOp_InvalidNeedRM, iemOp_vpermps_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1446	/* 0x17 */ iemOp_InvalidNeedRM, iemOp_vptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1447	/* 0x18 */ iemOp_InvalidNeedRM, iemOp_vbroadcastss_Vx_Wd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1448	/* 0x19 */ iemOp_InvalidNeedRM, iemOp_vbroadcastsd_Vqq_Wq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1449	/* 0x1a */ iemOp_InvalidNeedRM, iemOp_vbroadcastf128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1450	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
1451	/* 0x1c */ iemOp_InvalidNeedRM, iemOp_vpabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1452	/* 0x1d */ iemOp_InvalidNeedRM, iemOp_vpabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1453	/* 0x1e */ iemOp_InvalidNeedRM, iemOp_vpabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1454	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
1455
1456	/* 0x20 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1457	/* 0x21 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1458	/* 0x22 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1459	/* 0x23 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1460	/* 0x24 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1461	/* 0x25 */ iemOp_InvalidNeedRM, iemOp_vpmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1462	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
1463	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
1464	/* 0x28 */ iemOp_InvalidNeedRM, iemOp_vpmuldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1465	/* 0x29 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1466	/* 0x2a */ iemOp_InvalidNeedRM, iemOp_vmovntdqa_Vx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1467	/* 0x2b */ iemOp_InvalidNeedRM, iemOp_vpackusdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1468	/* 0x2c */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1469	/* 0x2d */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1470	/* 0x2e */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1471	/* 0x2f */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1472
1473	/* 0x30 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1474	/* 0x31 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1475	/* 0x32 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1476	/* 0x33 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1477	/* 0x34 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1478	/* 0x35 */ iemOp_InvalidNeedRM, iemOp_vpmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1479	/* 0x36 */ iemOp_InvalidNeedRM, iemOp_vpermd_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1480	/* 0x37 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1481	/* 0x38 */ iemOp_InvalidNeedRM, iemOp_vpminsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1482	/* 0x39 */ iemOp_InvalidNeedRM, iemOp_vpminsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1483	/* 0x3a */ iemOp_InvalidNeedRM, iemOp_vpminuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1484	/* 0x3b */ iemOp_InvalidNeedRM, iemOp_vpminud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1485	/* 0x3c */ iemOp_InvalidNeedRM, iemOp_vpmaxsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1486	/* 0x3d */ iemOp_InvalidNeedRM, iemOp_vpmaxsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1487	/* 0x3e */ iemOp_InvalidNeedRM, iemOp_vpmaxuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1488	/* 0x3f */ iemOp_InvalidNeedRM, iemOp_vpmaxud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1489
1490	/* 0x40 */ iemOp_InvalidNeedRM, iemOp_vpmulld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1491	/* 0x41 */ iemOp_InvalidNeedRM, iemOp_vphminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1492	/* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
1493	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
1494	/* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
1495	/* 0x45 */ iemOp_InvalidNeedRM, iemOp_vpsrlvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1496	/* 0x46 */ iemOp_InvalidNeedRM, iemOp_vsravd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1497	/* 0x47 */ iemOp_InvalidNeedRM, iemOp_vpsllvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1498	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
1499	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
1500	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
1501	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
1502	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
1503	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
1504	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
1505	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
1506
1507	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
1508	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
1509	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
1510	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
1511	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
1512	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
1513	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
1514	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
1515	/* 0x58 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1516	/* 0x59 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1517	/* 0x5a */ iemOp_InvalidNeedRM, iemOp_vbroadcasti128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1518	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
1519	/* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
1520	/* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
1521	/* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
1522	/* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
1523
1524	/* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
1525	/* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
1526	/* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
1527	/* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
1528	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
1529	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
1530	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
1531	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
1532	/* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
1533	/* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
1534	/* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
1535	/* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
1536	/* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
1537	/* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
1538	/* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
1539	/* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
1540
1541	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
1542	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
1543	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
1544	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
1545	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
1546	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
1547	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
1548	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
1549	/* 0x78 */ iemOp_InvalidNeedRM, iemOp_vpboardcastb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1550	/* 0x79 */ iemOp_InvalidNeedRM, iemOp_vpboardcastw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1551	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
1552	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
1553	/* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
1554	/* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
1555	/* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
1556	/* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
1557
1558	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
1559	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
1560	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
1561	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
1562	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
1563	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
1564	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
1565	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
1566	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
1567	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
1568	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
1569	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
1570	/* 0x8c */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1571	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
1572	/* 0x8e */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Mx_Vx_Hx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1573	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
1574
1575	/* 0x90 */ iemOp_InvalidNeedRM, iemOp_vgatherdd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1576	/* 0x91 */ iemOp_InvalidNeedRM, iemOp_vgatherqd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1577	/* 0x92 */ iemOp_InvalidNeedRM, iemOp_vgatherdps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1578	/* 0x93 */ iemOp_InvalidNeedRM, iemOp_vgatherqps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1579	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
1580	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
1581	/* 0x96 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub132ps_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1582	/* 0x97 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1583	/* 0x98 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1584	/* 0x99 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1585	/* 0x9a */ iemOp_InvalidNeedRM, iemOp_vfmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1586	/* 0x9b */ iemOp_InvalidNeedRM, iemOp_vfmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1587	/* 0x9c */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1588	/* 0x9d */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1589	/* 0x9e */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1590	/* 0x9f */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1591
1592	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1593	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1594	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1595	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1596	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1597	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1598	/* 0xa6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1599	/* 0xa7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1600	/* 0xa8 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1601	/* 0xa9 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1602	/* 0xaa */ iemOp_InvalidNeedRM, iemOp_vfmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1603	/* 0xab */ iemOp_InvalidNeedRM, iemOp_vfmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1604	/* 0xac */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1605	/* 0xad */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1606	/* 0xae */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1607	/* 0xaf */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1608
1609	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1610	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1611	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1612	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1613	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1614	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1615	/* 0xb6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1616	/* 0xb7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1617	/* 0xb8 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1618	/* 0xb9 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1619	/* 0xba */ iemOp_InvalidNeedRM, iemOp_vfmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1620	/* 0xbb */ iemOp_InvalidNeedRM, iemOp_vfmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1621	/* 0xbc */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1622	/* 0xbd */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1623	/* 0xbe */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1624	/* 0xbf */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1625
1626	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1627	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1628	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1629	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1630	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1631	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1632	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1633	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1634	/* 0xc8 */ iemOp_vsha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1635	/* 0xc9 */ iemOp_vsha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1636	/* 0xca */ iemOp_vsha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1637	/* 0xcb */ iemOp_vsha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1638	/* 0xcc */ iemOp_vsha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1639	/* 0xcd */ iemOp_vsha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1640	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
1641	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
1642
1643	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1644	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1645	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1646	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1647	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1648	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1649	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1650	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1651	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1652	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1653	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
1654	/* 0xdb */ iemOp_InvalidNeedRM, iemOp_vaesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1655	/* 0xdc */ iemOp_InvalidNeedRM, iemOp_vaesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1656	/* 0xdd */ iemOp_InvalidNeedRM, iemOp_vaesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1657	/* 0xde */ iemOp_InvalidNeedRM, iemOp_vaesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1658	/* 0xdf */ iemOp_InvalidNeedRM, iemOp_vaesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1659
1660	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1661	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1662	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1663	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1664	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1665	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1666	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1667	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1668	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1669	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1670	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
1671	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
1672	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
1673	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
1674	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
1675	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
1676
1677	/* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1678	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1679	/* 0xf2 */ iemOp_andn_Gy_By_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1680	/* 0xf3 */ iemOp_VGrp17_f3, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1681	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1682	/* 0xf5 */ iemOp_bzhi_Gy_Ey_By, iemOp_InvalidNeedRM, iemOp_pext_Gy_By_Ey, iemOp_pdep_Gy_By_Ey,
1683	/* 0xf6 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_mulx_By_Gy_rDX_Ey,
1684	/* 0xf7 */ iemOp_bextr_Gy_Ey_By, iemOp_shlx_Gy_Ey_By, iemOp_sarx_Gy_Ey_By, iemOp_shrx_Gy_Ey_By,
1685	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
1686	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
1687	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
1688	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
1689	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
1690	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
1691	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
1692	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
1693	};
1694	AssertCompile(RT_ELEMENTS(g_apfnVexMap2) == 1024);
1695
1696	/** @} */
1697

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h@ 96002

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