VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h@ 96115

Last change on this file since 96115 was 96115, checked in by vboxsync, 2 years ago

VMM/IEM: Implement [v]pmov{s,z}x[bw,bd,bq,wd,wq,dq] instructions, bugref:9898 (review is required)
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1/* $Id: IEMAllInstructionsVexMap2.cpp.h 96115 2022-08-08 20:04:00Z vboxsync $ */
2/** @file
3 * IEM - Instruction Decoding and Emulation.
4 *
5 * @remarks IEMAllInstructionsThree0f38.cpp.h is a VEX mirror of this file.
6 * Any update here is likely needed in that file too.
7 */
8
9/*
10 * Copyright (C) 2011-2022 Oracle Corporation
11 *
12 * This file is part of VirtualBox Open Source Edition (OSE), as
13 * available from http://www.virtualbox.org. This file is free software;
14 * you can redistribute it and/or modify it under the terms of the GNU
15 * General Public License (GPL) as published by the Free Software
16 * Foundation, in version 2 as it comes in the "COPYING" file of the
17 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19 */
20
21
22/** @name VEX Opcode Map 2
23 * @{
24 */
25
26/* Opcode VEX.0F38 0x00 - invalid. */
27
28
29/** Opcode VEX.66.0F38 0x00. */
30FNIEMOP_DEF(iemOp_vpshufb_Vx_Hx_Wx)
31{
32 IEMOP_MNEMONIC3(VEX_RVM, VPSHUFB, vpshufb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
33 IEMOPMEDIAF3_INIT_VARS(vpshufb);
34 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
35}
36
37
38/* Opcode VEX.0F38 0x01 - invalid. */
39
40
41/** Opcode VEX.66.0F38 0x01. */
42FNIEMOP_DEF(iemOp_vphaddw_Vx_Hx_Wx)
43{
44 IEMOP_MNEMONIC3(VEX_RVM, VPHADDW, vphaddw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
45 IEMOPMEDIAOPTF3_INIT_VARS(vphaddw);
46 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
47}
48
49
50/* Opcode VEX.0F38 0x02 - invalid. */
51
52
53/** Opcode VEX.66.0F38 0x02. */
54FNIEMOP_DEF(iemOp_vphaddd_Vx_Hx_Wx)
55{
56 IEMOP_MNEMONIC3(VEX_RVM, VPHADDD, vphaddd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
57 IEMOPMEDIAOPTF3_INIT_VARS(vphaddd);
58 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
59}
60
61
62/* Opcode VEX.0F38 0x03 - invalid. */
63
64
65/** Opcode VEX.66.0F38 0x03. */
66FNIEMOP_DEF(iemOp_vphaddsw_Vx_Hx_Wx)
67{
68 IEMOP_MNEMONIC3(VEX_RVM, VPHADDSW, vphaddsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
69 IEMOPMEDIAOPTF3_INIT_VARS(vphaddsw);
70 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
71}
72
73
74/* Opcode VEX.0F38 0x04 - invalid. */
75
76
77/** Opcode VEX.66.0F38 0x04. */
78FNIEMOP_DEF(iemOp_vpmaddubsw_Vx_Hx_Wx)
79{
80 IEMOP_MNEMONIC3(VEX_RVM, VPMADDUBSW, vpmaddubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
81 IEMOPMEDIAOPTF3_INIT_VARS(vpmaddubsw);
82 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
83}
84
85
86/* Opcode VEX.0F38 0x05 - invalid. */
87
88
89/** Opcode VEX.66.0F38 0x05. */
90FNIEMOP_DEF(iemOp_vphsubw_Vx_Hx_Wx)
91{
92 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBW, vphsubw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
93 IEMOPMEDIAOPTF3_INIT_VARS(vphsubw);
94 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
95}
96
97
98/* Opcode VEX.0F38 0x06 - invalid. */
99
100
101/** Opcode VEX.66.0F38 0x06. */
102FNIEMOP_DEF(iemOp_vphsubd_Vx_Hx_Wx)
103{
104 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBD, vphsubd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
105 IEMOPMEDIAOPTF3_INIT_VARS(vphsubd);
106 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
107}
108
109
110/* Opcode VEX.0F38 0x07 - invalid. */
111
112
113/** Opcode VEX.66.0F38 0x07. */
114FNIEMOP_DEF(iemOp_vphsubsw_Vx_Hx_Wx)
115{
116 IEMOP_MNEMONIC3(VEX_RVM, VPHSUBSW, vphsubsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
117 IEMOPMEDIAOPTF3_INIT_VARS(vphsubsw);
118 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
119}
120
121
122/* Opcode VEX.0F38 0x08 - invalid. */
123
124
125/** Opcode VEX.66.0F38 0x08. */
126FNIEMOP_DEF(iemOp_vpsignb_Vx_Hx_Wx)
127{
128 IEMOP_MNEMONIC3(VEX_RVM, VPSIGNB, vpsignb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
129 IEMOPMEDIAOPTF3_INIT_VARS(vpsignb);
130 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
131}
132
133
134/* Opcode VEX.0F38 0x09 - invalid. */
135
136
137/** Opcode VEX.66.0F38 0x09. */
138FNIEMOP_DEF(iemOp_vpsignw_Vx_Hx_Wx)
139{
140 IEMOP_MNEMONIC3(VEX_RVM, VPSIGNW, vpsignw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
141 IEMOPMEDIAOPTF3_INIT_VARS(vpsignw);
142 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
143}
144
145
146/* Opcode VEX.0F38 0x0a - invalid. */
147
148
149/** Opcode VEX.66.0F38 0x0a. */
150FNIEMOP_DEF(iemOp_vpsignd_Vx_Hx_Wx)
151{
152 IEMOP_MNEMONIC3(VEX_RVM, VPSIGND, vpsignd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
153 IEMOPMEDIAOPTF3_INIT_VARS(vpsignd);
154 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
155}
156
157
158/* Opcode VEX.0F38 0x0b - invalid. */
159
160
161/** Opcode VEX.66.0F38 0x0b. */
162FNIEMOP_DEF(iemOp_vpmulhrsw_Vx_Hx_Wx)
163{
164 IEMOP_MNEMONIC3(VEX_RVM, VPMULHRSW, vpmulhrsw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
165 IEMOPMEDIAOPTF3_INIT_VARS(vpmulhrsw);
166 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
167}
168
169
170/* Opcode VEX.0F38 0x0c - invalid. */
171/** Opcode VEX.66.0F38 0x0c. */
172FNIEMOP_STUB(iemOp_vpermilps_Vx_Hx_Wx);
173/* Opcode VEX.0F38 0x0d - invalid. */
174/** Opcode VEX.66.0F38 0x0d. */
175FNIEMOP_STUB(iemOp_vpermilpd_Vx_Hx_Wx);
176/* Opcode VEX.0F38 0x0e - invalid. */
177/** Opcode VEX.66.0F38 0x0e. */
178FNIEMOP_STUB(iemOp_vtestps_Vx_Wx);
179/* Opcode VEX.0F38 0x0f - invalid. */
180/** Opcode VEX.66.0F38 0x0f. */
181FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx);
182
183
184/* Opcode VEX.0F38 0x10 - invalid */
185/* Opcode VEX.66.0F38 0x10 - invalid (legacy only). */
186/* Opcode VEX.0F38 0x11 - invalid */
187/* Opcode VEX.66.0F38 0x11 - invalid */
188/* Opcode VEX.0F38 0x12 - invalid */
189/* Opcode VEX.66.0F38 0x12 - invalid */
190/* Opcode VEX.0F38 0x13 - invalid */
191/* Opcode VEX.66.0F38 0x13 - invalid (vex only). */
192/* Opcode VEX.0F38 0x14 - invalid */
193/* Opcode VEX.66.0F38 0x14 - invalid (legacy only). */
194/* Opcode VEX.0F38 0x15 - invalid */
195/* Opcode VEX.66.0F38 0x15 - invalid (legacy only). */
196/* Opcode VEX.0F38 0x16 - invalid */
197/** Opcode VEX.66.0F38 0x16. */
198FNIEMOP_STUB(iemOp_vpermps_Vqq_Hqq_Wqq);
199/* Opcode VEX.0F38 0x17 - invalid */
200
201
202/** Opcode VEX.66.0F38 0x17 - invalid */
203FNIEMOP_DEF(iemOp_vptest_Vx_Wx)
204{
205 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
206 if (IEM_IS_MODRM_REG_MODE(bRm))
207 {
208 /*
209 * Register, register.
210 */
211 if (pVCpu->iem.s.uVexLength)
212 {
213 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
214 IEM_MC_BEGIN(3, 2);
215 IEM_MC_LOCAL(RTUINT256U, uSrc1);
216 IEM_MC_LOCAL(RTUINT256U, uSrc2);
217 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
218 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
219 IEM_MC_ARG(uint32_t *, pEFlags, 2);
220 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
221 IEM_MC_PREPARE_AVX_USAGE();
222 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
223 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
224 IEM_MC_REF_EFLAGS(pEFlags);
225 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
226 puSrc1, puSrc2, pEFlags);
227 IEM_MC_ADVANCE_RIP();
228 IEM_MC_END();
229 }
230 else
231 {
232 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
233 IEM_MC_BEGIN(3, 0);
234 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
235 IEM_MC_ARG(PCRTUINT128U, puSrc2, 1);
236 IEM_MC_ARG(uint32_t *, pEFlags, 2);
237 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
238 IEM_MC_PREPARE_AVX_USAGE();
239 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
240 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
241 IEM_MC_REF_EFLAGS(pEFlags);
242 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
243 IEM_MC_ADVANCE_RIP();
244 IEM_MC_END();
245 }
246 }
247 else
248 {
249 /*
250 * Register, memory.
251 */
252 if (pVCpu->iem.s.uVexLength)
253 {
254 IEM_MC_BEGIN(3, 3);
255 IEM_MC_LOCAL(RTUINT256U, uSrc1);
256 IEM_MC_LOCAL(RTUINT256U, uSrc2);
257 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
258 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0);
259 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1);
260 IEM_MC_ARG(uint32_t *, pEFlags, 2);
261
262 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
263 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
264 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
265 IEM_MC_PREPARE_AVX_USAGE();
266
267 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
268 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
269 IEM_MC_REF_EFLAGS(pEFlags);
270 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback),
271 puSrc1, puSrc2, pEFlags);
272
273 IEM_MC_ADVANCE_RIP();
274 IEM_MC_END();
275 }
276 else
277 {
278 IEM_MC_BEGIN(3, 2);
279 IEM_MC_LOCAL(RTUINT128U, uSrc2);
280 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
281 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0);
282 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1);
283 IEM_MC_ARG(uint32_t *, pEFlags, 2);
284
285 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
286 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
287 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
288 IEM_MC_PREPARE_AVX_USAGE();
289
290 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
291 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
292 IEM_MC_REF_EFLAGS(pEFlags);
293 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags);
294
295 IEM_MC_ADVANCE_RIP();
296 IEM_MC_END();
297 }
298 }
299 return VINF_SUCCESS;
300
301}
302
303
304/* Opcode VEX.0F38 0x18 - invalid */
305/** Opcode VEX.66.0F38 0x18. */
306FNIEMOP_STUB(iemOp_vbroadcastss_Vx_Wd);
307/* Opcode VEX.0F38 0x19 - invalid */
308/** Opcode VEX.66.0F38 0x19. */
309FNIEMOP_STUB(iemOp_vbroadcastsd_Vqq_Wq);
310/* Opcode VEX.0F38 0x1a - invalid */
311/** Opcode VEX.66.0F38 0x1a. */
312FNIEMOP_STUB(iemOp_vbroadcastf128_Vqq_Mdq);
313/* Opcode VEX.0F38 0x1b - invalid */
314/* Opcode VEX.66.0F38 0x1b - invalid */
315/* Opcode VEX.0F38 0x1c - invalid. */
316
317
318/** Opcode VEX.66.0F38 0x1c. */
319FNIEMOP_DEF(iemOp_vpabsb_Vx_Wx)
320{
321 IEMOP_MNEMONIC2(VEX_RM, VPABSB, vpabsb, Vx, Wx, DISOPTYPE_HARMLESS, 0);
322 IEMOPMEDIAOPTF2_INIT_VARS(vpabsb);
323 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
324}
325
326
327/* Opcode VEX.0F38 0x1d - invalid. */
328
329
330/** Opcode VEX.66.0F38 0x1d. */
331FNIEMOP_DEF(iemOp_vpabsw_Vx_Wx)
332{
333 IEMOP_MNEMONIC2(VEX_RM, VPABSW, vpabsw, Vx, Wx, DISOPTYPE_HARMLESS, 0);
334 IEMOPMEDIAOPTF2_INIT_VARS(vpabsw);
335 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
336}
337
338/* Opcode VEX.0F38 0x1e - invalid. */
339
340
341/** Opcode VEX.66.0F38 0x1e. */
342FNIEMOP_DEF(iemOp_vpabsd_Vx_Wx)
343{
344 IEMOP_MNEMONIC2(VEX_RM, VPABSD, vpabsd, Vx, Wx, DISOPTYPE_HARMLESS, 0);
345 IEMOPMEDIAOPTF2_INIT_VARS(vpabsd);
346 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
347}
348
349
350/* Opcode VEX.0F38 0x1f - invalid */
351/* Opcode VEX.66.0F38 0x1f - invalid */
352
353
354/** Body for the vpmov{s,z}x* instructions. */
355#define IEMOP_BODY_VPMOV_S_Z(a_Instr, a_SrcWidth) \
356 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
357 if (IEM_IS_MODRM_REG_MODE(bRm)) \
358 { \
359 /* \
360 * Register, register. \
361 */ \
362 if (pVCpu->iem.s.uVexLength) \
363 { \
364 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2); \
365 IEM_MC_BEGIN(2, 1); \
366 IEM_MC_LOCAL(RTUINT256U, uDst); \
367 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
368 IEM_MC_ARG(PCRTUINT128U, puSrc, 1); \
369 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
370 IEM_MC_PREPARE_AVX_USAGE(); \
371 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
372 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
373 iemAImpl_ ## a_Instr ## _u256_fallback), \
374 puDst, puSrc); \
375 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
376 IEM_MC_ADVANCE_RIP(); \
377 IEM_MC_END(); \
378 } \
379 else \
380 { \
381 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx); \
382 IEM_MC_BEGIN(2, 0); \
383 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
384 IEM_MC_ARG(uint64_t, uSrc, 1); \
385 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
386 IEM_MC_PREPARE_AVX_USAGE(); \
387 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
388 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
389 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
390 iemAImpl_## a_Instr ## _u128_fallback), \
391 puDst, uSrc); \
392 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
393 IEM_MC_ADVANCE_RIP(); \
394 IEM_MC_END(); \
395 } \
396 } \
397 else \
398 { \
399 /* \
400 * Register, memory. \
401 */ \
402 if (pVCpu->iem.s.uVexLength) \
403 { \
404 IEM_MC_BEGIN(2, 3); \
405 IEM_MC_LOCAL(RTUINT256U, uDst); \
406 IEM_MC_LOCAL(RTUINT128U, uSrc); \
407 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
408 IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0); \
409 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1); \
410 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
411 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx2); \
412 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
413 IEM_MC_PREPARE_AVX_USAGE(); \
414 IEM_MC_FETCH_MEM_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
415 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u256, \
416 iemAImpl_ ## a_Instr ## _u256_fallback), \
417 puDst, puSrc); \
418 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \
419 IEM_MC_ADVANCE_RIP(); \
420 IEM_MC_END(); \
421 } \
422 else \
423 { \
424 IEM_MC_BEGIN(2, 1); \
425 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
426 IEM_MC_ARG(PRTUINT128U, puDst, 0); \
427 IEM_MC_ARG(uint ## a_SrcWidth ##_t, uSrc, 1); \
428 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
429 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(fAvx); \
430 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT(); \
431 IEM_MC_PREPARE_AVX_USAGE(); \
432 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
433 IEM_MC_FETCH_MEM_U ## a_SrcWidth (uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
434 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_ ## a_Instr ## _u128, \
435 iemAImpl_ ## a_Instr ## _u128_fallback), \
436 puDst, uSrc); \
437 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \
438 IEM_MC_ADVANCE_RIP(); \
439 IEM_MC_END(); \
440 } \
441 } \
442 return VINF_SUCCESS \
443
444/** Opcode VEX.66.0F38 0x20. */
445FNIEMOP_DEF(iemOp_vpmovsxbw_Vx_UxMq)
446{
447 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
448 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBW, vpmovsxbw, Vx, Wq, DISOPTYPE_HARMLESS, 0);
449 IEMOP_BODY_VPMOV_S_Z(vpmovsxbw, 64);
450}
451
452
453/** Opcode VEX.66.0F38 0x21. */
454FNIEMOP_DEF(iemOp_vpmovsxbd_Vx_UxMd)
455{
456 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
457 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBD, vpmovsxbd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
458 IEMOP_BODY_VPMOV_S_Z(vpmovsxbd, 32);
459}
460
461
462/** Opcode VEX.66.0F38 0x22. */
463FNIEMOP_DEF(iemOp_vpmovsxbq_Vx_UxMw)
464{
465 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
466 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXBQ, vpmovsxbq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
467 IEMOP_BODY_VPMOV_S_Z(vpmovsxbq, 16);
468}
469
470
471/** Opcode VEX.66.0F38 0x23. */
472FNIEMOP_DEF(iemOp_vpmovsxwd_Vx_UxMq)
473{
474 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
475 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXWD, vpmovsxwd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
476 IEMOP_BODY_VPMOV_S_Z(vpmovsxwd, 64);
477}
478
479
480/** Opcode VEX.66.0F38 0x24. */
481FNIEMOP_DEF(iemOp_vpmovsxwq_Vx_UxMd)
482{
483 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
484 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXWQ, vpmovsxwq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
485 IEMOP_BODY_VPMOV_S_Z(vpmovsxwq, 32);
486}
487
488
489/** Opcode VEX.66.0F38 0x25. */
490FNIEMOP_DEF(iemOp_vpmovsxdq_Vx_UxMq)
491{
492 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
493 IEMOP_MNEMONIC2(VEX_RM, VPMOVSXDQ, vpmovsxdq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
494 IEMOP_BODY_VPMOV_S_Z(vpmovsxdq, 64);
495}
496
497
498/* Opcode VEX.66.0F38 0x26 - invalid */
499/* Opcode VEX.66.0F38 0x27 - invalid */
500
501
502/** Opcode VEX.66.0F38 0x28. */
503FNIEMOP_DEF(iemOp_vpmuldq_Vx_Hx_Wx)
504{
505 IEMOP_MNEMONIC3(VEX_RVM, VPMULDQ, vpmuldq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
506 IEMOPMEDIAOPTF3_INIT_VARS(vpmuldq);
507 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
508}
509
510
511/** Opcode VEX.66.0F38 0x29. */
512FNIEMOP_DEF(iemOp_vpcmpeqq_Vx_Hx_Wx)
513{
514 IEMOP_MNEMONIC3(VEX_RVM, VPCMPEQQ, vpcmpeqq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
515 IEMOPMEDIAF3_INIT_VARS(vpcmpeqq);
516 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
517}
518
519
520FNIEMOP_DEF(iemOp_vmovntdqa_Vx_Mx)
521{
522 Assert(pVCpu->iem.s.uVexLength <= 1);
523 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
524 if (IEM_IS_MODRM_MEM_MODE(bRm))
525 {
526 if (pVCpu->iem.s.uVexLength == 0)
527 {
528 /**
529 * @opcode 0x2a
530 * @opcodesub !11 mr/reg vex.l=0
531 * @oppfx 0x66
532 * @opcpuid avx
533 * @opgroup og_avx_cachect
534 * @opxcpttype 1
535 * @optest op1=-1 op2=2 -> op1=2
536 * @optest op1=0 op2=-42 -> op1=-42
537 */
538 /* 128-bit: Memory, register. */
539 IEMOP_MNEMONIC2EX(vmovntdqa_Vdq_WO_Mdq_L0, "vmovntdqa, Vdq_WO, Mdq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
540 DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
541 IEM_MC_BEGIN(0, 2);
542 IEM_MC_LOCAL(RTUINT128U, uSrc);
543 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
544
545 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
546 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
547 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
548 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
549
550 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
551 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
552
553 IEM_MC_ADVANCE_RIP();
554 IEM_MC_END();
555 }
556 else
557 {
558 /**
559 * @opdone
560 * @opcode 0x2a
561 * @opcodesub !11 mr/reg vex.l=1
562 * @oppfx 0x66
563 * @opcpuid avx2
564 * @opgroup og_avx2_cachect
565 * @opxcpttype 1
566 * @optest op1=-1 op2=2 -> op1=2
567 * @optest op1=0 op2=-42 -> op1=-42
568 */
569 /* 256-bit: Memory, register. */
570 IEMOP_MNEMONIC2EX(vmovntdqa_Vqq_WO_Mqq_L1, "vmovntdqa, Vqq_WO,Mqq", VEX_RM_MEM, VMOVNTDQA, vmovntdqa, Vx_WO, Mx,
571 DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
572 IEM_MC_BEGIN(0, 2);
573 IEM_MC_LOCAL(RTUINT256U, uSrc);
574 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
575
576 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
577 IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
578 IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
579 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
580
581 IEM_MC_FETCH_MEM_U256_ALIGN_AVX(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
582 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc);
583
584 IEM_MC_ADVANCE_RIP();
585 IEM_MC_END();
586 }
587 return VINF_SUCCESS;
588 }
589
590 /**
591 * @opdone
592 * @opmnemonic udvex660f382arg
593 * @opcode 0x2a
594 * @opcodesub 11 mr/reg
595 * @oppfx 0x66
596 * @opunused immediate
597 * @opcpuid avx
598 * @optest ->
599 */
600 return IEMOP_RAISE_INVALID_OPCODE();
601}
602
603
604/** Opcode VEX.66.0F38 0x2b. */
605FNIEMOP_DEF(iemOp_vpackusdw_Vx_Hx_Wx)
606{
607 IEMOP_MNEMONIC3(VEX_RVM, VPACKUSDW, vpackusdw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, 0);
608 IEMOPMEDIAOPTF3_INIT_VARS( vpackusdw);
609 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
610}
611
612
613/** Opcode VEX.66.0F38 0x2c. */
614FNIEMOP_STUB(iemOp_vmaskmovps_Vx_Hx_Mx);
615/** Opcode VEX.66.0F38 0x2d. */
616FNIEMOP_STUB(iemOp_vmaskmovpd_Vx_Hx_Mx);
617/** Opcode VEX.66.0F38 0x2e. */
618FNIEMOP_STUB(iemOp_vmaskmovps_Mx_Hx_Vx);
619/** Opcode VEX.66.0F38 0x2f. */
620FNIEMOP_STUB(iemOp_vmaskmovpd_Mx_Hx_Vx);
621
622
623/** Opcode VEX.66.0F38 0x30. */
624FNIEMOP_DEF(iemOp_vpmovzxbw_Vx_UxMq)
625{
626 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
627 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBW, vpmovzxbw, Vx, Wq, DISOPTYPE_HARMLESS, 0);
628 IEMOP_BODY_VPMOV_S_Z(vpmovzxbw, 64);
629}
630
631
632/** Opcode VEX.66.0F38 0x31. */
633FNIEMOP_DEF(iemOp_vpmovzxbd_Vx_UxMd)
634{
635 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
636 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBD, vpmovzxbd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
637 IEMOP_BODY_VPMOV_S_Z(vpmovzxbd, 32);
638}
639
640
641/** Opcode VEX.66.0F38 0x32. */
642FNIEMOP_DEF(iemOp_vpmovzxbq_Vx_UxMw)
643{
644 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
645 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXBQ, vpmovzxbq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
646 IEMOP_BODY_VPMOV_S_Z(vpmovzxbq, 16);
647}
648
649
650/** Opcode VEX.66.0F38 0x33. */
651FNIEMOP_DEF(iemOp_vpmovzxwd_Vx_UxMq)
652{
653 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
654 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXWD, vpmovzxwd, Vx, Wq, DISOPTYPE_HARMLESS, 0);
655 IEMOP_BODY_VPMOV_S_Z(vpmovzxwd, 64);
656}
657
658
659/** Opcode VEX.66.0F38 0x34. */
660FNIEMOP_DEF(iemOp_vpmovzxwq_Vx_UxMd)
661{
662 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
663 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXWQ, vpmovzxwq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
664 IEMOP_BODY_VPMOV_S_Z(vpmovzxwq, 32);
665}
666
667
668/** Opcode VEX.66.0F38 0x35. */
669FNIEMOP_DEF(iemOp_vpmovzxdq_Vx_UxMq)
670{
671 /** @todo r=aeichner Review code, the naming of this function and the parameter type specifiers. */
672 IEMOP_MNEMONIC2(VEX_RM, VPMOVZXDQ, vpmovzxdq, Vx, Wq, DISOPTYPE_HARMLESS, 0);
673 IEMOP_BODY_VPMOV_S_Z(vpmovzxdq, 64);
674}
675
676
677/* Opcode VEX.66.0F38 0x36. */
678FNIEMOP_STUB(iemOp_vpermd_Vqq_Hqq_Wqq);
679
680
681/** Opcode VEX.66.0F38 0x37. */
682FNIEMOP_DEF(iemOp_vpcmpgtq_Vx_Hx_Wx)
683{
684 IEMOP_MNEMONIC3(VEX_RVM, VPCMPGTQ, vpcmpgtq, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
685 IEMOPMEDIAF3_INIT_VARS(vpcmpgtq);
686 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
687}
688
689
690/** Opcode VEX.66.0F38 0x38. */
691FNIEMOP_DEF(iemOp_vpminsb_Vx_Hx_Wx)
692{
693 IEMOP_MNEMONIC3(VEX_RVM, VPMINSB, vpminsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
694 IEMOPMEDIAF3_INIT_VARS(vpminsb);
695 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
696}
697
698
699/** Opcode VEX.66.0F38 0x39. */
700FNIEMOP_DEF(iemOp_vpminsd_Vx_Hx_Wx)
701{
702 IEMOP_MNEMONIC3(VEX_RVM, VPMINSD, vpminsd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
703 IEMOPMEDIAF3_INIT_VARS(vpminsd);
704 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
705}
706
707
708/** Opcode VEX.66.0F38 0x3a. */
709FNIEMOP_DEF(iemOp_vpminuw_Vx_Hx_Wx)
710{
711 IEMOP_MNEMONIC3(VEX_RVM, VPMINUW, vpminuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
712 IEMOPMEDIAF3_INIT_VARS(vpminuw);
713 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
714}
715
716
717/** Opcode VEX.66.0F38 0x3b. */
718FNIEMOP_DEF(iemOp_vpminud_Vx_Hx_Wx)
719{
720 IEMOP_MNEMONIC3(VEX_RVM, VPMINUD, vpminud, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
721 IEMOPMEDIAF3_INIT_VARS(vpminud);
722 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
723}
724
725
726/** Opcode VEX.66.0F38 0x3c. */
727FNIEMOP_DEF(iemOp_vpmaxsb_Vx_Hx_Wx)
728{
729 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSB, vpmaxsb, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
730 IEMOPMEDIAF3_INIT_VARS(vpmaxsb);
731 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
732}
733
734
735/** Opcode VEX.66.0F38 0x3d. */
736FNIEMOP_DEF(iemOp_vpmaxsd_Vx_Hx_Wx)
737{
738 IEMOP_MNEMONIC3(VEX_RVM, VPMAXSD, vpmaxsd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
739 IEMOPMEDIAF3_INIT_VARS(vpmaxsd);
740 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
741}
742
743
744/** Opcode VEX.66.0F38 0x3e. */
745FNIEMOP_DEF(iemOp_vpmaxuw_Vx_Hx_Wx)
746{
747 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUW, vpmaxuw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
748 IEMOPMEDIAF3_INIT_VARS(vpmaxuw);
749 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
750}
751
752
753/** Opcode VEX.66.0F38 0x3f. */
754FNIEMOP_DEF(iemOp_vpmaxud_Vx_Hx_Wx)
755{
756 IEMOP_MNEMONIC3(VEX_RVM, VPMAXUD, vpmaxud, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
757 IEMOPMEDIAF3_INIT_VARS(vpmaxud);
758 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
759}
760
761
762/** Opcode VEX.66.0F38 0x40. */
763FNIEMOP_DEF(iemOp_vpmulld_Vx_Hx_Wx)
764{
765 IEMOP_MNEMONIC3(VEX_RVM, VPMULLD, vpmulld, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
766 IEMOPMEDIAOPTF3_INIT_VARS(vpmulld);
767 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
768}
769
770
771/** Opcode VEX.66.0F38 0x41. */
772FNIEMOP_STUB(iemOp_vphminposuw_Vdq_Wdq);
773/* Opcode VEX.66.0F38 0x42 - invalid. */
774/* Opcode VEX.66.0F38 0x43 - invalid. */
775/* Opcode VEX.66.0F38 0x44 - invalid. */
776/** Opcode VEX.66.0F38 0x45. */
777FNIEMOP_STUB(iemOp_vpsrlvd_q_Vx_Hx_Wx);
778/** Opcode VEX.66.0F38 0x46. */
779FNIEMOP_STUB(iemOp_vsravd_Vx_Hx_Wx);
780/** Opcode VEX.66.0F38 0x47. */
781FNIEMOP_STUB(iemOp_vpsllvd_q_Vx_Hx_Wx);
782/* Opcode VEX.66.0F38 0x48 - invalid. */
783/* Opcode VEX.66.0F38 0x49 - invalid. */
784/* Opcode VEX.66.0F38 0x4a - invalid. */
785/* Opcode VEX.66.0F38 0x4b - invalid. */
786/* Opcode VEX.66.0F38 0x4c - invalid. */
787/* Opcode VEX.66.0F38 0x4d - invalid. */
788/* Opcode VEX.66.0F38 0x4e - invalid. */
789/* Opcode VEX.66.0F38 0x4f - invalid. */
790
791/* Opcode VEX.66.0F38 0x50 - invalid. */
792/* Opcode VEX.66.0F38 0x51 - invalid. */
793/* Opcode VEX.66.0F38 0x52 - invalid. */
794/* Opcode VEX.66.0F38 0x53 - invalid. */
795/* Opcode VEX.66.0F38 0x54 - invalid. */
796/* Opcode VEX.66.0F38 0x55 - invalid. */
797/* Opcode VEX.66.0F38 0x56 - invalid. */
798/* Opcode VEX.66.0F38 0x57 - invalid. */
799/** Opcode VEX.66.0F38 0x58. */
800FNIEMOP_STUB(iemOp_vpbroadcastd_Vx_Wx);
801/** Opcode VEX.66.0F38 0x59. */
802FNIEMOP_STUB(iemOp_vpbroadcastq_Vx_Wx);
803/** Opcode VEX.66.0F38 0x5a. */
804FNIEMOP_STUB(iemOp_vbroadcasti128_Vqq_Mdq);
805/* Opcode VEX.66.0F38 0x5b - invalid. */
806/* Opcode VEX.66.0F38 0x5c - invalid. */
807/* Opcode VEX.66.0F38 0x5d - invalid. */
808/* Opcode VEX.66.0F38 0x5e - invalid. */
809/* Opcode VEX.66.0F38 0x5f - invalid. */
810
811/* Opcode VEX.66.0F38 0x60 - invalid. */
812/* Opcode VEX.66.0F38 0x61 - invalid. */
813/* Opcode VEX.66.0F38 0x62 - invalid. */
814/* Opcode VEX.66.0F38 0x63 - invalid. */
815/* Opcode VEX.66.0F38 0x64 - invalid. */
816/* Opcode VEX.66.0F38 0x65 - invalid. */
817/* Opcode VEX.66.0F38 0x66 - invalid. */
818/* Opcode VEX.66.0F38 0x67 - invalid. */
819/* Opcode VEX.66.0F38 0x68 - invalid. */
820/* Opcode VEX.66.0F38 0x69 - invalid. */
821/* Opcode VEX.66.0F38 0x6a - invalid. */
822/* Opcode VEX.66.0F38 0x6b - invalid. */
823/* Opcode VEX.66.0F38 0x6c - invalid. */
824/* Opcode VEX.66.0F38 0x6d - invalid. */
825/* Opcode VEX.66.0F38 0x6e - invalid. */
826/* Opcode VEX.66.0F38 0x6f - invalid. */
827
828/* Opcode VEX.66.0F38 0x70 - invalid. */
829/* Opcode VEX.66.0F38 0x71 - invalid. */
830/* Opcode VEX.66.0F38 0x72 - invalid. */
831/* Opcode VEX.66.0F38 0x73 - invalid. */
832/* Opcode VEX.66.0F38 0x74 - invalid. */
833/* Opcode VEX.66.0F38 0x75 - invalid. */
834/* Opcode VEX.66.0F38 0x76 - invalid. */
835/* Opcode VEX.66.0F38 0x77 - invalid. */
836/** Opcode VEX.66.0F38 0x78. */
837FNIEMOP_STUB(iemOp_vpboardcastb_Vx_Wx);
838/** Opcode VEX.66.0F38 0x79. */
839FNIEMOP_STUB(iemOp_vpboardcastw_Vx_Wx);
840/* Opcode VEX.66.0F38 0x7a - invalid. */
841/* Opcode VEX.66.0F38 0x7b - invalid. */
842/* Opcode VEX.66.0F38 0x7c - invalid. */
843/* Opcode VEX.66.0F38 0x7d - invalid. */
844/* Opcode VEX.66.0F38 0x7e - invalid. */
845/* Opcode VEX.66.0F38 0x7f - invalid. */
846
847/* Opcode VEX.66.0F38 0x80 - invalid (legacy only). */
848/* Opcode VEX.66.0F38 0x81 - invalid (legacy only). */
849/* Opcode VEX.66.0F38 0x82 - invalid (legacy only). */
850/* Opcode VEX.66.0F38 0x83 - invalid. */
851/* Opcode VEX.66.0F38 0x84 - invalid. */
852/* Opcode VEX.66.0F38 0x85 - invalid. */
853/* Opcode VEX.66.0F38 0x86 - invalid. */
854/* Opcode VEX.66.0F38 0x87 - invalid. */
855/* Opcode VEX.66.0F38 0x88 - invalid. */
856/* Opcode VEX.66.0F38 0x89 - invalid. */
857/* Opcode VEX.66.0F38 0x8a - invalid. */
858/* Opcode VEX.66.0F38 0x8b - invalid. */
859/** Opcode VEX.66.0F38 0x8c. */
860FNIEMOP_STUB(iemOp_vpmaskmovd_q_Vx_Hx_Mx);
861/* Opcode VEX.66.0F38 0x8d - invalid. */
862/** Opcode VEX.66.0F38 0x8e. */
863FNIEMOP_STUB(iemOp_vpmaskmovd_q_Mx_Vx_Hx);
864/* Opcode VEX.66.0F38 0x8f - invalid. */
865
866/** Opcode VEX.66.0F38 0x90 (vex only). */
867FNIEMOP_STUB(iemOp_vgatherdd_q_Vx_Hx_Wx);
868/** Opcode VEX.66.0F38 0x91 (vex only). */
869FNIEMOP_STUB(iemOp_vgatherqd_q_Vx_Hx_Wx);
870/** Opcode VEX.66.0F38 0x92 (vex only). */
871FNIEMOP_STUB(iemOp_vgatherdps_d_Vx_Hx_Wx);
872/** Opcode VEX.66.0F38 0x93 (vex only). */
873FNIEMOP_STUB(iemOp_vgatherqps_d_Vx_Hx_Wx);
874/* Opcode VEX.66.0F38 0x94 - invalid. */
875/* Opcode VEX.66.0F38 0x95 - invalid. */
876/** Opcode VEX.66.0F38 0x96 (vex only). */
877FNIEMOP_STUB(iemOp_vfmaddsub132ps_q_Vx_Hx_Wx);
878/** Opcode VEX.66.0F38 0x97 (vex only). */
879FNIEMOP_STUB(iemOp_vfmsubadd132ps_d_Vx_Hx_Wx);
880/** Opcode VEX.66.0F38 0x98 (vex only). */
881FNIEMOP_STUB(iemOp_vfmadd132ps_d_Vx_Hx_Wx);
882/** Opcode VEX.66.0F38 0x99 (vex only). */
883FNIEMOP_STUB(iemOp_vfmadd132ss_d_Vx_Hx_Wx);
884/** Opcode VEX.66.0F38 0x9a (vex only). */
885FNIEMOP_STUB(iemOp_vfmsub132ps_d_Vx_Hx_Wx);
886/** Opcode VEX.66.0F38 0x9b (vex only). */
887FNIEMOP_STUB(iemOp_vfmsub132ss_d_Vx_Hx_Wx);
888/** Opcode VEX.66.0F38 0x9c (vex only). */
889FNIEMOP_STUB(iemOp_vfnmadd132ps_d_Vx_Hx_Wx);
890/** Opcode VEX.66.0F38 0x9d (vex only). */
891FNIEMOP_STUB(iemOp_vfnmadd132ss_d_Vx_Hx_Wx);
892/** Opcode VEX.66.0F38 0x9e (vex only). */
893FNIEMOP_STUB(iemOp_vfnmsub132ps_d_Vx_Hx_Wx);
894/** Opcode VEX.66.0F38 0x9f (vex only). */
895FNIEMOP_STUB(iemOp_vfnmsub132ss_d_Vx_Hx_Wx);
896
897/* Opcode VEX.66.0F38 0xa0 - invalid. */
898/* Opcode VEX.66.0F38 0xa1 - invalid. */
899/* Opcode VEX.66.0F38 0xa2 - invalid. */
900/* Opcode VEX.66.0F38 0xa3 - invalid. */
901/* Opcode VEX.66.0F38 0xa4 - invalid. */
902/* Opcode VEX.66.0F38 0xa5 - invalid. */
903/** Opcode VEX.66.0F38 0xa6 (vex only). */
904FNIEMOP_STUB(iemOp_vfmaddsub213ps_d_Vx_Hx_Wx);
905/** Opcode VEX.66.0F38 0xa7 (vex only). */
906FNIEMOP_STUB(iemOp_vfmsubadd213ps_d_Vx_Hx_Wx);
907/** Opcode VEX.66.0F38 0xa8 (vex only). */
908FNIEMOP_STUB(iemOp_vfmadd213ps_d_Vx_Hx_Wx);
909/** Opcode VEX.66.0F38 0xa9 (vex only). */
910FNIEMOP_STUB(iemOp_vfmadd213ss_d_Vx_Hx_Wx);
911/** Opcode VEX.66.0F38 0xaa (vex only). */
912FNIEMOP_STUB(iemOp_vfmsub213ps_d_Vx_Hx_Wx);
913/** Opcode VEX.66.0F38 0xab (vex only). */
914FNIEMOP_STUB(iemOp_vfmsub213ss_d_Vx_Hx_Wx);
915/** Opcode VEX.66.0F38 0xac (vex only). */
916FNIEMOP_STUB(iemOp_vfnmadd213ps_d_Vx_Hx_Wx);
917/** Opcode VEX.66.0F38 0xad (vex only). */
918FNIEMOP_STUB(iemOp_vfnmadd213ss_d_Vx_Hx_Wx);
919/** Opcode VEX.66.0F38 0xae (vex only). */
920FNIEMOP_STUB(iemOp_vfnmsub213ps_d_Vx_Hx_Wx);
921/** Opcode VEX.66.0F38 0xaf (vex only). */
922FNIEMOP_STUB(iemOp_vfnmsub213ss_d_Vx_Hx_Wx);
923
924/* Opcode VEX.66.0F38 0xb0 - invalid. */
925/* Opcode VEX.66.0F38 0xb1 - invalid. */
926/* Opcode VEX.66.0F38 0xb2 - invalid. */
927/* Opcode VEX.66.0F38 0xb3 - invalid. */
928/* Opcode VEX.66.0F38 0xb4 - invalid. */
929/* Opcode VEX.66.0F38 0xb5 - invalid. */
930/** Opcode VEX.66.0F38 0xb6 (vex only). */
931FNIEMOP_STUB(iemOp_vfmaddsub231ps_d_Vx_Hx_Wx);
932/** Opcode VEX.66.0F38 0xb7 (vex only). */
933FNIEMOP_STUB(iemOp_vfmsubadd231ps_d_Vx_Hx_Wx);
934/** Opcode VEX.66.0F38 0xb8 (vex only). */
935FNIEMOP_STUB(iemOp_vfmadd231ps_d_Vx_Hx_Wx);
936/** Opcode VEX.66.0F38 0xb9 (vex only). */
937FNIEMOP_STUB(iemOp_vfmadd231ss_d_Vx_Hx_Wx);
938/** Opcode VEX.66.0F38 0xba (vex only). */
939FNIEMOP_STUB(iemOp_vfmsub231ps_d_Vx_Hx_Wx);
940/** Opcode VEX.66.0F38 0xbb (vex only). */
941FNIEMOP_STUB(iemOp_vfmsub231ss_d_Vx_Hx_Wx);
942/** Opcode VEX.66.0F38 0xbc (vex only). */
943FNIEMOP_STUB(iemOp_vfnmadd231ps_d_Vx_Hx_Wx);
944/** Opcode VEX.66.0F38 0xbd (vex only). */
945FNIEMOP_STUB(iemOp_vfnmadd231ss_d_Vx_Hx_Wx);
946/** Opcode VEX.66.0F38 0xbe (vex only). */
947FNIEMOP_STUB(iemOp_vfnmsub231ps_d_Vx_Hx_Wx);
948/** Opcode VEX.66.0F38 0xbf (vex only). */
949FNIEMOP_STUB(iemOp_vfnmsub231ss_d_Vx_Hx_Wx);
950
951/* Opcode VEX.0F38 0xc0 - invalid. */
952/* Opcode VEX.66.0F38 0xc0 - invalid. */
953/* Opcode VEX.0F38 0xc1 - invalid. */
954/* Opcode VEX.66.0F38 0xc1 - invalid. */
955/* Opcode VEX.0F38 0xc2 - invalid. */
956/* Opcode VEX.66.0F38 0xc2 - invalid. */
957/* Opcode VEX.0F38 0xc3 - invalid. */
958/* Opcode VEX.66.0F38 0xc3 - invalid. */
959/* Opcode VEX.0F38 0xc4 - invalid. */
960/* Opcode VEX.66.0F38 0xc4 - invalid. */
961/* Opcode VEX.0F38 0xc5 - invalid. */
962/* Opcode VEX.66.0F38 0xc5 - invalid. */
963/* Opcode VEX.0F38 0xc6 - invalid. */
964/* Opcode VEX.66.0F38 0xc6 - invalid. */
965/* Opcode VEX.0F38 0xc7 - invalid. */
966/* Opcode VEX.66.0F38 0xc7 - invalid. */
967/** Opcode VEX.0F38 0xc8. */
968FNIEMOP_STUB(iemOp_vsha1nexte_Vdq_Wdq);
969/* Opcode VEX.66.0F38 0xc8 - invalid. */
970/** Opcode VEX.0F38 0xc9. */
971FNIEMOP_STUB(iemOp_vsha1msg1_Vdq_Wdq);
972/* Opcode VEX.66.0F38 0xc9 - invalid. */
973/** Opcode VEX.0F38 0xca. */
974FNIEMOP_STUB(iemOp_vsha1msg2_Vdq_Wdq);
975/* Opcode VEX.66.0F38 0xca - invalid. */
976/** Opcode VEX.0F38 0xcb. */
977FNIEMOP_STUB(iemOp_vsha256rnds2_Vdq_Wdq);
978/* Opcode VEX.66.0F38 0xcb - invalid. */
979/** Opcode VEX.0F38 0xcc. */
980FNIEMOP_STUB(iemOp_vsha256msg1_Vdq_Wdq);
981/* Opcode VEX.66.0F38 0xcc - invalid. */
982/** Opcode VEX.0F38 0xcd. */
983FNIEMOP_STUB(iemOp_vsha256msg2_Vdq_Wdq);
984/* Opcode VEX.66.0F38 0xcd - invalid. */
985/* Opcode VEX.0F38 0xce - invalid. */
986/* Opcode VEX.66.0F38 0xce - invalid. */
987/* Opcode VEX.0F38 0xcf - invalid. */
988/* Opcode VEX.66.0F38 0xcf - invalid. */
989
990/* Opcode VEX.66.0F38 0xd0 - invalid. */
991/* Opcode VEX.66.0F38 0xd1 - invalid. */
992/* Opcode VEX.66.0F38 0xd2 - invalid. */
993/* Opcode VEX.66.0F38 0xd3 - invalid. */
994/* Opcode VEX.66.0F38 0xd4 - invalid. */
995/* Opcode VEX.66.0F38 0xd5 - invalid. */
996/* Opcode VEX.66.0F38 0xd6 - invalid. */
997/* Opcode VEX.66.0F38 0xd7 - invalid. */
998/* Opcode VEX.66.0F38 0xd8 - invalid. */
999/* Opcode VEX.66.0F38 0xd9 - invalid. */
1000/* Opcode VEX.66.0F38 0xda - invalid. */
1001/** Opcode VEX.66.0F38 0xdb. */
1002FNIEMOP_STUB(iemOp_vaesimc_Vdq_Wdq);
1003/** Opcode VEX.66.0F38 0xdc. */
1004FNIEMOP_STUB(iemOp_vaesenc_Vdq_Wdq);
1005/** Opcode VEX.66.0F38 0xdd. */
1006FNIEMOP_STUB(iemOp_vaesenclast_Vdq_Wdq);
1007/** Opcode VEX.66.0F38 0xde. */
1008FNIEMOP_STUB(iemOp_vaesdec_Vdq_Wdq);
1009/** Opcode VEX.66.0F38 0xdf. */
1010FNIEMOP_STUB(iemOp_vaesdeclast_Vdq_Wdq);
1011
1012/* Opcode VEX.66.0F38 0xe0 - invalid. */
1013/* Opcode VEX.66.0F38 0xe1 - invalid. */
1014/* Opcode VEX.66.0F38 0xe2 - invalid. */
1015/* Opcode VEX.66.0F38 0xe3 - invalid. */
1016/* Opcode VEX.66.0F38 0xe4 - invalid. */
1017/* Opcode VEX.66.0F38 0xe5 - invalid. */
1018/* Opcode VEX.66.0F38 0xe6 - invalid. */
1019/* Opcode VEX.66.0F38 0xe7 - invalid. */
1020/* Opcode VEX.66.0F38 0xe8 - invalid. */
1021/* Opcode VEX.66.0F38 0xe9 - invalid. */
1022/* Opcode VEX.66.0F38 0xea - invalid. */
1023/* Opcode VEX.66.0F38 0xeb - invalid. */
1024/* Opcode VEX.66.0F38 0xec - invalid. */
1025/* Opcode VEX.66.0F38 0xed - invalid. */
1026/* Opcode VEX.66.0F38 0xee - invalid. */
1027/* Opcode VEX.66.0F38 0xef - invalid. */
1028
1029
1030/* Opcode VEX.0F38 0xf0 - invalid (legacy only). */
1031/* Opcode VEX.66.0F38 0xf0 - invalid (legacy only). */
1032/* Opcode VEX.F3.0F38 0xf0 - invalid. */
1033/* Opcode VEX.F2.0F38 0xf0 - invalid (legacy only). */
1034
1035/* Opcode VEX.0F38 0xf1 - invalid (legacy only). */
1036/* Opcode VEX.66.0F38 0xf1 - invalid (legacy only). */
1037/* Opcode VEX.F3.0F38 0xf1 - invalid. */
1038/* Opcode VEX.F2.0F38 0xf1 - invalid (legacy only). */
1039
1040/** Opcode VEX.0F38 0xf2 - ANDN (vex only). */
1041FNIEMOP_DEF(iemOp_andn_Gy_By_Ey)
1042{
1043 IEMOP_MNEMONIC3(VEX_RVM, ANDN, andn, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1044 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1)
1045 return iemOp_InvalidNeedRM(pVCpu);
1046 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_PF);
1047 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1048 if (IEM_IS_MODRM_REG_MODE(bRm))
1049 {
1050 /*
1051 * Register, register.
1052 */
1053 IEMOP_HLP_DONE_VEX_DECODING_L0();
1054 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1055 {
1056 IEM_MC_BEGIN(4, 0);
1057 IEM_MC_ARG(uint64_t *, pDst, 0);
1058 IEM_MC_ARG(uint64_t, uSrc1, 1);
1059 IEM_MC_ARG(uint64_t, uSrc2, 2);
1060 IEM_MC_ARG(uint32_t *, pEFlags, 3);
1061 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1062 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1063 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1064 IEM_MC_REF_EFLAGS(pEFlags);
1065 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
1066 pDst, uSrc1, uSrc2, pEFlags);
1067 IEM_MC_ADVANCE_RIP();
1068 IEM_MC_END();
1069 }
1070 else
1071 {
1072 IEM_MC_BEGIN(4, 0);
1073 IEM_MC_ARG(uint32_t *, pDst, 0);
1074 IEM_MC_ARG(uint32_t, uSrc1, 1);
1075 IEM_MC_ARG(uint32_t, uSrc2, 2);
1076 IEM_MC_ARG(uint32_t *, pEFlags, 3);
1077 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1078 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1079 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1080 IEM_MC_REF_EFLAGS(pEFlags);
1081 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
1082 pDst, uSrc1, uSrc2, pEFlags);
1083 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
1084 IEM_MC_ADVANCE_RIP();
1085 IEM_MC_END();
1086 }
1087 }
1088 else
1089 {
1090 /*
1091 * Register, memory.
1092 */
1093 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1094 {
1095 IEM_MC_BEGIN(4, 1);
1096 IEM_MC_ARG(uint64_t *, pDst, 0);
1097 IEM_MC_ARG(uint64_t, uSrc1, 1);
1098 IEM_MC_ARG(uint64_t, uSrc2, 2);
1099 IEM_MC_ARG(uint32_t *, pEFlags, 3);
1100 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1101 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1102 IEMOP_HLP_DONE_VEX_DECODING_L0();
1103 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1104 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1105 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1106 IEM_MC_REF_EFLAGS(pEFlags);
1107 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback),
1108 pDst, uSrc1, uSrc2, pEFlags);
1109 IEM_MC_ADVANCE_RIP();
1110 IEM_MC_END();
1111 }
1112 else
1113 {
1114 IEM_MC_BEGIN(4, 1);
1115 IEM_MC_ARG(uint32_t *, pDst, 0);
1116 IEM_MC_ARG(uint32_t, uSrc1, 1);
1117 IEM_MC_ARG(uint32_t, uSrc2, 2);
1118 IEM_MC_ARG(uint32_t *, pEFlags, 3);
1119 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1120 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1121 IEMOP_HLP_DONE_VEX_DECODING_L0();
1122 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1123 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1124 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
1125 IEM_MC_REF_EFLAGS(pEFlags);
1126 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u32, iemAImpl_andn_u32_fallback),
1127 pDst, uSrc1, uSrc2, pEFlags);
1128 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
1129 IEM_MC_ADVANCE_RIP();
1130 IEM_MC_END();
1131 }
1132 }
1133 return VINF_SUCCESS;
1134}
1135
1136/* Opcode VEX.66.0F38 0xf2 - invalid. */
1137/* Opcode VEX.F3.0F38 0xf2 - invalid. */
1138/* Opcode VEX.F2.0F38 0xf2 - invalid. */
1139
1140
1141/* Opcode VEX.0F38 0xf3 - invalid. */
1142/* Opcode VEX.66.0F38 0xf3 - invalid. */
1143
1144/* Opcode VEX.F3.0F38 0xf3 /0 - invalid. */
1145
1146/** Body for the vex group 17 instructions. */
1147#define IEMOP_BODY_By_Ey(a_Instr) \
1148 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi1) \
1149 return iemOp_InvalidWithRM(pVCpu, bRm); /* decode memory variant? */ \
1150 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_PF); \
1151 if (IEM_IS_MODRM_REG_MODE(bRm)) \
1152 { \
1153 /* \
1154 * Register, register. \
1155 */ \
1156 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1157 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1158 { \
1159 IEM_MC_BEGIN(3, 0); \
1160 IEM_MC_ARG(uint64_t *, pDst, 0); \
1161 IEM_MC_ARG(uint64_t, uSrc, 1); \
1162 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1163 IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1164 IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1165 IEM_MC_REF_EFLAGS(pEFlags); \
1166 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
1167 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
1168 IEM_MC_ADVANCE_RIP(); \
1169 IEM_MC_END(); \
1170 } \
1171 else \
1172 { \
1173 IEM_MC_BEGIN(3, 0); \
1174 IEM_MC_ARG(uint32_t *, pDst, 0); \
1175 IEM_MC_ARG(uint32_t, uSrc, 1); \
1176 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1177 IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1178 IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1179 IEM_MC_REF_EFLAGS(pEFlags); \
1180 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
1181 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
1182 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1183 IEM_MC_ADVANCE_RIP(); \
1184 IEM_MC_END(); \
1185 } \
1186 } \
1187 else \
1188 { \
1189 /* \
1190 * Register, memory. \
1191 */ \
1192 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1193 { \
1194 IEM_MC_BEGIN(3, 1); \
1195 IEM_MC_ARG(uint64_t *, pDst, 0); \
1196 IEM_MC_ARG(uint64_t, uSrc, 1); \
1197 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1198 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1199 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1200 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1201 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1202 IEM_MC_REF_GREG_U64(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1203 IEM_MC_REF_EFLAGS(pEFlags); \
1204 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u64, \
1205 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc, pEFlags); \
1206 IEM_MC_ADVANCE_RIP(); \
1207 IEM_MC_END(); \
1208 } \
1209 else \
1210 { \
1211 IEM_MC_BEGIN(3, 1); \
1212 IEM_MC_ARG(uint32_t *, pDst, 0); \
1213 IEM_MC_ARG(uint32_t, uSrc, 1); \
1214 IEM_MC_ARG(uint32_t *, pEFlags, 2); \
1215 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1216 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1217 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1218 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1219 IEM_MC_REF_GREG_U32(pDst, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1220 IEM_MC_REF_EFLAGS(pEFlags); \
1221 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_ ## a_Instr ## _u32, \
1222 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc, pEFlags); \
1223 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1224 IEM_MC_ADVANCE_RIP(); \
1225 IEM_MC_END(); \
1226 } \
1227 } \
1228 return VINF_SUCCESS
1229
1230
1231/* Opcode VEX.F3.0F38 0xf3 /1. */
1232/** @opcode /1
1233 * @opmaps vexgrp17 */
1234FNIEMOP_DEF_1(iemOp_VGrp17_blsr_By_Ey, uint8_t, bRm)
1235{
1236 IEMOP_MNEMONIC2(VEX_VM, BLSR, blsr, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1237 IEMOP_BODY_By_Ey(blsr);
1238}
1239
1240
1241/* Opcode VEX.F3.0F38 0xf3 /2. */
1242/** @opcode /2
1243 * @opmaps vexgrp17 */
1244FNIEMOP_DEF_1(iemOp_VGrp17_blsmsk_By_Ey, uint8_t, bRm)
1245{
1246 IEMOP_MNEMONIC2(VEX_VM, BLSMSK, blsmsk, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1247 IEMOP_BODY_By_Ey(blsmsk);
1248}
1249
1250
1251/* Opcode VEX.F3.0F38 0xf3 /3. */
1252/** @opcode /3
1253 * @opmaps vexgrp17 */
1254FNIEMOP_DEF_1(iemOp_VGrp17_blsi_By_Ey, uint8_t, bRm)
1255{
1256 IEMOP_MNEMONIC2(VEX_VM, BLSI, blsi, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1257 IEMOP_BODY_By_Ey(blsi);
1258}
1259
1260
1261/* Opcode VEX.F3.0F38 0xf3 /4 - invalid. */
1262/* Opcode VEX.F3.0F38 0xf3 /5 - invalid. */
1263/* Opcode VEX.F3.0F38 0xf3 /6 - invalid. */
1264/* Opcode VEX.F3.0F38 0xf3 /7 - invalid. */
1265
1266/**
1267 * Group 17 jump table for the VEX.F3 variant.
1268 */
1269IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =
1270{
1271 /* /0 */ iemOp_InvalidWithRM,
1272 /* /1 */ iemOp_VGrp17_blsr_By_Ey,
1273 /* /2 */ iemOp_VGrp17_blsmsk_By_Ey,
1274 /* /3 */ iemOp_VGrp17_blsi_By_Ey,
1275 /* /4 */ iemOp_InvalidWithRM,
1276 /* /5 */ iemOp_InvalidWithRM,
1277 /* /6 */ iemOp_InvalidWithRM,
1278 /* /7 */ iemOp_InvalidWithRM
1279};
1280AssertCompile(RT_ELEMENTS(g_apfnVexGroup17_f3) == 8);
1281
1282/** Opcode VEX.F3.0F38 0xf3 - invalid (vex only - group 17). */
1283FNIEMOP_DEF(iemOp_VGrp17_f3)
1284{
1285 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1286 return FNIEMOP_CALL_1(g_apfnVexGroup17_f3[IEM_GET_MODRM_REG_8(bRm)], bRm);
1287}
1288
1289/* Opcode VEX.F2.0F38 0xf3 - invalid (vex only - group 17). */
1290
1291
1292/* Opcode VEX.0F38 0xf4 - invalid. */
1293/* Opcode VEX.66.0F38 0xf4 - invalid. */
1294/* Opcode VEX.F3.0F38 0xf4 - invalid. */
1295/* Opcode VEX.F2.0F38 0xf4 - invalid. */
1296
1297/** Body for BZHI, BEXTR, ++; assumes VEX.L must be 0. */
1298#define IEMOP_BODY_Gy_Ey_By(a_Instr, a_fFeatureMember, a_fUndefFlags) \
1299 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
1300 return iemOp_InvalidNeedRM(pVCpu); \
1301 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
1302 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1303 if (IEM_IS_MODRM_REG_MODE(bRm)) \
1304 { \
1305 /* \
1306 * Register, register. \
1307 */ \
1308 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1309 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1310 { \
1311 IEM_MC_BEGIN(4, 0); \
1312 IEM_MC_ARG(uint64_t *, pDst, 0); \
1313 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1314 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1315 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1316 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1317 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1318 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1319 IEM_MC_REF_EFLAGS(pEFlags); \
1320 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1321 iemAImpl_ ## a_Instr ## _u64_fallback), \
1322 pDst, uSrc1, uSrc2, pEFlags); \
1323 IEM_MC_ADVANCE_RIP(); \
1324 IEM_MC_END(); \
1325 } \
1326 else \
1327 { \
1328 IEM_MC_BEGIN(4, 0); \
1329 IEM_MC_ARG(uint32_t *, pDst, 0); \
1330 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1331 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1332 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1333 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1334 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1335 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1336 IEM_MC_REF_EFLAGS(pEFlags); \
1337 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1338 iemAImpl_ ## a_Instr ## _u32_fallback), \
1339 pDst, uSrc1, uSrc2, pEFlags); \
1340 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1341 IEM_MC_ADVANCE_RIP(); \
1342 IEM_MC_END(); \
1343 } \
1344 } \
1345 else \
1346 { \
1347 /* \
1348 * Register, memory. \
1349 */ \
1350 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1351 { \
1352 IEM_MC_BEGIN(4, 1); \
1353 IEM_MC_ARG(uint64_t *, pDst, 0); \
1354 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1355 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1356 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1357 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1358 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1359 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1360 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1361 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1362 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1363 IEM_MC_REF_EFLAGS(pEFlags); \
1364 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1365 iemAImpl_ ## a_Instr ## _u64_fallback), \
1366 pDst, uSrc1, uSrc2, pEFlags); \
1367 IEM_MC_ADVANCE_RIP(); \
1368 IEM_MC_END(); \
1369 } \
1370 else \
1371 { \
1372 IEM_MC_BEGIN(4, 1); \
1373 IEM_MC_ARG(uint32_t *, pDst, 0); \
1374 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1375 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1376 IEM_MC_ARG(uint32_t *, pEFlags, 3); \
1377 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1378 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1379 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1380 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1381 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1382 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1383 IEM_MC_REF_EFLAGS(pEFlags); \
1384 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1385 iemAImpl_ ## a_Instr ## _u32_fallback), \
1386 pDst, uSrc1, uSrc2, pEFlags); \
1387 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1388 IEM_MC_ADVANCE_RIP(); \
1389 IEM_MC_END(); \
1390 } \
1391 } \
1392 return VINF_SUCCESS
1393
1394/** Body for SARX, SHLX, SHRX; assumes VEX.L must be 0. */
1395#define IEMOP_BODY_Gy_Ey_By_NoEflags(a_Instr, a_fFeatureMember, a_fUndefFlags) \
1396 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
1397 return iemOp_InvalidNeedRM(pVCpu); \
1398 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fUndefFlags); \
1399 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1400 if (IEM_IS_MODRM_REG_MODE(bRm)) \
1401 { \
1402 /* \
1403 * Register, register. \
1404 */ \
1405 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1406 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1407 { \
1408 IEM_MC_BEGIN(3, 0); \
1409 IEM_MC_ARG(uint64_t *, pDst, 0); \
1410 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1411 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1412 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1413 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1414 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1415 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1416 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1417 IEM_MC_ADVANCE_RIP(); \
1418 IEM_MC_END(); \
1419 } \
1420 else \
1421 { \
1422 IEM_MC_BEGIN(3, 0); \
1423 IEM_MC_ARG(uint32_t *, pDst, 0); \
1424 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1425 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1426 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1427 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1428 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1429 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1430 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1431 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1432 IEM_MC_ADVANCE_RIP(); \
1433 IEM_MC_END(); \
1434 } \
1435 } \
1436 else \
1437 { \
1438 /* \
1439 * Register, memory. \
1440 */ \
1441 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1442 { \
1443 IEM_MC_BEGIN(3, 1); \
1444 IEM_MC_ARG(uint64_t *, pDst, 0); \
1445 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1446 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1447 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1448 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1449 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1450 IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1451 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1452 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1453 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \
1454 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1455 IEM_MC_ADVANCE_RIP(); \
1456 IEM_MC_END(); \
1457 } \
1458 else \
1459 { \
1460 IEM_MC_BEGIN(3, 1); \
1461 IEM_MC_ARG(uint32_t *, pDst, 0); \
1462 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1463 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1464 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1465 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1466 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1467 IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1468 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1469 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1470 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u32, \
1471 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1472 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1473 IEM_MC_ADVANCE_RIP(); \
1474 IEM_MC_END(); \
1475 } \
1476 } \
1477 return VINF_SUCCESS
1478
1479/** Opcode VEX.0F38 0xf5 (vex only). */
1480FNIEMOP_DEF(iemOp_bzhi_Gy_Ey_By)
1481{
1482 IEMOP_MNEMONIC3(VEX_RMV, BZHI, bzhi, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1483 IEMOP_BODY_Gy_Ey_By(bzhi, fBmi2, X86_EFL_AF | X86_EFL_PF);
1484}
1485
1486/* Opcode VEX.66.0F38 0xf5 - invalid. */
1487
1488/** Body for PDEP and PEXT (similar to ANDN, except no EFLAGS). */
1489#define IEMOP_BODY_Gy_By_Ey_NoEflags(a_Instr, a_fFeatureMember) \
1490 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeatureMember) \
1491 return iemOp_InvalidNeedRM(pVCpu); \
1492 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
1493 if (IEM_IS_MODRM_REG_MODE(bRm)) \
1494 { \
1495 /* \
1496 * Register, register. \
1497 */ \
1498 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1499 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1500 { \
1501 IEM_MC_BEGIN(3, 0); \
1502 IEM_MC_ARG(uint64_t *, pDst, 0); \
1503 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1504 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1505 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1506 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1507 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1508 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1509 iemAImpl_ ## a_Instr ## _u64, \
1510 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1511 IEM_MC_ADVANCE_RIP(); \
1512 IEM_MC_END(); \
1513 } \
1514 else \
1515 { \
1516 IEM_MC_BEGIN(3, 0); \
1517 IEM_MC_ARG(uint32_t *, pDst, 0); \
1518 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1519 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1520 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1521 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1522 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); \
1523 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1524 iemAImpl_ ## a_Instr ## _u32, \
1525 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1526 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1527 IEM_MC_ADVANCE_RIP(); \
1528 IEM_MC_END(); \
1529 } \
1530 } \
1531 else \
1532 { \
1533 /* \
1534 * Register, memory. \
1535 */ \
1536 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W) \
1537 { \
1538 IEM_MC_BEGIN(3, 1); \
1539 IEM_MC_ARG(uint64_t *, pDst, 0); \
1540 IEM_MC_ARG(uint64_t, uSrc1, 1); \
1541 IEM_MC_ARG(uint64_t, uSrc2, 2); \
1542 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1543 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1544 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1545 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1546 IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1547 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1548 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1549 iemAImpl_ ## a_Instr ## _u64, \
1550 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \
1551 IEM_MC_ADVANCE_RIP(); \
1552 IEM_MC_END(); \
1553 } \
1554 else \
1555 { \
1556 IEM_MC_BEGIN(3, 1); \
1557 IEM_MC_ARG(uint32_t *, pDst, 0); \
1558 IEM_MC_ARG(uint32_t, uSrc1, 1); \
1559 IEM_MC_ARG(uint32_t, uSrc2, 2); \
1560 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
1561 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
1562 IEMOP_HLP_DONE_VEX_DECODING_L0(); \
1563 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
1564 IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu)); \
1565 IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
1566 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, \
1567 iemAImpl_ ## a_Instr ## _u32, \
1568 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \
1569 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst); \
1570 IEM_MC_ADVANCE_RIP(); \
1571 IEM_MC_END(); \
1572 } \
1573 } \
1574 return VINF_SUCCESS;
1575
1576
1577/** Opcode VEX.F3.0F38 0xf5 (vex only). */
1578FNIEMOP_DEF(iemOp_pext_Gy_By_Ey)
1579{
1580 IEMOP_MNEMONIC3(VEX_RVM, PEXT, pext, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1581 IEMOP_BODY_Gy_By_Ey_NoEflags(pext, fBmi2);
1582}
1583
1584
1585/** Opcode VEX.F2.0F38 0xf5 (vex only). */
1586FNIEMOP_DEF(iemOp_pdep_Gy_By_Ey)
1587{
1588 IEMOP_MNEMONIC3(VEX_RVM, PDEP, pdep, Gy, By, Ey, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1589 IEMOP_BODY_Gy_By_Ey_NoEflags(pdep, fBmi2);
1590}
1591
1592
1593/* Opcode VEX.0F38 0xf6 - invalid. */
1594/* Opcode VEX.66.0F38 0xf6 - invalid (legacy only). */
1595/* Opcode VEX.F3.0F38 0xf6 - invalid (legacy only). */
1596
1597
1598/** Opcode VEX.F2.0F38 0xf6 (vex only) */
1599FNIEMOP_DEF(iemOp_mulx_By_Gy_rDX_Ey)
1600{
1601 IEMOP_MNEMONIC4(VEX_RVM, MULX, mulx, Gy, By, Ey, rDX, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1602 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi2)
1603 return iemOp_InvalidNeedRM(pVCpu);
1604 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1605 if (IEM_IS_MODRM_REG_MODE(bRm))
1606 {
1607 /*
1608 * Register, register.
1609 */
1610 IEMOP_HLP_DONE_VEX_DECODING_L0();
1611 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1612 {
1613 IEM_MC_BEGIN(4, 0);
1614 IEM_MC_ARG(uint64_t *, pDst1, 0);
1615 IEM_MC_ARG(uint64_t *, pDst2, 1);
1616 IEM_MC_ARG(uint64_t, uSrc1, 2);
1617 IEM_MC_ARG(uint64_t, uSrc2, 3);
1618 IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1619 IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1620 IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1621 IEM_MC_FETCH_GREG_U64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1622 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1623 pDst1, pDst2, uSrc1, uSrc2);
1624 IEM_MC_ADVANCE_RIP();
1625 IEM_MC_END();
1626 }
1627 else
1628 {
1629 IEM_MC_BEGIN(4, 0);
1630 IEM_MC_ARG(uint32_t *, pDst1, 0);
1631 IEM_MC_ARG(uint32_t *, pDst2, 1);
1632 IEM_MC_ARG(uint32_t, uSrc1, 2);
1633 IEM_MC_ARG(uint32_t, uSrc2, 3);
1634 IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1635 IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1636 IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1637 IEM_MC_FETCH_GREG_U32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
1638 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1639 pDst1, pDst2, uSrc1, uSrc2);
1640 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1641 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1642 IEM_MC_ADVANCE_RIP();
1643 IEM_MC_END();
1644 }
1645 }
1646 else
1647 {
1648 /*
1649 * Register, memory.
1650 */
1651 if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
1652 {
1653 IEM_MC_BEGIN(4, 1);
1654 IEM_MC_ARG(uint64_t *, pDst1, 0);
1655 IEM_MC_ARG(uint64_t *, pDst2, 1);
1656 IEM_MC_ARG(uint64_t, uSrc1, 2);
1657 IEM_MC_ARG(uint64_t, uSrc2, 3);
1658 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1659 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1660 IEMOP_HLP_DONE_VEX_DECODING_L0();
1661 IEM_MC_FETCH_MEM_U64(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1662 IEM_MC_FETCH_GREG_U64(uSrc1, X86_GREG_xDX);
1663 IEM_MC_REF_GREG_U64(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1664 IEM_MC_REF_GREG_U64(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1665 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback),
1666 pDst1, pDst2, uSrc1, uSrc2);
1667 IEM_MC_ADVANCE_RIP();
1668 IEM_MC_END();
1669 }
1670 else
1671 {
1672 IEM_MC_BEGIN(4, 1);
1673 IEM_MC_ARG(uint32_t *, pDst1, 0);
1674 IEM_MC_ARG(uint32_t *, pDst2, 1);
1675 IEM_MC_ARG(uint32_t, uSrc1, 2);
1676 IEM_MC_ARG(uint32_t, uSrc2, 3);
1677 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1678 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1679 IEMOP_HLP_DONE_VEX_DECODING_L0();
1680 IEM_MC_FETCH_MEM_U32(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1681 IEM_MC_FETCH_GREG_U32(uSrc1, X86_GREG_xDX);
1682 IEM_MC_REF_GREG_U32(pDst2, IEM_GET_EFFECTIVE_VVVV(pVCpu));
1683 IEM_MC_REF_GREG_U32(pDst1, IEM_GET_MODRM_REG(pVCpu, bRm));
1684 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback),
1685 pDst1, pDst2, uSrc1, uSrc2);
1686 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst2);
1687 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst1);
1688 IEM_MC_ADVANCE_RIP();
1689 IEM_MC_END();
1690 }
1691 }
1692 return VINF_SUCCESS;
1693}
1694
1695
1696/** Opcode VEX.0F38 0xf7 (vex only). */
1697FNIEMOP_DEF(iemOp_bextr_Gy_Ey_By)
1698{
1699 IEMOP_MNEMONIC3(VEX_RMV, BEXTR, bextr, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1700 IEMOP_BODY_Gy_Ey_By(bextr, fBmi1, X86_EFL_SF | X86_EFL_AF | X86_EFL_PF);
1701}
1702
1703
1704/** Opcode VEX.66.0F38 0xf7 (vex only). */
1705FNIEMOP_DEF(iemOp_shlx_Gy_Ey_By)
1706{
1707 IEMOP_MNEMONIC3(VEX_RMV, SHLX, shlx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1708 IEMOP_BODY_Gy_Ey_By_NoEflags(shlx, fBmi2, 0);
1709}
1710
1711
1712/** Opcode VEX.F3.0F38 0xf7 (vex only). */
1713FNIEMOP_DEF(iemOp_sarx_Gy_Ey_By)
1714{
1715 IEMOP_MNEMONIC3(VEX_RMV, SARX, sarx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1716 IEMOP_BODY_Gy_Ey_By_NoEflags(sarx, fBmi2, 0);
1717}
1718
1719
1720/** Opcode VEX.F2.0F38 0xf7 (vex only). */
1721FNIEMOP_DEF(iemOp_shrx_Gy_Ey_By)
1722{
1723 IEMOP_MNEMONIC3(VEX_RMV, SHRX, shrx, Gy, Ey, By, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO);
1724 IEMOP_BODY_Gy_Ey_By_NoEflags(shrx, fBmi2, 0);
1725}
1726
1727/* Opcode VEX.0F38 0xf8 - invalid. */
1728/* Opcode VEX.66.0F38 0xf8 - invalid. */
1729/* Opcode VEX.F3.0F38 0xf8 - invalid. */
1730/* Opcode VEX.F2.0F38 0xf8 - invalid. */
1731
1732/* Opcode VEX.0F38 0xf9 - invalid. */
1733/* Opcode VEX.66.0F38 0xf9 - invalid. */
1734/* Opcode VEX.F3.0F38 0xf9 - invalid. */
1735/* Opcode VEX.F2.0F38 0xf9 - invalid. */
1736
1737/* Opcode VEX.0F38 0xfa - invalid. */
1738/* Opcode VEX.66.0F38 0xfa - invalid. */
1739/* Opcode VEX.F3.0F38 0xfa - invalid. */
1740/* Opcode VEX.F2.0F38 0xfa - invalid. */
1741
1742/* Opcode VEX.0F38 0xfb - invalid. */
1743/* Opcode VEX.66.0F38 0xfb - invalid. */
1744/* Opcode VEX.F3.0F38 0xfb - invalid. */
1745/* Opcode VEX.F2.0F38 0xfb - invalid. */
1746
1747/* Opcode VEX.0F38 0xfc - invalid. */
1748/* Opcode VEX.66.0F38 0xfc - invalid. */
1749/* Opcode VEX.F3.0F38 0xfc - invalid. */
1750/* Opcode VEX.F2.0F38 0xfc - invalid. */
1751
1752/* Opcode VEX.0F38 0xfd - invalid. */
1753/* Opcode VEX.66.0F38 0xfd - invalid. */
1754/* Opcode VEX.F3.0F38 0xfd - invalid. */
1755/* Opcode VEX.F2.0F38 0xfd - invalid. */
1756
1757/* Opcode VEX.0F38 0xfe - invalid. */
1758/* Opcode VEX.66.0F38 0xfe - invalid. */
1759/* Opcode VEX.F3.0F38 0xfe - invalid. */
1760/* Opcode VEX.F2.0F38 0xfe - invalid. */
1761
1762/* Opcode VEX.0F38 0xff - invalid. */
1763/* Opcode VEX.66.0F38 0xff - invalid. */
1764/* Opcode VEX.F3.0F38 0xff - invalid. */
1765/* Opcode VEX.F2.0F38 0xff - invalid. */
1766
1767
1768/**
1769 * VEX opcode map \#2.
1770 *
1771 * @sa g_apfnThreeByte0f38
1772 */
1773IEM_STATIC const PFNIEMOP g_apfnVexMap2[] =
1774{
1775 /* no prefix, 066h prefix f3h prefix, f2h prefix */
1776 /* 0x00 */ iemOp_InvalidNeedRM, iemOp_vpshufb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1777 /* 0x01 */ iemOp_InvalidNeedRM, iemOp_vphaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1778 /* 0x02 */ iemOp_InvalidNeedRM, iemOp_vphaddd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1779 /* 0x03 */ iemOp_InvalidNeedRM, iemOp_vphaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1780 /* 0x04 */ iemOp_InvalidNeedRM, iemOp_vpmaddubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1781 /* 0x05 */ iemOp_InvalidNeedRM, iemOp_vphsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1782 /* 0x06 */ iemOp_InvalidNeedRM, iemOp_vphsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1783 /* 0x07 */ iemOp_InvalidNeedRM, iemOp_vphsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1784 /* 0x08 */ iemOp_InvalidNeedRM, iemOp_vpsignb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1785 /* 0x09 */ iemOp_InvalidNeedRM, iemOp_vpsignw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1786 /* 0x0a */ iemOp_InvalidNeedRM, iemOp_vpsignd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1787 /* 0x0b */ iemOp_InvalidNeedRM, iemOp_vpmulhrsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1788 /* 0x0c */ iemOp_InvalidNeedRM, iemOp_vpermilps_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1789 /* 0x0d */ iemOp_InvalidNeedRM, iemOp_vpermilpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1790 /* 0x0e */ iemOp_InvalidNeedRM, iemOp_vtestps_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1791 /* 0x0f */ iemOp_InvalidNeedRM, iemOp_vtestpd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1792
1793 /* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRM),
1794 /* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRM),
1795 /* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRM),
1796 /* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRM),
1797 /* 0x14 */ IEMOP_X4(iemOp_InvalidNeedRM),
1798 /* 0x15 */ IEMOP_X4(iemOp_InvalidNeedRM),
1799 /* 0x16 */ iemOp_InvalidNeedRM, iemOp_vpermps_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1800 /* 0x17 */ iemOp_InvalidNeedRM, iemOp_vptest_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1801 /* 0x18 */ iemOp_InvalidNeedRM, iemOp_vbroadcastss_Vx_Wd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1802 /* 0x19 */ iemOp_InvalidNeedRM, iemOp_vbroadcastsd_Vqq_Wq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1803 /* 0x1a */ iemOp_InvalidNeedRM, iemOp_vbroadcastf128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1804 /* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
1805 /* 0x1c */ iemOp_InvalidNeedRM, iemOp_vpabsb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1806 /* 0x1d */ iemOp_InvalidNeedRM, iemOp_vpabsw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1807 /* 0x1e */ iemOp_InvalidNeedRM, iemOp_vpabsd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1808 /* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
1809
1810 /* 0x20 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1811 /* 0x21 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1812 /* 0x22 */ iemOp_InvalidNeedRM, iemOp_vpmovsxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1813 /* 0x23 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1814 /* 0x24 */ iemOp_InvalidNeedRM, iemOp_vpmovsxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1815 /* 0x25 */ iemOp_InvalidNeedRM, iemOp_vpmovsxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1816 /* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
1817 /* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
1818 /* 0x28 */ iemOp_InvalidNeedRM, iemOp_vpmuldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1819 /* 0x29 */ iemOp_InvalidNeedRM, iemOp_vpcmpeqq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1820 /* 0x2a */ iemOp_InvalidNeedRM, iemOp_vmovntdqa_Vx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1821 /* 0x2b */ iemOp_InvalidNeedRM, iemOp_vpackusdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1822 /* 0x2c */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1823 /* 0x2d */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1824 /* 0x2e */ iemOp_InvalidNeedRM, iemOp_vmaskmovps_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1825 /* 0x2f */ iemOp_InvalidNeedRM, iemOp_vmaskmovpd_Mx_Hx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1826
1827 /* 0x30 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbw_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1828 /* 0x31 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbd_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1829 /* 0x32 */ iemOp_InvalidNeedRM, iemOp_vpmovzxbq_Vx_UxMw, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1830 /* 0x33 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwd_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1831 /* 0x34 */ iemOp_InvalidNeedRM, iemOp_vpmovzxwq_Vx_UxMd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1832 /* 0x35 */ iemOp_InvalidNeedRM, iemOp_vpmovzxdq_Vx_UxMq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1833 /* 0x36 */ iemOp_InvalidNeedRM, iemOp_vpermd_Vqq_Hqq_Wqq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1834 /* 0x37 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1835 /* 0x38 */ iemOp_InvalidNeedRM, iemOp_vpminsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1836 /* 0x39 */ iemOp_InvalidNeedRM, iemOp_vpminsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1837 /* 0x3a */ iemOp_InvalidNeedRM, iemOp_vpminuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1838 /* 0x3b */ iemOp_InvalidNeedRM, iemOp_vpminud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1839 /* 0x3c */ iemOp_InvalidNeedRM, iemOp_vpmaxsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1840 /* 0x3d */ iemOp_InvalidNeedRM, iemOp_vpmaxsd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1841 /* 0x3e */ iemOp_InvalidNeedRM, iemOp_vpmaxuw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1842 /* 0x3f */ iemOp_InvalidNeedRM, iemOp_vpmaxud_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1843
1844 /* 0x40 */ iemOp_InvalidNeedRM, iemOp_vpmulld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1845 /* 0x41 */ iemOp_InvalidNeedRM, iemOp_vphminposuw_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1846 /* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
1847 /* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
1848 /* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
1849 /* 0x45 */ iemOp_InvalidNeedRM, iemOp_vpsrlvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1850 /* 0x46 */ iemOp_InvalidNeedRM, iemOp_vsravd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1851 /* 0x47 */ iemOp_InvalidNeedRM, iemOp_vpsllvd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1852 /* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
1853 /* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
1854 /* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
1855 /* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
1856 /* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
1857 /* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
1858 /* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
1859 /* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
1860
1861 /* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRM),
1862 /* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRM),
1863 /* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRM),
1864 /* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRM),
1865 /* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRM),
1866 /* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRM),
1867 /* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRM),
1868 /* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRM),
1869 /* 0x58 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastd_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1870 /* 0x59 */ iemOp_InvalidNeedRM, iemOp_vpbroadcastq_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1871 /* 0x5a */ iemOp_InvalidNeedRM, iemOp_vbroadcasti128_Vqq_Mdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1872 /* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRM),
1873 /* 0x5c */ IEMOP_X4(iemOp_InvalidNeedRM),
1874 /* 0x5d */ IEMOP_X4(iemOp_InvalidNeedRM),
1875 /* 0x5e */ IEMOP_X4(iemOp_InvalidNeedRM),
1876 /* 0x5f */ IEMOP_X4(iemOp_InvalidNeedRM),
1877
1878 /* 0x60 */ IEMOP_X4(iemOp_InvalidNeedRM),
1879 /* 0x61 */ IEMOP_X4(iemOp_InvalidNeedRM),
1880 /* 0x62 */ IEMOP_X4(iemOp_InvalidNeedRM),
1881 /* 0x63 */ IEMOP_X4(iemOp_InvalidNeedRM),
1882 /* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRM),
1883 /* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRM),
1884 /* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRM),
1885 /* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRM),
1886 /* 0x68 */ IEMOP_X4(iemOp_InvalidNeedRM),
1887 /* 0x69 */ IEMOP_X4(iemOp_InvalidNeedRM),
1888 /* 0x6a */ IEMOP_X4(iemOp_InvalidNeedRM),
1889 /* 0x6b */ IEMOP_X4(iemOp_InvalidNeedRM),
1890 /* 0x6c */ IEMOP_X4(iemOp_InvalidNeedRM),
1891 /* 0x6d */ IEMOP_X4(iemOp_InvalidNeedRM),
1892 /* 0x6e */ IEMOP_X4(iemOp_InvalidNeedRM),
1893 /* 0x6f */ IEMOP_X4(iemOp_InvalidNeedRM),
1894
1895 /* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRM),
1896 /* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRM),
1897 /* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRM),
1898 /* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRM),
1899 /* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRM),
1900 /* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRM),
1901 /* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRM),
1902 /* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRM),
1903 /* 0x78 */ iemOp_InvalidNeedRM, iemOp_vpboardcastb_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1904 /* 0x79 */ iemOp_InvalidNeedRM, iemOp_vpboardcastw_Vx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1905 /* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
1906 /* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
1907 /* 0x7c */ IEMOP_X4(iemOp_InvalidNeedRM),
1908 /* 0x7d */ IEMOP_X4(iemOp_InvalidNeedRM),
1909 /* 0x7e */ IEMOP_X4(iemOp_InvalidNeedRM),
1910 /* 0x7f */ IEMOP_X4(iemOp_InvalidNeedRM),
1911
1912 /* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
1913 /* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
1914 /* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
1915 /* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
1916 /* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
1917 /* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
1918 /* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
1919 /* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
1920 /* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
1921 /* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
1922 /* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
1923 /* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
1924 /* 0x8c */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Vx_Hx_Mx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1925 /* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
1926 /* 0x8e */ iemOp_InvalidNeedRM, iemOp_vpmaskmovd_q_Mx_Vx_Hx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1927 /* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
1928
1929 /* 0x90 */ iemOp_InvalidNeedRM, iemOp_vgatherdd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1930 /* 0x91 */ iemOp_InvalidNeedRM, iemOp_vgatherqd_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1931 /* 0x92 */ iemOp_InvalidNeedRM, iemOp_vgatherdps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1932 /* 0x93 */ iemOp_InvalidNeedRM, iemOp_vgatherqps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1933 /* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
1934 /* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
1935 /* 0x96 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub132ps_q_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1936 /* 0x97 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1937 /* 0x98 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1938 /* 0x99 */ iemOp_InvalidNeedRM, iemOp_vfmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1939 /* 0x9a */ iemOp_InvalidNeedRM, iemOp_vfmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1940 /* 0x9b */ iemOp_InvalidNeedRM, iemOp_vfmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1941 /* 0x9c */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1942 /* 0x9d */ iemOp_InvalidNeedRM, iemOp_vfnmadd132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1943 /* 0x9e */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1944 /* 0x9f */ iemOp_InvalidNeedRM, iemOp_vfnmsub132ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1945
1946 /* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1947 /* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1948 /* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1949 /* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1950 /* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1951 /* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1952 /* 0xa6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1953 /* 0xa7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1954 /* 0xa8 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1955 /* 0xa9 */ iemOp_InvalidNeedRM, iemOp_vfmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1956 /* 0xaa */ iemOp_InvalidNeedRM, iemOp_vfmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1957 /* 0xab */ iemOp_InvalidNeedRM, iemOp_vfmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1958 /* 0xac */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1959 /* 0xad */ iemOp_InvalidNeedRM, iemOp_vfnmadd213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1960 /* 0xae */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1961 /* 0xaf */ iemOp_InvalidNeedRM, iemOp_vfnmsub213ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1962
1963 /* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1964 /* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1965 /* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1966 /* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1967 /* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1968 /* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1969 /* 0xb6 */ iemOp_InvalidNeedRM, iemOp_vfmaddsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1970 /* 0xb7 */ iemOp_InvalidNeedRM, iemOp_vfmsubadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1971 /* 0xb8 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1972 /* 0xb9 */ iemOp_InvalidNeedRM, iemOp_vfmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1973 /* 0xba */ iemOp_InvalidNeedRM, iemOp_vfmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1974 /* 0xbb */ iemOp_InvalidNeedRM, iemOp_vfmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1975 /* 0xbc */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1976 /* 0xbd */ iemOp_InvalidNeedRM, iemOp_vfnmadd231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1977 /* 0xbe */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ps_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1978 /* 0xbf */ iemOp_InvalidNeedRM, iemOp_vfnmsub231ss_d_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1979
1980 /* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1981 /* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1982 /* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRM),
1983 /* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
1984 /* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRM),
1985 /* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRM),
1986 /* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRM),
1987 /* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
1988 /* 0xc8 */ iemOp_vsha1nexte_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1989 /* 0xc9 */ iemOp_vsha1msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1990 /* 0xca */ iemOp_vsha1msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1991 /* 0xcb */ iemOp_vsha256rnds2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1992 /* 0xcc */ iemOp_vsha256msg1_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1993 /* 0xcd */ iemOp_vsha256msg2_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
1994 /* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
1995 /* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
1996
1997 /* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRM),
1998 /* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRM),
1999 /* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2000 /* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2001 /* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2002 /* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2003 /* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2004 /* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2005 /* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2006 /* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2007 /* 0xda */ IEMOP_X4(iemOp_InvalidNeedRM),
2008 /* 0xdb */ iemOp_InvalidNeedRM, iemOp_vaesimc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2009 /* 0xdc */ iemOp_InvalidNeedRM, iemOp_vaesenc_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2010 /* 0xdd */ iemOp_InvalidNeedRM, iemOp_vaesenclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2011 /* 0xde */ iemOp_InvalidNeedRM, iemOp_vaesdec_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2012 /* 0xdf */ iemOp_InvalidNeedRM, iemOp_vaesdeclast_Vdq_Wdq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2013
2014 /* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2015 /* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2016 /* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRM),
2017 /* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRM),
2018 /* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2019 /* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRM),
2020 /* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRM),
2021 /* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRM),
2022 /* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2023 /* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2024 /* 0xea */ IEMOP_X4(iemOp_InvalidNeedRM),
2025 /* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRM),
2026 /* 0xec */ IEMOP_X4(iemOp_InvalidNeedRM),
2027 /* 0xed */ IEMOP_X4(iemOp_InvalidNeedRM),
2028 /* 0xee */ IEMOP_X4(iemOp_InvalidNeedRM),
2029 /* 0xef */ IEMOP_X4(iemOp_InvalidNeedRM),
2030
2031 /* 0xf0 */ IEMOP_X4(iemOp_InvalidNeedRM),
2032 /* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRM),
2033 /* 0xf2 */ iemOp_andn_Gy_By_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2034 /* 0xf3 */ iemOp_VGrp17_f3, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
2035 /* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRM),
2036 /* 0xf5 */ iemOp_bzhi_Gy_Ey_By, iemOp_InvalidNeedRM, iemOp_pext_Gy_By_Ey, iemOp_pdep_Gy_By_Ey,
2037 /* 0xf6 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_mulx_By_Gy_rDX_Ey,
2038 /* 0xf7 */ iemOp_bextr_Gy_Ey_By, iemOp_shlx_Gy_Ey_By, iemOp_sarx_Gy_Ey_By, iemOp_shrx_Gy_Ey_By,
2039 /* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRM),
2040 /* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRM),
2041 /* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRM),
2042 /* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRM),
2043 /* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRM),
2044 /* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRM),
2045 /* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRM),
2046 /* 0xff */ IEMOP_X4(iemOp_InvalidNeedRM),
2047};
2048AssertCompile(RT_ELEMENTS(g_apfnVexMap2) == 1024);
2049
2050/** @} */
2051
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