IEMAllInstructionsVexMap3.cpp.h@ 97694

Last change on this file since 97694 was 97361, checked in by vboxsync, 2 years ago
VMM/IEM: Removed a lot of now unnecessary return statements, while keeping unnecessary break statements for the look of the think. Also added missing IEM_NOT_REACHED_DEFAULT_CASE_RET uses to try make sure all cases in the switches will return and we can skip the function (typically) return statement. bugref:9898
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File size: 46.0 KB

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1	/* $Id: IEMAllInstructionsVexMap3.cpp.h 97361 2022-11-01 02:02:24Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, 0x0f 0x3a map.
4	*
5	* @remarks IEMAllInstructionsThree0f3a.cpp.h is a VEX mirror of this file.
6	* Any update here is likely needed in that file too.
7	*/
8
9	/*
10	* Copyright (C) 2011-2022 Oracle and/or its affiliates.
11	*
12	* This file is part of VirtualBox base platform packages, as
13	* available from https://www.virtualbox.org.
14	*
15	* This program is free software; you can redistribute it and/or
16	* modify it under the terms of the GNU General Public License
17	* as published by the Free Software Foundation, in version 3 of the
18	* License.
19	*
20	* This program is distributed in the hope that it will be useful, but
21	* WITHOUT ANY WARRANTY; without even the implied warranty of
22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23	* General Public License for more details.
24	*
25	* You should have received a copy of the GNU General Public License
26	* along with this program; if not, see <https://www.gnu.org/licenses>.
27	*
28	* SPDX-License-Identifier: GPL-3.0-only
29	*/
30
31
32	/** @name VEX Opcode Map 3
33	* @{
34	*/
35
36	/**
37	* Common worker for AVX2 instructions on the forms:
38	* - vpxxx xmm0, xmm1, xmm2/mem128, imm8
39	* - vpxxx ymm0, ymm1, ymm2/mem256, imm8
40	*
41	* Takes function table for function w/o implicit state parameter.
42	*
43	* Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
44	*/
45	FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, PCIEMOPMEDIAOPTF3IMM8, pImpl)
46	{
47	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
48	if (IEM_IS_MODRM_REG_MODE(bRm))
49	{
50	/*
51	* Register, register.
52	*/
53	if (pVCpu->iem.s.uVexLength)
54	{
55	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
56	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
57	IEM_MC_BEGIN(4, 3);
58	IEM_MC_LOCAL(RTUINT256U, uDst);
59	IEM_MC_LOCAL(RTUINT256U, uSrc1);
60	IEM_MC_LOCAL(RTUINT256U, uSrc2);
61	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
62	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
63	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
64	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
65	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
66	IEM_MC_PREPARE_AVX_USAGE();
67	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
68	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
69	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
70	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
71	IEM_MC_ADVANCE_RIP_AND_FINISH();
72	IEM_MC_END();
73	}
74	else
75	{
76	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
77	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
78	IEM_MC_BEGIN(4, 0);
79	IEM_MC_ARG(PRTUINT128U, puDst, 0);
80	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
81	IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
82	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
83	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
84	IEM_MC_PREPARE_AVX_USAGE();
85	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
86	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
87	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
88	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
89	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
90	IEM_MC_ADVANCE_RIP_AND_FINISH();
91	IEM_MC_END();
92	}
93	}
94	else
95	{
96	/*
97	* Register, memory.
98	*/
99	if (pVCpu->iem.s.uVexLength)
100	{
101	IEM_MC_BEGIN(4, 4);
102	IEM_MC_LOCAL(RTUINT256U, uDst);
103	IEM_MC_LOCAL(RTUINT256U, uSrc1);
104	IEM_MC_LOCAL(RTUINT256U, uSrc2);
105	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
106	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
107	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
108	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
109
110	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
111	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
112	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
113	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
114	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
115	IEM_MC_PREPARE_AVX_USAGE();
116
117	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
118	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
119	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg);
120	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
121
122	IEM_MC_ADVANCE_RIP_AND_FINISH();
123	IEM_MC_END();
124	}
125	else
126	{
127	IEM_MC_BEGIN(4, 2);
128	IEM_MC_LOCAL(RTUINT128U, uSrc2);
129	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
130	IEM_MC_ARG(PRTUINT128U, puDst, 0);
131	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
132	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
133
134	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
135	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
136	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
137	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
138	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
139	IEM_MC_PREPARE_AVX_USAGE();
140
141	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
142	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
143	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
144	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg);
145	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
146
147	IEM_MC_ADVANCE_RIP_AND_FINISH();
148	IEM_MC_END();
149	}
150	}
151	}
152
153
154	/** Opcode VEX.66.0F3A 0x00. */
155	FNIEMOP_STUB(iemOp_vpermq_Vqq_Wqq_Ib);
156	/** Opcode VEX.66.0F3A 0x01. */
157	FNIEMOP_STUB(iemOp_vpermqd_Vqq_Wqq_Ib);
158	/** Opcode VEX.66.0F3A 0x02. */
159	FNIEMOP_STUB(iemOp_vpblendd_Vx_Wx_Ib);
160	/* Opcode VEX.66.0F3A 0x03 - invalid */
161	/** Opcode VEX.66.0F3A 0x04. */
162	FNIEMOP_STUB(iemOp_vpermilps_Vx_Wx_Ib);
163	/** Opcode VEX.66.0F3A 0x05. */
164	FNIEMOP_STUB(iemOp_vpermilpd_Vx_Wx_Ib);
165	/** Opcode VEX.66.0F3A 0x06 (vex only) */
166	FNIEMOP_STUB(iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib);
167	/* Opcode VEX.66.0F3A 0x07 - invalid */
168	/** Opcode VEX.66.0F3A 0x08. */
169	FNIEMOP_STUB(iemOp_vroundps_Vx_Wx_Ib);
170	/** Opcode VEX.66.0F3A 0x09. */
171	FNIEMOP_STUB(iemOp_vroundpd_Vx_Wx_Ib);
172	/** Opcode VEX.66.0F3A 0x0a. */
173	FNIEMOP_STUB(iemOp_vroundss_Vss_Wss_Ib);
174	/** Opcode VEX.66.0F3A 0x0b. */
175	FNIEMOP_STUB(iemOp_vroundsd_Vsd_Wsd_Ib);
176
177
178	/** Opcode VEX.66.0F3A 0x0c. */
179	FNIEMOP_DEF(iemOp_vblendps_Vx_Hx_Wx_Ib)
180	{
181	IEMOP_MNEMONIC3(VEX_RVM, VBLENDPS, vblendps, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
182	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendps);
183	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
184	}
185
186
187	/** Opcode VEX.66.0F3A 0x0d. */
188	FNIEMOP_DEF(iemOp_vblendpd_Vx_Hx_Wx_Ib)
189	{
190	IEMOP_MNEMONIC3(VEX_RVM, VBLENDPD, vblendpd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
191	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vblendpd);
192	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
193	}
194
195
196	/** Opcode VEX.66.0F3A 0x0e. */
197	FNIEMOP_DEF(iemOp_vpblendw_Vx_Hx_Wx_Ib)
198	{
199	IEMOP_MNEMONIC3(VEX_RVM, VPBLENDW, vpblendw, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
200	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpblendw);
201	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
202	}
203
204
205	/** Opcode VEX.0F3A 0x0f - invalid. */
206
207
208	/** Opcode VEX.66.0F3A 0x0f. */
209	FNIEMOP_DEF(iemOp_vpalignr_Vx_Hx_Wx_Ib)
210	{
211	IEMOP_MNEMONIC3(VEX_RVM, VPALIGNR, vpalignr, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0); /* @todo */
212	IEMOPMEDIAOPTF3IMM8_INIT_VARS(vpalignr);
213	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Ib_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
214	}
215
216
217	/* Opcode VEX.66.0F3A 0x10 - invalid */
218	/* Opcode VEX.66.0F3A 0x11 - invalid */
219	/* Opcode VEX.66.0F3A 0x12 - invalid */
220	/* Opcode VEX.66.0F3A 0x13 - invalid */
221	/** Opcode VEX.66.0F3A 0x14. */
222	FNIEMOP_STUB(iemOp_vpextrb_RdMb_Vdq_Ib);
223	/** Opcode VEX.66.0F3A 0x15. */
224	FNIEMOP_STUB(iemOp_vpextrw_RdMw_Vdq_Ib);
225	/** Opcode VEX.66.0F3A 0x16. */
226	FNIEMOP_STUB(iemOp_vpextrd_q_RdMw_Vdq_Ib);
227	/** Opcode VEX.66.0F3A 0x17. */
228	FNIEMOP_STUB(iemOp_vextractps_Ed_Vdq_Ib);
229	/** Opcode VEX.66.0F3A 0x18 (vex only). */
230	FNIEMOP_STUB(iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib);
231	/** Opcode VEX.66.0F3A 0x19 (vex only). */
232	FNIEMOP_STUB(iemOp_vextractf128_Wdq_Vqq_Ib);
233	/* Opcode VEX.66.0F3A 0x1a - invalid */
234	/* Opcode VEX.66.0F3A 0x1b - invalid */
235	/* Opcode VEX.66.0F3A 0x1c - invalid */
236	/** Opcode VEX.66.0F3A 0x1d (vex only). */
237	FNIEMOP_STUB(iemOp_vcvtps2ph_Wx_Vx_Ib);
238	/* Opcode VEX.66.0F3A 0x1e - invalid */
239	/* Opcode VEX.66.0F3A 0x1f - invalid */
240
241
242	/** Opcode VEX.66.0F3A 0x20. */
243	FNIEMOP_STUB(iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib);
244	/** Opcode VEX.66.0F3A 0x21, */
245	FNIEMOP_STUB(iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib);
246	/** Opcode VEX.66.0F3A 0x22. */
247	FNIEMOP_STUB(iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib);
248	/* Opcode VEX.66.0F3A 0x23 - invalid */
249	/* Opcode VEX.66.0F3A 0x24 - invalid */
250	/* Opcode VEX.66.0F3A 0x25 - invalid */
251	/* Opcode VEX.66.0F3A 0x26 - invalid */
252	/* Opcode VEX.66.0F3A 0x27 - invalid */
253	/* Opcode VEX.66.0F3A 0x28 - invalid */
254	/* Opcode VEX.66.0F3A 0x29 - invalid */
255	/* Opcode VEX.66.0F3A 0x2a - invalid */
256	/* Opcode VEX.66.0F3A 0x2b - invalid */
257	/* Opcode VEX.66.0F3A 0x2c - invalid */
258	/* Opcode VEX.66.0F3A 0x2d - invalid */
259	/* Opcode VEX.66.0F3A 0x2e - invalid */
260	/* Opcode VEX.66.0F3A 0x2f - invalid */
261
262
263	/* Opcode VEX.66.0F3A 0x30 - invalid */
264	/* Opcode VEX.66.0F3A 0x31 - invalid */
265	/* Opcode VEX.66.0F3A 0x32 - invalid */
266	/* Opcode VEX.66.0F3A 0x33 - invalid */
267	/* Opcode VEX.66.0F3A 0x34 - invalid */
268	/* Opcode VEX.66.0F3A 0x35 - invalid */
269	/* Opcode VEX.66.0F3A 0x36 - invalid */
270	/* Opcode VEX.66.0F3A 0x37 - invalid */
271	/** Opcode VEX.66.0F3A 0x38 (vex only). */
272	FNIEMOP_STUB(iemOp_vinserti128_Vqq_Hqq_Wqq_Ib);
273	/** Opcode VEX.66.0F3A 0x39 (vex only). */
274	FNIEMOP_STUB(iemOp_vextracti128_Wdq_Vqq_Ib);
275	/* Opcode VEX.66.0F3A 0x3a - invalid */
276	/* Opcode VEX.66.0F3A 0x3b - invalid */
277	/* Opcode VEX.66.0F3A 0x3c - invalid */
278	/* Opcode VEX.66.0F3A 0x3d - invalid */
279	/* Opcode VEX.66.0F3A 0x3e - invalid */
280	/* Opcode VEX.66.0F3A 0x3f - invalid */
281
282
283	/** Opcode VEX.66.0F3A 0x40. */
284	FNIEMOP_STUB(iemOp_vdpps_Vx_Hx_Wx_Ib);
285	/** Opcode VEX.66.0F3A 0x41, */
286	FNIEMOP_STUB(iemOp_vdppd_Vdq_Hdq_Wdq_Ib);
287	/** Opcode VEX.66.0F3A 0x42. */
288	FNIEMOP_STUB(iemOp_vmpsadbw_Vx_Hx_Wx_Ib);
289	/* Opcode VEX.66.0F3A 0x43 - invalid */
290
291
292	/** Opcode VEX.66.0F3A 0x44. */
293	FNIEMOP_DEF(iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib)
294	{
295	//IEMOP_MNEMONIC3(VEX_RVM, VPCLMULQDQ, vpclmulqdq, Vdq, Hdq, Wdq, DISOPTYPE_HARMLESS, 0); /* @todo */
296
297	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
298	if (IEM_IS_MODRM_REG_MODE(bRm))
299	{
300	/*
301	* Register, register.
302	*/
303	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
304	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
305	IEM_MC_BEGIN(4, 0);
306	IEM_MC_ARG(PRTUINT128U, puDst, 0);
307	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
308	IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
309	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
310	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
311	IEM_MC_PREPARE_AVX_USAGE();
312	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
313	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
314	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
315	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
316	puDst, puSrc1, puSrc2, bImmArg);
317	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
318	IEM_MC_ADVANCE_RIP_AND_FINISH();
319	IEM_MC_END();
320	}
321	else
322	{
323	/*
324	* Register, memory.
325	*/
326	IEM_MC_BEGIN(4, 2);
327	IEM_MC_LOCAL(RTUINT128U, uSrc2);
328	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
329	IEM_MC_ARG(PRTUINT128U, puDst, 0);
330	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
331	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
332
333	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
334	uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm);
335	IEM_MC_ARG_CONST(uint8_t, bImmArg, /=/ bImm, 3);
336	IEMOP_HLP_DONE_VEX_DECODING_L0_EX(fPclMul);
337	IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
338	IEM_MC_PREPARE_AVX_USAGE();
339
340	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
341	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
342	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
343	IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fPclMul, iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback),
344	puDst, puSrc1, puSrc2, bImmArg);
345	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
346
347	IEM_MC_ADVANCE_RIP_AND_FINISH();
348	IEM_MC_END();
349	}
350	}
351
352
353	/* Opcode VEX.66.0F3A 0x45 - invalid */
354	/** Opcode VEX.66.0F3A 0x46 (vex only) */
355	FNIEMOP_STUB(iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib);
356	/* Opcode VEX.66.0F3A 0x47 - invalid */
357	/** Opcode VEX.66.0F3A 0x48 (AMD tables only). */
358	FNIEMOP_STUB(iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx);
359	/** Opcode VEX.66.0F3A 0x49 (AMD tables only). */
360	FNIEMOP_STUB(iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx);
361
362
363	/**
364	* Common worker for AVX2 instructions on the forms:
365	* - vpxxx xmm0, xmm1, xmm2/mem128, xmm4
366	* - vpxxx ymm0, ymm1, ymm2/mem256, ymm4
367	*
368	* Exceptions type 4. AVX cpuid check for 128-bit operation, AVX2 for 256-bit.
369	*/
370	FNIEMOP_DEF_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, PCIEMOPBLENDOP, pImpl)
371	{
372	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
373	if (IEM_IS_MODRM_REG_MODE(bRm))
374	{
375	/*
376	* Register, register.
377	*/
378	if (pVCpu->iem.s.uVexLength)
379	{
380	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
381
382	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
383	IEM_MC_BEGIN(4, 4);
384	IEM_MC_LOCAL(RTUINT256U, uDst);
385	IEM_MC_LOCAL(RTUINT256U, uSrc1);
386	IEM_MC_LOCAL(RTUINT256U, uSrc2);
387	IEM_MC_LOCAL(RTUINT256U, uSrc3);
388	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
389	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
390	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
391	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
392	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
393	IEM_MC_PREPARE_AVX_USAGE();
394	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
395	IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
396	IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
397	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
398	IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
399	IEM_MC_ADVANCE_RIP_AND_FINISH();
400	IEM_MC_END();
401	}
402	else
403	{
404	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
405
406	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
407	IEM_MC_BEGIN(4, 0);
408	IEM_MC_ARG(PRTUINT128U, puDst, 0);
409	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
410	IEM_MC_ARG(PCRTUINT128U, puSrc2, 2);
411	IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
412	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
413	IEM_MC_PREPARE_AVX_USAGE();
414	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
415	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
416	IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
417	IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
418	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
419	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
420	IEM_MC_ADVANCE_RIP_AND_FINISH();
421	IEM_MC_END();
422	}
423	}
424	else
425	{
426	/*
427	* Register, memory.
428	*/
429	if (pVCpu->iem.s.uVexLength)
430	{
431	IEM_MC_BEGIN(4, 5);
432	IEM_MC_LOCAL(RTUINT256U, uDst);
433	IEM_MC_LOCAL(RTUINT256U, uSrc1);
434	IEM_MC_LOCAL(RTUINT256U, uSrc2);
435	IEM_MC_LOCAL(RTUINT256U, uSrc3);
436	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
437	IEM_MC_ARG_LOCAL_REF(PRTUINT256U, puDst, uDst, 0);
438	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 1);
439	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 2);
440	IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc3, uSrc3, 3);
441
442	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
443	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
444
445	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx2);
446	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
447	IEM_MC_PREPARE_AVX_USAGE();
448
449	IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
450	IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
451	IEM_MC_FETCH_YREG_U256(uSrc3, IEM_GET_EFFECTIVE_VVVV(pVCpu));
452	IEM_MC_FETCH_YREG_U256(uSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
453	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3);
454	IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst);
455
456	IEM_MC_ADVANCE_RIP_AND_FINISH();
457	IEM_MC_END();
458	}
459	else
460	{
461	IEM_MC_BEGIN(4, 2);
462	IEM_MC_LOCAL(RTUINT128U, uSrc2);
463	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
464	IEM_MC_ARG(PRTUINT128U, puDst, 0);
465	IEM_MC_ARG(PCRTUINT128U, puSrc1, 1);
466	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 2);
467	IEM_MC_ARG(PCRTUINT128U, puSrc3, 3);
468
469	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
470	uint8_t bOp4; IEM_OPCODE_GET_NEXT_U8(&bOp4);
471
472	IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
473	IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT();
474	IEM_MC_PREPARE_AVX_USAGE();
475
476	IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
477	IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm));
478	IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_EFFECTIVE_VVVV(pVCpu));
479	IEM_MC_REF_XREG_U128_CONST(puSrc3, bOp4 >> 4); /** @todo Ignore MSB in 32-bit mode. */
480	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3);
481	IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm));
482
483	IEM_MC_ADVANCE_RIP_AND_FINISH();
484	IEM_MC_END();
485	}
486	}
487	}
488
489
490	/** Opcode VEX.66.0F3A 0x4a (vex only). */
491	FNIEMOP_DEF(iemOp_vblendvps_Vx_Hx_Wx_Lx)
492	{
493	//IEMOP_MNEMONIC4(VEX_RVM, VBLENDVPS, vpblendvps, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
494	IEMOPBLENDOP_INIT_VARS(vblendvps);
495	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
496	}
497
498
499	/** Opcode VEX.66.0F3A 0x4b (vex only). */
500	FNIEMOP_DEF(iemOp_vblendvpd_Vx_Hx_Wx_Lx)
501	{
502	//IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVPD, blendvpd, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
503	IEMOPBLENDOP_INIT_VARS(vblendvpd);
504	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
505	}
506
507
508	/** Opcode VEX.66.0F3A 0x4c (vex only). */
509	FNIEMOP_DEF(iemOp_vpblendvb_Vx_Hx_Wx_Lx)
510	{
511	//IEMOP_MNEMONIC4(VEX_RVM, VPBLENDVB, vpblendvb, Vx, Hx, Wx, Lx, DISOPTYPE_HARMLESS, 0); @todo
512	IEMOPBLENDOP_INIT_VARS(vpblendvb);
513	return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Lx, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
514	}
515
516
517	/* Opcode VEX.66.0F3A 0x4d - invalid */
518	/* Opcode VEX.66.0F3A 0x4e - invalid */
519	/* Opcode VEX.66.0F3A 0x4f - invalid */
520
521
522	/* Opcode VEX.66.0F3A 0x50 - invalid */
523	/* Opcode VEX.66.0F3A 0x51 - invalid */
524	/* Opcode VEX.66.0F3A 0x52 - invalid */
525	/* Opcode VEX.66.0F3A 0x53 - invalid */
526	/* Opcode VEX.66.0F3A 0x54 - invalid */
527	/* Opcode VEX.66.0F3A 0x55 - invalid */
528	/* Opcode VEX.66.0F3A 0x56 - invalid */
529	/* Opcode VEX.66.0F3A 0x57 - invalid */
530	/* Opcode VEX.66.0F3A 0x58 - invalid */
531	/* Opcode VEX.66.0F3A 0x59 - invalid */
532	/* Opcode VEX.66.0F3A 0x5a - invalid */
533	/* Opcode VEX.66.0F3A 0x5b - invalid */
534	/** Opcode VEX.66.0F3A 0x5c (AMD tables only). */
535	FNIEMOP_STUB(iemOp_vfmaddsubps_Vx_Lx_Wx_Hx);
536	/** Opcode VEX.66.0F3A 0x5d (AMD tables only). */
537	FNIEMOP_STUB(iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx);
538	/** Opcode VEX.66.0F3A 0x5e (AMD tables only). */
539	FNIEMOP_STUB(iemOp_vfmsubaddps_Vx_Lx_Wx_Hx);
540	/** Opcode VEX.66.0F3A 0x5f (AMD tables only). */
541	FNIEMOP_STUB(iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx);
542
543
544	/** Opcode VEX.66.0F3A 0x60. */
545	FNIEMOP_STUB(iemOp_vpcmpestrm_Vdq_Wdq_Ib);
546	/** Opcode VEX.66.0F3A 0x61, */
547	FNIEMOP_STUB(iemOp_vpcmpestri_Vdq_Wdq_Ib);
548	/** Opcode VEX.66.0F3A 0x62. */
549	FNIEMOP_STUB(iemOp_vpcmpistrm_Vdq_Wdq_Ib);
550	/** Opcode VEX.66.0F3A 0x63*/
551	FNIEMOP_STUB(iemOp_vpcmpistri_Vdq_Wdq_Ib);
552	/* Opcode VEX.66.0F3A 0x64 - invalid */
553	/* Opcode VEX.66.0F3A 0x65 - invalid */
554	/* Opcode VEX.66.0F3A 0x66 - invalid */
555	/* Opcode VEX.66.0F3A 0x67 - invalid */
556	/** Opcode VEX.66.0F3A 0x68 (AMD tables only). */
557	FNIEMOP_STUB(iemOp_vfmaddps_Vx_Lx_Wx_Hx);
558	/** Opcode VEX.66.0F3A 0x69 (AMD tables only). */
559	FNIEMOP_STUB(iemOp_vfmaddpd_Vx_Lx_Wx_Hx);
560	/** Opcode VEX.66.0F3A 0x6a (AMD tables only). */
561	FNIEMOP_STUB(iemOp_vfmaddss_Vx_Lx_Wx_Hx);
562	/** Opcode VEX.66.0F3A 0x6b (AMD tables only). */
563	FNIEMOP_STUB(iemOp_vfmaddsd_Vx_Lx_Wx_Hx);
564	/** Opcode VEX.66.0F3A 0x6c (AMD tables only). */
565	FNIEMOP_STUB(iemOp_vfmsubps_Vx_Lx_Wx_Hx);
566	/** Opcode VEX.66.0F3A 0x6d (AMD tables only). */
567	FNIEMOP_STUB(iemOp_vfmsubpd_Vx_Lx_Wx_Hx);
568	/** Opcode VEX.66.0F3A 0x6e (AMD tables only). */
569	FNIEMOP_STUB(iemOp_vfmsubss_Vx_Lx_Wx_Hx);
570	/** Opcode VEX.66.0F3A 0x6f (AMD tables only). */
571	FNIEMOP_STUB(iemOp_vfmsubsd_Vx_Lx_Wx_Hx);
572
573	/* Opcode VEX.66.0F3A 0x70 - invalid */
574	/* Opcode VEX.66.0F3A 0x71 - invalid */
575	/* Opcode VEX.66.0F3A 0x72 - invalid */
576	/* Opcode VEX.66.0F3A 0x73 - invalid */
577	/* Opcode VEX.66.0F3A 0x74 - invalid */
578	/* Opcode VEX.66.0F3A 0x75 - invalid */
579	/* Opcode VEX.66.0F3A 0x76 - invalid */
580	/* Opcode VEX.66.0F3A 0x77 - invalid */
581	/** Opcode VEX.66.0F3A 0x78 (AMD tables only). */
582	FNIEMOP_STUB(iemOp_vfnmaddps_Vx_Lx_Wx_Hx);
583	/** Opcode VEX.66.0F3A 0x79 (AMD tables only). */
584	FNIEMOP_STUB(iemOp_vfnmaddpd_Vx_Lx_Wx_Hx);
585	/** Opcode VEX.66.0F3A 0x7a (AMD tables only). */
586	FNIEMOP_STUB(iemOp_vfnmaddss_Vx_Lx_Wx_Hx);
587	/** Opcode VEX.66.0F3A 0x7b (AMD tables only). */
588	FNIEMOP_STUB(iemOp_vfnmaddsd_Vx_Lx_Wx_Hx);
589	/** Opcode VEX.66.0F3A 0x7c (AMD tables only). */
590	FNIEMOP_STUB(iemOp_vfnmsubps_Vx_Lx_Wx_Hx);
591	/** Opcode VEX.66.0F3A 0x7d (AMD tables only). */
592	FNIEMOP_STUB(iemOp_vfnmsubpd_Vx_Lx_Wx_Hx);
593	/** Opcode VEX.66.0F3A 0x7e (AMD tables only). */
594	FNIEMOP_STUB(iemOp_vfnmsubss_Vx_Lx_Wx_Hx);
595	/** Opcode VEX.66.0F3A 0x7f (AMD tables only). */
596	FNIEMOP_STUB(iemOp_vfnmsubsd_Vx_Lx_Wx_Hx);
597
598	/* Opcodes 0x0f 0x80 thru 0x0f 0xb0 are unused. */
599
600
601	/* Opcode 0x0f 0xc0 - invalid */
602	/* Opcode 0x0f 0xc1 - invalid */
603	/* Opcode 0x0f 0xc2 - invalid */
604	/* Opcode 0x0f 0xc3 - invalid */
605	/* Opcode 0x0f 0xc4 - invalid */
606	/* Opcode 0x0f 0xc5 - invalid */
607	/* Opcode 0x0f 0xc6 - invalid */
608	/* Opcode 0x0f 0xc7 - invalid */
609	/* Opcode 0x0f 0xc8 - invalid */
610	/* Opcode 0x0f 0xc9 - invalid */
611	/* Opcode 0x0f 0xca - invalid */
612	/* Opcode 0x0f 0xcb - invalid */
613	/* Opcode 0x0f 0xcc */
614	FNIEMOP_STUB(iemOp_vsha1rnds4_Vdq_Wdq_Ib);
615	/* Opcode 0x0f 0xcd - invalid */
616	/* Opcode 0x0f 0xce - invalid */
617	/* Opcode 0x0f 0xcf - invalid */
618
619
620	/* Opcode VEX.66.0F3A 0xd0 - invalid */
621	/* Opcode VEX.66.0F3A 0xd1 - invalid */
622	/* Opcode VEX.66.0F3A 0xd2 - invalid */
623	/* Opcode VEX.66.0F3A 0xd3 - invalid */
624	/* Opcode VEX.66.0F3A 0xd4 - invalid */
625	/* Opcode VEX.66.0F3A 0xd5 - invalid */
626	/* Opcode VEX.66.0F3A 0xd6 - invalid */
627	/* Opcode VEX.66.0F3A 0xd7 - invalid */
628	/* Opcode VEX.66.0F3A 0xd8 - invalid */
629	/* Opcode VEX.66.0F3A 0xd9 - invalid */
630	/* Opcode VEX.66.0F3A 0xda - invalid */
631	/* Opcode VEX.66.0F3A 0xdb - invalid */
632	/* Opcode VEX.66.0F3A 0xdc - invalid */
633	/* Opcode VEX.66.0F3A 0xdd - invalid */
634	/* Opcode VEX.66.0F3A 0xde - invalid */
635	/* Opcode VEX.66.0F3A 0xdf - (aeskeygenassist). */
636	FNIEMOP_STUB(iemOp_vaeskeygen_Vdq_Wdq_Ib);
637
638
639	/** Opcode VEX.F2.0F3A (vex only) */
640	FNIEMOP_DEF(iemOp_rorx_Gy_Ey_Ib)
641	{
642	IEMOP_MNEMONIC3(VEX_RMI, RORX, rorx, Gy, Ey, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_VEX_L_ZERO \| IEMOPHINT_VEX_V_ZERO);
643	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fBmi2)
644	return iemOp_InvalidNeedRMImm8(pVCpu);
645	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
646	if (IEM_IS_MODRM_REG_MODE(bRm))
647	{
648	/*
649	* Register, register.
650	*/
651	uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
652	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
653	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
654	{
655	IEM_MC_BEGIN(3, 0);
656	IEM_MC_ARG(uint64_t *, pDst, 0);
657	IEM_MC_ARG(uint64_t, uSrc1, 1);
658	IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
659	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
660	IEM_MC_FETCH_GREG_U64(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
661	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
662	IEM_MC_ADVANCE_RIP_AND_FINISH();
663	IEM_MC_END();
664	}
665	else
666	{
667	IEM_MC_BEGIN(3, 0);
668	IEM_MC_ARG(uint32_t *, pDst, 0);
669	IEM_MC_ARG(uint32_t, uSrc1, 1);
670	IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
671	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
672	IEM_MC_FETCH_GREG_U32(uSrc1, IEM_GET_MODRM_RM(pVCpu, bRm));
673	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
674	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
675	IEM_MC_ADVANCE_RIP_AND_FINISH();
676	IEM_MC_END();
677	}
678	}
679	else
680	{
681	/*
682	* Register, memory.
683	*/
684	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
685	{
686	IEM_MC_BEGIN(3, 1);
687	IEM_MC_ARG(uint64_t *, pDst, 0);
688	IEM_MC_ARG(uint64_t, uSrc1, 1);
689	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
690	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
691	uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
692	IEM_MC_ARG_CONST(uint64_t, uSrc2, bImm8, 2);
693	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
694	IEM_MC_FETCH_MEM_U64(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
695	IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
696	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2);
697	IEM_MC_ADVANCE_RIP_AND_FINISH();
698	IEM_MC_END();
699	}
700	else
701	{
702	IEM_MC_BEGIN(3, 1);
703	IEM_MC_ARG(uint32_t *, pDst, 0);
704	IEM_MC_ARG(uint32_t, uSrc1, 1);
705	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
706	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
707	uint8_t bImm8; IEM_OPCODE_GET_NEXT_U8(&bImm8);
708	IEM_MC_ARG_CONST(uint32_t, uSrc2, bImm8, 2);
709	IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV();
710	IEM_MC_FETCH_MEM_U32(uSrc1, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
711	IEM_MC_REF_GREG_U32(pDst, IEM_GET_MODRM_REG(pVCpu, bRm));
712	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2);
713	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pDst);
714	IEM_MC_ADVANCE_RIP_AND_FINISH();
715	IEM_MC_END();
716	}
717	}
718	}
719
720
721	/**
722	* VEX opcode map \#3.
723	*
724	* @sa g_apfnThreeByte0f3a
725	*/
726	IEM_STATIC const PFNIEMOP g_apfnVexMap3[] =
727	{
728	/* no prefix, 066h prefix f3h prefix, f2h prefix */
729	/* 0x00 */ iemOp_InvalidNeedRMImm8, iemOp_vpermq_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
730	/* 0x01 */ iemOp_InvalidNeedRMImm8, iemOp_vpermqd_Vqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
731	/* 0x02 */ iemOp_InvalidNeedRMImm8, iemOp_vpblendd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
732	/* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
733	/* 0x04 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
734	/* 0x05 */ iemOp_InvalidNeedRMImm8, iemOp_vpermilpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
735	/* 0x06 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2f128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
736	/* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
737	/* 0x08 */ iemOp_InvalidNeedRMImm8, iemOp_vroundps_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
738	/* 0x09 */ iemOp_InvalidNeedRMImm8, iemOp_vroundpd_Vx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
739	/* 0x0a */ iemOp_InvalidNeedRMImm8, iemOp_vroundss_Vss_Wss_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
740	/* 0x0b */ iemOp_InvalidNeedRMImm8, iemOp_vroundsd_Vsd_Wsd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
741	/* 0x0c */ iemOp_InvalidNeedRMImm8, iemOp_vblendps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
742	/* 0x0d */ iemOp_InvalidNeedRMImm8, iemOp_vblendpd_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
743	/* 0x0e */ iemOp_InvalidNeedRMImm8, iemOp_vpblendw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
744	/* 0x0f */ iemOp_InvalidNeedRMImm8, iemOp_vpalignr_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
745
746	/* 0x10 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
747	/* 0x11 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
748	/* 0x12 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
749	/* 0x13 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
750	/* 0x14 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrb_RdMb_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
751	/* 0x15 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrw_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
752	/* 0x16 */ iemOp_InvalidNeedRMImm8, iemOp_vpextrd_q_RdMw_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
753	/* 0x17 */ iemOp_InvalidNeedRMImm8, iemOp_vextractps_Ed_Vdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
754	/* 0x18 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertf128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
755	/* 0x19 */ iemOp_InvalidNeedRMImm8, iemOp_vextractf128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
756	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
757	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
758	/* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
759	/* 0x1d */ iemOp_InvalidNeedRMImm8, iemOp_vcvtps2ph_Wx_Vx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
760	/* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
761	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
762
763	/* 0x20 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrb_Vdq_Hdq_RyMb_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
764	/* 0x21 */ iemOp_InvalidNeedRMImm8, iemOp_vinsertps_Vdq_Hdq_UdqMd_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
765	/* 0x22 */ iemOp_InvalidNeedRMImm8, iemOp_vpinsrd_q_Vdq_Hdq_Ey_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
766	/* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
767	/* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
768	/* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
769	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
770	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
771	/* 0x28 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
772	/* 0x29 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
773	/* 0x2a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
774	/* 0x2b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
775	/* 0x2c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
776	/* 0x2d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
777	/* 0x2e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
778	/* 0x2f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
779
780	/* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
781	/* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
782	/* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
783	/* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
784	/* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
785	/* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
786	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
787	/* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
788	/* 0x38 */ iemOp_InvalidNeedRMImm8, iemOp_vinserti128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
789	/* 0x39 */ iemOp_InvalidNeedRMImm8, iemOp_vextracti128_Wdq_Vqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
790	/* 0x3a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
791	/* 0x3b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
792	/* 0x3c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
793	/* 0x3d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
794	/* 0x3e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
795	/* 0x3f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
796
797	/* 0x40 */ iemOp_InvalidNeedRMImm8, iemOp_vdpps_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
798	/* 0x41 */ iemOp_InvalidNeedRMImm8, iemOp_vdppd_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
799	/* 0x42 */ iemOp_InvalidNeedRMImm8, iemOp_vmpsadbw_Vx_Hx_Wx_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
800	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
801	/* 0x44 */ iemOp_InvalidNeedRMImm8, iemOp_vpclmulqdq_Vdq_Hdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
802	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
803	/* 0x46 */ iemOp_InvalidNeedRMImm8, iemOp_vperm2i128_Vqq_Hqq_Wqq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
804	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
805	/* 0x48 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2ps_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
806	/* 0x49 */ iemOp_InvalidNeedRMImm8, iemOp_vperlmilzz2pd_Vx_Hx_Wp_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
807	/* 0x4a */ iemOp_InvalidNeedRMImm8, iemOp_vblendvps_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
808	/* 0x4b */ iemOp_InvalidNeedRMImm8, iemOp_vblendvpd_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
809	/* 0x4c */ iemOp_InvalidNeedRMImm8, iemOp_vpblendvb_Vx_Hx_Wx_Lx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
810	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
811	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
812	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
813
814	/* 0x50 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
815	/* 0x51 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
816	/* 0x52 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
817	/* 0x53 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
818	/* 0x54 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
819	/* 0x55 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
820	/* 0x56 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
821	/* 0x57 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
822	/* 0x58 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
823	/* 0x59 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
824	/* 0x5a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
825	/* 0x5b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
826	/* 0x5c */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
827	/* 0x5d */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
828	/* 0x5e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
829	/* 0x5f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
830
831	/* 0x60 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
832	/* 0x61 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpestri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
833	/* 0x62 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistrm_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
834	/* 0x63 */ iemOp_InvalidNeedRMImm8, iemOp_vpcmpistri_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
835	/* 0x64 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
836	/* 0x65 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
837	/* 0x66 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
838	/* 0x67 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
839	/* 0x68 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
840	/* 0x69 */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
841	/* 0x6a */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
842	/* 0x6b */ iemOp_InvalidNeedRMImm8, iemOp_vfmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
843	/* 0x6c */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
844	/* 0x6d */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
845	/* 0x6e */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
846	/* 0x6f */ iemOp_InvalidNeedRMImm8, iemOp_vfmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
847
848	/* 0x70 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
849	/* 0x71 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
850	/* 0x72 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
851	/* 0x73 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
852	/* 0x74 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
853	/* 0x75 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
854	/* 0x76 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
855	/* 0x77 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
856	/* 0x78 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
857	/* 0x79 */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
858	/* 0x7a */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
859	/* 0x7b */ iemOp_InvalidNeedRMImm8, iemOp_vfnmaddsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
860	/* 0x7c */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubps_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
861	/* 0x7d */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubpd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
862	/* 0x7e */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubss_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
863	/* 0x7f */ iemOp_InvalidNeedRMImm8, iemOp_vfnmsubsd_Vx_Lx_Wx_Hx, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
864
865	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
866	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
867	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
868	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
869	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
870	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
871	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
872	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
873	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
874	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
875	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
876	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
877	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
878	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
879	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
880	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
881
882	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
883	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
884	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
885	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
886	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
887	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
888	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
889	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
890	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
891	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
892	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
893	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
894	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
895	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
896	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
897	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
898
899	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
900	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
901	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
902	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
903	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
904	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
905	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
906	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
907	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
908	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
909	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
910	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
911	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
912	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
913	/* 0xae */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
914	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
915
916	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
917	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
918	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
919	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
920	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
921	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
922	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
923	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
924	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
925	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
926	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
927	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
928	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
929	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
930	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
931	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
932
933	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
934	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
935	/* 0xc2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
936	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
937	/* 0xc4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
938	/* 0xc5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
939	/* 0xc6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
940	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
941	/* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
942	/* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
943	/* 0xca */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
944	/* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
945	/* 0xcc */ iemOp_vsha1rnds4_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
946	/* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
947	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
948	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
949
950	/* 0xd0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
951	/* 0xd1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
952	/* 0xd2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
953	/* 0xd3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
954	/* 0xd4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
955	/* 0xd5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
956	/* 0xd6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
957	/* 0xd7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
958	/* 0xd8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
959	/* 0xd9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
960	/* 0xda */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
961	/* 0xdb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
962	/* 0xdc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
963	/* 0xdd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
964	/* 0xde */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
965	/* 0xdf */ iemOp_vaeskeygen_Vdq_Wdq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
966
967	/* 0xe0 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
968	/* 0xe1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
969	/* 0xe2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
970	/* 0xe3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
971	/* 0xe4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
972	/* 0xe5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
973	/* 0xe6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
974	/* 0xe7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
975	/* 0xe8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
976	/* 0xe9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
977	/* 0xea */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
978	/* 0xeb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
979	/* 0xec */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
980	/* 0xed */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
981	/* 0xee */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
982	/* 0xef */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
983
984	/* 0xf0 */ iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8, iemOp_rorx_Gy_Ey_Ib,
985	/* 0xf1 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
986	/* 0xf2 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
987	/* 0xf3 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
988	/* 0xf4 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
989	/* 0xf5 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
990	/* 0xf6 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
991	/* 0xf7 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
992	/* 0xf8 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
993	/* 0xf9 */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
994	/* 0xfa */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
995	/* 0xfb */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
996	/* 0xfc */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
997	/* 0xfd */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
998	/* 0xfe */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
999	/* 0xff */ IEMOP_X4(iemOp_InvalidNeedRMImm8),
1000	};
1001	AssertCompile(RT_ELEMENTS(g_apfnVexMap3) == 1024);
1002
1003	/** @} */
1004

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap3.cpp.h@ 97694

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