IEMAllN8veRecompiler.cpp@ 103528

Last change on this file since 103528 was 103404, checked in by vboxsync, 12 months ago
VMM/IEM: Threaded function statistics. bugref:10376
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1	/* $Id: IEMAllN8veRecompiler.cpp 103404 2024-02-17 01:53:09Z vboxsync $ */
2	/** @file
3	* IEM - Native Recompiler
4	*
5	* Logging group IEM_RE_NATIVE assignments:
6	* - Level 1 (Log) : ...
7	* - Flow (LogFlow) : ...
8	* - Level 2 (Log2) : Details calls as they're recompiled.
9	* - Level 3 (Log3) : Disassemble native code after recompiling.
10	* - Level 4 (Log4) : ...
11	* - Level 5 (Log5) : ...
12	* - Level 6 (Log6) : ...
13	* - Level 7 (Log7) : ...
14	* - Level 8 (Log8) : ...
15	* - Level 9 (Log9) : ...
16	* - Level 10 (Log10): ...
17	* - Level 11 (Log11): Variable allocator.
18	* - Level 12 (Log12): Register allocator.
19	*/
20
21	/*
22	* Copyright (C) 2023 Oracle and/or its affiliates.
23	*
24	* This file is part of VirtualBox base platform packages, as
25	* available from https://www.virtualbox.org.
26	*
27	* This program is free software; you can redistribute it and/or
28	* modify it under the terms of the GNU General Public License
29	* as published by the Free Software Foundation, in version 3 of the
30	* License.
31	*
32	* This program is distributed in the hope that it will be useful, but
33	* WITHOUT ANY WARRANTY; without even the implied warranty of
34	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
35	* General Public License for more details.
36	*
37	* You should have received a copy of the GNU General Public License
38	* along with this program; if not, see <https://www.gnu.org/licenses>.
39	*
40	* SPDX-License-Identifier: GPL-3.0-only
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_IEM_RE_NATIVE
48	#define IEM_WITH_OPAQUE_DECODER_STATE
49	#define VMCPU_INCL_CPUM_GST_CTX
50	#define VMM_INCLUDED_SRC_include_IEMMc_h /* block IEMMc.h inclusion. */
51	#include <VBox/vmm/iem.h>
52	#include <VBox/vmm/cpum.h>
53	#include <VBox/vmm/dbgf.h>
54	#include "IEMInternal.h"
55	#include <VBox/vmm/vmcc.h>
56	#include <VBox/log.h>
57	#include <VBox/err.h>
58	#include <VBox/dis.h>
59	#include <VBox/param.h>
60	#include <iprt/assert.h>
61	#include <iprt/heap.h>
62	#include <iprt/mem.h>
63	#include <iprt/string.h>
64	#if defined(RT_ARCH_AMD64)
65	# include <iprt/x86.h>
66	#elif defined(RT_ARCH_ARM64)
67	# include <iprt/armv8.h>
68	#endif
69
70	#ifdef RT_OS_WINDOWS
71	# include <iprt/formats/pecoff.h> /* this is incomaptible with windows.h, thus: */
72	extern "C" DECLIMPORT(uint8_t) __cdecl RtlAddFunctionTable(void *pvFunctionTable, uint32_t cEntries, uintptr_t uBaseAddress);
73	extern "C" DECLIMPORT(uint8_t) __cdecl RtlDelFunctionTable(void *pvFunctionTable);
74	#else
75	# include <iprt/formats/dwarf.h>
76	# if defined(RT_OS_DARWIN)
77	# include <libkern/OSCacheControl.h>
78	# define IEMNATIVE_USE_LIBUNWIND
79	extern "C" void __register_frame(const void *pvFde);
80	extern "C" void __deregister_frame(const void *pvFde);
81	# else
82	# ifdef DEBUG_bird /** @todo not thread safe yet */
83	# define IEMNATIVE_USE_GDB_JIT
84	# endif
85	# ifdef IEMNATIVE_USE_GDB_JIT
86	# include <iprt/critsect.h>
87	# include <iprt/once.h>
88	# include <iprt/formats/elf64.h>
89	# endif
90	extern "C" void __register_frame_info(void pvBegin, void pvObj); /* found no header for these two */
91	extern "C" void __deregister_frame_info(void pvBegin); /* (returns pvObj from __register_frame_info call) */
92	# endif
93	#endif
94	#ifdef VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER
95	# include "/opt/local/include/capstone/capstone.h"
96	#endif
97
98	#include "IEMInline.h"
99	#include "IEMThreadedFunctions.h"
100	#include "IEMN8veRecompiler.h"
101	#include "IEMN8veRecompilerEmit.h"
102	#include "IEMN8veRecompilerTlbLookup.h"
103	#include "IEMNativeFunctions.h"
104
105
106	/*
107	* Narrow down configs here to avoid wasting time on unused configs here.
108	* Note! Same checks in IEMAllThrdRecompiler.cpp.
109	*/
110
111	#ifndef IEM_WITH_CODE_TLB
112	# error The code TLB must be enabled for the recompiler.
113	#endif
114
115	#ifndef IEM_WITH_DATA_TLB
116	# error The data TLB must be enabled for the recompiler.
117	#endif
118
119	#ifndef IEM_WITH_SETJMP
120	# error The setjmp approach must be enabled for the recompiler.
121	#endif
122
123	/** @todo eliminate this clang build hack. */
124	#if RT_CLANG_PREREQ(4, 0)
125	# pragma GCC diagnostic ignored "-Wunused-function"
126	#endif
127
128
129	/*********************************************************************************************************************************
130	* Internal Functions *
131	*********************************************************************************************************************************/
132	#ifdef VBOX_STRICT
133	static uint32_t iemNativeEmitGuestRegValueCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off,
134	uint8_t idxReg, IEMNATIVEGSTREG enmGstReg);
135	static void iemNativeRegAssertSanity(PIEMRECOMPILERSTATE pReNative);
136	#endif
137	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
138	static void iemNativeDbgInfoAddNativeOffset(PIEMRECOMPILERSTATE pReNative, uint32_t off);
139	static void iemNativeDbgInfoAddLabel(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType, uint16_t uData);
140	#endif
141	DECL_FORCE_INLINE(void) iemNativeRegClearGstRegShadowing(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, uint32_t off);
142	DECL_FORCE_INLINE(void) iemNativeRegClearGstRegShadowingOne(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg,
143	IEMNATIVEGSTREG enmGstReg, uint32_t off);
144	DECL_INLINE_THROW(void) iemNativeVarRegisterRelease(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar);
145
146
147	/*********************************************************************************************************************************
148	* Executable Memory Allocator *
149	*********************************************************************************************************************************/
150	/** @def IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
151	* Use an alternative chunk sub-allocator that does store internal data
152	* in the chunk.
153	*
154	* Using the RTHeapSimple is not practial on newer darwin systems where
155	* RTMEM_PROT_WRITE and RTMEM_PROT_EXEC are mutually exclusive in process
156	* memory. We would have to change the protection of the whole chunk for
157	* every call to RTHeapSimple, which would be rather expensive.
158	*
159	* This alternative implemenation let restrict page protection modifications
160	* to the pages backing the executable memory we just allocated.
161	*/
162	#define IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
163	/** The chunk sub-allocation unit size in bytes. */
164	#define IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SIZE 128
165	/** The chunk sub-allocation unit size as a shift factor. */
166	#define IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SHIFT 7
167
168	#if defined(IN_RING3) && !defined(RT_OS_WINDOWS)
169	# ifdef IEMNATIVE_USE_GDB_JIT
170	# define IEMNATIVE_USE_GDB_JIT_ET_DYN
171
172	/** GDB JIT: Code entry. */
173	typedef struct GDBJITCODEENTRY
174	{
175	struct GDBJITCODEENTRY *pNext;
176	struct GDBJITCODEENTRY *pPrev;
177	uint8_t *pbSymFile;
178	uint64_t cbSymFile;
179	} GDBJITCODEENTRY;
180
181	/** GDB JIT: Actions. */
182	typedef enum GDBJITACTIONS : uint32_t
183	{
184	kGdbJitaction_NoAction = 0, kGdbJitaction_Register, kGdbJitaction_Unregister
185	} GDBJITACTIONS;
186
187	/** GDB JIT: Descriptor. */
188	typedef struct GDBJITDESCRIPTOR
189	{
190	uint32_t uVersion;
191	GDBJITACTIONS enmAction;
192	GDBJITCODEENTRY *pRelevant;
193	GDBJITCODEENTRY *pHead;
194	/** Our addition: */
195	GDBJITCODEENTRY *pTail;
196	} GDBJITDESCRIPTOR;
197
198	/** GDB JIT: Our simple symbol file data. */
199	typedef struct GDBJITSYMFILE
200	{
201	Elf64_Ehdr EHdr;
202	# ifndef IEMNATIVE_USE_GDB_JIT_ET_DYN
203	Elf64_Shdr aShdrs[5];
204	# else
205	Elf64_Shdr aShdrs[7];
206	Elf64_Phdr aPhdrs[2];
207	# endif
208	/** The dwarf ehframe data for the chunk. */
209	uint8_t abEhFrame[512];
210	char szzStrTab[128];
211	Elf64_Sym aSymbols[3];
212	# ifdef IEMNATIVE_USE_GDB_JIT_ET_DYN
213	Elf64_Sym aDynSyms[2];
214	Elf64_Dyn aDyn[6];
215	# endif
216	} GDBJITSYMFILE;
217
218	extern "C" GDBJITDESCRIPTOR __jit_debug_descriptor;
219	extern "C" DECLEXPORT(void) __jit_debug_register_code(void);
220
221	/** Init once for g_IemNativeGdbJitLock. */
222	static RTONCE g_IemNativeGdbJitOnce = RTONCE_INITIALIZER;
223	/** Init once for the critical section. */
224	static RTCRITSECT g_IemNativeGdbJitLock;
225
226	/** GDB reads the info here. */
227	GDBJITDESCRIPTOR __jit_debug_descriptor = { 1, kGdbJitaction_NoAction, NULL, NULL };
228
229	/** GDB sets a breakpoint on this and checks __jit_debug_descriptor when hit. */
230	DECL_NO_INLINE(RT_NOTHING, DECLEXPORT(void)) __jit_debug_register_code(void)
231	{
232	ASMNopPause();
233	}
234
235	/** @callback_method_impl{FNRTONCE} */
236	static DECLCALLBACK(int32_t) iemNativeGdbJitInitOnce(void *pvUser)
237	{
238	RT_NOREF(pvUser);
239	return RTCritSectInit(&g_IemNativeGdbJitLock);
240	}
241
242
243	# endif /* IEMNATIVE_USE_GDB_JIT */
244
245	/**
246	* Per-chunk unwind info for non-windows hosts.
247	*/
248	typedef struct IEMEXECMEMCHUNKEHFRAME
249	{
250	# ifdef IEMNATIVE_USE_LIBUNWIND
251	/** The offset of the FDA into abEhFrame. */
252	uintptr_t offFda;
253	# else
254	/** 'struct object' storage area. */
255	uint8_t abObject[1024];
256	# endif
257	# ifdef IEMNATIVE_USE_GDB_JIT
258	# if 0
259	/** The GDB JIT 'symbol file' data. */
260	GDBJITSYMFILE GdbJitSymFile;
261	# endif
262	/** The GDB JIT list entry. */
263	GDBJITCODEENTRY GdbJitEntry;
264	# endif
265	/** The dwarf ehframe data for the chunk. */
266	uint8_t abEhFrame[512];
267	} IEMEXECMEMCHUNKEHFRAME;
268	/** Pointer to per-chunk info info for non-windows hosts. */
269	typedef IEMEXECMEMCHUNKEHFRAME *PIEMEXECMEMCHUNKEHFRAME;
270	#endif
271
272
273	/**
274	* An chunk of executable memory.
275	*/
276	typedef struct IEMEXECMEMCHUNK
277	{
278	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
279	/** Number of free items in this chunk. */
280	uint32_t cFreeUnits;
281	/** Hint were to start searching for free space in the allocation bitmap. */
282	uint32_t idxFreeHint;
283	#else
284	/** The heap handle. */
285	RTHEAPSIMPLE hHeap;
286	#endif
287	/** Pointer to the chunk. */
288	void *pvChunk;
289	#ifdef IN_RING3
290	/**
291	* Pointer to the unwind information.
292	*
293	* This is used during C++ throw and longjmp (windows and probably most other
294	* platforms). Some debuggers (windbg) makes use of it as well.
295	*
296	* Windows: This is allocated from hHeap on windows because (at least for
297	* AMD64) the UNWIND_INFO structure address in the
298	* RUNTIME_FUNCTION entry is an RVA and the chunk is the "image".
299	*
300	* Others: Allocated from the regular heap to avoid unnecessary executable data
301	* structures. This points to an IEMEXECMEMCHUNKEHFRAME structure. */
302	void *pvUnwindInfo;
303	#elif defined(IN_RING0)
304	/** Allocation handle. */
305	RTR0MEMOBJ hMemObj;
306	#endif
307	} IEMEXECMEMCHUNK;
308	/** Pointer to a memory chunk. */
309	typedef IEMEXECMEMCHUNK *PIEMEXECMEMCHUNK;
310
311
312	/**
313	* Executable memory allocator for the native recompiler.
314	*/
315	typedef struct IEMEXECMEMALLOCATOR
316	{
317	/** Magic value (IEMEXECMEMALLOCATOR_MAGIC). */
318	uint32_t uMagic;
319
320	/** The chunk size. */
321	uint32_t cbChunk;
322	/** The maximum number of chunks. */
323	uint32_t cMaxChunks;
324	/** The current number of chunks. */
325	uint32_t cChunks;
326	/** Hint where to start looking for available memory. */
327	uint32_t idxChunkHint;
328	/** Statistics: Current number of allocations. */
329	uint32_t cAllocations;
330
331	/** The total amount of memory available. */
332	uint64_t cbTotal;
333	/** Total amount of free memory. */
334	uint64_t cbFree;
335	/** Total amount of memory allocated. */
336	uint64_t cbAllocated;
337
338	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
339	/** Pointer to the allocation bitmaps for all the chunks (follows aChunks).
340	*
341	* Since the chunk size is a power of two and the minimum chunk size is a lot
342	* higher than the IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SIZE, each chunk will always
343	* require a whole number of uint64_t elements in the allocation bitmap. So,
344	* for sake of simplicity, they are allocated as one continous chunk for
345	* simplicity/laziness. */
346	uint64_t *pbmAlloc;
347	/** Number of units (IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SIZE) per chunk. */
348	uint32_t cUnitsPerChunk;
349	/** Number of bitmap elements per chunk (for quickly locating the bitmap
350	* portion corresponding to an chunk). */
351	uint32_t cBitmapElementsPerChunk;
352	#else
353	/** @name Tweaks to get 64 byte aligned allocats w/o unnecessary fragmentation.
354	* @{ */
355	/** The size of the heap internal block header. This is used to adjust the
356	* request memory size to make sure there is exacly enough room for a header at
357	* the end of the blocks we allocate before the next 64 byte alignment line. */
358	uint32_t cbHeapBlockHdr;
359	/** The size of initial heap allocation required make sure the first
360	* allocation is correctly aligned. */
361	uint32_t cbHeapAlignTweak;
362	/** The alignment tweak allocation address. */
363	void *pvAlignTweak;
364	/** @} */
365	#endif
366
367	#if defined(IN_RING3) && !defined(RT_OS_WINDOWS)
368	/** Pointer to the array of unwind info running parallel to aChunks (same
369	* allocation as this structure, located after the bitmaps).
370	* (For Windows, the structures must reside in 32-bit RVA distance to the
371	* actual chunk, so they are allocated off the chunk.) */
372	PIEMEXECMEMCHUNKEHFRAME paEhFrames;
373	#endif
374
375	/** The allocation chunks. */
376	RT_FLEXIBLE_ARRAY_EXTENSION
377	IEMEXECMEMCHUNK aChunks[RT_FLEXIBLE_ARRAY];
378	} IEMEXECMEMALLOCATOR;
379	/** Pointer to an executable memory allocator. */
380	typedef IEMEXECMEMALLOCATOR *PIEMEXECMEMALLOCATOR;
381
382	/** Magic value for IEMEXECMEMALLOCATOR::uMagic (Scott Frederick Turow). */
383	#define IEMEXECMEMALLOCATOR_MAGIC UINT32_C(0x19490412)
384
385
386	static int iemExecMemAllocatorGrow(PVMCPUCC pVCpu, PIEMEXECMEMALLOCATOR pExecMemAllocator);
387
388
389	/**
390	* Worker for iemExecMemAllocatorAlloc that returns @a pvRet after updating
391	* the heap statistics.
392	*/
393	static void * iemExecMemAllocatorAllocTailCode(PIEMEXECMEMALLOCATOR pExecMemAllocator, void *pvRet,
394	uint32_t cbReq, uint32_t idxChunk)
395	{
396	pExecMemAllocator->cAllocations += 1;
397	pExecMemAllocator->cbAllocated += cbReq;
398	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
399	pExecMemAllocator->cbFree -= cbReq;
400	#else
401	pExecMemAllocator->cbFree -= RT_ALIGN_32(cbReq, 64);
402	#endif
403	pExecMemAllocator->idxChunkHint = idxChunk;
404
405	#ifdef RT_OS_DARWIN
406	/*
407	* Sucks, but RTMEM_PROT_EXEC and RTMEM_PROT_WRITE are mutually exclusive
408	* on darwin. So, we mark the pages returned as read+write after alloc and
409	* expect the caller to call iemExecMemAllocatorReadyForUse when done
410	* writing to the allocation.
411	*
412	* See also https://developer.apple.com/documentation/apple-silicon/porting-just-in-time-compilers-to-apple-silicon
413	* for details.
414	*/
415	/** @todo detect if this is necessary... it wasn't required on 10.15 or
416	* whatever older version it was. */
417	int rc = RTMemProtect(pvRet, cbReq, RTMEM_PROT_WRITE \| RTMEM_PROT_READ);
418	AssertRC(rc);
419	#endif
420
421	return pvRet;
422	}
423
424
425	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
426	static void iemExecMemAllocatorAllocInChunkInt(PIEMEXECMEMALLOCATOR pExecMemAllocator, uint64_t pbmAlloc, uint32_t idxFirst,
427	uint32_t cToScan, uint32_t cReqUnits, uint32_t idxChunk)
428	{
429	/*
430	* Shift the bitmap to the idxFirst bit so we can use ASMBitFirstClear.
431	*/
432	Assert(!(cToScan & 63));
433	Assert(!(idxFirst & 63));
434	Assert(cToScan + idxFirst <= pExecMemAllocator->cUnitsPerChunk);
435	pbmAlloc += idxFirst / 64;
436
437	/*
438	* Scan the bitmap for cReqUnits of consequtive clear bits
439	*/
440	/** @todo This can probably be done more efficiently for non-x86 systems. */
441	int iBit = ASMBitFirstClear(pbmAlloc, cToScan);
442	while (iBit >= 0 && (uint32_t)iBit <= cToScan - cReqUnits)
443	{
444	uint32_t idxAddBit = 1;
445	while (idxAddBit < cReqUnits && !ASMBitTest(pbmAlloc, (uint32_t)iBit + idxAddBit))
446	idxAddBit++;
447	if (idxAddBit >= cReqUnits)
448	{
449	ASMBitSetRange(pbmAlloc, (uint32_t)iBit, (uint32_t)iBit + cReqUnits);
450
451	PIEMEXECMEMCHUNK const pChunk = &pExecMemAllocator->aChunks[idxChunk];
452	pChunk->cFreeUnits -= cReqUnits;
453	pChunk->idxFreeHint = (uint32_t)iBit + cReqUnits;
454
455	void * const pvRet = (uint8_t *)pChunk->pvChunk
456	+ ((idxFirst + (uint32_t)iBit) << IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SHIFT);
457
458	return iemExecMemAllocatorAllocTailCode(pExecMemAllocator, pvRet,
459	cReqUnits << IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SHIFT, idxChunk);
460	}
461
462	iBit = ASMBitNextClear(pbmAlloc, cToScan, iBit + idxAddBit - 1);
463	}
464	return NULL;
465	}
466	#endif /* IEMEXECMEM_USE_ALT_SUB_ALLOCATOR */
467
468
469	static void *iemExecMemAllocatorAllocInChunk(PIEMEXECMEMALLOCATOR pExecMemAllocator, uint32_t idxChunk, uint32_t cbReq)
470	{
471	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
472	/*
473	* Figure out how much to allocate.
474	*/
475	uint32_t const cReqUnits = (cbReq + IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SIZE - 1) >> IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SHIFT;
476	if (cReqUnits <= pExecMemAllocator->aChunks[idxChunk].cFreeUnits)
477	{
478	uint64_t * const pbmAlloc = &pExecMemAllocator->pbmAlloc[pExecMemAllocator->cBitmapElementsPerChunk * idxChunk];
479	uint32_t const idxHint = pExecMemAllocator->aChunks[idxChunk].idxFreeHint & ~(uint32_t)63;
480	if (idxHint + cReqUnits <= pExecMemAllocator->cUnitsPerChunk)
481	{
482	void *pvRet = iemExecMemAllocatorAllocInChunkInt(pExecMemAllocator, pbmAlloc, idxHint,
483	pExecMemAllocator->cUnitsPerChunk - idxHint, cReqUnits, idxChunk);
484	if (pvRet)
485	return pvRet;
486	}
487	return iemExecMemAllocatorAllocInChunkInt(pExecMemAllocator, pbmAlloc, 0,
488	RT_MIN(pExecMemAllocator->cUnitsPerChunk, RT_ALIGN_32(idxHint + cReqUnits, 64)),
489	cReqUnits, idxChunk);
490	}
491	#else
492	void *pvRet = RTHeapSimpleAlloc(pExecMemAllocator->aChunks[idxChunk].hHeap, cbReq, 32);
493	if (pvRet)
494	return iemExecMemAllocatorAllocTailCode(pExecMemAllocator, pvRet, cbReq, idxChunk);
495	#endif
496	return NULL;
497
498	}
499
500
501	/**
502	* Allocates @a cbReq bytes of executable memory.
503	*
504	* @returns Pointer to the memory, NULL if out of memory or other problem
505	* encountered.
506	* @param pVCpu The cross context virtual CPU structure of the calling
507	* thread.
508	* @param cbReq How many bytes are required.
509	*/
510	static void *iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq)
511	{
512	PIEMEXECMEMALLOCATOR pExecMemAllocator = pVCpu->iem.s.pExecMemAllocatorR3;
513	AssertReturn(pExecMemAllocator && pExecMemAllocator->uMagic == IEMEXECMEMALLOCATOR_MAGIC, NULL);
514	AssertMsgReturn(cbReq > 32 && cbReq < _512K, ("%#x\n", cbReq), NULL);
515
516
517	for (unsigned iIteration = 0;; iIteration++)
518	{
519	/*
520	* Adjust the request size so it'll fit the allocator alignment/whatnot.
521	*
522	* For the RTHeapSimple allocator this means to follow the logic described
523	* in iemExecMemAllocatorGrow and attempt to allocate it from one of the
524	* existing chunks if we think we've got sufficient free memory around.
525	*
526	* While for the alternative one we just align it up to a whole unit size.
527	*/
528	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
529	cbReq = RT_ALIGN_32(cbReq, IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SIZE);
530	#else
531	cbReq = RT_ALIGN_32(cbReq + pExecMemAllocator->cbHeapBlockHdr, 64) - pExecMemAllocator->cbHeapBlockHdr;
532	#endif
533	if (cbReq <= pExecMemAllocator->cbFree)
534	{
535	uint32_t const cChunks = pExecMemAllocator->cChunks;
536	uint32_t const idxChunkHint = pExecMemAllocator->idxChunkHint < cChunks ? pExecMemAllocator->idxChunkHint : 0;
537	for (uint32_t idxChunk = idxChunkHint; idxChunk < cChunks; idxChunk++)
538	{
539	void *pvRet = iemExecMemAllocatorAllocInChunk(pExecMemAllocator, idxChunk, cbReq);
540	if (pvRet)
541	return pvRet;
542	}
543	for (uint32_t idxChunk = 0; idxChunk < idxChunkHint; idxChunk++)
544	{
545	void *pvRet = iemExecMemAllocatorAllocInChunk(pExecMemAllocator, idxChunk, cbReq);
546	if (pvRet)
547	return pvRet;
548	}
549	}
550
551	/*
552	* Can we grow it with another chunk?
553	*/
554	if (pExecMemAllocator->cChunks < pExecMemAllocator->cMaxChunks)
555	{
556	int rc = iemExecMemAllocatorGrow(pVCpu, pExecMemAllocator);
557	AssertLogRelRCReturn(rc, NULL);
558
559	uint32_t const idxChunk = pExecMemAllocator->cChunks - 1;
560	void *pvRet = iemExecMemAllocatorAllocInChunk(pExecMemAllocator, idxChunk, cbReq);
561	if (pvRet)
562	return pvRet;
563	AssertFailed();
564	}
565
566	/*
567	* Try prune native TBs once.
568	*/
569	if (iIteration == 0)
570	iemTbAllocatorFreeupNativeSpace(pVCpu, cbReq / sizeof(IEMNATIVEINSTR));
571	else
572	{
573	/** @todo stats... */
574	return NULL;
575	}
576	}
577
578	}
579
580
581	/** This is a hook that we may need later for changing memory protection back
582	* to readonly+exec */
583	static void iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb)
584	{
585	#ifdef RT_OS_DARWIN
586	/* See iemExecMemAllocatorAllocTailCode for the explanation. */
587	int rc = RTMemProtect(pv, cb, RTMEM_PROT_EXEC \| RTMEM_PROT_READ);
588	AssertRC(rc); RT_NOREF(pVCpu);
589
590	/*
591	* Flush the instruction cache:
592	* https://developer.apple.com/documentation/apple-silicon/porting-just-in-time-compilers-to-apple-silicon
593	*/
594	/* sys_dcache_flush(pv, cb); - not necessary */
595	sys_icache_invalidate(pv, cb);
596	#else
597	RT_NOREF(pVCpu, pv, cb);
598	#endif
599	}
600
601
602	/**
603	* Frees executable memory.
604	*/
605	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb)
606	{
607	PIEMEXECMEMALLOCATOR pExecMemAllocator = pVCpu->iem.s.pExecMemAllocatorR3;
608	Assert(pExecMemAllocator && pExecMemAllocator->uMagic == IEMEXECMEMALLOCATOR_MAGIC);
609	Assert(pv);
610	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
611	Assert(!((uintptr_t)pv & (IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SIZE - 1)));
612	#else
613	Assert(!((uintptr_t)pv & 63));
614	#endif
615
616	/* Align the size as we did when allocating the block. */
617	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
618	cb = RT_ALIGN_Z(cb, IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SIZE);
619	#else
620	cb = RT_ALIGN_Z(cb + pExecMemAllocator->cbHeapBlockHdr, 64) - pExecMemAllocator->cbHeapBlockHdr;
621	#endif
622
623	/* Free it / assert sanity. */
624	#if defined(VBOX_STRICT) \|\| defined(IEMEXECMEM_USE_ALT_SUB_ALLOCATOR)
625	uint32_t const cChunks = pExecMemAllocator->cChunks;
626	uint32_t const cbChunk = pExecMemAllocator->cbChunk;
627	bool fFound = false;
628	for (uint32_t idxChunk = 0; idxChunk < cChunks; idxChunk++)
629	{
630	uintptr_t const offChunk = (uintptr_t)pv - (uintptr_t)pExecMemAllocator->aChunks[idxChunk].pvChunk;
631	fFound = offChunk < cbChunk;
632	if (fFound)
633	{
634	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
635	uint32_t const idxFirst = (uint32_t)offChunk >> IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SHIFT;
636	uint32_t const cReqUnits = (uint32_t)cb >> IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SHIFT;
637
638	/* Check that it's valid and free it. */
639	uint64_t * const pbmAlloc = &pExecMemAllocator->pbmAlloc[pExecMemAllocator->cBitmapElementsPerChunk * idxChunk];
640	AssertReturnVoid(ASMBitTest(pbmAlloc, idxFirst));
641	for (uint32_t i = 1; i < cReqUnits; i++)
642	AssertReturnVoid(ASMBitTest(pbmAlloc, idxFirst + i));
643	ASMBitClearRange(pbmAlloc, idxFirst, idxFirst + cReqUnits);
644
645	pExecMemAllocator->aChunks[idxChunk].cFreeUnits += cReqUnits;
646	pExecMemAllocator->aChunks[idxChunk].idxFreeHint = idxFirst;
647
648	/* Update the stats. */
649	pExecMemAllocator->cbAllocated -= cb;
650	pExecMemAllocator->cbFree += cb;
651	pExecMemAllocator->cAllocations -= 1;
652	return;
653	#else
654	Assert(RTHeapSimpleSize(pExecMemAllocator->aChunks[idxChunk].hHeap, pv) == cb);
655	break;
656	#endif
657	}
658	}
659	# ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
660	AssertFailed();
661	# else
662	Assert(fFound);
663	# endif
664	#endif
665
666	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
667	/* Update stats while cb is freshly calculated.*/
668	pExecMemAllocator->cbAllocated -= cb;
669	pExecMemAllocator->cbFree += RT_ALIGN_Z(cb, 64);
670	pExecMemAllocator->cAllocations -= 1;
671
672	/* Free it. */
673	RTHeapSimpleFree(NIL_RTHEAPSIMPLE, pv);
674	#endif
675	}
676
677
678
679	#ifdef IN_RING3
680	# ifdef RT_OS_WINDOWS
681
682	/**
683	* Initializes the unwind info structures for windows hosts.
684	*/
685	static int
686	iemExecMemAllocatorInitAndRegisterUnwindInfoForChunk(PVMCPUCC pVCpu, PIEMEXECMEMALLOCATOR pExecMemAllocator,
687	void *pvChunk, uint32_t idxChunk)
688	{
689	RT_NOREF(pVCpu);
690
691	/*
692	* The AMD64 unwind opcodes.
693	*
694	* This is a program that starts with RSP after a RET instruction that
695	* ends up in recompiled code, and the operations we describe here will
696	* restore all non-volatile registers and bring RSP back to where our
697	* RET address is. This means it's reverse order from what happens in
698	* the prologue.
699	*
700	* Note! Using a frame register approach here both because we have one
701	* and but mainly because the UWOP_ALLOC_LARGE argument values
702	* would be a pain to write initializers for. On the positive
703	* side, we're impervious to changes in the the stack variable
704	* area can can deal with dynamic stack allocations if necessary.
705	*/
706	static const IMAGE_UNWIND_CODE s_aOpcodes[] =
707	{
708	{ { 16, IMAGE_AMD64_UWOP_SET_FPREG, 0 } }, /* RSP = RBP - FrameOffset * 10 (0x60) */
709	{ { 16, IMAGE_AMD64_UWOP_ALLOC_SMALL, 0 } }, /* RSP += 8; */
710	{ { 14, IMAGE_AMD64_UWOP_PUSH_NONVOL, X86_GREG_x15 } }, /* R15 = [RSP]; RSP += 8; */
711	{ { 12, IMAGE_AMD64_UWOP_PUSH_NONVOL, X86_GREG_x14 } }, /* R14 = [RSP]; RSP += 8; */
712	{ { 10, IMAGE_AMD64_UWOP_PUSH_NONVOL, X86_GREG_x13 } }, /* R13 = [RSP]; RSP += 8; */
713	{ { 8, IMAGE_AMD64_UWOP_PUSH_NONVOL, X86_GREG_x12 } }, /* R12 = [RSP]; RSP += 8; */
714	{ { 7, IMAGE_AMD64_UWOP_PUSH_NONVOL, X86_GREG_xDI } }, /* RDI = [RSP]; RSP += 8; */
715	{ { 6, IMAGE_AMD64_UWOP_PUSH_NONVOL, X86_GREG_xSI } }, /* RSI = [RSP]; RSP += 8; */
716	{ { 5, IMAGE_AMD64_UWOP_PUSH_NONVOL, X86_GREG_xBX } }, /* RBX = [RSP]; RSP += 8; */
717	{ { 4, IMAGE_AMD64_UWOP_PUSH_NONVOL, X86_GREG_xBP } }, /* RBP = [RSP]; RSP += 8; */
718	};
719	union
720	{
721	IMAGE_UNWIND_INFO Info;
722	uint8_t abPadding[RT_UOFFSETOF(IMAGE_UNWIND_INFO, aOpcodes) + 16];
723	} s_UnwindInfo =
724	{
725	{
726	/* .Version = */ 1,
727	/* .Flags = */ 0,
728	/* .SizeOfProlog = / 16, / whatever */
729	/* .CountOfCodes = */ RT_ELEMENTS(s_aOpcodes),
730	/* .FrameRegister = */ X86_GREG_xBP,
731	/* .FrameOffset = / (-IEMNATIVE_FP_OFF_LAST_PUSH + 8) / 16 / we're off by one slot. sigh. */,
732	}
733	};
734	AssertCompile(-IEMNATIVE_FP_OFF_LAST_PUSH < 240 && -IEMNATIVE_FP_OFF_LAST_PUSH > 0);
735	AssertCompile((-IEMNATIVE_FP_OFF_LAST_PUSH & 0xf) == 8);
736
737	/*
738	* Calc how much space we need and allocate it off the exec heap.
739	*/
740	unsigned const cFunctionEntries = 1;
741	unsigned const cbUnwindInfo = sizeof(s_aOpcodes) + RT_UOFFSETOF(IMAGE_UNWIND_INFO, aOpcodes);
742	unsigned const cbNeeded = sizeof(IMAGE_RUNTIME_FUNCTION_ENTRY) * cFunctionEntries + cbUnwindInfo;
743	# ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
744	unsigned const cbNeededAligned = RT_ALIGN_32(cbNeeded, IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SIZE);
745	PIMAGE_RUNTIME_FUNCTION_ENTRY const paFunctions
746	= (PIMAGE_RUNTIME_FUNCTION_ENTRY)iemExecMemAllocatorAllocInChunk(pExecMemAllocator, idxChunk, cbNeededAligned);
747	# else
748	unsigned const cbNeededAligned = RT_ALIGN_32(cbNeeded + pExecMemAllocator->cbHeapBlockHdr, 64)
749	- pExecMemAllocator->cbHeapBlockHdr;
750	PIMAGE_RUNTIME_FUNCTION_ENTRY const paFunctions = (PIMAGE_RUNTIME_FUNCTION_ENTRY)RTHeapSimpleAlloc(hHeap, cbNeededAligned,
751	32 /cbAlignment/);
752	# endif
753	AssertReturn(paFunctions, VERR_INTERNAL_ERROR_5);
754	pExecMemAllocator->aChunks[idxChunk].pvUnwindInfo = paFunctions;
755
756	/*
757	* Initialize the structures.
758	*/
759	PIMAGE_UNWIND_INFO const pInfo = (PIMAGE_UNWIND_INFO)&paFunctions[cFunctionEntries];
760
761	paFunctions[0].BeginAddress = 0;
762	paFunctions[0].EndAddress = pExecMemAllocator->cbChunk;
763	paFunctions[0].UnwindInfoAddress = (uint32_t)((uintptr_t)pInfo - (uintptr_t)pvChunk);
764
765	memcpy(pInfo, &s_UnwindInfo, RT_UOFFSETOF(IMAGE_UNWIND_INFO, aOpcodes));
766	memcpy(&pInfo->aOpcodes[0], s_aOpcodes, sizeof(s_aOpcodes));
767
768	/*
769	* Register it.
770	*/
771	uint8_t fRet = RtlAddFunctionTable(paFunctions, cFunctionEntries, (uintptr_t)pvChunk);
772	AssertReturn(fRet, VERR_INTERNAL_ERROR_3); /* Nothing to clean up on failure, since its within the chunk itself. */
773
774	return VINF_SUCCESS;
775	}
776
777
778	# else /* !RT_OS_WINDOWS */
779
780	/**
781	* Emits a LEB128 encoded value between -0x2000 and 0x2000 (both exclusive).
782	*/
783	DECLINLINE(RTPTRUNION) iemDwarfPutLeb128(RTPTRUNION Ptr, int32_t iValue)
784	{
785	if (iValue >= 64)
786	{
787	Assert(iValue < 0x2000);
788	*Ptr.pb++ = ((uint8_t)iValue & 0x7f) \| 0x80;
789	*Ptr.pb++ = (uint8_t)(iValue >> 7) & 0x3f;
790	}
791	else if (iValue >= 0)
792	*Ptr.pb++ = (uint8_t)iValue;
793	else if (iValue > -64)
794	*Ptr.pb++ = ((uint8_t)iValue & 0x3f) \| 0x40;
795	else
796	{
797	Assert(iValue > -0x2000);
798	*Ptr.pb++ = ((uint8_t)iValue & 0x7f) \| 0x80;
799	*Ptr.pb++ = ((uint8_t)(iValue >> 7) & 0x3f) \| 0x40;
800	}
801	return Ptr;
802	}
803
804
805	/**
806	* Emits an ULEB128 encoded value (up to 64-bit wide).
807	*/
808	DECLINLINE(RTPTRUNION) iemDwarfPutUleb128(RTPTRUNION Ptr, uint64_t uValue)
809	{
810	while (uValue >= 0x80)
811	{
812	*Ptr.pb++ = ((uint8_t)uValue & 0x7f) \| 0x80;
813	uValue >>= 7;
814	}
815	*Ptr.pb++ = (uint8_t)uValue;
816	return Ptr;
817	}
818
819
820	/**
821	* Emits a CFA rule as register @a uReg + offset @a off.
822	*/
823	DECLINLINE(RTPTRUNION) iemDwarfPutCfaDefCfa(RTPTRUNION Ptr, uint32_t uReg, uint32_t off)
824	{
825	*Ptr.pb++ = DW_CFA_def_cfa;
826	Ptr = iemDwarfPutUleb128(Ptr, uReg);
827	Ptr = iemDwarfPutUleb128(Ptr, off);
828	return Ptr;
829	}
830
831
832	/**
833	* Emits a register (@a uReg) save location:
834	* CFA + @a off * data_alignment_factor
835	*/
836	DECLINLINE(RTPTRUNION) iemDwarfPutCfaOffset(RTPTRUNION Ptr, uint32_t uReg, uint32_t off)
837	{
838	if (uReg < 0x40)
839	*Ptr.pb++ = DW_CFA_offset \| uReg;
840	else
841	{
842	*Ptr.pb++ = DW_CFA_offset_extended;
843	Ptr = iemDwarfPutUleb128(Ptr, uReg);
844	}
845	Ptr = iemDwarfPutUleb128(Ptr, off);
846	return Ptr;
847	}
848
849
850	# if 0 /* unused */
851	/**
852	* Emits a register (@a uReg) save location, using signed offset:
853	* CFA + @a offSigned * data_alignment_factor
854	*/
855	DECLINLINE(RTPTRUNION) iemDwarfPutCfaSignedOffset(RTPTRUNION Ptr, uint32_t uReg, int32_t offSigned)
856	{
857	*Ptr.pb++ = DW_CFA_offset_extended_sf;
858	Ptr = iemDwarfPutUleb128(Ptr, uReg);
859	Ptr = iemDwarfPutLeb128(Ptr, offSigned);
860	return Ptr;
861	}
862	# endif
863
864
865	/**
866	* Initializes the unwind info section for non-windows hosts.
867	*/
868	static int
869	iemExecMemAllocatorInitAndRegisterUnwindInfoForChunk(PVMCPUCC pVCpu, PIEMEXECMEMALLOCATOR pExecMemAllocator,
870	void *pvChunk, uint32_t idxChunk)
871	{
872	PIEMEXECMEMCHUNKEHFRAME const pEhFrame = &pExecMemAllocator->paEhFrames[idxChunk];
873	pExecMemAllocator->aChunks[idxChunk].pvUnwindInfo = pEhFrame; /* not necessary, but whatever */
874
875	RTPTRUNION Ptr = { pEhFrame->abEhFrame };
876
877	/*
878	* Generate the CIE first.
879	*/
880	# ifdef IEMNATIVE_USE_LIBUNWIND /* libunwind (llvm, darwin) only supports v1 and v3. */
881	uint8_t const iDwarfVer = 3;
882	# else
883	uint8_t const iDwarfVer = 4;
884	# endif
885	RTPTRUNION const PtrCie = Ptr;
886	Ptr.pu32++ = 123; / The CIE length will be determined later. */
887	Ptr.pu32++ = 0 /UINT32_MAX/; / I'm a CIE in .eh_frame speak. */
888	Ptr.pb++ = iDwarfVer; / DwARF version */
889	Ptr.pb++ = 0; / Augmentation. */
890	if (iDwarfVer >= 4)
891	{
892	Ptr.pb++ = sizeof(uintptr_t); / Address size. */
893	Ptr.pb++ = 0; / Segment selector size. */
894	}
895	# ifdef RT_ARCH_AMD64
896	Ptr = iemDwarfPutLeb128(Ptr, 1); /* Code alignment factor (LEB128 = 1). */
897	# else
898	Ptr = iemDwarfPutLeb128(Ptr, 4); /* Code alignment factor (LEB128 = 4). */
899	# endif
900	Ptr = iemDwarfPutLeb128(Ptr, -8); /* Data alignment factor (LEB128 = -8). */
901	# ifdef RT_ARCH_AMD64
902	Ptr = iemDwarfPutUleb128(Ptr, DWREG_AMD64_RA); /* Return address column (ULEB128) */
903	# elif defined(RT_ARCH_ARM64)
904	Ptr = iemDwarfPutUleb128(Ptr, DWREG_ARM64_LR); /* Return address column (ULEB128) */
905	# else
906	# error "port me"
907	# endif
908	/* Initial instructions: */
909	# ifdef RT_ARCH_AMD64
910	Ptr = iemDwarfPutCfaDefCfa(Ptr, DWREG_AMD64_RBP, 16); /* CFA = RBP + 0x10 - first stack parameter */
911	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_AMD64_RA, 1); /* Ret RIP = [CFA + 1-8] /
912	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_AMD64_RBP, 2); /* RBP = [CFA + 2-8] /
913	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_AMD64_RBX, 3); /* RBX = [CFA + 3-8] /
914	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_AMD64_R12, 4); /* R12 = [CFA + 4-8] /
915	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_AMD64_R13, 5); /* R13 = [CFA + 5-8] /
916	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_AMD64_R14, 6); /* R14 = [CFA + 6-8] /
917	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_AMD64_R15, 7); /* R15 = [CFA + 7-8] /
918	# elif defined(RT_ARCH_ARM64)
919	# if 1
920	Ptr = iemDwarfPutCfaDefCfa(Ptr, DWREG_ARM64_BP, 16); /* CFA = BP + 0x10 - first stack parameter */
921	# else
922	Ptr = iemDwarfPutCfaDefCfa(Ptr, DWREG_ARM64_SP, IEMNATIVE_FRAME_VAR_SIZE + IEMNATIVE_FRAME_SAVE_REG_SIZE);
923	# endif
924	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_ARM64_LR, 1); /* Ret PC = [CFA + 1-8] /
925	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_ARM64_BP, 2); /* Ret BP = [CFA + 2-8] /
926	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_ARM64_X28, 3); /* X28 = [CFA + 3-8] /
927	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_ARM64_X27, 4); /* X27 = [CFA + 4-8] /
928	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_ARM64_X26, 5); /* X26 = [CFA + 5-8] /
929	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_ARM64_X25, 6); /* X25 = [CFA + 6-8] /
930	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_ARM64_X24, 7); /* X24 = [CFA + 7-8] /
931	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_ARM64_X23, 8); /* X23 = [CFA + 8-8] /
932	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_ARM64_X22, 9); /* X22 = [CFA + 9-8] /
933	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_ARM64_X21, 10); /* X21 = [CFA +10-8] /
934	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_ARM64_X20, 11); /* X20 = [CFA +11-8] /
935	Ptr = iemDwarfPutCfaOffset(Ptr, DWREG_ARM64_X19, 12); /* X19 = [CFA +12-8] /
936	AssertCompile(IEMNATIVE_FRAME_SAVE_REG_SIZE / 8 == 12);
937	/** @todo we we need to do something about clearing DWREG_ARM64_RA_SIGN_STATE or something? */
938	# else
939	# error "port me"
940	# endif
941	while ((Ptr.u - PtrCie.u) & 3)
942	*Ptr.pb++ = DW_CFA_nop;
943	/* Finalize the CIE size. */
944	*PtrCie.pu32 = Ptr.u - PtrCie.u - sizeof(uint32_t);
945
946	/*
947	* Generate an FDE for the whole chunk area.
948	*/
949	# ifdef IEMNATIVE_USE_LIBUNWIND
950	pEhFrame->offFda = Ptr.u - (uintptr_t)&pEhFrame->abEhFrame[0];
951	# endif
952	RTPTRUNION const PtrFde = Ptr;
953	Ptr.pu32++ = 123; / The CIE length will be determined later. */
954	Ptr.pu32 = Ptr.u - PtrCie.u; / Negated self relative CIE address. */
955	Ptr.pu32++;
956	Ptr.pu64++ = (uintptr_t)pvChunk; / Absolute start PC of this FDE. */
957	Ptr.pu64++ = pExecMemAllocator->cbChunk; / PC range length for this PDE. */
958	# if 0 /* not requried for recent libunwind.dylib nor recent libgcc/glib. */
959	*Ptr.pb++ = DW_CFA_nop;
960	# endif
961	while ((Ptr.u - PtrFde.u) & 3)
962	*Ptr.pb++ = DW_CFA_nop;
963	/* Finalize the FDE size. */
964	*PtrFde.pu32 = Ptr.u - PtrFde.u - sizeof(uint32_t);
965
966	/* Terminator entry. */
967	*Ptr.pu32++ = 0;
968	Ptr.pu32++ = 0; / just to be sure... */
969	Assert(Ptr.u - (uintptr_t)&pEhFrame->abEhFrame[0] <= sizeof(pEhFrame->abEhFrame));
970
971	/*
972	* Register it.
973	*/
974	# ifdef IEMNATIVE_USE_LIBUNWIND
975	__register_frame(&pEhFrame->abEhFrame[pEhFrame->offFda]);
976	# else
977	memset(pEhFrame->abObject, 0xf6, sizeof(pEhFrame->abObject)); /* color the memory to better spot usage */
978	__register_frame_info(pEhFrame->abEhFrame, pEhFrame->abObject);
979	# endif
980
981	# ifdef IEMNATIVE_USE_GDB_JIT
982	/*
983	* Now for telling GDB about this (experimental).
984	*
985	* This seems to work best with ET_DYN.
986	*/
987	unsigned const cbNeeded = sizeof(GDBJITSYMFILE);
988	# ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
989	unsigned const cbNeededAligned = RT_ALIGN_32(cbNeeded, IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SIZE);
990	GDBJITSYMFILE * const pSymFile = (GDBJITSYMFILE *)iemExecMemAllocatorAllocInChunk(pExecMemAllocator, idxChunk, cbNeededAligned);
991	# else
992	unsigned const cbNeededAligned = RT_ALIGN_32(cbNeeded + pExecMemAllocator->cbHeapBlockHdr, 64)
993	- pExecMemAllocator->cbHeapBlockHdr;
994	GDBJITSYMFILE * const pSymFile = (PIMAGE_RUNTIME_FUNCTION_ENTRY)RTHeapSimpleAlloc(hHeap, cbNeededAligned, 32 /cbAlignment/);
995	# endif
996	AssertReturn(pSymFile, VERR_INTERNAL_ERROR_5);
997	unsigned const offSymFileInChunk = (uintptr_t)pSymFile - (uintptr_t)pvChunk;
998
999	RT_ZERO(*pSymFile);
1000
1001	/*
1002	* The ELF header:
1003	*/
1004	pSymFile->EHdr.e_ident[0] = ELFMAG0;
1005	pSymFile->EHdr.e_ident[1] = ELFMAG1;
1006	pSymFile->EHdr.e_ident[2] = ELFMAG2;
1007	pSymFile->EHdr.e_ident[3] = ELFMAG3;
1008	pSymFile->EHdr.e_ident[EI_VERSION] = EV_CURRENT;
1009	pSymFile->EHdr.e_ident[EI_CLASS] = ELFCLASS64;
1010	pSymFile->EHdr.e_ident[EI_DATA] = ELFDATA2LSB;
1011	pSymFile->EHdr.e_ident[EI_OSABI] = ELFOSABI_NONE;
1012	# ifdef IEMNATIVE_USE_GDB_JIT_ET_DYN
1013	pSymFile->EHdr.e_type = ET_DYN;
1014	# else
1015	pSymFile->EHdr.e_type = ET_REL;
1016	# endif
1017	# ifdef RT_ARCH_AMD64
1018	pSymFile->EHdr.e_machine = EM_AMD64;
1019	# elif defined(RT_ARCH_ARM64)
1020	pSymFile->EHdr.e_machine = EM_AARCH64;
1021	# else
1022	# error "port me"
1023	# endif
1024	pSymFile->EHdr.e_version = 1; /?/
1025	pSymFile->EHdr.e_entry = 0;
1026	# if defined(IEMNATIVE_USE_GDB_JIT_ET_DYN)
1027	pSymFile->EHdr.e_phoff = RT_UOFFSETOF(GDBJITSYMFILE, aPhdrs);
1028	# else
1029	pSymFile->EHdr.e_phoff = 0;
1030	# endif
1031	pSymFile->EHdr.e_shoff = sizeof(pSymFile->EHdr);
1032	pSymFile->EHdr.e_flags = 0;
1033	pSymFile->EHdr.e_ehsize = sizeof(pSymFile->EHdr);
1034	# if defined(IEMNATIVE_USE_GDB_JIT_ET_DYN)
1035	pSymFile->EHdr.e_phentsize = sizeof(pSymFile->aPhdrs[0]);
1036	pSymFile->EHdr.e_phnum = RT_ELEMENTS(pSymFile->aPhdrs);
1037	# else
1038	pSymFile->EHdr.e_phentsize = 0;
1039	pSymFile->EHdr.e_phnum = 0;
1040	# endif
1041	pSymFile->EHdr.e_shentsize = sizeof(pSymFile->aShdrs[0]);
1042	pSymFile->EHdr.e_shnum = RT_ELEMENTS(pSymFile->aShdrs);
1043	pSymFile->EHdr.e_shstrndx = 0; /* set later */
1044
1045	uint32_t offStrTab = 0;
1046	#define APPEND_STR(a_szStr) do { \
1047	memcpy(&pSymFile->szzStrTab[offStrTab], a_szStr, sizeof(a_szStr)); \
1048	offStrTab += sizeof(a_szStr); \
1049	Assert(offStrTab < sizeof(pSymFile->szzStrTab)); \
1050	} while (0)
1051	#define APPEND_STR_FMT(a_szStr, ...) do { \
1052	offStrTab += RTStrPrintf(&pSymFile->szzStrTab[offStrTab], sizeof(pSymFile->szzStrTab) - offStrTab, a_szStr, __VA_ARGS__); \
1053	offStrTab++; \
1054	Assert(offStrTab < sizeof(pSymFile->szzStrTab)); \
1055	} while (0)
1056
1057	/*
1058	* Section headers.
1059	*/
1060	/* Section header #0: NULL */
1061	unsigned i = 0;
1062	APPEND_STR("");
1063	RT_ZERO(pSymFile->aShdrs[i]);
1064	i++;
1065
1066	/* Section header: .eh_frame */
1067	pSymFile->aShdrs[i].sh_name = offStrTab;
1068	APPEND_STR(".eh_frame");
1069	pSymFile->aShdrs[i].sh_type = SHT_PROGBITS;
1070	pSymFile->aShdrs[i].sh_flags = SHF_ALLOC \| SHF_EXECINSTR;
1071	# if defined(IEMNATIVE_USE_GDB_JIT_ET_DYN) \|\| defined(IEMNATIVE_USE_GDB_JIT_ELF_RVAS)
1072	pSymFile->aShdrs[i].sh_offset
1073	= pSymFile->aShdrs[i].sh_addr = RT_UOFFSETOF(GDBJITSYMFILE, abEhFrame);
1074	# else
1075	pSymFile->aShdrs[i].sh_addr = (uintptr_t)&pSymFile->abEhFrame[0];
1076	pSymFile->aShdrs[i].sh_offset = 0;
1077	# endif
1078
1079	pSymFile->aShdrs[i].sh_size = sizeof(pEhFrame->abEhFrame);
1080	pSymFile->aShdrs[i].sh_link = 0;
1081	pSymFile->aShdrs[i].sh_info = 0;
1082	pSymFile->aShdrs[i].sh_addralign = 1;
1083	pSymFile->aShdrs[i].sh_entsize = 0;
1084	memcpy(pSymFile->abEhFrame, pEhFrame->abEhFrame, sizeof(pEhFrame->abEhFrame));
1085	i++;
1086
1087	/* Section header: .shstrtab */
1088	unsigned const iShStrTab = i;
1089	pSymFile->EHdr.e_shstrndx = iShStrTab;
1090	pSymFile->aShdrs[i].sh_name = offStrTab;
1091	APPEND_STR(".shstrtab");
1092	pSymFile->aShdrs[i].sh_type = SHT_STRTAB;
1093	pSymFile->aShdrs[i].sh_flags = SHF_ALLOC;
1094	# if defined(IEMNATIVE_USE_GDB_JIT_ET_DYN) \|\| defined(IEMNATIVE_USE_GDB_JIT_ELF_RVAS)
1095	pSymFile->aShdrs[i].sh_offset
1096	= pSymFile->aShdrs[i].sh_addr = RT_UOFFSETOF(GDBJITSYMFILE, szzStrTab);
1097	# else
1098	pSymFile->aShdrs[i].sh_addr = (uintptr_t)&pSymFile->szzStrTab[0];
1099	pSymFile->aShdrs[i].sh_offset = 0;
1100	# endif
1101	pSymFile->aShdrs[i].sh_size = sizeof(pSymFile->szzStrTab);
1102	pSymFile->aShdrs[i].sh_link = 0;
1103	pSymFile->aShdrs[i].sh_info = 0;
1104	pSymFile->aShdrs[i].sh_addralign = 1;
1105	pSymFile->aShdrs[i].sh_entsize = 0;
1106	i++;
1107
1108	/* Section header: .symbols */
1109	pSymFile->aShdrs[i].sh_name = offStrTab;
1110	APPEND_STR(".symtab");
1111	pSymFile->aShdrs[i].sh_type = SHT_SYMTAB;
1112	pSymFile->aShdrs[i].sh_flags = SHF_ALLOC;
1113	pSymFile->aShdrs[i].sh_offset
1114	= pSymFile->aShdrs[i].sh_addr = RT_UOFFSETOF(GDBJITSYMFILE, aSymbols);
1115	pSymFile->aShdrs[i].sh_size = sizeof(pSymFile->aSymbols);
1116	pSymFile->aShdrs[i].sh_link = iShStrTab;
1117	pSymFile->aShdrs[i].sh_info = RT_ELEMENTS(pSymFile->aSymbols);
1118	pSymFile->aShdrs[i].sh_addralign = sizeof(pSymFile->aSymbols[0].st_value);
1119	pSymFile->aShdrs[i].sh_entsize = sizeof(pSymFile->aSymbols[0]);
1120	i++;
1121
1122	# if defined(IEMNATIVE_USE_GDB_JIT_ET_DYN)
1123	/* Section header: .symbols */
1124	pSymFile->aShdrs[i].sh_name = offStrTab;
1125	APPEND_STR(".dynsym");
1126	pSymFile->aShdrs[i].sh_type = SHT_DYNSYM;
1127	pSymFile->aShdrs[i].sh_flags = SHF_ALLOC;
1128	pSymFile->aShdrs[i].sh_offset
1129	= pSymFile->aShdrs[i].sh_addr = RT_UOFFSETOF(GDBJITSYMFILE, aDynSyms);
1130	pSymFile->aShdrs[i].sh_size = sizeof(pSymFile->aDynSyms);
1131	pSymFile->aShdrs[i].sh_link = iShStrTab;
1132	pSymFile->aShdrs[i].sh_info = RT_ELEMENTS(pSymFile->aDynSyms);
1133	pSymFile->aShdrs[i].sh_addralign = sizeof(pSymFile->aDynSyms[0].st_value);
1134	pSymFile->aShdrs[i].sh_entsize = sizeof(pSymFile->aDynSyms[0]);
1135	i++;
1136	# endif
1137
1138	# if defined(IEMNATIVE_USE_GDB_JIT_ET_DYN)
1139	/* Section header: .dynamic */
1140	pSymFile->aShdrs[i].sh_name = offStrTab;
1141	APPEND_STR(".dynamic");
1142	pSymFile->aShdrs[i].sh_type = SHT_DYNAMIC;
1143	pSymFile->aShdrs[i].sh_flags = SHF_ALLOC;
1144	pSymFile->aShdrs[i].sh_offset
1145	= pSymFile->aShdrs[i].sh_addr = RT_UOFFSETOF(GDBJITSYMFILE, aDyn);
1146	pSymFile->aShdrs[i].sh_size = sizeof(pSymFile->aDyn);
1147	pSymFile->aShdrs[i].sh_link = iShStrTab;
1148	pSymFile->aShdrs[i].sh_info = 0;
1149	pSymFile->aShdrs[i].sh_addralign = 1;
1150	pSymFile->aShdrs[i].sh_entsize = sizeof(pSymFile->aDyn[0]);
1151	i++;
1152	# endif
1153
1154	/* Section header: .text */
1155	unsigned const iShText = i;
1156	pSymFile->aShdrs[i].sh_name = offStrTab;
1157	APPEND_STR(".text");
1158	pSymFile->aShdrs[i].sh_type = SHT_PROGBITS;
1159	pSymFile->aShdrs[i].sh_flags = SHF_ALLOC \| SHF_EXECINSTR;
1160	# if defined(IEMNATIVE_USE_GDB_JIT_ET_DYN) \|\| defined(IEMNATIVE_USE_GDB_JIT_ELF_RVAS)
1161	pSymFile->aShdrs[i].sh_offset
1162	= pSymFile->aShdrs[i].sh_addr = sizeof(GDBJITSYMFILE);
1163	# else
1164	pSymFile->aShdrs[i].sh_addr = (uintptr_t)(pSymFile + 1);
1165	pSymFile->aShdrs[i].sh_offset = 0;
1166	# endif
1167	pSymFile->aShdrs[i].sh_size = pExecMemAllocator->cbChunk - offSymFileInChunk - sizeof(GDBJITSYMFILE);
1168	pSymFile->aShdrs[i].sh_link = 0;
1169	pSymFile->aShdrs[i].sh_info = 0;
1170	pSymFile->aShdrs[i].sh_addralign = 1;
1171	pSymFile->aShdrs[i].sh_entsize = 0;
1172	i++;
1173
1174	Assert(i == RT_ELEMENTS(pSymFile->aShdrs));
1175
1176	# if defined(IEMNATIVE_USE_GDB_JIT_ET_DYN)
1177	/*
1178	* The program headers:
1179	*/
1180	/* Everything in a single LOAD segment: */
1181	i = 0;
1182	pSymFile->aPhdrs[i].p_type = PT_LOAD;
1183	pSymFile->aPhdrs[i].p_flags = PF_X \| PF_R;
1184	pSymFile->aPhdrs[i].p_offset
1185	= pSymFile->aPhdrs[i].p_vaddr
1186	= pSymFile->aPhdrs[i].p_paddr = 0;
1187	pSymFile->aPhdrs[i].p_filesz /* Size of segment in file. */
1188	= pSymFile->aPhdrs[i].p_memsz = pExecMemAllocator->cbChunk - offSymFileInChunk;
1189	pSymFile->aPhdrs[i].p_align = HOST_PAGE_SIZE;
1190	i++;
1191	/* The .dynamic segment. */
1192	pSymFile->aPhdrs[i].p_type = PT_DYNAMIC;
1193	pSymFile->aPhdrs[i].p_flags = PF_R;
1194	pSymFile->aPhdrs[i].p_offset
1195	= pSymFile->aPhdrs[i].p_vaddr
1196	= pSymFile->aPhdrs[i].p_paddr = RT_UOFFSETOF(GDBJITSYMFILE, aDyn);
1197	pSymFile->aPhdrs[i].p_filesz /* Size of segment in file. */
1198	= pSymFile->aPhdrs[i].p_memsz = sizeof(pSymFile->aDyn);
1199	pSymFile->aPhdrs[i].p_align = sizeof(pSymFile->aDyn[0].d_tag);
1200	i++;
1201
1202	Assert(i == RT_ELEMENTS(pSymFile->aPhdrs));
1203
1204	/*
1205	* The dynamic section:
1206	*/
1207	i = 0;
1208	pSymFile->aDyn[i].d_tag = DT_SONAME;
1209	pSymFile->aDyn[i].d_un.d_val = offStrTab;
1210	APPEND_STR_FMT("iem-exec-chunk-%u-%u", pVCpu->idCpu, idxChunk);
1211	i++;
1212	pSymFile->aDyn[i].d_tag = DT_STRTAB;
1213	pSymFile->aDyn[i].d_un.d_ptr = RT_UOFFSETOF(GDBJITSYMFILE, szzStrTab);
1214	i++;
1215	pSymFile->aDyn[i].d_tag = DT_STRSZ;
1216	pSymFile->aDyn[i].d_un.d_val = sizeof(pSymFile->szzStrTab);
1217	i++;
1218	pSymFile->aDyn[i].d_tag = DT_SYMTAB;
1219	pSymFile->aDyn[i].d_un.d_ptr = RT_UOFFSETOF(GDBJITSYMFILE, aDynSyms);
1220	i++;
1221	pSymFile->aDyn[i].d_tag = DT_SYMENT;
1222	pSymFile->aDyn[i].d_un.d_val = sizeof(pSymFile->aDynSyms[0]);
1223	i++;
1224	pSymFile->aDyn[i].d_tag = DT_NULL;
1225	i++;
1226	Assert(i == RT_ELEMENTS(pSymFile->aDyn));
1227	# endif /* IEMNATIVE_USE_GDB_JIT_ET_DYN */
1228
1229	/*
1230	* Symbol tables:
1231	*/
1232	/** @todo gdb doesn't seem to really like this ... */
1233	i = 0;
1234	pSymFile->aSymbols[i].st_name = 0;
1235	pSymFile->aSymbols[i].st_shndx = SHN_UNDEF;
1236	pSymFile->aSymbols[i].st_value = 0;
1237	pSymFile->aSymbols[i].st_size = 0;
1238	pSymFile->aSymbols[i].st_info = ELF64_ST_INFO(STB_LOCAL, STT_NOTYPE);
1239	pSymFile->aSymbols[i].st_other = 0 /* STV_DEFAULT */;
1240	# ifdef IEMNATIVE_USE_GDB_JIT_ET_DYN
1241	pSymFile->aDynSyms[0] = pSymFile->aSymbols[i];
1242	# endif
1243	i++;
1244
1245	pSymFile->aSymbols[i].st_name = 0;
1246	pSymFile->aSymbols[i].st_shndx = SHN_ABS;
1247	pSymFile->aSymbols[i].st_value = 0;
1248	pSymFile->aSymbols[i].st_size = 0;
1249	pSymFile->aSymbols[i].st_info = ELF64_ST_INFO(STB_LOCAL, STT_FILE);
1250	pSymFile->aSymbols[i].st_other = 0 /* STV_DEFAULT */;
1251	i++;
1252
1253	pSymFile->aSymbols[i].st_name = offStrTab;
1254	APPEND_STR_FMT("iem_exec_chunk_%u_%u", pVCpu->idCpu, idxChunk);
1255	# if 0
1256	pSymFile->aSymbols[i].st_shndx = iShText;
1257	pSymFile->aSymbols[i].st_value = 0;
1258	# else
1259	pSymFile->aSymbols[i].st_shndx = SHN_ABS;
1260	pSymFile->aSymbols[i].st_value = (uintptr_t)(pSymFile + 1);
1261	# endif
1262	pSymFile->aSymbols[i].st_size = pSymFile->aShdrs[iShText].sh_size;
1263	pSymFile->aSymbols[i].st_info = ELF64_ST_INFO(STB_GLOBAL, STT_FUNC);
1264	pSymFile->aSymbols[i].st_other = 0 /* STV_DEFAULT */;
1265	# ifdef IEMNATIVE_USE_GDB_JIT_ET_DYN
1266	pSymFile->aDynSyms[1] = pSymFile->aSymbols[i];
1267	pSymFile->aDynSyms[1].st_value = (uintptr_t)(pSymFile + 1);
1268	# endif
1269	i++;
1270
1271	Assert(i == RT_ELEMENTS(pSymFile->aSymbols));
1272	Assert(offStrTab < sizeof(pSymFile->szzStrTab));
1273
1274	/*
1275	* The GDB JIT entry and informing GDB.
1276	*/
1277	pEhFrame->GdbJitEntry.pbSymFile = (uint8_t *)pSymFile;
1278	# if 1
1279	pEhFrame->GdbJitEntry.cbSymFile = pExecMemAllocator->cbChunk - ((uintptr_t)pSymFile - (uintptr_t)pvChunk);
1280	# else
1281	pEhFrame->GdbJitEntry.cbSymFile = sizeof(GDBJITSYMFILE);
1282	# endif
1283
1284	RTOnce(&g_IemNativeGdbJitOnce, iemNativeGdbJitInitOnce, NULL);
1285	RTCritSectEnter(&g_IemNativeGdbJitLock);
1286	pEhFrame->GdbJitEntry.pNext = NULL;
1287	pEhFrame->GdbJitEntry.pPrev = __jit_debug_descriptor.pTail;
1288	if (__jit_debug_descriptor.pTail)
1289	__jit_debug_descriptor.pTail->pNext = &pEhFrame->GdbJitEntry;
1290	else
1291	__jit_debug_descriptor.pHead = &pEhFrame->GdbJitEntry;
1292	__jit_debug_descriptor.pTail = &pEhFrame->GdbJitEntry;
1293	__jit_debug_descriptor.pRelevant = &pEhFrame->GdbJitEntry;
1294
1295	/* Notify GDB: */
1296	__jit_debug_descriptor.enmAction = kGdbJitaction_Register;
1297	__jit_debug_register_code();
1298	__jit_debug_descriptor.enmAction = kGdbJitaction_NoAction;
1299	RTCritSectLeave(&g_IemNativeGdbJitLock);
1300
1301	# else /* !IEMNATIVE_USE_GDB_JIT */
1302	RT_NOREF(pVCpu);
1303	# endif /* !IEMNATIVE_USE_GDB_JIT */
1304
1305	return VINF_SUCCESS;
1306	}
1307
1308	# endif /* !RT_OS_WINDOWS */
1309	#endif /* IN_RING3 */
1310
1311
1312	/**
1313	* Adds another chunk to the executable memory allocator.
1314	*
1315	* This is used by the init code for the initial allocation and later by the
1316	* regular allocator function when it's out of memory.
1317	*/
1318	static int iemExecMemAllocatorGrow(PVMCPUCC pVCpu, PIEMEXECMEMALLOCATOR pExecMemAllocator)
1319	{
1320	/* Check that we've room for growth. */
1321	uint32_t const idxChunk = pExecMemAllocator->cChunks;
1322	AssertLogRelReturn(idxChunk < pExecMemAllocator->cMaxChunks, VERR_OUT_OF_RESOURCES);
1323
1324	/* Allocate a chunk. */
1325	#ifdef RT_OS_DARWIN
1326	void *pvChunk = RTMemPageAllocEx(pExecMemAllocator->cbChunk, 0);
1327	#else
1328	void *pvChunk = RTMemPageAllocEx(pExecMemAllocator->cbChunk, RTMEMPAGEALLOC_F_EXECUTABLE);
1329	#endif
1330	AssertLogRelReturn(pvChunk, VERR_NO_EXEC_MEMORY);
1331
1332	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
1333	int rc = VINF_SUCCESS;
1334	#else
1335	/* Initialize the heap for the chunk. */
1336	RTHEAPSIMPLE hHeap = NIL_RTHEAPSIMPLE;
1337	int rc = RTHeapSimpleInit(&hHeap, pvChunk, pExecMemAllocator->cbChunk);
1338	AssertRC(rc);
1339	if (RT_SUCCESS(rc))
1340	{
1341	/*
1342	* We want the memory to be aligned on 64 byte, so the first time thru
1343	* here we do some exploratory allocations to see how we can achieve this.
1344	* On subsequent runs we only make an initial adjustment allocation, if
1345	* necessary.
1346	*
1347	* Since we own the heap implementation, we know that the internal block
1348	* header is 32 bytes in size for 64-bit systems (see RTHEAPSIMPLEBLOCK),
1349	* so all we need to wrt allocation size adjustments is to add 32 bytes
1350	* to the size, align up by 64 bytes, and subtract 32 bytes.
1351	*
1352	* The heap anchor block is 8 * sizeof(void *) (see RTHEAPSIMPLEINTERNAL),
1353	* which mean 64 bytes on a 64-bit system, so we need to make a 64 byte
1354	* allocation to force subsequent allocations to return 64 byte aligned
1355	* user areas.
1356	*/
1357	if (!pExecMemAllocator->cbHeapBlockHdr)
1358	{
1359	pExecMemAllocator->cbHeapBlockHdr = sizeof(void ) 4; /* See RTHEAPSIMPLEBLOCK. */
1360	pExecMemAllocator->cbHeapAlignTweak = 64;
1361	pExecMemAllocator->pvAlignTweak = RTHeapSimpleAlloc(hHeap, pExecMemAllocator->cbHeapAlignTweak,
1362	32 /cbAlignment/);
1363	AssertStmt(pExecMemAllocator->pvAlignTweak, rc = VERR_INTERNAL_ERROR_2);
1364
1365	void *pvTest1 = RTHeapSimpleAlloc(hHeap,
1366	RT_ALIGN_32(256 + pExecMemAllocator->cbHeapBlockHdr, 64)
1367	- pExecMemAllocator->cbHeapBlockHdr, 32 /cbAlignment/);
1368	AssertStmt(pvTest1, rc = VERR_INTERNAL_ERROR_2);
1369	AssertStmt(!((uintptr_t)pvTest1 & 63), rc = VERR_INTERNAL_ERROR_3);
1370
1371	void *pvTest2 = RTHeapSimpleAlloc(hHeap,
1372	RT_ALIGN_32(687 + pExecMemAllocator->cbHeapBlockHdr, 64)
1373	- pExecMemAllocator->cbHeapBlockHdr, 32 /cbAlignment/);
1374	AssertStmt(pvTest2, rc = VERR_INTERNAL_ERROR_2);
1375	AssertStmt(!((uintptr_t)pvTest2 & 63), rc = VERR_INTERNAL_ERROR_3);
1376
1377	RTHeapSimpleFree(hHeap, pvTest2);
1378	RTHeapSimpleFree(hHeap, pvTest1);
1379	}
1380	else
1381	{
1382	pExecMemAllocator->pvAlignTweak = RTHeapSimpleAlloc(hHeap, pExecMemAllocator->cbHeapAlignTweak, 32 /cbAlignment/);
1383	AssertStmt(pExecMemAllocator->pvAlignTweak, rc = VERR_INTERNAL_ERROR_4);
1384	}
1385	if (RT_SUCCESS(rc))
1386	#endif /* !IEMEXECMEM_USE_ALT_SUB_ALLOCATOR */
1387	{
1388	/*
1389	* Add the chunk.
1390	*
1391	* This must be done before the unwind init so windows can allocate
1392	* memory from the chunk when using the alternative sub-allocator.
1393	*/
1394	pExecMemAllocator->aChunks[idxChunk].pvChunk = pvChunk;
1395	#ifdef IN_RING3
1396	pExecMemAllocator->aChunks[idxChunk].pvUnwindInfo = NULL;
1397	#endif
1398	#ifndef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
1399	pExecMemAllocator->aChunks[idxChunk].hHeap = hHeap;
1400	#else
1401	pExecMemAllocator->aChunks[idxChunk].cFreeUnits = pExecMemAllocator->cUnitsPerChunk;
1402	pExecMemAllocator->aChunks[idxChunk].idxFreeHint = 0;
1403	memset(&pExecMemAllocator->pbmAlloc[pExecMemAllocator->cBitmapElementsPerChunk * idxChunk],
1404	0, sizeof(pExecMemAllocator->pbmAlloc[0]) * pExecMemAllocator->cBitmapElementsPerChunk);
1405	#endif
1406
1407	pExecMemAllocator->cChunks = idxChunk + 1;
1408	pExecMemAllocator->idxChunkHint = idxChunk;
1409
1410	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
1411	pExecMemAllocator->cbTotal += pExecMemAllocator->cbChunk;
1412	pExecMemAllocator->cbFree += pExecMemAllocator->cbChunk;
1413	#else
1414	size_t const cbFree = RTHeapSimpleGetFreeSize(hHeap);
1415	pExecMemAllocator->cbTotal += cbFree;
1416	pExecMemAllocator->cbFree += cbFree;
1417	#endif
1418
1419	#ifdef IN_RING3
1420	/*
1421	* Initialize the unwind information (this cannot really fail atm).
1422	* (This sets pvUnwindInfo.)
1423	*/
1424	rc = iemExecMemAllocatorInitAndRegisterUnwindInfoForChunk(pVCpu, pExecMemAllocator, pvChunk, idxChunk);
1425	if (RT_SUCCESS(rc))
1426	#endif
1427	{
1428	return VINF_SUCCESS;
1429	}
1430
1431	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
1432	/* Just in case the impossible happens, undo the above up: */
1433	pExecMemAllocator->cbTotal -= pExecMemAllocator->cbChunk;
1434	pExecMemAllocator->cbFree -= pExecMemAllocator->aChunks[idxChunk].cFreeUnits << IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SHIFT;
1435	pExecMemAllocator->cChunks = idxChunk;
1436	memset(&pExecMemAllocator->pbmAlloc[pExecMemAllocator->cBitmapElementsPerChunk * idxChunk],
1437	0xff, sizeof(pExecMemAllocator->pbmAlloc[0]) * pExecMemAllocator->cBitmapElementsPerChunk);
1438	pExecMemAllocator->aChunks[idxChunk].pvChunk = NULL;
1439	pExecMemAllocator->aChunks[idxChunk].cFreeUnits = 0;
1440	#endif
1441	}
1442	#ifndef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
1443	}
1444	#endif
1445	RTMemPageFree(pvChunk, pExecMemAllocator->cbChunk);
1446	RT_NOREF(pVCpu);
1447	return rc;
1448	}
1449
1450
1451	/**
1452	* Initializes the executable memory allocator for native recompilation on the
1453	* calling EMT.
1454	*
1455	* @returns VBox status code.
1456	* @param pVCpu The cross context virtual CPU structure of the calling
1457	* thread.
1458	* @param cbMax The max size of the allocator.
1459	* @param cbInitial The initial allocator size.
1460	* @param cbChunk The chunk size, 0 or UINT32_MAX for default (@a cbMax
1461	* dependent).
1462	*/
1463	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk)
1464	{
1465	/*
1466	* Validate input.
1467	*/
1468	AssertLogRelMsgReturn(cbMax >= _1M && cbMax <= _4G+_4G, ("cbMax=%RU64 (%RX64)\n", cbMax, cbMax), VERR_OUT_OF_RANGE);
1469	AssertReturn(cbInitial <= cbMax, VERR_OUT_OF_RANGE);
1470	AssertLogRelMsgReturn( cbChunk != UINT32_MAX
1471	\|\| cbChunk == 0
1472	\|\| ( RT_IS_POWER_OF_TWO(cbChunk)
1473	&& cbChunk >= _1M
1474	&& cbChunk <= _256M
1475	&& cbChunk <= cbMax),
1476	("cbChunk=%RU32 (%RX32) cbMax=%RU64\n", cbChunk, cbChunk, cbMax),
1477	VERR_OUT_OF_RANGE);
1478
1479	/*
1480	* Adjust/figure out the chunk size.
1481	*/
1482	if (cbChunk == 0 \|\| cbChunk == UINT32_MAX)
1483	{
1484	if (cbMax >= _256M)
1485	cbChunk = _64M;
1486	else
1487	{
1488	if (cbMax < _16M)
1489	cbChunk = cbMax >= _4M ? _4M : (uint32_t)cbMax;
1490	else
1491	cbChunk = (uint32_t)cbMax / 4;
1492	if (!RT_IS_POWER_OF_TWO(cbChunk))
1493	cbChunk = RT_BIT_32(ASMBitLastSetU32(cbChunk));
1494	}
1495	}
1496
1497	if (cbChunk > cbMax)
1498	cbMax = cbChunk;
1499	else
1500	cbMax = (cbMax - 1 + cbChunk) / cbChunk * cbChunk;
1501	uint32_t const cMaxChunks = (uint32_t)(cbMax / cbChunk);
1502	AssertLogRelReturn((uint64_t)cMaxChunks * cbChunk == cbMax, VERR_INTERNAL_ERROR_3);
1503
1504	/*
1505	* Allocate and initialize the allocatore instance.
1506	*/
1507	size_t cbNeeded = RT_UOFFSETOF_DYN(IEMEXECMEMALLOCATOR, aChunks[cMaxChunks]);
1508	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
1509	size_t const offBitmaps = RT_ALIGN_Z(cbNeeded, RT_CACHELINE_SIZE);
1510	size_t const cbBitmap = cbChunk >> (IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SHIFT + 3);
1511	cbNeeded += cbBitmap * cMaxChunks;
1512	AssertCompile(IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SHIFT <= 10);
1513	Assert(cbChunk > RT_BIT_32(IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SHIFT + 3));
1514	#endif
1515	#if defined(IN_RING3) && !defined(RT_OS_WINDOWS)
1516	size_t const offEhFrames = RT_ALIGN_Z(cbNeeded, RT_CACHELINE_SIZE);
1517	cbNeeded += sizeof(IEMEXECMEMCHUNKEHFRAME) * cMaxChunks;
1518	#endif
1519	PIEMEXECMEMALLOCATOR pExecMemAllocator = (PIEMEXECMEMALLOCATOR)RTMemAllocZ(cbNeeded);
1520	AssertLogRelMsgReturn(pExecMemAllocator, ("cbNeeded=%zx cMaxChunks=%#x cbChunk=%#x\n", cbNeeded, cMaxChunks, cbChunk),
1521	VERR_NO_MEMORY);
1522	pExecMemAllocator->uMagic = IEMEXECMEMALLOCATOR_MAGIC;
1523	pExecMemAllocator->cbChunk = cbChunk;
1524	pExecMemAllocator->cMaxChunks = cMaxChunks;
1525	pExecMemAllocator->cChunks = 0;
1526	pExecMemAllocator->idxChunkHint = 0;
1527	pExecMemAllocator->cAllocations = 0;
1528	pExecMemAllocator->cbTotal = 0;
1529	pExecMemAllocator->cbFree = 0;
1530	pExecMemAllocator->cbAllocated = 0;
1531	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
1532	pExecMemAllocator->pbmAlloc = (uint64_t *)((uintptr_t)pExecMemAllocator + offBitmaps);
1533	pExecMemAllocator->cUnitsPerChunk = cbChunk >> IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SHIFT;
1534	pExecMemAllocator->cBitmapElementsPerChunk = cbChunk >> (IEMEXECMEM_ALT_SUB_ALLOC_UNIT_SHIFT + 6);
1535	memset(pExecMemAllocator->pbmAlloc, 0xff, cbBitmap); /* Mark everything as allocated. Clear when chunks are added. */
1536	#endif
1537	#if defined(IN_RING3) && !defined(RT_OS_WINDOWS)
1538	pExecMemAllocator->paEhFrames = (PIEMEXECMEMCHUNKEHFRAME)((uintptr_t)pExecMemAllocator + offEhFrames);
1539	#endif
1540	for (uint32_t i = 0; i < cMaxChunks; i++)
1541	{
1542	#ifdef IEMEXECMEM_USE_ALT_SUB_ALLOCATOR
1543	pExecMemAllocator->aChunks[i].cFreeUnits = 0;
1544	pExecMemAllocator->aChunks[i].idxFreeHint = 0;
1545	#else
1546	pExecMemAllocator->aChunks[i].hHeap = NIL_RTHEAPSIMPLE;
1547	#endif
1548	pExecMemAllocator->aChunks[i].pvChunk = NULL;
1549	#ifdef IN_RING0
1550	pExecMemAllocator->aChunks[i].hMemObj = NIL_RTR0MEMOBJ;
1551	#else
1552	pExecMemAllocator->aChunks[i].pvUnwindInfo = NULL;
1553	#endif
1554	}
1555	pVCpu->iem.s.pExecMemAllocatorR3 = pExecMemAllocator;
1556
1557	/*
1558	* Do the initial allocations.
1559	*/
1560	while (cbInitial < (uint64_t)pExecMemAllocator->cChunks * pExecMemAllocator->cbChunk)
1561	{
1562	int rc = iemExecMemAllocatorGrow(pVCpu, pExecMemAllocator);
1563	AssertLogRelRCReturn(rc, rc);
1564	}
1565
1566	pExecMemAllocator->idxChunkHint = 0;
1567
1568	return VINF_SUCCESS;
1569	}
1570
1571
1572	/*********************************************************************************************************************************
1573	* Native Recompilation *
1574	*********************************************************************************************************************************/
1575
1576
1577	/**
1578	* Used by TB code when encountering a non-zero status or rcPassUp after a call.
1579	*/
1580	IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecStatusCodeFiddling,(PVMCPUCC pVCpu, int rc, uint8_t idxInstr))
1581	{
1582	pVCpu->iem.s.cInstructions += idxInstr;
1583	return VBOXSTRICTRC_VAL(iemExecStatusCodeFiddling(pVCpu, rc == VINF_IEM_REEXEC_BREAK ? VINF_SUCCESS : rc));
1584	}
1585
1586
1587	/**
1588	* Used by TB code when it wants to raise a \#GP(0).
1589	*/
1590	IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecRaiseGp0,(PVMCPUCC pVCpu))
1591	{
1592	iemRaiseGeneralProtectionFault0Jmp(pVCpu);
1593	#ifndef _MSC_VER
1594	return VINF_IEM_RAISED_XCPT; /* not reached */
1595	#endif
1596	}
1597
1598
1599	/**
1600	* Used by TB code when detecting opcode changes.
1601	* @see iemThreadeFuncWorkerObsoleteTb
1602	*/
1603	IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpObsoleteTb,(PVMCPUCC pVCpu))
1604	{
1605	/* We set fSafeToFree to false where as we're being called in the context
1606	of a TB callback function, which for native TBs means we cannot release
1607	the executable memory till we've returned our way back to iemTbExec as
1608	that return path codes via the native code generated for the TB. */
1609	Log7(("TB obsolete: %p at %04x:%08RX64\n", pVCpu->iem.s.pCurTbR3, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
1610	iemThreadedTbObsolete(pVCpu, pVCpu->iem.s.pCurTbR3, false /fSafeToFree/);
1611	return VINF_IEM_REEXEC_BREAK;
1612	}
1613
1614
1615	/**
1616	* Used by TB code when we need to switch to a TB with CS.LIM checking.
1617	*/
1618	IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpNeedCsLimChecking,(PVMCPUCC pVCpu))
1619	{
1620	Log7(("TB need CS.LIM: %p at %04x:%08RX64; offFromLim=%#RX64 CS.LIM=%#RX32 CS.BASE=%#RX64\n",
1621	pVCpu->iem.s.pCurTbR3, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
1622	(int64_t)pVCpu->cpum.GstCtx.cs.u32Limit - (int64_t)pVCpu->cpum.GstCtx.rip,
1623	pVCpu->cpum.GstCtx.cs.u32Limit, pVCpu->cpum.GstCtx.cs.u64Base));
1624	STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatCheckNeedCsLimChecking);
1625	return VINF_IEM_REEXEC_BREAK;
1626	}
1627
1628
1629	/**
1630	* Used by TB code when we missed a PC check after a branch.
1631	*/
1632	IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpCheckBranchMiss,(PVMCPUCC pVCpu))
1633	{
1634	Log7(("TB jmp miss: %p at %04x:%08RX64; GCPhysWithOffset=%RGp, pbInstrBuf=%p\n",
1635	pVCpu->iem.s.pCurTbR3, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
1636	pVCpu->iem.s.GCPhysInstrBuf + pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base - pVCpu->iem.s.uInstrBufPc,
1637	pVCpu->iem.s.pbInstrBuf));
1638	STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatCheckBranchMisses);
1639	return VINF_IEM_REEXEC_BREAK;
1640	}
1641
1642
1643
1644	/*********************************************************************************************************************************
1645	* Helpers: Segmented memory fetches and stores. *
1646	*********************************************************************************************************************************/
1647
1648	/**
1649	* Used by TB code to load unsigned 8-bit data w/ segmentation.
1650	*/
1651	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
1652	{
1653	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1654	return (uint64_t)iemMemFetchDataU8SafeJmp(pVCpu, iSegReg, GCPtrMem);
1655	#else
1656	return (uint64_t)iemMemFetchDataU8Jmp(pVCpu, iSegReg, GCPtrMem);
1657	#endif
1658	}
1659
1660
1661	/**
1662	* Used by TB code to load signed 8-bit data w/ segmentation, sign extending it
1663	* to 16 bits.
1664	*/
1665	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU8_Sx_U16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
1666	{
1667	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1668	return (uint64_t)(uint16_t)(int16_t)(int8_t)iemMemFetchDataU8SafeJmp(pVCpu, iSegReg, GCPtrMem);
1669	#else
1670	return (uint64_t)(uint16_t)(int16_t)(int8_t)iemMemFetchDataU8Jmp(pVCpu, iSegReg, GCPtrMem);
1671	#endif
1672	}
1673
1674
1675	/**
1676	* Used by TB code to load signed 8-bit data w/ segmentation, sign extending it
1677	* to 32 bits.
1678	*/
1679	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU8_Sx_U32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
1680	{
1681	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1682	return (uint64_t)(uint32_t)(int32_t)(int8_t)iemMemFetchDataU8SafeJmp(pVCpu, iSegReg, GCPtrMem);
1683	#else
1684	return (uint64_t)(uint32_t)(int32_t)(int8_t)iemMemFetchDataU8Jmp(pVCpu, iSegReg, GCPtrMem);
1685	#endif
1686	}
1687
1688	/**
1689	* Used by TB code to load signed 8-bit data w/ segmentation, sign extending it
1690	* to 64 bits.
1691	*/
1692	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU8_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
1693	{
1694	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1695	return (uint64_t)(int64_t)(int8_t)iemMemFetchDataU8SafeJmp(pVCpu, iSegReg, GCPtrMem);
1696	#else
1697	return (uint64_t)(int64_t)(int8_t)iemMemFetchDataU8Jmp(pVCpu, iSegReg, GCPtrMem);
1698	#endif
1699	}
1700
1701
1702	/**
1703	* Used by TB code to load unsigned 16-bit data w/ segmentation.
1704	*/
1705	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
1706	{
1707	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1708	return (uint64_t)iemMemFetchDataU16SafeJmp(pVCpu, iSegReg, GCPtrMem);
1709	#else
1710	return (uint64_t)iemMemFetchDataU16Jmp(pVCpu, iSegReg, GCPtrMem);
1711	#endif
1712	}
1713
1714
1715	/**
1716	* Used by TB code to load signed 16-bit data w/ segmentation, sign extending it
1717	* to 32 bits.
1718	*/
1719	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU16_Sx_U32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
1720	{
1721	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1722	return (uint64_t)(uint32_t)(int32_t)(int16_t)iemMemFetchDataU16SafeJmp(pVCpu, iSegReg, GCPtrMem);
1723	#else
1724	return (uint64_t)(uint32_t)(int32_t)(int16_t)iemMemFetchDataU16Jmp(pVCpu, iSegReg, GCPtrMem);
1725	#endif
1726	}
1727
1728
1729	/**
1730	* Used by TB code to load signed 16-bit data w/ segmentation, sign extending it
1731	* to 64 bits.
1732	*/
1733	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU16_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
1734	{
1735	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1736	return (uint64_t)(int64_t)(int16_t)iemMemFetchDataU16SafeJmp(pVCpu, iSegReg, GCPtrMem);
1737	#else
1738	return (uint64_t)(int64_t)(int16_t)iemMemFetchDataU16Jmp(pVCpu, iSegReg, GCPtrMem);
1739	#endif
1740	}
1741
1742
1743	/**
1744	* Used by TB code to load unsigned 32-bit data w/ segmentation.
1745	*/
1746	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
1747	{
1748	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1749	return (uint64_t)iemMemFetchDataU32SafeJmp(pVCpu, iSegReg, GCPtrMem);
1750	#else
1751	return (uint64_t)iemMemFetchDataU32Jmp(pVCpu, iSegReg, GCPtrMem);
1752	#endif
1753	}
1754
1755
1756	/**
1757	* Used by TB code to load signed 32-bit data w/ segmentation, sign extending it
1758	* to 64 bits.
1759	*/
1760	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU32_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
1761	{
1762	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1763	return (uint64_t)(int64_t)(int32_t)iemMemFetchDataU32SafeJmp(pVCpu, iSegReg, GCPtrMem);
1764	#else
1765	return (uint64_t)(int64_t)(int32_t)iemMemFetchDataU32Jmp(pVCpu, iSegReg, GCPtrMem);
1766	#endif
1767	}
1768
1769
1770	/**
1771	* Used by TB code to load unsigned 64-bit data w/ segmentation.
1772	*/
1773	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFetchDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg))
1774	{
1775	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1776	return iemMemFetchDataU64SafeJmp(pVCpu, iSegReg, GCPtrMem);
1777	#else
1778	return iemMemFetchDataU64Jmp(pVCpu, iSegReg, GCPtrMem);
1779	#endif
1780	}
1781
1782
1783	/**
1784	* Used by TB code to store unsigned 8-bit data w/ segmentation.
1785	*/
1786	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint8_t u8Value))
1787	{
1788	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
1789	iemMemStoreDataU8SafeJmp(pVCpu, iSegReg, GCPtrMem, u8Value);
1790	#else
1791	iemMemStoreDataU8Jmp(pVCpu, iSegReg, GCPtrMem, u8Value);
1792	#endif
1793	}
1794
1795
1796	/**
1797	* Used by TB code to store unsigned 16-bit data w/ segmentation.
1798	*/
1799	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint16_t u16Value))
1800	{
1801	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
1802	iemMemStoreDataU16SafeJmp(pVCpu, iSegReg, GCPtrMem, u16Value);
1803	#else
1804	iemMemStoreDataU16Jmp(pVCpu, iSegReg, GCPtrMem, u16Value);
1805	#endif
1806	}
1807
1808
1809	/**
1810	* Used by TB code to store unsigned 32-bit data w/ segmentation.
1811	*/
1812	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint32_t u32Value))
1813	{
1814	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
1815	iemMemStoreDataU32SafeJmp(pVCpu, iSegReg, GCPtrMem, u32Value);
1816	#else
1817	iemMemStoreDataU32Jmp(pVCpu, iSegReg, GCPtrMem, u32Value);
1818	#endif
1819	}
1820
1821
1822	/**
1823	* Used by TB code to store unsigned 64-bit data w/ segmentation.
1824	*/
1825	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint64_t u64Value))
1826	{
1827	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
1828	iemMemStoreDataU64SafeJmp(pVCpu, iSegReg, GCPtrMem, u64Value);
1829	#else
1830	iemMemStoreDataU64Jmp(pVCpu, iSegReg, GCPtrMem, u64Value);
1831	#endif
1832	}
1833
1834
1835
1836	/**
1837	* Used by TB code to store an unsigned 16-bit value onto a generic stack.
1838	*/
1839	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackStoreU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value))
1840	{
1841	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
1842	iemMemStoreStackU16SafeJmp(pVCpu, GCPtrMem, u16Value);
1843	#else
1844	iemMemStoreStackU16Jmp(pVCpu, GCPtrMem, u16Value);
1845	#endif
1846	}
1847
1848
1849	/**
1850	* Used by TB code to store an unsigned 32-bit value onto a generic stack.
1851	*/
1852	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackStoreU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value))
1853	{
1854	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
1855	iemMemStoreStackU32SafeJmp(pVCpu, GCPtrMem, u32Value);
1856	#else
1857	iemMemStoreStackU32Jmp(pVCpu, GCPtrMem, u32Value);
1858	#endif
1859	}
1860
1861
1862	/**
1863	* Used by TB code to store an 32-bit selector value onto a generic stack.
1864	*
1865	* Intel CPUs doesn't do write a whole dword, thus the special function.
1866	*/
1867	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackStoreU32SReg,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value))
1868	{
1869	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
1870	iemMemStoreStackU32SRegSafeJmp(pVCpu, GCPtrMem, u32Value);
1871	#else
1872	iemMemStoreStackU32SRegJmp(pVCpu, GCPtrMem, u32Value);
1873	#endif
1874	}
1875
1876
1877	/**
1878	* Used by TB code to push unsigned 64-bit value onto a generic stack.
1879	*/
1880	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackStoreU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t u64Value))
1881	{
1882	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
1883	iemMemStoreStackU64SafeJmp(pVCpu, GCPtrMem, u64Value);
1884	#else
1885	iemMemStoreStackU64Jmp(pVCpu, GCPtrMem, u64Value);
1886	#endif
1887	}
1888
1889
1890	/**
1891	* Used by TB code to fetch an unsigned 16-bit item off a generic stack.
1892	*/
1893	IEM_DECL_NATIVE_HLP_DEF(uint16_t, iemNativeHlpStackFetchU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1894	{
1895	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_POP
1896	return iemMemFetchStackU16SafeJmp(pVCpu, GCPtrMem);
1897	#else
1898	return iemMemFetchStackU16Jmp(pVCpu, GCPtrMem);
1899	#endif
1900	}
1901
1902
1903	/**
1904	* Used by TB code to fetch an unsigned 32-bit item off a generic stack.
1905	*/
1906	IEM_DECL_NATIVE_HLP_DEF(uint32_t, iemNativeHlpStackFetchU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1907	{
1908	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_POP
1909	return iemMemFetchStackU32SafeJmp(pVCpu, GCPtrMem);
1910	#else
1911	return iemMemFetchStackU32Jmp(pVCpu, GCPtrMem);
1912	#endif
1913	}
1914
1915
1916	/**
1917	* Used by TB code to fetch an unsigned 64-bit item off a generic stack.
1918	*/
1919	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpStackFetchU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1920	{
1921	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_POP
1922	return iemMemFetchStackU64SafeJmp(pVCpu, GCPtrMem);
1923	#else
1924	return iemMemFetchStackU64Jmp(pVCpu, GCPtrMem);
1925	#endif
1926	}
1927
1928
1929
1930	/*********************************************************************************************************************************
1931	* Helpers: Flat memory fetches and stores. *
1932	*********************************************************************************************************************************/
1933
1934	/**
1935	* Used by TB code to load unsigned 8-bit data w/ flat address.
1936	* @note Zero extending the value to 64-bit to simplify assembly.
1937	*/
1938	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1939	{
1940	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1941	return (uint64_t)iemMemFetchDataU8SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
1942	#else
1943	return (uint64_t)iemMemFlatFetchDataU8Jmp(pVCpu, GCPtrMem);
1944	#endif
1945	}
1946
1947
1948	/**
1949	* Used by TB code to load signed 8-bit data w/ flat address, sign extending it
1950	* to 16 bits.
1951	* @note Zero extending the value to 64-bit to simplify assembly.
1952	*/
1953	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU8_Sx_U16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1954	{
1955	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1956	return (uint64_t)(uint16_t)(int16_t)(int8_t)iemMemFetchDataU8SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
1957	#else
1958	return (uint64_t)(uint16_t)(int16_t)(int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, GCPtrMem);
1959	#endif
1960	}
1961
1962
1963	/**
1964	* Used by TB code to load signed 8-bit data w/ flat address, sign extending it
1965	* to 32 bits.
1966	* @note Zero extending the value to 64-bit to simplify assembly.
1967	*/
1968	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU8_Sx_U32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1969	{
1970	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1971	return (uint64_t)(uint32_t)(int32_t)(int8_t)iemMemFetchDataU8SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
1972	#else
1973	return (uint64_t)(uint32_t)(int32_t)(int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, GCPtrMem);
1974	#endif
1975	}
1976
1977
1978	/**
1979	* Used by TB code to load signed 8-bit data w/ flat address, sign extending it
1980	* to 64 bits.
1981	*/
1982	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU8_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1983	{
1984	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1985	return (uint64_t)(int64_t)(int8_t)iemMemFetchDataU8SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
1986	#else
1987	return (uint64_t)(int64_t)(int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, GCPtrMem);
1988	#endif
1989	}
1990
1991
1992	/**
1993	* Used by TB code to load unsigned 16-bit data w/ flat address.
1994	* @note Zero extending the value to 64-bit to simplify assembly.
1995	*/
1996	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
1997	{
1998	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
1999	return (uint64_t)iemMemFetchDataU16SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
2000	#else
2001	return (uint64_t)iemMemFlatFetchDataU16Jmp(pVCpu, GCPtrMem);
2002	#endif
2003	}
2004
2005
2006	/**
2007	* Used by TB code to load signed 16-bit data w/ flat address, sign extending it
2008	* to 32 bits.
2009	* @note Zero extending the value to 64-bit to simplify assembly.
2010	*/
2011	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU16_Sx_U32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
2012	{
2013	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
2014	return (uint64_t)(uint32_t)(int32_t)(int16_t)iemMemFetchDataU16SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
2015	#else
2016	return (uint64_t)(uint32_t)(int32_t)(int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, GCPtrMem);
2017	#endif
2018	}
2019
2020
2021	/**
2022	* Used by TB code to load signed 16-bit data w/ flat address, sign extending it
2023	* to 64 bits.
2024	* @note Zero extending the value to 64-bit to simplify assembly.
2025	*/
2026	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU16_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
2027	{
2028	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
2029	return (uint64_t)(int64_t)(int16_t)iemMemFetchDataU16SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
2030	#else
2031	return (uint64_t)(int64_t)(int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, GCPtrMem);
2032	#endif
2033	}
2034
2035
2036	/**
2037	* Used by TB code to load unsigned 32-bit data w/ flat address.
2038	* @note Zero extending the value to 64-bit to simplify assembly.
2039	*/
2040	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
2041	{
2042	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
2043	return (uint64_t)iemMemFetchDataU32SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
2044	#else
2045	return (uint64_t)iemMemFlatFetchDataU32Jmp(pVCpu, GCPtrMem);
2046	#endif
2047	}
2048
2049
2050	/**
2051	* Used by TB code to load signed 32-bit data w/ flat address, sign extending it
2052	* to 64 bits.
2053	* @note Zero extending the value to 64-bit to simplify assembly.
2054	*/
2055	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU32_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
2056	{
2057	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
2058	return (uint64_t)(int64_t)(int32_t)iemMemFetchDataU32SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
2059	#else
2060	return (uint64_t)(int64_t)(int32_t)iemMemFlatFetchDataU32Jmp(pVCpu, GCPtrMem);
2061	#endif
2062	}
2063
2064
2065	/**
2066	* Used by TB code to load unsigned 64-bit data w/ flat address.
2067	*/
2068	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpMemFlatFetchDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
2069	{
2070	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_FETCH
2071	return iemMemFetchDataU64SafeJmp(pVCpu, UINT8_MAX, GCPtrMem);
2072	#else
2073	return iemMemFlatFetchDataU64Jmp(pVCpu, GCPtrMem);
2074	#endif
2075	}
2076
2077
2078	/**
2079	* Used by TB code to store unsigned 8-bit data w/ flat address.
2080	*/
2081	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t u8Value))
2082	{
2083	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
2084	iemMemStoreDataU8SafeJmp(pVCpu, UINT8_MAX, GCPtrMem, u8Value);
2085	#else
2086	iemMemFlatStoreDataU8Jmp(pVCpu, GCPtrMem, u8Value);
2087	#endif
2088	}
2089
2090
2091	/**
2092	* Used by TB code to store unsigned 16-bit data w/ flat address.
2093	*/
2094	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value))
2095	{
2096	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
2097	iemMemStoreDataU16SafeJmp(pVCpu, UINT8_MAX, GCPtrMem, u16Value);
2098	#else
2099	iemMemFlatStoreDataU16Jmp(pVCpu, GCPtrMem, u16Value);
2100	#endif
2101	}
2102
2103
2104	/**
2105	* Used by TB code to store unsigned 32-bit data w/ flat address.
2106	*/
2107	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value))
2108	{
2109	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
2110	iemMemStoreDataU32SafeJmp(pVCpu, UINT8_MAX, GCPtrMem, u32Value);
2111	#else
2112	iemMemFlatStoreDataU32Jmp(pVCpu, GCPtrMem, u32Value);
2113	#endif
2114	}
2115
2116
2117	/**
2118	* Used by TB code to store unsigned 64-bit data w/ flat address.
2119	*/
2120	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t u64Value))
2121	{
2122	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
2123	iemMemStoreDataU64SafeJmp(pVCpu, UINT8_MAX, GCPtrMem, u64Value);
2124	#else
2125	iemMemFlatStoreDataU64Jmp(pVCpu, GCPtrMem, u64Value);
2126	#endif
2127	}
2128
2129
2130
2131	/**
2132	* Used by TB code to store an unsigned 16-bit value onto a flat stack.
2133	*/
2134	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackFlatStoreU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value))
2135	{
2136	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
2137	iemMemStoreStackU16SafeJmp(pVCpu, GCPtrMem, u16Value);
2138	#else
2139	iemMemFlatStoreStackU16Jmp(pVCpu, GCPtrMem, u16Value);
2140	#endif
2141	}
2142
2143
2144	/**
2145	* Used by TB code to store an unsigned 32-bit value onto a flat stack.
2146	*/
2147	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackFlatStoreU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value))
2148	{
2149	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
2150	iemMemStoreStackU32SafeJmp(pVCpu, GCPtrMem, u32Value);
2151	#else
2152	iemMemFlatStoreStackU32Jmp(pVCpu, GCPtrMem, u32Value);
2153	#endif
2154	}
2155
2156
2157	/**
2158	* Used by TB code to store a segment selector value onto a flat stack.
2159	*
2160	* Intel CPUs doesn't do write a whole dword, thus the special function.
2161	*/
2162	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackFlatStoreU32SReg,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value))
2163	{
2164	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
2165	iemMemStoreStackU32SRegSafeJmp(pVCpu, GCPtrMem, u32Value);
2166	#else
2167	iemMemFlatStoreStackU32SRegJmp(pVCpu, GCPtrMem, u32Value);
2168	#endif
2169	}
2170
2171
2172	/**
2173	* Used by TB code to store an unsigned 64-bit value onto a flat stack.
2174	*/
2175	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpStackFlatStoreU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t u64Value))
2176	{
2177	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_PUSH
2178	iemMemStoreStackU64SafeJmp(pVCpu, GCPtrMem, u64Value);
2179	#else
2180	iemMemFlatStoreStackU64Jmp(pVCpu, GCPtrMem, u64Value);
2181	#endif
2182	}
2183
2184
2185	/**
2186	* Used by TB code to fetch an unsigned 16-bit item off a generic stack.
2187	*/
2188	IEM_DECL_NATIVE_HLP_DEF(uint16_t, iemNativeHlpStackFlatFetchU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
2189	{
2190	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_POP
2191	return iemMemFetchStackU16SafeJmp(pVCpu, GCPtrMem);
2192	#else
2193	return iemMemFlatFetchStackU16Jmp(pVCpu, GCPtrMem);
2194	#endif
2195	}
2196
2197
2198	/**
2199	* Used by TB code to fetch an unsigned 32-bit item off a generic stack.
2200	*/
2201	IEM_DECL_NATIVE_HLP_DEF(uint32_t, iemNativeHlpStackFlatFetchU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
2202	{
2203	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_POP
2204	return iemMemFetchStackU32SafeJmp(pVCpu, GCPtrMem);
2205	#else
2206	return iemMemFlatFetchStackU32Jmp(pVCpu, GCPtrMem);
2207	#endif
2208	}
2209
2210
2211	/**
2212	* Used by TB code to fetch an unsigned 64-bit item off a generic stack.
2213	*/
2214	IEM_DECL_NATIVE_HLP_DEF(uint64_t, iemNativeHlpStackFlatFetchU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem))
2215	{
2216	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_POP
2217	return iemMemFetchStackU64SafeJmp(pVCpu, GCPtrMem);
2218	#else
2219	return iemMemFlatFetchStackU64Jmp(pVCpu, GCPtrMem);
2220	#endif
2221	}
2222
2223
2224
2225	/*********************************************************************************************************************************
2226	* Helpers: Segmented memory mapping. *
2227	*********************************************************************************************************************************/
2228
2229	/**
2230	* Used by TB code to map unsigned 8-bit data for atomic read-write w/
2231	* segmentation.
2232	*/
2233	IEM_DECL_NATIVE_HLP_DEF(uint8_t , iemNativeHlpMemMapDataU8Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2234	RTGCPTR GCPtrMem, uint8_t iSegReg))
2235	{
2236	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2237	return iemMemMapDataU8AtSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2238	#else
2239	return iemMemMapDataU8AtJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2240	#endif
2241	}
2242
2243
2244	/**
2245	* Used by TB code to map unsigned 8-bit data read-write w/ segmentation.
2246	*/
2247	IEM_DECL_NATIVE_HLP_DEF(uint8_t , iemNativeHlpMemMapDataU8Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2248	RTGCPTR GCPtrMem, uint8_t iSegReg))
2249	{
2250	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2251	return iemMemMapDataU8RwSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2252	#else
2253	return iemMemMapDataU8RwJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2254	#endif
2255	}
2256
2257
2258	/**
2259	* Used by TB code to map unsigned 8-bit data writeonly w/ segmentation.
2260	*/
2261	IEM_DECL_NATIVE_HLP_DEF(uint8_t , iemNativeHlpMemMapDataU8Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2262	RTGCPTR GCPtrMem, uint8_t iSegReg))
2263	{
2264	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2265	return iemMemMapDataU8WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2266	#else
2267	return iemMemMapDataU8WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2268	#endif
2269	}
2270
2271
2272	/**
2273	* Used by TB code to map unsigned 8-bit data readonly w/ segmentation.
2274	*/
2275	IEM_DECL_NATIVE_HLP_DEF(uint8_t const , iemNativeHlpMemMapDataU8Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2276	RTGCPTR GCPtrMem, uint8_t iSegReg))
2277	{
2278	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2279	return iemMemMapDataU8RoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2280	#else
2281	return iemMemMapDataU8RoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2282	#endif
2283	}
2284
2285
2286	/**
2287	* Used by TB code to map unsigned 16-bit data for atomic read-write w/
2288	* segmentation.
2289	*/
2290	IEM_DECL_NATIVE_HLP_DEF(uint16_t , iemNativeHlpMemMapDataU16Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2291	RTGCPTR GCPtrMem, uint8_t iSegReg))
2292	{
2293	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2294	return iemMemMapDataU16AtSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2295	#else
2296	return iemMemMapDataU16AtJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2297	#endif
2298	}
2299
2300
2301	/**
2302	* Used by TB code to map unsigned 16-bit data read-write w/ segmentation.
2303	*/
2304	IEM_DECL_NATIVE_HLP_DEF(uint16_t , iemNativeHlpMemMapDataU16Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2305	RTGCPTR GCPtrMem, uint8_t iSegReg))
2306	{
2307	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2308	return iemMemMapDataU16RwSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2309	#else
2310	return iemMemMapDataU16RwJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2311	#endif
2312	}
2313
2314
2315	/**
2316	* Used by TB code to map unsigned 16-bit data writeonly w/ segmentation.
2317	*/
2318	IEM_DECL_NATIVE_HLP_DEF(uint16_t , iemNativeHlpMemMapDataU16Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2319	RTGCPTR GCPtrMem, uint8_t iSegReg))
2320	{
2321	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2322	return iemMemMapDataU16WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2323	#else
2324	return iemMemMapDataU16WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2325	#endif
2326	}
2327
2328
2329	/**
2330	* Used by TB code to map unsigned 16-bit data readonly w/ segmentation.
2331	*/
2332	IEM_DECL_NATIVE_HLP_DEF(uint16_t const , iemNativeHlpMemMapDataU16Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2333	RTGCPTR GCPtrMem, uint8_t iSegReg))
2334	{
2335	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2336	return iemMemMapDataU16RoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2337	#else
2338	return iemMemMapDataU16RoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2339	#endif
2340	}
2341
2342
2343	/**
2344	* Used by TB code to map unsigned 32-bit data for atomic read-write w/
2345	* segmentation.
2346	*/
2347	IEM_DECL_NATIVE_HLP_DEF(uint32_t , iemNativeHlpMemMapDataU32Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2348	RTGCPTR GCPtrMem, uint8_t iSegReg))
2349	{
2350	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2351	return iemMemMapDataU32AtSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2352	#else
2353	return iemMemMapDataU32AtJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2354	#endif
2355	}
2356
2357
2358	/**
2359	* Used by TB code to map unsigned 32-bit data read-write w/ segmentation.
2360	*/
2361	IEM_DECL_NATIVE_HLP_DEF(uint32_t , iemNativeHlpMemMapDataU32Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2362	RTGCPTR GCPtrMem, uint8_t iSegReg))
2363	{
2364	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2365	return iemMemMapDataU32RwSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2366	#else
2367	return iemMemMapDataU32RwJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2368	#endif
2369	}
2370
2371
2372	/**
2373	* Used by TB code to map unsigned 32-bit data writeonly w/ segmentation.
2374	*/
2375	IEM_DECL_NATIVE_HLP_DEF(uint32_t , iemNativeHlpMemMapDataU32Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2376	RTGCPTR GCPtrMem, uint8_t iSegReg))
2377	{
2378	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2379	return iemMemMapDataU32WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2380	#else
2381	return iemMemMapDataU32WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2382	#endif
2383	}
2384
2385
2386	/**
2387	* Used by TB code to map unsigned 32-bit data readonly w/ segmentation.
2388	*/
2389	IEM_DECL_NATIVE_HLP_DEF(uint32_t const , iemNativeHlpMemMapDataU32Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2390	RTGCPTR GCPtrMem, uint8_t iSegReg))
2391	{
2392	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2393	return iemMemMapDataU32RoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2394	#else
2395	return iemMemMapDataU32RoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2396	#endif
2397	}
2398
2399
2400	/**
2401	* Used by TB code to map unsigned 64-bit data for atomic read-write w/
2402	* segmentation.
2403	*/
2404	IEM_DECL_NATIVE_HLP_DEF(uint64_t , iemNativeHlpMemMapDataU64Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2405	RTGCPTR GCPtrMem, uint8_t iSegReg))
2406	{
2407	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2408	return iemMemMapDataU64AtSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2409	#else
2410	return iemMemMapDataU64AtJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2411	#endif
2412	}
2413
2414
2415	/**
2416	* Used by TB code to map unsigned 64-bit data read-write w/ segmentation.
2417	*/
2418	IEM_DECL_NATIVE_HLP_DEF(uint64_t , iemNativeHlpMemMapDataU64Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2419	RTGCPTR GCPtrMem, uint8_t iSegReg))
2420	{
2421	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2422	return iemMemMapDataU64RwSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2423	#else
2424	return iemMemMapDataU64RwJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2425	#endif
2426	}
2427
2428
2429	/**
2430	* Used by TB code to map unsigned 64-bit data writeonly w/ segmentation.
2431	*/
2432	IEM_DECL_NATIVE_HLP_DEF(uint64_t , iemNativeHlpMemMapDataU64Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2433	RTGCPTR GCPtrMem, uint8_t iSegReg))
2434	{
2435	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2436	return iemMemMapDataU64WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2437	#else
2438	return iemMemMapDataU64WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2439	#endif
2440	}
2441
2442
2443	/**
2444	* Used by TB code to map unsigned 64-bit data readonly w/ segmentation.
2445	*/
2446	IEM_DECL_NATIVE_HLP_DEF(uint64_t const , iemNativeHlpMemMapDataU64Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2447	RTGCPTR GCPtrMem, uint8_t iSegReg))
2448	{
2449	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2450	return iemMemMapDataU64RoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2451	#else
2452	return iemMemMapDataU64RoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2453	#endif
2454	}
2455
2456
2457	/**
2458	* Used by TB code to map 80-bit float data writeonly w/ segmentation.
2459	*/
2460	IEM_DECL_NATIVE_HLP_DEF(RTFLOAT80U , iemNativeHlpMemMapDataR80Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2461	RTGCPTR GCPtrMem, uint8_t iSegReg))
2462	{
2463	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2464	return iemMemMapDataR80WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2465	#else
2466	return iemMemMapDataR80WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2467	#endif
2468	}
2469
2470
2471	/**
2472	* Used by TB code to map 80-bit BCD data writeonly w/ segmentation.
2473	*/
2474	IEM_DECL_NATIVE_HLP_DEF(RTPBCD80U , iemNativeHlpMemMapDataD80Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2475	RTGCPTR GCPtrMem, uint8_t iSegReg))
2476	{
2477	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2478	return iemMemMapDataD80WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2479	#else
2480	return iemMemMapDataD80WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2481	#endif
2482	}
2483
2484
2485	/**
2486	* Used by TB code to map unsigned 128-bit data for atomic read-write w/
2487	* segmentation.
2488	*/
2489	IEM_DECL_NATIVE_HLP_DEF(RTUINT128U , iemNativeHlpMemMapDataU128Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2490	RTGCPTR GCPtrMem, uint8_t iSegReg))
2491	{
2492	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2493	return iemMemMapDataU128AtSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2494	#else
2495	return iemMemMapDataU128AtJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2496	#endif
2497	}
2498
2499
2500	/**
2501	* Used by TB code to map unsigned 128-bit data read-write w/ segmentation.
2502	*/
2503	IEM_DECL_NATIVE_HLP_DEF(RTUINT128U , iemNativeHlpMemMapDataU128Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2504	RTGCPTR GCPtrMem, uint8_t iSegReg))
2505	{
2506	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2507	return iemMemMapDataU128RwSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2508	#else
2509	return iemMemMapDataU128RwJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2510	#endif
2511	}
2512
2513
2514	/**
2515	* Used by TB code to map unsigned 128-bit data writeonly w/ segmentation.
2516	*/
2517	IEM_DECL_NATIVE_HLP_DEF(RTUINT128U , iemNativeHlpMemMapDataU128Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2518	RTGCPTR GCPtrMem, uint8_t iSegReg))
2519	{
2520	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2521	return iemMemMapDataU128WoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2522	#else
2523	return iemMemMapDataU128WoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2524	#endif
2525	}
2526
2527
2528	/**
2529	* Used by TB code to map unsigned 128-bit data readonly w/ segmentation.
2530	*/
2531	IEM_DECL_NATIVE_HLP_DEF(RTUINT128U const , iemNativeHlpMemMapDataU128Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo,
2532	RTGCPTR GCPtrMem, uint8_t iSegReg))
2533	{
2534	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2535	return iemMemMapDataU128RoSafeJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2536	#else
2537	return iemMemMapDataU128RoJmp(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
2538	#endif
2539	}
2540
2541
2542	/*********************************************************************************************************************************
2543	* Helpers: Flat memory mapping. *
2544	*********************************************************************************************************************************/
2545
2546	/**
2547	* Used by TB code to map unsigned 8-bit data for atomic read-write w/ flat
2548	* address.
2549	*/
2550	IEM_DECL_NATIVE_HLP_DEF(uint8_t , iemNativeHlpMemFlatMapDataU8Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2551	{
2552	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2553	return iemMemMapDataU8AtSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2554	#else
2555	return iemMemFlatMapDataU8AtJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2556	#endif
2557	}
2558
2559
2560	/**
2561	* Used by TB code to map unsigned 8-bit data read-write w/ flat address.
2562	*/
2563	IEM_DECL_NATIVE_HLP_DEF(uint8_t , iemNativeHlpMemFlatMapDataU8Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2564	{
2565	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2566	return iemMemMapDataU8RwSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2567	#else
2568	return iemMemFlatMapDataU8RwJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2569	#endif
2570	}
2571
2572
2573	/**
2574	* Used by TB code to map unsigned 8-bit data writeonly w/ flat address.
2575	*/
2576	IEM_DECL_NATIVE_HLP_DEF(uint8_t , iemNativeHlpMemFlatMapDataU8Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2577	{
2578	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2579	return iemMemMapDataU8WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2580	#else
2581	return iemMemFlatMapDataU8WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2582	#endif
2583	}
2584
2585
2586	/**
2587	* Used by TB code to map unsigned 8-bit data readonly w/ flat address.
2588	*/
2589	IEM_DECL_NATIVE_HLP_DEF(uint8_t const , iemNativeHlpMemFlatMapDataU8Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2590	{
2591	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2592	return iemMemMapDataU8RoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2593	#else
2594	return iemMemFlatMapDataU8RoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2595	#endif
2596	}
2597
2598
2599	/**
2600	* Used by TB code to map unsigned 16-bit data for atomic read-write w/ flat
2601	* address.
2602	*/
2603	IEM_DECL_NATIVE_HLP_DEF(uint16_t , iemNativeHlpMemFlatMapDataU16Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2604	{
2605	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2606	return iemMemMapDataU16AtSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2607	#else
2608	return iemMemFlatMapDataU16AtJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2609	#endif
2610	}
2611
2612
2613	/**
2614	* Used by TB code to map unsigned 16-bit data read-write w/ flat address.
2615	*/
2616	IEM_DECL_NATIVE_HLP_DEF(uint16_t , iemNativeHlpMemFlatMapDataU16Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2617	{
2618	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2619	return iemMemMapDataU16RwSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2620	#else
2621	return iemMemFlatMapDataU16RwJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2622	#endif
2623	}
2624
2625
2626	/**
2627	* Used by TB code to map unsigned 16-bit data writeonly w/ flat address.
2628	*/
2629	IEM_DECL_NATIVE_HLP_DEF(uint16_t , iemNativeHlpMemFlatMapDataU16Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2630	{
2631	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2632	return iemMemMapDataU16WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2633	#else
2634	return iemMemFlatMapDataU16WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2635	#endif
2636	}
2637
2638
2639	/**
2640	* Used by TB code to map unsigned 16-bit data readonly w/ flat address.
2641	*/
2642	IEM_DECL_NATIVE_HLP_DEF(uint16_t const , iemNativeHlpMemFlatMapDataU16Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2643	{
2644	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2645	return iemMemMapDataU16RoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2646	#else
2647	return iemMemFlatMapDataU16RoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2648	#endif
2649	}
2650
2651
2652	/**
2653	* Used by TB code to map unsigned 32-bit data for atomic read-write w/ flat
2654	* address.
2655	*/
2656	IEM_DECL_NATIVE_HLP_DEF(uint32_t , iemNativeHlpMemFlatMapDataU32Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2657	{
2658	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2659	return iemMemMapDataU32AtSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2660	#else
2661	return iemMemFlatMapDataU32AtJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2662	#endif
2663	}
2664
2665
2666	/**
2667	* Used by TB code to map unsigned 32-bit data read-write w/ flat address.
2668	*/
2669	IEM_DECL_NATIVE_HLP_DEF(uint32_t , iemNativeHlpMemFlatMapDataU32Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2670	{
2671	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2672	return iemMemMapDataU32RwSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2673	#else
2674	return iemMemFlatMapDataU32RwJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2675	#endif
2676	}
2677
2678
2679	/**
2680	* Used by TB code to map unsigned 32-bit data writeonly w/ flat address.
2681	*/
2682	IEM_DECL_NATIVE_HLP_DEF(uint32_t , iemNativeHlpMemFlatMapDataU32Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2683	{
2684	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2685	return iemMemMapDataU32WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2686	#else
2687	return iemMemFlatMapDataU32WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2688	#endif
2689	}
2690
2691
2692	/**
2693	* Used by TB code to map unsigned 32-bit data readonly w/ flat address.
2694	*/
2695	IEM_DECL_NATIVE_HLP_DEF(uint32_t const , iemNativeHlpMemFlatMapDataU32Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2696	{
2697	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2698	return iemMemMapDataU32RoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2699	#else
2700	return iemMemFlatMapDataU32RoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2701	#endif
2702	}
2703
2704
2705	/**
2706	* Used by TB code to map unsigned 64-bit data for atomic read-write w/ flat
2707	* address.
2708	*/
2709	IEM_DECL_NATIVE_HLP_DEF(uint64_t , iemNativeHlpMemFlatMapDataU64Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2710	{
2711	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2712	return iemMemMapDataU64AtSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2713	#else
2714	return iemMemFlatMapDataU64AtJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2715	#endif
2716	}
2717
2718
2719	/**
2720	* Used by TB code to map unsigned 64-bit data read-write w/ flat address.
2721	*/
2722	IEM_DECL_NATIVE_HLP_DEF(uint64_t , iemNativeHlpMemFlatMapDataU64Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2723	{
2724	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2725	return iemMemMapDataU64RwSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2726	#else
2727	return iemMemFlatMapDataU64RwJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2728	#endif
2729	}
2730
2731
2732	/**
2733	* Used by TB code to map unsigned 64-bit data writeonly w/ flat address.
2734	*/
2735	IEM_DECL_NATIVE_HLP_DEF(uint64_t , iemNativeHlpMemFlatMapDataU64Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2736	{
2737	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2738	return iemMemMapDataU64WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2739	#else
2740	return iemMemFlatMapDataU64WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2741	#endif
2742	}
2743
2744
2745	/**
2746	* Used by TB code to map unsigned 64-bit data readonly w/ flat address.
2747	*/
2748	IEM_DECL_NATIVE_HLP_DEF(uint64_t const , iemNativeHlpMemFlatMapDataU64Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2749	{
2750	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2751	return iemMemMapDataU64RoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2752	#else
2753	return iemMemFlatMapDataU64RoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2754	#endif
2755	}
2756
2757
2758	/**
2759	* Used by TB code to map 80-bit float data writeonly w/ flat address.
2760	*/
2761	IEM_DECL_NATIVE_HLP_DEF(RTFLOAT80U , iemNativeHlpMemFlatMapDataR80Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2762	{
2763	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2764	return iemMemMapDataR80WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2765	#else
2766	return iemMemFlatMapDataR80WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2767	#endif
2768	}
2769
2770
2771	/**
2772	* Used by TB code to map 80-bit BCD data writeonly w/ flat address.
2773	*/
2774	IEM_DECL_NATIVE_HLP_DEF(RTPBCD80U , iemNativeHlpMemFlatMapDataD80Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2775	{
2776	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2777	return iemMemMapDataD80WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2778	#else
2779	return iemMemFlatMapDataD80WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2780	#endif
2781	}
2782
2783
2784	/**
2785	* Used by TB code to map unsigned 128-bit data for atomic read-write w/ flat
2786	* address.
2787	*/
2788	IEM_DECL_NATIVE_HLP_DEF(RTUINT128U , iemNativeHlpMemFlatMapDataU128Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2789	{
2790	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2791	return iemMemMapDataU128AtSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2792	#else
2793	return iemMemFlatMapDataU128AtJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2794	#endif
2795	}
2796
2797
2798	/**
2799	* Used by TB code to map unsigned 128-bit data read-write w/ flat address.
2800	*/
2801	IEM_DECL_NATIVE_HLP_DEF(RTUINT128U , iemNativeHlpMemFlatMapDataU128Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2802	{
2803	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2804	return iemMemMapDataU128RwSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2805	#else
2806	return iemMemFlatMapDataU128RwJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2807	#endif
2808	}
2809
2810
2811	/**
2812	* Used by TB code to map unsigned 128-bit data writeonly w/ flat address.
2813	*/
2814	IEM_DECL_NATIVE_HLP_DEF(RTUINT128U , iemNativeHlpMemFlatMapDataU128Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2815	{
2816	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2817	return iemMemMapDataU128WoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2818	#else
2819	return iemMemFlatMapDataU128WoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2820	#endif
2821	}
2822
2823
2824	/**
2825	* Used by TB code to map unsigned 128-bit data readonly w/ flat address.
2826	*/
2827	IEM_DECL_NATIVE_HLP_DEF(RTUINT128U const , iemNativeHlpMemFlatMapDataU128Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem))
2828	{
2829	#ifdef IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
2830	return iemMemMapDataU128RoSafeJmp(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
2831	#else
2832	return iemMemFlatMapDataU128RoJmp(pVCpu, pbUnmapInfo, GCPtrMem);
2833	#endif
2834	}
2835
2836
2837	/*********************************************************************************************************************************
2838	* Helpers: Commit, rollback & unmap *
2839	*********************************************************************************************************************************/
2840
2841	/**
2842	* Used by TB code to commit and unmap a read-write memory mapping.
2843	*/
2844	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemCommitAndUnmapAtomic,(PVMCPUCC pVCpu, uint8_t bUnmapInfo))
2845	{
2846	return iemMemCommitAndUnmapAtSafeJmp(pVCpu, bUnmapInfo);
2847	}
2848
2849
2850	/**
2851	* Used by TB code to commit and unmap a read-write memory mapping.
2852	*/
2853	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemCommitAndUnmapRw,(PVMCPUCC pVCpu, uint8_t bUnmapInfo))
2854	{
2855	return iemMemCommitAndUnmapRwSafeJmp(pVCpu, bUnmapInfo);
2856	}
2857
2858
2859	/**
2860	* Used by TB code to commit and unmap a write-only memory mapping.
2861	*/
2862	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemCommitAndUnmapWo,(PVMCPUCC pVCpu, uint8_t bUnmapInfo))
2863	{
2864	return iemMemCommitAndUnmapWoSafeJmp(pVCpu, bUnmapInfo);
2865	}
2866
2867
2868	/**
2869	* Used by TB code to commit and unmap a read-only memory mapping.
2870	*/
2871	IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemCommitAndUnmapRo,(PVMCPUCC pVCpu, uint8_t bUnmapInfo))
2872	{
2873	return iemMemCommitAndUnmapRoSafeJmp(pVCpu, bUnmapInfo);
2874	}
2875
2876
2877	/**
2878	* Reinitializes the native recompiler state.
2879	*
2880	* Called before starting a new recompile job.
2881	*/
2882	static PIEMRECOMPILERSTATE iemNativeReInit(PIEMRECOMPILERSTATE pReNative, PCIEMTB pTb)
2883	{
2884	pReNative->cLabels = 0;
2885	pReNative->bmLabelTypes = 0;
2886	pReNative->cFixups = 0;
2887	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2888	pReNative->pDbgInfo->cEntries = 0;
2889	#endif
2890	pReNative->pTbOrg = pTb;
2891	pReNative->cCondDepth = 0;
2892	pReNative->uCondSeqNo = 0;
2893	pReNative->uCheckIrqSeqNo = 0;
2894	pReNative->uTlbSeqNo = 0;
2895
2896	pReNative->Core.bmHstRegs = IEMNATIVE_REG_FIXED_MASK
2897	#if IEMNATIVE_HST_GREG_COUNT < 32
2898	\| ~(RT_BIT(IEMNATIVE_HST_GREG_COUNT) - 1U)
2899	#endif
2900	;
2901	pReNative->Core.bmHstRegsWithGstShadow = 0;
2902	pReNative->Core.bmGstRegShadows = 0;
2903	pReNative->Core.bmVars = 0;
2904	pReNative->Core.bmStack = 0;
2905	AssertCompile(sizeof(pReNative->Core.bmStack) * 8 == IEMNATIVE_FRAME_VAR_SLOTS); /* Must set reserved slots to 1 otherwise. */
2906	pReNative->Core.u64ArgVars = UINT64_MAX;
2907
2908	AssertCompile(RT_ELEMENTS(pReNative->aidxUniqueLabels) == 9);
2909	pReNative->aidxUniqueLabels[0] = UINT32_MAX;
2910	pReNative->aidxUniqueLabels[1] = UINT32_MAX;
2911	pReNative->aidxUniqueLabels[2] = UINT32_MAX;
2912	pReNative->aidxUniqueLabels[3] = UINT32_MAX;
2913	pReNative->aidxUniqueLabels[4] = UINT32_MAX;
2914	pReNative->aidxUniqueLabels[5] = UINT32_MAX;
2915	pReNative->aidxUniqueLabels[6] = UINT32_MAX;
2916	pReNative->aidxUniqueLabels[7] = UINT32_MAX;
2917	pReNative->aidxUniqueLabels[8] = UINT32_MAX;
2918
2919	/* Full host register reinit: */
2920	for (unsigned i = 0; i < RT_ELEMENTS(pReNative->Core.aHstRegs); i++)
2921	{
2922	pReNative->Core.aHstRegs[i].fGstRegShadows = 0;
2923	pReNative->Core.aHstRegs[i].enmWhat = kIemNativeWhat_Invalid;
2924	pReNative->Core.aHstRegs[i].idxVar = UINT8_MAX;
2925	}
2926
2927	uint32_t fRegs = IEMNATIVE_REG_FIXED_MASK
2928	& ~( RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU)
2929	#ifdef IEMNATIVE_REG_FIXED_PCPUMCTX
2930	\| RT_BIT_32(IEMNATIVE_REG_FIXED_PCPUMCTX)
2931	#endif
2932	#ifdef IEMNATIVE_REG_FIXED_PCPUMCTX
2933	\| RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0)
2934	#endif
2935	);
2936	for (uint32_t idxReg = ASMBitFirstSetU32(fRegs) - 1; fRegs != 0; idxReg = ASMBitFirstSetU32(fRegs) - 1)
2937	{
2938	fRegs &= ~RT_BIT_32(idxReg);
2939	pReNative->Core.aHstRegs[IEMNATIVE_REG_FIXED_PVMCPU].enmWhat = kIemNativeWhat_FixedReserved;
2940	}
2941
2942	pReNative->Core.aHstRegs[IEMNATIVE_REG_FIXED_PVMCPU].enmWhat = kIemNativeWhat_pVCpuFixed;
2943	#ifdef IEMNATIVE_REG_FIXED_PCPUMCTX
2944	pReNative->Core.aHstRegs[IEMNATIVE_REG_FIXED_PCPUMCTX].enmWhat = kIemNativeWhat_pCtxFixed;
2945	#endif
2946	#ifdef IEMNATIVE_REG_FIXED_TMP0
2947	pReNative->Core.aHstRegs[IEMNATIVE_REG_FIXED_TMP0].enmWhat = kIemNativeWhat_FixedTmp;
2948	#endif
2949	return pReNative;
2950	}
2951
2952
2953	/**
2954	* Allocates and initializes the native recompiler state.
2955	*
2956	* This is called the first time an EMT wants to recompile something.
2957	*
2958	* @returns Pointer to the new recompiler state.
2959	* @param pVCpu The cross context virtual CPU structure of the calling
2960	* thread.
2961	* @param pTb The TB that's about to be recompiled.
2962	* @thread EMT(pVCpu)
2963	*/
2964	static PIEMRECOMPILERSTATE iemNativeInit(PVMCPUCC pVCpu, PCIEMTB pTb)
2965	{
2966	VMCPU_ASSERT_EMT(pVCpu);
2967
2968	PIEMRECOMPILERSTATE pReNative = (PIEMRECOMPILERSTATE)RTMemAllocZ(sizeof(*pReNative));
2969	AssertReturn(pReNative, NULL);
2970
2971	/*
2972	* Try allocate all the buffers and stuff we need.
2973	*/
2974	pReNative->pInstrBuf = (PIEMNATIVEINSTR)RTMemAllocZ(_64K);
2975	pReNative->paLabels = (PIEMNATIVELABEL)RTMemAllocZ(sizeof(IEMNATIVELABEL) * _8K);
2976	pReNative->paFixups = (PIEMNATIVEFIXUP)RTMemAllocZ(sizeof(IEMNATIVEFIXUP) * _16K);
2977	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2978	pReNative->pDbgInfo = (PIEMTBDBG)RTMemAllocZ(RT_UOFFSETOF_DYN(IEMTBDBG, aEntries[_16K]));
2979	#endif
2980	if (RT_LIKELY( pReNative->pInstrBuf
2981	&& pReNative->paLabels
2982	&& pReNative->paFixups)
2983	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2984	&& pReNative->pDbgInfo
2985	#endif
2986	)
2987	{
2988	/*
2989	* Set the buffer & array sizes on success.
2990	*/
2991	pReNative->cInstrBufAlloc = _64K / sizeof(IEMNATIVEINSTR);
2992	pReNative->cLabelsAlloc = _8K;
2993	pReNative->cFixupsAlloc = _16K;
2994	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2995	pReNative->cDbgInfoAlloc = _16K;
2996	#endif
2997
2998	/* Other constant stuff: */
2999	pReNative->pVCpu = pVCpu;
3000
3001	/*
3002	* Done, just need to save it and reinit it.
3003	*/
3004	pVCpu->iem.s.pNativeRecompilerStateR3 = pReNative;
3005	return iemNativeReInit(pReNative, pTb);
3006	}
3007
3008	/*
3009	* Failed. Cleanup and return.
3010	*/
3011	AssertFailed();
3012	RTMemFree(pReNative->pInstrBuf);
3013	RTMemFree(pReNative->paLabels);
3014	RTMemFree(pReNative->paFixups);
3015	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
3016	RTMemFree(pReNative->pDbgInfo);
3017	#endif
3018	RTMemFree(pReNative);
3019	return NULL;
3020	}
3021
3022
3023	/**
3024	* Creates a label
3025	*
3026	* If the label does not yet have a defined position,
3027	* call iemNativeLabelDefine() later to set it.
3028	*
3029	* @returns Label ID. Throws VBox status code on failure, so no need to check
3030	* the return value.
3031	* @param pReNative The native recompile state.
3032	* @param enmType The label type.
3033	* @param offWhere The instruction offset of the label. UINT32_MAX if the
3034	* label is not yet defined (default).
3035	* @param uData Data associated with the lable. Only applicable to
3036	* certain type of labels. Default is zero.
3037	*/
3038	DECL_HIDDEN_THROW(uint32_t)
3039	iemNativeLabelCreate(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType,
3040	uint32_t offWhere /= UINT32_MAX/, uint16_t uData /= 0/)
3041	{
3042	Assert(uData == 0 \|\| enmType >= kIemNativeLabelType_FirstWithMultipleInstances);
3043
3044	/*
3045	* Locate existing label definition.
3046	*
3047	* This is only allowed for forward declarations where offWhere=UINT32_MAX
3048	* and uData is zero.
3049	*/
3050	PIEMNATIVELABEL paLabels = pReNative->paLabels;
3051	uint32_t const cLabels = pReNative->cLabels;
3052	if ( pReNative->bmLabelTypes & RT_BIT_64(enmType)
3053	#ifndef VBOX_STRICT
3054	&& enmType < kIemNativeLabelType_FirstWithMultipleInstances
3055	&& offWhere == UINT32_MAX
3056	&& uData == 0
3057	#endif
3058	)
3059	{
3060	#ifndef VBOX_STRICT
3061	AssertStmt(enmType > kIemNativeLabelType_Invalid && enmType < kIemNativeLabelType_FirstWithMultipleInstances,
3062	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_1));
3063	uint32_t const idxLabel = pReNative->aidxUniqueLabels[enmType];
3064	if (idxLabel < pReNative->cLabels)
3065	return idxLabel;
3066	#else
3067	for (uint32_t i = 0; i < cLabels; i++)
3068	if ( paLabels[i].enmType == enmType
3069	&& paLabels[i].uData == uData)
3070	{
3071	AssertStmt(uData == 0, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_1));
3072	AssertStmt(offWhere == UINT32_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_1));
3073	AssertStmt(paLabels[i].off == UINT32_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_2));
3074	AssertStmt(enmType < kIemNativeLabelType_FirstWithMultipleInstances && pReNative->aidxUniqueLabels[enmType] == i,
3075	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_1));
3076	return i;
3077	}
3078	AssertStmt( enmType >= kIemNativeLabelType_FirstWithMultipleInstances
3079	\|\| pReNative->aidxUniqueLabels[enmType] == UINT32_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_1));
3080	#endif
3081	}
3082
3083	/*
3084	* Make sure we've got room for another label.
3085	*/
3086	if (RT_LIKELY(cLabels < pReNative->cLabelsAlloc))
3087	{ /* likely */ }
3088	else
3089	{
3090	uint32_t cNew = pReNative->cLabelsAlloc;
3091	AssertStmt(cNew, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_3));
3092	AssertStmt(cLabels == cNew, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_3));
3093	cNew *= 2;
3094	AssertStmt(cNew <= _64K, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_TOO_MANY)); /* IEMNATIVEFIXUP::idxLabel type restrict this */
3095	paLabels = (PIEMNATIVELABEL)RTMemRealloc(paLabels, cNew * sizeof(paLabels[0]));
3096	AssertStmt(paLabels, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_OUT_OF_MEMORY));
3097	pReNative->paLabels = paLabels;
3098	pReNative->cLabelsAlloc = cNew;
3099	}
3100
3101	/*
3102	* Define a new label.
3103	*/
3104	paLabels[cLabels].off = offWhere;
3105	paLabels[cLabels].enmType = enmType;
3106	paLabels[cLabels].uData = uData;
3107	pReNative->cLabels = cLabels + 1;
3108
3109	Assert((unsigned)enmType < 64);
3110	pReNative->bmLabelTypes \|= RT_BIT_64(enmType);
3111
3112	if (enmType < kIemNativeLabelType_FirstWithMultipleInstances)
3113	{
3114	Assert(uData == 0);
3115	pReNative->aidxUniqueLabels[enmType] = cLabels;
3116	}
3117
3118	if (offWhere != UINT32_MAX)
3119	{
3120	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
3121	iemNativeDbgInfoAddNativeOffset(pReNative, offWhere);
3122	iemNativeDbgInfoAddLabel(pReNative, enmType, uData);
3123	#endif
3124	}
3125	return cLabels;
3126	}
3127
3128
3129	/**
3130	* Defines the location of an existing label.
3131	*
3132	* @param pReNative The native recompile state.
3133	* @param idxLabel The label to define.
3134	* @param offWhere The position.
3135	*/
3136	DECL_HIDDEN_THROW(void) iemNativeLabelDefine(PIEMRECOMPILERSTATE pReNative, uint32_t idxLabel, uint32_t offWhere)
3137	{
3138	AssertStmt(idxLabel < pReNative->cLabels, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_4));
3139	PIEMNATIVELABEL const pLabel = &pReNative->paLabels[idxLabel];
3140	AssertStmt(pLabel->off == UINT32_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_5));
3141	pLabel->off = offWhere;
3142	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
3143	iemNativeDbgInfoAddNativeOffset(pReNative, offWhere);
3144	iemNativeDbgInfoAddLabel(pReNative, (IEMNATIVELABELTYPE)pLabel->enmType, pLabel->uData);
3145	#endif
3146	}
3147
3148
3149	/**
3150	* Looks up a lable.
3151	*
3152	* @returns Label ID if found, UINT32_MAX if not.
3153	*/
3154	static uint32_t iemNativeLabelFind(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType,
3155	uint32_t offWhere = UINT32_MAX, uint16_t uData = 0) RT_NOEXCEPT
3156	{
3157	Assert((unsigned)enmType < 64);
3158	if (RT_BIT_64(enmType) & pReNative->bmLabelTypes)
3159	{
3160	if (enmType < kIemNativeLabelType_FirstWithMultipleInstances)
3161	return pReNative->aidxUniqueLabels[enmType];
3162
3163	PIEMNATIVELABEL paLabels = pReNative->paLabels;
3164	uint32_t const cLabels = pReNative->cLabels;
3165	for (uint32_t i = 0; i < cLabels; i++)
3166	if ( paLabels[i].enmType == enmType
3167	&& paLabels[i].uData == uData
3168	&& ( paLabels[i].off == offWhere
3169	\|\| offWhere == UINT32_MAX
3170	\|\| paLabels[i].off == UINT32_MAX))
3171	return i;
3172	}
3173	return UINT32_MAX;
3174	}
3175
3176
3177	/**
3178	* Adds a fixup.
3179	*
3180	* @throws VBox status code (int) on failure.
3181	* @param pReNative The native recompile state.
3182	* @param offWhere The instruction offset of the fixup location.
3183	* @param idxLabel The target label ID for the fixup.
3184	* @param enmType The fixup type.
3185	* @param offAddend Fixup addend if applicable to the type. Default is 0.
3186	*/
3187	DECL_HIDDEN_THROW(void)
3188	iemNativeAddFixup(PIEMRECOMPILERSTATE pReNative, uint32_t offWhere, uint32_t idxLabel,
3189	IEMNATIVEFIXUPTYPE enmType, int8_t offAddend /= 0/)
3190	{
3191	Assert(idxLabel <= UINT16_MAX);
3192	Assert((unsigned)enmType <= UINT8_MAX);
3193
3194	/*
3195	* Make sure we've room.
3196	*/
3197	PIEMNATIVEFIXUP paFixups = pReNative->paFixups;
3198	uint32_t const cFixups = pReNative->cFixups;
3199	if (RT_LIKELY(cFixups < pReNative->cFixupsAlloc))
3200	{ /* likely */ }
3201	else
3202	{
3203	uint32_t cNew = pReNative->cFixupsAlloc;
3204	AssertStmt(cNew, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_FIXUP_IPE_1));
3205	AssertStmt(cFixups == cNew, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_FIXUP_IPE_1));
3206	cNew *= 2;
3207	AssertStmt(cNew <= _128K, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_FIXUP_TOO_MANY));
3208	paFixups = (PIEMNATIVEFIXUP)RTMemRealloc(paFixups, cNew * sizeof(paFixups[0]));
3209	AssertStmt(paFixups, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_FIXUP_OUT_OF_MEMORY));
3210	pReNative->paFixups = paFixups;
3211	pReNative->cFixupsAlloc = cNew;
3212	}
3213
3214	/*
3215	* Add the fixup.
3216	*/
3217	paFixups[cFixups].off = offWhere;
3218	paFixups[cFixups].idxLabel = (uint16_t)idxLabel;
3219	paFixups[cFixups].enmType = enmType;
3220	paFixups[cFixups].offAddend = offAddend;
3221	pReNative->cFixups = cFixups + 1;
3222	}
3223
3224
3225	/**
3226	* Slow code path for iemNativeInstrBufEnsure.
3227	*/
3228	DECL_HIDDEN_THROW(PIEMNATIVEINSTR) iemNativeInstrBufEnsureSlow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq)
3229	{
3230	/* Double the buffer size till we meet the request. */
3231	uint32_t cNew = pReNative->cInstrBufAlloc;
3232	AssertStmt(cNew > 0, IEMNATIVE_DO_LONGJMP(pReNative, VERR_INTERNAL_ERROR_5)); /* impossible */
3233	do
3234	cNew *= 2;
3235	while (cNew < off + cInstrReq);
3236
3237	uint32_t const cbNew = cNew * sizeof(IEMNATIVEINSTR);
3238	#ifdef RT_ARCH_ARM64
3239	uint32_t const cbMaxInstrBuf = _1M; /* Limited by the branch instruction range (18+2 bits). */
3240	#else
3241	uint32_t const cbMaxInstrBuf = _2M;
3242	#endif
3243	AssertStmt(cbNew <= cbMaxInstrBuf, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_INSTR_BUF_TOO_LARGE));
3244
3245	void *pvNew = RTMemRealloc(pReNative->pInstrBuf, cbNew);
3246	AssertStmt(pvNew, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_INSTR_BUF_OUT_OF_MEMORY));
3247
3248	#ifdef VBOX_STRICT
3249	pReNative->offInstrBufChecked = off + cInstrReq;
3250	#endif
3251	pReNative->cInstrBufAlloc = cNew;
3252	return pReNative->pInstrBuf = (PIEMNATIVEINSTR)pvNew;
3253	}
3254
3255	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
3256
3257	/**
3258	* Grows the static debug info array used during recompilation.
3259	*
3260	* @returns Pointer to the new debug info block; throws VBox status code on
3261	* failure, so no need to check the return value.
3262	*/
3263	DECL_NO_INLINE(static, PIEMTBDBG) iemNativeDbgInfoGrow(PIEMRECOMPILERSTATE pReNative, PIEMTBDBG pDbgInfo)
3264	{
3265	uint32_t cNew = pReNative->cDbgInfoAlloc * 2;
3266	AssertStmt(cNew < _1M && cNew != 0, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_DBGINFO_IPE_1));
3267	pDbgInfo = (PIEMTBDBG)RTMemRealloc(pDbgInfo, RT_UOFFSETOF_DYN(IEMTBDBG, aEntries[cNew]));
3268	AssertStmt(pDbgInfo, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_DBGINFO_OUT_OF_MEMORY));
3269	pReNative->pDbgInfo = pDbgInfo;
3270	pReNative->cDbgInfoAlloc = cNew;
3271	return pDbgInfo;
3272	}
3273
3274
3275	/**
3276	* Adds a new debug info uninitialized entry, returning the pointer to it.
3277	*/
3278	DECL_INLINE_THROW(PIEMTBDBGENTRY) iemNativeDbgInfoAddNewEntry(PIEMRECOMPILERSTATE pReNative, PIEMTBDBG pDbgInfo)
3279	{
3280	if (RT_LIKELY(pDbgInfo->cEntries < pReNative->cDbgInfoAlloc))
3281	{ /* likely */ }
3282	else
3283	pDbgInfo = iemNativeDbgInfoGrow(pReNative, pDbgInfo);
3284	return &pDbgInfo->aEntries[pDbgInfo->cEntries++];
3285	}
3286
3287
3288	/**
3289	* Debug Info: Adds a native offset record, if necessary.
3290	*/
3291	static void iemNativeDbgInfoAddNativeOffset(PIEMRECOMPILERSTATE pReNative, uint32_t off)
3292	{
3293	PIEMTBDBG pDbgInfo = pReNative->pDbgInfo;
3294
3295	/*
3296	* Search backwards to see if we've got a similar record already.
3297	*/
3298	uint32_t idx = pDbgInfo->cEntries;
3299	uint32_t idxStop = idx > 8 ? idx - 8 : 0;
3300	while (idx-- > idxStop)
3301	if (pDbgInfo->aEntries[idx].Gen.uType == kIemTbDbgEntryType_NativeOffset)
3302	{
3303	if (pDbgInfo->aEntries[idx].NativeOffset.offNative == off)
3304	return;
3305	AssertStmt(pDbgInfo->aEntries[idx].NativeOffset.offNative < off,
3306	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_DBGINFO_IPE_2));
3307	break;
3308	}
3309
3310	/*
3311	* Add it.
3312	*/
3313	PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pDbgInfo);
3314	pEntry->NativeOffset.uType = kIemTbDbgEntryType_NativeOffset;
3315	pEntry->NativeOffset.offNative = off;
3316	}
3317
3318
3319	/**
3320	* Debug Info: Record info about a label.
3321	*/
3322	static void iemNativeDbgInfoAddLabel(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType, uint16_t uData)
3323	{
3324	PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
3325	pEntry->Label.uType = kIemTbDbgEntryType_Label;
3326	pEntry->Label.uUnused = 0;
3327	pEntry->Label.enmLabel = (uint8_t)enmType;
3328	pEntry->Label.uData = uData;
3329	}
3330
3331
3332	/**
3333	* Debug Info: Record info about a threaded call.
3334	*/
3335	static void iemNativeDbgInfoAddThreadedCall(PIEMRECOMPILERSTATE pReNative, IEMTHREADEDFUNCS enmCall, bool fRecompiled)
3336	{
3337	PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
3338	pEntry->ThreadedCall.uType = kIemTbDbgEntryType_ThreadedCall;
3339	pEntry->ThreadedCall.fRecompiled = fRecompiled;
3340	pEntry->ThreadedCall.uUnused = 0;
3341	pEntry->ThreadedCall.enmCall = (uint16_t)enmCall;
3342	}
3343
3344
3345	/**
3346	* Debug Info: Record info about a new guest instruction.
3347	*/
3348	static void iemNativeDbgInfoAddGuestInstruction(PIEMRECOMPILERSTATE pReNative, uint32_t fExec)
3349	{
3350	PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
3351	pEntry->GuestInstruction.uType = kIemTbDbgEntryType_GuestInstruction;
3352	pEntry->GuestInstruction.uUnused = 0;
3353	pEntry->GuestInstruction.fExec = fExec;
3354	}
3355
3356
3357	/**
3358	* Debug Info: Record info about guest register shadowing.
3359	*/
3360	static void iemNativeDbgInfoAddGuestRegShadowing(PIEMRECOMPILERSTATE pReNative, IEMNATIVEGSTREG enmGstReg,
3361	uint8_t idxHstReg = UINT8_MAX, uint8_t idxHstRegPrev = UINT8_MAX)
3362	{
3363	PIEMTBDBGENTRY const pEntry = iemNativeDbgInfoAddNewEntry(pReNative, pReNative->pDbgInfo);
3364	pEntry->GuestRegShadowing.uType = kIemTbDbgEntryType_GuestRegShadowing;
3365	pEntry->GuestRegShadowing.uUnused = 0;
3366	pEntry->GuestRegShadowing.idxGstReg = enmGstReg;
3367	pEntry->GuestRegShadowing.idxHstReg = idxHstReg;
3368	pEntry->GuestRegShadowing.idxHstRegPrev = idxHstRegPrev;
3369	}
3370
3371	#endif /* IEMNATIVE_WITH_TB_DEBUG_INFO */
3372
3373
3374	/*********************************************************************************************************************************
3375	* Register Allocator *
3376	*********************************************************************************************************************************/
3377
3378	/**
3379	* Register parameter indexes (indexed by argument number).
3380	*/
3381	DECL_HIDDEN_CONST(uint8_t) const g_aidxIemNativeCallRegs[] =
3382	{
3383	IEMNATIVE_CALL_ARG0_GREG,
3384	IEMNATIVE_CALL_ARG1_GREG,
3385	IEMNATIVE_CALL_ARG2_GREG,
3386	IEMNATIVE_CALL_ARG3_GREG,
3387	#if defined(IEMNATIVE_CALL_ARG4_GREG)
3388	IEMNATIVE_CALL_ARG4_GREG,
3389	# if defined(IEMNATIVE_CALL_ARG5_GREG)
3390	IEMNATIVE_CALL_ARG5_GREG,
3391	# if defined(IEMNATIVE_CALL_ARG6_GREG)
3392	IEMNATIVE_CALL_ARG6_GREG,
3393	# if defined(IEMNATIVE_CALL_ARG7_GREG)
3394	IEMNATIVE_CALL_ARG7_GREG,
3395	# endif
3396	# endif
3397	# endif
3398	#endif
3399	};
3400
3401	/**
3402	* Call register masks indexed by argument count.
3403	*/
3404	DECL_HIDDEN_CONST(uint32_t) const g_afIemNativeCallRegs[] =
3405	{
3406	0,
3407	RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG),
3408	RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG),
3409	RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG),
3410	RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG)
3411	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG),
3412	#if defined(IEMNATIVE_CALL_ARG4_GREG)
3413	RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG)
3414	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG),
3415	# if defined(IEMNATIVE_CALL_ARG5_GREG)
3416	RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG)
3417	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG5_GREG),
3418	# if defined(IEMNATIVE_CALL_ARG6_GREG)
3419	RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG)
3420	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG5_GREG)
3421	\| RT_BIT_32(IEMNATIVE_CALL_ARG6_GREG),
3422	# if defined(IEMNATIVE_CALL_ARG7_GREG)
3423	RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG)
3424	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG5_GREG)
3425	\| RT_BIT_32(IEMNATIVE_CALL_ARG6_GREG) \| RT_BIT_32(IEMNATIVE_CALL_ARG7_GREG),
3426	# endif
3427	# endif
3428	# endif
3429	#endif
3430	};
3431
3432	#ifdef IEMNATIVE_FP_OFF_STACK_ARG0
3433	/**
3434	* BP offset of the stack argument slots.
3435	*
3436	* This array is indexed by \#argument - IEMNATIVE_CALL_ARG_GREG_COUNT and has
3437	* IEMNATIVE_FRAME_STACK_ARG_COUNT entries.
3438	*/
3439	DECL_HIDDEN_CONST(int32_t) const g_aoffIemNativeCallStackArgBpDisp[] =
3440	{
3441	IEMNATIVE_FP_OFF_STACK_ARG0,
3442	# ifdef IEMNATIVE_FP_OFF_STACK_ARG1
3443	IEMNATIVE_FP_OFF_STACK_ARG1,
3444	# endif
3445	# ifdef IEMNATIVE_FP_OFF_STACK_ARG2
3446	IEMNATIVE_FP_OFF_STACK_ARG2,
3447	# endif
3448	# ifdef IEMNATIVE_FP_OFF_STACK_ARG3
3449	IEMNATIVE_FP_OFF_STACK_ARG3,
3450	# endif
3451	};
3452	AssertCompile(RT_ELEMENTS(g_aoffIemNativeCallStackArgBpDisp) == IEMNATIVE_FRAME_STACK_ARG_COUNT);
3453	#endif /* IEMNATIVE_FP_OFF_STACK_ARG0 */
3454
3455	/**
3456	* Info about shadowed guest register values.
3457	* @see IEMNATIVEGSTREG
3458	*/
3459	static struct
3460	{
3461	/** Offset in VMCPU. */
3462	uint32_t off;
3463	/** The field size. */
3464	uint8_t cb;
3465	/** Name (for logging). */
3466	const char *pszName;
3467	} const g_aGstShadowInfo[] =
3468	{
3469	#define CPUMCTX_OFF_AND_SIZE(a_Reg) (uint32_t)RT_UOFFSETOF(VMCPU, cpum.GstCtx. a_Reg), RT_SIZEOFMEMB(VMCPU, cpum.GstCtx. a_Reg)
3470	/* [kIemNativeGstReg_GprFirst + X86_GREG_xAX] = */ { CPUMCTX_OFF_AND_SIZE(rax), "rax", },
3471	/* [kIemNativeGstReg_GprFirst + X86_GREG_xCX] = */ { CPUMCTX_OFF_AND_SIZE(rcx), "rcx", },
3472	/* [kIemNativeGstReg_GprFirst + X86_GREG_xDX] = */ { CPUMCTX_OFF_AND_SIZE(rdx), "rdx", },
3473	/* [kIemNativeGstReg_GprFirst + X86_GREG_xBX] = */ { CPUMCTX_OFF_AND_SIZE(rbx), "rbx", },
3474	/* [kIemNativeGstReg_GprFirst + X86_GREG_xSP] = */ { CPUMCTX_OFF_AND_SIZE(rsp), "rsp", },
3475	/* [kIemNativeGstReg_GprFirst + X86_GREG_xBP] = */ { CPUMCTX_OFF_AND_SIZE(rbp), "rbp", },
3476	/* [kIemNativeGstReg_GprFirst + X86_GREG_xSI] = */ { CPUMCTX_OFF_AND_SIZE(rsi), "rsi", },
3477	/* [kIemNativeGstReg_GprFirst + X86_GREG_xDI] = */ { CPUMCTX_OFF_AND_SIZE(rdi), "rdi", },
3478	/* [kIemNativeGstReg_GprFirst + X86_GREG_x8 ] = */ { CPUMCTX_OFF_AND_SIZE(r8), "r8", },
3479	/* [kIemNativeGstReg_GprFirst + X86_GREG_x9 ] = */ { CPUMCTX_OFF_AND_SIZE(r9), "r9", },
3480	/* [kIemNativeGstReg_GprFirst + X86_GREG_x10] = */ { CPUMCTX_OFF_AND_SIZE(r10), "r10", },
3481	/* [kIemNativeGstReg_GprFirst + X86_GREG_x11] = */ { CPUMCTX_OFF_AND_SIZE(r11), "r11", },
3482	/* [kIemNativeGstReg_GprFirst + X86_GREG_x12] = */ { CPUMCTX_OFF_AND_SIZE(r12), "r12", },
3483	/* [kIemNativeGstReg_GprFirst + X86_GREG_x13] = */ { CPUMCTX_OFF_AND_SIZE(r13), "r13", },
3484	/* [kIemNativeGstReg_GprFirst + X86_GREG_x14] = */ { CPUMCTX_OFF_AND_SIZE(r14), "r14", },
3485	/* [kIemNativeGstReg_GprFirst + X86_GREG_x15] = */ { CPUMCTX_OFF_AND_SIZE(r15), "r15", },
3486	/* [kIemNativeGstReg_Pc] = */ { CPUMCTX_OFF_AND_SIZE(rip), "rip", },
3487	/* [kIemNativeGstReg_LivenessPadding17] = */ { UINT32_MAX / 4, 0, "pad17", },
3488	/* [kIemNativeGstReg_LivenessPadding18] = */ { UINT32_MAX / 4, 0, "pad18", },
3489	/* [kIemNativeGstReg_LivenessPadding19] = */ { UINT32_MAX / 4, 0, "pad19", },
3490	/* [kIemNativeGstReg_SegBaseFirst + 0] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[0].u64Base), "es_base", },
3491	/* [kIemNativeGstReg_SegBaseFirst + 1] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[1].u64Base), "cs_base", },
3492	/* [kIemNativeGstReg_SegBaseFirst + 2] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[2].u64Base), "ss_base", },
3493	/* [kIemNativeGstReg_SegBaseFirst + 3] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[3].u64Base), "ds_base", },
3494	/* [kIemNativeGstReg_SegBaseFirst + 4] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[4].u64Base), "fs_base", },
3495	/* [kIemNativeGstReg_SegBaseFirst + 5] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[5].u64Base), "gs_base", },
3496	/* [kIemNativeGstReg_SegAttribFirst + 0] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[0].Attr.u), "es_attrib", },
3497	/* [kIemNativeGstReg_SegAttribFirst + 1] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[1].Attr.u), "cs_attrib", },
3498	/* [kIemNativeGstReg_SegAttribFirst + 2] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[2].Attr.u), "ss_attrib", },
3499	/* [kIemNativeGstReg_SegAttribFirst + 3] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[3].Attr.u), "ds_attrib", },
3500	/* [kIemNativeGstReg_SegAttribFirst + 4] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[4].Attr.u), "fs_attrib", },
3501	/* [kIemNativeGstReg_SegAttribFirst + 5] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[5].Attr.u), "gs_attrib", },
3502	/* [kIemNativeGstReg_SegLimitFirst + 0] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[0].u32Limit), "es_limit", },
3503	/* [kIemNativeGstReg_SegLimitFirst + 1] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[1].u32Limit), "cs_limit", },
3504	/* [kIemNativeGstReg_SegLimitFirst + 2] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[2].u32Limit), "ss_limit", },
3505	/* [kIemNativeGstReg_SegLimitFirst + 3] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[3].u32Limit), "ds_limit", },
3506	/* [kIemNativeGstReg_SegLimitFirst + 4] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[4].u32Limit), "fs_limit", },
3507	/* [kIemNativeGstReg_SegLimitFirst + 5] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[5].u32Limit), "gs_limit", },
3508	/* [kIemNativeGstReg_SegSelFirst + 0] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[0].Sel), "es", },
3509	/* [kIemNativeGstReg_SegSelFirst + 1] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[1].Sel), "cs", },
3510	/* [kIemNativeGstReg_SegSelFirst + 2] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[2].Sel), "ss", },
3511	/* [kIemNativeGstReg_SegSelFirst + 3] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[3].Sel), "ds", },
3512	/* [kIemNativeGstReg_SegSelFirst + 4] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[4].Sel), "fs", },
3513	/* [kIemNativeGstReg_SegSelFirst + 5] = */ { CPUMCTX_OFF_AND_SIZE(aSRegs[5].Sel), "gs", },
3514	/* [kIemNativeGstReg_EFlags] = */ { CPUMCTX_OFF_AND_SIZE(eflags), "eflags", },
3515	#undef CPUMCTX_OFF_AND_SIZE
3516	};
3517	AssertCompile(RT_ELEMENTS(g_aGstShadowInfo) == kIemNativeGstReg_End);
3518
3519
3520	/** Host CPU general purpose register names. */
3521	DECL_HIDDEN_CONST(const char * const) g_apszIemNativeHstRegNames[] =
3522	{
3523	#ifdef RT_ARCH_AMD64
3524	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3525	#elif RT_ARCH_ARM64
3526	"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3527	"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "bp", "lr", "sp/xzr",
3528	#else
3529	# error "port me"
3530	#endif
3531	};
3532
3533
3534	DECL_FORCE_INLINE(uint8_t) iemNativeRegMarkAllocated(PIEMRECOMPILERSTATE pReNative, unsigned idxReg,
3535	IEMNATIVEWHAT enmWhat, uint8_t idxVar = UINT8_MAX) RT_NOEXCEPT
3536	{
3537	pReNative->Core.bmHstRegs \|= RT_BIT_32(idxReg);
3538
3539	pReNative->Core.aHstRegs[idxReg].enmWhat = enmWhat;
3540	pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
3541	pReNative->Core.aHstRegs[idxReg].idxVar = idxVar;
3542	return (uint8_t)idxReg;
3543	}
3544
3545
3546	#if 0 /* unused */
3547	/**
3548	* Tries to locate a suitable register in the given register mask.
3549	*
3550	* This ASSUMES the caller has done the minimal/optimal allocation checks and
3551	* failed.
3552	*
3553	* @returns Host register number on success, returns UINT8_MAX on failure.
3554	*/
3555	static uint8_t iemNativeRegTryAllocFree(PIEMRECOMPILERSTATE pReNative, uint32_t fRegMask)
3556	{
3557	Assert(!(fRegMask & ~IEMNATIVE_HST_GREG_MASK));
3558	uint32_t fRegs = ~pReNative->Core.bmHstRegs & fRegMask;
3559	if (fRegs)
3560	{
3561	/** @todo pick better here: */
3562	unsigned const idxReg = ASMBitFirstSetU32(fRegs) - 1;
3563
3564	Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows != 0);
3565	Assert( (pReNative->Core.aHstRegs[idxReg].fGstRegShadows & pReNative->Core.bmGstRegShadows)
3566	== pReNative->Core.aHstRegs[idxReg].fGstRegShadows);
3567	Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg));
3568
3569	pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
3570	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxReg);
3571	pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
3572	return idxReg;
3573	}
3574	return UINT8_MAX;
3575	}
3576	#endif /* unused */
3577
3578
3579	/**
3580	* Locate a register, possibly freeing one up.
3581	*
3582	* This ASSUMES the caller has done the minimal/optimal allocation checks and
3583	* failed.
3584	*
3585	* @returns Host register number on success. Returns UINT8_MAX if no registers
3586	* found, the caller is supposed to deal with this and raise a
3587	* allocation type specific status code (if desired).
3588	*
3589	* @throws VBox status code if we're run into trouble spilling a variable of
3590	* recording debug info. Does NOT throw anything if we're out of
3591	* registers, though.
3592	*/
3593	static uint8_t iemNativeRegAllocFindFree(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, bool fPreferVolatile,
3594	uint32_t fRegMask = IEMNATIVE_HST_GREG_MASK & ~IEMNATIVE_REG_FIXED_MASK)
3595	{
3596	STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeRegFindFree);
3597	Assert(!(fRegMask & ~IEMNATIVE_HST_GREG_MASK));
3598	Assert(!(fRegMask & IEMNATIVE_REG_FIXED_MASK));
3599
3600	/*
3601	* Try a freed register that's shadowing a guest register.
3602	*/
3603	uint32_t fRegs = ~pReNative->Core.bmHstRegs & fRegMask;
3604	if (fRegs)
3605	{
3606	STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeRegFindFreeNoVar);
3607
3608	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
3609	/*
3610	* When we have livness information, we use it to kick out all shadowed
3611	* guest register that will not be needed any more in this TB. If we're
3612	* lucky, this may prevent us from ending up here again.
3613	*
3614	* Note! We must consider the previous entry here so we don't free
3615	* anything that the current threaded function requires (current
3616	* entry is produced by the next threaded function).
3617	*/
3618	uint32_t const idxCurCall = pReNative->idxCurCall;
3619	if (idxCurCall > 0)
3620	{
3621	PCIEMLIVENESSENTRY const pLivenessEntry = &pReNative->paLivenessEntries[idxCurCall - 1];
3622
3623	# ifndef IEMLIVENESS_EXTENDED_LAYOUT
3624	/* Construct a mask of the guest registers in the UNUSED and XCPT_OR_CALL state. */
3625	AssertCompile(IEMLIVENESS_STATE_UNUSED == 1 && IEMLIVENESS_STATE_XCPT_OR_CALL == 2);
3626	uint64_t fToFreeMask = pLivenessEntry->Bit0.bm64 ^ pLivenessEntry->Bit1.bm64; /* mask of regs in either UNUSED */
3627	#else
3628	/* Construct a mask of the registers not in the read or write state.
3629	Note! We could skips writes, if they aren't from us, as this is just
3630	a hack to prevent trashing registers that have just been written
3631	or will be written when we retire the current instruction. */
3632	uint64_t fToFreeMask = ~pLivenessEntry->aBits[IEMLIVENESS_BIT_READ].bm64
3633	& ~pLivenessEntry->aBits[IEMLIVENESS_BIT_WRITE].bm64
3634	& IEMLIVENESSBIT_MASK;
3635	#endif
3636	/* Merge EFLAGS. */
3637	uint64_t fTmp = fToFreeMask & (fToFreeMask >> 3); /* AF2,PF2,CF2,Other2 = AF,PF,CF,Other & OF,SF,ZF,AF */
3638	fTmp &= fTmp >> 2; /* CF3,Other3 = AF2,PF2 & CF2,Other2 */
3639	fTmp &= fTmp >> 1; /* Other4 = CF3 & Other3 */
3640	fToFreeMask &= RT_BIT_64(kIemNativeGstReg_EFlags) - 1;
3641	fToFreeMask \|= fTmp & RT_BIT_64(kIemNativeGstReg_EFlags);
3642
3643	/* If it matches any shadowed registers. */
3644	if (pReNative->Core.bmGstRegShadows & fToFreeMask)
3645	{
3646	STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeRegFindFreeLivenessUnshadowed);
3647	iemNativeRegFlushGuestShadows(pReNative, fToFreeMask);
3648	Assert(fRegs == (~pReNative->Core.bmHstRegs & fRegMask)); /* this shall not change. */
3649
3650	/* See if we've got any unshadowed registers we can return now. */
3651	uint32_t const fUnshadowedRegs = fRegs & ~pReNative->Core.bmHstRegsWithGstShadow;
3652	if (fUnshadowedRegs)
3653	{
3654	STAM_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeRegFindFreeLivenessHelped);
3655	return (fPreferVolatile
3656	? ASMBitFirstSetU32(fUnshadowedRegs)
3657	: ASMBitLastSetU32( fUnshadowedRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK
3658	? fUnshadowedRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK : fUnshadowedRegs))
3659	- 1;
3660	}
3661	}
3662	}
3663	#endif /* IEMNATIVE_WITH_LIVENESS_ANALYSIS */
3664
3665	unsigned const idxReg = (fPreferVolatile
3666	? ASMBitFirstSetU32(fRegs)
3667	: ASMBitLastSetU32( fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK
3668	? fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK : fRegs))
3669	- 1;
3670
3671	Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows != 0);
3672	Assert( (pReNative->Core.aHstRegs[idxReg].fGstRegShadows & pReNative->Core.bmGstRegShadows)
3673	== pReNative->Core.aHstRegs[idxReg].fGstRegShadows);
3674	Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg));
3675
3676	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxReg);
3677	pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
3678	pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
3679	return idxReg;
3680	}
3681
3682	/*
3683	* Try free up a variable that's in a register.
3684	*
3685	* We do two rounds here, first evacuating variables we don't need to be
3686	* saved on the stack, then in the second round move things to the stack.
3687	*/
3688	STAM_REL_COUNTER_INC(&pReNative->pVCpu->iem.s.StatNativeRegFindFreeVar);
3689	for (uint32_t iLoop = 0; iLoop < 2; iLoop++)
3690	{
3691	uint32_t fVars = pReNative->Core.bmVars;
3692	while (fVars)
3693	{
3694	uint32_t const idxVar = ASMBitFirstSetU32(fVars) - 1;
3695	uint8_t const idxReg = pReNative->Core.aVars[idxVar].idxReg;
3696	if ( idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs)
3697	&& (RT_BIT_32(idxReg) & fRegMask)
3698	&& ( iLoop == 0
3699	? pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_Stack
3700	: pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
3701	&& !pReNative->Core.aVars[idxVar].fRegAcquired)
3702	{
3703	Assert(pReNative->Core.bmHstRegs & RT_BIT_32(idxReg));
3704	Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxReg].fGstRegShadows)
3705	== pReNative->Core.aHstRegs[idxReg].fGstRegShadows);
3706	Assert(pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
3707	Assert( RT_BOOL(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg))
3708	== RT_BOOL(pReNative->Core.aHstRegs[idxReg].fGstRegShadows));
3709
3710	if (pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
3711	{
3712	uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxVar);
3713	poff = iemNativeEmitStoreGprByBp(pReNative, poff, iemNativeStackCalcBpDisp(idxStackSlot), idxReg);
3714	}
3715
3716	pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
3717	pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxReg);
3718
3719	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxReg);
3720	pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
3721	pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
3722	return idxReg;
3723	}
3724	fVars &= ~RT_BIT_32(idxVar);
3725	}
3726	}
3727
3728	return UINT8_MAX;
3729	}
3730
3731
3732	/**
3733	* Reassigns a variable to a different register specified by the caller.
3734	*
3735	* @returns The new code buffer position.
3736	* @param pReNative The native recompile state.
3737	* @param off The current code buffer position.
3738	* @param idxVar The variable index.
3739	* @param idxRegOld The old host register number.
3740	* @param idxRegNew The new host register number.
3741	* @param pszCaller The caller for logging.
3742	*/
3743	static uint32_t iemNativeRegMoveVar(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVar,
3744	uint8_t idxRegOld, uint8_t idxRegNew, const char *pszCaller)
3745	{
3746	Assert(pReNative->Core.aVars[idxVar].idxReg == idxRegOld);
3747	RT_NOREF(pszCaller);
3748
3749	iemNativeRegClearGstRegShadowing(pReNative, idxRegNew, off);
3750
3751	uint64_t fGstRegShadows = pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows;
3752	Log12(("%s: moving idxVar=%d from %s to %s (fGstRegShadows=%RX64)\n",
3753	pszCaller, idxVar, g_apszIemNativeHstRegNames[idxRegOld], g_apszIemNativeHstRegNames[idxRegNew], fGstRegShadows));
3754	off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxRegNew, idxRegOld);
3755
3756	pReNative->Core.aHstRegs[idxRegNew].fGstRegShadows = fGstRegShadows;
3757	pReNative->Core.aHstRegs[idxRegNew].enmWhat = kIemNativeWhat_Var;
3758	pReNative->Core.aHstRegs[idxRegNew].idxVar = idxVar;
3759	if (fGstRegShadows)
3760	{
3761	pReNative->Core.bmHstRegsWithGstShadow = (pReNative->Core.bmHstRegsWithGstShadow & ~RT_BIT_32(idxRegOld))
3762	\| RT_BIT_32(idxRegNew);
3763	while (fGstRegShadows)
3764	{
3765	unsigned const idxGstReg = ASMBitFirstSetU64(fGstRegShadows) - 1;
3766	fGstRegShadows &= ~RT_BIT_64(idxGstReg);
3767
3768	Assert(pReNative->Core.aidxGstRegShadows[idxGstReg] == idxRegOld);
3769	pReNative->Core.aidxGstRegShadows[idxGstReg] = idxRegNew;
3770	}
3771	}
3772
3773	pReNative->Core.aVars[idxVar].idxReg = (uint8_t)idxRegNew;
3774	pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows = 0;
3775	pReNative->Core.bmHstRegs = RT_BIT_32(idxRegNew) \| (pReNative->Core.bmHstRegs & ~RT_BIT_32(idxRegOld));
3776	return off;
3777	}
3778
3779
3780	/**
3781	* Moves a variable to a different register or spills it onto the stack.
3782	*
3783	* This must be a stack variable (kIemNativeVarKind_Stack) because the other
3784	* kinds can easily be recreated if needed later.
3785	*
3786	* @returns The new code buffer position.
3787	* @param pReNative The native recompile state.
3788	* @param off The current code buffer position.
3789	* @param idxVar The variable index.
3790	* @param fForbiddenRegs Mask of the forbidden registers. Defaults to
3791	* call-volatile registers.
3792	*/
3793	static uint32_t iemNativeRegMoveOrSpillStackVar(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVar,
3794	uint32_t fForbiddenRegs = IEMNATIVE_CALL_VOLATILE_GREG_MASK)
3795	{
3796	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
3797	Assert(pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack);
3798	Assert(!pReNative->Core.aVars[idxVar].fRegAcquired);
3799
3800	uint8_t const idxRegOld = pReNative->Core.aVars[idxVar].idxReg;
3801	Assert(idxRegOld < RT_ELEMENTS(pReNative->Core.aHstRegs));
3802	Assert(pReNative->Core.bmHstRegs & RT_BIT_32(idxRegOld));
3803	Assert(pReNative->Core.aHstRegs[idxRegOld].enmWhat == kIemNativeWhat_Var);
3804	Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows)
3805	== pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows);
3806	Assert(pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
3807	Assert( RT_BOOL(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxRegOld))
3808	== RT_BOOL(pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows));
3809
3810
3811	/** @todo Add statistics on this.*/
3812	/** @todo Implement basic variable liveness analysis (python) so variables
3813	* can be freed immediately once no longer used. This has the potential to
3814	* be trashing registers and stack for dead variables.
3815	* Update: This is mostly done. (Not IEMNATIVE_WITH_LIVENESS_ANALYSIS.) */
3816
3817	/*
3818	* First try move it to a different register, as that's cheaper.
3819	*/
3820	fForbiddenRegs \|= RT_BIT_32(idxRegOld);
3821	fForbiddenRegs \|= IEMNATIVE_REG_FIXED_MASK;
3822	uint32_t fRegs = ~pReNative->Core.bmHstRegs & ~fForbiddenRegs;
3823	if (fRegs)
3824	{
3825	/* Avoid using shadow registers, if possible. */
3826	if (fRegs & ~pReNative->Core.bmHstRegsWithGstShadow)
3827	fRegs &= ~pReNative->Core.bmHstRegsWithGstShadow;
3828	unsigned const idxRegNew = ASMBitFirstSetU32(fRegs) - 1;
3829	return iemNativeRegMoveVar(pReNative, off, idxVar, idxRegOld, idxRegNew, "iemNativeRegMoveOrSpillStackVar");
3830	}
3831
3832	/*
3833	* Otherwise we must spill the register onto the stack.
3834	*/
3835	uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxVar);
3836	Log12(("iemNativeRegMoveOrSpillStackVar: spilling idxVar=%d/idxReg=%d onto the stack (slot %#x bp+%d, off=%#x)\n",
3837	idxVar, idxRegOld, idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
3838	off = iemNativeEmitStoreGprByBp(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
3839
3840	pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
3841	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxRegOld);
3842	pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxRegOld);
3843	pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows;
3844	pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows = 0;
3845	return off;
3846	}
3847
3848
3849	/**
3850	* Allocates a temporary host general purpose register.
3851	*
3852	* This may emit code to save register content onto the stack in order to free
3853	* up a register.
3854	*
3855	* @returns The host register number; throws VBox status code on failure,
3856	* so no need to check the return value.
3857	* @param pReNative The native recompile state.
3858	* @param poff Pointer to the variable with the code buffer position.
3859	* This will be update if we need to move a variable from
3860	* register to stack in order to satisfy the request.
3861	* @param fPreferVolatile Whether to prefer volatile over non-volatile
3862	* registers (@c true, default) or the other way around
3863	* (@c false, for iemNativeRegAllocTmpForGuestReg()).
3864	*/
3865	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmp(PIEMRECOMPILERSTATE pReNative, uint32_t poff, bool fPreferVolatile /= true*/)
3866	{
3867	/*
3868	* Try find a completely unused register, preferably a call-volatile one.
3869	*/
3870	uint8_t idxReg;
3871	uint32_t fRegs = ~pReNative->Core.bmHstRegs
3872	& ~pReNative->Core.bmHstRegsWithGstShadow
3873	& (~IEMNATIVE_REG_FIXED_MASK & IEMNATIVE_HST_GREG_MASK);
3874	if (fRegs)
3875	{
3876	if (fPreferVolatile)
3877	idxReg = (uint8_t)ASMBitFirstSetU32( fRegs & IEMNATIVE_CALL_VOLATILE_GREG_MASK
3878	? fRegs & IEMNATIVE_CALL_VOLATILE_GREG_MASK : fRegs) - 1;
3879	else
3880	idxReg = (uint8_t)ASMBitFirstSetU32( fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK
3881	? fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK : fRegs) - 1;
3882	Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows == 0);
3883	Assert(!(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg)));
3884	Log12(("iemNativeRegAllocTmp: %s\n", g_apszIemNativeHstRegNames[idxReg]));
3885	}
3886	else
3887	{
3888	idxReg = iemNativeRegAllocFindFree(pReNative, poff, fPreferVolatile);
3889	AssertStmt(idxReg != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_ALLOCATOR_NO_FREE_TMP));
3890	Log12(("iemNativeRegAllocTmp: %s (slow)\n", g_apszIemNativeHstRegNames[idxReg]));
3891	}
3892	return iemNativeRegMarkAllocated(pReNative, idxReg, kIemNativeWhat_Tmp);
3893	}
3894
3895
3896	/**
3897	* Alternative version of iemNativeRegAllocTmp that takes mask with acceptable
3898	* registers.
3899	*
3900	* @returns The host register number; throws VBox status code on failure,
3901	* so no need to check the return value.
3902	* @param pReNative The native recompile state.
3903	* @param poff Pointer to the variable with the code buffer position.
3904	* This will be update if we need to move a variable from
3905	* register to stack in order to satisfy the request.
3906	* @param fRegMask Mask of acceptable registers.
3907	* @param fPreferVolatile Whether to prefer volatile over non-volatile
3908	* registers (@c true, default) or the other way around
3909	* (@c false, for iemNativeRegAllocTmpForGuestReg()).
3910	*/
3911	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpEx(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint32_t fRegMask,
3912	bool fPreferVolatile /= true/)
3913	{
3914	Assert(!(fRegMask & ~IEMNATIVE_HST_GREG_MASK));
3915	Assert(!(fRegMask & IEMNATIVE_REG_FIXED_MASK));
3916
3917	/*
3918	* Try find a completely unused register, preferably a call-volatile one.
3919	*/
3920	uint8_t idxReg;
3921	uint32_t fRegs = ~pReNative->Core.bmHstRegs
3922	& ~pReNative->Core.bmHstRegsWithGstShadow
3923	& (~IEMNATIVE_REG_FIXED_MASK & IEMNATIVE_HST_GREG_MASK)
3924	& fRegMask;
3925	if (fRegs)
3926	{
3927	if (fPreferVolatile)
3928	idxReg = (uint8_t)ASMBitFirstSetU32( fRegs & IEMNATIVE_CALL_VOLATILE_GREG_MASK
3929	? fRegs & IEMNATIVE_CALL_VOLATILE_GREG_MASK : fRegs) - 1;
3930	else
3931	idxReg = (uint8_t)ASMBitFirstSetU32( fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK
3932	? fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK : fRegs) - 1;
3933	Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows == 0);
3934	Assert(!(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg)));
3935	Log12(("iemNativeRegAllocTmpEx: %s\n", g_apszIemNativeHstRegNames[idxReg]));
3936	}
3937	else
3938	{
3939	idxReg = iemNativeRegAllocFindFree(pReNative, poff, fPreferVolatile, fRegMask);
3940	AssertStmt(idxReg != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_ALLOCATOR_NO_FREE_TMP));
3941	Log12(("iemNativeRegAllocTmpEx: %s (slow)\n", g_apszIemNativeHstRegNames[idxReg]));
3942	}
3943	return iemNativeRegMarkAllocated(pReNative, idxReg, kIemNativeWhat_Tmp);
3944	}
3945
3946
3947	/**
3948	* Allocates a temporary register for loading an immediate value into.
3949	*
3950	* This will emit code to load the immediate, unless there happens to be an
3951	* unused register with the value already loaded.
3952	*
3953	* The caller will not modify the returned register, it must be considered
3954	* read-only. Free using iemNativeRegFreeTmpImm.
3955	*
3956	* @returns The host register number; throws VBox status code on failure, so no
3957	* need to check the return value.
3958	* @param pReNative The native recompile state.
3959	* @param poff Pointer to the variable with the code buffer position.
3960	* @param uImm The immediate value that the register must hold upon
3961	* return.
3962	* @param fPreferVolatile Whether to prefer volatile over non-volatile
3963	* registers (@c true, default) or the other way around
3964	* (@c false).
3965	*
3966	* @note Reusing immediate values has not been implemented yet.
3967	*/
3968	DECL_HIDDEN_THROW(uint8_t)
3969	iemNativeRegAllocTmpImm(PIEMRECOMPILERSTATE pReNative, uint32_t poff, uint64_t uImm, bool fPreferVolatile /= true*/)
3970	{
3971	uint8_t const idxReg = iemNativeRegAllocTmp(pReNative, poff, fPreferVolatile);
3972	poff = iemNativeEmitLoadGprImm64(pReNative, poff, idxReg, uImm);
3973	return idxReg;
3974	}
3975
3976	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
3977
3978	# ifndef IEMLIVENESS_EXTENDED_LAYOUT
3979	/**
3980	* Helper for iemNativeLivenessGetStateByGstReg.
3981	*
3982	* @returns IEMLIVENESS_STATE_XXX
3983	* @param fMergedStateExp2 This is the RT_BIT_32() of each sub-state
3984	* ORed together.
3985	*/
3986	DECL_FORCE_INLINE(uint32_t)
3987	iemNativeLivenessMergeExpandedEFlagsState(uint32_t fMergedStateExp2)
3988	{
3989	/* INPUT trumps anything else. */
3990	if (fMergedStateExp2 & RT_BIT_32(IEMLIVENESS_STATE_INPUT))
3991	return IEMLIVENESS_STATE_INPUT;
3992
3993	/* CLOBBERED trumps XCPT_OR_CALL and UNUSED. */
3994	if (fMergedStateExp2 & RT_BIT_32(IEMLIVENESS_STATE_CLOBBERED))
3995	{
3996	/* If not all sub-fields are clobbered they must be considered INPUT. */
3997	if (fMergedStateExp2 & (RT_BIT_32(IEMLIVENESS_STATE_UNUSED) \| RT_BIT_32(IEMLIVENESS_STATE_XCPT_OR_CALL)))
3998	return IEMLIVENESS_STATE_INPUT;
3999	return IEMLIVENESS_STATE_CLOBBERED;
4000	}
4001
4002	/* XCPT_OR_CALL trumps UNUSED. */
4003	if (fMergedStateExp2 & RT_BIT_32(IEMLIVENESS_STATE_XCPT_OR_CALL))
4004	return IEMLIVENESS_STATE_XCPT_OR_CALL;
4005
4006	return IEMLIVENESS_STATE_UNUSED;
4007	}
4008	# endif /* !IEMLIVENESS_EXTENDED_LAYOUT */
4009
4010
4011	DECL_FORCE_INLINE(uint32_t)
4012	iemNativeLivenessGetStateByGstRegEx(PCIEMLIVENESSENTRY pLivenessEntry, unsigned enmGstRegEx)
4013	{
4014	# ifndef IEMLIVENESS_EXTENDED_LAYOUT
4015	return ((pLivenessEntry->Bit0.bm64 >> enmGstRegEx) & 1)
4016	\| (((pLivenessEntry->Bit1.bm64 >> enmGstRegEx) << 1) & 2);
4017	# else
4018	return ( (pLivenessEntry->Bit0.bm64 >> enmGstRegEx) & 1)
4019	\| (((pLivenessEntry->Bit1.bm64 >> enmGstRegEx) << 1) & 2)
4020	\| (((pLivenessEntry->Bit2.bm64 >> enmGstRegEx) << 2) & 4)
4021	\| (((pLivenessEntry->Bit3.bm64 >> enmGstRegEx) << 2) & 8);
4022	# endif
4023	}
4024
4025
4026	DECL_FORCE_INLINE(uint32_t)
4027	iemNativeLivenessGetStateByGstReg(PCIEMLIVENESSENTRY pLivenessEntry, IEMNATIVEGSTREG enmGstReg)
4028	{
4029	uint32_t uRet = iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, (unsigned)enmGstReg);
4030	if (enmGstReg == kIemNativeGstReg_EFlags)
4031	{
4032	/* Merge the eflags states to one. */
4033	# ifndef IEMLIVENESS_EXTENDED_LAYOUT
4034	uRet = RT_BIT_32(uRet);
4035	uRet \|= RT_BIT_32(pLivenessEntry->Bit0.fEflCf \| (pLivenessEntry->Bit1.fEflCf << 1));
4036	uRet \|= RT_BIT_32(pLivenessEntry->Bit0.fEflPf \| (pLivenessEntry->Bit1.fEflPf << 1));
4037	uRet \|= RT_BIT_32(pLivenessEntry->Bit0.fEflAf \| (pLivenessEntry->Bit1.fEflAf << 1));
4038	uRet \|= RT_BIT_32(pLivenessEntry->Bit0.fEflZf \| (pLivenessEntry->Bit1.fEflZf << 1));
4039	uRet \|= RT_BIT_32(pLivenessEntry->Bit0.fEflSf \| (pLivenessEntry->Bit1.fEflSf << 1));
4040	uRet \|= RT_BIT_32(pLivenessEntry->Bit0.fEflOf \| (pLivenessEntry->Bit1.fEflOf << 1));
4041	uRet = iemNativeLivenessMergeExpandedEFlagsState(uRet);
4042	# else
4043	AssertCompile(IEMLIVENESSBIT_IDX_EFL_OTHER == (unsigned)kIemNativeGstReg_EFlags);
4044	uRet \|= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_CF);
4045	uRet \|= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_PF);
4046	uRet \|= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_AF);
4047	uRet \|= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_ZF);
4048	uRet \|= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_SF);
4049	uRet \|= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_OF);
4050	# endif
4051	}
4052	return uRet;
4053	}
4054
4055
4056	# ifdef VBOX_STRICT
4057	/** For assertions only, user checks that idxCurCall isn't zerow. */
4058	DECL_FORCE_INLINE(uint32_t)
4059	iemNativeLivenessGetPrevStateByGstReg(PIEMRECOMPILERSTATE pReNative, IEMNATIVEGSTREG enmGstReg)
4060	{
4061	return iemNativeLivenessGetStateByGstReg(&pReNative->paLivenessEntries[pReNative->idxCurCall - 1], enmGstReg);
4062	}
4063	# endif /* VBOX_STRICT */
4064
4065	#endif /* IEMNATIVE_WITH_LIVENESS_ANALYSIS */
4066
4067	/**
4068	* Marks host register @a idxHstReg as containing a shadow copy of guest
4069	* register @a enmGstReg.
4070	*
4071	* ASSUMES that caller has made sure @a enmGstReg is not associated with any
4072	* host register before calling.
4073	*/
4074	DECL_FORCE_INLINE(void)
4075	iemNativeRegMarkAsGstRegShadow(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, IEMNATIVEGSTREG enmGstReg, uint32_t off)
4076	{
4077	Assert(!(pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg)));
4078	Assert(!pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows);
4079	Assert((unsigned)enmGstReg < (unsigned)kIemNativeGstReg_End);
4080
4081	pReNative->Core.aidxGstRegShadows[enmGstReg] = idxHstReg;
4082	pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = RT_BIT_64(enmGstReg); /** @todo why? not OR? */
4083	pReNative->Core.bmGstRegShadows \|= RT_BIT_64(enmGstReg);
4084	pReNative->Core.bmHstRegsWithGstShadow \|= RT_BIT_32(idxHstReg);
4085	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
4086	iemNativeDbgInfoAddNativeOffset(pReNative, off);
4087	iemNativeDbgInfoAddGuestRegShadowing(pReNative, enmGstReg, idxHstReg);
4088	#else
4089	RT_NOREF(off);
4090	#endif
4091	}
4092
4093
4094	/**
4095	* Clear any guest register shadow claims from @a idxHstReg.
4096	*
4097	* The register does not need to be shadowing any guest registers.
4098	*/
4099	DECL_FORCE_INLINE(void)
4100	iemNativeRegClearGstRegShadowing(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, uint32_t off)
4101	{
4102	Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows)
4103	== pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows
4104	&& pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
4105	Assert( RT_BOOL(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxHstReg))
4106	== RT_BOOL(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows));
4107
4108	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
4109	uint64_t fGstRegs = pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
4110	if (fGstRegs)
4111	{
4112	Assert(fGstRegs < RT_BIT_64(kIemNativeGstReg_End));
4113	iemNativeDbgInfoAddNativeOffset(pReNative, off);
4114	while (fGstRegs)
4115	{
4116	unsigned const iGstReg = ASMBitFirstSetU64(fGstRegs) - 1;
4117	fGstRegs &= ~RT_BIT_64(iGstReg);
4118	iemNativeDbgInfoAddGuestRegShadowing(pReNative, (IEMNATIVEGSTREG)iGstReg, UINT8_MAX, idxHstReg);
4119	}
4120	}
4121	#else
4122	RT_NOREF(off);
4123	#endif
4124
4125	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
4126	pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
4127	pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = 0;
4128	}
4129
4130
4131	/**
4132	* Clear guest register shadow claim regarding @a enmGstReg from @a idxHstReg
4133	* and global overview flags.
4134	*/
4135	DECL_FORCE_INLINE(void)
4136	iemNativeRegClearGstRegShadowingOne(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, IEMNATIVEGSTREG enmGstReg, uint32_t off)
4137	{
4138	Assert(pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
4139	Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows)
4140	== pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows
4141	&& pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
4142	Assert(pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg));
4143	Assert(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & RT_BIT_64(enmGstReg));
4144	Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxHstReg));
4145
4146	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
4147	iemNativeDbgInfoAddNativeOffset(pReNative, off);
4148	iemNativeDbgInfoAddGuestRegShadowing(pReNative, enmGstReg, UINT8_MAX, idxHstReg);
4149	#else
4150	RT_NOREF(off);
4151	#endif
4152
4153	uint64_t const fGstRegShadowsNew = pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & ~RT_BIT_64(enmGstReg);
4154	pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = fGstRegShadowsNew;
4155	if (!fGstRegShadowsNew)
4156	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
4157	pReNative->Core.bmGstRegShadows &= ~RT_BIT_64(enmGstReg);
4158	}
4159
4160
4161	#if 0 /* unused */
4162	/**
4163	* Clear any guest register shadow claim for @a enmGstReg.
4164	*/
4165	DECL_FORCE_INLINE(void)
4166	iemNativeRegClearGstRegShadowingByGstReg(PIEMRECOMPILERSTATE pReNative, IEMNATIVEGSTREG enmGstReg, uint32_t off)
4167	{
4168	Assert(pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
4169	if (pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg))
4170	{
4171	Assert(pReNative->Core.aidxGstRegShadows[enmGstReg] < RT_ELEMENTS(pReNative->Core.aHstRegs));
4172	iemNativeRegClearGstRegShadowingOne(pReNative, pReNative->Core.aidxGstRegShadows[enmGstReg], enmGstReg, off);
4173	}
4174	}
4175	#endif
4176
4177
4178	/**
4179	* Clear any guest register shadow claim for @a enmGstReg and mark @a idxHstRegNew
4180	* as the new shadow of it.
4181	*
4182	* Unlike the other guest reg shadow helpers, this does the logging for you.
4183	* However, it is the liveness state is not asserted here, the caller must do
4184	* that.
4185	*/
4186	DECL_FORCE_INLINE(void)
4187	iemNativeRegClearAndMarkAsGstRegShadow(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstRegNew,
4188	IEMNATIVEGSTREG enmGstReg, uint32_t off)
4189	{
4190	Assert(pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
4191	if (pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg))
4192	{
4193	uint8_t const idxHstRegOld = pReNative->Core.aidxGstRegShadows[enmGstReg];
4194	Assert(idxHstRegOld < RT_ELEMENTS(pReNative->Core.aHstRegs));
4195	if (idxHstRegOld == idxHstRegNew)
4196	return;
4197	Log12(("iemNativeRegClearAndMarkAsGstRegShadow: %s for guest %s (from %s)\n", g_apszIemNativeHstRegNames[idxHstRegNew],
4198	g_aGstShadowInfo[enmGstReg].pszName, g_apszIemNativeHstRegNames[idxHstRegOld]));
4199	iemNativeRegClearGstRegShadowingOne(pReNative, pReNative->Core.aidxGstRegShadows[enmGstReg], enmGstReg, off);
4200	}
4201	else
4202	Log12(("iemNativeRegClearAndMarkAsGstRegShadow: %s for guest %s\n", g_apszIemNativeHstRegNames[idxHstRegNew],
4203	g_aGstShadowInfo[enmGstReg].pszName));
4204	iemNativeRegMarkAsGstRegShadow(pReNative, idxHstRegNew, enmGstReg, off);
4205	}
4206
4207
4208	/**
4209	* Transfers the guest register shadow claims of @a enmGstReg from @a idxRegFrom
4210	* to @a idxRegTo.
4211	*/
4212	DECL_FORCE_INLINE(void)
4213	iemNativeRegTransferGstRegShadowing(PIEMRECOMPILERSTATE pReNative, uint8_t idxRegFrom, uint8_t idxRegTo,
4214	IEMNATIVEGSTREG enmGstReg, uint32_t off)
4215	{
4216	Assert(pReNative->Core.aHstRegs[idxRegFrom].fGstRegShadows & RT_BIT_64(enmGstReg));
4217	Assert(pReNative->Core.aidxGstRegShadows[enmGstReg] == idxRegFrom);
4218	Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxRegFrom].fGstRegShadows)
4219	== pReNative->Core.aHstRegs[idxRegFrom].fGstRegShadows
4220	&& pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
4221	Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxRegTo].fGstRegShadows)
4222	== pReNative->Core.aHstRegs[idxRegTo].fGstRegShadows);
4223	Assert( RT_BOOL(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxRegFrom))
4224	== RT_BOOL(pReNative->Core.aHstRegs[idxRegFrom].fGstRegShadows));
4225
4226	uint64_t const fGstRegShadowsFrom = pReNative->Core.aHstRegs[idxRegFrom].fGstRegShadows & ~RT_BIT_64(enmGstReg);
4227	pReNative->Core.aHstRegs[idxRegFrom].fGstRegShadows = fGstRegShadowsFrom;
4228	if (!fGstRegShadowsFrom)
4229	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxRegFrom);
4230	pReNative->Core.bmHstRegsWithGstShadow \|= RT_BIT_32(idxRegTo);
4231	pReNative->Core.aHstRegs[idxRegTo].fGstRegShadows \|= RT_BIT_64(enmGstReg);
4232	pReNative->Core.aidxGstRegShadows[enmGstReg] = idxRegTo;
4233	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
4234	iemNativeDbgInfoAddNativeOffset(pReNative, off);
4235	iemNativeDbgInfoAddGuestRegShadowing(pReNative, enmGstReg, idxRegTo, idxRegFrom);
4236	#else
4237	RT_NOREF(off);
4238	#endif
4239	}
4240
4241
4242	/**
4243	* Allocates a temporary host general purpose register for keeping a guest
4244	* register value.
4245	*
4246	* Since we may already have a register holding the guest register value,
4247	* code will be emitted to do the loading if that's not the case. Code may also
4248	* be emitted if we have to free up a register to satify the request.
4249	*
4250	* @returns The host register number; throws VBox status code on failure, so no
4251	* need to check the return value.
4252	* @param pReNative The native recompile state.
4253	* @param poff Pointer to the variable with the code buffer
4254	* position. This will be update if we need to move a
4255	* variable from register to stack in order to satisfy
4256	* the request.
4257	* @param enmGstReg The guest register that will is to be updated.
4258	* @param enmIntendedUse How the caller will be using the host register.
4259	* @param fNoVolatileRegs Set if no volatile register allowed, clear if any
4260	* register is okay (default). The ASSUMPTION here is
4261	* that the caller has already flushed all volatile
4262	* registers, so this is only applied if we allocate a
4263	* new register.
4264	* @param fSkipLivenessAssert Hack for liveness input validation of EFLAGS.
4265	* @sa iemNativeRegAllocTmpForGuestRegIfAlreadyPresent
4266	*/
4267	DECL_HIDDEN_THROW(uint8_t)
4268	iemNativeRegAllocTmpForGuestReg(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, IEMNATIVEGSTREG enmGstReg,
4269	IEMNATIVEGSTREGUSE enmIntendedUse /= kIemNativeGstRegUse_ReadOnly/,
4270	bool fNoVolatileRegs /= false/, bool fSkipLivenessAssert /= false/)
4271	{
4272	Assert(enmGstReg < kIemNativeGstReg_End && g_aGstShadowInfo[enmGstReg].cb != 0);
4273	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
4274	AssertMsg( fSkipLivenessAssert
4275	\|\| pReNative->idxCurCall == 0
4276	\|\| enmGstReg == kIemNativeGstReg_Pc
4277	\|\| (enmIntendedUse == kIemNativeGstRegUse_ForFullWrite
4278	? IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg))
4279	: enmIntendedUse == kIemNativeGstRegUse_ForUpdate
4280	? IEMLIVENESS_STATE_IS_MODIFY_EXPECTED( iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg))
4281	: IEMLIVENESS_STATE_IS_INPUT_EXPECTED( iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg)) ),
4282	("%s - %u\n", g_aGstShadowInfo[enmGstReg].pszName, iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg)));
4283	#endif
4284	RT_NOREF(fSkipLivenessAssert);
4285	#if defined(LOG_ENABLED) \|\| defined(VBOX_STRICT)
4286	static const char * const s_pszIntendedUse[] = { "fetch", "update", "full write", "destructive calc" };
4287	#endif
4288	uint32_t const fRegMask = !fNoVolatileRegs
4289	? IEMNATIVE_HST_GREG_MASK & ~IEMNATIVE_REG_FIXED_MASK
4290	: IEMNATIVE_HST_GREG_MASK & ~IEMNATIVE_REG_FIXED_MASK & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK;
4291
4292	/*
4293	* First check if the guest register value is already in a host register.
4294	*/
4295	if (pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg))
4296	{
4297	uint8_t idxReg = pReNative->Core.aidxGstRegShadows[enmGstReg];
4298	Assert(idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs));
4299	Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows & RT_BIT_64(enmGstReg));
4300	Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg));
4301
4302	/* It's not supposed to be allocated... */
4303	if (!(pReNative->Core.bmHstRegs & RT_BIT_32(idxReg)))
4304	{
4305	/*
4306	* If the register will trash the guest shadow copy, try find a
4307	* completely unused register we can use instead. If that fails,
4308	* we need to disassociate the host reg from the guest reg.
4309	*/
4310	/** @todo would be nice to know if preserving the register is in any way helpful. */
4311	/* If the purpose is calculations, try duplicate the register value as
4312	we'll be clobbering the shadow. */
4313	if ( enmIntendedUse == kIemNativeGstRegUse_Calculation
4314	&& ( ~pReNative->Core.bmHstRegs
4315	& ~pReNative->Core.bmHstRegsWithGstShadow
4316	& (~IEMNATIVE_REG_FIXED_MASK & IEMNATIVE_HST_GREG_MASK)))
4317	{
4318	uint8_t const idxRegNew = iemNativeRegAllocTmpEx(pReNative, poff, fRegMask);
4319
4320	poff = iemNativeEmitLoadGprFromGpr(pReNative, poff, idxRegNew, idxReg);
4321
4322	Log12(("iemNativeRegAllocTmpForGuestReg: Duplicated %s for guest %s into %s for destructive calc\n",
4323	g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName,
4324	g_apszIemNativeHstRegNames[idxRegNew]));
4325	idxReg = idxRegNew;
4326	}
4327	/* If the current register matches the restrictions, go ahead and allocate
4328	it for the caller. */
4329	else if (fRegMask & RT_BIT_32(idxReg))
4330	{
4331	pReNative->Core.bmHstRegs \|= RT_BIT_32(idxReg);
4332	pReNative->Core.aHstRegs[idxReg].enmWhat = kIemNativeWhat_Tmp;
4333	pReNative->Core.aHstRegs[idxReg].idxVar = UINT8_MAX;
4334	if (enmIntendedUse != kIemNativeGstRegUse_Calculation)
4335	Log12(("iemNativeRegAllocTmpForGuestReg: Reusing %s for guest %s %s\n",
4336	g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName, s_pszIntendedUse[enmIntendedUse]));
4337	else
4338	{
4339	iemNativeRegClearGstRegShadowing(pReNative, idxReg, *poff);
4340	Log12(("iemNativeRegAllocTmpForGuestReg: Grabbing %s for guest %s - destructive calc\n",
4341	g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName));
4342	}
4343	}
4344	/* Otherwise, allocate a register that satisfies the caller and transfer
4345	the shadowing if compatible with the intended use. (This basically
4346	means the call wants a non-volatile register (RSP push/pop scenario).) */
4347	else
4348	{
4349	Assert(fNoVolatileRegs);
4350	uint8_t const idxRegNew = iemNativeRegAllocTmpEx(pReNative, poff, fRegMask & ~RT_BIT_32(idxReg),
4351	!fNoVolatileRegs
4352	&& enmIntendedUse == kIemNativeGstRegUse_Calculation);
4353	poff = iemNativeEmitLoadGprFromGpr(pReNative, poff, idxRegNew, idxReg);
4354	if (enmIntendedUse != kIemNativeGstRegUse_Calculation)
4355	{
4356	iemNativeRegTransferGstRegShadowing(pReNative, idxReg, idxRegNew, enmGstReg, *poff);
4357	Log12(("iemNativeRegAllocTmpForGuestReg: Transfering %s to %s for guest %s %s\n",
4358	g_apszIemNativeHstRegNames[idxReg], g_apszIemNativeHstRegNames[idxRegNew],
4359	g_aGstShadowInfo[enmGstReg].pszName, s_pszIntendedUse[enmIntendedUse]));
4360	}
4361	else
4362	Log12(("iemNativeRegAllocTmpForGuestReg: Duplicated %s for guest %s into %s for destructive calc\n",
4363	g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName,
4364	g_apszIemNativeHstRegNames[idxRegNew]));
4365	idxReg = idxRegNew;
4366	}
4367	}
4368	else
4369	{
4370	/*
4371	* Oops. Shadowed guest register already allocated!
4372	*
4373	* Allocate a new register, copy the value and, if updating, the
4374	* guest shadow copy assignment to the new register.
4375	*/
4376	AssertMsg( enmIntendedUse != kIemNativeGstRegUse_ForUpdate
4377	&& enmIntendedUse != kIemNativeGstRegUse_ForFullWrite,
4378	("This shouldn't happen: idxReg=%d enmGstReg=%d enmIntendedUse=%s\n",
4379	idxReg, enmGstReg, s_pszIntendedUse[enmIntendedUse]));
4380
4381	/** @todo share register for readonly access. */
4382	uint8_t const idxRegNew = iemNativeRegAllocTmpEx(pReNative, poff, fRegMask,
4383	enmIntendedUse == kIemNativeGstRegUse_Calculation);
4384
4385	if (enmIntendedUse != kIemNativeGstRegUse_ForFullWrite)
4386	poff = iemNativeEmitLoadGprFromGpr(pReNative, poff, idxRegNew, idxReg);
4387
4388	if ( enmIntendedUse != kIemNativeGstRegUse_ForUpdate
4389	&& enmIntendedUse != kIemNativeGstRegUse_ForFullWrite)
4390	Log12(("iemNativeRegAllocTmpForGuestReg: Duplicated %s for guest %s into %s for %s\n",
4391	g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName,
4392	g_apszIemNativeHstRegNames[idxRegNew], s_pszIntendedUse[enmIntendedUse]));
4393	else
4394	{
4395	iemNativeRegTransferGstRegShadowing(pReNative, idxReg, idxRegNew, enmGstReg, *poff);
4396	Log12(("iemNativeRegAllocTmpForGuestReg: Moved %s for guest %s into %s for %s\n",
4397	g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName,
4398	g_apszIemNativeHstRegNames[idxRegNew], s_pszIntendedUse[enmIntendedUse]));
4399	}
4400	idxReg = idxRegNew;
4401	}
4402	Assert(RT_BIT_32(idxReg) & fRegMask); /* See assumption in fNoVolatileRegs docs. */
4403
4404	#ifdef VBOX_STRICT
4405	/* Strict builds: Check that the value is correct. */
4406	poff = iemNativeEmitGuestRegValueCheck(pReNative, poff, idxReg, enmGstReg);
4407	#endif
4408
4409	return idxReg;
4410	}
4411
4412	/*
4413	* Allocate a new register, load it with the guest value and designate it as a copy of the
4414	*/
4415	uint8_t const idxRegNew = iemNativeRegAllocTmpEx(pReNative, poff, fRegMask, enmIntendedUse == kIemNativeGstRegUse_Calculation);
4416
4417	if (enmIntendedUse != kIemNativeGstRegUse_ForFullWrite)
4418	poff = iemNativeEmitLoadGprWithGstShadowReg(pReNative, poff, idxRegNew, enmGstReg);
4419
4420	if (enmIntendedUse != kIemNativeGstRegUse_Calculation)
4421	iemNativeRegMarkAsGstRegShadow(pReNative, idxRegNew, enmGstReg, *poff);
4422	Log12(("iemNativeRegAllocTmpForGuestReg: Allocated %s for guest %s %s\n",
4423	g_apszIemNativeHstRegNames[idxRegNew], g_aGstShadowInfo[enmGstReg].pszName, s_pszIntendedUse[enmIntendedUse]));
4424
4425	return idxRegNew;
4426	}
4427
4428
4429	/**
4430	* Allocates a temporary host general purpose register that already holds the
4431	* given guest register value.
4432	*
4433	* The use case for this function is places where the shadowing state cannot be
4434	* modified due to branching and such. This will fail if the we don't have a
4435	* current shadow copy handy or if it's incompatible. The only code that will
4436	* be emitted here is value checking code in strict builds.
4437	*
4438	* The intended use can only be readonly!
4439	*
4440	* @returns The host register number, UINT8_MAX if not present.
4441	* @param pReNative The native recompile state.
4442	* @param poff Pointer to the instruction buffer offset.
4443	* Will be updated in strict builds if a register is
4444	* found.
4445	* @param enmGstReg The guest register that will is to be updated.
4446	* @note In strict builds, this may throw instruction buffer growth failures.
4447	* Non-strict builds will not throw anything.
4448	* @sa iemNativeRegAllocTmpForGuestReg
4449	*/
4450	DECL_HIDDEN_THROW(uint8_t)
4451	iemNativeRegAllocTmpForGuestRegIfAlreadyPresent(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, IEMNATIVEGSTREG enmGstReg)
4452	{
4453	Assert(enmGstReg < kIemNativeGstReg_End && g_aGstShadowInfo[enmGstReg].cb != 0);
4454	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
4455	AssertMsg( pReNative->idxCurCall == 0
4456	\|\| IEMLIVENESS_STATE_IS_INPUT_EXPECTED(iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg))
4457	\|\| enmGstReg == kIemNativeGstReg_Pc,
4458	("%s - %u\n", g_aGstShadowInfo[enmGstReg].pszName, iemNativeLivenessGetPrevStateByGstReg(pReNative, enmGstReg)));
4459	#endif
4460
4461	/*
4462	* First check if the guest register value is already in a host register.
4463	*/
4464	if (pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg))
4465	{
4466	uint8_t idxReg = pReNative->Core.aidxGstRegShadows[enmGstReg];
4467	Assert(idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs));
4468	Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows & RT_BIT_64(enmGstReg));
4469	Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg));
4470
4471	if (!(pReNative->Core.bmHstRegs & RT_BIT_32(idxReg)))
4472	{
4473	/*
4474	* We only do readonly use here, so easy compared to the other
4475	* variant of this code.
4476	*/
4477	pReNative->Core.bmHstRegs \|= RT_BIT_32(idxReg);
4478	pReNative->Core.aHstRegs[idxReg].enmWhat = kIemNativeWhat_Tmp;
4479	pReNative->Core.aHstRegs[idxReg].idxVar = UINT8_MAX;
4480	Log12(("iemNativeRegAllocTmpForGuestRegIfAlreadyPresent: Reusing %s for guest %s readonly\n",
4481	g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName));
4482
4483	#ifdef VBOX_STRICT
4484	/* Strict builds: Check that the value is correct. */
4485	poff = iemNativeEmitGuestRegValueCheck(pReNative, poff, idxReg, enmGstReg);
4486	#else
4487	RT_NOREF(poff);
4488	#endif
4489	return idxReg;
4490	}
4491	}
4492
4493	return UINT8_MAX;
4494	}
4495
4496
4497	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocVar(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint8_t idxVar);
4498
4499
4500	/**
4501	* Allocates argument registers for a function call.
4502	*
4503	* @returns New code buffer offset on success; throws VBox status code on failure, so no
4504	* need to check the return value.
4505	* @param pReNative The native recompile state.
4506	* @param off The current code buffer offset.
4507	* @param cArgs The number of arguments the function call takes.
4508	*/
4509	DECL_HIDDEN_THROW(uint32_t) iemNativeRegAllocArgs(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs)
4510	{
4511	AssertStmt(cArgs <= IEMNATIVE_CALL_ARG_GREG_COUNT + IEMNATIVE_FRAME_STACK_ARG_COUNT,
4512	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_4));
4513	Assert(RT_ELEMENTS(g_aidxIemNativeCallRegs) == IEMNATIVE_CALL_ARG_GREG_COUNT);
4514	Assert(RT_ELEMENTS(g_afIemNativeCallRegs) == IEMNATIVE_CALL_ARG_GREG_COUNT);
4515
4516	if (cArgs > RT_ELEMENTS(g_aidxIemNativeCallRegs))
4517	cArgs = RT_ELEMENTS(g_aidxIemNativeCallRegs);
4518	else if (cArgs == 0)
4519	return true;
4520
4521	/*
4522	* Do we get luck and all register are free and not shadowing anything?
4523	*/
4524	if (((pReNative->Core.bmHstRegs \| pReNative->Core.bmHstRegsWithGstShadow) & g_afIemNativeCallRegs[cArgs]) == 0)
4525	for (uint32_t i = 0; i < cArgs; i++)
4526	{
4527	uint8_t const idxReg = g_aidxIemNativeCallRegs[i];
4528	pReNative->Core.aHstRegs[idxReg].enmWhat = kIemNativeWhat_Arg;
4529	pReNative->Core.aHstRegs[idxReg].idxVar = UINT8_MAX;
4530	Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows == 0);
4531	}
4532	/*
4533	* Okay, not lucky so we have to free up the registers.
4534	*/
4535	else
4536	for (uint32_t i = 0; i < cArgs; i++)
4537	{
4538	uint8_t const idxReg = g_aidxIemNativeCallRegs[i];
4539	if (pReNative->Core.bmHstRegs & RT_BIT_32(idxReg))
4540	{
4541	switch (pReNative->Core.aHstRegs[idxReg].enmWhat)
4542	{
4543	case kIemNativeWhat_Var:
4544	{
4545	uint8_t const idxVar = pReNative->Core.aHstRegs[idxReg].idxVar;
4546	AssertStmt(idxVar < RT_ELEMENTS(pReNative->Core.aVars),
4547	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_5));
4548	Assert(pReNative->Core.aVars[idxVar].idxReg == idxReg);
4549	Assert(pReNative->Core.bmVars & RT_BIT_32(idxVar));
4550
4551	if (pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_Stack)
4552	pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
4553	else
4554	{
4555	off = iemNativeRegMoveOrSpillStackVar(pReNative, off, idxVar);
4556	Assert(!(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg)));
4557	}
4558	break;
4559	}
4560
4561	case kIemNativeWhat_Tmp:
4562	case kIemNativeWhat_Arg:
4563	case kIemNativeWhat_rc:
4564	AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_5));
4565	default:
4566	AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_6));
4567	}
4568
4569	}
4570	if (pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg))
4571	{
4572	Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows != 0);
4573	Assert( (pReNative->Core.aHstRegs[idxReg].fGstRegShadows & pReNative->Core.bmGstRegShadows)
4574	== pReNative->Core.aHstRegs[idxReg].fGstRegShadows);
4575	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxReg);
4576	pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
4577	pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
4578	}
4579	else
4580	Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows == 0);
4581	pReNative->Core.aHstRegs[idxReg].enmWhat = kIemNativeWhat_Arg;
4582	pReNative->Core.aHstRegs[idxReg].idxVar = UINT8_MAX;
4583	}
4584	pReNative->Core.bmHstRegs \|= g_afIemNativeCallRegs[cArgs];
4585	return true;
4586	}
4587
4588
4589	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAssignRc(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg);
4590
4591
4592	#if 0
4593	/**
4594	* Frees a register assignment of any type.
4595	*
4596	* @param pReNative The native recompile state.
4597	* @param idxHstReg The register to free.
4598	*
4599	* @note Does not update variables.
4600	*/
4601	DECLHIDDEN(void) iemNativeRegFree(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT
4602	{
4603	Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aHstRegs));
4604	Assert(pReNative->Core.bmHstRegs & RT_BIT_32(idxHstReg));
4605	Assert(!(IEMNATIVE_REG_FIXED_MASK & RT_BIT_32(idxHstReg)));
4606	Assert( pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Var
4607	\|\| pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Tmp
4608	\|\| pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Arg
4609	\|\| pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_rc);
4610	Assert( pReNative->Core.aHstRegs[idxHstReg].enmWhat != kIemNativeWhat_Var
4611	\|\| pReNative->Core.aVars[pReNative->Core.aHstRegs[idxHstReg].idxVar].idxReg == UINT8_MAX
4612	\|\| (pReNative->Core.bmVars & RT_BIT_32(pReNative->Core.aHstRegs[idxHstReg].idxVar)));
4613	Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows)
4614	== pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows);
4615	Assert( RT_BOOL(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxHstReg))
4616	== RT_BOOL(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows));
4617
4618	pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
4619	/* no flushing, right:
4620	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
4621	pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
4622	pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = 0;
4623	*/
4624	}
4625	#endif
4626
4627
4628	/**
4629	* Frees a temporary register.
4630	*
4631	* Any shadow copies of guest registers assigned to the host register will not
4632	* be flushed by this operation.
4633	*/
4634	DECLHIDDEN(void) iemNativeRegFreeTmp(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT
4635	{
4636	Assert(pReNative->Core.bmHstRegs & RT_BIT_32(idxHstReg));
4637	Assert(pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Tmp);
4638	pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
4639	Log12(("iemNativeRegFreeTmp: %s (gst: %#RX64)\n",
4640	g_apszIemNativeHstRegNames[idxHstReg], pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows));
4641	}
4642
4643
4644	/**
4645	* Frees a temporary immediate register.
4646	*
4647	* It is assumed that the call has not modified the register, so it still hold
4648	* the same value as when it was allocated via iemNativeRegAllocTmpImm().
4649	*/
4650	DECLHIDDEN(void) iemNativeRegFreeTmpImm(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT
4651	{
4652	iemNativeRegFreeTmp(pReNative, idxHstReg);
4653	}
4654
4655
4656	/**
4657	* Frees a register assigned to a variable.
4658	*
4659	* The register will be disassociated from the variable.
4660	*/
4661	DECLHIDDEN(void) iemNativeRegFreeVar(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, bool fFlushShadows) RT_NOEXCEPT
4662	{
4663	Assert(pReNative->Core.bmHstRegs & RT_BIT_32(idxHstReg));
4664	Assert(pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Var);
4665	uint8_t const idxVar = pReNative->Core.aHstRegs[idxHstReg].idxVar;
4666	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
4667	Assert(pReNative->Core.aVars[idxVar].idxReg == idxHstReg);
4668
4669	pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
4670	pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
4671	if (!fFlushShadows)
4672	Log12(("iemNativeRegFreeVar: %s (gst: %#RX64) idxVar=%d\n",
4673	g_apszIemNativeHstRegNames[idxHstReg], pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows, idxVar));
4674	else
4675	{
4676	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
4677	uint64_t const fGstRegShadowsOld = pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
4678	pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = 0;
4679	pReNative->Core.bmGstRegShadows &= ~fGstRegShadowsOld;
4680	uint64_t fGstRegShadows = fGstRegShadowsOld;
4681	while (fGstRegShadows)
4682	{
4683	unsigned const idxGstReg = ASMBitFirstSetU64(fGstRegShadows) - 1;
4684	fGstRegShadows &= ~RT_BIT_64(idxGstReg);
4685
4686	Assert(pReNative->Core.aidxGstRegShadows[idxGstReg] == idxHstReg);
4687	pReNative->Core.aidxGstRegShadows[idxGstReg] = UINT8_MAX;
4688	}
4689	Log12(("iemNativeRegFreeVar: %s (gst: %#RX64 -> 0) idxVar=%d\n",
4690	g_apszIemNativeHstRegNames[idxHstReg], fGstRegShadowsOld, idxVar));
4691	}
4692	}
4693
4694
4695	/**
4696	* Called right before emitting a call instruction to move anything important
4697	* out of call-volatile registers, free and flush the call-volatile registers,
4698	* optionally freeing argument variables.
4699	*
4700	* @returns New code buffer offset, UINT32_MAX on failure.
4701	* @param pReNative The native recompile state.
4702	* @param off The code buffer offset.
4703	* @param cArgs The number of arguments the function call takes.
4704	* It is presumed that the host register part of these have
4705	* been allocated as such already and won't need moving,
4706	* just freeing.
4707	* @param fKeepVars Mask of variables that should keep their register
4708	* assignments. Caller must take care to handle these.
4709	*/
4710	DECL_HIDDEN_THROW(uint32_t)
4711	iemNativeRegMoveAndFreeAndFlushAtCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs, uint32_t fKeepVars /= 0/)
4712	{
4713	Assert(cArgs <= IEMNATIVE_CALL_MAX_ARG_COUNT);
4714
4715	/* fKeepVars will reduce this mask. */
4716	uint32_t fRegsToFree = IEMNATIVE_CALL_VOLATILE_GREG_MASK;
4717
4718	/*
4719	* Move anything important out of volatile registers.
4720	*/
4721	if (cArgs > RT_ELEMENTS(g_aidxIemNativeCallRegs))
4722	cArgs = RT_ELEMENTS(g_aidxIemNativeCallRegs);
4723	uint32_t fRegsToMove = IEMNATIVE_CALL_VOLATILE_GREG_MASK
4724	#ifdef IEMNATIVE_REG_FIXED_TMP0
4725	& ~RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0)
4726	#endif
4727	& ~g_afIemNativeCallRegs[cArgs];
4728
4729	fRegsToMove &= pReNative->Core.bmHstRegs;
4730	if (!fRegsToMove)
4731	{ /* likely */ }
4732	else
4733	{
4734	Log12(("iemNativeRegMoveAndFreeAndFlushAtCall: fRegsToMove=%#x\n", fRegsToMove));
4735	while (fRegsToMove != 0)
4736	{
4737	unsigned const idxReg = ASMBitFirstSetU32(fRegsToMove) - 1;
4738	fRegsToMove &= ~RT_BIT_32(idxReg);
4739
4740	switch (pReNative->Core.aHstRegs[idxReg].enmWhat)
4741	{
4742	case kIemNativeWhat_Var:
4743	{
4744	uint8_t const idxVar = pReNative->Core.aHstRegs[idxReg].idxVar;
4745	Assert(idxVar < RT_ELEMENTS(pReNative->Core.aVars));
4746	Assert(pReNative->Core.bmVars & RT_BIT_32(idxVar));
4747	Assert(pReNative->Core.aVars[idxVar].idxReg == idxReg);
4748	if (!(RT_BIT_32(idxVar) & fKeepVars))
4749	{
4750	Log12(("iemNativeRegMoveAndFreeAndFlushAtCall: idxVar=%d enmKind=%d idxReg=%d\n",
4751	idxVar, pReNative->Core.aVars[idxVar].enmKind, pReNative->Core.aVars[idxVar].idxReg));
4752	if (pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_Stack)
4753	pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
4754	else
4755	off = iemNativeRegMoveOrSpillStackVar(pReNative, off, idxVar);
4756	}
4757	else
4758	fRegsToFree &= ~RT_BIT_32(idxReg);
4759	continue;
4760	}
4761
4762	case kIemNativeWhat_Arg:
4763	AssertMsgFailed(("What?!?: %u\n", idxReg));
4764	continue;
4765
4766	case kIemNativeWhat_rc:
4767	case kIemNativeWhat_Tmp:
4768	AssertMsgFailed(("Missing free: %u\n", idxReg));
4769	continue;
4770
4771	case kIemNativeWhat_FixedTmp:
4772	case kIemNativeWhat_pVCpuFixed:
4773	case kIemNativeWhat_pCtxFixed:
4774	case kIemNativeWhat_FixedReserved:
4775	case kIemNativeWhat_Invalid:
4776	case kIemNativeWhat_End:
4777	AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_1));
4778	}
4779	AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_2));
4780	}
4781	}
4782
4783	/*
4784	* Do the actual freeing.
4785	*/
4786	if (pReNative->Core.bmHstRegs & fRegsToFree)
4787	Log12(("iemNativeRegMoveAndFreeAndFlushAtCall: bmHstRegs %#x -> %#x\n",
4788	pReNative->Core.bmHstRegs, pReNative->Core.bmHstRegs & ~fRegsToFree));
4789	pReNative->Core.bmHstRegs &= ~fRegsToFree;
4790
4791	/* If there are guest register shadows in any call-volatile register, we
4792	have to clear the corrsponding guest register masks for each register. */
4793	uint32_t fHstRegsWithGstShadow = pReNative->Core.bmHstRegsWithGstShadow & fRegsToFree;
4794	if (fHstRegsWithGstShadow)
4795	{
4796	Log12(("iemNativeRegMoveAndFreeAndFlushAtCall: bmHstRegsWithGstShadow %#RX32 -> %#RX32; removed %#RX32\n",
4797	pReNative->Core.bmHstRegsWithGstShadow, pReNative->Core.bmHstRegsWithGstShadow & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK, fHstRegsWithGstShadow));
4798	pReNative->Core.bmHstRegsWithGstShadow &= ~fHstRegsWithGstShadow;
4799	do
4800	{
4801	unsigned const idxReg = ASMBitFirstSetU32(fHstRegsWithGstShadow) - 1;
4802	fHstRegsWithGstShadow &= ~RT_BIT_32(idxReg);
4803
4804	AssertMsg(pReNative->Core.aHstRegs[idxReg].fGstRegShadows != 0, ("idxReg=%#x\n", idxReg));
4805	pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxReg].fGstRegShadows;
4806	pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
4807	} while (fHstRegsWithGstShadow != 0);
4808	}
4809
4810	return off;
4811	}
4812
4813
4814	/**
4815	* Flushes a set of guest register shadow copies.
4816	*
4817	* This is usually done after calling a threaded function or a C-implementation
4818	* of an instruction.
4819	*
4820	* @param pReNative The native recompile state.
4821	* @param fGstRegs Set of guest registers to flush.
4822	*/
4823	DECLHIDDEN(void) iemNativeRegFlushGuestShadows(PIEMRECOMPILERSTATE pReNative, uint64_t fGstRegs) RT_NOEXCEPT
4824	{
4825	/*
4826	* Reduce the mask by what's currently shadowed
4827	*/
4828	uint64_t const bmGstRegShadowsOld = pReNative->Core.bmGstRegShadows;
4829	fGstRegs &= bmGstRegShadowsOld;
4830	if (fGstRegs)
4831	{
4832	uint64_t const bmGstRegShadowsNew = bmGstRegShadowsOld & ~fGstRegs;
4833	Log12(("iemNativeRegFlushGuestShadows: flushing %#RX64 (%#RX64 -> %#RX64)\n", fGstRegs, bmGstRegShadowsOld, bmGstRegShadowsNew));
4834	pReNative->Core.bmGstRegShadows = bmGstRegShadowsNew;
4835	if (bmGstRegShadowsNew)
4836	{
4837	/*
4838	* Partial.
4839	*/
4840	do
4841	{
4842	unsigned const idxGstReg = ASMBitFirstSetU64(fGstRegs) - 1;
4843	uint8_t const idxHstReg = pReNative->Core.aidxGstRegShadows[idxGstReg];
4844	Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aidxGstRegShadows));
4845	Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxHstReg));
4846	Assert(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & RT_BIT_64(idxGstReg));
4847
4848	uint64_t const fInThisHstReg = (pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & fGstRegs) \| RT_BIT_64(idxGstReg);
4849	fGstRegs &= ~fInThisHstReg;
4850	uint64_t const fGstRegShadowsNew = pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & ~fInThisHstReg;
4851	pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = fGstRegShadowsNew;
4852	if (!fGstRegShadowsNew)
4853	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
4854	} while (fGstRegs != 0);
4855	}
4856	else
4857	{
4858	/*
4859	* Clear all.
4860	*/
4861	do
4862	{
4863	unsigned const idxGstReg = ASMBitFirstSetU64(fGstRegs) - 1;
4864	uint8_t const idxHstReg = pReNative->Core.aidxGstRegShadows[idxGstReg];
4865	Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aidxGstRegShadows));
4866	Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxHstReg));
4867	Assert(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & RT_BIT_64(idxGstReg));
4868
4869	fGstRegs &= ~(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows \| RT_BIT_64(idxGstReg));
4870	pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = 0;
4871	} while (fGstRegs != 0);
4872	pReNative->Core.bmHstRegsWithGstShadow = 0;
4873	}
4874	}
4875	}
4876
4877
4878	/**
4879	* Flushes guest register shadow copies held by a set of host registers.
4880	*
4881	* This is used with the TLB lookup code for ensuring that we don't carry on
4882	* with any guest shadows in volatile registers, as these will get corrupted by
4883	* a TLB miss.
4884	*
4885	* @param pReNative The native recompile state.
4886	* @param fHstRegs Set of host registers to flush guest shadows for.
4887	*/
4888	DECLHIDDEN(void) iemNativeRegFlushGuestShadowsByHostMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegs) RT_NOEXCEPT
4889	{
4890	/*
4891	* Reduce the mask by what's currently shadowed.
4892	*/
4893	uint32_t const bmHstRegsWithGstShadowOld = pReNative->Core.bmHstRegsWithGstShadow;
4894	fHstRegs &= bmHstRegsWithGstShadowOld;
4895	if (fHstRegs)
4896	{
4897	uint32_t const bmHstRegsWithGstShadowNew = bmHstRegsWithGstShadowOld & ~fHstRegs;
4898	Log12(("iemNativeRegFlushGuestShadowsByHostMask: flushing %#RX32 (%#RX32 -> %#RX32)\n",
4899	fHstRegs, bmHstRegsWithGstShadowOld, bmHstRegsWithGstShadowNew));
4900	pReNative->Core.bmHstRegsWithGstShadow = bmHstRegsWithGstShadowNew;
4901	if (bmHstRegsWithGstShadowNew)
4902	{
4903	/*
4904	* Partial (likely).
4905	*/
4906	uint64_t fGstShadows = 0;
4907	do
4908	{
4909	unsigned const idxHstReg = ASMBitFirstSetU32(fHstRegs) - 1;
4910	Assert(!(pReNative->Core.bmHstRegs & RT_BIT_32(idxHstReg)));
4911	Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows)
4912	== pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows);
4913
4914	fGstShadows \|= pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
4915	pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = 0;
4916	fHstRegs &= ~RT_BIT_32(idxHstReg);
4917	} while (fHstRegs != 0);
4918	pReNative->Core.bmGstRegShadows &= ~fGstShadows;
4919	}
4920	else
4921	{
4922	/*
4923	* Clear all.
4924	*/
4925	do
4926	{
4927	unsigned const idxHstReg = ASMBitFirstSetU32(fHstRegs) - 1;
4928	Assert(!(pReNative->Core.bmHstRegs & RT_BIT_32(idxHstReg)));
4929	Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows)
4930	== pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows);
4931
4932	pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = 0;
4933	fHstRegs &= ~RT_BIT_32(idxHstReg);
4934	} while (fHstRegs != 0);
4935	pReNative->Core.bmGstRegShadows = 0;
4936	}
4937	}
4938	}
4939
4940
4941	/**
4942	* Restores guest shadow copies in volatile registers.
4943	*
4944	* This is used after calling a helper function (think TLB miss) to restore the
4945	* register state of volatile registers.
4946	*
4947	* @param pReNative The native recompile state.
4948	* @param off The code buffer offset.
4949	* @param fHstRegsActiveShadows Set of host registers which are allowed to
4950	* be active (allocated) w/o asserting. Hack.
4951	* @see iemNativeVarSaveVolatileRegsPreHlpCall(),
4952	* iemNativeVarRestoreVolatileRegsPostHlpCall()
4953	*/
4954	DECL_HIDDEN_THROW(uint32_t)
4955	iemNativeRegRestoreGuestShadowsInVolatileRegs(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fHstRegsActiveShadows)
4956	{
4957	uint32_t fHstRegs = pReNative->Core.bmHstRegsWithGstShadow & IEMNATIVE_CALL_VOLATILE_GREG_MASK;
4958	if (fHstRegs)
4959	{
4960	Log12(("iemNativeRegRestoreGuestShadowsInVolatileRegs: %#RX32\n", fHstRegs));
4961	do
4962	{
4963	unsigned const idxHstReg = ASMBitFirstSetU32(fHstRegs) - 1;
4964
4965	/* It's not fatal if a register is active holding a variable that
4966	shadowing a guest register, ASSUMING all pending guest register
4967	writes were flushed prior to the helper call. However, we'll be
4968	emitting duplicate restores, so it wasts code space. */
4969	Assert(!(pReNative->Core.bmHstRegs & ~fHstRegsActiveShadows & RT_BIT_32(idxHstReg)));
4970	RT_NOREF(fHstRegsActiveShadows);
4971
4972	uint64_t const fGstRegShadows = pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
4973	Assert((pReNative->Core.bmGstRegShadows & fGstRegShadows) == fGstRegShadows);
4974	AssertStmt(fGstRegShadows != 0 && fGstRegShadows < RT_BIT_64(kIemNativeGstReg_End),
4975	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_12));
4976
4977	unsigned const idxGstReg = ASMBitFirstSetU64(fGstRegShadows) - 1;
4978	off = iemNativeEmitLoadGprWithGstShadowReg(pReNative, off, idxHstReg, (IEMNATIVEGSTREG)idxGstReg);
4979
4980	fHstRegs &= ~RT_BIT_32(idxHstReg);
4981	} while (fHstRegs != 0);
4982	}
4983	return off;
4984	}
4985
4986
4987	/**
4988	* Flushes delayed write of a specific guest register.
4989	*
4990	* This must be called prior to calling CImpl functions and any helpers that use
4991	* the guest state (like raising exceptions) and such.
4992	*
4993	* This optimization has not yet been implemented. The first target would be
4994	* RIP updates, since these are the most common ones.
4995	*/
4996	DECL_HIDDEN_THROW(uint32_t) iemNativeRegFlushPendingSpecificWrite(PIEMRECOMPILERSTATE pReNative, uint32_t off,
4997	IEMNATIVEGSTREGREF enmClass, uint8_t idxReg)
4998	{
4999	RT_NOREF(pReNative, enmClass, idxReg);
5000	return off;
5001	}
5002
5003
5004	/**
5005	* Flushes any delayed guest register writes.
5006	*
5007	* This must be called prior to calling CImpl functions and any helpers that use
5008	* the guest state (like raising exceptions) and such.
5009	*
5010	* This optimization has not yet been implemented. The first target would be
5011	* RIP updates, since these are the most common ones.
5012	*/
5013	DECL_HIDDEN_THROW(uint32_t) iemNativeRegFlushPendingWrites(PIEMRECOMPILERSTATE pReNative, uint32_t off)
5014	{
5015	RT_NOREF(pReNative, off);
5016	return off;
5017	}
5018
5019
5020	#ifdef VBOX_STRICT
5021	/**
5022	* Does internal register allocator sanity checks.
5023	*/
5024	static void iemNativeRegAssertSanity(PIEMRECOMPILERSTATE pReNative)
5025	{
5026	/*
5027	* Iterate host registers building a guest shadowing set.
5028	*/
5029	uint64_t bmGstRegShadows = 0;
5030	uint32_t bmHstRegsWithGstShadow = pReNative->Core.bmHstRegsWithGstShadow;
5031	AssertMsg(!(bmHstRegsWithGstShadow & IEMNATIVE_REG_FIXED_MASK), ("%#RX32\n", bmHstRegsWithGstShadow));
5032	while (bmHstRegsWithGstShadow)
5033	{
5034	unsigned const idxHstReg = ASMBitFirstSetU32(bmHstRegsWithGstShadow) - 1;
5035	Assert(idxHstReg < RT_ELEMENTS(pReNative->Core.aHstRegs));
5036	bmHstRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
5037
5038	uint64_t fThisGstRegShadows = pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
5039	AssertMsg(fThisGstRegShadows != 0, ("idxHstReg=%d\n", idxHstReg));
5040	AssertMsg(fThisGstRegShadows < RT_BIT_64(kIemNativeGstReg_End), ("idxHstReg=%d %#RX64\n", idxHstReg, fThisGstRegShadows));
5041	bmGstRegShadows \|= fThisGstRegShadows;
5042	while (fThisGstRegShadows)
5043	{
5044	unsigned const idxGstReg = ASMBitFirstSetU64(fThisGstRegShadows) - 1;
5045	fThisGstRegShadows &= ~RT_BIT_64(idxGstReg);
5046	AssertMsg(pReNative->Core.aidxGstRegShadows[idxGstReg] == idxHstReg,
5047	("idxHstReg=%d aidxGstRegShadows[idxGstReg=%d]=%d\n",
5048	idxHstReg, idxGstReg, pReNative->Core.aidxGstRegShadows[idxGstReg]));
5049	}
5050	}
5051	AssertMsg(bmGstRegShadows == pReNative->Core.bmGstRegShadows,
5052	("%RX64 vs %RX64; diff %RX64\n", bmGstRegShadows, pReNative->Core.bmGstRegShadows,
5053	bmGstRegShadows ^ pReNative->Core.bmGstRegShadows));
5054
5055	/*
5056	* Now the other way around, checking the guest to host index array.
5057	*/
5058	bmHstRegsWithGstShadow = 0;
5059	bmGstRegShadows = pReNative->Core.bmGstRegShadows;
5060	Assert(bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
5061	while (bmGstRegShadows)
5062	{
5063	unsigned const idxGstReg = ASMBitFirstSetU64(bmGstRegShadows) - 1;
5064	Assert(idxGstReg < RT_ELEMENTS(pReNative->Core.aidxGstRegShadows));
5065	bmGstRegShadows &= ~RT_BIT_64(idxGstReg);
5066
5067	uint8_t const idxHstReg = pReNative->Core.aidxGstRegShadows[idxGstReg];
5068	AssertMsg(idxHstReg < RT_ELEMENTS(pReNative->Core.aHstRegs), ("aidxGstRegShadows[%d]=%d\n", idxGstReg, idxHstReg));
5069	AssertMsg(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & RT_BIT_64(idxGstReg),
5070	("idxGstReg=%d idxHstReg=%d fGstRegShadows=%RX64\n",
5071	idxGstReg, idxHstReg, pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows));
5072	bmHstRegsWithGstShadow \|= RT_BIT_32(idxHstReg);
5073	}
5074	AssertMsg(bmHstRegsWithGstShadow == pReNative->Core.bmHstRegsWithGstShadow,
5075	("%RX64 vs %RX64; diff %RX64\n", bmHstRegsWithGstShadow, pReNative->Core.bmHstRegsWithGstShadow,
5076	bmHstRegsWithGstShadow ^ pReNative->Core.bmHstRegsWithGstShadow));
5077	}
5078	#endif
5079
5080
5081	/*********************************************************************************************************************************
5082	* Code Emitters (larger snippets) *
5083	*********************************************************************************************************************************/
5084
5085	/**
5086	* Loads the guest shadow register @a enmGstReg into host reg @a idxHstReg, zero
5087	* extending to 64-bit width.
5088	*
5089	* @returns New code buffer offset on success, UINT32_MAX on failure.
5090	* @param pReNative .
5091	* @param off The current code buffer position.
5092	* @param idxHstReg The host register to load the guest register value into.
5093	* @param enmGstReg The guest register to load.
5094	*
5095	* @note This does not mark @a idxHstReg as having a shadow copy of @a enmGstReg,
5096	* that is something the caller needs to do if applicable.
5097	*/
5098	DECL_HIDDEN_THROW(uint32_t)
5099	iemNativeEmitLoadGprWithGstShadowReg(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxHstReg, IEMNATIVEGSTREG enmGstReg)
5100	{
5101	Assert((unsigned)enmGstReg < RT_ELEMENTS(g_aGstShadowInfo));
5102	Assert(g_aGstShadowInfo[enmGstReg].cb != 0);
5103
5104	switch (g_aGstShadowInfo[enmGstReg].cb)
5105	{
5106	case sizeof(uint64_t):
5107	return iemNativeEmitLoadGprFromVCpuU64(pReNative, off, idxHstReg, g_aGstShadowInfo[enmGstReg].off);
5108	case sizeof(uint32_t):
5109	return iemNativeEmitLoadGprFromVCpuU32(pReNative, off, idxHstReg, g_aGstShadowInfo[enmGstReg].off);
5110	case sizeof(uint16_t):
5111	return iemNativeEmitLoadGprFromVCpuU16(pReNative, off, idxHstReg, g_aGstShadowInfo[enmGstReg].off);
5112	#if 0 /* not present in the table. */
5113	case sizeof(uint8_t):
5114	return iemNativeEmitLoadGprFromVCpuU8(pReNative, off, idxHstReg, g_aGstShadowInfo[enmGstReg].off);
5115	#endif
5116	default:
5117	AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IPE_NOT_REACHED_DEFAULT_CASE));
5118	}
5119	}
5120
5121
5122	#ifdef VBOX_STRICT
5123	/**
5124	* Emitting code that checks that the value of @a idxReg is UINT32_MAX or less.
5125	*
5126	* @note May of course trash IEMNATIVE_REG_FIXED_TMP0.
5127	* Trashes EFLAGS on AMD64.
5128	*/
5129	static uint32_t
5130	iemNativeEmitTop32BitsClearCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxReg)
5131	{
5132	# ifdef RT_ARCH_AMD64
5133	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 20);
5134
5135	/* rol reg64, 32 */
5136	pbCodeBuf[off++] = X86_OP_REX_W \| (idxReg < 8 ? 0 : X86_OP_REX_B);
5137	pbCodeBuf[off++] = 0xc1;
5138	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxReg & 7);
5139	pbCodeBuf[off++] = 32;
5140
5141	/* test reg32, ffffffffh */
5142	if (idxReg >= 8)
5143	pbCodeBuf[off++] = X86_OP_REX_B;
5144	pbCodeBuf[off++] = 0xf7;
5145	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxReg & 7);
5146	pbCodeBuf[off++] = 0xff;
5147	pbCodeBuf[off++] = 0xff;
5148	pbCodeBuf[off++] = 0xff;
5149	pbCodeBuf[off++] = 0xff;
5150
5151	/* je/jz +1 */
5152	pbCodeBuf[off++] = 0x74;
5153	pbCodeBuf[off++] = 0x01;
5154
5155	/* int3 */
5156	pbCodeBuf[off++] = 0xcc;
5157
5158	/* rol reg64, 32 */
5159	pbCodeBuf[off++] = X86_OP_REX_W \| (idxReg < 8 ? 0 : X86_OP_REX_B);
5160	pbCodeBuf[off++] = 0xc1;
5161	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxReg & 7);
5162	pbCodeBuf[off++] = 32;
5163
5164	# elif defined(RT_ARCH_ARM64)
5165	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
5166	/* lsr tmp0, reg64, #32 */
5167	pu32CodeBuf[off++] = Armv8A64MkInstrLsrImm(IEMNATIVE_REG_FIXED_TMP0, idxReg, 32);
5168	/* cbz tmp0, +1 */
5169	pu32CodeBuf[off++] = Armv8A64MkInstrCbzCbnz(false /fJmpIfNotZero/, 2, IEMNATIVE_REG_FIXED_TMP0);
5170	/* brk #0x1100 */
5171	pu32CodeBuf[off++] = Armv8A64MkInstrBrk(UINT32_C(0x1100));
5172
5173	# else
5174	# error "Port me!"
5175	# endif
5176	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
5177	return off;
5178	}
5179	#endif /* VBOX_STRICT */
5180
5181
5182	#ifdef VBOX_STRICT
5183	/**
5184	* Emitting code that checks that the content of register @a idxReg is the same
5185	* as what's in the guest register @a enmGstReg, resulting in a breakpoint
5186	* instruction if that's not the case.
5187	*
5188	* @note May of course trash IEMNATIVE_REG_FIXED_TMP0.
5189	* Trashes EFLAGS on AMD64.
5190	*/
5191	static uint32_t
5192	iemNativeEmitGuestRegValueCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxReg, IEMNATIVEGSTREG enmGstReg)
5193	{
5194	# ifdef RT_ARCH_AMD64
5195	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 32);
5196
5197	/* cmp reg, [mem] */
5198	if (g_aGstShadowInfo[enmGstReg].cb == sizeof(uint8_t))
5199	{
5200	if (idxReg >= 8)
5201	pbCodeBuf[off++] = X86_OP_REX_R;
5202	pbCodeBuf[off++] = 0x38;
5203	}
5204	else
5205	{
5206	if (g_aGstShadowInfo[enmGstReg].cb == sizeof(uint64_t))
5207	pbCodeBuf[off++] = X86_OP_REX_W \| (idxReg < 8 ? 0 : X86_OP_REX_R);
5208	else
5209	{
5210	if (g_aGstShadowInfo[enmGstReg].cb == sizeof(uint16_t))
5211	pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
5212	else
5213	AssertStmt(g_aGstShadowInfo[enmGstReg].cb == sizeof(uint32_t),
5214	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_LABEL_IPE_6));
5215	if (idxReg >= 8)
5216	pbCodeBuf[off++] = X86_OP_REX_R;
5217	}
5218	pbCodeBuf[off++] = 0x39;
5219	}
5220	off = iemNativeEmitGprByVCpuDisp(pbCodeBuf, off, idxReg, g_aGstShadowInfo[enmGstReg].off);
5221
5222	/* je/jz +1 */
5223	pbCodeBuf[off++] = 0x74;
5224	pbCodeBuf[off++] = 0x01;
5225
5226	/* int3 */
5227	pbCodeBuf[off++] = 0xcc;
5228
5229	/* For values smaller than the register size, we must check that the rest
5230	of the register is all zeros. */
5231	if (g_aGstShadowInfo[enmGstReg].cb < sizeof(uint32_t))
5232	{
5233	/* test reg64, imm32 */
5234	pbCodeBuf[off++] = X86_OP_REX_W \| (idxReg < 8 ? 0 : X86_OP_REX_B);
5235	pbCodeBuf[off++] = 0xf7;
5236	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxReg & 7);
5237	pbCodeBuf[off++] = 0;
5238	pbCodeBuf[off++] = g_aGstShadowInfo[enmGstReg].cb > sizeof(uint8_t) ? 0 : 0xff;
5239	pbCodeBuf[off++] = 0xff;
5240	pbCodeBuf[off++] = 0xff;
5241
5242	/* je/jz +1 */
5243	pbCodeBuf[off++] = 0x74;
5244	pbCodeBuf[off++] = 0x01;
5245
5246	/* int3 */
5247	pbCodeBuf[off++] = 0xcc;
5248	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
5249	}
5250	else
5251	{
5252	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
5253	if (g_aGstShadowInfo[enmGstReg].cb == sizeof(uint32_t))
5254	iemNativeEmitTop32BitsClearCheck(pReNative, off, idxReg);
5255	}
5256
5257	# elif defined(RT_ARCH_ARM64)
5258	/* mov TMP0, [gstreg] */
5259	off = iemNativeEmitLoadGprWithGstShadowReg(pReNative, off, IEMNATIVE_REG_FIXED_TMP0, enmGstReg);
5260
5261	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
5262	/* sub tmp0, tmp0, idxReg */
5263	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubReg(true /fSub/, IEMNATIVE_REG_FIXED_TMP0, IEMNATIVE_REG_FIXED_TMP0, idxReg);
5264	/* cbz tmp0, +1 */
5265	pu32CodeBuf[off++] = Armv8A64MkInstrCbzCbnz(false /fJmpIfNotZero/, 2, IEMNATIVE_REG_FIXED_TMP0);
5266	/* brk #0x1000+enmGstReg */
5267	pu32CodeBuf[off++] = Armv8A64MkInstrBrk((uint32_t)enmGstReg \| UINT32_C(0x1000));
5268	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
5269
5270	# else
5271	# error "Port me!"
5272	# endif
5273	return off;
5274	}
5275	#endif /* VBOX_STRICT */
5276
5277
5278	#ifdef VBOX_STRICT
5279	/**
5280	* Emitting code that checks that IEMCPU::fExec matches @a fExec for all
5281	* important bits.
5282	*
5283	* @note May of course trash IEMNATIVE_REG_FIXED_TMP0.
5284	* Trashes EFLAGS on AMD64.
5285	*/
5286	static uint32_t
5287	iemNativeEmitExecFlagsCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fExec)
5288	{
5289	uint8_t const idxRegTmp = iemNativeRegAllocTmp(pReNative, &off);
5290	off = iemNativeEmitLoadGprFromVCpuU32(pReNative, off, idxRegTmp, RT_UOFFSETOF(VMCPUCC, iem.s.fExec));
5291	off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxRegTmp, IEMTB_F_IEM_F_MASK & IEMTB_F_KEY_MASK);
5292	off = iemNativeEmitCmpGpr32WithImm(pReNative, off, idxRegTmp, fExec & IEMTB_F_KEY_MASK);
5293
5294	#ifdef RT_ARCH_AMD64
5295	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
5296
5297	/* je/jz +1 */
5298	pbCodeBuf[off++] = 0x74;
5299	pbCodeBuf[off++] = 0x01;
5300
5301	/* int3 */
5302	pbCodeBuf[off++] = 0xcc;
5303
5304	# elif defined(RT_ARCH_ARM64)
5305	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
5306
5307	/* b.eq +1 */
5308	pu32CodeBuf[off++] = Armv8A64MkInstrBCond(kArmv8InstrCond_Eq, 2);
5309	/* brk #0x2000 */
5310	pu32CodeBuf[off++] = Armv8A64MkInstrBrk(UINT32_C(0x2000));
5311
5312	# else
5313	# error "Port me!"
5314	# endif
5315	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
5316
5317	iemNativeRegFreeTmp(pReNative, idxRegTmp);
5318	return off;
5319	}
5320	#endif /* VBOX_STRICT */
5321
5322
5323	/**
5324	* Emits a code for checking the return code of a call and rcPassUp, returning
5325	* from the code if either are non-zero.
5326	*/
5327	DECL_HIDDEN_THROW(uint32_t)
5328	iemNativeEmitCheckCallRetAndPassUp(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr)
5329	{
5330	#ifdef RT_ARCH_AMD64
5331	/*
5332	* AMD64: eax = call status code.
5333	*/
5334
5335	/* edx = rcPassUp */
5336	off = iemNativeEmitLoadGprFromVCpuU32(pReNative, off, X86_GREG_xDX, RT_UOFFSETOF(VMCPUCC, iem.s.rcPassUp));
5337	# ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
5338	off = iemNativeEmitLoadGpr8Imm(pReNative, off, X86_GREG_xCX, idxInstr);
5339	# endif
5340
5341	/* edx = eax \| rcPassUp */
5342	uint8_t *pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
5343	pbCodeBuf[off++] = 0x0b; /* or edx, eax */
5344	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, X86_GREG_xDX, X86_GREG_xAX);
5345	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
5346
5347	/* Jump to non-zero status return path. */
5348	off = iemNativeEmitJnzToNewLabel(pReNative, off, kIemNativeLabelType_NonZeroRetOrPassUp);
5349
5350	/* done. */
5351
5352	#elif RT_ARCH_ARM64
5353	/*
5354	* ARM64: w0 = call status code.
5355	*/
5356	# ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
5357	off = iemNativeEmitLoadGprImm64(pReNative, off, ARMV8_A64_REG_X2, idxInstr);
5358	# endif
5359	off = iemNativeEmitLoadGprFromVCpuU32(pReNative, off, ARMV8_A64_REG_X3, RT_UOFFSETOF(VMCPUCC, iem.s.rcPassUp));
5360
5361	uint32_t *pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
5362
5363	pu32CodeBuf[off++] = Armv8A64MkInstrOrr(ARMV8_A64_REG_X4, ARMV8_A64_REG_X3, ARMV8_A64_REG_X0, false /f64Bit/);
5364
5365	uint32_t const idxLabel = iemNativeLabelCreate(pReNative, kIemNativeLabelType_NonZeroRetOrPassUp);
5366	iemNativeAddFixup(pReNative, off, idxLabel, kIemNativeFixupType_RelImm19At5);
5367	pu32CodeBuf[off++] = Armv8A64MkInstrCbzCbnz(true /fJmpIfNotZero/, 0, ARMV8_A64_REG_X4, false /f64Bit/);
5368
5369	#else
5370	# error "port me"
5371	#endif
5372	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
5373	RT_NOREF_PV(idxInstr);
5374	return off;
5375	}
5376
5377
5378	/**
5379	* Emits code to check if the content of @a idxAddrReg is a canonical address,
5380	* raising a \#GP(0) if it isn't.
5381	*
5382	* @returns New code buffer offset, UINT32_MAX on failure.
5383	* @param pReNative The native recompile state.
5384	* @param off The code buffer offset.
5385	* @param idxAddrReg The host register with the address to check.
5386	* @param idxInstr The current instruction.
5387	*/
5388	DECL_HIDDEN_THROW(uint32_t)
5389	iemNativeEmitCheckGprCanonicalMaybeRaiseGp0(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxAddrReg, uint8_t idxInstr)
5390	{
5391	/*
5392	* Make sure we don't have any outstanding guest register writes as we may
5393	* raise an #GP(0) and all guest register must be up to date in CPUMCTX.
5394	*/
5395	off = iemNativeRegFlushPendingWrites(pReNative, off);
5396
5397	#ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
5398	off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr));
5399	#else
5400	RT_NOREF(idxInstr);
5401	#endif
5402
5403	#ifdef RT_ARCH_AMD64
5404	/*
5405	* if ((((uint32_t)(a_u64Addr >> 32) + UINT32_C(0x8000)) >> 16) != 0)
5406	* return raisexcpt();
5407	* ---- this wariant avoid loading a 64-bit immediate, but is an instruction longer.
5408	*/
5409	uint8_t const iTmpReg = iemNativeRegAllocTmp(pReNative, &off);
5410
5411	off = iemNativeEmitLoadGprFromGpr(pReNative, off, iTmpReg, idxAddrReg);
5412	off = iemNativeEmitShiftGprRight(pReNative, off, iTmpReg, 32);
5413	off = iemNativeEmitAddGpr32Imm(pReNative, off, iTmpReg, (int32_t)0x8000);
5414	off = iemNativeEmitShiftGprRight(pReNative, off, iTmpReg, 16);
5415	off = iemNativeEmitJnzToNewLabel(pReNative, off, kIemNativeLabelType_RaiseGp0);
5416
5417	iemNativeRegFreeTmp(pReNative, iTmpReg);
5418
5419	#elif defined(RT_ARCH_ARM64)
5420	/*
5421	* if ((((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000)) >> 48) != 0)
5422	* return raisexcpt();
5423	* ----
5424	* mov x1, 0x800000000000
5425	* add x1, x0, x1
5426	* cmp xzr, x1, lsr 48
5427	* b.ne .Lraisexcpt
5428	*/
5429	uint8_t const iTmpReg = iemNativeRegAllocTmp(pReNative, &off);
5430
5431	off = iemNativeEmitLoadGprImm64(pReNative, off, iTmpReg, UINT64_C(0x800000000000));
5432	off = iemNativeEmitAddTwoGprs(pReNative, off, iTmpReg, idxAddrReg);
5433	off = iemNativeEmitCmpArm64(pReNative, off, ARMV8_A64_REG_XZR, iTmpReg, true /f64Bit/, 48 /cShift/, kArmv8A64InstrShift_Lsr);
5434	off = iemNativeEmitJnzToNewLabel(pReNative, off, kIemNativeLabelType_RaiseGp0);
5435
5436	iemNativeRegFreeTmp(pReNative, iTmpReg);
5437
5438	#else
5439	# error "Port me"
5440	#endif
5441	return off;
5442	}
5443
5444
5445	/**
5446	* Emits code to check if that the content of @a idxAddrReg is within the limit
5447	* of CS, raising a \#GP(0) if it isn't.
5448	*
5449	* @returns New code buffer offset; throws VBox status code on error.
5450	* @param pReNative The native recompile state.
5451	* @param off The code buffer offset.
5452	* @param idxAddrReg The host register (32-bit) with the address to
5453	* check.
5454	* @param idxInstr The current instruction.
5455	*/
5456	DECL_HIDDEN_THROW(uint32_t)
5457	iemNativeEmitCheckGpr32AgainstCsSegLimitMaybeRaiseGp0(PIEMRECOMPILERSTATE pReNative, uint32_t off,
5458	uint8_t idxAddrReg, uint8_t idxInstr)
5459	{
5460	/*
5461	* Make sure we don't have any outstanding guest register writes as we may
5462	* raise an #GP(0) and all guest register must be up to date in CPUMCTX.
5463	*/
5464	off = iemNativeRegFlushPendingWrites(pReNative, off);
5465
5466	#ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
5467	off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr));
5468	#else
5469	RT_NOREF(idxInstr);
5470	#endif
5471
5472	uint8_t const idxRegCsLim = iemNativeRegAllocTmpForGuestReg(pReNative, &off,
5473	(IEMNATIVEGSTREG)(kIemNativeGstReg_SegLimitFirst + X86_SREG_CS),
5474	kIemNativeGstRegUse_ReadOnly);
5475
5476	off = iemNativeEmitCmpGpr32WithGpr(pReNative, off, idxAddrReg, idxRegCsLim);
5477	off = iemNativeEmitJaToNewLabel(pReNative, off, kIemNativeLabelType_RaiseGp0);
5478
5479	iemNativeRegFreeTmp(pReNative, idxRegCsLim);
5480	return off;
5481	}
5482
5483
5484	/**
5485	* Converts IEM_CIMPL_F_XXX flags into a guest register shadow copy flush mask.
5486	*
5487	* @returns The flush mask.
5488	* @param fCImpl The IEM_CIMPL_F_XXX flags.
5489	* @param fGstShwFlush The starting flush mask.
5490	*/
5491	DECL_FORCE_INLINE(uint64_t) iemNativeCImplFlagsToGuestShadowFlushMask(uint32_t fCImpl, uint64_t fGstShwFlush)
5492	{
5493	if (fCImpl & IEM_CIMPL_F_BRANCH_FAR)
5494	fGstShwFlush \|= RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_CS)
5495	\| RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_CS)
5496	\| RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_CS);
5497	if (fCImpl & IEM_CIMPL_F_BRANCH_STACK_FAR)
5498	fGstShwFlush \|= RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP)
5499	\| RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_SS)
5500	\| RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_SS)
5501	\| RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_SS);
5502	else if (fCImpl & IEM_CIMPL_F_BRANCH_STACK)
5503	fGstShwFlush \|= RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP);
5504	if (fCImpl & (IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_STATUS_FLAGS \| IEM_CIMPL_F_INHIBIT_SHADOW))
5505	fGstShwFlush \|= RT_BIT_64(kIemNativeGstReg_EFlags);
5506	return fGstShwFlush;
5507	}
5508
5509
5510	/**
5511	* Emits a call to a CImpl function or something similar.
5512	*/
5513	DECL_HIDDEN_THROW(uint32_t)
5514	iemNativeEmitCImplCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr, uint64_t fGstShwFlush, uintptr_t pfnCImpl,
5515	uint8_t cbInstr, uint8_t cAddParams, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5516	{
5517	/*
5518	* Flush stuff. PC and EFlags are implictly flushed, the latter because we
5519	* don't do with/without flags variants of defer-to-cimpl stuff at the moment.
5520	*/
5521	fGstShwFlush = iemNativeCImplFlagsToGuestShadowFlushMask(pReNative->fCImpl,
5522	fGstShwFlush
5523	\| RT_BIT_64(kIemNativeGstReg_Pc)
5524	\| RT_BIT_64(kIemNativeGstReg_EFlags));
5525	iemNativeRegFlushGuestShadows(pReNative, fGstShwFlush);
5526
5527	off = iemNativeRegMoveAndFreeAndFlushAtCall(pReNative, off, 4);
5528
5529	/*
5530	* Load the parameters.
5531	*/
5532	#if defined(RT_OS_WINDOWS) && defined(VBOXSTRICTRC_STRICT_ENABLED)
5533	/* Special code the hidden VBOXSTRICTRC pointer. */
5534	off = iemNativeEmitLoadGprFromGpr( pReNative, off, IEMNATIVE_CALL_ARG1_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
5535	off = iemNativeEmitLoadGprImm64( pReNative, off, IEMNATIVE_CALL_ARG2_GREG, cbInstr); /** @todo 8-bit reg load opt for amd64 */
5536	if (cAddParams > 0)
5537	off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG3_GREG, uParam0);
5538	if (cAddParams > 1)
5539	off = iemNativeEmitStoreImm64ByBp(pReNative, off, IEMNATIVE_FP_OFF_STACK_ARG0, uParam1);
5540	if (cAddParams > 2)
5541	off = iemNativeEmitStoreImm64ByBp(pReNative, off, IEMNATIVE_FP_OFF_STACK_ARG1, uParam2);
5542	off = iemNativeEmitLeaGprByBp(pReNative, off, X86_GREG_xCX, IEMNATIVE_FP_OFF_IN_SHADOW_ARG0); /* rcStrict */
5543
5544	#else
5545	AssertCompile(IEMNATIVE_CALL_ARG_GREG_COUNT >= 4);
5546	off = iemNativeEmitLoadGprFromGpr( pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
5547	off = iemNativeEmitLoadGprImm64( pReNative, off, IEMNATIVE_CALL_ARG1_GREG, cbInstr); /** @todo 8-bit reg load opt for amd64 */
5548	if (cAddParams > 0)
5549	off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG2_GREG, uParam0);
5550	if (cAddParams > 1)
5551	off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG3_GREG, uParam1);
5552	if (cAddParams > 2)
5553	# if IEMNATIVE_CALL_ARG_GREG_COUNT >= 5
5554	off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG4_GREG, uParam2);
5555	# else
5556	off = iemNativeEmitStoreImm64ByBp(pReNative, off, IEMNATIVE_FP_OFF_STACK_ARG0, uParam2);
5557	# endif
5558	#endif
5559
5560	/*
5561	* Make the call.
5562	*/
5563	off = iemNativeEmitCallImm(pReNative, off, pfnCImpl);
5564
5565	#if defined(RT_ARCH_AMD64) && defined(VBOXSTRICTRC_STRICT_ENABLED) && defined(RT_OS_WINDOWS)
5566	off = iemNativeEmitLoadGprByBpU32(pReNative, off, X86_GREG_xAX, IEMNATIVE_FP_OFF_IN_SHADOW_ARG0); /* rcStrict (see above) */
5567	#endif
5568
5569	/*
5570	* Check the status code.
5571	*/
5572	return iemNativeEmitCheckCallRetAndPassUp(pReNative, off, idxInstr);
5573	}
5574
5575
5576	/**
5577	* Emits a call to a threaded worker function.
5578	*/
5579	DECL_HIDDEN_THROW(uint32_t)
5580	iemNativeEmitThreadedCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry)
5581	{
5582	iemNativeRegFlushGuestShadows(pReNative, UINT64_MAX); /** @todo optimize this */
5583	off = iemNativeRegMoveAndFreeAndFlushAtCall(pReNative, off, 4);
5584
5585	#ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
5586	/* The threaded function may throw / long jmp, so set current instruction
5587	number if we're counting. */
5588	off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, pCallEntry->idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr));
5589	#endif
5590
5591	uint8_t const cParams = g_acIemThreadedFunctionUsedArgs[pCallEntry->enmFunction];
5592
5593	#ifdef RT_ARCH_AMD64
5594	/* Load the parameters and emit the call. */
5595	# ifdef RT_OS_WINDOWS
5596	# ifndef VBOXSTRICTRC_STRICT_ENABLED
5597	off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xCX, IEMNATIVE_REG_FIXED_PVMCPU);
5598	if (cParams > 0)
5599	off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_xDX, pCallEntry->auParams[0]);
5600	if (cParams > 1)
5601	off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_x8, pCallEntry->auParams[1]);
5602	if (cParams > 2)
5603	off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_x9, pCallEntry->auParams[2]);
5604	# else /* VBOXSTRICTRC: Returned via hidden parameter. Sigh. */
5605	off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xDX, IEMNATIVE_REG_FIXED_PVMCPU);
5606	if (cParams > 0)
5607	off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_x8, pCallEntry->auParams[0]);
5608	if (cParams > 1)
5609	off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_x9, pCallEntry->auParams[1]);
5610	if (cParams > 2)
5611	{
5612	off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_x10, pCallEntry->auParams[2]);
5613	off = iemNativeEmitStoreGprByBp(pReNative, off, IEMNATIVE_FP_OFF_STACK_ARG0, X86_GREG_x10);
5614	}
5615	off = iemNativeEmitLeaGprByBp(pReNative, off, X86_GREG_xCX, IEMNATIVE_FP_OFF_IN_SHADOW_ARG0); /* rcStrict */
5616	# endif /* VBOXSTRICTRC_STRICT_ENABLED */
5617	# else
5618	off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xDI, IEMNATIVE_REG_FIXED_PVMCPU);
5619	if (cParams > 0)
5620	off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_xSI, pCallEntry->auParams[0]);
5621	if (cParams > 1)
5622	off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_xDX, pCallEntry->auParams[1]);
5623	if (cParams > 2)
5624	off = iemNativeEmitLoadGprImm64(pReNative, off, X86_GREG_xCX, pCallEntry->auParams[2]);
5625	# endif
5626
5627	off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)g_apfnIemThreadedFunctions[pCallEntry->enmFunction]);
5628
5629	# if defined(VBOXSTRICTRC_STRICT_ENABLED) && defined(RT_OS_WINDOWS)
5630	off = iemNativeEmitLoadGprByBpU32(pReNative, off, X86_GREG_xAX, IEMNATIVE_FP_OFF_IN_SHADOW_ARG0); /* rcStrict (see above) */
5631	# endif
5632
5633	#elif RT_ARCH_ARM64
5634	/*
5635	* ARM64:
5636	*/
5637	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
5638	if (cParams > 0)
5639	off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG1_GREG, pCallEntry->auParams[0]);
5640	if (cParams > 1)
5641	off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG2_GREG, pCallEntry->auParams[1]);
5642	if (cParams > 2)
5643	off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_ARG3_GREG, pCallEntry->auParams[2]);
5644
5645	off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)g_apfnIemThreadedFunctions[pCallEntry->enmFunction]);
5646
5647	#else
5648	# error "port me"
5649	#endif
5650
5651	/*
5652	* Check the status code.
5653	*/
5654	off = iemNativeEmitCheckCallRetAndPassUp(pReNative, off, pCallEntry->idxInstr);
5655
5656	return off;
5657	}
5658
5659	#ifdef VBOX_WITH_STATISTICS
5660	/**
5661	* Emits code to update the thread call statistics.
5662	*/
5663	DECL_INLINE_THROW(uint32_t)
5664	iemNativeEmitThreadCallStats(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry)
5665	{
5666	/*
5667	* Update threaded function stats.
5668	*/
5669	uint32_t const offVCpu = RT_UOFFSETOF_DYN(VMCPUCC, iem.s.acThreadedFuncStats[pCallEntry->enmFunction]);
5670	AssertCompile(sizeof(pReNative->pVCpu->iem.s.acThreadedFuncStats[pCallEntry->enmFunction]) == sizeof(uint32_t));
5671	# if defined(RT_ARCH_ARM64)
5672	uint8_t const idxTmp1 = iemNativeRegAllocTmp(pReNative, &off);
5673	uint8_t const idxTmp2 = iemNativeRegAllocTmp(pReNative, &off);
5674	off = iemNativeEmitIncU32CounterInVCpu(pReNative, off, idxTmp1, idxTmp2, offVCpu);
5675	iemNativeRegFreeTmp(pReNative, idxTmp1);
5676	iemNativeRegFreeTmp(pReNative, idxTmp2);
5677	# else
5678	off = iemNativeEmitIncU32CounterInVCpu(pReNative, off, UINT8_MAX, UINT8_MAX, offVCpu);
5679	# endif
5680	return off;
5681	}
5682	#endif /* VBOX_WITH_STATISTICS */
5683
5684
5685	/**
5686	* Emits the code at the CheckBranchMiss label.
5687	*/
5688	static uint32_t iemNativeEmitCheckBranchMiss(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t idxReturnLabel)
5689	{
5690	uint32_t const idxLabel = iemNativeLabelFind(pReNative, kIemNativeLabelType_CheckBranchMiss);
5691	if (idxLabel != UINT32_MAX)
5692	{
5693	iemNativeLabelDefine(pReNative, idxLabel, off);
5694
5695	/* int iemNativeHlpCheckBranchMiss(PVMCPUCC pVCpu) */
5696	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
5697	off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)iemNativeHlpCheckBranchMiss);
5698
5699	/* jump back to the return sequence. */
5700	off = iemNativeEmitJmpToLabel(pReNative, off, idxReturnLabel);
5701	}
5702	return off;
5703	}
5704
5705
5706	/**
5707	* Emits the code at the NeedCsLimChecking label.
5708	*/
5709	static uint32_t iemNativeEmitNeedCsLimChecking(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t idxReturnLabel)
5710	{
5711	uint32_t const idxLabel = iemNativeLabelFind(pReNative, kIemNativeLabelType_NeedCsLimChecking);
5712	if (idxLabel != UINT32_MAX)
5713	{
5714	iemNativeLabelDefine(pReNative, idxLabel, off);
5715
5716	/* int iemNativeHlpNeedCsLimChecking(PVMCPUCC pVCpu) */
5717	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
5718	off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)iemNativeHlpNeedCsLimChecking);
5719
5720	/* jump back to the return sequence. */
5721	off = iemNativeEmitJmpToLabel(pReNative, off, idxReturnLabel);
5722	}
5723	return off;
5724	}
5725
5726
5727	/**
5728	* Emits the code at the ObsoleteTb label.
5729	*/
5730	static uint32_t iemNativeEmitObsoleteTb(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t idxReturnLabel)
5731	{
5732	uint32_t const idxLabel = iemNativeLabelFind(pReNative, kIemNativeLabelType_ObsoleteTb);
5733	if (idxLabel != UINT32_MAX)
5734	{
5735	iemNativeLabelDefine(pReNative, idxLabel, off);
5736
5737	/* int iemNativeHlpObsoleteTb(PVMCPUCC pVCpu) */
5738	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
5739	off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)iemNativeHlpObsoleteTb);
5740
5741	/* jump back to the return sequence. */
5742	off = iemNativeEmitJmpToLabel(pReNative, off, idxReturnLabel);
5743	}
5744	return off;
5745	}
5746
5747
5748	/**
5749	* Emits the code at the RaiseGP0 label.
5750	*/
5751	static uint32_t iemNativeEmitRaiseGp0(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t idxReturnLabel)
5752	{
5753	uint32_t const idxLabel = iemNativeLabelFind(pReNative, kIemNativeLabelType_RaiseGp0);
5754	if (idxLabel != UINT32_MAX)
5755	{
5756	iemNativeLabelDefine(pReNative, idxLabel, off);
5757
5758	/* iemNativeHlpExecRaiseGp0(PVMCPUCC pVCpu) */
5759	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
5760	off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)iemNativeHlpExecRaiseGp0);
5761
5762	/* jump back to the return sequence. */
5763	off = iemNativeEmitJmpToLabel(pReNative, off, idxReturnLabel);
5764	}
5765	return off;
5766	}
5767
5768
5769	/**
5770	* Emits the code at the ReturnWithFlags label (returns
5771	* VINF_IEM_REEXEC_FINISH_WITH_FLAGS).
5772	*/
5773	static uint32_t iemNativeEmitReturnWithFlags(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t idxReturnLabel)
5774	{
5775	uint32_t const idxLabel = iemNativeLabelFind(pReNative, kIemNativeLabelType_ReturnWithFlags);
5776	if (idxLabel != UINT32_MAX)
5777	{
5778	iemNativeLabelDefine(pReNative, idxLabel, off);
5779
5780	off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_RET_GREG, VINF_IEM_REEXEC_FINISH_WITH_FLAGS);
5781
5782	/* jump back to the return sequence. */
5783	off = iemNativeEmitJmpToLabel(pReNative, off, idxReturnLabel);
5784	}
5785	return off;
5786	}
5787
5788
5789	/**
5790	* Emits the code at the ReturnBreak label (returns VINF_IEM_REEXEC_BREAK).
5791	*/
5792	static uint32_t iemNativeEmitReturnBreak(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t idxReturnLabel)
5793	{
5794	uint32_t const idxLabel = iemNativeLabelFind(pReNative, kIemNativeLabelType_ReturnBreak);
5795	if (idxLabel != UINT32_MAX)
5796	{
5797	iemNativeLabelDefine(pReNative, idxLabel, off);
5798
5799	off = iemNativeEmitLoadGprImm64(pReNative, off, IEMNATIVE_CALL_RET_GREG, VINF_IEM_REEXEC_BREAK);
5800
5801	/* jump back to the return sequence. */
5802	off = iemNativeEmitJmpToLabel(pReNative, off, idxReturnLabel);
5803	}
5804	return off;
5805	}
5806
5807
5808	/**
5809	* Emits the RC fiddling code for handling non-zero return code or rcPassUp.
5810	*/
5811	static uint32_t iemNativeEmitRcFiddling(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t idxReturnLabel)
5812	{
5813	/*
5814	* Generate the rc + rcPassUp fiddling code if needed.
5815	*/
5816	uint32_t const idxLabel = iemNativeLabelFind(pReNative, kIemNativeLabelType_NonZeroRetOrPassUp);
5817	if (idxLabel != UINT32_MAX)
5818	{
5819	iemNativeLabelDefine(pReNative, idxLabel, off);
5820
5821	/* iemNativeHlpExecStatusCodeFiddling(PVMCPUCC pVCpu, int rc, uint8_t idxInstr) */
5822	#ifdef RT_ARCH_AMD64
5823	# ifdef RT_OS_WINDOWS
5824	# ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
5825	off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_x8, X86_GREG_xCX); /* cl = instruction number */
5826	# endif
5827	off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xCX, IEMNATIVE_REG_FIXED_PVMCPU);
5828	off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xDX, X86_GREG_xAX);
5829	# else
5830	off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xDI, IEMNATIVE_REG_FIXED_PVMCPU);
5831	off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xSI, X86_GREG_xAX);
5832	# ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
5833	off = iemNativeEmitLoadGprFromGpr(pReNative, off, X86_GREG_xDX, X86_GREG_xCX); /* cl = instruction number */
5834	# endif
5835	# endif
5836	# ifndef IEMNATIVE_WITH_INSTRUCTION_COUNTING
5837	off = iemNativeEmitLoadGpr8Imm(pReNative, off, X86_GREG_xCX, 0);
5838	# endif
5839
5840	#else
5841	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG1_GREG, IEMNATIVE_CALL_RET_GREG);
5842	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
5843	/* IEMNATIVE_CALL_ARG2_GREG is already set. */
5844	#endif
5845
5846	off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)iemNativeHlpExecStatusCodeFiddling);
5847	off = iemNativeEmitJmpToLabel(pReNative, off, idxReturnLabel);
5848	}
5849	return off;
5850	}
5851
5852
5853	/**
5854	* Emits a standard epilog.
5855	*/
5856	static uint32_t iemNativeEmitEpilog(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t *pidxReturnLabel)
5857	{
5858	*pidxReturnLabel = UINT32_MAX;
5859
5860	/*
5861	* Successful return, so clear the return register (eax, w0).
5862	*/
5863	off = iemNativeEmitGprZero(pReNative,off, IEMNATIVE_CALL_RET_GREG);
5864
5865	/*
5866	* Define label for common return point.
5867	*/
5868	uint32_t const idxReturn = iemNativeLabelCreate(pReNative, kIemNativeLabelType_Return, off);
5869	*pidxReturnLabel = idxReturn;
5870
5871	/*
5872	* Restore registers and return.
5873	*/
5874	#ifdef RT_ARCH_AMD64
5875	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 20);
5876
5877	/* Reposition esp at the r15 restore point. */
5878	pbCodeBuf[off++] = X86_OP_REX_W;
5879	pbCodeBuf[off++] = 0x8d; /* lea rsp, [rbp - (gcc ? 5 : 7) * 8] */
5880	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_MEM1, X86_GREG_xSP, X86_GREG_xBP);
5881	pbCodeBuf[off++] = (uint8_t)IEMNATIVE_FP_OFF_LAST_PUSH;
5882
5883	/* Pop non-volatile registers and return */
5884	pbCodeBuf[off++] = X86_OP_REX_B; /* pop r15 */
5885	pbCodeBuf[off++] = 0x58 + X86_GREG_x15 - 8;
5886	pbCodeBuf[off++] = X86_OP_REX_B; /* pop r14 */
5887	pbCodeBuf[off++] = 0x58 + X86_GREG_x14 - 8;
5888	pbCodeBuf[off++] = X86_OP_REX_B; /* pop r13 */
5889	pbCodeBuf[off++] = 0x58 + X86_GREG_x13 - 8;
5890	pbCodeBuf[off++] = X86_OP_REX_B; /* pop r12 */
5891	pbCodeBuf[off++] = 0x58 + X86_GREG_x12 - 8;
5892	# ifdef RT_OS_WINDOWS
5893	pbCodeBuf[off++] = 0x58 + X86_GREG_xDI; /* pop rdi */
5894	pbCodeBuf[off++] = 0x58 + X86_GREG_xSI; /* pop rsi */
5895	# endif
5896	pbCodeBuf[off++] = 0x58 + X86_GREG_xBX; /* pop rbx */
5897	pbCodeBuf[off++] = 0xc9; /* leave */
5898	pbCodeBuf[off++] = 0xc3; /* ret */
5899	pbCodeBuf[off++] = 0xcc; /* int3 poison */
5900
5901	#elif RT_ARCH_ARM64
5902	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 10);
5903
5904	/* ldp x19, x20, [sp #IEMNATIVE_FRAME_VAR_SIZE]! ; Unallocate the variable space and restore x19+x20. */
5905	AssertCompile(IEMNATIVE_FRAME_VAR_SIZE < 64*8);
5906	pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(true /fLoad/, 2 /64-bit/, kArm64InstrStLdPairType_PreIndex,
5907	ARMV8_A64_REG_X19, ARMV8_A64_REG_X20, ARMV8_A64_REG_SP,
5908	IEMNATIVE_FRAME_VAR_SIZE / 8);
5909	/* Restore x21 thru x28 + BP and LR (ret address) (SP remains unchanged in the kSigned variant). */
5910	pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(true /fLoad/, 2 /64-bit/, kArm64InstrStLdPairType_Signed,
5911	ARMV8_A64_REG_X21, ARMV8_A64_REG_X22, ARMV8_A64_REG_SP, 2);
5912	pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(true /fLoad/, 2 /64-bit/, kArm64InstrStLdPairType_Signed,
5913	ARMV8_A64_REG_X23, ARMV8_A64_REG_X24, ARMV8_A64_REG_SP, 4);
5914	pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(true /fLoad/, 2 /64-bit/, kArm64InstrStLdPairType_Signed,
5915	ARMV8_A64_REG_X25, ARMV8_A64_REG_X26, ARMV8_A64_REG_SP, 6);
5916	pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(true /fLoad/, 2 /64-bit/, kArm64InstrStLdPairType_Signed,
5917	ARMV8_A64_REG_X27, ARMV8_A64_REG_X28, ARMV8_A64_REG_SP, 8);
5918	pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(true /fLoad/, 2 /64-bit/, kArm64InstrStLdPairType_Signed,
5919	ARMV8_A64_REG_BP, ARMV8_A64_REG_LR, ARMV8_A64_REG_SP, 10);
5920	AssertCompile(IEMNATIVE_FRAME_SAVE_REG_SIZE / 8 == 12);
5921
5922	/* add sp, sp, IEMNATIVE_FRAME_SAVE_REG_SIZE ; */
5923	AssertCompile(IEMNATIVE_FRAME_SAVE_REG_SIZE < 4096);
5924	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(false /fSub/, ARMV8_A64_REG_SP, ARMV8_A64_REG_SP,
5925	IEMNATIVE_FRAME_SAVE_REG_SIZE);
5926
5927	/* retab / ret */
5928	# ifdef RT_OS_DARWIN /** @todo See todo on pacibsp in the prolog. */
5929	if (1)
5930	pu32CodeBuf[off++] = ARMV8_A64_INSTR_RETAB;
5931	else
5932	# endif
5933	pu32CodeBuf[off++] = ARMV8_A64_INSTR_RET;
5934
5935	#else
5936	# error "port me"
5937	#endif
5938	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
5939
5940	return iemNativeEmitRcFiddling(pReNative, off, idxReturn);
5941	}
5942
5943
5944	/**
5945	* Emits a standard prolog.
5946	*/
5947	static uint32_t iemNativeEmitProlog(PIEMRECOMPILERSTATE pReNative, uint32_t off)
5948	{
5949	#ifdef RT_ARCH_AMD64
5950	/*
5951	* Set up a regular xBP stack frame, pushing all non-volatile GPRs,
5952	* reserving 64 bytes for stack variables plus 4 non-register argument
5953	* slots. Fixed register assignment: xBX = pReNative;
5954	*
5955	* Since we always do the same register spilling, we can use the same
5956	* unwind description for all the code.
5957	*/
5958	uint8_t *const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 32);
5959	pbCodeBuf[off++] = 0x50 + X86_GREG_xBP; /* push rbp */
5960	pbCodeBuf[off++] = X86_OP_REX_W; /* mov rbp, rsp */
5961	pbCodeBuf[off++] = 0x8b;
5962	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, X86_GREG_xBP, X86_GREG_xSP);
5963	pbCodeBuf[off++] = 0x50 + X86_GREG_xBX; /* push rbx */
5964	AssertCompile(IEMNATIVE_REG_FIXED_PVMCPU == X86_GREG_xBX);
5965	# ifdef RT_OS_WINDOWS
5966	pbCodeBuf[off++] = X86_OP_REX_W; /* mov rbx, rcx ; RBX = pVCpu */
5967	pbCodeBuf[off++] = 0x8b;
5968	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, X86_GREG_xBX, X86_GREG_xCX);
5969	pbCodeBuf[off++] = 0x50 + X86_GREG_xSI; /* push rsi */
5970	pbCodeBuf[off++] = 0x50 + X86_GREG_xDI; /* push rdi */
5971	# else
5972	pbCodeBuf[off++] = X86_OP_REX_W; /* mov rbx, rdi ; RBX = pVCpu */
5973	pbCodeBuf[off++] = 0x8b;
5974	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, X86_GREG_xBX, X86_GREG_xDI);
5975	# endif
5976	pbCodeBuf[off++] = X86_OP_REX_B; /* push r12 */
5977	pbCodeBuf[off++] = 0x50 + X86_GREG_x12 - 8;
5978	pbCodeBuf[off++] = X86_OP_REX_B; /* push r13 */
5979	pbCodeBuf[off++] = 0x50 + X86_GREG_x13 - 8;
5980	pbCodeBuf[off++] = X86_OP_REX_B; /* push r14 */
5981	pbCodeBuf[off++] = 0x50 + X86_GREG_x14 - 8;
5982	pbCodeBuf[off++] = X86_OP_REX_B; /* push r15 */
5983	pbCodeBuf[off++] = 0x50 + X86_GREG_x15 - 8;
5984
5985	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
5986	/* Save the frame pointer. */
5987	off = iemNativeEmitStoreGprToVCpuU64Ex(pbCodeBuf, off, X86_GREG_xBP, RT_UOFFSETOF(VMCPUCC, iem.s.pvTbFramePointerR3));
5988	# endif
5989
5990	off = iemNativeEmitSubGprImm(pReNative, off, /* sub rsp, byte 28h */
5991	X86_GREG_xSP,
5992	IEMNATIVE_FRAME_ALIGN_SIZE
5993	+ IEMNATIVE_FRAME_VAR_SIZE
5994	+ IEMNATIVE_FRAME_STACK_ARG_COUNT * 8
5995	+ IEMNATIVE_FRAME_SHADOW_ARG_COUNT * 8);
5996	AssertCompile(!(IEMNATIVE_FRAME_VAR_SIZE & 0xf));
5997	AssertCompile(!(IEMNATIVE_FRAME_STACK_ARG_COUNT & 0x1));
5998	AssertCompile(!(IEMNATIVE_FRAME_SHADOW_ARG_COUNT & 0x1));
5999
6000	#elif RT_ARCH_ARM64
6001	/*
6002	* We set up a stack frame exactly like on x86, only we have to push the
6003	* return address our selves here. We save all non-volatile registers.
6004	*/
6005	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 16);
6006
6007	# ifdef RT_OS_DARWIN /** @todo This seems to be requirement by libunwind for JIT FDEs. Investigate further as been unable
6008	* to figure out where the BRK following AUTHB+XPACB stuff comes from in libunwind. It's
6009	* definitely the dwarf stepping code, but till found it's very tedious to figure out whether it's
6010	* in any way conditional, so just emitting this instructions now and hoping for the best... */
6011	/* pacibsp */
6012	pu32CodeBuf[off++] = ARMV8_A64_INSTR_PACIBSP;
6013	# endif
6014
6015	/* stp x19, x20, [sp, #-IEMNATIVE_FRAME_SAVE_REG_SIZE] ; Allocate space for saving registers and place x19+x20 at the bottom. */
6016	AssertCompile(IEMNATIVE_FRAME_SAVE_REG_SIZE < 64*8);
6017	pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(false /fLoad/, 2 /64-bit/, kArm64InstrStLdPairType_PreIndex,
6018	ARMV8_A64_REG_X19, ARMV8_A64_REG_X20, ARMV8_A64_REG_SP,
6019	-IEMNATIVE_FRAME_SAVE_REG_SIZE / 8);
6020	/* Save x21 thru x28 (SP remains unchanged in the kSigned variant). */
6021	pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(false /fLoad/, 2 /64-bit/, kArm64InstrStLdPairType_Signed,
6022	ARMV8_A64_REG_X21, ARMV8_A64_REG_X22, ARMV8_A64_REG_SP, 2);
6023	pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(false /fLoad/, 2 /64-bit/, kArm64InstrStLdPairType_Signed,
6024	ARMV8_A64_REG_X23, ARMV8_A64_REG_X24, ARMV8_A64_REG_SP, 4);
6025	pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(false /fLoad/, 2 /64-bit/, kArm64InstrStLdPairType_Signed,
6026	ARMV8_A64_REG_X25, ARMV8_A64_REG_X26, ARMV8_A64_REG_SP, 6);
6027	pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(false /fLoad/, 2 /64-bit/, kArm64InstrStLdPairType_Signed,
6028	ARMV8_A64_REG_X27, ARMV8_A64_REG_X28, ARMV8_A64_REG_SP, 8);
6029	/* Save the BP and LR (ret address) registers at the top of the frame. */
6030	pu32CodeBuf[off++] = Armv8A64MkInstrStLdPair(false /fLoad/, 2 /64-bit/, kArm64InstrStLdPairType_Signed,
6031	ARMV8_A64_REG_BP, ARMV8_A64_REG_LR, ARMV8_A64_REG_SP, 10);
6032	AssertCompile(IEMNATIVE_FRAME_SAVE_REG_SIZE / 8 == 12);
6033	/* add bp, sp, IEMNATIVE_FRAME_SAVE_REG_SIZE - 16 ; Set BP to point to the old BP stack address. */
6034	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(false /fSub/, ARMV8_A64_REG_BP,
6035	ARMV8_A64_REG_SP, IEMNATIVE_FRAME_SAVE_REG_SIZE - 16);
6036
6037	/* sub sp, sp, IEMNATIVE_FRAME_VAR_SIZE ; Allocate the variable area from SP. */
6038	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(true /fSub/, ARMV8_A64_REG_SP, ARMV8_A64_REG_SP, IEMNATIVE_FRAME_VAR_SIZE);
6039
6040	/* mov r28, r0 */
6041	off = iemNativeEmitLoadGprFromGprEx(pu32CodeBuf, off, IEMNATIVE_REG_FIXED_PVMCPU, IEMNATIVE_CALL_ARG0_GREG);
6042	/* mov r27, r1 */
6043	off = iemNativeEmitLoadGprFromGprEx(pu32CodeBuf, off, IEMNATIVE_REG_FIXED_PCPUMCTX, IEMNATIVE_CALL_ARG1_GREG);
6044
6045	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
6046	/* Save the frame pointer. */
6047	off = iemNativeEmitStoreGprToVCpuU64Ex(pu32CodeBuf, off, ARMV8_A64_REG_BP, RT_UOFFSETOF(VMCPUCC, iem.s.pvTbFramePointerR3),
6048	ARMV8_A64_REG_X2);
6049	# endif
6050
6051	#else
6052	# error "port me"
6053	#endif
6054	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
6055	return off;
6056	}
6057
6058
6059
6060
6061	/*********************************************************************************************************************************
6062	* Emitters for IEM_MC_BEGIN and IEM_MC_END. *
6063	*********************************************************************************************************************************/
6064
6065	#define IEM_MC_BEGIN(a_cArgs, a_cLocals, a_fMcFlags, a_fCImplFlags) \
6066	{ \
6067	Assert(pReNative->Core.bmVars == 0); \
6068	Assert(pReNative->Core.u64ArgVars == UINT64_MAX); \
6069	Assert(pReNative->Core.bmStack == 0); \
6070	pReNative->fMc = (a_fMcFlags); \
6071	pReNative->fCImpl = (a_fCImplFlags); \
6072	pReNative->cArgs = ((a_cArgs) + iemNativeArgGetHiddenArgCount(pReNative))
6073
6074	/** We have to get to the end in recompilation mode, as otherwise we won't
6075	* generate code for all the IEM_MC_IF_XXX branches. */
6076	#define IEM_MC_END() \
6077	iemNativeVarFreeAll(pReNative); \
6078	} return off
6079
6080
6081
6082	/*********************************************************************************************************************************
6083	* Emitters for standalone C-implementation deferals (IEM_MC_DEFER_TO_CIMPL_XXXX) *
6084	*********************************************************************************************************************************/
6085
6086	#define IEM_MC_DEFER_TO_CIMPL_0_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl) \
6087	pReNative->fMc = 0; \
6088	pReNative->fCImpl = (a_fFlags); \
6089	return iemNativeEmitCImplCall0(pReNative, off, pCallEntry->idxInstr, a_fGstShwFlush, (uintptr_t)a_pfnCImpl, a_cbInstr) /** @todo not used ... */
6090
6091
6092	#define IEM_MC_DEFER_TO_CIMPL_1_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) \
6093	pReNative->fMc = 0; \
6094	pReNative->fCImpl = (a_fFlags); \
6095	return iemNativeEmitCImplCall1(pReNative, off, pCallEntry->idxInstr, a_fGstShwFlush, (uintptr_t)a_pfnCImpl, a_cbInstr, a0)
6096
6097	DECL_INLINE_THROW(uint32_t) iemNativeEmitCImplCall1(PIEMRECOMPILERSTATE pReNative, uint32_t off,
6098	uint8_t idxInstr, uint64_t a_fGstShwFlush,
6099	uintptr_t pfnCImpl, uint8_t cbInstr, uint64_t uArg0)
6100	{
6101	return iemNativeEmitCImplCall(pReNative, off, idxInstr, a_fGstShwFlush, pfnCImpl, cbInstr, 1, uArg0, 0, 0);
6102	}
6103
6104
6105	#define IEM_MC_DEFER_TO_CIMPL_2_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) \
6106	pReNative->fMc = 0; \
6107	pReNative->fCImpl = (a_fFlags); \
6108	return iemNativeEmitCImplCall2(pReNative, off, pCallEntry->idxInstr, a_fGstShwFlush, \
6109	(uintptr_t)a_pfnCImpl, a_cbInstr, a0, a1)
6110
6111	DECL_INLINE_THROW(uint32_t) iemNativeEmitCImplCall2(PIEMRECOMPILERSTATE pReNative, uint32_t off,
6112	uint8_t idxInstr, uint64_t a_fGstShwFlush,
6113	uintptr_t pfnCImpl, uint8_t cbInstr, uint64_t uArg0, uint64_t uArg1)
6114	{
6115	return iemNativeEmitCImplCall(pReNative, off, idxInstr, a_fGstShwFlush, pfnCImpl, cbInstr, 2, uArg0, uArg1, 0);
6116	}
6117
6118
6119	#define IEM_MC_DEFER_TO_CIMPL_3_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) \
6120	pReNative->fMc = 0; \
6121	pReNative->fCImpl = (a_fFlags); \
6122	return iemNativeEmitCImplCall3(pReNative, off, pCallEntry->idxInstr, a_fGstShwFlush, \
6123	(uintptr_t)a_pfnCImpl, a_cbInstr, a0, a1, a2)
6124
6125	DECL_INLINE_THROW(uint32_t) iemNativeEmitCImplCall3(PIEMRECOMPILERSTATE pReNative, uint32_t off,
6126	uint8_t idxInstr, uint64_t a_fGstShwFlush,
6127	uintptr_t pfnCImpl, uint8_t cbInstr, uint64_t uArg0, uint64_t uArg1,
6128	uint64_t uArg2)
6129	{
6130	return iemNativeEmitCImplCall(pReNative, off, idxInstr, a_fGstShwFlush, pfnCImpl, cbInstr, 3, uArg0, uArg1, uArg2);
6131	}
6132
6133
6134
6135	/*********************************************************************************************************************************
6136	* Emitters for advancing PC/RIP/EIP/IP (IEM_MC_ADVANCE_RIP_AND_FINISH_XXX) *
6137	*********************************************************************************************************************************/
6138
6139	/** Emits the flags check for IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64_WITH_FLAGS
6140	* and the other _WITH_FLAGS MCs, see iemRegFinishClearingRF. */
6141	DECL_INLINE_THROW(uint32_t)
6142	iemNativeEmitFinishInstructionFlagsCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off)
6143	{
6144	/*
6145	* If its not just X86_EFL_RF and CPUMCTX_INHIBIT_SHADOW that are set, we
6146	* return with special status code and make the execution loop deal with
6147	* this. If TF or CPUMCTX_DBG_HIT_DRX_MASK triggers, we have to raise an
6148	* exception and won't continue execution. While CPUMCTX_DBG_DBGF_MASK
6149	* could continue w/o interruption, it probably will drop into the
6150	* debugger, so not worth the effort of trying to services it here and we
6151	* just lump it in with the handling of the others.
6152	*
6153	* To simplify the code and the register state management even more (wrt
6154	* immediate in AND operation), we always update the flags and skip the
6155	* extra check associated conditional jump.
6156	*/
6157	AssertCompile( (X86_EFL_TF \| X86_EFL_RF \| CPUMCTX_INHIBIT_SHADOW \| CPUMCTX_DBG_HIT_DRX_MASK \| CPUMCTX_DBG_DBGF_MASK)
6158	<= UINT32_MAX);
6159	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
6160	AssertMsg( pReNative->idxCurCall == 0
6161	\|\| IEMLIVENESS_STATE_IS_INPUT_EXPECTED(iemNativeLivenessGetStateByGstRegEx(&pReNative->paLivenessEntries[pReNative->idxCurCall - 1], IEMLIVENESSBIT_IDX_EFL_OTHER)),
6162	("Efl_Other - %u\n", iemNativeLivenessGetStateByGstRegEx(&pReNative->paLivenessEntries[pReNative->idxCurCall - 1], IEMLIVENESSBIT_IDX_EFL_OTHER)));
6163	#endif
6164
6165	uint8_t const idxEflReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_EFlags,
6166	kIemNativeGstRegUse_ForUpdate, false /fNoVolatileRegs/,
6167	true /fSkipLivenessAssert/);
6168	off = iemNativeEmitTestAnyBitsInGprAndJmpToLabelIfAnySet(pReNative, off, idxEflReg,
6169	X86_EFL_TF \| CPUMCTX_DBG_HIT_DRX_MASK \| CPUMCTX_DBG_DBGF_MASK,
6170	iemNativeLabelCreate(pReNative, kIemNativeLabelType_ReturnWithFlags));
6171	off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxEflReg, ~(uint32_t)(X86_EFL_RF \| CPUMCTX_INHIBIT_SHADOW));
6172	off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxEflReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.eflags));
6173
6174	/* Free but don't flush the EFLAGS register. */
6175	iemNativeRegFreeTmp(pReNative, idxEflReg);
6176
6177	return off;
6178	}
6179
6180
6181	/** The VINF_SUCCESS dummy. */
6182	template<int const a_rcNormal>
6183	DECL_FORCE_INLINE(uint32_t)
6184	iemNativeEmitFinishInstructionWithStatus(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr)
6185	{
6186	AssertCompile(a_rcNormal == VINF_SUCCESS \|\| a_rcNormal == VINF_IEM_REEXEC_BREAK);
6187	if (a_rcNormal != VINF_SUCCESS)
6188	{
6189	#ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
6190	off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr));
6191	#else
6192	RT_NOREF_PV(idxInstr);
6193	#endif
6194	return iemNativeEmitJmpToNewLabel(pReNative, off, kIemNativeLabelType_ReturnBreak);
6195	}
6196	return off;
6197	}
6198
6199
6200	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64(a_cbInstr, a_rcNormal) \
6201	off = iemNativeEmitAddToRip64AndFinishingNoFlags(pReNative, off, (a_cbInstr)); \
6202	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6203
6204	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_cbInstr, a_rcNormal) \
6205	off = iemNativeEmitAddToRip64AndFinishingNoFlags(pReNative, off, (a_cbInstr)); \
6206	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \
6207	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6208
6209	/** Same as iemRegAddToRip64AndFinishingNoFlags. */
6210	DECL_INLINE_THROW(uint32_t)
6211	iemNativeEmitAddToRip64AndFinishingNoFlags(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cbInstr)
6212	{
6213	/* Allocate a temporary PC register. */
6214	uint8_t const idxPcReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Pc, kIemNativeGstRegUse_ForUpdate);
6215
6216	/* Perform the addition and store the result. */
6217	off = iemNativeEmitAddGprImm8(pReNative, off, idxPcReg, cbInstr);
6218	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
6219
6220	/* Free but don't flush the PC register. */
6221	iemNativeRegFreeTmp(pReNative, idxPcReg);
6222
6223	return off;
6224	}
6225
6226
6227	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32(a_cbInstr, a_rcNormal) \
6228	off = iemNativeEmitAddToEip32AndFinishingNoFlags(pReNative, off, (a_cbInstr)); \
6229	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6230
6231	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_cbInstr, a_rcNormal) \
6232	off = iemNativeEmitAddToEip32AndFinishingNoFlags(pReNative, off, (a_cbInstr)); \
6233	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \
6234	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6235
6236	/** Same as iemRegAddToEip32AndFinishingNoFlags. */
6237	DECL_INLINE_THROW(uint32_t)
6238	iemNativeEmitAddToEip32AndFinishingNoFlags(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cbInstr)
6239	{
6240	/* Allocate a temporary PC register. */
6241	uint8_t const idxPcReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Pc, kIemNativeGstRegUse_ForUpdate);
6242
6243	/* Perform the addition and store the result. */
6244	off = iemNativeEmitAddGpr32Imm8(pReNative, off, idxPcReg, cbInstr);
6245	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
6246
6247	/* Free but don't flush the PC register. */
6248	iemNativeRegFreeTmp(pReNative, idxPcReg);
6249
6250	return off;
6251	}
6252
6253
6254	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16(a_cbInstr, a_rcNormal) \
6255	off = iemNativeEmitAddToIp16AndFinishingNoFlags(pReNative, off, (a_cbInstr)); \
6256	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6257
6258	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_cbInstr, a_rcNormal) \
6259	off = iemNativeEmitAddToIp16AndFinishingNoFlags(pReNative, off, (a_cbInstr)); \
6260	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \
6261	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6262
6263	/** Same as iemRegAddToIp16AndFinishingNoFlags. */
6264	DECL_INLINE_THROW(uint32_t)
6265	iemNativeEmitAddToIp16AndFinishingNoFlags(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cbInstr)
6266	{
6267	/* Allocate a temporary PC register. */
6268	uint8_t const idxPcReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Pc, kIemNativeGstRegUse_ForUpdate);
6269
6270	/* Perform the addition and store the result. */
6271	off = iemNativeEmitAddGpr32Imm8(pReNative, off, idxPcReg, cbInstr);
6272	off = iemNativeEmitClear16UpGpr(pReNative, off, idxPcReg);
6273	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
6274
6275	/* Free but don't flush the PC register. */
6276	iemNativeRegFreeTmp(pReNative, idxPcReg);
6277
6278	return off;
6279	}
6280
6281
6282
6283	/*********************************************************************************************************************************
6284	* Emitters for changing PC/RIP/EIP/IP with a relative jump (IEM_MC_REL_JMP_XXX_AND_FINISH_XXX). *
6285	*********************************************************************************************************************************/
6286
6287	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
6288	off = iemNativeEmitRip64RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (int8_t)(a_i8), \
6289	(a_enmEffOpSize), pCallEntry->idxInstr); \
6290	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6291
6292	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
6293	off = iemNativeEmitRip64RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (int8_t)(a_i8), \
6294	(a_enmEffOpSize), pCallEntry->idxInstr); \
6295	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \
6296	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6297
6298	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64(a_i16, a_cbInstr, a_rcNormal) \
6299	off = iemNativeEmitRip64RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (int16_t)(a_i16), \
6300	IEMMODE_16BIT, pCallEntry->idxInstr); \
6301	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6302
6303	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i16, a_cbInstr, a_rcNormal) \
6304	off = iemNativeEmitRip64RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (int16_t)(a_i16), \
6305	IEMMODE_16BIT, pCallEntry->idxInstr); \
6306	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \
6307	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6308
6309	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64(a_i32, a_cbInstr, a_rcNormal) \
6310	off = iemNativeEmitRip64RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (a_i32), \
6311	IEMMODE_64BIT, pCallEntry->idxInstr); \
6312	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6313
6314	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i32, a_cbInstr, a_rcNormal) \
6315	off = iemNativeEmitRip64RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (a_i32), \
6316	IEMMODE_64BIT, pCallEntry->idxInstr); \
6317	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \
6318	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6319
6320	/** Same as iemRegRip64RelativeJumpS8AndFinishNoFlags,
6321	* iemRegRip64RelativeJumpS16AndFinishNoFlags and
6322	* iemRegRip64RelativeJumpS32AndFinishNoFlags. */
6323	DECL_INLINE_THROW(uint32_t)
6324	iemNativeEmitRip64RelativeJumpAndFinishingNoFlags(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cbInstr,
6325	int32_t offDisp, IEMMODE enmEffOpSize, uint8_t idxInstr)
6326	{
6327	Assert(enmEffOpSize == IEMMODE_64BIT \|\| enmEffOpSize == IEMMODE_16BIT);
6328
6329	/* We speculatively modify PC and may raise #GP(0), so make sure the right values are in CPUMCTX. */
6330	off = iemNativeRegFlushPendingWrites(pReNative, off);
6331
6332	/* Allocate a temporary PC register. */
6333	uint8_t const idxPcReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Pc, kIemNativeGstRegUse_ForUpdate);
6334
6335	/* Perform the addition. */
6336	off = iemNativeEmitAddGprImm(pReNative, off, idxPcReg, (int64_t)offDisp + cbInstr);
6337
6338	if (RT_LIKELY(enmEffOpSize == IEMMODE_64BIT))
6339	{
6340	/* Check that the address is canonical, raising #GP(0) + exit TB if it isn't. */
6341	off = iemNativeEmitCheckGprCanonicalMaybeRaiseGp0(pReNative, off, idxPcReg, idxInstr);
6342	}
6343	else
6344	{
6345	/* Just truncate the result to 16-bit IP. */
6346	Assert(enmEffOpSize == IEMMODE_16BIT);
6347	off = iemNativeEmitClear16UpGpr(pReNative, off, idxPcReg);
6348	}
6349	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
6350
6351	/* Free but don't flush the PC register. */
6352	iemNativeRegFreeTmp(pReNative, idxPcReg);
6353
6354	return off;
6355	}
6356
6357
6358	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
6359	off = iemNativeEmitEip32RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (int8_t)(a_i8), \
6360	(a_enmEffOpSize), pCallEntry->idxInstr); \
6361	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6362
6363	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i8, a_cbInstr, a_enmEffOpSize, a_rcNormal) \
6364	off = iemNativeEmitEip32RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (int8_t)(a_i8), \
6365	(a_enmEffOpSize), pCallEntry->idxInstr); \
6366	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \
6367	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6368
6369	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32(a_i16, a_cbInstr, a_rcNormal) \
6370	off = iemNativeEmitEip32RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (int16_t)(a_i16), \
6371	IEMMODE_16BIT, pCallEntry->idxInstr); \
6372	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6373
6374	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i16, a_cbInstr, a_rcNormal) \
6375	off = iemNativeEmitEip32RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (int16_t)(a_i16), \
6376	IEMMODE_16BIT, pCallEntry->idxInstr); \
6377	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \
6378	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6379
6380	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32(a_i32, a_cbInstr, a_rcNormal) \
6381	off = iemNativeEmitEip32RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (a_i32), \
6382	IEMMODE_32BIT, pCallEntry->idxInstr); \
6383	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6384
6385	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i32, a_cbInstr, a_rcNormal) \
6386	off = iemNativeEmitEip32RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (a_i32), \
6387	IEMMODE_32BIT, pCallEntry->idxInstr); \
6388	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \
6389	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6390
6391	/** Same as iemRegEip32RelativeJumpS8AndFinishNoFlags,
6392	* iemRegEip32RelativeJumpS16AndFinishNoFlags and
6393	* iemRegEip32RelativeJumpS32AndFinishNoFlags. */
6394	DECL_INLINE_THROW(uint32_t)
6395	iemNativeEmitEip32RelativeJumpAndFinishingNoFlags(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cbInstr,
6396	int32_t offDisp, IEMMODE enmEffOpSize, uint8_t idxInstr)
6397	{
6398	Assert(enmEffOpSize == IEMMODE_32BIT \|\| enmEffOpSize == IEMMODE_16BIT);
6399
6400	/* We speculatively modify PC and may raise #GP(0), so make sure the right values are in CPUMCTX. */
6401	off = iemNativeRegFlushPendingWrites(pReNative, off);
6402
6403	/* Allocate a temporary PC register. */
6404	uint8_t const idxPcReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Pc, kIemNativeGstRegUse_ForUpdate);
6405
6406	/* Perform the addition. */
6407	off = iemNativeEmitAddGpr32Imm(pReNative, off, idxPcReg, offDisp + cbInstr);
6408
6409	/* Truncate the result to 16-bit IP if the operand size is 16-bit. */
6410	if (enmEffOpSize == IEMMODE_16BIT)
6411	off = iemNativeEmitClear16UpGpr(pReNative, off, idxPcReg);
6412
6413	/* Perform limit checking, potentially raising #GP(0) and exit the TB. */
6414	/** @todo we can skip this in 32-bit FLAT mode. */
6415	off = iemNativeEmitCheckGpr32AgainstCsSegLimitMaybeRaiseGp0(pReNative, off, idxPcReg, idxInstr);
6416
6417	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
6418
6419	/* Free but don't flush the PC register. */
6420	iemNativeRegFreeTmp(pReNative, idxPcReg);
6421
6422	return off;
6423	}
6424
6425
6426	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16(a_i8, a_cbInstr, a_rcNormal) \
6427	off = iemNativeEmitIp16RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (int8_t)(a_i8), pCallEntry->idxInstr); \
6428	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6429
6430	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i8, a_cbInstr, a_rcNormal) \
6431	off = iemNativeEmitIp16RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (int8_t)(a_i8), pCallEntry->idxInstr); \
6432	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \
6433	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6434
6435	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16(a_i16, a_cbInstr, a_rcNormal) \
6436	off = iemNativeEmitIp16RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (int16_t)(a_i16), pCallEntry->idxInstr); \
6437	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6438
6439	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i16, a_cbInstr, a_rcNormal) \
6440	off = iemNativeEmitIp16RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (int16_t)(a_i16), pCallEntry->idxInstr); \
6441	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \
6442	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6443
6444	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC16(a_i32, a_cbInstr, a_rcNormal) \
6445	off = iemNativeEmitIp16RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (a_i32), pCallEntry->idxInstr); \
6446	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6447
6448	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i32, a_cbInstr, a_rcNormal) \
6449	off = iemNativeEmitIp16RelativeJumpAndFinishingNoFlags(pReNative, off, (a_cbInstr), (a_i32), pCallEntry->idxInstr); \
6450	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \
6451	off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal>(pReNative, off, pCallEntry->idxInstr)
6452
6453	/** Same as iemRegIp16RelativeJumpS8AndFinishNoFlags. */
6454	DECL_INLINE_THROW(uint32_t)
6455	iemNativeEmitIp16RelativeJumpAndFinishingNoFlags(PIEMRECOMPILERSTATE pReNative, uint32_t off,
6456	uint8_t cbInstr, int32_t offDisp, uint8_t idxInstr)
6457	{
6458	/* We speculatively modify PC and may raise #GP(0), so make sure the right values are in CPUMCTX. */
6459	off = iemNativeRegFlushPendingWrites(pReNative, off);
6460
6461	/* Allocate a temporary PC register. */
6462	uint8_t const idxPcReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Pc, kIemNativeGstRegUse_ForUpdate);
6463
6464	/* Perform the addition, clamp the result, check limit (may #GP(0) + exit TB) and store the result. */
6465	off = iemNativeEmitAddGpr32Imm(pReNative, off, idxPcReg, offDisp + cbInstr);
6466	off = iemNativeEmitClear16UpGpr(pReNative, off, idxPcReg);
6467	off = iemNativeEmitCheckGpr32AgainstCsSegLimitMaybeRaiseGp0(pReNative, off, idxPcReg, idxInstr);
6468	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
6469
6470	/* Free but don't flush the PC register. */
6471	iemNativeRegFreeTmp(pReNative, idxPcReg);
6472
6473	return off;
6474	}
6475
6476
6477
6478	/*********************************************************************************************************************************
6479	* Emitters for changing PC/RIP/EIP/IP with a indirect jump (IEM_MC_SET_RIP_UXX_AND_FINISH). *
6480	*********************************************************************************************************************************/
6481
6482	/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for pre-386 targets. */
6483	#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC16(a_u16NewIP) \
6484	off = iemNativeEmitRipJumpNoFlags(pReNative, off, (a_u16NewIP), false /f64Bit/, pCallEntry->idxInstr, sizeof(uint16_t))
6485
6486	/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for 386+ targets. */
6487	#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC32(a_u16NewIP) \
6488	off = iemNativeEmitRipJumpNoFlags(pReNative, off, (a_u16NewIP), false /f64Bit/, pCallEntry->idxInstr, sizeof(uint16_t))
6489
6490	/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for use in 64-bit code. */
6491	#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC64(a_u16NewIP) \
6492	off = iemNativeEmitRipJumpNoFlags(pReNative, off, (a_u16NewIP), true /f64Bit/, pCallEntry->idxInstr, sizeof(uint16_t))
6493
6494	/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for pre-386 targets that checks and
6495	* clears flags. */
6496	#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_u16NewIP) \
6497	IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC16(a_u16NewIP); \
6498	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off)
6499
6500	/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for 386+ targets that checks and
6501	* clears flags. */
6502	#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_u16NewIP) \
6503	IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC32(a_u16NewIP); \
6504	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off)
6505
6506	/** Variant of IEM_MC_SET_RIP_U16_AND_FINISH for use in 64-bit code that checks and
6507	* clears flags. */
6508	#define IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u16NewIP) \
6509	IEM_MC_SET_RIP_U16_AND_FINISH_THREADED_PC64(a_u16NewIP); \
6510	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off)
6511
6512	#undef IEM_MC_SET_RIP_U16_AND_FINISH
6513
6514
6515	/** Variant of IEM_MC_SET_RIP_U32_AND_FINISH for 386+ targets. */
6516	#define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC32(a_u32NewEIP) \
6517	off = iemNativeEmitRipJumpNoFlags(pReNative, off, (a_u32NewEIP), false /f64Bit/, pCallEntry->idxInstr, sizeof(uint32_t))
6518
6519	/** Variant of IEM_MC_SET_RIP_U32_AND_FINISH for use in 64-bit code. */
6520	#define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC64(a_u32NewEIP) \
6521	off = iemNativeEmitRipJumpNoFlags(pReNative, off, (a_u32NewEIP), true /f64Bit/, pCallEntry->idxInstr, sizeof(uint32_t))
6522
6523	/** Variant of IEM_MC_SET_RIP_U32_AND_FINISH for 386+ targets that checks and
6524	* clears flags. */
6525	#define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_u32NewEIP) \
6526	IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC32(a_u32NewEIP); \
6527	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off)
6528
6529	/** Variant of IEM_MC_SET_RIP_U32_AND_FINISH for use in 64-bit code that checks
6530	* and clears flags. */
6531	#define IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u32NewEIP) \
6532	IEM_MC_SET_RIP_U32_AND_FINISH_THREADED_PC64(a_u32NewEIP); \
6533	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off)
6534
6535	#undef IEM_MC_SET_RIP_U32_AND_FINISH
6536
6537
6538	/** Variant of IEM_MC_SET_RIP_U64_AND_FINISH for use in 64-bit code. */
6539	#define IEM_MC_SET_RIP_U64_AND_FINISH_THREADED_PC64(a_u64NewEIP) \
6540	off = iemNativeEmitRipJumpNoFlags(pReNative, off, (a_u64NewEIP), true /f64Bit/, pCallEntry->idxInstr, sizeof(uint64_t))
6541
6542	/** Variant of IEM_MC_SET_RIP_U64_AND_FINISH for use in 64-bit code that checks
6543	* and clears flags. */
6544	#define IEM_MC_SET_RIP_U64_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_u64NewEIP) \
6545	IEM_MC_SET_RIP_U64_AND_FINISH_THREADED_PC64(a_u64NewEIP); \
6546	off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off)
6547
6548	#undef IEM_MC_SET_RIP_U64_AND_FINISH
6549
6550
6551	/** Same as iemRegRipJumpU16AndFinishNoFlags,
6552	* iemRegRipJumpU32AndFinishNoFlags and iemRegRipJumpU64AndFinishNoFlags. */
6553	DECL_INLINE_THROW(uint32_t)
6554	iemNativeEmitRipJumpNoFlags(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarPc, bool f64Bit,
6555	uint8_t idxInstr, uint8_t cbVar)
6556	{
6557	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarPc);
6558	Assert(pReNative->Core.aVars[idxVarPc].cbVar == cbVar);
6559
6560	/* We speculatively modify PC and may raise #GP(0), so make sure the right values are in CPUMCTX. */
6561	off = iemNativeRegFlushPendingWrites(pReNative, off);
6562
6563	/* Get a register with the new PC loaded from idxVarPc.
6564	Note! This ASSUMES that the high bits of the GPR is zeroed. */
6565	uint8_t const idxPcReg = iemNativeVarRegisterAcquireForGuestReg(pReNative, idxVarPc, kIemNativeGstReg_Pc, &off);
6566
6567	/* Check limit (may #GP(0) + exit TB). */
6568	if (!f64Bit)
6569	/** @todo we can skip this test in FLAT 32-bit mode. */
6570	off = iemNativeEmitCheckGpr32AgainstCsSegLimitMaybeRaiseGp0(pReNative, off, idxPcReg, idxInstr);
6571	/* Check that the address is canonical, raising #GP(0) + exit TB if it isn't. */
6572	else if (cbVar > sizeof(uint32_t))
6573	off = iemNativeEmitCheckGprCanonicalMaybeRaiseGp0(pReNative, off, idxPcReg, idxInstr);
6574
6575	/* Store the result. */
6576	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxPcReg, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rip));
6577
6578	iemNativeVarRegisterRelease(pReNative, idxVarPc);
6579	/** @todo implictly free the variable? */
6580
6581	return off;
6582	}
6583
6584
6585
6586	/*********************************************************************************************************************************
6587	* Emitters for conditionals (IEM_MC_IF_XXX, IEM_MC_ELSE, IEM_MC_ENDIF) *
6588	*********************************************************************************************************************************/
6589
6590	/**
6591	* Pushes an IEM_MC_IF_XXX onto the condition stack.
6592	*
6593	* @returns Pointer to the condition stack entry on success, NULL on failure
6594	* (too many nestings)
6595	*/
6596	DECL_INLINE_THROW(PIEMNATIVECOND) iemNativeCondPushIf(PIEMRECOMPILERSTATE pReNative)
6597	{
6598	uint32_t const idxStack = pReNative->cCondDepth;
6599	AssertStmt(idxStack < RT_ELEMENTS(pReNative->aCondStack), IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_COND_TOO_DEEPLY_NESTED));
6600
6601	PIEMNATIVECOND const pEntry = &pReNative->aCondStack[idxStack];
6602	pReNative->cCondDepth = (uint8_t)(idxStack + 1);
6603
6604	uint16_t const uCondSeqNo = ++pReNative->uCondSeqNo;
6605	pEntry->fInElse = false;
6606	pEntry->idxLabelElse = iemNativeLabelCreate(pReNative, kIemNativeLabelType_Else, UINT32_MAX /offWhere/, uCondSeqNo);
6607	pEntry->idxLabelEndIf = iemNativeLabelCreate(pReNative, kIemNativeLabelType_Endif, UINT32_MAX /offWhere/, uCondSeqNo);
6608
6609	return pEntry;
6610	}
6611
6612
6613	/**
6614	* Start of the if-block, snapshotting the register and variable state.
6615	*/
6616	DECL_INLINE_THROW(void)
6617	iemNativeCondStartIfBlock(PIEMRECOMPILERSTATE pReNative, uint32_t offIfBlock, uint32_t idxLabelIf = UINT32_MAX)
6618	{
6619	Assert(offIfBlock != UINT32_MAX);
6620	Assert(pReNative->cCondDepth > 0 && pReNative->cCondDepth <= RT_ELEMENTS(pReNative->aCondStack));
6621	PIEMNATIVECOND const pEntry = &pReNative->aCondStack[pReNative->cCondDepth - 1];
6622	Assert(!pEntry->fInElse);
6623
6624	/* Define the start of the IF block if request or for disassembly purposes. */
6625	if (idxLabelIf != UINT32_MAX)
6626	iemNativeLabelDefine(pReNative, idxLabelIf, offIfBlock);
6627	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
6628	else
6629	iemNativeLabelCreate(pReNative, kIemNativeLabelType_If, offIfBlock, pReNative->paLabels[pEntry->idxLabelElse].uData);
6630	#else
6631	RT_NOREF(offIfBlock);
6632	#endif
6633
6634	/* Copy the initial state so we can restore it in the 'else' block. */
6635	pEntry->InitialState = pReNative->Core;
6636	}
6637
6638
6639	#define IEM_MC_ELSE() } while (0); \
6640	off = iemNativeEmitElse(pReNative, off); \
6641	do {
6642
6643	/** Emits code related to IEM_MC_ELSE. */
6644	DECL_INLINE_THROW(uint32_t) iemNativeEmitElse(PIEMRECOMPILERSTATE pReNative, uint32_t off)
6645	{
6646	/* Check sanity and get the conditional stack entry. */
6647	Assert(off != UINT32_MAX);
6648	Assert(pReNative->cCondDepth > 0 && pReNative->cCondDepth <= RT_ELEMENTS(pReNative->aCondStack));
6649	PIEMNATIVECOND const pEntry = &pReNative->aCondStack[pReNative->cCondDepth - 1];
6650	Assert(!pEntry->fInElse);
6651
6652	/* Jump to the endif */
6653	off = iemNativeEmitJmpToLabel(pReNative, off, pEntry->idxLabelEndIf);
6654
6655	/* Define the else label and enter the else part of the condition. */
6656	iemNativeLabelDefine(pReNative, pEntry->idxLabelElse, off);
6657	pEntry->fInElse = true;
6658
6659	/* Snapshot the core state so we can do a merge at the endif and restore
6660	the snapshot we took at the start of the if-block. */
6661	pEntry->IfFinalState = pReNative->Core;
6662	pReNative->Core = pEntry->InitialState;
6663
6664	return off;
6665	}
6666
6667
6668	#define IEM_MC_ENDIF() } while (0); \
6669	off = iemNativeEmitEndIf(pReNative, off)
6670
6671	/** Emits code related to IEM_MC_ENDIF. */
6672	DECL_INLINE_THROW(uint32_t) iemNativeEmitEndIf(PIEMRECOMPILERSTATE pReNative, uint32_t off)
6673	{
6674	/* Check sanity and get the conditional stack entry. */
6675	Assert(off != UINT32_MAX);
6676	Assert(pReNative->cCondDepth > 0 && pReNative->cCondDepth <= RT_ELEMENTS(pReNative->aCondStack));
6677	PIEMNATIVECOND const pEntry = &pReNative->aCondStack[pReNative->cCondDepth - 1];
6678
6679	/*
6680	* Now we have find common group with the core state at the end of the
6681	* if-final. Use the smallest common denominator and just drop anything
6682	* that isn't the same in both states.
6683	*/
6684	/** @todo We could, maybe, shuffle registers around if we thought it helpful,
6685	* which is why we're doing this at the end of the else-block.
6686	* But we'd need more info about future for that to be worth the effort. */
6687	PCIEMNATIVECORESTATE const pOther = pEntry->fInElse ? &pEntry->IfFinalState : &pEntry->InitialState;
6688	if (memcmp(&pReNative->Core, pOther, sizeof(*pOther)) != 0)
6689	{
6690	/* shadow guest stuff first. */
6691	uint64_t fGstRegs = pReNative->Core.bmGstRegShadows;
6692	if (fGstRegs)
6693	{
6694	Assert(pReNative->Core.bmHstRegsWithGstShadow != 0);
6695	do
6696	{
6697	unsigned idxGstReg = ASMBitFirstSetU64(fGstRegs) - 1;
6698	fGstRegs &= ~RT_BIT_64(idxGstReg);
6699
6700	uint8_t const idxHstReg = pReNative->Core.aidxGstRegShadows[idxGstReg];
6701	if ( !(pOther->bmGstRegShadows & RT_BIT_64(idxGstReg))
6702	\|\| idxHstReg != pOther->aidxGstRegShadows[idxGstReg])
6703	{
6704	Log12(("iemNativeEmitEndIf: dropping gst %s from hst %s\n",
6705	g_aGstShadowInfo[idxGstReg].pszName, g_apszIemNativeHstRegNames[idxHstReg]));
6706	iemNativeRegClearGstRegShadowing(pReNative, idxHstReg, off);
6707	}
6708	} while (fGstRegs);
6709	}
6710	else
6711	Assert(pReNative->Core.bmHstRegsWithGstShadow == 0);
6712
6713	/* Check variables next. For now we must require them to be identical
6714	or stuff we can recreate. */
6715	Assert(pReNative->Core.u64ArgVars == pOther->u64ArgVars);
6716	uint32_t fVars = pReNative->Core.bmVars \| pOther->bmVars;
6717	if (fVars)
6718	{
6719	uint32_t const fVarsMustRemove = pReNative->Core.bmVars ^ pOther->bmVars;
6720	do
6721	{
6722	unsigned idxVar = ASMBitFirstSetU32(fVars) - 1;
6723	fVars &= ~RT_BIT_32(idxVar);
6724
6725	if (!(fVarsMustRemove & RT_BIT_32(idxVar)))
6726	{
6727	if (pReNative->Core.aVars[idxVar].idxReg == pOther->aVars[idxVar].idxReg)
6728	continue;
6729	if (pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_Stack)
6730	{
6731	uint8_t const idxHstReg = pReNative->Core.aVars[idxVar].idxReg;
6732	if (idxHstReg != UINT8_MAX)
6733	{
6734	pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
6735	pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
6736	Log12(("iemNativeEmitEndIf: Dropping hst reg %s for var #%u\n",
6737	g_apszIemNativeHstRegNames[idxHstReg], idxVar));
6738	}
6739	continue;
6740	}
6741	}
6742	else if (!(pReNative->Core.bmVars & RT_BIT_32(idxVar)))
6743	continue;
6744
6745	/* Irreconcilable, so drop it. */
6746	uint8_t const idxHstReg = pReNative->Core.aVars[idxVar].idxReg;
6747	if (idxHstReg != UINT8_MAX)
6748	{
6749	pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
6750	pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
6751	Log12(("iemNativeEmitEndIf: Dropping hst reg %s for var #%u (also dropped)\n",
6752	g_apszIemNativeHstRegNames[idxHstReg], idxVar));
6753	}
6754	Log11(("iemNativeEmitEndIf: Freeing variable #%u\n", idxVar));
6755	pReNative->Core.bmVars &= ~RT_BIT_32(idxVar);
6756	} while (fVars);
6757	}
6758
6759	/* Finally, check that the host register allocations matches. */
6760	AssertMsgStmt(pReNative->Core.bmHstRegs == pOther->bmHstRegs,
6761	("Core.bmHstRegs=%#x pOther->bmHstRegs=%#x - %#x\n",
6762	pReNative->Core.bmHstRegs, pOther->bmHstRegs, pReNative->Core.bmHstRegs ^ pOther->bmHstRegs),
6763	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_COND_ENDIF_RECONCILIATION_FAILED));
6764	}
6765
6766	/*
6767	* Define the endif label and maybe the else one if we're still in the 'if' part.
6768	*/
6769	if (!pEntry->fInElse)
6770	iemNativeLabelDefine(pReNative, pEntry->idxLabelElse, off);
6771	else
6772	Assert(pReNative->paLabels[pEntry->idxLabelElse].off <= off);
6773	iemNativeLabelDefine(pReNative, pEntry->idxLabelEndIf, off);
6774
6775	/* Pop the conditional stack.*/
6776	pReNative->cCondDepth -= 1;
6777
6778	return off;
6779	}
6780
6781
6782	#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) \
6783	off = iemNativeEmitIfEflagAnysBitsSet(pReNative, off, (a_fBits)); \
6784	do {
6785
6786	/** Emits code for IEM_MC_IF_EFL_ANY_BITS_SET. */
6787	DECL_INLINE_THROW(uint32_t) iemNativeEmitIfEflagAnysBitsSet(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fBitsInEfl)
6788	{
6789	PIEMNATIVECOND const pEntry = iemNativeCondPushIf(pReNative);
6790
6791	/* Get the eflags. */
6792	uint8_t const idxEflReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_EFlags,
6793	kIemNativeGstRegUse_ReadOnly);
6794
6795	/* Test and jump. */
6796	off = iemNativeEmitTestAnyBitsInGprAndJmpToLabelIfNoneSet(pReNative, off, idxEflReg, fBitsInEfl, pEntry->idxLabelElse);
6797
6798	/* Free but don't flush the EFlags register. */
6799	iemNativeRegFreeTmp(pReNative, idxEflReg);
6800
6801	/* Make a copy of the core state now as we start the if-block. */
6802	iemNativeCondStartIfBlock(pReNative, off);
6803
6804	return off;
6805	}
6806
6807
6808	#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) \
6809	off = iemNativeEmitIfEflagNoBitsSet(pReNative, off, (a_fBits)); \
6810	do {
6811
6812	/** Emits code for IEM_MC_IF_EFL_NO_BITS_SET. */
6813	DECL_INLINE_THROW(uint32_t) iemNativeEmitIfEflagNoBitsSet(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fBitsInEfl)
6814	{
6815	PIEMNATIVECOND const pEntry = iemNativeCondPushIf(pReNative);
6816
6817	/* Get the eflags. */
6818	uint8_t const idxEflReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_EFlags,
6819	kIemNativeGstRegUse_ReadOnly);
6820
6821	/* Test and jump. */
6822	off = iemNativeEmitTestAnyBitsInGprAndJmpToLabelIfAnySet(pReNative, off, idxEflReg, fBitsInEfl, pEntry->idxLabelElse);
6823
6824	/* Free but don't flush the EFlags register. */
6825	iemNativeRegFreeTmp(pReNative, idxEflReg);
6826
6827	/* Make a copy of the core state now as we start the if-block. */
6828	iemNativeCondStartIfBlock(pReNative, off);
6829
6830	return off;
6831	}
6832
6833
6834	#define IEM_MC_IF_EFL_BIT_SET(a_fBit) \
6835	off = iemNativeEmitIfEflagsBitSet(pReNative, off, (a_fBit)); \
6836	do {
6837
6838	/** Emits code for IEM_MC_IF_EFL_BIT_SET. */
6839	DECL_INLINE_THROW(uint32_t) iemNativeEmitIfEflagsBitSet(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fBitInEfl)
6840	{
6841	PIEMNATIVECOND const pEntry = iemNativeCondPushIf(pReNative);
6842
6843	/* Get the eflags. */
6844	uint8_t const idxEflReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_EFlags,
6845	kIemNativeGstRegUse_ReadOnly);
6846
6847	unsigned const iBitNo = ASMBitFirstSetU32(fBitInEfl) - 1;
6848	Assert(RT_BIT_32(iBitNo) == fBitInEfl);
6849
6850	/* Test and jump. */
6851	off = iemNativeEmitTestBitInGprAndJmpToLabelIfNotSet(pReNative, off, idxEflReg, iBitNo, pEntry->idxLabelElse);
6852
6853	/* Free but don't flush the EFlags register. */
6854	iemNativeRegFreeTmp(pReNative, idxEflReg);
6855
6856	/* Make a copy of the core state now as we start the if-block. */
6857	iemNativeCondStartIfBlock(pReNative, off);
6858
6859	return off;
6860	}
6861
6862
6863	#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) \
6864	off = iemNativeEmitIfEflagsBitNotSet(pReNative, off, (a_fBit)); \
6865	do {
6866
6867	/** Emits code for IEM_MC_IF_EFL_BIT_NOT_SET. */
6868	DECL_INLINE_THROW(uint32_t) iemNativeEmitIfEflagsBitNotSet(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fBitInEfl)
6869	{
6870	PIEMNATIVECOND const pEntry = iemNativeCondPushIf(pReNative);
6871
6872	/* Get the eflags. */
6873	uint8_t const idxEflReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_EFlags,
6874	kIemNativeGstRegUse_ReadOnly);
6875
6876	unsigned const iBitNo = ASMBitFirstSetU32(fBitInEfl) - 1;
6877	Assert(RT_BIT_32(iBitNo) == fBitInEfl);
6878
6879	/* Test and jump. */
6880	off = iemNativeEmitTestBitInGprAndJmpToLabelIfSet(pReNative, off, idxEflReg, iBitNo, pEntry->idxLabelElse);
6881
6882	/* Free but don't flush the EFlags register. */
6883	iemNativeRegFreeTmp(pReNative, idxEflReg);
6884
6885	/* Make a copy of the core state now as we start the if-block. */
6886	iemNativeCondStartIfBlock(pReNative, off);
6887
6888	return off;
6889	}
6890
6891
6892	#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
6893	off = iemNativeEmitIfEflagsTwoBitsEqual(pReNative, off, a_fBit1, a_fBit2, false /fInverted/); \
6894	do {
6895
6896	#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
6897	off = iemNativeEmitIfEflagsTwoBitsEqual(pReNative, off, a_fBit1, a_fBit2, true /fInverted/); \
6898	do {
6899
6900	/** Emits code for IEM_MC_IF_EFL_BITS_EQ and IEM_MC_IF_EFL_BITS_NE. */
6901	DECL_INLINE_THROW(uint32_t)
6902	iemNativeEmitIfEflagsTwoBitsEqual(PIEMRECOMPILERSTATE pReNative, uint32_t off,
6903	uint32_t fBit1InEfl, uint32_t fBit2InEfl, bool fInverted)
6904	{
6905	PIEMNATIVECOND const pEntry = iemNativeCondPushIf(pReNative);
6906
6907	/* Get the eflags. */
6908	uint8_t const idxEflReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_EFlags,
6909	kIemNativeGstRegUse_ReadOnly);
6910
6911	unsigned const iBitNo1 = ASMBitFirstSetU32(fBit1InEfl) - 1;
6912	Assert(RT_BIT_32(iBitNo1) == fBit1InEfl);
6913
6914	unsigned const iBitNo2 = ASMBitFirstSetU32(fBit2InEfl) - 1;
6915	Assert(RT_BIT_32(iBitNo2) == fBit2InEfl);
6916	Assert(iBitNo1 != iBitNo2);
6917
6918	#ifdef RT_ARCH_AMD64
6919	uint8_t const idxTmpReg = iemNativeRegAllocTmpImm(pReNative, &off, fBit1InEfl);
6920
6921	off = iemNativeEmitAndGpr32ByGpr32(pReNative, off, idxTmpReg, idxEflReg);
6922	if (iBitNo1 > iBitNo2)
6923	off = iemNativeEmitShiftGpr32Right(pReNative, off, idxTmpReg, iBitNo1 - iBitNo2);
6924	else
6925	off = iemNativeEmitShiftGpr32Left(pReNative, off, idxTmpReg, iBitNo2 - iBitNo1);
6926	off = iemNativeEmitXorGpr32ByGpr32(pReNative, off, idxTmpReg, idxEflReg);
6927
6928	#elif defined(RT_ARCH_ARM64)
6929	uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
6930	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
6931
6932	/* and tmpreg, eflreg, #1<<iBitNo1 */
6933	pu32CodeBuf[off++] = Armv8A64MkInstrAndImm(idxTmpReg, idxEflReg, 0 /uImm7SizeLen -> 32/, 32 - iBitNo1, false /f64Bit/);
6934
6935	/* eeyore tmpreg, eflreg, tmpreg, LSL/LSR, #abs(iBitNo2 - iBitNo1) */
6936	if (iBitNo1 > iBitNo2)
6937	pu32CodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxEflReg, idxTmpReg, false /64bit/,
6938	iBitNo1 - iBitNo2, kArmv8A64InstrShift_Lsr);
6939	else
6940	pu32CodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxEflReg, idxTmpReg, false /64bit/,
6941	iBitNo2 - iBitNo1, kArmv8A64InstrShift_Lsl);
6942
6943	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
6944
6945	#else
6946	# error "Port me"
6947	#endif
6948
6949	/* Test (bit #2 is set in tmpreg if not-equal) and jump. */
6950	off = iemNativeEmitTestBitInGprAndJmpToLabelIfCc(pReNative, off, idxTmpReg, iBitNo2,
6951	pEntry->idxLabelElse, !fInverted /fJmpIfSet/);
6952
6953	/* Free but don't flush the EFlags and tmp registers. */
6954	iemNativeRegFreeTmp(pReNative, idxTmpReg);
6955	iemNativeRegFreeTmp(pReNative, idxEflReg);
6956
6957	/* Make a copy of the core state now as we start the if-block. */
6958	iemNativeCondStartIfBlock(pReNative, off);
6959
6960	return off;
6961	}
6962
6963
6964	#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
6965	off = iemNativeEmitIfEflagsBitNotSetAndTwoBitsEqual(pReNative, off, a_fBit, a_fBit1, a_fBit2, false /fInverted/); \
6966	do {
6967
6968	#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
6969	off = iemNativeEmitIfEflagsBitNotSetAndTwoBitsEqual(pReNative, off, a_fBit, a_fBit1, a_fBit2, true /fInverted/); \
6970	do {
6971
6972	/** Emits code for IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ and
6973	* IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE. */
6974	DECL_INLINE_THROW(uint32_t)
6975	iemNativeEmitIfEflagsBitNotSetAndTwoBitsEqual(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fBitInEfl,
6976	uint32_t fBit1InEfl, uint32_t fBit2InEfl, bool fInverted)
6977	{
6978	PIEMNATIVECOND const pEntry = iemNativeCondPushIf(pReNative);
6979
6980	/* We need an if-block label for the non-inverted variant. */
6981	uint32_t const idxLabelIf = fInverted ? iemNativeLabelCreate(pReNative, kIemNativeLabelType_If, UINT32_MAX,
6982	pReNative->paLabels[pEntry->idxLabelElse].uData) : UINT32_MAX;
6983
6984	/* Get the eflags. */
6985	uint8_t const idxEflReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_EFlags,
6986	kIemNativeGstRegUse_ReadOnly);
6987
6988	/* Translate the flag masks to bit numbers. */
6989	unsigned const iBitNo = ASMBitFirstSetU32(fBitInEfl) - 1;
6990	Assert(RT_BIT_32(iBitNo) == fBitInEfl);
6991
6992	unsigned const iBitNo1 = ASMBitFirstSetU32(fBit1InEfl) - 1;
6993	Assert(RT_BIT_32(iBitNo1) == fBit1InEfl);
6994	Assert(iBitNo1 != iBitNo);
6995
6996	unsigned const iBitNo2 = ASMBitFirstSetU32(fBit2InEfl) - 1;
6997	Assert(RT_BIT_32(iBitNo2) == fBit2InEfl);
6998	Assert(iBitNo2 != iBitNo);
6999	Assert(iBitNo2 != iBitNo1);
7000
7001	#ifdef RT_ARCH_AMD64
7002	uint8_t const idxTmpReg = iemNativeRegAllocTmpImm(pReNative, &off, fBit1InEfl); /* This must come before we jump anywhere! */
7003	#elif defined(RT_ARCH_ARM64)
7004	uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
7005	#endif
7006
7007	/* Check for the lone bit first. */
7008	if (!fInverted)
7009	off = iemNativeEmitTestBitInGprAndJmpToLabelIfSet(pReNative, off, idxEflReg, iBitNo, pEntry->idxLabelElse);
7010	else
7011	off = iemNativeEmitTestBitInGprAndJmpToLabelIfSet(pReNative, off, idxEflReg, iBitNo, idxLabelIf);
7012
7013	/* Then extract and compare the other two bits. */
7014	#ifdef RT_ARCH_AMD64
7015	off = iemNativeEmitAndGpr32ByGpr32(pReNative, off, idxTmpReg, idxEflReg);
7016	if (iBitNo1 > iBitNo2)
7017	off = iemNativeEmitShiftGpr32Right(pReNative, off, idxTmpReg, iBitNo1 - iBitNo2);
7018	else
7019	off = iemNativeEmitShiftGpr32Left(pReNative, off, idxTmpReg, iBitNo2 - iBitNo1);
7020	off = iemNativeEmitXorGpr32ByGpr32(pReNative, off, idxTmpReg, idxEflReg);
7021
7022	#elif defined(RT_ARCH_ARM64)
7023	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
7024
7025	/* and tmpreg, eflreg, #1<<iBitNo1 */
7026	pu32CodeBuf[off++] = Armv8A64MkInstrAndImm(idxTmpReg, idxEflReg, 0 /uImm7SizeLen -> 32/, 32 - iBitNo1, false /f64Bit/);
7027
7028	/* eeyore tmpreg, eflreg, tmpreg, LSL/LSR, #abs(iBitNo2 - iBitNo1) */
7029	if (iBitNo1 > iBitNo2)
7030	pu32CodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxEflReg, idxTmpReg, false /64bit/,
7031	iBitNo1 - iBitNo2, kArmv8A64InstrShift_Lsr);
7032	else
7033	pu32CodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxEflReg, idxTmpReg, false /64bit/,
7034	iBitNo2 - iBitNo1, kArmv8A64InstrShift_Lsl);
7035
7036	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
7037
7038	#else
7039	# error "Port me"
7040	#endif
7041
7042	/* Test (bit #2 is set in tmpreg if not-equal) and jump. */
7043	off = iemNativeEmitTestBitInGprAndJmpToLabelIfCc(pReNative, off, idxTmpReg, iBitNo2,
7044	pEntry->idxLabelElse, !fInverted /fJmpIfSet/);
7045
7046	/* Free but don't flush the EFlags and tmp registers. */
7047	iemNativeRegFreeTmp(pReNative, idxTmpReg);
7048	iemNativeRegFreeTmp(pReNative, idxEflReg);
7049
7050	/* Make a copy of the core state now as we start the if-block. */
7051	iemNativeCondStartIfBlock(pReNative, off, idxLabelIf);
7052
7053	return off;
7054	}
7055
7056
7057	#define IEM_MC_IF_CX_IS_NZ() \
7058	off = iemNativeEmitIfCxIsNotZero(pReNative, off); \
7059	do {
7060
7061	/** Emits code for IEM_MC_IF_CX_IS_NZ. */
7062	DECL_INLINE_THROW(uint32_t) iemNativeEmitIfCxIsNotZero(PIEMRECOMPILERSTATE pReNative, uint32_t off)
7063	{
7064	PIEMNATIVECOND const pEntry = iemNativeCondPushIf(pReNative);
7065
7066	uint8_t const idxGstRcxReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(X86_GREG_xCX),
7067	kIemNativeGstRegUse_ReadOnly);
7068	off = iemNativeEmitTestAnyBitsInGprAndJmpToLabelIfNoneSet(pReNative, off, idxGstRcxReg, UINT16_MAX, pEntry->idxLabelElse);
7069	iemNativeRegFreeTmp(pReNative, idxGstRcxReg);
7070
7071	iemNativeCondStartIfBlock(pReNative, off);
7072	return off;
7073	}
7074
7075
7076	#define IEM_MC_IF_ECX_IS_NZ() \
7077	off = iemNativeEmitIfRcxEcxIsNotZero(pReNative, off, false /f64Bit/); \
7078	do {
7079
7080	#define IEM_MC_IF_RCX_IS_NZ() \
7081	off = iemNativeEmitIfRcxEcxIsNotZero(pReNative, off, true /f64Bit/); \
7082	do {
7083
7084	/** Emits code for IEM_MC_IF_ECX_IS_NZ and IEM_MC_IF_RCX_IS_NZ. */
7085	DECL_INLINE_THROW(uint32_t) iemNativeEmitIfRcxEcxIsNotZero(PIEMRECOMPILERSTATE pReNative, uint32_t off, bool f64Bit)
7086	{
7087	PIEMNATIVECOND const pEntry = iemNativeCondPushIf(pReNative);
7088
7089	uint8_t const idxGstRcxReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(X86_GREG_xCX),
7090	kIemNativeGstRegUse_ReadOnly);
7091	off = iemNativeEmitTestIfGprIsZeroAndJmpToLabel(pReNative, off, idxGstRcxReg, f64Bit, pEntry->idxLabelElse);
7092	iemNativeRegFreeTmp(pReNative, idxGstRcxReg);
7093
7094	iemNativeCondStartIfBlock(pReNative, off);
7095	return off;
7096	}
7097
7098
7099	#define IEM_MC_IF_CX_IS_NOT_ONE() \
7100	off = iemNativeEmitIfCxIsNotOne(pReNative, off); \
7101	do {
7102
7103	/** Emits code for IEM_MC_IF_CX_IS_NOT_ONE. */
7104	DECL_INLINE_THROW(uint32_t) iemNativeEmitIfCxIsNotOne(PIEMRECOMPILERSTATE pReNative, uint32_t off)
7105	{
7106	PIEMNATIVECOND const pEntry = iemNativeCondPushIf(pReNative);
7107
7108	uint8_t const idxGstRcxReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(X86_GREG_xCX),
7109	kIemNativeGstRegUse_ReadOnly);
7110	#ifdef RT_ARCH_AMD64
7111	off = iemNativeEmitTestIfGpr16EqualsImmAndJmpToLabel(pReNative, off, idxGstRcxReg, 1, pEntry->idxLabelElse);
7112	#else
7113	uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
7114	off = iemNativeEmitTestIfGpr16EqualsImmAndJmpToLabel(pReNative, off, idxGstRcxReg, 1, pEntry->idxLabelElse, idxTmpReg);
7115	iemNativeRegFreeTmp(pReNative, idxTmpReg);
7116	#endif
7117	iemNativeRegFreeTmp(pReNative, idxGstRcxReg);
7118
7119	iemNativeCondStartIfBlock(pReNative, off);
7120	return off;
7121	}
7122
7123
7124	#define IEM_MC_IF_ECX_IS_NOT_ONE() \
7125	off = iemNativeEmitIfRcxEcxIsNotOne(pReNative, off, false /f64Bit/); \
7126	do {
7127
7128	#define IEM_MC_IF_RCX_IS_NOT_ONE() \
7129	off = iemNativeEmitIfRcxEcxIsNotOne(pReNative, off, true /f64Bit/); \
7130	do {
7131
7132	/** Emits code for IEM_MC_IF_ECX_IS_NOT_ONE and IEM_MC_IF_RCX_IS_NOT_ONE. */
7133	DECL_INLINE_THROW(uint32_t) iemNativeEmitIfRcxEcxIsNotOne(PIEMRECOMPILERSTATE pReNative, uint32_t off, bool f64Bit)
7134	{
7135	PIEMNATIVECOND const pEntry = iemNativeCondPushIf(pReNative);
7136
7137	uint8_t const idxGstRcxReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(X86_GREG_xCX),
7138	kIemNativeGstRegUse_ReadOnly);
7139	if (f64Bit)
7140	off = iemNativeEmitTestIfGprEqualsImmAndJmpToLabel(pReNative, off, idxGstRcxReg, 1, pEntry->idxLabelElse);
7141	else
7142	off = iemNativeEmitTestIfGpr32EqualsImmAndJmpToLabel(pReNative, off, idxGstRcxReg, 1, pEntry->idxLabelElse);
7143	iemNativeRegFreeTmp(pReNative, idxGstRcxReg);
7144
7145	iemNativeCondStartIfBlock(pReNative, off);
7146	return off;
7147	}
7148
7149
7150	#define IEM_MC_IF_CX_IS_NOT_ONE_AND_EFL_BIT_SET(a_fBit) \
7151	off = iemNativeEmitIfCxIsNotOneAndTestEflagsBit(pReNative, off, a_fBit, true /fCheckIfSet/); \
7152	do {
7153
7154	#define IEM_MC_IF_CX_IS_NOT_ONE_AND_EFL_BIT_NOT_SET(a_fBit) \
7155	off = iemNativeEmitIfCxIsNotOneAndTestEflagsBit(pReNative, off, a_fBit, false /fCheckIfSet/); \
7156	do {
7157
7158	/** Emits code for IEM_MC_IF_CX_IS_NOT_ONE_AND_EFL_BIT_SET and
7159	* IEM_MC_IF_CX_IS_NOT_ONE_AND_EFL_BIT_NOT_SET. */
7160	DECL_INLINE_THROW(uint32_t)
7161	iemNativeEmitIfCxIsNotOneAndTestEflagsBit(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fBitInEfl, bool fCheckIfSet)
7162	{
7163	PIEMNATIVECOND const pEntry = iemNativeCondPushIf(pReNative);
7164
7165	/* We have to load both RCX and EFLAGS before we can start branching,
7166	otherwise we'll end up in the else-block with an inconsistent
7167	register allocator state.
7168	Doing EFLAGS first as it's more likely to be loaded, right? */
7169	uint8_t const idxEflReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_EFlags,
7170	kIemNativeGstRegUse_ReadOnly);
7171	uint8_t const idxGstRcxReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(X86_GREG_xCX),
7172	kIemNativeGstRegUse_ReadOnly);
7173
7174	/** @todo we could reduce this to a single branch instruction by spending a
7175	* temporary register and some setnz stuff. Not sure if loops are
7176	* worth it. */
7177	/* Check CX. */
7178	#ifdef RT_ARCH_AMD64
7179	off = iemNativeEmitTestIfGpr16EqualsImmAndJmpToLabel(pReNative, off, idxGstRcxReg, 1, pEntry->idxLabelElse);
7180	#else
7181	uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
7182	off = iemNativeEmitTestIfGpr16EqualsImmAndJmpToLabel(pReNative, off, idxGstRcxReg, 1, pEntry->idxLabelElse, idxTmpReg);
7183	iemNativeRegFreeTmp(pReNative, idxTmpReg);
7184	#endif
7185
7186	/* Check the EFlags bit. */
7187	unsigned const iBitNo = ASMBitFirstSetU32(fBitInEfl) - 1;
7188	Assert(RT_BIT_32(iBitNo) == fBitInEfl);
7189	off = iemNativeEmitTestBitInGprAndJmpToLabelIfCc(pReNative, off, idxEflReg, iBitNo, pEntry->idxLabelElse,
7190	!fCheckIfSet /fJmpIfSet/);
7191
7192	iemNativeRegFreeTmp(pReNative, idxGstRcxReg);
7193	iemNativeRegFreeTmp(pReNative, idxEflReg);
7194
7195	iemNativeCondStartIfBlock(pReNative, off);
7196	return off;
7197	}
7198
7199
7200	#define IEM_MC_IF_ECX_IS_NOT_ONE_AND_EFL_BIT_SET(a_fBit) \
7201	off = iemNativeEmitIfRcxEcxIsNotOneAndTestEflagsBit(pReNative, off, a_fBit, true /fCheckIfSet/, false /f64Bit/); \
7202	do {
7203
7204	#define IEM_MC_IF_ECX_IS_NOT_ONE_AND_EFL_BIT_NOT_SET(a_fBit) \
7205	off = iemNativeEmitIfRcxEcxIsNotOneAndTestEflagsBit(pReNative, off, a_fBit, false /fCheckIfSet/, false /f64Bit/); \
7206	do {
7207
7208	#define IEM_MC_IF_RCX_IS_NOT_ONE_AND_EFL_BIT_SET(a_fBit) \
7209	off = iemNativeEmitIfRcxEcxIsNotOneAndTestEflagsBit(pReNative, off, a_fBit, true /fCheckIfSet/, true /f64Bit/); \
7210	do {
7211
7212	#define IEM_MC_IF_RCX_IS_NOT_ONE_AND_EFL_BIT_NOT_SET(a_fBit) \
7213	off = iemNativeEmitIfRcxEcxIsNotOneAndTestEflagsBit(pReNative, off, a_fBit, false /fCheckIfSet/, true /f64Bit/); \
7214	do {
7215
7216	/** Emits code for IEM_MC_IF_ECX_IS_NOT_ONE_AND_EFL_BIT_SET,
7217	* IEM_MC_IF_ECX_IS_NOT_ONE_AND_EFL_BIT_NOT_SET,
7218	* IEM_MC_IF_RCX_IS_NOT_ONE_AND_EFL_BIT_SET and
7219	* IEM_MC_IF_RCX_IS_NOT_ONE_AND_EFL_BIT_NOT_SET. */
7220	DECL_INLINE_THROW(uint32_t)
7221	iemNativeEmitIfRcxEcxIsNotOneAndTestEflagsBit(PIEMRECOMPILERSTATE pReNative, uint32_t off,
7222	uint32_t fBitInEfl, bool fCheckIfSet, bool f64Bit)
7223	{
7224	PIEMNATIVECOND const pEntry = iemNativeCondPushIf(pReNative);
7225
7226	/* We have to load both RCX and EFLAGS before we can start branching,
7227	otherwise we'll end up in the else-block with an inconsistent
7228	register allocator state.
7229	Doing EFLAGS first as it's more likely to be loaded, right? */
7230	uint8_t const idxEflReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_EFlags,
7231	kIemNativeGstRegUse_ReadOnly);
7232	uint8_t const idxGstRcxReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(X86_GREG_xCX),
7233	kIemNativeGstRegUse_ReadOnly);
7234
7235	/** @todo we could reduce this to a single branch instruction by spending a
7236	* temporary register and some setnz stuff. Not sure if loops are
7237	* worth it. */
7238	/* Check RCX/ECX. */
7239	if (f64Bit)
7240	off = iemNativeEmitTestIfGprEqualsImmAndJmpToLabel(pReNative, off, idxGstRcxReg, 1, pEntry->idxLabelElse);
7241	else
7242	off = iemNativeEmitTestIfGpr32EqualsImmAndJmpToLabel(pReNative, off, idxGstRcxReg, 1, pEntry->idxLabelElse);
7243
7244	/* Check the EFlags bit. */
7245	unsigned const iBitNo = ASMBitFirstSetU32(fBitInEfl) - 1;
7246	Assert(RT_BIT_32(iBitNo) == fBitInEfl);
7247	off = iemNativeEmitTestBitInGprAndJmpToLabelIfCc(pReNative, off, idxEflReg, iBitNo, pEntry->idxLabelElse,
7248	!fCheckIfSet /fJmpIfSet/);
7249
7250	iemNativeRegFreeTmp(pReNative, idxGstRcxReg);
7251	iemNativeRegFreeTmp(pReNative, idxEflReg);
7252
7253	iemNativeCondStartIfBlock(pReNative, off);
7254	return off;
7255	}
7256
7257
7258
7259	/*********************************************************************************************************************************
7260	* Emitters for IEM_MC_ARG_XXX, IEM_MC_LOCAL, IEM_MC_LOCAL_CONST, ++ *
7261	*********************************************************************************************************************************/
7262	/** Number of hidden arguments for CIMPL calls.
7263	* @note We're sufferning from the usual VBOXSTRICTRC fun on Windows. */
7264	#if defined(VBOXSTRICTRC_STRICT_ENABLED) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_AMD64)
7265	# define IEM_CIMPL_HIDDEN_ARGS 3
7266	#else
7267	# define IEM_CIMPL_HIDDEN_ARGS 2
7268	#endif
7269
7270	#define IEM_MC_NOREF(a_Name) \
7271	RT_NOREF_PV(a_Name)
7272
7273	#define IEM_MC_ARG(a_Type, a_Name, a_iArg) \
7274	uint8_t const a_Name = iemNativeArgAlloc(pReNative, (a_iArg), sizeof(a_Type))
7275
7276	#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) \
7277	uint8_t const a_Name = iemNativeArgAllocConst(pReNative, (a_iArg), sizeof(a_Type), (a_Value))
7278
7279	#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) \
7280	uint8_t const a_Name = iemNativeArgAllocLocalRef(pReNative, (a_iArg), (a_Local))
7281
7282	#define IEM_MC_LOCAL(a_Type, a_Name) \
7283	uint8_t const a_Name = iemNativeVarAlloc(pReNative, sizeof(a_Type))
7284
7285	#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) \
7286	uint8_t const a_Name = iemNativeVarAllocConst(pReNative, sizeof(a_Type), (a_Value))
7287
7288
7289	/**
7290	* Gets the number of hidden arguments for an expected IEM_MC_CALL statement.
7291	*/
7292	DECLINLINE(uint8_t) iemNativeArgGetHiddenArgCount(PIEMRECOMPILERSTATE pReNative)
7293	{
7294	if (pReNative->fCImpl & IEM_CIMPL_F_CALLS_CIMPL)
7295	return IEM_CIMPL_HIDDEN_ARGS;
7296	if (pReNative->fCImpl & IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE)
7297	return 1;
7298	return 0;
7299	}
7300
7301
7302	/**
7303	* Internal work that allocates a variable with kind set to
7304	* kIemNativeVarKind_Invalid and no current stack allocation.
7305	*
7306	* The kind will either be set by the caller or later when the variable is first
7307	* assigned a value.
7308	*/
7309	static uint8_t iemNativeVarAllocInt(PIEMRECOMPILERSTATE pReNative, uint8_t cbType)
7310	{
7311	Assert(cbType > 0 && cbType <= 64);
7312	unsigned const idxVar = ASMBitFirstSetU32(~pReNative->Core.bmVars) - 1;
7313	AssertStmt(idxVar < RT_ELEMENTS(pReNative->Core.aVars), IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_EXHAUSTED));
7314	pReNative->Core.bmVars \|= RT_BIT_32(idxVar);
7315	pReNative->Core.aVars[idxVar].enmKind = kIemNativeVarKind_Invalid;
7316	pReNative->Core.aVars[idxVar].cbVar = cbType;
7317	pReNative->Core.aVars[idxVar].idxStackSlot = UINT8_MAX;
7318	pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
7319	pReNative->Core.aVars[idxVar].uArgNo = UINT8_MAX;
7320	pReNative->Core.aVars[idxVar].idxReferrerVar = UINT8_MAX;
7321	pReNative->Core.aVars[idxVar].enmGstReg = kIemNativeGstReg_End;
7322	pReNative->Core.aVars[idxVar].fRegAcquired = false;
7323	pReNative->Core.aVars[idxVar].u.uValue = 0;
7324	return idxVar;
7325	}
7326
7327
7328	/**
7329	* Internal work that allocates an argument variable w/o setting enmKind.
7330	*/
7331	static uint8_t iemNativeArgAllocInt(PIEMRECOMPILERSTATE pReNative, uint8_t iArgNo, uint8_t cbType)
7332	{
7333	iArgNo += iemNativeArgGetHiddenArgCount(pReNative);
7334	AssertStmt(iArgNo < RT_ELEMENTS(pReNative->Core.aidxArgVars), IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_1));
7335	AssertStmt(pReNative->Core.aidxArgVars[iArgNo] == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_DUP_ARG_NO));
7336
7337	uint8_t const idxVar = iemNativeVarAllocInt(pReNative, cbType);
7338	pReNative->Core.aidxArgVars[iArgNo] = idxVar;
7339	pReNative->Core.aVars[idxVar].uArgNo = iArgNo;
7340	return idxVar;
7341	}
7342
7343
7344	/**
7345	* Gets the stack slot for a stack variable, allocating one if necessary.
7346	*
7347	* Calling this function implies that the stack slot will contain a valid
7348	* variable value. The caller deals with any register currently assigned to the
7349	* variable, typically by spilling it into the stack slot.
7350	*
7351	* @returns The stack slot number.
7352	* @param pReNative The recompiler state.
7353	* @param idxVar The variable.
7354	* @throws VERR_IEM_VAR_OUT_OF_STACK_SLOTS
7355	*/
7356	DECL_HIDDEN_THROW(uint8_t) iemNativeVarGetStackSlot(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
7357	{
7358	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7359	Assert(pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack);
7360
7361	/* Already got a slot? */
7362	uint8_t const idxStackSlot = pReNative->Core.aVars[idxVar].idxStackSlot;
7363	if (idxStackSlot != UINT8_MAX)
7364	{
7365	Assert(idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS);
7366	return idxStackSlot;
7367	}
7368
7369	/*
7370	* A single slot is easy to allocate.
7371	* Allocate them from the top end, closest to BP, to reduce the displacement.
7372	*/
7373	if (pReNative->Core.aVars[idxVar].cbVar <= sizeof(uint64_t))
7374	{
7375	unsigned const iSlot = ASMBitLastSetU32(~pReNative->Core.bmStack) - 1;
7376	AssertStmt(iSlot < IEMNATIVE_FRAME_VAR_SLOTS, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_OUT_OF_STACK_SLOTS));
7377	pReNative->Core.bmStack \|= RT_BIT_32(iSlot);
7378	pReNative->Core.aVars[idxVar].idxStackSlot = (uint8_t)iSlot;
7379	Log11(("iemNativeVarSetKindToStack: idxVar=%d iSlot=%#x\n", idxVar, iSlot));
7380	return (uint8_t)iSlot;
7381	}
7382
7383	/*
7384	* We need more than one stack slot.
7385	*
7386	* cbVar -> fBitAlignMask: 16 -> 1; 32 -> 3; 64 -> 7;
7387	*/
7388	AssertCompile(RT_IS_POWER_OF_TWO(IEMNATIVE_FRAME_VAR_SLOTS)); /* If not we have to add an overflow check. */
7389	Assert(pReNative->Core.aVars[idxVar].cbVar <= 64);
7390	uint32_t const fBitAlignMask = RT_BIT_32(ASMBitLastSetU32(pReNative->Core.aVars[idxVar].cbVar) - 4) - 1;
7391	uint32_t fBitAllocMask = RT_BIT_32((pReNative->Core.aVars[idxVar].cbVar + 7) >> 3) - 1;
7392	uint32_t bmStack = ~pReNative->Core.bmStack;
7393	while (bmStack != UINT32_MAX)
7394	{
7395	/** @todo allocate from the top to reduce BP displacement. */
7396	unsigned const iSlot = ASMBitFirstSetU32(bmStack) - 1;
7397	AssertStmt(iSlot < IEMNATIVE_FRAME_VAR_SLOTS, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_OUT_OF_STACK_SLOTS));
7398	if (!(iSlot & fBitAlignMask))
7399	{
7400	if ((bmStack & (fBitAllocMask << iSlot)) == (fBitAllocMask << iSlot))
7401	{
7402	pReNative->Core.bmStack \|= (fBitAllocMask << iSlot);
7403	pReNative->Core.aVars[idxVar].idxStackSlot = (uint8_t)iSlot;
7404	Log11(("iemNativeVarSetKindToStack: idxVar=%d iSlot=%#x/%#x (cbVar=%#x)\n",
7405	idxVar, iSlot, fBitAllocMask, pReNative->Core.aVars[idxVar].cbVar));
7406	return (uint8_t)iSlot;
7407	}
7408	}
7409	bmStack \|= fBitAlignMask << (iSlot & ~fBitAlignMask);
7410	}
7411	AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_OUT_OF_STACK_SLOTS));
7412	}
7413
7414
7415	/**
7416	* Changes the variable to a stack variable.
7417	*
7418	* Currently this is s only possible to do the first time the variable is used,
7419	* switching later is can be implemented but not done.
7420	*
7421	* @param pReNative The recompiler state.
7422	* @param idxVar The variable.
7423	* @throws VERR_IEM_VAR_IPE_2
7424	*/
7425	static void iemNativeVarSetKindToStack(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
7426	{
7427	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7428	if (pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_Stack)
7429	{
7430	/* We could in theory transition from immediate to stack as well, but it
7431	would involve the caller doing work storing the value on the stack. So,
7432	till that's required we only allow transition from invalid. */
7433	AssertStmt(pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Invalid,
7434	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7435	AssertStmt(pReNative->Core.aVars[idxVar].idxReg == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7436	pReNative->Core.aVars[idxVar].enmKind = kIemNativeVarKind_Stack;
7437
7438	/* Note! We don't allocate a stack slot here, that's only done when a
7439	slot is actually needed to hold a variable value. */
7440	}
7441	}
7442
7443
7444	/**
7445	* Sets it to a variable with a constant value.
7446	*
7447	* This does not require stack storage as we know the value and can always
7448	* reload it, unless of course it's referenced.
7449	*
7450	* @param pReNative The recompiler state.
7451	* @param idxVar The variable.
7452	* @param uValue The immediate value.
7453	* @throws VERR_IEM_VAR_OUT_OF_STACK_SLOTS, VERR_IEM_VAR_IPE_2
7454	*/
7455	static void iemNativeVarSetKindToConst(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint64_t uValue)
7456	{
7457	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7458	if (pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_Immediate)
7459	{
7460	/* Only simple transitions for now. */
7461	AssertStmt(pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Invalid,
7462	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7463	pReNative->Core.aVars[idxVar].enmKind = kIemNativeVarKind_Immediate;
7464	}
7465	AssertStmt(pReNative->Core.aVars[idxVar].idxReg == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7466
7467	pReNative->Core.aVars[idxVar].u.uValue = uValue;
7468	AssertMsg( pReNative->Core.aVars[idxVar].cbVar >= sizeof(uint64_t)
7469	\|\| pReNative->Core.aVars[idxVar].u.uValue < RT_BIT_64(pReNative->Core.aVars[idxVar].cbVar * 8),
7470	("idxVar=%d cbVar=%u uValue=%#RX64\n", idxVar, pReNative->Core.aVars[idxVar].cbVar, uValue));
7471	}
7472
7473
7474	/**
7475	* Sets the variable to a reference (pointer) to @a idxOtherVar.
7476	*
7477	* This does not require stack storage as we know the value and can always
7478	* reload it. Loading is postponed till needed.
7479	*
7480	* @param pReNative The recompiler state.
7481	* @param idxVar The variable.
7482	* @param idxOtherVar The variable to take the (stack) address of.
7483	*
7484	* @throws VERR_IEM_VAR_OUT_OF_STACK_SLOTS, VERR_IEM_VAR_IPE_2
7485	*/
7486	static void iemNativeVarSetKindToLocalRef(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint8_t idxOtherVar)
7487	{
7488	Assert(idxVar < RT_ELEMENTS(pReNative->Core.aVars) && (pReNative->Core.bmVars & RT_BIT_32(idxVar)));
7489	Assert(idxOtherVar < RT_ELEMENTS(pReNative->Core.aVars) && (pReNative->Core.bmVars & RT_BIT_32(idxOtherVar)));
7490
7491	if (pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_VarRef)
7492	{
7493	/* Only simple transitions for now. */
7494	AssertStmt(pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Invalid,
7495	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7496	pReNative->Core.aVars[idxVar].enmKind = kIemNativeVarKind_VarRef;
7497	}
7498	AssertStmt(pReNative->Core.aVars[idxVar].idxReg == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7499
7500	pReNative->Core.aVars[idxVar].u.idxRefVar = idxOtherVar;
7501
7502	/* Update the other variable, ensure it's a stack variable. */
7503	/** @todo handle variables with const values... that'll go boom now. */
7504	pReNative->Core.aVars[idxOtherVar].idxReferrerVar = idxVar;
7505	iemNativeVarSetKindToStack(pReNative, idxOtherVar);
7506	}
7507
7508
7509	/**
7510	* Sets the variable to a reference (pointer) to a guest register reference.
7511	*
7512	* This does not require stack storage as we know the value and can always
7513	* reload it. Loading is postponed till needed.
7514	*
7515	* @param pReNative The recompiler state.
7516	* @param idxVar The variable.
7517	* @param enmRegClass The class guest registers to reference.
7518	* @param idxReg The register within @a enmRegClass to reference.
7519	*
7520	* @throws VERR_IEM_VAR_IPE_2
7521	*/
7522	static void iemNativeVarSetKindToGstRegRef(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar,
7523	IEMNATIVEGSTREGREF enmRegClass, uint8_t idxReg)
7524	{
7525	Assert(idxVar < RT_ELEMENTS(pReNative->Core.aVars) && (pReNative->Core.bmVars & RT_BIT_32(idxVar)));
7526
7527	if (pReNative->Core.aVars[idxVar].enmKind != kIemNativeVarKind_GstRegRef)
7528	{
7529	/* Only simple transitions for now. */
7530	AssertStmt(pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Invalid,
7531	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7532	pReNative->Core.aVars[idxVar].enmKind = kIemNativeVarKind_GstRegRef;
7533	}
7534	AssertStmt(pReNative->Core.aVars[idxVar].idxReg == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_2));
7535
7536	pReNative->Core.aVars[idxVar].u.GstRegRef.enmClass = enmRegClass;
7537	pReNative->Core.aVars[idxVar].u.GstRegRef.idx = idxReg;
7538	}
7539
7540
7541	DECL_HIDDEN_THROW(uint8_t) iemNativeArgAlloc(PIEMRECOMPILERSTATE pReNative, uint8_t iArgNo, uint8_t cbType)
7542	{
7543	return iemNativeArgAllocInt(pReNative, iArgNo, cbType);
7544	}
7545
7546
7547	DECL_HIDDEN_THROW(uint8_t) iemNativeArgAllocConst(PIEMRECOMPILERSTATE pReNative, uint8_t iArgNo, uint8_t cbType, uint64_t uValue)
7548	{
7549	uint8_t const idxVar = iemNativeArgAllocInt(pReNative, iArgNo, cbType);
7550
7551	/* Since we're using a generic uint64_t value type, we must truncate it if
7552	the variable is smaller otherwise we may end up with too large value when
7553	scaling up a imm8 w/ sign-extension.
7554
7555	This caused trouble with a "add bx, 0xffff" instruction (around f000:ac60
7556	in the bios, bx=1) when running on arm, because clang expect 16-bit
7557	register parameters to have bits 16 and up set to zero. Instead of
7558	setting x1 = 0xffff we ended up with x1 = 0xffffffffffffff and the wrong
7559	CF value in the result. */
7560	switch (cbType)
7561	{
7562	case sizeof(uint8_t): uValue &= UINT64_C(0xff); break;
7563	case sizeof(uint16_t): uValue &= UINT64_C(0xffff); break;
7564	case sizeof(uint32_t): uValue &= UINT64_C(0xffffffff); break;
7565	}
7566	iemNativeVarSetKindToConst(pReNative, idxVar, uValue);
7567	return idxVar;
7568	}
7569
7570
7571	DECL_HIDDEN_THROW(uint8_t) iemNativeArgAllocLocalRef(PIEMRECOMPILERSTATE pReNative, uint8_t iArgNo, uint8_t idxOtherVar)
7572	{
7573	AssertStmt( idxOtherVar < RT_ELEMENTS(pReNative->Core.aVars)
7574	&& (pReNative->Core.bmVars & RT_BIT_32(idxOtherVar))
7575	&& pReNative->Core.aVars[idxOtherVar].uArgNo == UINT8_MAX,
7576	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_1));
7577
7578	uint8_t const idxArgVar = iemNativeArgAlloc(pReNative, iArgNo, sizeof(uintptr_t));
7579	iemNativeVarSetKindToLocalRef(pReNative, idxArgVar, idxOtherVar);
7580	return idxArgVar;
7581	}
7582
7583
7584	DECL_HIDDEN_THROW(uint8_t) iemNativeVarAlloc(PIEMRECOMPILERSTATE pReNative, uint8_t cbType)
7585	{
7586	uint8_t const idxVar = iemNativeVarAllocInt(pReNative, cbType);
7587	/* Don't set to stack now, leave that to the first use as for instance
7588	IEM_MC_CALC_RM_EFF_ADDR may produce a const/immediate result (esp. in DOS). */
7589	return idxVar;
7590	}
7591
7592
7593	DECL_HIDDEN_THROW(uint8_t) iemNativeVarAllocConst(PIEMRECOMPILERSTATE pReNative, uint8_t cbType, uint64_t uValue)
7594	{
7595	uint8_t const idxVar = iemNativeVarAllocInt(pReNative, cbType);
7596
7597	/* Since we're using a generic uint64_t value type, we must truncate it if
7598	the variable is smaller otherwise we may end up with too large value when
7599	scaling up a imm8 w/ sign-extension. */
7600	switch (cbType)
7601	{
7602	case sizeof(uint8_t): uValue &= UINT64_C(0xff); break;
7603	case sizeof(uint16_t): uValue &= UINT64_C(0xffff); break;
7604	case sizeof(uint32_t): uValue &= UINT64_C(0xffffffff); break;
7605	}
7606	iemNativeVarSetKindToConst(pReNative, idxVar, uValue);
7607	return idxVar;
7608	}
7609
7610
7611	/**
7612	* Makes sure variable @a idxVar has a register assigned to it and that it stays
7613	* fixed till we call iemNativeVarRegisterRelease.
7614	*
7615	* @returns The host register number.
7616	* @param pReNative The recompiler state.
7617	* @param idxVar The variable.
7618	* @param poff Pointer to the instruction buffer offset.
7619	* In case a register needs to be freed up or the value
7620	* loaded off the stack.
7621	* @param fInitialized Set if the variable must already have been initialized.
7622	* Will throw VERR_IEM_VAR_NOT_INITIALIZED if this is not
7623	* the case.
7624	* @param idxRegPref Preferred register number or UINT8_MAX.
7625	*/
7626	DECL_HIDDEN_THROW(uint8_t) iemNativeVarRegisterAcquire(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint32_t *poff,
7627	bool fInitialized /= false/, uint8_t idxRegPref /= UINT8_MAX/)
7628	{
7629	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7630	Assert(pReNative->Core.aVars[idxVar].cbVar <= 8);
7631	Assert(!pReNative->Core.aVars[idxVar].fRegAcquired);
7632
7633	uint8_t idxReg = pReNative->Core.aVars[idxVar].idxReg;
7634	if (idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
7635	{
7636	Assert( pReNative->Core.aVars[idxVar].enmKind > kIemNativeVarKind_Invalid
7637	&& pReNative->Core.aVars[idxVar].enmKind < kIemNativeVarKind_End);
7638	pReNative->Core.aVars[idxVar].fRegAcquired = true;
7639	return idxReg;
7640	}
7641
7642	/*
7643	* If the kind of variable has not yet been set, default to 'stack'.
7644	*/
7645	Assert( pReNative->Core.aVars[idxVar].enmKind >= kIemNativeVarKind_Invalid
7646	&& pReNative->Core.aVars[idxVar].enmKind < kIemNativeVarKind_End);
7647	if (pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Invalid)
7648	iemNativeVarSetKindToStack(pReNative, idxVar);
7649
7650	/*
7651	* We have to allocate a register for the variable, even if its a stack one
7652	* as we don't know if there are modification being made to it before its
7653	* finalized (todo: analyze and insert hints about that?).
7654	*
7655	* If we can, we try get the correct register for argument variables. This
7656	* is assuming that most argument variables are fetched as close as possible
7657	* to the actual call, so that there aren't any interfering hidden calls
7658	* (memory accesses, etc) inbetween.
7659	*
7660	* If we cannot or it's a variable, we make sure no argument registers
7661	* that will be used by this MC block will be allocated here, and we always
7662	* prefer non-volatile registers to avoid needing to spill stuff for internal
7663	* call.
7664	*/
7665	/** @todo Detect too early argument value fetches and warn about hidden
7666	* calls causing less optimal code to be generated in the python script. */
7667
7668	uint8_t const uArgNo = pReNative->Core.aVars[idxVar].uArgNo;
7669	if ( uArgNo < RT_ELEMENTS(g_aidxIemNativeCallRegs)
7670	&& !(pReNative->Core.bmHstRegs & RT_BIT_32(g_aidxIemNativeCallRegs[uArgNo])))
7671	{
7672	idxReg = g_aidxIemNativeCallRegs[uArgNo];
7673	iemNativeRegClearGstRegShadowing(pReNative, idxReg, *poff);
7674	Log11(("iemNativeVarRegisterAcquire: idxVar=%u idxReg=%u (matching arg %u)\n", idxVar, idxReg, uArgNo));
7675	}
7676	else if ( idxRegPref >= RT_ELEMENTS(pReNative->Core.aHstRegs)
7677	\|\| (pReNative->Core.bmHstRegs & RT_BIT_32(idxRegPref)))
7678	{
7679	uint32_t const fNotArgsMask = ~g_afIemNativeCallRegs[RT_MIN(pReNative->cArgs, IEMNATIVE_CALL_ARG_GREG_COUNT)];
7680	uint32_t const fRegs = ~pReNative->Core.bmHstRegs
7681	& ~pReNative->Core.bmHstRegsWithGstShadow
7682	& (~IEMNATIVE_REG_FIXED_MASK & IEMNATIVE_HST_GREG_MASK)
7683	& fNotArgsMask;
7684	if (fRegs)
7685	{
7686	/* Pick from the top as that both arm64 and amd64 have a block of non-volatile registers there. */
7687	idxReg = (uint8_t)ASMBitLastSetU32( fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK
7688	? fRegs & ~IEMNATIVE_CALL_VOLATILE_GREG_MASK : fRegs) - 1;
7689	Assert(pReNative->Core.aHstRegs[idxReg].fGstRegShadows == 0);
7690	Assert(!(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxReg)));
7691	Log11(("iemNativeVarRegisterAcquire: idxVar=%u idxReg=%u (uArgNo=%u)\n", idxVar, idxReg, uArgNo));
7692	}
7693	else
7694	{
7695	idxReg = iemNativeRegAllocFindFree(pReNative, poff, false /fPreferVolatile/,
7696	IEMNATIVE_HST_GREG_MASK & ~IEMNATIVE_REG_FIXED_MASK & fNotArgsMask);
7697	AssertStmt(idxReg != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_ALLOCATOR_NO_FREE_VAR));
7698	Log11(("iemNativeVarRegisterAcquire: idxVar=%u idxReg=%u (slow, uArgNo=%u)\n", idxVar, idxReg, uArgNo));
7699	}
7700	}
7701	else
7702	{
7703	idxReg = idxRegPref;
7704	iemNativeRegClearGstRegShadowing(pReNative, idxReg, *poff);
7705	Log11(("iemNativeVarRegisterAcquire: idxVar=%u idxReg=%u (preferred)\n", idxVar, idxReg));
7706	}
7707	iemNativeRegMarkAllocated(pReNative, idxReg, kIemNativeWhat_Var, idxVar);
7708	pReNative->Core.aVars[idxVar].idxReg = idxReg;
7709
7710	/*
7711	* Load it off the stack if we've got a stack slot.
7712	*/
7713	uint8_t const idxStackSlot = pReNative->Core.aVars[idxVar].idxStackSlot;
7714	if (idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS)
7715	{
7716	Assert(fInitialized);
7717	int32_t const offDispBp = iemNativeStackCalcBpDisp(idxStackSlot);
7718	switch (pReNative->Core.aVars[idxVar].cbVar)
7719	{
7720	case 1: poff = iemNativeEmitLoadGprByBpU8( pReNative, poff, idxReg, offDispBp); break;
7721	case 2: poff = iemNativeEmitLoadGprByBpU16(pReNative, poff, idxReg, offDispBp); break;
7722	case 3: AssertFailed(); RT_FALL_THRU();
7723	case 4: poff = iemNativeEmitLoadGprByBpU32(pReNative, poff, idxReg, offDispBp); break;
7724	default: AssertFailed(); RT_FALL_THRU();
7725	case 8: poff = iemNativeEmitLoadGprByBp( pReNative, poff, idxReg, offDispBp); break;
7726	}
7727	}
7728	else
7729	{
7730	Assert(idxStackSlot == UINT8_MAX);
7731	AssertStmt(!fInitialized, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_NOT_INITIALIZED));
7732	}
7733	pReNative->Core.aVars[idxVar].fRegAcquired = true;
7734	return idxReg;
7735	}
7736
7737
7738	/**
7739	* The value of variable @a idxVar will be written in full to the @a enmGstReg
7740	* guest register.
7741	*
7742	* This function makes sure there is a register for it and sets it to be the
7743	* current shadow copy of @a enmGstReg.
7744	*
7745	* @returns The host register number.
7746	* @param pReNative The recompiler state.
7747	* @param idxVar The variable.
7748	* @param enmGstReg The guest register this variable will be written to
7749	* after this call.
7750	* @param poff Pointer to the instruction buffer offset.
7751	* In case a register needs to be freed up or if the
7752	* variable content needs to be loaded off the stack.
7753	*
7754	* @note We DO NOT expect @a idxVar to be an argument variable,
7755	* because we can only in the commit stage of an instruction when this
7756	* function is used.
7757	*/
7758	DECL_HIDDEN_THROW(uint8_t)
7759	iemNativeVarRegisterAcquireForGuestReg(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, IEMNATIVEGSTREG enmGstReg, uint32_t *poff)
7760	{
7761	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7762	Assert(!pReNative->Core.aVars[idxVar].fRegAcquired);
7763	AssertMsgStmt( pReNative->Core.aVars[idxVar].cbVar <= 8
7764	&& ( pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Immediate
7765	\|\| pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack),
7766	("idxVar=%d cbVar=%d enmKind=%d enmGstReg=%s\n", idxVar, pReNative->Core.aVars[idxVar].cbVar,
7767	pReNative->Core.aVars[idxVar].enmKind, g_aGstShadowInfo[enmGstReg].pszName),
7768	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_6));
7769
7770	/*
7771	* This shouldn't ever be used for arguments, unless it's in a weird else
7772	* branch that doesn't do any calling and even then it's questionable.
7773	*
7774	* However, in case someone writes crazy wrong MC code and does register
7775	* updates before making calls, just use the regular register allocator to
7776	* ensure we get a register suitable for the intended argument number.
7777	*/
7778	AssertStmt(pReNative->Core.aVars[idxVar].uArgNo == UINT8_MAX, iemNativeVarRegisterAcquire(pReNative, idxVar, poff));
7779
7780	/*
7781	* If there is already a register for the variable, we transfer/set the
7782	* guest shadow copy assignment to it.
7783	*/
7784	uint8_t idxReg = pReNative->Core.aVars[idxVar].idxReg;
7785	if (idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
7786	{
7787	if (pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg))
7788	{
7789	uint8_t const idxRegOld = pReNative->Core.aidxGstRegShadows[enmGstReg];
7790	iemNativeRegTransferGstRegShadowing(pReNative, idxRegOld, idxReg, enmGstReg, *poff);
7791	Log12(("iemNativeVarRegisterAcquireForGuestReg: Moved %s for guest %s into %s for full write\n",
7792	g_apszIemNativeHstRegNames[idxRegOld], g_aGstShadowInfo[enmGstReg].pszName, g_apszIemNativeHstRegNames[idxReg]));
7793	}
7794	else
7795	{
7796	iemNativeRegMarkAsGstRegShadow(pReNative, idxReg, enmGstReg, *poff);
7797	Log12(("iemNativeVarRegisterAcquireForGuestReg: Marking %s as copy of guest %s (full write)\n",
7798	g_apszIemNativeHstRegNames[idxReg], g_aGstShadowInfo[enmGstReg].pszName));
7799	}
7800	/** @todo figure this one out. We need some way of making sure the register isn't
7801	* modified after this point, just in case we start writing crappy MC code. */
7802	pReNative->Core.aVars[idxVar].enmGstReg = enmGstReg;
7803	pReNative->Core.aVars[idxVar].fRegAcquired = true;
7804	return idxReg;
7805	}
7806	Assert(pReNative->Core.aVars[idxVar].uArgNo == UINT8_MAX);
7807
7808	/*
7809	* Because this is supposed to be the commit stage, we're just tag along with the
7810	* temporary register allocator and upgrade it to a variable register.
7811	*/
7812	idxReg = iemNativeRegAllocTmpForGuestReg(pReNative, poff, enmGstReg, kIemNativeGstRegUse_ForFullWrite);
7813	Assert(pReNative->Core.aHstRegs[idxReg].enmWhat == kIemNativeWhat_Tmp);
7814	Assert(pReNative->Core.aHstRegs[idxReg].idxVar == UINT8_MAX);
7815	pReNative->Core.aHstRegs[idxReg].enmWhat = kIemNativeWhat_Var;
7816	pReNative->Core.aHstRegs[idxReg].idxVar = idxVar;
7817	pReNative->Core.aVars[idxVar].idxReg = idxReg;
7818
7819	/*
7820	* Now we need to load the register value.
7821	*/
7822	if (pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Immediate)
7823	poff = iemNativeEmitLoadGprImm64(pReNative, poff, idxReg, pReNative->Core.aVars[idxVar].u.uValue);
7824	else
7825	{
7826	uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxVar);
7827	int32_t const offDispBp = iemNativeStackCalcBpDisp(idxStackSlot);
7828	switch (pReNative->Core.aVars[idxVar].cbVar)
7829	{
7830	case sizeof(uint64_t):
7831	poff = iemNativeEmitLoadGprByBp(pReNative, poff, idxReg, offDispBp);
7832	break;
7833	case sizeof(uint32_t):
7834	poff = iemNativeEmitLoadGprByBpU32(pReNative, poff, idxReg, offDispBp);
7835	break;
7836	case sizeof(uint16_t):
7837	poff = iemNativeEmitLoadGprByBpU16(pReNative, poff, idxReg, offDispBp);
7838	break;
7839	case sizeof(uint8_t):
7840	poff = iemNativeEmitLoadGprByBpU8(pReNative, poff, idxReg, offDispBp);
7841	break;
7842	default:
7843	AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_6));
7844	}
7845	}
7846
7847	pReNative->Core.aVars[idxVar].fRegAcquired = true;
7848	return idxReg;
7849	}
7850
7851
7852	/**
7853	* Sets the host register for @a idxVarRc to @a idxReg.
7854	*
7855	* The register must not be allocated. Any guest register shadowing will be
7856	* implictly dropped by this call.
7857	*
7858	* The variable must not have any register associated with it (causes
7859	* VERR_IEM_VAR_IPE_10 to be raised). Conversion to a stack variable is
7860	* implied.
7861	*
7862	* @returns idxReg
7863	* @param pReNative The recompiler state.
7864	* @param idxVar The variable.
7865	* @param idxReg The host register (typically IEMNATIVE_CALL_RET_GREG).
7866	* @param off For recording in debug info.
7867	*
7868	* @throws VERR_IEM_VAR_IPE_10, VERR_IEM_VAR_IPE_11
7869	*/
7870	DECL_INLINE_THROW(uint8_t) iemNativeVarRegisterSet(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint8_t idxReg, uint32_t off)
7871	{
7872	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
7873	Assert(!pReNative->Core.aVars[idxVar].fRegAcquired);
7874	Assert(idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs));
7875	AssertStmt(pReNative->Core.aVars[idxVar].idxReg == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_10));
7876	AssertStmt(!(pReNative->Core.bmHstRegs & RT_BIT_32(idxReg)), IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_11));
7877
7878	iemNativeRegClearGstRegShadowing(pReNative, idxReg, off);
7879	iemNativeRegMarkAllocated(pReNative, idxReg, kIemNativeWhat_Var, idxVar);
7880
7881	iemNativeVarSetKindToStack(pReNative, idxVar);
7882	pReNative->Core.aVars[idxVar].idxReg = idxReg;
7883
7884	return idxReg;
7885	}
7886
7887
7888	/**
7889	* A convenient helper function.
7890	*/
7891	DECL_INLINE_THROW(uint8_t) iemNativeVarRegisterSetAndAcquire(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar,
7892	uint8_t idxReg, uint32_t *poff)
7893	{
7894	idxReg = iemNativeVarRegisterSet(pReNative, idxVar, idxReg, *poff);
7895	pReNative->Core.aVars[idxVar].fRegAcquired = true;
7896	return idxReg;
7897	}
7898
7899
7900	/**
7901	* Emit code to save volatile registers prior to a call to a helper (TLB miss).
7902	*
7903	* This is used together with iemNativeVarRestoreVolatileRegsPostHlpCall() and
7904	* optionally iemNativeRegRestoreGuestShadowsInVolatileRegs() to bypass the
7905	* requirement of flushing anything in volatile host registers when making a
7906	* call.
7907	*
7908	* @returns New @a off value.
7909	* @param pReNative The recompiler state.
7910	* @param off The code buffer position.
7911	* @param fHstRegsNotToSave Set of registers not to save & restore.
7912	*/
7913	DECL_HIDDEN_THROW(uint32_t)
7914	iemNativeVarSaveVolatileRegsPreHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fHstRegsNotToSave)
7915	{
7916	uint32_t fHstRegs = pReNative->Core.bmHstRegs & IEMNATIVE_CALL_VOLATILE_GREG_MASK & ~fHstRegsNotToSave;
7917	if (fHstRegs)
7918	{
7919	do
7920	{
7921	unsigned int const idxHstReg = ASMBitFirstSetU32(fHstRegs) - 1;
7922	fHstRegs &= ~RT_BIT_32(idxHstReg);
7923
7924	if (pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Var)
7925	{
7926	uint8_t const idxVar = pReNative->Core.aHstRegs[idxHstReg].idxVar;
7927	AssertStmt( idxVar < RT_ELEMENTS(pReNative->Core.aVars)
7928	&& (pReNative->Core.bmVars & RT_BIT_32(idxVar))
7929	&& pReNative->Core.aVars[idxVar].idxReg == idxHstReg,
7930	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_12));
7931	switch (pReNative->Core.aVars[idxVar].enmKind)
7932	{
7933	case kIemNativeVarKind_Stack:
7934	{
7935	/* Temporarily spill the variable register. */
7936	uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxVar);
7937	Log12(("iemNativeVarSaveVolatileRegsPreHlpCall: spilling idxVar=%d/idxReg=%d onto the stack (slot %#x bp+%d, off=%#x)\n",
7938	idxVar, idxHstReg, idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
7939	off = iemNativeEmitStoreGprByBp(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxHstReg);
7940	continue;
7941	}
7942
7943	case kIemNativeVarKind_Immediate:
7944	case kIemNativeVarKind_VarRef:
7945	case kIemNativeVarKind_GstRegRef:
7946	/* It is weird to have any of these loaded at this point. */
7947	AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_13));
7948	continue;
7949
7950	case kIemNativeVarKind_End:
7951	case kIemNativeVarKind_Invalid:
7952	break;
7953	}
7954	AssertFailed();
7955	}
7956	else
7957	{
7958	/*
7959	* Allocate a temporary stack slot and spill the register to it.
7960	*/
7961	unsigned const idxStackSlot = ASMBitLastSetU32(~pReNative->Core.bmStack) - 1;
7962	AssertStmt(idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS,
7963	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_OUT_OF_STACK_SLOTS));
7964	pReNative->Core.bmStack \|= RT_BIT_32(idxStackSlot);
7965	pReNative->Core.aHstRegs[idxHstReg].idxStackSlot = (uint8_t)idxStackSlot;
7966	Log12(("iemNativeVarSaveVolatileRegsPreHlpCall: spilling idxReg=%d onto the stack (slot %#x bp+%d, off=%#x)\n",
7967	idxHstReg, idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
7968	off = iemNativeEmitStoreGprByBp(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxHstReg);
7969	}
7970	} while (fHstRegs);
7971	}
7972	return off;
7973	}
7974
7975
7976	/**
7977	* Emit code to restore volatile registers after to a call to a helper.
7978	*
7979	* @returns New @a off value.
7980	* @param pReNative The recompiler state.
7981	* @param off The code buffer position.
7982	* @param fHstRegsNotToSave Set of registers not to save & restore.
7983	* @see iemNativeVarSaveVolatileRegsPreHlpCall(),
7984	* iemNativeRegRestoreGuestShadowsInVolatileRegs()
7985	*/
7986	DECL_HIDDEN_THROW(uint32_t)
7987	iemNativeVarRestoreVolatileRegsPostHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fHstRegsNotToSave)
7988	{
7989	uint32_t fHstRegs = pReNative->Core.bmHstRegs & IEMNATIVE_CALL_VOLATILE_GREG_MASK & ~fHstRegsNotToSave;
7990	if (fHstRegs)
7991	{
7992	do
7993	{
7994	unsigned int const idxHstReg = ASMBitFirstSetU32(fHstRegs) - 1;
7995	fHstRegs &= ~RT_BIT_32(idxHstReg);
7996
7997	if (pReNative->Core.aHstRegs[idxHstReg].enmWhat == kIemNativeWhat_Var)
7998	{
7999	uint8_t const idxVar = pReNative->Core.aHstRegs[idxHstReg].idxVar;
8000	AssertStmt( idxVar < RT_ELEMENTS(pReNative->Core.aVars)
8001	&& (pReNative->Core.bmVars & RT_BIT_32(idxVar))
8002	&& pReNative->Core.aVars[idxVar].idxReg == idxHstReg,
8003	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_12));
8004	switch (pReNative->Core.aVars[idxVar].enmKind)
8005	{
8006	case kIemNativeVarKind_Stack:
8007	{
8008	/* Unspill the variable register. */
8009	uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxVar);
8010	Log12(("iemNativeVarRestoreVolatileRegsPostHlpCall: unspilling idxVar=%d/idxReg=%d (slot %#x bp+%d, off=%#x)\n",
8011	idxVar, idxHstReg, idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
8012	off = iemNativeEmitLoadGprByBp(pReNative, off, idxHstReg, iemNativeStackCalcBpDisp(idxStackSlot));
8013	continue;
8014	}
8015
8016	case kIemNativeVarKind_Immediate:
8017	case kIemNativeVarKind_VarRef:
8018	case kIemNativeVarKind_GstRegRef:
8019	/* It is weird to have any of these loaded at this point. */
8020	AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_13));
8021	continue;
8022
8023	case kIemNativeVarKind_End:
8024	case kIemNativeVarKind_Invalid:
8025	break;
8026	}
8027	AssertFailed();
8028	}
8029	else
8030	{
8031	/*
8032	* Restore from temporary stack slot.
8033	*/
8034	uint8_t const idxStackSlot = pReNative->Core.aHstRegs[idxHstReg].idxStackSlot;
8035	AssertContinue(idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS && (pReNative->Core.bmStack & RT_BIT_32(idxStackSlot)));
8036	pReNative->Core.bmStack &= ~RT_BIT_32(idxStackSlot);
8037	pReNative->Core.aHstRegs[idxHstReg].idxStackSlot = UINT8_MAX;
8038
8039	off = iemNativeEmitLoadGprByBp(pReNative, off, idxHstReg, iemNativeStackCalcBpDisp(idxStackSlot));
8040	}
8041	} while (fHstRegs);
8042	}
8043	return off;
8044	}
8045
8046
8047	/**
8048	* Worker that frees the stack slots for variable @a idxVar if any allocated.
8049	*
8050	* This is used both by iemNativeVarFreeOneWorker and iemNativeEmitCallCommon.
8051	*/
8052	DECL_FORCE_INLINE(void) iemNativeVarFreeStackSlots(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
8053	{
8054	uint8_t const idxStackSlot = pReNative->Core.aVars[idxVar].idxStackSlot;
8055	if (idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS)
8056	{
8057	uint8_t const cbVar = pReNative->Core.aVars[idxVar].cbVar;
8058	uint8_t const cSlots = (cbVar + sizeof(uint64_t) - 1) / sizeof(uint64_t);
8059	uint32_t const fAllocMask = (uint32_t)(RT_BIT_32(cSlots) - 1U);
8060	Assert(cSlots > 0);
8061	Assert(((pReNative->Core.bmStack >> idxStackSlot) & fAllocMask) == fAllocMask);
8062	Log11(("iemNativeVarFreeStackSlots: idxVar=%d iSlot=%#x/%#x (cbVar=%#x)\n", idxVar, idxStackSlot, fAllocMask, cbVar));
8063	pReNative->Core.bmStack &= ~(fAllocMask << idxStackSlot);
8064	pReNative->Core.aVars[idxVar].idxStackSlot = UINT8_MAX;
8065	}
8066	else
8067	Assert(idxStackSlot == UINT8_MAX);
8068	}
8069
8070
8071	/**
8072	* Worker that frees a single variable.
8073	*
8074	* ASSUMES that @a idxVar is valid.
8075	*/
8076	DECLINLINE(void) iemNativeVarFreeOneWorker(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
8077	{
8078	Assert( pReNative->Core.aVars[idxVar].enmKind >= kIemNativeVarKind_Invalid /* Including invalid as we may have unused */
8079	&& pReNative->Core.aVars[idxVar].enmKind < kIemNativeVarKind_End); /* variables in conditional branches. */
8080	Assert(!pReNative->Core.aVars[idxVar].fRegAcquired);
8081
8082	/* Free the host register first if any assigned. */
8083	uint8_t const idxHstReg = pReNative->Core.aVars[idxVar].idxReg;
8084	if (idxHstReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
8085	{
8086	Assert(pReNative->Core.aHstRegs[idxHstReg].idxVar == idxVar);
8087	pReNative->Core.aHstRegs[idxHstReg].idxVar = UINT8_MAX;
8088	pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
8089	}
8090
8091	/* Free argument mapping. */
8092	uint8_t const uArgNo = pReNative->Core.aVars[idxVar].uArgNo;
8093	if (uArgNo < RT_ELEMENTS(pReNative->Core.aidxArgVars))
8094	pReNative->Core.aidxArgVars[uArgNo] = UINT8_MAX;
8095
8096	/* Free the stack slots. */
8097	iemNativeVarFreeStackSlots(pReNative, idxVar);
8098
8099	/* Free the actual variable. */
8100	pReNative->Core.aVars[idxVar].enmKind = kIemNativeVarKind_Invalid;
8101	pReNative->Core.bmVars &= ~RT_BIT_32(idxVar);
8102	}
8103
8104
8105	/**
8106	* Worker for iemNativeVarFreeAll that's called when there is anything to do.
8107	*/
8108	DECLINLINE(void) iemNativeVarFreeAllSlow(PIEMRECOMPILERSTATE pReNative, uint32_t bmVars)
8109	{
8110	while (bmVars != 0)
8111	{
8112	uint8_t const idxVar = ASMBitFirstSetU32(bmVars) - 1;
8113	bmVars &= ~RT_BIT_32(idxVar);
8114
8115	#if 1 /** @todo optimize by simplifying this later... */
8116	iemNativeVarFreeOneWorker(pReNative, idxVar);
8117	#else
8118	/* Only need to free the host register, the rest is done as bulk updates below. */
8119	uint8_t const idxHstReg = pReNative->Core.aVars[idxVar].idxReg;
8120	if (idxHstReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
8121	{
8122	Assert(pReNative->Core.aHstRegs[idxHstReg].idxVar == idxVar);
8123	pReNative->Core.aHstRegs[idxHstReg].idxVar = UINT8_MAX;
8124	pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxHstReg);
8125	}
8126	#endif
8127	}
8128	#if 0 /** @todo optimize by simplifying this later... */
8129	pReNative->Core.bmVars = 0;
8130	pReNative->Core.bmStack = 0;
8131	pReNative->Core.u64ArgVars = UINT64_MAX;
8132	#endif
8133	}
8134
8135
8136	/**
8137	* This is called by IEM_MC_END() to clean up all variables.
8138	*/
8139	DECL_FORCE_INLINE(void) iemNativeVarFreeAll(PIEMRECOMPILERSTATE pReNative)
8140	{
8141	uint32_t const bmVars = pReNative->Core.bmVars;
8142	if (bmVars != 0)
8143	iemNativeVarFreeAllSlow(pReNative, bmVars);
8144	Assert(pReNative->Core.u64ArgVars == UINT64_MAX);
8145	Assert(pReNative->Core.bmStack == 0);
8146	}
8147
8148
8149	#define IEM_MC_FREE_LOCAL(a_Name) iemNativeVarFreeLocal(pReNative, a_Name)
8150
8151	/**
8152	* This is called by IEM_MC_FREE_LOCAL.
8153	*/
8154	DECLINLINE(void) iemNativeVarFreeLocal(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
8155	{
8156	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
8157	Assert(pReNative->Core.aVars[idxVar].uArgNo == UINT8_MAX);
8158	iemNativeVarFreeOneWorker(pReNative, idxVar);
8159	}
8160
8161
8162	#define IEM_MC_FREE_ARG(a_Name) iemNativeVarFreeArg(pReNative, a_Name)
8163
8164	/**
8165	* This is called by IEM_MC_FREE_ARG.
8166	*/
8167	DECLINLINE(void) iemNativeVarFreeArg(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
8168	{
8169	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
8170	Assert(pReNative->Core.aVars[idxVar].uArgNo < RT_ELEMENTS(pReNative->Core.aidxArgVars));
8171	iemNativeVarFreeOneWorker(pReNative, idxVar);
8172	}
8173
8174
8175	#define IEM_MC_ASSIGN_TO_SMALLER(a_VarDst, a_VarSrcEol) off = iemNativeVarAssignToSmaller(pReNative, off, a_VarDst, a_VarSrcEol)
8176
8177	/**
8178	* This is called by IEM_MC_ASSIGN_TO_SMALLER.
8179	*/
8180	DECL_INLINE_THROW(uint32_t)
8181	iemNativeVarAssignToSmaller(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarDst, uint8_t idxVarSrc)
8182	{
8183	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarDst);
8184	AssertStmt(pReNative->Core.aVars[idxVarDst].enmKind == kIemNativeVarKind_Invalid,
8185	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_UNEXPECTED_KIND));
8186	Assert( pReNative->Core.aVars[idxVarDst].cbVar == sizeof(uint16_t)
8187	\|\| pReNative->Core.aVars[idxVarDst].cbVar == sizeof(uint32_t));
8188
8189	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarSrc);
8190	AssertStmt( pReNative->Core.aVars[idxVarSrc].enmKind == kIemNativeVarKind_Stack
8191	\|\| pReNative->Core.aVars[idxVarSrc].enmKind == kIemNativeVarKind_Immediate,
8192	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_UNEXPECTED_KIND));
8193
8194	Assert(pReNative->Core.aVars[idxVarDst].cbVar < pReNative->Core.aVars[idxVarSrc].cbVar);
8195
8196	/*
8197	* Special case for immediates.
8198	*/
8199	if (pReNative->Core.aVars[idxVarSrc].enmKind == kIemNativeVarKind_Immediate)
8200	{
8201	switch (pReNative->Core.aVars[idxVarDst].cbVar)
8202	{
8203	case sizeof(uint16_t):
8204	iemNativeVarSetKindToConst(pReNative, idxVarDst, (uint16_t)pReNative->Core.aVars[idxVarSrc].u.uValue);
8205	break;
8206	case sizeof(uint32_t):
8207	iemNativeVarSetKindToConst(pReNative, idxVarDst, (uint32_t)pReNative->Core.aVars[idxVarSrc].u.uValue);
8208	break;
8209	default: AssertFailed(); break;
8210	}
8211	}
8212	else
8213	{
8214	/*
8215	* The generic solution for now.
8216	*/
8217	/** @todo optimize this by having the python script make sure the source
8218	* variable passed to IEM_MC_ASSIGN_TO_SMALLER is not used after the
8219	* statement. Then we could just transfer the register assignments. */
8220	uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off);
8221	uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off);
8222	switch (pReNative->Core.aVars[idxVarDst].cbVar)
8223	{
8224	case sizeof(uint16_t):
8225	off = iemNativeEmitLoadGprFromGpr16(pReNative, off, idxRegDst, idxRegSrc);
8226	break;
8227	case sizeof(uint32_t):
8228	off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxRegDst, idxRegSrc);
8229	break;
8230	default: AssertFailed(); break;
8231	}
8232	iemNativeVarRegisterRelease(pReNative, idxVarSrc);
8233	iemNativeVarRegisterRelease(pReNative, idxVarDst);
8234	}
8235	return off;
8236	}
8237
8238
8239
8240	/*********************************************************************************************************************************
8241	* Emitters for IEM_MC_CALL_CIMPL_XXX *
8242	*********************************************************************************************************************************/
8243
8244	/**
8245	* Emits code to load a reference to the given guest register into @a idxGprDst.
8246	*/
8247	DECL_INLINE_THROW(uint32_t)
8248	iemNativeEmitLeaGprByGstRegRef(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxGprDst,
8249	IEMNATIVEGSTREGREF enmClass, uint8_t idxRegInClass)
8250	{
8251	/*
8252	* Get the offset relative to the CPUMCTX structure.
8253	*/
8254	uint32_t offCpumCtx;
8255	switch (enmClass)
8256	{
8257	case kIemNativeGstRegRef_Gpr:
8258	Assert(idxRegInClass < 16);
8259	offCpumCtx = RT_UOFFSETOF_DYN(CPUMCTX, aGRegs[idxRegInClass]);
8260	break;
8261
8262	case kIemNativeGstRegRef_GprHighByte: /*< AH, CH, DH, BH/
8263	Assert(idxRegInClass < 4);
8264	offCpumCtx = RT_UOFFSETOF_DYN(CPUMCTX, aGRegs[0].bHi) + idxRegInClass * sizeof(CPUMCTXGREG);
8265	break;
8266
8267	case kIemNativeGstRegRef_EFlags:
8268	Assert(idxRegInClass == 0);
8269	offCpumCtx = RT_UOFFSETOF(CPUMCTX, eflags);
8270	break;
8271
8272	case kIemNativeGstRegRef_MxCsr:
8273	Assert(idxRegInClass == 0);
8274	offCpumCtx = RT_UOFFSETOF(CPUMCTX, XState.x87.MXCSR);
8275	break;
8276
8277	case kIemNativeGstRegRef_FpuReg:
8278	Assert(idxRegInClass < 8);
8279	AssertFailed(); /** @todo what kind of indexing? */
8280	offCpumCtx = RT_UOFFSETOF_DYN(CPUMCTX, XState.x87.aRegs[idxRegInClass]);
8281	break;
8282
8283	case kIemNativeGstRegRef_MReg:
8284	Assert(idxRegInClass < 8);
8285	AssertFailed(); /** @todo what kind of indexing? */
8286	offCpumCtx = RT_UOFFSETOF_DYN(CPUMCTX, XState.x87.aRegs[idxRegInClass]);
8287	break;
8288
8289	case kIemNativeGstRegRef_XReg:
8290	Assert(idxRegInClass < 16);
8291	offCpumCtx = RT_UOFFSETOF_DYN(CPUMCTX, XState.x87.aXMM[idxRegInClass]);
8292	break;
8293
8294	default:
8295	AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_5));
8296	}
8297
8298	/*
8299	* Load the value into the destination register.
8300	*/
8301	#ifdef RT_ARCH_AMD64
8302	off = iemNativeEmitLeaGprByVCpu(pReNative, off, idxGprDst, offCpumCtx + RT_UOFFSETOF(VMCPUCC, cpum.GstCtx));
8303
8304	#elif defined(RT_ARCH_ARM64)
8305	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
8306	Assert(offCpumCtx < 4096);
8307	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(false /fSub/, idxGprDst, IEMNATIVE_REG_FIXED_PCPUMCTX, offCpumCtx);
8308
8309	#else
8310	# error "Port me!"
8311	#endif
8312
8313	return off;
8314	}
8315
8316
8317	/**
8318	* Common code for CIMPL and AIMPL calls.
8319	*
8320	* These are calls that uses argument variables and such. They should not be
8321	* confused with internal calls required to implement an MC operation,
8322	* like a TLB load and similar.
8323	*
8324	* Upon return all that is left to do is to load any hidden arguments and
8325	* perform the call. All argument variables are freed.
8326	*
8327	* @returns New code buffer offset; throws VBox status code on error.
8328	* @param pReNative The native recompile state.
8329	* @param off The code buffer offset.
8330	* @param cArgs The total nubmer of arguments (includes hidden
8331	* count).
8332	* @param cHiddenArgs The number of hidden arguments. The hidden
8333	* arguments must not have any variable declared for
8334	* them, whereas all the regular arguments must
8335	* (tstIEMCheckMc ensures this).
8336	*/
8337	DECL_HIDDEN_THROW(uint32_t)
8338	iemNativeEmitCallCommon(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs, uint8_t cHiddenArgs)
8339	{
8340	#ifdef VBOX_STRICT
8341	/*
8342	* Assert sanity.
8343	*/
8344	Assert(cArgs <= IEMNATIVE_CALL_MAX_ARG_COUNT);
8345	Assert(cHiddenArgs < IEMNATIVE_CALL_ARG_GREG_COUNT);
8346	for (unsigned i = 0; i < cHiddenArgs; i++)
8347	Assert(pReNative->Core.aidxArgVars[i] == UINT8_MAX);
8348	for (unsigned i = cHiddenArgs; i < cArgs; i++)
8349	{
8350	Assert(pReNative->Core.aidxArgVars[i] != UINT8_MAX); /* checked by tstIEMCheckMc.cpp */
8351	Assert(pReNative->Core.bmVars & RT_BIT_32(pReNative->Core.aidxArgVars[i]));
8352	}
8353	iemNativeRegAssertSanity(pReNative);
8354	#endif
8355
8356	/*
8357	* Before we do anything else, go over variables that are referenced and
8358	* make sure they are not in a register.
8359	*/
8360	uint32_t bmVars = pReNative->Core.bmVars;
8361	if (bmVars)
8362	{
8363	do
8364	{
8365	uint8_t const idxVar = ASMBitFirstSetU32(bmVars) - 1;
8366	bmVars &= ~RT_BIT_32(idxVar);
8367
8368	if (pReNative->Core.aVars[idxVar].idxReferrerVar != UINT8_MAX)
8369	{
8370	uint8_t const idxRegOld = pReNative->Core.aVars[idxVar].idxReg;
8371	if (idxRegOld < RT_ELEMENTS(pReNative->Core.aHstRegs))
8372	{
8373	uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxVar);
8374	Log12(("iemNativeEmitCallCommon: spilling idxVar=%d/idxReg=%d (referred to by %d) onto the stack (slot %#x bp+%d, off=%#x)\n",
8375	idxVar, idxRegOld, pReNative->Core.aVars[idxVar].idxReferrerVar,
8376	idxStackSlot, iemNativeStackCalcBpDisp(idxStackSlot), off));
8377	off = iemNativeEmitStoreGprByBp(pReNative, off, iemNativeStackCalcBpDisp(idxStackSlot), idxRegOld);
8378
8379	pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
8380	pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxRegOld);
8381	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxRegOld);
8382	pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows;
8383	pReNative->Core.aHstRegs[idxRegOld].fGstRegShadows = 0;
8384	}
8385	}
8386	} while (bmVars != 0);
8387	#if 0 //def VBOX_STRICT
8388	iemNativeRegAssertSanity(pReNative);
8389	#endif
8390	}
8391
8392	uint8_t const cRegArgs = RT_MIN(cArgs, RT_ELEMENTS(g_aidxIemNativeCallRegs));
8393
8394	/*
8395	* First, go over the host registers that will be used for arguments and make
8396	* sure they either hold the desired argument or are free.
8397	*/
8398	if (pReNative->Core.bmHstRegs & g_afIemNativeCallRegs[cRegArgs])
8399	{
8400	for (uint32_t i = 0; i < cRegArgs; i++)
8401	{
8402	uint8_t const idxArgReg = g_aidxIemNativeCallRegs[i];
8403	if (pReNative->Core.bmHstRegs & RT_BIT_32(idxArgReg))
8404	{
8405	if (pReNative->Core.aHstRegs[idxArgReg].enmWhat == kIemNativeWhat_Var)
8406	{
8407	uint8_t const idxVar = pReNative->Core.aHstRegs[idxArgReg].idxVar;
8408	Assert(idxVar < RT_ELEMENTS(pReNative->Core.aVars));
8409	Assert(pReNative->Core.aVars[idxVar].idxReg == idxArgReg);
8410	uint8_t const uArgNo = pReNative->Core.aVars[idxVar].uArgNo;
8411	if (uArgNo == i)
8412	{ /* prefect */ }
8413	/* The variable allocator logic should make sure this is impossible,
8414	except for when the return register is used as a parameter (ARM,
8415	but not x86). */
8416	#if RT_BIT_32(IEMNATIVE_CALL_RET_GREG) & IEMNATIVE_CALL_ARGS_GREG_MASK
8417	else if (idxArgReg == IEMNATIVE_CALL_RET_GREG && uArgNo != UINT8_MAX)
8418	{
8419	# ifdef IEMNATIVE_FP_OFF_STACK_ARG0
8420	# error "Implement this"
8421	# endif
8422	Assert(uArgNo < IEMNATIVE_CALL_ARG_GREG_COUNT);
8423	uint8_t const idxFinalArgReg = g_aidxIemNativeCallRegs[uArgNo];
8424	AssertStmt(!(pReNative->Core.bmHstRegs & RT_BIT_32(idxFinalArgReg)),
8425	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_10));
8426	off = iemNativeRegMoveVar(pReNative, off, idxVar, idxArgReg, idxFinalArgReg, "iemNativeEmitCallCommon");
8427	}
8428	#endif
8429	else
8430	{
8431	AssertStmt(uArgNo == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_10));
8432
8433	if (pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack)
8434	off = iemNativeRegMoveOrSpillStackVar(pReNative, off, idxVar);
8435	else
8436	{
8437	/* just free it, can be reloaded if used again */
8438	pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
8439	pReNative->Core.bmHstRegs &= ~RT_BIT_32(idxArgReg);
8440	iemNativeRegClearGstRegShadowing(pReNative, idxArgReg, off);
8441	}
8442	}
8443	}
8444	else
8445	AssertStmt(pReNative->Core.aHstRegs[idxArgReg].enmWhat == kIemNativeWhat_Arg,
8446	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_REG_IPE_8));
8447	}
8448	}
8449	#if 0 //def VBOX_STRICT
8450	iemNativeRegAssertSanity(pReNative);
8451	#endif
8452	}
8453
8454	Assert(!(pReNative->Core.bmHstRegs & g_afIemNativeCallRegs[cHiddenArgs])); /* No variables for hidden arguments. */
8455
8456	#ifdef IEMNATIVE_FP_OFF_STACK_ARG0
8457	/*
8458	* If there are any stack arguments, make sure they are in their place as well.
8459	*
8460	* We can use IEMNATIVE_CALL_ARG0_GREG as temporary register since we'll (or
8461	* the caller) be loading it later and it must be free (see first loop).
8462	*/
8463	if (cArgs > IEMNATIVE_CALL_ARG_GREG_COUNT)
8464	{
8465	for (unsigned i = IEMNATIVE_CALL_ARG_GREG_COUNT; i < cArgs; i++)
8466	{
8467	uint8_t const idxVar = pReNative->Core.aidxArgVars[i];
8468	int32_t const offBpDisp = g_aoffIemNativeCallStackArgBpDisp[i - IEMNATIVE_CALL_ARG_GREG_COUNT];
8469	if (pReNative->Core.aVars[idxVar].idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
8470	{
8471	Assert(pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack); /* Imm as well? */
8472	off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDisp, pReNative->Core.aVars[idxVar].idxReg);
8473	pReNative->Core.bmHstRegs &= ~RT_BIT_32(pReNative->Core.aVars[idxVar].idxReg);
8474	pReNative->Core.aVars[idxVar].idxReg = UINT8_MAX;
8475	}
8476	else
8477	{
8478	/* Use ARG0 as temp for stuff we need registers for. */
8479	switch (pReNative->Core.aVars[idxVar].enmKind)
8480	{
8481	case kIemNativeVarKind_Stack:
8482	{
8483	uint8_t const idxStackSlot = pReNative->Core.aVars[idxVar].idxStackSlot;
8484	AssertStmt(idxStackSlot != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_NOT_INITIALIZED));
8485	off = iemNativeEmitLoadGprByBp(pReNative, off, IEMNATIVE_CALL_ARG0_GREG /* is free */,
8486	iemNativeStackCalcBpDisp(idxStackSlot));
8487	off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDisp, IEMNATIVE_CALL_ARG0_GREG);
8488	continue;
8489	}
8490
8491	case kIemNativeVarKind_Immediate:
8492	off = iemNativeEmitStoreImm64ByBp(pReNative, off, offBpDisp, pReNative->Core.aVars[idxVar].u.uValue);
8493	continue;
8494
8495	case kIemNativeVarKind_VarRef:
8496	{
8497	uint8_t const idxOtherVar = pReNative->Core.aVars[idxVar].u.idxRefVar;
8498	Assert(idxOtherVar < RT_ELEMENTS(pReNative->Core.aVars));
8499	uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxOtherVar);
8500	int32_t const offBpDispOther = iemNativeStackCalcBpDisp(idxStackSlot);
8501	uint8_t const idxRegOther = pReNative->Core.aVars[idxOtherVar].idxReg;
8502	if (idxRegOther < RT_ELEMENTS(pReNative->Core.aHstRegs))
8503	{
8504	off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDispOther, idxRegOther);
8505	iemNativeRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
8506	Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
8507	}
8508	Assert( pReNative->Core.aVars[idxOtherVar].idxStackSlot != UINT8_MAX
8509	&& pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
8510	off = iemNativeEmitLeaGprByBp(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, offBpDispOther);
8511	off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDisp, IEMNATIVE_CALL_ARG0_GREG);
8512	continue;
8513	}
8514
8515	case kIemNativeVarKind_GstRegRef:
8516	off = iemNativeEmitLeaGprByGstRegRef(pReNative, off, IEMNATIVE_CALL_ARG0_GREG,
8517	pReNative->Core.aVars[idxVar].u.GstRegRef.enmClass,
8518	pReNative->Core.aVars[idxVar].u.GstRegRef.idx);
8519	off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDisp, IEMNATIVE_CALL_ARG0_GREG);
8520	continue;
8521
8522	case kIemNativeVarKind_Invalid:
8523	case kIemNativeVarKind_End:
8524	break;
8525	}
8526	AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_3));
8527	}
8528	}
8529	# if 0 //def VBOX_STRICT
8530	iemNativeRegAssertSanity(pReNative);
8531	# endif
8532	}
8533	#else
8534	AssertCompile(IEMNATIVE_CALL_MAX_ARG_COUNT <= IEMNATIVE_CALL_ARG_GREG_COUNT);
8535	#endif
8536
8537	/*
8538	* Make sure the argument variables are loaded into their respective registers.
8539	*
8540	* We can optimize this by ASSUMING that any register allocations are for
8541	* registeres that have already been loaded and are ready. The previous step
8542	* saw to that.
8543	*/
8544	if (~pReNative->Core.bmHstRegs & (g_afIemNativeCallRegs[cRegArgs] & ~g_afIemNativeCallRegs[cHiddenArgs]))
8545	{
8546	for (unsigned i = cHiddenArgs; i < cRegArgs; i++)
8547	{
8548	uint8_t const idxArgReg = g_aidxIemNativeCallRegs[i];
8549	if (pReNative->Core.bmHstRegs & RT_BIT_32(idxArgReg))
8550	Assert( pReNative->Core.aHstRegs[idxArgReg].idxVar == pReNative->Core.aidxArgVars[i]
8551	&& pReNative->Core.aVars[pReNative->Core.aidxArgVars[i]].uArgNo == i
8552	&& pReNative->Core.aVars[pReNative->Core.aidxArgVars[i]].idxReg == idxArgReg);
8553	else
8554	{
8555	uint8_t const idxVar = pReNative->Core.aidxArgVars[i];
8556	if (pReNative->Core.aVars[idxVar].idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
8557	{
8558	Assert(pReNative->Core.aVars[idxVar].enmKind == kIemNativeVarKind_Stack);
8559	off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxArgReg, pReNative->Core.aVars[idxVar].idxReg);
8560	pReNative->Core.bmHstRegs = (pReNative->Core.bmHstRegs & ~RT_BIT_32(pReNative->Core.aVars[idxVar].idxReg))
8561	\| RT_BIT_32(idxArgReg);
8562	pReNative->Core.aVars[idxVar].idxReg = idxArgReg;
8563	}
8564	else
8565	{
8566	/* Use ARG0 as temp for stuff we need registers for. */
8567	switch (pReNative->Core.aVars[idxVar].enmKind)
8568	{
8569	case kIemNativeVarKind_Stack:
8570	{
8571	uint8_t const idxStackSlot = pReNative->Core.aVars[idxVar].idxStackSlot;
8572	AssertStmt(idxStackSlot != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_NOT_INITIALIZED));
8573	off = iemNativeEmitLoadGprByBp(pReNative, off, idxArgReg, iemNativeStackCalcBpDisp(idxStackSlot));
8574	continue;
8575	}
8576
8577	case kIemNativeVarKind_Immediate:
8578	off = iemNativeEmitLoadGprImm64(pReNative, off, idxArgReg, pReNative->Core.aVars[idxVar].u.uValue);
8579	continue;
8580
8581	case kIemNativeVarKind_VarRef:
8582	{
8583	uint8_t const idxOtherVar = pReNative->Core.aVars[idxVar].u.idxRefVar;
8584	Assert(idxOtherVar < RT_ELEMENTS(pReNative->Core.aVars));
8585	uint8_t const idxStackSlot = iemNativeVarGetStackSlot(pReNative, idxOtherVar);
8586	int32_t const offBpDispOther = iemNativeStackCalcBpDisp(idxStackSlot);
8587	uint8_t const idxRegOther = pReNative->Core.aVars[idxOtherVar].idxReg;
8588	if (idxRegOther < RT_ELEMENTS(pReNative->Core.aHstRegs))
8589	{
8590	off = iemNativeEmitStoreGprByBp(pReNative, off, offBpDispOther, idxRegOther);
8591	iemNativeRegFreeVar(pReNative, idxRegOther, true); /** @todo const ref? */
8592	Assert(pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
8593	}
8594	Assert( pReNative->Core.aVars[idxOtherVar].idxStackSlot != UINT8_MAX
8595	&& pReNative->Core.aVars[idxOtherVar].idxReg == UINT8_MAX);
8596	off = iemNativeEmitLeaGprByBp(pReNative, off, idxArgReg, offBpDispOther);
8597	continue;
8598	}
8599
8600	case kIemNativeVarKind_GstRegRef:
8601	off = iemNativeEmitLeaGprByGstRegRef(pReNative, off, idxArgReg,
8602	pReNative->Core.aVars[idxVar].u.GstRegRef.enmClass,
8603	pReNative->Core.aVars[idxVar].u.GstRegRef.idx);
8604	continue;
8605
8606	case kIemNativeVarKind_Invalid:
8607	case kIemNativeVarKind_End:
8608	break;
8609	}
8610	AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_3));
8611	}
8612	}
8613	}
8614	#if 0 //def VBOX_STRICT
8615	iemNativeRegAssertSanity(pReNative);
8616	#endif
8617	}
8618	#ifdef VBOX_STRICT
8619	else
8620	for (unsigned i = cHiddenArgs; i < cRegArgs; i++)
8621	{
8622	Assert(pReNative->Core.aVars[pReNative->Core.aidxArgVars[i]].uArgNo == i);
8623	Assert(pReNative->Core.aVars[pReNative->Core.aidxArgVars[i]].idxReg == g_aidxIemNativeCallRegs[i]);
8624	}
8625	#endif
8626
8627	/*
8628	* Free all argument variables (simplified).
8629	* Their lifetime always expires with the call they are for.
8630	*/
8631	/** @todo Make the python script check that arguments aren't used after
8632	* IEM_MC_CALL_XXXX. */
8633	/** @todo There is a special with IEM_MC_MEM_MAP_U16_RW and friends requiring
8634	* a IEM_MC_MEM_COMMIT_AND_UNMAP_RW after a AIMPL call typically with
8635	* an argument value. There is also some FPU stuff. */
8636	for (uint32_t i = cHiddenArgs; i < cArgs; i++)
8637	{
8638	uint8_t const idxVar = pReNative->Core.aidxArgVars[i];
8639	Assert(idxVar < RT_ELEMENTS(pReNative->Core.aVars));
8640
8641	/* no need to free registers: */
8642	AssertMsg(i < IEMNATIVE_CALL_ARG_GREG_COUNT
8643	? pReNative->Core.aVars[idxVar].idxReg == g_aidxIemNativeCallRegs[i]
8644	\|\| pReNative->Core.aVars[idxVar].idxReg == UINT8_MAX
8645	: pReNative->Core.aVars[idxVar].idxReg == UINT8_MAX,
8646	("i=%d idxVar=%d idxReg=%d, expected %d\n", i, idxVar, pReNative->Core.aVars[idxVar].idxReg,
8647	i < IEMNATIVE_CALL_ARG_GREG_COUNT ? g_aidxIemNativeCallRegs[i] : UINT8_MAX));
8648
8649	pReNative->Core.aidxArgVars[i] = UINT8_MAX;
8650	pReNative->Core.bmVars &= ~RT_BIT_32(idxVar);
8651	iemNativeVarFreeStackSlots(pReNative, idxVar);
8652	}
8653	Assert(pReNative->Core.u64ArgVars == UINT64_MAX);
8654
8655	/*
8656	* Flush volatile registers as we make the call.
8657	*/
8658	off = iemNativeRegMoveAndFreeAndFlushAtCall(pReNative, off, cRegArgs);
8659
8660	return off;
8661	}
8662
8663
8664	/** Common emit function for IEM_MC_CALL_CIMPL_XXXX. */
8665	DECL_HIDDEN_THROW(uint32_t)
8666	iemNativeEmitCallCImplCommon(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cbInstr, uint8_t idxInstr,
8667	uint64_t fGstShwFlush, uintptr_t pfnCImpl, uint8_t cArgs)
8668
8669	{
8670	/*
8671	* Do all the call setup and cleanup.
8672	*/
8673	off = iemNativeEmitCallCommon(pReNative, off, cArgs + IEM_CIMPL_HIDDEN_ARGS, IEM_CIMPL_HIDDEN_ARGS);
8674
8675	/*
8676	* Load the two or three hidden arguments.
8677	*/
8678	#if defined(VBOXSTRICTRC_STRICT_ENABLED) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_AMD64)
8679	off = iemNativeEmitLeaGprByBp(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_FP_OFF_IN_SHADOW_ARG0); /* rcStrict */
8680	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG1_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
8681	off = iemNativeEmitLoadGpr8Imm(pReNative, off, IEMNATIVE_CALL_ARG2_GREG, cbInstr);
8682	#else
8683	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
8684	off = iemNativeEmitLoadGpr8Imm(pReNative, off, IEMNATIVE_CALL_ARG1_GREG, cbInstr);
8685	#endif
8686
8687	/*
8688	* Make the call and check the return code.
8689	*
8690	* Shadow PC copies are always flushed here, other stuff depends on flags.
8691	* Segment and general purpose registers are explictily flushed via the
8692	* IEM_MC_HINT_FLUSH_GUEST_SHADOW_GREG and IEM_MC_HINT_FLUSH_GUEST_SHADOW_SREG
8693	* macros.
8694	*/
8695	off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)pfnCImpl);
8696	#if defined(VBOXSTRICTRC_STRICT_ENABLED) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_AMD64)
8697	off = iemNativeEmitLoadGprByBpU32(pReNative, off, X86_GREG_xAX, IEMNATIVE_FP_OFF_IN_SHADOW_ARG0); /* rcStrict (see above) */
8698	#endif
8699	fGstShwFlush = iemNativeCImplFlagsToGuestShadowFlushMask(pReNative->fCImpl, fGstShwFlush \| RT_BIT_64(kIemNativeGstReg_Pc));
8700	if (!(pReNative->fMc & IEM_MC_F_WITHOUT_FLAGS)) /** @todo We don't emit with-flags/without-flags variations for CIMPL calls. */
8701	fGstShwFlush \|= RT_BIT_64(kIemNativeGstReg_EFlags);
8702	iemNativeRegFlushGuestShadows(pReNative, fGstShwFlush);
8703
8704	return iemNativeEmitCheckCallRetAndPassUp(pReNative, off, idxInstr);
8705	}
8706
8707
8708	#define IEM_MC_CALL_CIMPL_1_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) \
8709	off = iemNativeEmitCallCImpl1(pReNative, off, a_cbInstr, pCallEntry->idxInstr, a_fGstShwFlush, (uintptr_t)a_pfnCImpl, a0)
8710
8711	/** Emits code for IEM_MC_CALL_CIMPL_1. */
8712	DECL_INLINE_THROW(uint32_t)
8713	iemNativeEmitCallCImpl1(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cbInstr, uint8_t idxInstr, uint64_t fGstShwFlush,
8714	uintptr_t pfnCImpl, uint8_t idxArg0)
8715	{
8716	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg0, 0 + IEM_CIMPL_HIDDEN_ARGS);
8717	return iemNativeEmitCallCImplCommon(pReNative, off, cbInstr, idxInstr, fGstShwFlush, pfnCImpl, 1);
8718	}
8719
8720
8721	#define IEM_MC_CALL_CIMPL_2_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) \
8722	off = iemNativeEmitCallCImpl2(pReNative, off, a_cbInstr, pCallEntry->idxInstr, a_fGstShwFlush, (uintptr_t)a_pfnCImpl, a0, a1)
8723
8724	/** Emits code for IEM_MC_CALL_CIMPL_2. */
8725	DECL_INLINE_THROW(uint32_t)
8726	iemNativeEmitCallCImpl2(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cbInstr, uint8_t idxInstr, uint64_t fGstShwFlush,
8727	uintptr_t pfnCImpl, uint8_t idxArg0, uint8_t idxArg1)
8728	{
8729	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg0, 0 + IEM_CIMPL_HIDDEN_ARGS);
8730	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg1, 1 + IEM_CIMPL_HIDDEN_ARGS);
8731	return iemNativeEmitCallCImplCommon(pReNative, off, cbInstr, idxInstr, fGstShwFlush, pfnCImpl, 2);
8732	}
8733
8734
8735	#define IEM_MC_CALL_CIMPL_3_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) \
8736	off = iemNativeEmitCallCImpl3(pReNative, off, a_cbInstr, pCallEntry->idxInstr, a_fGstShwFlush, \
8737	(uintptr_t)a_pfnCImpl, a0, a1, a2)
8738
8739	/** Emits code for IEM_MC_CALL_CIMPL_3. */
8740	DECL_INLINE_THROW(uint32_t)
8741	iemNativeEmitCallCImpl3(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cbInstr, uint8_t idxInstr, uint64_t fGstShwFlush,
8742	uintptr_t pfnCImpl, uint8_t idxArg0, uint8_t idxArg1, uint8_t idxArg2)
8743	{
8744	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg0, 0 + IEM_CIMPL_HIDDEN_ARGS);
8745	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg1, 1 + IEM_CIMPL_HIDDEN_ARGS);
8746	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg2, 2 + IEM_CIMPL_HIDDEN_ARGS);
8747	return iemNativeEmitCallCImplCommon(pReNative, off, cbInstr, idxInstr, fGstShwFlush, pfnCImpl, 3);
8748	}
8749
8750
8751	#define IEM_MC_CALL_CIMPL_4_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3) \
8752	off = iemNativeEmitCallCImpl4(pReNative, off, a_cbInstr, pCallEntry->idxInstr, a_fGstShwFlush, \
8753	(uintptr_t)a_pfnCImpl, a0, a1, a2, a3)
8754
8755	/** Emits code for IEM_MC_CALL_CIMPL_4. */
8756	DECL_INLINE_THROW(uint32_t)
8757	iemNativeEmitCallCImpl4(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cbInstr, uint8_t idxInstr, uint64_t fGstShwFlush,
8758	uintptr_t pfnCImpl, uint8_t idxArg0, uint8_t idxArg1, uint8_t idxArg2, uint8_t idxArg3)
8759	{
8760	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg0, 0 + IEM_CIMPL_HIDDEN_ARGS);
8761	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg1, 1 + IEM_CIMPL_HIDDEN_ARGS);
8762	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg2, 2 + IEM_CIMPL_HIDDEN_ARGS);
8763	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg3, 3 + IEM_CIMPL_HIDDEN_ARGS);
8764	return iemNativeEmitCallCImplCommon(pReNative, off, cbInstr, idxInstr, fGstShwFlush, pfnCImpl, 4);
8765	}
8766
8767
8768	#define IEM_MC_CALL_CIMPL_5_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3, a4) \
8769	off = iemNativeEmitCallCImpl5(pReNative, off, a_cbInstr, pCallEntry->idxInstr, a_fGstShwFlush, \
8770	(uintptr_t)a_pfnCImpl, a0, a1, a2, a3, a4)
8771
8772	/** Emits code for IEM_MC_CALL_CIMPL_4. */
8773	DECL_INLINE_THROW(uint32_t)
8774	iemNativeEmitCallCImpl5(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cbInstr, uint8_t idxInstr, uint64_t fGstShwFlush,
8775	uintptr_t pfnCImpl, uint8_t idxArg0, uint8_t idxArg1, uint8_t idxArg2, uint8_t idxArg3, uint8_t idxArg4)
8776	{
8777	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg0, 0 + IEM_CIMPL_HIDDEN_ARGS);
8778	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg1, 1 + IEM_CIMPL_HIDDEN_ARGS);
8779	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg2, 2 + IEM_CIMPL_HIDDEN_ARGS);
8780	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg3, 3 + IEM_CIMPL_HIDDEN_ARGS);
8781	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg4, 4 + IEM_CIMPL_HIDDEN_ARGS);
8782	return iemNativeEmitCallCImplCommon(pReNative, off, cbInstr, idxInstr, fGstShwFlush, pfnCImpl, 5);
8783	}
8784
8785
8786	/** Recompiler debugging: Flush guest register shadow copies. */
8787	#define IEM_MC_HINT_FLUSH_GUEST_SHADOW(g_fGstShwFlush) iemNativeRegFlushGuestShadows(pReNative, g_fGstShwFlush)
8788
8789
8790
8791	/*********************************************************************************************************************************
8792	* Emitters for IEM_MC_CALL_VOID_AIMPL_XXX and IEM_MC_CALL_AIMPL_XXX *
8793	*********************************************************************************************************************************/
8794
8795	/**
8796	* Common worker for IEM_MC_CALL_VOID_AIMPL_XXX and IEM_MC_CALL_AIMPL_XXX.
8797	*/
8798	DECL_INLINE_THROW(uint32_t)
8799	iemNativeEmitCallAImplCommon(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarRc,
8800	uintptr_t pfnAImpl, uint8_t cArgs)
8801	{
8802	if (idxVarRc != UINT8_MAX)
8803	{
8804	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarRc);
8805	AssertStmt(pReNative->Core.aVars[idxVarRc].uArgNo == UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_8));
8806	AssertStmt(pReNative->Core.aVars[idxVarRc].cbVar <= sizeof(uint64_t), IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_IPE_9));
8807	}
8808
8809	/*
8810	* Do all the call setup and cleanup.
8811	*/
8812	off = iemNativeEmitCallCommon(pReNative, off, cArgs, 0 /cHiddenArgs/);
8813
8814	/*
8815	* Make the call and update the return code variable if we've got one.
8816	*/
8817	off = iemNativeEmitCallImm(pReNative, off, pfnAImpl);
8818	if (idxVarRc < RT_ELEMENTS(pReNative->Core.aVars))
8819	{
8820	pReNative->pInstrBuf[off++] = 0xcc; /** @todo test IEM_MC_CALL_AIMPL_3 and IEM_MC_CALL_AIMPL_4 return codes. */
8821	iemNativeVarRegisterSet(pReNative, idxVarRc, IEMNATIVE_CALL_RET_GREG, off);
8822	}
8823
8824	return off;
8825	}
8826
8827
8828
8829	#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) \
8830	off = iemNativeEmitCallAImpl0(pReNative, off, UINT8_MAX /idxVarRc/, (uintptr_t)(a_pfn))
8831
8832	#define IEM_MC_CALL_AIMPL_0(a_rc, a_pfn) \
8833	off = iemNativeEmitCallAImpl0(pReNative, off, a_rc, (uintptr_t)(a_pfn))
8834
8835	/** Emits code for IEM_MC_CALL_VOID_AIMPL_0 and IEM_MC_CALL_AIMPL_0. */
8836	DECL_INLINE_THROW(uint32_t)
8837	iemNativeEmitCallAImpl0(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarRc, uintptr_t pfnAImpl)
8838	{
8839	return iemNativeEmitCallAImplCommon(pReNative, off, idxVarRc, pfnAImpl, 0);
8840	}
8841
8842
8843	#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) \
8844	off = iemNativeEmitCallAImpl1(pReNative, off, UINT8_MAX /idxVarRc/, (uintptr_t)(a_pfn), a0)
8845
8846	#define IEM_MC_CALL_AIMPL_1(a_rc, a_pfn, a0) \
8847	off = iemNativeEmitCallAImpl1(pReNative, off, a_rc, (uintptr_t)(a_pfn), a0)
8848
8849	/** Emits code for IEM_MC_CALL_VOID_AIMPL_1 and IEM_MC_CALL_AIMPL_1. */
8850	DECL_INLINE_THROW(uint32_t)
8851	iemNativeEmitCallAImpl1(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarRc, uintptr_t pfnAImpl, uint8_t idxArg0)
8852	{
8853	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg0, 0);
8854	return iemNativeEmitCallAImplCommon(pReNative, off, idxVarRc, pfnAImpl, 1);
8855	}
8856
8857
8858	#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) \
8859	off = iemNativeEmitCallAImpl2(pReNative, off, UINT8_MAX /idxVarRc/, (uintptr_t)(a_pfn), a0, a1)
8860
8861	#define IEM_MC_CALL_AIMPL_2(a_rc, a_pfn, a0, a1) \
8862	off = iemNativeEmitCallAImpl2(pReNative, off, a_rc, (uintptr_t)(a_pfn), a0, a1)
8863
8864	/** Emits code for IEM_MC_CALL_VOID_AIMPL_2 and IEM_MC_CALL_AIMPL_2. */
8865	DECL_INLINE_THROW(uint32_t)
8866	iemNativeEmitCallAImpl2(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarRc,
8867	uintptr_t pfnAImpl, uint8_t idxArg0, uint8_t idxArg1)
8868	{
8869	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg0, 0);
8870	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg1, 1);
8871	return iemNativeEmitCallAImplCommon(pReNative, off, idxVarRc, pfnAImpl, 2);
8872	}
8873
8874
8875	#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) \
8876	off = iemNativeEmitCallAImpl3(pReNative, off, UINT8_MAX /idxVarRc/, (uintptr_t)(a_pfn), a0, a1, a2)
8877
8878	#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) \
8879	off = iemNativeEmitCallAImpl3(pReNative, off, a_rc, (uintptr_t)(a_pfn), a0, a1, a2)
8880
8881	/** Emits code for IEM_MC_CALL_VOID_AIMPL_3 and IEM_MC_CALL_AIMPL_3. */
8882	DECL_INLINE_THROW(uint32_t)
8883	iemNativeEmitCallAImpl3(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarRc,
8884	uintptr_t pfnAImpl, uint8_t idxArg0, uint8_t idxArg1, uint8_t idxArg2)
8885	{
8886	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg0, 0);
8887	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg1, 1);
8888	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg2, 2);
8889	return iemNativeEmitCallAImplCommon(pReNative, off, idxVarRc, pfnAImpl, 3);
8890	}
8891
8892
8893	#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) \
8894	off = iemNativeEmitCallAImpl4(pReNative, off, UINT8_MAX /idxVarRc/, (uintptr_t)(a_pfn), a0, a1, a2, a3)
8895
8896	#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) \
8897	off = iemNativeEmitCallAImpl4(pReNative, off, a_rc, (uintptr_t)(a_pfn), a0, a1, a2, a3)
8898
8899	/** Emits code for IEM_MC_CALL_VOID_AIMPL_4 and IEM_MC_CALL_AIMPL_4. */
8900	DECL_INLINE_THROW(uint32_t)
8901	iemNativeEmitCallAImpl4(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarRc,
8902	uintptr_t pfnAImpl, uint8_t idxArg0, uint8_t idxArg1, uint8_t idxArg2, uint8_t idxArg3)
8903	{
8904	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg0, 0);
8905	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg1, 1);
8906	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg2, 2);
8907	IEMNATIVE_ASSERT_ARG_VAR_IDX(pReNative, idxArg3, 3);
8908	return iemNativeEmitCallAImplCommon(pReNative, off, idxVarRc, pfnAImpl, 4);
8909	}
8910
8911
8912
8913	/*********************************************************************************************************************************
8914	* Emitters for general purpose register fetches (IEM_MC_FETCH_GREG_XXX). *
8915	*********************************************************************************************************************************/
8916
8917	#define IEM_MC_FETCH_GREG_U8_THREADED(a_u8Dst, a_iGRegEx) \
8918	off = iemNativeEmitFetchGregU8(pReNative, off, a_u8Dst, a_iGRegEx, sizeof(uint8_t) /cbZeroExtended/)
8919
8920	#define IEM_MC_FETCH_GREG_U8_ZX_U16_THREADED(a_u16Dst, a_iGRegEx) \
8921	off = iemNativeEmitFetchGregU8(pReNative, off, a_u16Dst, a_iGRegEx, sizeof(uint16_t) /cbZeroExtended/)
8922
8923	#define IEM_MC_FETCH_GREG_U8_ZX_U32_THREADED(a_u32Dst, a_iGRegEx) \
8924	off = iemNativeEmitFetchGregU8(pReNative, off, a_u32Dst, a_iGRegEx, sizeof(uint32_t) /cbZeroExtended/)
8925
8926	#define IEM_MC_FETCH_GREG_U8_ZX_U64_THREADED(a_u64Dst, a_iGRegEx) \
8927	off = iemNativeEmitFetchGregU8(pReNative, off, a_u64Dst, a_iGRegEx, sizeof(uint64_t) /cbZeroExtended/)
8928
8929
8930	/** Emits code for IEM_MC_FETCH_GREG_U8_THREADED and
8931	* IEM_MC_FETCH_GREG_U8_ZX_U16/32/64_THREADED. */
8932	DECL_INLINE_THROW(uint32_t)
8933	iemNativeEmitFetchGregU8(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar, uint8_t iGRegEx, int8_t cbZeroExtended)
8934	{
8935	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar);
8936	Assert(pReNative->Core.aVars[idxDstVar].cbVar == cbZeroExtended); RT_NOREF(cbZeroExtended);
8937	Assert(iGRegEx < 20);
8938
8939	/* Same discussion as in iemNativeEmitFetchGregU16 */
8940	uint8_t const idxGstFullReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGRegEx & 15),
8941	kIemNativeGstRegUse_ReadOnly);
8942
8943	iemNativeVarSetKindToStack(pReNative, idxDstVar);
8944	uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off);
8945
8946	/* The value is zero-extended to the full 64-bit host register width. */
8947	if (iGRegEx < 16)
8948	off = iemNativeEmitLoadGprFromGpr8(pReNative, off, idxVarReg, idxGstFullReg);
8949	else
8950	off = iemNativeEmitLoadGprFromGpr8Hi(pReNative, off, idxVarReg, idxGstFullReg);
8951
8952	iemNativeVarRegisterRelease(pReNative, idxDstVar);
8953	iemNativeRegFreeTmp(pReNative, idxGstFullReg);
8954	return off;
8955	}
8956
8957
8958	#define IEM_MC_FETCH_GREG_U8_SX_U16_THREADED(a_u16Dst, a_iGRegEx) \
8959	off = iemNativeEmitFetchGregU8Sx(pReNative, off, a_u16Dst, a_iGRegEx, sizeof(uint16_t))
8960
8961	#define IEM_MC_FETCH_GREG_U8_SX_U32_THREADED(a_u32Dst, a_iGRegEx) \
8962	off = iemNativeEmitFetchGregU8Sx(pReNative, off, a_u32Dst, a_iGRegEx, sizeof(uint32_t))
8963
8964	#define IEM_MC_FETCH_GREG_U8_SX_U64_THREADED(a_u64Dst, a_iGRegEx) \
8965	off = iemNativeEmitFetchGregU8Sx(pReNative, off, a_u64Dst, a_iGRegEx, sizeof(uint64_t))
8966
8967	/** Emits code for IEM_MC_FETCH_GREG_U8_SX_U16/32/64_THREADED. */
8968	DECL_INLINE_THROW(uint32_t)
8969	iemNativeEmitFetchGregU8Sx(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar, uint8_t iGRegEx, uint8_t cbSignExtended)
8970	{
8971	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar);
8972	Assert(pReNative->Core.aVars[idxDstVar].cbVar == cbSignExtended);
8973	Assert(iGRegEx < 20);
8974
8975	/* Same discussion as in iemNativeEmitFetchGregU16 */
8976	uint8_t const idxGstFullReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGRegEx & 15),
8977	kIemNativeGstRegUse_ReadOnly);
8978
8979	iemNativeVarSetKindToStack(pReNative, idxDstVar);
8980	uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off);
8981
8982	if (iGRegEx < 16)
8983	{
8984	switch (cbSignExtended)
8985	{
8986	case sizeof(uint16_t):
8987	off = iemNativeEmitLoadGpr16SignExtendedFromGpr8(pReNative, off, idxVarReg, idxGstFullReg);
8988	break;
8989	case sizeof(uint32_t):
8990	off = iemNativeEmitLoadGpr32SignExtendedFromGpr8(pReNative, off, idxVarReg, idxGstFullReg);
8991	break;
8992	case sizeof(uint64_t):
8993	off = iemNativeEmitLoadGprSignExtendedFromGpr8(pReNative, off, idxVarReg, idxGstFullReg);
8994	break;
8995	default: AssertFailed(); break;
8996	}
8997	}
8998	else
8999	{
9000	off = iemNativeEmitLoadGprFromGpr8Hi(pReNative, off, idxVarReg, idxGstFullReg);
9001	switch (cbSignExtended)
9002	{
9003	case sizeof(uint16_t):
9004	off = iemNativeEmitLoadGpr16SignExtendedFromGpr8(pReNative, off, idxVarReg, idxVarReg);
9005	break;
9006	case sizeof(uint32_t):
9007	off = iemNativeEmitLoadGpr32SignExtendedFromGpr8(pReNative, off, idxVarReg, idxVarReg);
9008	break;
9009	case sizeof(uint64_t):
9010	off = iemNativeEmitLoadGprSignExtendedFromGpr8(pReNative, off, idxVarReg, idxVarReg);
9011	break;
9012	default: AssertFailed(); break;
9013	}
9014	}
9015
9016	iemNativeVarRegisterRelease(pReNative, idxDstVar);
9017	iemNativeRegFreeTmp(pReNative, idxGstFullReg);
9018	return off;
9019	}
9020
9021
9022
9023	#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) \
9024	off = iemNativeEmitFetchGregU16(pReNative, off, a_u16Dst, a_iGReg, sizeof(uint16_t))
9025
9026	#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u16Dst, a_iGReg) \
9027	off = iemNativeEmitFetchGregU16(pReNative, off, a_u16Dst, a_iGReg, sizeof(uint32_t))
9028
9029	#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u16Dst, a_iGReg) \
9030	off = iemNativeEmitFetchGregU16(pReNative, off, a_u16Dst, a_iGReg, sizeof(uint64_t))
9031
9032	/** Emits code for IEM_MC_FETCH_GREG_U16 and IEM_MC_FETCH_GREG_U16_ZX_U32/64. */
9033	DECL_INLINE_THROW(uint32_t)
9034	iemNativeEmitFetchGregU16(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar, uint8_t iGReg, uint8_t cbZeroExtended)
9035	{
9036	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar);
9037	Assert(pReNative->Core.aVars[idxDstVar].cbVar == cbZeroExtended); RT_NOREF(cbZeroExtended);
9038	Assert(iGReg < 16);
9039
9040	/*
9041	* We can either just load the low 16-bit of the GPR into a host register
9042	* for the variable, or we can do so via a shadow copy host register. The
9043	* latter will avoid having to reload it if it's being stored later, but
9044	* will waste a host register if it isn't touched again. Since we don't
9045	* know what going to happen, we choose the latter for now.
9046	*/
9047	uint8_t const idxGstFullReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9048	kIemNativeGstRegUse_ReadOnly);
9049
9050	iemNativeVarSetKindToStack(pReNative, idxDstVar);
9051	uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off);
9052	off = iemNativeEmitLoadGprFromGpr16(pReNative, off, idxVarReg, idxGstFullReg);
9053	iemNativeVarRegisterRelease(pReNative, idxDstVar);
9054
9055	iemNativeRegFreeTmp(pReNative, idxGstFullReg);
9056	return off;
9057	}
9058
9059
9060	#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u16Dst, a_iGReg) \
9061	off = iemNativeEmitFetchGregU16Sx(pReNative, off, a_u16Dst, a_iGReg, sizeof(uint32_t))
9062
9063	#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u16Dst, a_iGReg) \
9064	off = iemNativeEmitFetchGregU16Sx(pReNative, off, a_u16Dst, a_iGReg, sizeof(uint64_t))
9065
9066	/** Emits code for IEM_MC_FETCH_GREG_U16_SX_U32/64. */
9067	DECL_INLINE_THROW(uint32_t)
9068	iemNativeEmitFetchGregU16Sx(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar, uint8_t iGReg, uint8_t cbSignExtended)
9069	{
9070	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar);
9071	Assert(pReNative->Core.aVars[idxDstVar].cbVar == cbSignExtended);
9072	Assert(iGReg < 16);
9073
9074	/*
9075	* We can either just load the low 16-bit of the GPR into a host register
9076	* for the variable, or we can do so via a shadow copy host register. The
9077	* latter will avoid having to reload it if it's being stored later, but
9078	* will waste a host register if it isn't touched again. Since we don't
9079	* know what going to happen, we choose the latter for now.
9080	*/
9081	uint8_t const idxGstFullReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9082	kIemNativeGstRegUse_ReadOnly);
9083
9084	iemNativeVarSetKindToStack(pReNative, idxDstVar);
9085	uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off);
9086	if (cbSignExtended == sizeof(uint32_t))
9087	off = iemNativeEmitLoadGpr32SignExtendedFromGpr16(pReNative, off, idxVarReg, idxGstFullReg);
9088	else
9089	{
9090	Assert(cbSignExtended == sizeof(uint64_t));
9091	off = iemNativeEmitLoadGprSignExtendedFromGpr16(pReNative, off, idxVarReg, idxGstFullReg);
9092	}
9093	iemNativeVarRegisterRelease(pReNative, idxDstVar);
9094
9095	iemNativeRegFreeTmp(pReNative, idxGstFullReg);
9096	return off;
9097	}
9098
9099
9100	#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) \
9101	off = iemNativeEmitFetchGregU32(pReNative, off, a_u32Dst, a_iGReg, sizeof(uint32_t))
9102
9103	#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u32Dst, a_iGReg) \
9104	off = iemNativeEmitFetchGregU32(pReNative, off, a_u32Dst, a_iGReg, sizeof(uint64_t))
9105
9106	/** Emits code for IEM_MC_FETCH_GREG_U32. */
9107	DECL_INLINE_THROW(uint32_t)
9108	iemNativeEmitFetchGregU32(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar, uint8_t iGReg, uint8_t cbZeroExtended)
9109	{
9110	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar);
9111	Assert(pReNative->Core.aVars[idxDstVar].cbVar == cbZeroExtended); RT_NOREF_PV(cbZeroExtended);
9112	Assert(iGReg < 16);
9113
9114	/*
9115	* We can either just load the low 16-bit of the GPR into a host register
9116	* for the variable, or we can do so via a shadow copy host register. The
9117	* latter will avoid having to reload it if it's being stored later, but
9118	* will waste a host register if it isn't touched again. Since we don't
9119	* know what going to happen, we choose the latter for now.
9120	*/
9121	uint8_t const idxGstFullReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9122	kIemNativeGstRegUse_ReadOnly);
9123
9124	iemNativeVarSetKindToStack(pReNative, idxDstVar);
9125	uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off);
9126	off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxVarReg, idxGstFullReg);
9127	iemNativeVarRegisterRelease(pReNative, idxDstVar);
9128
9129	iemNativeRegFreeTmp(pReNative, idxGstFullReg);
9130	return off;
9131	}
9132
9133
9134	#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u32Dst, a_iGReg) \
9135	off = iemNativeEmitFetchGregU32SxU64(pReNative, off, a_u32Dst, a_iGReg)
9136
9137	/** Emits code for IEM_MC_FETCH_GREG_U32. */
9138	DECL_INLINE_THROW(uint32_t)
9139	iemNativeEmitFetchGregU32SxU64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar, uint8_t iGReg)
9140	{
9141	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar);
9142	Assert(pReNative->Core.aVars[idxDstVar].cbVar == sizeof(uint64_t));
9143	Assert(iGReg < 16);
9144
9145	/*
9146	* We can either just load the low 32-bit of the GPR into a host register
9147	* for the variable, or we can do so via a shadow copy host register. The
9148	* latter will avoid having to reload it if it's being stored later, but
9149	* will waste a host register if it isn't touched again. Since we don't
9150	* know what going to happen, we choose the latter for now.
9151	*/
9152	uint8_t const idxGstFullReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9153	kIemNativeGstRegUse_ReadOnly);
9154
9155	iemNativeVarSetKindToStack(pReNative, idxDstVar);
9156	uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off);
9157	off = iemNativeEmitLoadGprSignExtendedFromGpr32(pReNative, off, idxVarReg, idxGstFullReg);
9158	iemNativeVarRegisterRelease(pReNative, idxDstVar);
9159
9160	iemNativeRegFreeTmp(pReNative, idxGstFullReg);
9161	return off;
9162	}
9163
9164
9165	#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) \
9166	off = iemNativeEmitFetchGregU64(pReNative, off, a_u64Dst, a_iGReg)
9167
9168	#define IEM_MC_FETCH_GREG_U64_ZX_U64(a_u64Dst, a_iGReg) \
9169	off = iemNativeEmitFetchGregU64(pReNative, off, a_u64Dst, a_iGReg)
9170
9171	/** Emits code for IEM_MC_FETCH_GREG_U64 (and the
9172	* IEM_MC_FETCH_GREG_U64_ZX_U64 alias). */
9173	DECL_INLINE_THROW(uint32_t)
9174	iemNativeEmitFetchGregU64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar, uint8_t iGReg)
9175	{
9176	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar);
9177	Assert(pReNative->Core.aVars[idxDstVar].cbVar == sizeof(uint64_t));
9178	Assert(iGReg < 16);
9179
9180	uint8_t const idxGstFullReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9181	kIemNativeGstRegUse_ReadOnly);
9182
9183	iemNativeVarSetKindToStack(pReNative, idxDstVar);
9184	uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off);
9185	off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxVarReg, idxGstFullReg);
9186	/** @todo name the register a shadow one already? */
9187	iemNativeVarRegisterRelease(pReNative, idxDstVar);
9188
9189	iemNativeRegFreeTmp(pReNative, idxGstFullReg);
9190	return off;
9191	}
9192
9193
9194
9195	/*********************************************************************************************************************************
9196	* Emitters for general purpose register stores (IEM_MC_STORE_GREG_XXX). *
9197	*********************************************************************************************************************************/
9198
9199	#define IEM_MC_STORE_GREG_U8_CONST_THREADED(a_iGRegEx, a_u8Value) \
9200	off = iemNativeEmitStoreGregU8Const(pReNative, off, a_iGRegEx, a_u8Value)
9201
9202	/** Emits code for IEM_MC_STORE_GREG_U8_CONST_THREADED. */
9203	DECL_INLINE_THROW(uint32_t)
9204	iemNativeEmitStoreGregU8Const(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGRegEx, uint8_t u8Value)
9205	{
9206	Assert(iGRegEx < 20);
9207	uint8_t const idxGstTmpReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGRegEx & 15),
9208	kIemNativeGstRegUse_ForUpdate);
9209	#ifdef RT_ARCH_AMD64
9210	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 12);
9211
9212	/* To the lowest byte of the register: mov r8, imm8 */
9213	if (iGRegEx < 16)
9214	{
9215	if (idxGstTmpReg >= 8)
9216	pbCodeBuf[off++] = X86_OP_REX_B;
9217	else if (idxGstTmpReg >= 4)
9218	pbCodeBuf[off++] = X86_OP_REX;
9219	pbCodeBuf[off++] = 0xb0 + (idxGstTmpReg & 7);
9220	pbCodeBuf[off++] = u8Value;
9221	}
9222	/* Otherwise it's to ah, ch, dh or bh: use mov r8, imm8 if we can, otherwise, we rotate. */
9223	else if (idxGstTmpReg < 4)
9224	{
9225	pbCodeBuf[off++] = 0xb4 + idxGstTmpReg;
9226	pbCodeBuf[off++] = u8Value;
9227	}
9228	else
9229	{
9230	/* ror reg64, 8 */
9231	pbCodeBuf[off++] = X86_OP_REX_W \| (idxGstTmpReg < 8 ? 0 : X86_OP_REX_B);
9232	pbCodeBuf[off++] = 0xc1;
9233	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 1, idxGstTmpReg & 7);
9234	pbCodeBuf[off++] = 8;
9235
9236	/* mov reg8, imm8 */
9237	if (idxGstTmpReg >= 8)
9238	pbCodeBuf[off++] = X86_OP_REX_B;
9239	else if (idxGstTmpReg >= 4)
9240	pbCodeBuf[off++] = X86_OP_REX;
9241	pbCodeBuf[off++] = 0xb0 + (idxGstTmpReg & 7);
9242	pbCodeBuf[off++] = u8Value;
9243
9244	/* rol reg64, 8 */
9245	pbCodeBuf[off++] = X86_OP_REX_W \| (idxGstTmpReg < 8 ? 0 : X86_OP_REX_B);
9246	pbCodeBuf[off++] = 0xc1;
9247	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxGstTmpReg & 7);
9248	pbCodeBuf[off++] = 8;
9249	}
9250
9251	#elif defined(RT_ARCH_ARM64)
9252	uint8_t const idxImmReg = iemNativeRegAllocTmpImm(pReNative, &off, u8Value);
9253	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
9254	if (iGRegEx < 16)
9255	/* bfi w1, w2, 0, 8 - moves bits 7:0 from idxImmReg to idxGstTmpReg bits 7:0. */
9256	pu32CodeBuf[off++] = Armv8A64MkInstrBfi(idxGstTmpReg, idxImmReg, 0, 8);
9257	else
9258	/* bfi w1, w2, 8, 8 - moves bits 7:0 from idxImmReg to idxGstTmpReg bits 15:8. */
9259	pu32CodeBuf[off++] = Armv8A64MkInstrBfi(idxGstTmpReg, idxImmReg, 8, 8);
9260	iemNativeRegFreeTmp(pReNative, idxImmReg);
9261
9262	#else
9263	# error "Port me!"
9264	#endif
9265
9266	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
9267
9268	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxGstTmpReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[iGRegEx & 15]));
9269
9270	iemNativeRegFreeTmp(pReNative, idxGstTmpReg);
9271	return off;
9272	}
9273
9274
9275	#define IEM_MC_STORE_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
9276	off = iemNativeEmitStoreGregU8(pReNative, off, a_iGRegEx, a_u8Value)
9277
9278	/** Emits code for IEM_MC_STORE_GREG_U8_THREADED. */
9279	DECL_INLINE_THROW(uint32_t)
9280	iemNativeEmitStoreGregU8(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGRegEx, uint8_t idxValueVar)
9281	{
9282	Assert(iGRegEx < 20);
9283	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxValueVar);
9284
9285	/*
9286	* If it's a constant value (unlikely) we treat this as a
9287	* IEM_MC_STORE_GREG_U8_CONST statement.
9288	*/
9289	if (pReNative->Core.aVars[idxValueVar].enmKind == kIemNativeVarKind_Stack)
9290	{ /* likely */ }
9291	else
9292	{
9293	AssertStmt(pReNative->Core.aVars[idxValueVar].enmKind == kIemNativeVarKind_Immediate,
9294	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_UNEXPECTED_KIND));
9295	return iemNativeEmitStoreGregU8Const(pReNative, off, iGRegEx, (uint8_t)pReNative->Core.aVars[idxValueVar].u.uValue);
9296	}
9297
9298	uint8_t const idxGstTmpReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGRegEx & 15),
9299	kIemNativeGstRegUse_ForUpdate);
9300	uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxValueVar, &off, true /fInitialized/);
9301
9302	#ifdef RT_ARCH_AMD64
9303	/* To the lowest byte of the register: mov reg8, reg8(r/m) */
9304	if (iGRegEx < 16)
9305	{
9306	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
9307	if (idxGstTmpReg >= 8 \|\| idxVarReg >= 8)
9308	pbCodeBuf[off++] = (idxGstTmpReg >= 8 ? X86_OP_REX_R : 0) \| (idxVarReg >= 8 ? X86_OP_REX_B : 0);
9309	else if (idxGstTmpReg >= 4 \|\| idxVarReg >= 4)
9310	pbCodeBuf[off++] = X86_OP_REX;
9311	pbCodeBuf[off++] = 0x8a;
9312	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxGstTmpReg & 7, idxVarReg & 7);
9313	}
9314	/* Otherwise it's to ah, ch, dh or bh from al, cl, dl or bl: use mov r8, r8 if we can, otherwise, we rotate. */
9315	else if (idxGstTmpReg < 4 && idxVarReg < 4)
9316	{
9317	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2+1);
9318	pbCodeBuf[off++] = 0x8a;
9319	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxGstTmpReg + 4, idxVarReg);
9320	}
9321	else
9322	{
9323	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 15);
9324
9325	/* ror reg64, 8 */
9326	pbCodeBuf[off++] = X86_OP_REX_W \| (idxGstTmpReg < 8 ? 0 : X86_OP_REX_B);
9327	pbCodeBuf[off++] = 0xc1;
9328	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 1, idxGstTmpReg & 7);
9329	pbCodeBuf[off++] = 8;
9330
9331	/* mov reg8, reg8(r/m) */
9332	if (idxGstTmpReg >= 8 \|\| idxVarReg >= 8)
9333	pbCodeBuf[off++] = (idxGstTmpReg >= 8 ? X86_OP_REX_R : 0) \| (idxVarReg >= 8 ? X86_OP_REX_B : 0);
9334	else if (idxGstTmpReg >= 4 \|\| idxVarReg >= 4)
9335	pbCodeBuf[off++] = X86_OP_REX;
9336	pbCodeBuf[off++] = 0x8a;
9337	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxGstTmpReg & 7, idxVarReg & 7);
9338
9339	/* rol reg64, 8 */
9340	pbCodeBuf[off++] = X86_OP_REX_W \| (idxGstTmpReg < 8 ? 0 : X86_OP_REX_B);
9341	pbCodeBuf[off++] = 0xc1;
9342	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxGstTmpReg & 7);
9343	pbCodeBuf[off++] = 8;
9344	}
9345
9346	#elif defined(RT_ARCH_ARM64)
9347	/* bfi w1, w2, 0, 8 - moves bits 7:0 from idxVarReg to idxGstTmpReg bits 7:0.
9348	or
9349	bfi w1, w2, 8, 8 - moves bits 7:0 from idxVarReg to idxGstTmpReg bits 15:8. */
9350	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
9351	if (iGRegEx < 16)
9352	pu32CodeBuf[off++] = Armv8A64MkInstrBfi(idxGstTmpReg, idxVarReg, 0, 8);
9353	else
9354	pu32CodeBuf[off++] = Armv8A64MkInstrBfi(idxGstTmpReg, idxVarReg, 8, 8);
9355
9356	#else
9357	# error "Port me!"
9358	#endif
9359	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
9360
9361	iemNativeVarRegisterRelease(pReNative, idxValueVar);
9362
9363	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxGstTmpReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[iGRegEx & 15]));
9364	iemNativeRegFreeTmp(pReNative, idxGstTmpReg);
9365	return off;
9366	}
9367
9368
9369
9370	#define IEM_MC_STORE_GREG_U16_CONST(a_iGReg, a_u16Const) \
9371	off = iemNativeEmitStoreGregU16Const(pReNative, off, a_iGReg, a_u16Const)
9372
9373	/** Emits code for IEM_MC_STORE_GREG_U16. */
9374	DECL_INLINE_THROW(uint32_t)
9375	iemNativeEmitStoreGregU16Const(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGReg, uint16_t uValue)
9376	{
9377	Assert(iGReg < 16);
9378	uint8_t const idxGstTmpReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9379	kIemNativeGstRegUse_ForUpdate);
9380	#ifdef RT_ARCH_AMD64
9381	/* mov reg16, imm16 */
9382	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 5);
9383	pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
9384	if (idxGstTmpReg >= 8)
9385	pbCodeBuf[off++] = X86_OP_REX_B;
9386	pbCodeBuf[off++] = 0xb8 + (idxGstTmpReg & 7);
9387	pbCodeBuf[off++] = RT_BYTE1(uValue);
9388	pbCodeBuf[off++] = RT_BYTE2(uValue);
9389
9390	#elif defined(RT_ARCH_ARM64)
9391	/* movk xdst, #uValue, lsl #0 */
9392	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
9393	pu32CodeBuf[off++] = Armv8A64MkInstrMovK(idxGstTmpReg, uValue);
9394
9395	#else
9396	# error "Port me!"
9397	#endif
9398
9399	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
9400
9401	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxGstTmpReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[iGReg]));
9402	iemNativeRegFreeTmp(pReNative, idxGstTmpReg);
9403	return off;
9404	}
9405
9406
9407	#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) \
9408	off = iemNativeEmitStoreGregU16(pReNative, off, a_iGReg, a_u16Value)
9409
9410	/** Emits code for IEM_MC_STORE_GREG_U16. */
9411	DECL_INLINE_THROW(uint32_t)
9412	iemNativeEmitStoreGregU16(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGReg, uint8_t idxValueVar)
9413	{
9414	Assert(iGReg < 16);
9415	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxValueVar);
9416
9417	/*
9418	* If it's a constant value (unlikely) we treat this as a
9419	* IEM_MC_STORE_GREG_U16_CONST statement.
9420	*/
9421	if (pReNative->Core.aVars[idxValueVar].enmKind == kIemNativeVarKind_Stack)
9422	{ /* likely */ }
9423	else
9424	{
9425	AssertStmt(pReNative->Core.aVars[idxValueVar].enmKind == kIemNativeVarKind_Immediate,
9426	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_UNEXPECTED_KIND));
9427	return iemNativeEmitStoreGregU16Const(pReNative, off, iGReg, (uint16_t)pReNative->Core.aVars[idxValueVar].u.uValue);
9428	}
9429
9430	uint8_t const idxGstTmpReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9431	kIemNativeGstRegUse_ForUpdate);
9432
9433	#ifdef RT_ARCH_AMD64
9434	/* mov reg16, reg16 or [mem16] */
9435	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 12);
9436	pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
9437	if (pReNative->Core.aVars[idxValueVar].idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs))
9438	{
9439	if (idxGstTmpReg >= 8 \|\| pReNative->Core.aVars[idxValueVar].idxReg >= 8)
9440	pbCodeBuf[off++] = (idxGstTmpReg >= 8 ? X86_OP_REX_R : 0)
9441	\| (pReNative->Core.aVars[idxValueVar].idxReg >= 8 ? X86_OP_REX_B : 0);
9442	pbCodeBuf[off++] = 0x8b;
9443	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxGstTmpReg & 7, pReNative->Core.aVars[idxValueVar].idxReg & 7);
9444	}
9445	else
9446	{
9447	uint8_t const idxStackSlot = pReNative->Core.aVars[idxValueVar].idxStackSlot;
9448	AssertStmt(idxStackSlot != UINT8_MAX, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_NOT_INITIALIZED));
9449	if (idxGstTmpReg >= 8)
9450	pbCodeBuf[off++] = X86_OP_REX_R;
9451	pbCodeBuf[off++] = 0x8b;
9452	off = iemNativeEmitGprByBpDisp(pbCodeBuf, off, idxGstTmpReg, iemNativeStackCalcBpDisp(idxStackSlot), pReNative);
9453	}
9454
9455	#elif defined(RT_ARCH_ARM64)
9456	/* bfi w1, w2, 0, 16 - moves bits 15:0 from idxVarReg to idxGstTmpReg bits 15:0. */
9457	uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxValueVar, &off, true /fInitialized/);
9458	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
9459	pu32CodeBuf[off++] = Armv8A64MkInstrBfi(idxGstTmpReg, idxVarReg, 0, 16);
9460	iemNativeVarRegisterRelease(pReNative, idxValueVar);
9461
9462	#else
9463	# error "Port me!"
9464	#endif
9465
9466	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
9467
9468	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxGstTmpReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[iGReg]));
9469	iemNativeRegFreeTmp(pReNative, idxGstTmpReg);
9470	return off;
9471	}
9472
9473
9474	#define IEM_MC_STORE_GREG_U32_CONST(a_iGReg, a_u32Const) \
9475	off = iemNativeEmitStoreGregU32Const(pReNative, off, a_iGReg, a_u32Const)
9476
9477	/** Emits code for IEM_MC_STORE_GREG_U32_CONST. */
9478	DECL_INLINE_THROW(uint32_t)
9479	iemNativeEmitStoreGregU32Const(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGReg, uint32_t uValue)
9480	{
9481	Assert(iGReg < 16);
9482	uint8_t const idxGstTmpReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9483	kIemNativeGstRegUse_ForFullWrite);
9484	off = iemNativeEmitLoadGprImm64(pReNative, off, idxGstTmpReg, uValue);
9485	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxGstTmpReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[iGReg]));
9486	iemNativeRegFreeTmp(pReNative, idxGstTmpReg);
9487	return off;
9488	}
9489
9490
9491	#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) \
9492	off = iemNativeEmitStoreGregU32(pReNative, off, a_iGReg, a_u32Value)
9493
9494	/** Emits code for IEM_MC_STORE_GREG_U32. */
9495	DECL_INLINE_THROW(uint32_t)
9496	iemNativeEmitStoreGregU32(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGReg, uint8_t idxValueVar)
9497	{
9498	Assert(iGReg < 16);
9499	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxValueVar);
9500
9501	/*
9502	* If it's a constant value (unlikely) we treat this as a
9503	* IEM_MC_STORE_GREG_U32_CONST statement.
9504	*/
9505	if (pReNative->Core.aVars[idxValueVar].enmKind == kIemNativeVarKind_Stack)
9506	{ /* likely */ }
9507	else
9508	{
9509	AssertStmt(pReNative->Core.aVars[idxValueVar].enmKind == kIemNativeVarKind_Immediate,
9510	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_UNEXPECTED_KIND));
9511	return iemNativeEmitStoreGregU32Const(pReNative, off, iGReg, (uint32_t)pReNative->Core.aVars[idxValueVar].u.uValue);
9512	}
9513
9514	/*
9515	* For the rest we allocate a guest register for the variable and writes
9516	* it to the CPUMCTX structure.
9517	*/
9518	uint8_t const idxVarReg = iemNativeVarRegisterAcquireForGuestReg(pReNative, idxValueVar, IEMNATIVEGSTREG_GPR(iGReg), &off);
9519	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxVarReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[iGReg]));
9520	#ifdef VBOX_STRICT
9521	off = iemNativeEmitTop32BitsClearCheck(pReNative, off, idxVarReg);
9522	#endif
9523	iemNativeVarRegisterRelease(pReNative, idxValueVar);
9524	return off;
9525	}
9526
9527
9528	#define IEM_MC_STORE_GREG_U64_CONST(a_iGReg, a_u64Const) \
9529	off = iemNativeEmitStoreGregU64Const(pReNative, off, a_iGReg, a_u64Const)
9530
9531	/** Emits code for IEM_MC_STORE_GREG_U64_CONST. */
9532	DECL_INLINE_THROW(uint32_t)
9533	iemNativeEmitStoreGregU64Const(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGReg, uint64_t uValue)
9534	{
9535	Assert(iGReg < 16);
9536	uint8_t const idxGstTmpReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9537	kIemNativeGstRegUse_ForFullWrite);
9538	off = iemNativeEmitLoadGprImm64(pReNative, off, idxGstTmpReg, uValue);
9539	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxGstTmpReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[iGReg]));
9540	iemNativeRegFreeTmp(pReNative, idxGstTmpReg);
9541	return off;
9542	}
9543
9544
9545	#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) \
9546	off = iemNativeEmitStoreGregU64(pReNative, off, a_iGReg, a_u64Value)
9547
9548	/** Emits code for IEM_MC_STORE_GREG_U64. */
9549	DECL_INLINE_THROW(uint32_t)
9550	iemNativeEmitStoreGregU64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGReg, uint8_t idxValueVar)
9551	{
9552	Assert(iGReg < 16);
9553	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxValueVar);
9554
9555	/*
9556	* If it's a constant value (unlikely) we treat this as a
9557	* IEM_MC_STORE_GREG_U64_CONST statement.
9558	*/
9559	if (pReNative->Core.aVars[idxValueVar].enmKind == kIemNativeVarKind_Stack)
9560	{ /* likely */ }
9561	else
9562	{
9563	AssertStmt(pReNative->Core.aVars[idxValueVar].enmKind == kIemNativeVarKind_Immediate,
9564	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_UNEXPECTED_KIND));
9565	return iemNativeEmitStoreGregU64Const(pReNative, off, iGReg, pReNative->Core.aVars[idxValueVar].u.uValue);
9566	}
9567
9568	/*
9569	* For the rest we allocate a guest register for the variable and writes
9570	* it to the CPUMCTX structure.
9571	*/
9572	uint8_t const idxVarReg = iemNativeVarRegisterAcquireForGuestReg(pReNative, idxValueVar, IEMNATIVEGSTREG_GPR(iGReg), &off);
9573	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxVarReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[iGReg]));
9574	iemNativeVarRegisterRelease(pReNative, idxValueVar);
9575	return off;
9576	}
9577
9578
9579	#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) \
9580	off = iemNativeEmitClearHighGregU64(pReNative, off, a_iGReg)
9581
9582	/** Emits code for IEM_MC_CLEAR_HIGH_GREG_U64. */
9583	DECL_INLINE_THROW(uint32_t)
9584	iemNativeEmitClearHighGregU64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGReg)
9585	{
9586	Assert(iGReg < 16);
9587	uint8_t const idxGstTmpReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9588	kIemNativeGstRegUse_ForUpdate);
9589	off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxGstTmpReg, idxGstTmpReg);
9590	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxGstTmpReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[iGReg]));
9591	iemNativeRegFreeTmp(pReNative, idxGstTmpReg);
9592	return off;
9593	}
9594
9595
9596	/*********************************************************************************************************************************
9597	* General purpose register manipulation (add, sub). *
9598	*********************************************************************************************************************************/
9599
9600	#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u8SubtrahendConst) \
9601	off = iemNativeEmitAddGregU16(pReNative, off, a_iGReg, a_u8SubtrahendConst)
9602
9603	/** Emits code for IEM_MC_ADD_GREG_U16. */
9604	DECL_INLINE_THROW(uint32_t)
9605	iemNativeEmitAddGregU16(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGReg, uint8_t uAddend)
9606	{
9607	uint8_t const idxGstTmpReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9608	kIemNativeGstRegUse_ForUpdate);
9609
9610	#ifdef RT_ARCH_AMD64
9611	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6);
9612	pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
9613	if (idxGstTmpReg >= 8)
9614	pbCodeBuf[off++] = X86_OP_REX_B;
9615	if (uAddend == 1)
9616	{
9617	pbCodeBuf[off++] = 0xff; /* inc */
9618	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxGstTmpReg & 7);
9619	}
9620	else
9621	{
9622	pbCodeBuf[off++] = 0x81;
9623	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxGstTmpReg & 7);
9624	pbCodeBuf[off++] = uAddend;
9625	pbCodeBuf[off++] = 0;
9626	}
9627
9628	#else
9629	uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
9630	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
9631
9632	/* sub tmp, gstgrp, uAddend */
9633	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(false /fSub/, idxTmpReg, idxGstTmpReg, uAddend, false /f64Bit/);
9634
9635	/* bfi w1, w2, 0, 16 - moves bits 15:0 from tmpreg2 to tmpreg. */
9636	pu32CodeBuf[off++] = Armv8A64MkInstrBfi(idxGstTmpReg, idxTmpReg, 0, 16);
9637
9638	iemNativeRegFreeTmp(pReNative, idxTmpReg);
9639	#endif
9640
9641	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
9642
9643	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxGstTmpReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[iGReg]));
9644
9645	iemNativeRegFreeTmp(pReNative, idxGstTmpReg);
9646	return off;
9647	}
9648
9649
9650	#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u8Const) \
9651	off = iemNativeEmitAddGregU32U64(pReNative, off, a_iGReg, a_u8Const, false /f64Bit/)
9652
9653	#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u8Const) \
9654	off = iemNativeEmitAddGregU32U64(pReNative, off, a_iGReg, a_u8Const, true /f64Bit/)
9655
9656	/** Emits code for IEM_MC_ADD_GREG_U32 and IEM_MC_ADD_GREG_U64. */
9657	DECL_INLINE_THROW(uint32_t)
9658	iemNativeEmitAddGregU32U64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGReg, uint8_t uAddend, bool f64Bit)
9659	{
9660	uint8_t const idxGstTmpReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9661	kIemNativeGstRegUse_ForUpdate);
9662
9663	#ifdef RT_ARCH_AMD64
9664	uint8_t *pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 7);
9665	if (f64Bit)
9666	pbCodeBuf[off++] = X86_OP_REX_W \| (idxGstTmpReg >= 8 ? X86_OP_REX_B : 0);
9667	else if (idxGstTmpReg >= 8)
9668	pbCodeBuf[off++] = X86_OP_REX_B;
9669	if (uAddend == 1)
9670	{
9671	pbCodeBuf[off++] = 0xff; /* inc */
9672	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxGstTmpReg & 7);
9673	}
9674	else if (uAddend < 128)
9675	{
9676	pbCodeBuf[off++] = 0x83; /* add */
9677	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxGstTmpReg & 7);
9678	pbCodeBuf[off++] = RT_BYTE1(uAddend);
9679	}
9680	else
9681	{
9682	pbCodeBuf[off++] = 0x81; /* add */
9683	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, idxGstTmpReg & 7);
9684	pbCodeBuf[off++] = RT_BYTE1(uAddend);
9685	pbCodeBuf[off++] = 0;
9686	pbCodeBuf[off++] = 0;
9687	pbCodeBuf[off++] = 0;
9688	}
9689
9690	#else
9691	/* sub tmp, gstgrp, uAddend */
9692	uint32_t *pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
9693	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(false /fSub/, idxGstTmpReg, idxGstTmpReg, uAddend, f64Bit);
9694
9695	#endif
9696
9697	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
9698
9699	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxGstTmpReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[iGReg]));
9700
9701	iemNativeRegFreeTmp(pReNative, idxGstTmpReg);
9702	return off;
9703	}
9704
9705
9706
9707	#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u8SubtrahendConst) \
9708	off = iemNativeEmitSubGregU16(pReNative, off, a_iGReg, a_u8SubtrahendConst)
9709
9710	/** Emits code for IEM_MC_SUB_GREG_U16. */
9711	DECL_INLINE_THROW(uint32_t)
9712	iemNativeEmitSubGregU16(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGReg, uint8_t uSubtrahend)
9713	{
9714	uint8_t const idxGstTmpReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9715	kIemNativeGstRegUse_ForUpdate);
9716
9717	#ifdef RT_ARCH_AMD64
9718	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6);
9719	pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
9720	if (idxGstTmpReg >= 8)
9721	pbCodeBuf[off++] = X86_OP_REX_B;
9722	if (uSubtrahend == 1)
9723	{
9724	pbCodeBuf[off++] = 0xff; /* dec */
9725	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 1, idxGstTmpReg & 7);
9726	}
9727	else
9728	{
9729	pbCodeBuf[off++] = 0x81;
9730	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 5, idxGstTmpReg & 7);
9731	pbCodeBuf[off++] = uSubtrahend;
9732	pbCodeBuf[off++] = 0;
9733	}
9734
9735	#else
9736	uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
9737	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
9738
9739	/* sub tmp, gstgrp, uSubtrahend */
9740	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(true /fSub/, idxTmpReg, idxGstTmpReg, uSubtrahend, false /f64Bit/);
9741
9742	/* bfi w1, w2, 0, 16 - moves bits 15:0 from tmpreg2 to tmpreg. */
9743	pu32CodeBuf[off++] = Armv8A64MkInstrBfi(idxGstTmpReg, idxTmpReg, 0, 16);
9744
9745	iemNativeRegFreeTmp(pReNative, idxTmpReg);
9746	#endif
9747
9748	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
9749
9750	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxGstTmpReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[iGReg]));
9751
9752	iemNativeRegFreeTmp(pReNative, idxGstTmpReg);
9753	return off;
9754	}
9755
9756
9757	#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u8Const) \
9758	off = iemNativeEmitSubGregU32U64(pReNative, off, a_iGReg, a_u8Const, false /f64Bit/)
9759
9760	#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u8Const) \
9761	off = iemNativeEmitSubGregU32U64(pReNative, off, a_iGReg, a_u8Const, true /f64Bit/)
9762
9763	/** Emits code for IEM_MC_SUB_GREG_U32 and IEM_MC_SUB_GREG_U64. */
9764	DECL_INLINE_THROW(uint32_t)
9765	iemNativeEmitSubGregU32U64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGReg, uint8_t uSubtrahend, bool f64Bit)
9766	{
9767	uint8_t const idxGstTmpReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(iGReg),
9768	kIemNativeGstRegUse_ForUpdate);
9769
9770	#ifdef RT_ARCH_AMD64
9771	uint8_t *pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 7);
9772	if (f64Bit)
9773	pbCodeBuf[off++] = X86_OP_REX_W \| (idxGstTmpReg >= 8 ? X86_OP_REX_B : 0);
9774	else if (idxGstTmpReg >= 8)
9775	pbCodeBuf[off++] = X86_OP_REX_B;
9776	if (uSubtrahend == 1)
9777	{
9778	pbCodeBuf[off++] = 0xff; /* dec */
9779	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 1, idxGstTmpReg & 7);
9780	}
9781	else if (uSubtrahend < 128)
9782	{
9783	pbCodeBuf[off++] = 0x83; /* sub */
9784	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 5, idxGstTmpReg & 7);
9785	pbCodeBuf[off++] = RT_BYTE1(uSubtrahend);
9786	}
9787	else
9788	{
9789	pbCodeBuf[off++] = 0x81; /* sub */
9790	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 5, idxGstTmpReg & 7);
9791	pbCodeBuf[off++] = RT_BYTE1(uSubtrahend);
9792	pbCodeBuf[off++] = 0;
9793	pbCodeBuf[off++] = 0;
9794	pbCodeBuf[off++] = 0;
9795	}
9796
9797	#else
9798	/* sub tmp, gstgrp, uSubtrahend */
9799	uint32_t *pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
9800	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(true /fSub/, idxGstTmpReg, idxGstTmpReg, uSubtrahend, f64Bit);
9801
9802	#endif
9803
9804	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
9805
9806	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxGstTmpReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[iGReg]));
9807
9808	iemNativeRegFreeTmp(pReNative, idxGstTmpReg);
9809	return off;
9810	}
9811
9812
9813
9814	/*********************************************************************************************************************************
9815	* EFLAGS *
9816	*********************************************************************************************************************************/
9817
9818	#if !defined(VBOX_WITH_STATISTICS) \|\| !defined(IEMNATIVE_WITH_LIVENESS_ANALYSIS)
9819	# define IEMNATIVE_EFLAGS_OPTIMIZATION_STATS(a_fEflInput, a_fEflOutput) ((void)0)
9820	#else
9821	# define IEMNATIVE_EFLAGS_OPTIMIZATION_STATS(a_fEflInput, a_fEflOutput) \
9822	iemNativeEFlagsOptimizationStats(pReNative, a_fEflInput, a_fEflOutput)
9823
9824	DECLINLINE(void) iemNativeEFlagsOptimizationStats(PIEMRECOMPILERSTATE pReNative, uint32_t fEflInput, uint32_t fEflOutput)
9825	{
9826	if (fEflOutput)
9827	{
9828	PVMCPUCC const pVCpu = pReNative->pVCpu;
9829	# ifndef IEMLIVENESS_EXTENDED_LAYOUT
9830	IEMLIVENESSBIT const LivenessBit0 = pReNative->paLivenessEntries[pReNative->idxCurCall].Bit0;
9831	IEMLIVENESSBIT const LivenessBit1 = pReNative->paLivenessEntries[pReNative->idxCurCall].Bit1;
9832	AssertCompile(IEMLIVENESS_STATE_CLOBBERED == 0);
9833	# define CHECK_FLAG_AND_UPDATE_STATS(a_fEfl, a_fLivenessMember, a_CoreStatName) \
9834	if (fEflOutput & (a_fEfl)) \
9835	{ \
9836	if (LivenessBit0.a_fLivenessMember \| LivenessBit1.a_fLivenessMember) \
9837	STAM_COUNTER_INC(&pVCpu->iem.s.a_CoreStatName ## Required); \
9838	else \
9839	STAM_COUNTER_INC(&pVCpu->iem.s.a_CoreStatName ## Skippable); \
9840	} else do { } while (0)
9841	# else
9842	PCIEMLIVENESSENTRY const pLivenessEntry = &pReNative->paLivenessEntries[pReNative->idxCurCall];
9843	IEMLIVENESSBIT const LivenessClobbered =
9844	{
9845	pLivenessEntry->aBits[IEMLIVENESS_BIT_WRITE].bm64
9846	& ~( pLivenessEntry->aBits[IEMLIVENESS_BIT_READ].bm64
9847	\| pLivenessEntry->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64
9848	\| pLivenessEntry->aBits[IEMLIVENESS_BIT_OTHER].bm64)
9849	};
9850	IEMLIVENESSBIT const LivenessDelayable =
9851	{
9852	pLivenessEntry->aBits[IEMLIVENESS_BIT_WRITE].bm64
9853	& pLivenessEntry->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64
9854	& ~( pLivenessEntry->aBits[IEMLIVENESS_BIT_READ].bm64
9855	\| pLivenessEntry->aBits[IEMLIVENESS_BIT_OTHER].bm64)
9856	};
9857	# define CHECK_FLAG_AND_UPDATE_STATS(a_fEfl, a_fLivenessMember, a_CoreStatName) \
9858	if (fEflOutput & (a_fEfl)) \
9859	{ \
9860	if (LivenessClobbered.a_fLivenessMember) \
9861	STAM_COUNTER_INC(&pVCpu->iem.s.a_CoreStatName ## Skippable); \
9862	else if (LivenessDelayable.a_fLivenessMember) \
9863	STAM_COUNTER_INC(&pVCpu->iem.s.a_CoreStatName ## Delayable); \
9864	else \
9865	STAM_COUNTER_INC(&pVCpu->iem.s.a_CoreStatName ## Required); \
9866	} else do { } while (0)
9867	# endif
9868	CHECK_FLAG_AND_UPDATE_STATS(X86_EFL_CF, fEflCf, StatNativeLivenessEflCf);
9869	CHECK_FLAG_AND_UPDATE_STATS(X86_EFL_PF, fEflPf, StatNativeLivenessEflPf);
9870	CHECK_FLAG_AND_UPDATE_STATS(X86_EFL_AF, fEflAf, StatNativeLivenessEflAf);
9871	CHECK_FLAG_AND_UPDATE_STATS(X86_EFL_ZF, fEflZf, StatNativeLivenessEflZf);
9872	CHECK_FLAG_AND_UPDATE_STATS(X86_EFL_SF, fEflSf, StatNativeLivenessEflSf);
9873	CHECK_FLAG_AND_UPDATE_STATS(X86_EFL_OF, fEflOf, StatNativeLivenessEflOf);
9874	//CHECK_FLAG_AND_UPDATE_STATS(~X86_EFL_STATUS_BITS, fEflOther, StatNativeLivenessEflOther);
9875	# undef CHECK_FLAG_AND_UPDATE_STATS
9876	}
9877	RT_NOREF(fEflInput);
9878	}
9879	#endif /* VBOX_WITH_STATISTICS */
9880
9881	#undef IEM_MC_FETCH_EFLAGS /* should not be used */
9882	#define IEM_MC_FETCH_EFLAGS_EX(a_EFlags, a_fEflInput, a_fEflOutput) \
9883	off = iemNativeEmitFetchEFlags(pReNative, off, a_EFlags, a_fEflInput, a_fEflOutput)
9884
9885	/** Handles IEM_MC_FETCH_EFLAGS_EX. */
9886	DECL_INLINE_THROW(uint32_t)
9887	iemNativeEmitFetchEFlags(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarEFlags,
9888	uint32_t fEflInput, uint32_t fEflOutput)
9889	{
9890	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarEFlags);
9891	Assert(pReNative->Core.aVars[idxVarEFlags].cbVar == sizeof(uint32_t));
9892	RT_NOREF(fEflInput, fEflOutput);
9893
9894	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
9895	# ifdef VBOX_STRICT
9896	if ( pReNative->idxCurCall != 0
9897	&& (fEflInput != 0 \|\| fEflOutput != 0) /* for NOT these are both zero for now. */)
9898	{
9899	PCIEMLIVENESSENTRY const pLivenessEntry = &pReNative->paLivenessEntries[pReNative->idxCurCall - 1];
9900	uint32_t const fBoth = fEflInput \| fEflOutput;
9901	# define ASSERT_ONE_EFL(a_fElfConst, a_idxField) \
9902	AssertMsg( !(fBoth & (a_fElfConst)) \
9903	\|\| (!(fEflInput & (a_fElfConst)) \
9904	? IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, a_idxField)) \
9905	: !(fEflOutput & (a_fElfConst)) \
9906	? IEMLIVENESS_STATE_IS_INPUT_EXPECTED( iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, a_idxField)) \
9907	: IEMLIVENESS_STATE_IS_MODIFY_EXPECTED( iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, a_idxField)) ), \
9908	("%s - %u\n", #a_fElfConst, iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, a_idxField)))
9909	ASSERT_ONE_EFL(~(uint32_t)X86_EFL_STATUS_BITS, IEMLIVENESSBIT_IDX_EFL_OTHER);
9910	ASSERT_ONE_EFL(X86_EFL_CF, IEMLIVENESSBIT_IDX_EFL_CF);
9911	ASSERT_ONE_EFL(X86_EFL_PF, IEMLIVENESSBIT_IDX_EFL_PF);
9912	ASSERT_ONE_EFL(X86_EFL_AF, IEMLIVENESSBIT_IDX_EFL_AF);
9913	ASSERT_ONE_EFL(X86_EFL_ZF, IEMLIVENESSBIT_IDX_EFL_ZF);
9914	ASSERT_ONE_EFL(X86_EFL_SF, IEMLIVENESSBIT_IDX_EFL_SF);
9915	ASSERT_ONE_EFL(X86_EFL_OF, IEMLIVENESSBIT_IDX_EFL_OF);
9916	# undef ASSERT_ONE_EFL
9917	}
9918	# endif
9919	#endif
9920
9921	/** @todo this is suboptimial. EFLAGS is probably shadowed and we should use
9922	* the existing shadow copy. */
9923	uint8_t const idxReg = iemNativeVarRegisterAcquire(pReNative, idxVarEFlags, &off, false /fInitialized/);
9924	iemNativeRegClearAndMarkAsGstRegShadow(pReNative, idxReg, kIemNativeGstReg_EFlags, off);
9925	off = iemNativeEmitLoadGprFromVCpuU32(pReNative, off, idxReg, RT_UOFFSETOF(VMCPUCC, cpum.GstCtx.eflags));
9926	iemNativeVarRegisterRelease(pReNative, idxVarEFlags);
9927	return off;
9928	}
9929
9930
9931
9932	/** @todo emit strict build assertions for IEM_MC_COMMIT_EFLAGS_EX when we
9933	* start using it with custom native code emission (inlining assembly
9934	* instruction helpers). */
9935	#undef IEM_MC_COMMIT_EFLAGS /* should not be used */
9936	#define IEM_MC_COMMIT_EFLAGS_EX(a_EFlags, a_fEflInput, a_fEflOutput) \
9937	IEMNATIVE_EFLAGS_OPTIMIZATION_STATS(a_fEflInput, a_fEflOutput); \
9938	off = iemNativeEmitCommitEFlags(pReNative, off, a_EFlags, a_fEflOutput)
9939
9940	/** Handles IEM_MC_COMMIT_EFLAGS_EX. */
9941	DECL_INLINE_THROW(uint32_t)
9942	iemNativeEmitCommitEFlags(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarEFlags, uint32_t fEflOutput)
9943	{
9944	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarEFlags);
9945	Assert(pReNative->Core.aVars[idxVarEFlags].cbVar == sizeof(uint32_t));
9946	RT_NOREF(fEflOutput);
9947
9948	uint8_t const idxReg = iemNativeVarRegisterAcquire(pReNative, idxVarEFlags, &off, true /fInitialized/);
9949
9950	#ifdef VBOX_STRICT
9951	off = iemNativeEmitTestAnyBitsInGpr(pReNative, off, idxReg, X86_EFL_RA1_MASK);
9952	uint32_t offFixup = off;
9953	off = iemNativeEmitJnzToFixed(pReNative, off, off);
9954	off = iemNativeEmitBrk(pReNative, off, UINT32_C(0x2001));
9955	iemNativeFixupFixedJump(pReNative, offFixup, off);
9956
9957	off = iemNativeEmitTestAnyBitsInGpr(pReNative, off, idxReg, X86_EFL_RAZ_MASK & CPUMX86EFLAGS_HW_MASK_32);
9958	offFixup = off;
9959	off = iemNativeEmitJzToFixed(pReNative, off, off);
9960	off = iemNativeEmitBrk(pReNative, off, UINT32_C(0x2002));
9961	iemNativeFixupFixedJump(pReNative, offFixup, off);
9962
9963	/** @todo validate that only bits in the fElfOutput mask changed. */
9964	#endif
9965
9966	iemNativeRegClearAndMarkAsGstRegShadow(pReNative, idxReg, kIemNativeGstReg_EFlags, off);
9967	off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxReg, RT_UOFFSETOF_DYN(VMCPUCC, cpum.GstCtx.eflags));
9968	iemNativeVarRegisterRelease(pReNative, idxVarEFlags);
9969	return off;
9970	}
9971
9972
9973
9974	/*********************************************************************************************************************************
9975	* Emitters for segment register fetches (IEM_MC_FETCH_SREG_XXX).
9976	*********************************************************************************************************************************/
9977
9978	#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) \
9979	off = iemNativeEmitFetchSReg(pReNative, off, a_u16Dst, a_iSReg, sizeof(uint16_t))
9980
9981	#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) \
9982	off = iemNativeEmitFetchSReg(pReNative, off, a_u32Dst, a_iSReg, sizeof(uint32_t))
9983
9984	#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) \
9985	off = iemNativeEmitFetchSReg(pReNative, off, a_u64Dst, a_iSReg, sizeof(uint64_t))
9986
9987
9988	/** Emits code for IEM_MC_FETCH_SREG_U16, IEM_MC_FETCH_SREG_ZX_U32 and
9989	* IEM_MC_FETCH_SREG_ZX_U64. */
9990	DECL_INLINE_THROW(uint32_t)
9991	iemNativeEmitFetchSReg(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar, uint8_t iSReg, int8_t cbVar)
9992	{
9993	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar);
9994	Assert(pReNative->Core.aVars[idxDstVar].cbVar == cbVar); RT_NOREF(cbVar);
9995	Assert(iSReg < X86_SREG_COUNT);
9996
9997	/*
9998	* For now, we will not create a shadow copy of a selector. The rational
9999	* is that since we do not recompile the popping and loading of segment
10000	* registers and that the the IEM_MC_FETCH_SREG_U* MCs are only used for
10001	* pushing and moving to registers, there is only a small chance that the
10002	* shadow copy will be accessed again before the register is reloaded. One
10003	* scenario would be nested called in 16-bit code, but I doubt it's worth
10004	* the extra register pressure atm.
10005	*
10006	* What we really need first, though, is to combine iemNativeRegAllocTmpForGuestReg
10007	* and iemNativeVarRegisterAcquire for a load scenario. We only got the
10008	* store scencario covered at present (r160730).
10009	*/
10010	iemNativeVarSetKindToStack(pReNative, idxDstVar);
10011	uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off);
10012	off = iemNativeEmitLoadGprFromVCpuU16(pReNative, off, idxVarReg, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aSRegs[iSReg].Sel));
10013	iemNativeVarRegisterRelease(pReNative, idxDstVar);
10014	return off;
10015	}
10016
10017
10018
10019	/*********************************************************************************************************************************
10020	* Register references. *
10021	*********************************************************************************************************************************/
10022
10023	#define IEM_MC_REF_GREG_U8_THREADED(a_pu8Dst, a_iGRegEx) \
10024	off = iemNativeEmitRefGregU8(pReNative, off, a_pu8Dst, a_iGRegEx, false /fConst/)
10025
10026	#define IEM_MC_REF_GREG_U8_CONST_THREADED(a_pu8Dst, a_iGReg) \
10027	off = iemNativeEmitRefGregU8(pReNative, off, a_pu8Dst, a_iGRegEx, true /fConst/)
10028
10029	/** Handles IEM_MC_REF_GREG_U8[_CONST]. */
10030	DECL_INLINE_THROW(uint32_t)
10031	iemNativeEmitRefGregU8(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarRef, uint8_t iGRegEx, bool fConst)
10032	{
10033	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarRef);
10034	Assert(pReNative->Core.aVars[idxVarRef].cbVar == sizeof(void *));
10035	Assert(iGRegEx < 20);
10036
10037	if (iGRegEx < 16)
10038	iemNativeVarSetKindToGstRegRef(pReNative, idxVarRef, kIemNativeGstRegRef_Gpr, iGRegEx & 15);
10039	else
10040	iemNativeVarSetKindToGstRegRef(pReNative, idxVarRef, kIemNativeGstRegRef_GprHighByte, iGRegEx & 15);
10041
10042	/* If we've delayed writing back the register value, flush it now. */
10043	off = iemNativeRegFlushPendingSpecificWrite(pReNative, off, kIemNativeGstRegRef_Gpr, iGRegEx & 15);
10044
10045	/* If it's not a const reference we need to flush the shadow copy of the register now. */
10046	if (!fConst)
10047	iemNativeRegFlushGuestShadows(pReNative, RT_BIT_64(IEMNATIVEGSTREG_GPR(iGRegEx & 15)));
10048
10049	return off;
10050	}
10051
10052	#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) \
10053	off = iemNativeEmitRefGregUxx(pReNative, off, a_pu16Dst, a_iGReg, false /fConst/)
10054
10055	#define IEM_MC_REF_GREG_U16_CONST(a_pu16Dst, a_iGReg) \
10056	off = iemNativeEmitRefGregUxx(pReNative, off, a_pu16Dst, a_iGReg, true /fConst/)
10057
10058	#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) \
10059	off = iemNativeEmitRefGregUxx(pReNative, off, a_pu32Dst, a_iGReg, false /fConst/)
10060
10061	#define IEM_MC_REF_GREG_U32_CONST(a_pu32Dst, a_iGReg) \
10062	off = iemNativeEmitRefGregUxx(pReNative, off, a_pu32Dst, a_iGReg, true /fConst/)
10063
10064	#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) \
10065	off = iemNativeEmitRefGregUxx(pReNative, off, a_pi32Dst, a_iGReg, false /fConst/)
10066
10067	#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) \
10068	off = iemNativeEmitRefGregUxx(pReNative, off, a_pi32Dst, a_iGReg, true /fConst/)
10069
10070	#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) \
10071	off = iemNativeEmitRefGregUxx(pReNative, off, a_pu64Dst, a_iGReg, false /fConst/)
10072
10073	#define IEM_MC_REF_GREG_U64_CONST(a_pu64Dst, a_iGReg) \
10074	off = iemNativeEmitRefGregUxx(pReNative, off, a_pu64Dst, a_iGReg, true /fConst/)
10075
10076	#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) \
10077	off = iemNativeEmitRefGregUxx(pReNative, off, a_pi64Dst, a_iGReg, false /fConst/)
10078
10079	#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) \
10080	off = iemNativeEmitRefGregUxx(pReNative, off, a_pi64Dst, a_iGReg, true /fConst/)
10081
10082	/** Handles IEM_MC_REF_GREG_Uxx[_CONST] and IEM_MC_REF_GREG_Ixx[_CONST]. */
10083	DECL_INLINE_THROW(uint32_t)
10084	iemNativeEmitRefGregUxx(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarRef, uint8_t iGReg, bool fConst)
10085	{
10086	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarRef);
10087	Assert(pReNative->Core.aVars[idxVarRef].cbVar == sizeof(void *));
10088	Assert(iGReg < 16);
10089
10090	iemNativeVarSetKindToGstRegRef(pReNative, idxVarRef, kIemNativeGstRegRef_Gpr, iGReg);
10091
10092	/* If we've delayed writing back the register value, flush it now. */
10093	off = iemNativeRegFlushPendingSpecificWrite(pReNative, off, kIemNativeGstRegRef_Gpr, iGReg);
10094
10095	/* If it's not a const reference we need to flush the shadow copy of the register now. */
10096	if (!fConst)
10097	iemNativeRegFlushGuestShadows(pReNative, RT_BIT_64(IEMNATIVEGSTREG_GPR(iGReg)));
10098
10099	return off;
10100	}
10101
10102
10103	#undef IEM_MC_REF_EFLAGS /* should not be used. */
10104	#define IEM_MC_REF_EFLAGS_EX(a_pEFlags, a_fEflInput, a_fEflOutput) \
10105	IEMNATIVE_EFLAGS_OPTIMIZATION_STATS(a_fEflInput, a_fEflOutput); \
10106	off = iemNativeEmitRefEFlags(pReNative, off, a_pEFlags)
10107
10108	/** Handles IEM_MC_REF_EFLAGS. */
10109	DECL_INLINE_THROW(uint32_t)
10110	iemNativeEmitRefEFlags(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarRef)
10111	{
10112	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarRef);
10113	Assert(pReNative->Core.aVars[idxVarRef].cbVar == sizeof(void *));
10114
10115	iemNativeVarSetKindToGstRegRef(pReNative, idxVarRef, kIemNativeGstRegRef_EFlags, 0);
10116
10117	/* If we've delayed writing back the register value, flush it now. */
10118	off = iemNativeRegFlushPendingSpecificWrite(pReNative, off, kIemNativeGstRegRef_EFlags, 0);
10119
10120	/* If there is a shadow copy of guest EFLAGS, flush it now. */
10121	iemNativeRegFlushGuestShadows(pReNative, RT_BIT_64(kIemNativeGstReg_EFlags));
10122
10123	return off;
10124	}
10125
10126
10127	/** @todo Emit code for IEM_MC_ASSERT_EFLAGS in strict builds? Once we emit
10128	* different code from threaded recompiler, maybe it would be helpful. For now
10129	* we assume the threaded recompiler catches any incorrect EFLAGS delcarations. */
10130	#define IEM_MC_ASSERT_EFLAGS(a_fEflInput, a_fEflOutput) ((void)0)
10131
10132
10133
10134	/*********************************************************************************************************************************
10135	* Effective Address Calculation *
10136	*********************************************************************************************************************************/
10137	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp) \
10138	off = iemNativeEmitCalcRmEffAddrThreadedAddr16(pReNative, off, a_bRm, a_u16Disp, a_GCPtrEff)
10139
10140	/** Emit code for IEM_MC_CALC_RM_EFF_ADDR_THREADED_16.
10141	* @sa iemOpHlpCalcRmEffAddrThreadedAddr16 */
10142	DECL_INLINE_THROW(uint32_t)
10143	iemNativeEmitCalcRmEffAddrThreadedAddr16(PIEMRECOMPILERSTATE pReNative, uint32_t off,
10144	uint8_t bRm, uint16_t u16Disp, uint8_t idxVarRet)
10145	{
10146	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarRet);
10147
10148	/*
10149	* Handle the disp16 form with no registers first.
10150	*
10151	* Convert to an immediate value, as that'll delay the register allocation
10152	* and assignment till the memory access / call / whatever and we can use
10153	* a more appropriate register (or none at all).
10154	*/
10155	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 6)
10156	{
10157	iemNativeVarSetKindToConst(pReNative, idxVarRet, u16Disp);
10158	return off;
10159	}
10160
10161	/* Determin the displacment. */
10162	uint16_t u16EffAddr;
10163	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
10164	{
10165	case 0: u16EffAddr = 0; break;
10166	case 1: u16EffAddr = (int16_t)(int8_t)u16Disp; break;
10167	case 2: u16EffAddr = u16Disp; break;
10168	default: AssertFailedStmt(u16EffAddr = 0);
10169	}
10170
10171	/* Determine the registers involved. */
10172	uint8_t idxGstRegBase;
10173	uint8_t idxGstRegIndex;
10174	switch (bRm & X86_MODRM_RM_MASK)
10175	{
10176	case 0:
10177	idxGstRegBase = X86_GREG_xBX;
10178	idxGstRegIndex = X86_GREG_xSI;
10179	break;
10180	case 1:
10181	idxGstRegBase = X86_GREG_xBX;
10182	idxGstRegIndex = X86_GREG_xDI;
10183	break;
10184	case 2:
10185	idxGstRegBase = X86_GREG_xBP;
10186	idxGstRegIndex = X86_GREG_xSI;
10187	break;
10188	case 3:
10189	idxGstRegBase = X86_GREG_xBP;
10190	idxGstRegIndex = X86_GREG_xDI;
10191	break;
10192	case 4:
10193	idxGstRegBase = X86_GREG_xSI;
10194	idxGstRegIndex = UINT8_MAX;
10195	break;
10196	case 5:
10197	idxGstRegBase = X86_GREG_xDI;
10198	idxGstRegIndex = UINT8_MAX;
10199	break;
10200	case 6:
10201	idxGstRegBase = X86_GREG_xBP;
10202	idxGstRegIndex = UINT8_MAX;
10203	break;
10204	#ifdef _MSC_VER /* lazy compiler, thinks idxGstRegBase and idxGstRegIndex may otherwise be used uninitialized. */
10205	default:
10206	#endif
10207	case 7:
10208	idxGstRegBase = X86_GREG_xBX;
10209	idxGstRegIndex = UINT8_MAX;
10210	break;
10211	}
10212
10213	/*
10214	* Now emit code that calculates: idxRegRet = (uint16_t)(u16EffAddr + idxGstRegBase [+ idxGstRegIndex])
10215	*/
10216	uint8_t const idxRegRet = iemNativeVarRegisterAcquire(pReNative, idxVarRet, &off);
10217	uint8_t const idxRegBase = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(idxGstRegBase),
10218	kIemNativeGstRegUse_ReadOnly);
10219	uint8_t const idxRegIndex = idxGstRegIndex != UINT8_MAX
10220	? iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(idxGstRegIndex),
10221	kIemNativeGstRegUse_ReadOnly)
10222	: UINT8_MAX;
10223	#ifdef RT_ARCH_AMD64
10224	if (idxRegIndex == UINT8_MAX)
10225	{
10226	if (u16EffAddr == 0)
10227	{
10228	/* movxz ret, base */
10229	off = iemNativeEmitLoadGprFromGpr16(pReNative, off, idxRegRet, idxRegBase);
10230	}
10231	else
10232	{
10233	/* lea ret32, [base64 + disp32] */
10234	Assert(idxRegBase != X86_GREG_xSP /SIB/);
10235	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
10236	if (idxRegRet >= 8 \|\| idxRegBase >= 8)
10237	pbCodeBuf[off++] = (idxRegRet >= 8 ? X86_OP_REX_R : 0) \| (idxRegBase >= 8 ? X86_OP_REX_B : 0);
10238	pbCodeBuf[off++] = 0x8d;
10239	if (idxRegBase != X86_GREG_x12 /SIB/)
10240	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_MEM4, idxRegRet & 7, idxRegBase & 7);
10241	else
10242	{
10243	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_MEM4, idxRegRet & 7, 4 /SIB/);
10244	pbCodeBuf[off++] = X86_SIB_MAKE(X86_GREG_x12 & 7, 4 /no index/, 0);
10245	}
10246	pbCodeBuf[off++] = RT_BYTE1(u16EffAddr);
10247	pbCodeBuf[off++] = RT_BYTE2(u16EffAddr);
10248	pbCodeBuf[off++] = 0;
10249	pbCodeBuf[off++] = 0;
10250	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
10251
10252	off = iemNativeEmitClear16UpGpr(pReNative, off, idxRegRet);
10253	}
10254	}
10255	else
10256	{
10257	/* lea ret32, [index64 + base64 (+ disp32)] */
10258	Assert(idxRegIndex != X86_GREG_xSP /no-index/);
10259	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
10260	if (idxRegRet >= 8 \|\| idxRegBase >= 8 \|\| idxRegIndex >= 8)
10261	pbCodeBuf[off++] = (idxRegRet >= 8 ? X86_OP_REX_R : 0)
10262	\| (idxRegBase >= 8 ? X86_OP_REX_B : 0)
10263	\| (idxRegIndex >= 8 ? X86_OP_REX_X : 0);
10264	pbCodeBuf[off++] = 0x8d;
10265	uint8_t const bMod = u16EffAddr == 0 && (idxRegBase & 7) != X86_GREG_xBP ? X86_MOD_MEM0 : X86_MOD_MEM4;
10266	pbCodeBuf[off++] = X86_MODRM_MAKE(bMod, idxRegRet & 7, 4 /SIB/);
10267	pbCodeBuf[off++] = X86_SIB_MAKE(idxRegBase & 7, idxRegIndex & 7, 0);
10268	if (bMod == X86_MOD_MEM4)
10269	{
10270	pbCodeBuf[off++] = RT_BYTE1(u16EffAddr);
10271	pbCodeBuf[off++] = RT_BYTE2(u16EffAddr);
10272	pbCodeBuf[off++] = 0;
10273	pbCodeBuf[off++] = 0;
10274	}
10275	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
10276	off = iemNativeEmitClear16UpGpr(pReNative, off, idxRegRet);
10277	}
10278
10279	#elif defined(RT_ARCH_ARM64)
10280	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 5);
10281	if (u16EffAddr == 0)
10282	{
10283	if (idxRegIndex == UINT8_MAX)
10284	pu32CodeBuf[off++] = Armv8A64MkInstrUxth(idxRegRet, idxRegBase);
10285	else
10286	{
10287	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubReg(false /fSub/, idxRegRet, idxRegBase, idxRegIndex, false /f64Bit/);
10288	pu32CodeBuf[off++] = Armv8A64MkInstrUxth(idxRegRet, idxRegRet);
10289	}
10290	}
10291	else
10292	{
10293	if ((int16_t)u16EffAddr < 4096 && (int16_t)u16EffAddr >= 0)
10294	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(false /fSub/, idxRegRet, idxRegBase, u16EffAddr, false /f64Bit/);
10295	else if ((int16_t)u16EffAddr > -4096 && (int16_t)u16EffAddr < 0)
10296	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(true /fSub/, idxRegRet, idxRegBase,
10297	(uint16_t)-(int16_t)u16EffAddr, false /f64Bit/);
10298	else
10299	{
10300	pu32CodeBuf[off++] = Armv8A64MkInstrMovZ(idxRegRet, u16EffAddr);
10301	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubReg(false /fSub/, idxRegRet, idxRegRet, idxRegBase, false /f64Bit/);
10302	}
10303	if (idxRegIndex != UINT8_MAX)
10304	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubReg(false /fSub/, idxRegRet, idxRegRet, idxRegIndex, false /f64Bit/);
10305	pu32CodeBuf[off++] = Armv8A64MkInstrUxth(idxRegRet, idxRegRet);
10306	}
10307
10308	#else
10309	# error "port me"
10310	#endif
10311
10312	if (idxRegIndex != UINT8_MAX)
10313	iemNativeRegFreeTmp(pReNative, idxRegIndex);
10314	iemNativeRegFreeTmp(pReNative, idxRegBase);
10315	iemNativeVarRegisterRelease(pReNative, idxVarRet);
10316	return off;
10317	}
10318
10319
10320	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32(a_GCPtrEff, a_bRm, a_uSibAndRspOffset, a_u32Disp) \
10321	off = iemNativeEmitCalcRmEffAddrThreadedAddr32(pReNative, off, a_bRm, a_uSibAndRspOffset, a_u32Disp, a_GCPtrEff)
10322
10323	/** Emit code for IEM_MC_CALC_RM_EFF_ADDR_THREADED_32.
10324	* @see iemOpHlpCalcRmEffAddrThreadedAddr32 */
10325	DECL_INLINE_THROW(uint32_t)
10326	iemNativeEmitCalcRmEffAddrThreadedAddr32(PIEMRECOMPILERSTATE pReNative, uint32_t off,
10327	uint8_t bRm, uint32_t uSibAndRspOffset, uint32_t u32Disp, uint8_t idxVarRet)
10328	{
10329	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarRet);
10330
10331	/*
10332	* Handle the disp32 form with no registers first.
10333	*
10334	* Convert to an immediate value, as that'll delay the register allocation
10335	* and assignment till the memory access / call / whatever and we can use
10336	* a more appropriate register (or none at all).
10337	*/
10338	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
10339	{
10340	iemNativeVarSetKindToConst(pReNative, idxVarRet, u32Disp);
10341	return off;
10342	}
10343
10344	/* Calculate the fixed displacement (more down in SIB.B=4 and SIB.B=5 on this). */
10345	uint32_t u32EffAddr = 0;
10346	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
10347	{
10348	case 0: break;
10349	case 1: u32EffAddr = (int8_t)u32Disp; break;
10350	case 2: u32EffAddr = u32Disp; break;
10351	default: AssertFailed();
10352	}
10353
10354	/* Get the register (or SIB) value. */
10355	uint8_t idxGstRegBase = UINT8_MAX;
10356	uint8_t idxGstRegIndex = UINT8_MAX;
10357	uint8_t cShiftIndex = 0;
10358	switch (bRm & X86_MODRM_RM_MASK)
10359	{
10360	case 0: idxGstRegBase = X86_GREG_xAX; break;
10361	case 1: idxGstRegBase = X86_GREG_xCX; break;
10362	case 2: idxGstRegBase = X86_GREG_xDX; break;
10363	case 3: idxGstRegBase = X86_GREG_xBX; break;
10364	case 4: /* SIB */
10365	{
10366	/* index /w scaling . */
10367	cShiftIndex = (uSibAndRspOffset >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
10368	switch ((uSibAndRspOffset >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
10369	{
10370	case 0: idxGstRegIndex = X86_GREG_xAX; break;
10371	case 1: idxGstRegIndex = X86_GREG_xCX; break;
10372	case 2: idxGstRegIndex = X86_GREG_xDX; break;
10373	case 3: idxGstRegIndex = X86_GREG_xBX; break;
10374	case 4: cShiftIndex = 0; /no index/ break;
10375	case 5: idxGstRegIndex = X86_GREG_xBP; break;
10376	case 6: idxGstRegIndex = X86_GREG_xSI; break;
10377	case 7: idxGstRegIndex = X86_GREG_xDI; break;
10378	}
10379
10380	/* base */
10381	switch (uSibAndRspOffset & X86_SIB_BASE_MASK)
10382	{
10383	case 0: idxGstRegBase = X86_GREG_xAX; break;
10384	case 1: idxGstRegBase = X86_GREG_xCX; break;
10385	case 2: idxGstRegBase = X86_GREG_xDX; break;
10386	case 3: idxGstRegBase = X86_GREG_xBX; break;
10387	case 4:
10388	idxGstRegBase = X86_GREG_xSP;
10389	u32EffAddr += uSibAndRspOffset >> 8;
10390	break;
10391	case 5:
10392	if ((bRm & X86_MODRM_MOD_MASK) != 0)
10393	idxGstRegBase = X86_GREG_xBP;
10394	else
10395	{
10396	Assert(u32EffAddr == 0);
10397	u32EffAddr = u32Disp;
10398	}
10399	break;
10400	case 6: idxGstRegBase = X86_GREG_xSI; break;
10401	case 7: idxGstRegBase = X86_GREG_xDI; break;
10402	}
10403	break;
10404	}
10405	case 5: idxGstRegBase = X86_GREG_xBP; break;
10406	case 6: idxGstRegBase = X86_GREG_xSI; break;
10407	case 7: idxGstRegBase = X86_GREG_xDI; break;
10408	}
10409
10410	/*
10411	* If no registers are involved (SIB.B=5, SIB.X=4) repeat what we did at
10412	* the start of the function.
10413	*/
10414	if (idxGstRegBase == UINT8_MAX && idxGstRegIndex == UINT8_MAX)
10415	{
10416	iemNativeVarSetKindToConst(pReNative, idxVarRet, u32EffAddr);
10417	return off;
10418	}
10419
10420	/*
10421	* Now emit code that calculates: idxRegRet = (uint32_t)(u32EffAddr [+ idxGstRegBase] [+ (idxGstRegIndex << cShiftIndex)])
10422	*/
10423	uint8_t const idxRegRet = iemNativeVarRegisterAcquire(pReNative, idxVarRet, &off);
10424	uint8_t idxRegBase = idxGstRegBase == UINT8_MAX ? UINT8_MAX
10425	: iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(idxGstRegBase),
10426	kIemNativeGstRegUse_ReadOnly);
10427	uint8_t idxRegIndex = idxGstRegIndex == UINT8_MAX ? UINT8_MAX
10428	: iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(idxGstRegIndex),
10429	kIemNativeGstRegUse_ReadOnly);
10430
10431	/* If base is not given and there is no shifting, swap the registers to avoid code duplication. */
10432	if (idxRegBase == UINT8_MAX && cShiftIndex == 0)
10433	{
10434	idxRegBase = idxRegIndex;
10435	idxRegIndex = UINT8_MAX;
10436	}
10437
10438	#ifdef RT_ARCH_AMD64
10439	if (idxRegIndex == UINT8_MAX)
10440	{
10441	if (u32EffAddr == 0)
10442	{
10443	/* mov ret, base */
10444	off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxRegRet, idxRegBase);
10445	}
10446	else
10447	{
10448	/* lea ret32, [base64 + disp32] */
10449	Assert(idxRegBase != X86_GREG_xSP /SIB/);
10450	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
10451	if (idxRegRet >= 8 \|\| idxRegBase >= 8)
10452	pbCodeBuf[off++] = (idxRegRet >= 8 ? X86_OP_REX_R : 0) \| (idxRegBase >= 8 ? X86_OP_REX_B : 0);
10453	pbCodeBuf[off++] = 0x8d;
10454	uint8_t const bMod = (int8_t)u32EffAddr == (int32_t)u32EffAddr ? X86_MOD_MEM1 : X86_MOD_MEM4;
10455	if (idxRegBase != X86_GREG_x12 /SIB/)
10456	pbCodeBuf[off++] = X86_MODRM_MAKE(bMod, idxRegRet & 7, idxRegBase & 7);
10457	else
10458	{
10459	pbCodeBuf[off++] = X86_MODRM_MAKE(bMod, idxRegRet & 7, 4 /SIB/);
10460	pbCodeBuf[off++] = X86_SIB_MAKE(X86_GREG_x12 & 7, 4 /no index/, 0);
10461	}
10462	pbCodeBuf[off++] = RT_BYTE1(u32EffAddr);
10463	if (bMod == X86_MOD_MEM4)
10464	{
10465	pbCodeBuf[off++] = RT_BYTE2(u32EffAddr);
10466	pbCodeBuf[off++] = RT_BYTE3(u32EffAddr);
10467	pbCodeBuf[off++] = RT_BYTE4(u32EffAddr);
10468	}
10469	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
10470	}
10471	}
10472	else
10473	{
10474	Assert(idxRegIndex != X86_GREG_xSP /no-index/);
10475	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
10476	if (idxRegBase == UINT8_MAX)
10477	{
10478	/* lea ret32, [(index64 << cShiftIndex) + disp32] */
10479	if (idxRegRet >= 8 \|\| idxRegIndex >= 8)
10480	pbCodeBuf[off++] = (idxRegRet >= 8 ? X86_OP_REX_R : 0)
10481	\| (idxRegIndex >= 8 ? X86_OP_REX_X : 0);
10482	pbCodeBuf[off++] = 0x8d;
10483	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_MEM0, idxRegRet & 7, 4 /SIB/);
10484	pbCodeBuf[off++] = X86_SIB_MAKE(5 /nobase/bp/, idxRegIndex & 7, cShiftIndex);
10485	pbCodeBuf[off++] = RT_BYTE1(u32EffAddr);
10486	pbCodeBuf[off++] = RT_BYTE2(u32EffAddr);
10487	pbCodeBuf[off++] = RT_BYTE3(u32EffAddr);
10488	pbCodeBuf[off++] = RT_BYTE4(u32EffAddr);
10489	}
10490	else
10491	{
10492	/* lea ret32, [(index64 << cShiftIndex) + base64 (+ disp32)] */
10493	if (idxRegRet >= 8 \|\| idxRegBase >= 8 \|\| idxRegIndex >= 8)
10494	pbCodeBuf[off++] = (idxRegRet >= 8 ? X86_OP_REX_R : 0)
10495	\| (idxRegBase >= 8 ? X86_OP_REX_B : 0)
10496	\| (idxRegIndex >= 8 ? X86_OP_REX_X : 0);
10497	pbCodeBuf[off++] = 0x8d;
10498	uint8_t const bMod = u32EffAddr == 0 && (idxRegBase & 7) != X86_GREG_xBP ? X86_MOD_MEM0
10499	: (int8_t)u32EffAddr == (int32_t)u32EffAddr ? X86_MOD_MEM1 : X86_MOD_MEM4;
10500	pbCodeBuf[off++] = X86_MODRM_MAKE(bMod, idxRegRet & 7, 4 /SIB/);
10501	pbCodeBuf[off++] = X86_SIB_MAKE(idxRegBase & 7, idxRegIndex & 7, cShiftIndex);
10502	if (bMod != X86_MOD_MEM0)
10503	{
10504	pbCodeBuf[off++] = RT_BYTE1(u32EffAddr);
10505	if (bMod == X86_MOD_MEM4)
10506	{
10507	pbCodeBuf[off++] = RT_BYTE2(u32EffAddr);
10508	pbCodeBuf[off++] = RT_BYTE3(u32EffAddr);
10509	pbCodeBuf[off++] = RT_BYTE4(u32EffAddr);
10510	}
10511	}
10512	}
10513	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
10514	}
10515
10516	#elif defined(RT_ARCH_ARM64)
10517	if (u32EffAddr == 0)
10518	{
10519	if (idxRegIndex == UINT8_MAX)
10520	off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxRegRet, idxRegBase);
10521	else if (idxRegBase == UINT8_MAX)
10522	{
10523	if (cShiftIndex == 0)
10524	off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxRegRet, idxRegIndex);
10525	else
10526	{
10527	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
10528	pu32CodeBuf[off++] = Armv8A64MkInstrLslImm(idxRegRet, idxRegIndex, cShiftIndex, false /f64Bit/);
10529	}
10530	}
10531	else
10532	{
10533	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
10534	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubReg(false /fSub/, idxRegRet, idxRegBase, idxRegIndex,
10535	false /f64Bit/, false /fSetFlags/, cShiftIndex);
10536	}
10537	}
10538	else
10539	{
10540	if ((int32_t)u32EffAddr < 4096 && (int32_t)u32EffAddr >= 0 && idxRegBase != UINT8_MAX)
10541	{
10542	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
10543	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(false /fSub/, idxRegRet, idxRegBase, u32EffAddr, false /f64Bit/);
10544	}
10545	else if ((int32_t)u32EffAddr > -4096 && (int32_t)u32EffAddr < 0 && idxRegBase != UINT8_MAX)
10546	{
10547	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
10548	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(true /fSub/, idxRegRet, idxRegBase,
10549	(uint32_t)-(int32_t)u32EffAddr, false /f64Bit/);
10550	}
10551	else
10552	{
10553	off = iemNativeEmitLoadGprImm64(pReNative, off, idxRegRet, u32EffAddr);
10554	if (idxRegBase != UINT8_MAX)
10555	{
10556	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
10557	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubReg(false /fSub/, idxRegRet, idxRegRet, idxRegBase, false /f64Bit/);
10558	}
10559	}
10560	if (idxRegIndex != UINT8_MAX)
10561	{
10562	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
10563	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubReg(false /fSub/, idxRegRet, idxRegRet, idxRegIndex,
10564	false /f64Bit/, false /fSetFlags/, cShiftIndex);
10565	}
10566	}
10567
10568	#else
10569	# error "port me"
10570	#endif
10571
10572	if (idxRegIndex != UINT8_MAX)
10573	iemNativeRegFreeTmp(pReNative, idxRegIndex);
10574	if (idxRegBase != UINT8_MAX)
10575	iemNativeRegFreeTmp(pReNative, idxRegBase);
10576	iemNativeVarRegisterRelease(pReNative, idxVarRet);
10577	return off;
10578	}
10579
10580
10581	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
10582	off = iemNativeEmitCalcRmEffAddrThreadedAddr64(pReNative, off, a_bRmEx, a_uSibAndRspOffset, \
10583	a_u32Disp, a_cbImm, a_GCPtrEff, true /f64Bit/)
10584
10585	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_FSGS(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
10586	off = iemNativeEmitCalcRmEffAddrThreadedAddr64(pReNative, off, a_bRmEx, a_uSibAndRspOffset, \
10587	a_u32Disp, a_cbImm, a_GCPtrEff, true /f64Bit/)
10588
10589	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_ADDR32(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
10590	off = iemNativeEmitCalcRmEffAddrThreadedAddr64(pReNative, off, a_bRmEx, a_uSibAndRspOffset, \
10591	a_u32Disp, a_cbImm, a_GCPtrEff, false /f64Bit/)
10592
10593	/**
10594	* Emit code for IEM_MC_CALC_RM_EFF_ADDR_THREADED_64*.
10595	*
10596	* @returns New off.
10597	* @param pReNative .
10598	* @param off .
10599	* @param bRmEx The ModRM byte but with bit 3 set to REX.B and
10600	* bit 4 to REX.X. The two bits are part of the
10601	* REG sub-field, which isn't needed in this
10602	* function.
10603	* @param uSibAndRspOffset Two parts:
10604	* - The first 8 bits make up the SIB byte.
10605	* - The next 8 bits are the fixed RSP/ESP offset
10606	* in case of a pop [xSP].
10607	* @param u32Disp The displacement byte/word/dword, if any.
10608	* @param cbInstr The size of the fully decoded instruction. Used
10609	* for RIP relative addressing.
10610	* @param idxVarRet The result variable number.
10611	* @param f64Bit Whether to use a 64-bit or 32-bit address size
10612	* when calculating the address.
10613	*
10614	* @see iemOpHlpCalcRmEffAddrThreadedAddr64
10615	*/
10616	DECL_INLINE_THROW(uint32_t)
10617	iemNativeEmitCalcRmEffAddrThreadedAddr64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t bRmEx, uint32_t uSibAndRspOffset,
10618	uint32_t u32Disp, uint8_t cbInstr, uint8_t idxVarRet, bool f64Bit)
10619	{
10620	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarRet);
10621
10622	/*
10623	* Special case the rip + disp32 form first.
10624	*/
10625	if ((bRmEx & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
10626	{
10627	uint8_t const idxRegRet = iemNativeVarRegisterAcquire(pReNative, idxVarRet, &off);
10628	uint8_t const idxRegPc = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Pc,
10629	kIemNativeGstRegUse_ReadOnly);
10630	#ifdef RT_ARCH_AMD64
10631	if (f64Bit)
10632	{
10633	int64_t const offFinalDisp = (int64_t)(int32_t)u32Disp + cbInstr;
10634	if ((int32_t)offFinalDisp == offFinalDisp)
10635	off = iemNativeEmitLoadGprFromGprWithAddendMaybeZero(pReNative, off, idxRegRet, idxRegPc, (int32_t)offFinalDisp);
10636	else
10637	{
10638	off = iemNativeEmitLoadGprFromGprWithAddend(pReNative, off, idxRegRet, idxRegPc, (int32_t)u32Disp);
10639	off = iemNativeEmitAddGprImm8(pReNative, off, idxRegRet, cbInstr);
10640	}
10641	}
10642	else
10643	off = iemNativeEmitLoadGprFromGpr32WithAddendMaybeZero(pReNative, off, idxRegRet, idxRegPc, (int32_t)u32Disp + cbInstr);
10644
10645	#elif defined(RT_ARCH_ARM64)
10646	if (f64Bit)
10647	off = iemNativeEmitLoadGprFromGprWithAddendMaybeZero(pReNative, off, idxRegRet, idxRegPc,
10648	(int64_t)(int32_t)u32Disp + cbInstr);
10649	else
10650	off = iemNativeEmitLoadGprFromGpr32WithAddendMaybeZero(pReNative, off, idxRegRet, idxRegPc,
10651	(int32_t)u32Disp + cbInstr);
10652
10653	#else
10654	# error "Port me!"
10655	#endif
10656	iemNativeRegFreeTmp(pReNative, idxRegPc);
10657	iemNativeVarRegisterRelease(pReNative, idxVarRet);
10658	return off;
10659	}
10660
10661	/* Calculate the fixed displacement (more down in SIB.B=4 and SIB.B=5 on this). */
10662	int64_t i64EffAddr = 0;
10663	switch ((bRmEx >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
10664	{
10665	case 0: break;
10666	case 1: i64EffAddr = (int8_t)u32Disp; break;
10667	case 2: i64EffAddr = (int32_t)u32Disp; break;
10668	default: AssertFailed();
10669	}
10670
10671	/* Get the register (or SIB) value. */
10672	uint8_t idxGstRegBase = UINT8_MAX;
10673	uint8_t idxGstRegIndex = UINT8_MAX;
10674	uint8_t cShiftIndex = 0;
10675	if ((bRmEx & X86_MODRM_RM_MASK) != 4)
10676	idxGstRegBase = bRmEx & (X86_MODRM_RM_MASK \| 0x8); /* bRmEx[bit 3] = REX.B */
10677	else /* SIB: */
10678	{
10679	/* index /w scaling . */
10680	cShiftIndex = (uSibAndRspOffset >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
10681	idxGstRegIndex = ((uSibAndRspOffset >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
10682	\| ((bRmEx & 0x10) >> 1); /* bRmEx[bit 4] = REX.X */
10683	if (idxGstRegIndex == 4)
10684	{
10685	/* no index */
10686	cShiftIndex = 0;
10687	idxGstRegIndex = UINT8_MAX;
10688	}
10689
10690	/* base */
10691	idxGstRegBase = (uSibAndRspOffset & X86_SIB_BASE_MASK) \| (bRmEx & 0x8); /* bRmEx[bit 3] = REX.B */
10692	if (idxGstRegBase == 4)
10693	{
10694	/* pop [rsp] hack */
10695	i64EffAddr += uSibAndRspOffset >> 8; /* (this is why i64EffAddr must be 64-bit) */
10696	}
10697	else if ( (idxGstRegBase & X86_SIB_BASE_MASK) == 5
10698	&& (bRmEx & X86_MODRM_MOD_MASK) == 0)
10699	{
10700	/* mod=0 and base=5 -> disp32, no base reg. */
10701	Assert(i64EffAddr == 0);
10702	i64EffAddr = (int32_t)u32Disp;
10703	idxGstRegBase = UINT8_MAX;
10704	}
10705	}
10706
10707	/*
10708	* If no registers are involved (SIB.B=5, SIB.X=4) repeat what we did at
10709	* the start of the function.
10710	*/
10711	if (idxGstRegBase == UINT8_MAX && idxGstRegIndex == UINT8_MAX)
10712	{
10713	if (f64Bit)
10714	iemNativeVarSetKindToConst(pReNative, idxVarRet, (uint64_t)i64EffAddr);
10715	else
10716	iemNativeVarSetKindToConst(pReNative, idxVarRet, (uint32_t)i64EffAddr);
10717	return off;
10718	}
10719
10720	/*
10721	* Now emit code that calculates:
10722	* idxRegRet = (uint64_t)(i64EffAddr [+ idxGstRegBase] [+ (idxGstRegIndex << cShiftIndex)])
10723	* or if !f64Bit:
10724	* idxRegRet = (uint32_t)(i64EffAddr [+ idxGstRegBase] [+ (idxGstRegIndex << cShiftIndex)])
10725	*/
10726	uint8_t const idxRegRet = iemNativeVarRegisterAcquire(pReNative, idxVarRet, &off);
10727	uint8_t idxRegBase = idxGstRegBase == UINT8_MAX ? UINT8_MAX
10728	: iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(idxGstRegBase),
10729	kIemNativeGstRegUse_ReadOnly);
10730	uint8_t idxRegIndex = idxGstRegIndex == UINT8_MAX ? UINT8_MAX
10731	: iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(idxGstRegIndex),
10732	kIemNativeGstRegUse_ReadOnly);
10733
10734	/* If base is not given and there is no shifting, swap the registers to avoid code duplication. */
10735	if (idxRegBase == UINT8_MAX && cShiftIndex == 0)
10736	{
10737	idxRegBase = idxRegIndex;
10738	idxRegIndex = UINT8_MAX;
10739	}
10740
10741	#ifdef RT_ARCH_AMD64
10742	uint8_t bFinalAdj;
10743	if (!f64Bit \|\| (int32_t)i64EffAddr == i64EffAddr)
10744	bFinalAdj = 0; /* likely */
10745	else
10746	{
10747	/* pop [rsp] with a problematic disp32 value. Split out the
10748	RSP offset and add it separately afterwards (bFinalAdj). */
10749	/** @todo testcase: pop [rsp] with problematic disp32 (mod4). */
10750	Assert(idxGstRegBase == X86_GREG_xSP);
10751	Assert(((bRmEx >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK) == X86_MOD_MEM4);
10752	bFinalAdj = (uint8_t)(uSibAndRspOffset >> 8);
10753	Assert(bFinalAdj != 0);
10754	i64EffAddr -= bFinalAdj;
10755	Assert((int32_t)i64EffAddr == i64EffAddr);
10756	}
10757	uint32_t const u32EffAddr = (uint32_t)i64EffAddr;
10758	//pReNative->pInstrBuf[off++] = 0xcc;
10759
10760	if (idxRegIndex == UINT8_MAX)
10761	{
10762	if (u32EffAddr == 0)
10763	{
10764	/* mov ret, base */
10765	if (f64Bit)
10766	off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxRegRet, idxRegBase);
10767	else
10768	off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxRegRet, idxRegBase);
10769	}
10770	else
10771	{
10772	/* lea ret, [base + disp32] */
10773	Assert(idxRegBase != X86_GREG_xSP /SIB/);
10774	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
10775	if (f64Bit \|\| idxRegRet >= 8 \|\| idxRegBase >= 8)
10776	pbCodeBuf[off++] = (idxRegRet >= 8 ? X86_OP_REX_R : 0)
10777	\| (idxRegBase >= 8 ? X86_OP_REX_B : 0)
10778	\| (f64Bit ? X86_OP_REX_W : 0);
10779	pbCodeBuf[off++] = 0x8d;
10780	uint8_t const bMod = (int8_t)u32EffAddr == (int32_t)u32EffAddr ? X86_MOD_MEM1 : X86_MOD_MEM4;
10781	if (idxRegBase != X86_GREG_x12 /SIB/)
10782	pbCodeBuf[off++] = X86_MODRM_MAKE(bMod, idxRegRet & 7, idxRegBase & 7);
10783	else
10784	{
10785	pbCodeBuf[off++] = X86_MODRM_MAKE(bMod, idxRegRet & 7, 4 /SIB/);
10786	pbCodeBuf[off++] = X86_SIB_MAKE(X86_GREG_x12 & 7, 4 /no index/, 0);
10787	}
10788	pbCodeBuf[off++] = RT_BYTE1(u32EffAddr);
10789	if (bMod == X86_MOD_MEM4)
10790	{
10791	pbCodeBuf[off++] = RT_BYTE2(u32EffAddr);
10792	pbCodeBuf[off++] = RT_BYTE3(u32EffAddr);
10793	pbCodeBuf[off++] = RT_BYTE4(u32EffAddr);
10794	}
10795	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
10796	}
10797	}
10798	else
10799	{
10800	Assert(idxRegIndex != X86_GREG_xSP /no-index/);
10801	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
10802	if (idxRegBase == UINT8_MAX)
10803	{
10804	/* lea ret, [(index64 << cShiftIndex) + disp32] */
10805	if (f64Bit \|\| idxRegRet >= 8 \|\| idxRegIndex >= 8)
10806	pbCodeBuf[off++] = (idxRegRet >= 8 ? X86_OP_REX_R : 0)
10807	\| (idxRegIndex >= 8 ? X86_OP_REX_X : 0)
10808	\| (f64Bit ? X86_OP_REX_W : 0);
10809	pbCodeBuf[off++] = 0x8d;
10810	pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_MEM0, idxRegRet & 7, 4 /SIB/);
10811	pbCodeBuf[off++] = X86_SIB_MAKE(5 /nobase/bp/, idxRegIndex & 7, cShiftIndex);
10812	pbCodeBuf[off++] = RT_BYTE1(u32EffAddr);
10813	pbCodeBuf[off++] = RT_BYTE2(u32EffAddr);
10814	pbCodeBuf[off++] = RT_BYTE3(u32EffAddr);
10815	pbCodeBuf[off++] = RT_BYTE4(u32EffAddr);
10816	}
10817	else
10818	{
10819	/* lea ret, [(index64 << cShiftIndex) + base64 (+ disp32)] */
10820	if (f64Bit \|\| idxRegRet >= 8 \|\| idxRegBase >= 8 \|\| idxRegIndex >= 8)
10821	pbCodeBuf[off++] = (idxRegRet >= 8 ? X86_OP_REX_R : 0)
10822	\| (idxRegBase >= 8 ? X86_OP_REX_B : 0)
10823	\| (idxRegIndex >= 8 ? X86_OP_REX_X : 0)
10824	\| (f64Bit ? X86_OP_REX_W : 0);
10825	pbCodeBuf[off++] = 0x8d;
10826	uint8_t const bMod = u32EffAddr == 0 && (idxRegBase & 7) != X86_GREG_xBP ? X86_MOD_MEM0
10827	: (int8_t)u32EffAddr == (int32_t)u32EffAddr ? X86_MOD_MEM1 : X86_MOD_MEM4;
10828	pbCodeBuf[off++] = X86_MODRM_MAKE(bMod, idxRegRet & 7, 4 /SIB/);
10829	pbCodeBuf[off++] = X86_SIB_MAKE(idxRegBase & 7, idxRegIndex & 7, cShiftIndex);
10830	if (bMod != X86_MOD_MEM0)
10831	{
10832	pbCodeBuf[off++] = RT_BYTE1(u32EffAddr);
10833	if (bMod == X86_MOD_MEM4)
10834	{
10835	pbCodeBuf[off++] = RT_BYTE2(u32EffAddr);
10836	pbCodeBuf[off++] = RT_BYTE3(u32EffAddr);
10837	pbCodeBuf[off++] = RT_BYTE4(u32EffAddr);
10838	}
10839	}
10840	}
10841	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
10842	}
10843
10844	if (!bFinalAdj)
10845	{ /* likely */ }
10846	else
10847	{
10848	Assert(f64Bit);
10849	off = iemNativeEmitAddGprImm8(pReNative, off, idxRegRet, bFinalAdj);
10850	}
10851
10852	#elif defined(RT_ARCH_ARM64)
10853	if (i64EffAddr == 0)
10854	{
10855	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
10856	if (idxRegIndex == UINT8_MAX)
10857	pu32CodeBuf[off++] = Armv8A64MkInstrMov(idxRegRet, idxRegBase, f64Bit);
10858	else if (idxRegBase != UINT8_MAX)
10859	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubReg(false /fSub/, idxRegRet, idxRegBase, idxRegIndex,
10860	f64Bit, false /fSetFlags/, cShiftIndex);
10861	else
10862	{
10863	Assert(cShiftIndex != 0); /* See base = index swap above when shift is 0 and we have no base reg. */
10864	pu32CodeBuf[off++] = Armv8A64MkInstrLslImm(idxRegRet, idxRegIndex, cShiftIndex, f64Bit);
10865	}
10866	}
10867	else
10868	{
10869	if (f64Bit)
10870	{ /* likely */ }
10871	else
10872	i64EffAddr = (int32_t)i64EffAddr;
10873
10874	if (i64EffAddr < 4096 && i64EffAddr >= 0 && idxRegBase != UINT8_MAX)
10875	{
10876	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
10877	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(false /fSub/, idxRegRet, idxRegBase, i64EffAddr, f64Bit);
10878	}
10879	else if (i64EffAddr > -4096 && i64EffAddr < 0 && idxRegBase != UINT8_MAX)
10880	{
10881	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
10882	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubUImm12(true /fSub/, idxRegRet, idxRegBase, (uint32_t)-i64EffAddr, f64Bit);
10883	}
10884	else
10885	{
10886	if (f64Bit)
10887	off = iemNativeEmitLoadGprImm64(pReNative, off, idxRegRet, i64EffAddr);
10888	else
10889	off = iemNativeEmitLoadGprImm64(pReNative, off, idxRegRet, (uint32_t)i64EffAddr);
10890	if (idxRegBase != UINT8_MAX)
10891	{
10892	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
10893	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubReg(false /fSub/, idxRegRet, idxRegRet, idxRegBase, f64Bit);
10894	}
10895	}
10896	if (idxRegIndex != UINT8_MAX)
10897	{
10898	uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
10899	pu32CodeBuf[off++] = Armv8A64MkInstrAddSubReg(false /fSub/, idxRegRet, idxRegRet, idxRegIndex,
10900	f64Bit, false /fSetFlags/, cShiftIndex);
10901	}
10902	}
10903
10904	#else
10905	# error "port me"
10906	#endif
10907
10908	if (idxRegIndex != UINT8_MAX)
10909	iemNativeRegFreeTmp(pReNative, idxRegIndex);
10910	if (idxRegBase != UINT8_MAX)
10911	iemNativeRegFreeTmp(pReNative, idxRegBase);
10912	iemNativeVarRegisterRelease(pReNative, idxVarRet);
10913	return off;
10914	}
10915
10916
10917	/*********************************************************************************************************************************
10918	* TLB Lookup. *
10919	*********************************************************************************************************************************/
10920
10921	/**
10922	* This is called via iemNativeHlpAsmSafeWrapCheckTlbLookup.
10923	*/
10924	DECLASM(void) iemNativeHlpCheckTlbLookup(PVMCPU pVCpu, uintptr_t uResult, uint64_t GCPtr, uint32_t uSegAndSizeAndAccess)
10925	{
10926	uint8_t const iSegReg = RT_BYTE1(uSegAndSizeAndAccess);
10927	uint8_t const cbMem = RT_BYTE2(uSegAndSizeAndAccess);
10928	uint32_t const fAccess = uSegAndSizeAndAccess >> 16;
10929	Log(("iemNativeHlpCheckTlbLookup: %x:%#RX64 LB %#x fAccess=%#x -> %#RX64\n", iSegReg, GCPtr, cbMem, fAccess, uResult));
10930
10931	/* Do the lookup manually. */
10932	RTGCPTR const GCPtrFlat = iSegReg == UINT8_MAX ? GCPtr : GCPtr + pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base;
10933	uint64_t const uTag = IEMTLB_CALC_TAG( &pVCpu->iem.s.DataTlb, GCPtrFlat);
10934	PIEMTLBENTRY const pTlbe = IEMTLB_TAG_TO_ENTRY(&pVCpu->iem.s.DataTlb, uTag);
10935	if (RT_LIKELY(pTlbe->uTag == uTag))
10936	{
10937	/*
10938	* Check TLB page table level access flags.
10939	*/
10940	AssertCompile(IEMTLBE_F_PT_NO_USER == 4);
10941	uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER;
10942	uint64_t const fNoWriteNoDirty = !(fAccess & IEM_ACCESS_TYPE_WRITE) ? 0
10943	: IEMTLBE_F_PT_NO_WRITE \| IEMTLBE_F_PT_NO_DIRTY \| IEMTLBE_F_PG_NO_WRITE;
10944	uint64_t const fFlagsAndPhysRev = pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PHYS_REV \| IEMTLBE_F_NO_MAPPINGR3
10945	\| IEMTLBE_F_PG_UNASSIGNED
10946	\| IEMTLBE_F_PT_NO_ACCESSED
10947	\| fNoWriteNoDirty \| fNoUser);
10948	uint64_t const uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev;
10949	if (RT_LIKELY(fFlagsAndPhysRev == uTlbPhysRev))
10950	{
10951	/*
10952	* Return the address.
10953	*/
10954	uint8_t const * const pbAddr = &pTlbe->pbMappingR3[GCPtrFlat & GUEST_PAGE_OFFSET_MASK];
10955	if ((uintptr_t)pbAddr == uResult)
10956	return;
10957	RT_NOREF(cbMem);
10958	AssertFailed();
10959	}
10960	else
10961	AssertMsgFailed(("fFlagsAndPhysRev=%#RX64 vs uTlbPhysRev=%#RX64: %#RX64\n",
10962	fFlagsAndPhysRev, uTlbPhysRev, fFlagsAndPhysRev ^ uTlbPhysRev));
10963	}
10964	else
10965	AssertFailed();
10966	RT_BREAKPOINT();
10967	}
10968
10969	/* The rest of the code is in IEMN8veRecompilerTlbLookup.h. */
10970
10971
10972	/*********************************************************************************************************************************
10973	* Memory fetches and stores common *
10974	*********************************************************************************************************************************/
10975
10976	typedef enum IEMNATIVEMITMEMOP
10977	{
10978	kIemNativeEmitMemOp_Store = 0,
10979	kIemNativeEmitMemOp_Fetch,
10980	kIemNativeEmitMemOp_Fetch_Zx_U16,
10981	kIemNativeEmitMemOp_Fetch_Zx_U32,
10982	kIemNativeEmitMemOp_Fetch_Zx_U64,
10983	kIemNativeEmitMemOp_Fetch_Sx_U16,
10984	kIemNativeEmitMemOp_Fetch_Sx_U32,
10985	kIemNativeEmitMemOp_Fetch_Sx_U64
10986	} IEMNATIVEMITMEMOP;
10987
10988	/** Emits code for IEM_MC_FETCH_MEM_U8/16/32/64 and IEM_MC_STORE_MEM_U8/16/32/64,
10989	* and IEM_MC_FETCH_MEM_FLAT_U8/16/32/64 and IEM_MC_STORE_MEM_FLAT_U8/16/32/64
10990	* (with iSegReg = UINT8_MAX). */
10991	DECL_INLINE_THROW(uint32_t)
10992	iemNativeEmitMemFetchStoreDataCommon(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarValue, uint8_t iSegReg,
10993	uint8_t idxVarGCPtrMem, uint8_t cbMem, uint8_t fAlignMask, IEMNATIVEMITMEMOP enmOp,
10994	uintptr_t pfnFunction, uint8_t idxInstr, uint8_t offDisp = 0)
10995	{
10996	/*
10997	* Assert sanity.
10998	*/
10999	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarValue);
11000	Assert( enmOp != kIemNativeEmitMemOp_Store
11001	\|\| pReNative->Core.aVars[idxVarValue].enmKind == kIemNativeVarKind_Immediate
11002	\|\| pReNative->Core.aVars[idxVarValue].enmKind == kIemNativeVarKind_Stack);
11003	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarGCPtrMem);
11004	AssertStmt( pReNative->Core.aVars[idxVarGCPtrMem].enmKind == kIemNativeVarKind_Immediate
11005	\|\| pReNative->Core.aVars[idxVarGCPtrMem].enmKind == kIemNativeVarKind_Stack,
11006	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_UNEXPECTED_KIND));
11007	Assert(iSegReg < 6 \|\| iSegReg == UINT8_MAX);
11008	Assert(cbMem == 1 \|\| cbMem == 2 \|\| cbMem == 4 \|\| cbMem == 8);
11009	AssertCompile(IEMNATIVE_CALL_ARG_GREG_COUNT >= 4);
11010	#ifdef VBOX_STRICT
11011	if (iSegReg == UINT8_MAX)
11012	{
11013	Assert( (pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT
11014	\|\| (pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT
11015	\|\| (pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT);
11016	switch (cbMem)
11017	{
11018	case 1:
11019	Assert( pfnFunction
11020	== ( enmOp == kIemNativeEmitMemOp_Store ? (uintptr_t)iemNativeHlpMemFlatStoreDataU8
11021	: enmOp == kIemNativeEmitMemOp_Fetch ? (uintptr_t)iemNativeHlpMemFlatFetchDataU8
11022	: enmOp == kIemNativeEmitMemOp_Fetch_Zx_U16 ? (uintptr_t)iemNativeHlpMemFlatFetchDataU8
11023	: enmOp == kIemNativeEmitMemOp_Fetch_Zx_U32 ? (uintptr_t)iemNativeHlpMemFlatFetchDataU8
11024	: enmOp == kIemNativeEmitMemOp_Fetch_Zx_U64 ? (uintptr_t)iemNativeHlpMemFlatFetchDataU8
11025	: enmOp == kIemNativeEmitMemOp_Fetch_Sx_U16 ? (uintptr_t)iemNativeHlpMemFlatFetchDataU8_Sx_U16
11026	: enmOp == kIemNativeEmitMemOp_Fetch_Sx_U32 ? (uintptr_t)iemNativeHlpMemFlatFetchDataU8_Sx_U32
11027	: enmOp == kIemNativeEmitMemOp_Fetch_Sx_U64 ? (uintptr_t)iemNativeHlpMemFlatFetchDataU8_Sx_U64
11028	: UINT64_C(0xc000b000a0009000) ));
11029	break;
11030	case 2:
11031	Assert( pfnFunction
11032	== ( enmOp == kIemNativeEmitMemOp_Store ? (uintptr_t)iemNativeHlpMemFlatStoreDataU16
11033	: enmOp == kIemNativeEmitMemOp_Fetch ? (uintptr_t)iemNativeHlpMemFlatFetchDataU16
11034	: enmOp == kIemNativeEmitMemOp_Fetch_Zx_U32 ? (uintptr_t)iemNativeHlpMemFlatFetchDataU16
11035	: enmOp == kIemNativeEmitMemOp_Fetch_Zx_U64 ? (uintptr_t)iemNativeHlpMemFlatFetchDataU16
11036	: enmOp == kIemNativeEmitMemOp_Fetch_Sx_U32 ? (uintptr_t)iemNativeHlpMemFlatFetchDataU16_Sx_U32
11037	: enmOp == kIemNativeEmitMemOp_Fetch_Sx_U64 ? (uintptr_t)iemNativeHlpMemFlatFetchDataU16_Sx_U64
11038	: UINT64_C(0xc000b000a0009000) ));
11039	break;
11040	case 4:
11041	Assert( pfnFunction
11042	== ( enmOp == kIemNativeEmitMemOp_Store ? (uintptr_t)iemNativeHlpMemFlatStoreDataU32
11043	: enmOp == kIemNativeEmitMemOp_Fetch ? (uintptr_t)iemNativeHlpMemFlatFetchDataU32
11044	: enmOp == kIemNativeEmitMemOp_Fetch_Zx_U64 ? (uintptr_t)iemNativeHlpMemFlatFetchDataU32
11045	: enmOp == kIemNativeEmitMemOp_Fetch_Sx_U64 ? (uintptr_t)iemNativeHlpMemFlatFetchDataU32_Sx_U64
11046	: UINT64_C(0xc000b000a0009000) ));
11047	break;
11048	case 8:
11049	Assert( pfnFunction
11050	== ( enmOp == kIemNativeEmitMemOp_Store ? (uintptr_t)iemNativeHlpMemFlatStoreDataU64
11051	: enmOp == kIemNativeEmitMemOp_Fetch ? (uintptr_t)iemNativeHlpMemFlatFetchDataU64
11052	: UINT64_C(0xc000b000a0009000) ));
11053	break;
11054	}
11055	}
11056	else
11057	{
11058	Assert(iSegReg < 6);
11059	switch (cbMem)
11060	{
11061	case 1:
11062	Assert( pfnFunction
11063	== ( enmOp == kIemNativeEmitMemOp_Store ? (uintptr_t)iemNativeHlpMemStoreDataU8
11064	: enmOp == kIemNativeEmitMemOp_Fetch ? (uintptr_t)iemNativeHlpMemFetchDataU8
11065	: enmOp == kIemNativeEmitMemOp_Fetch_Zx_U16 ? (uintptr_t)iemNativeHlpMemFetchDataU8
11066	: enmOp == kIemNativeEmitMemOp_Fetch_Zx_U32 ? (uintptr_t)iemNativeHlpMemFetchDataU8
11067	: enmOp == kIemNativeEmitMemOp_Fetch_Zx_U64 ? (uintptr_t)iemNativeHlpMemFetchDataU8
11068	: enmOp == kIemNativeEmitMemOp_Fetch_Sx_U16 ? (uintptr_t)iemNativeHlpMemFetchDataU8_Sx_U16
11069	: enmOp == kIemNativeEmitMemOp_Fetch_Sx_U32 ? (uintptr_t)iemNativeHlpMemFetchDataU8_Sx_U32
11070	: enmOp == kIemNativeEmitMemOp_Fetch_Sx_U64 ? (uintptr_t)iemNativeHlpMemFetchDataU8_Sx_U64
11071	: UINT64_C(0xc000b000a0009000) ));
11072	break;
11073	case 2:
11074	Assert( pfnFunction
11075	== ( enmOp == kIemNativeEmitMemOp_Store ? (uintptr_t)iemNativeHlpMemStoreDataU16
11076	: enmOp == kIemNativeEmitMemOp_Fetch ? (uintptr_t)iemNativeHlpMemFetchDataU16
11077	: enmOp == kIemNativeEmitMemOp_Fetch_Zx_U32 ? (uintptr_t)iemNativeHlpMemFetchDataU16
11078	: enmOp == kIemNativeEmitMemOp_Fetch_Zx_U64 ? (uintptr_t)iemNativeHlpMemFetchDataU16
11079	: enmOp == kIemNativeEmitMemOp_Fetch_Sx_U32 ? (uintptr_t)iemNativeHlpMemFetchDataU16_Sx_U32
11080	: enmOp == kIemNativeEmitMemOp_Fetch_Sx_U64 ? (uintptr_t)iemNativeHlpMemFetchDataU16_Sx_U64
11081	: UINT64_C(0xc000b000a0009000) ));
11082	break;
11083	case 4:
11084	Assert( pfnFunction
11085	== ( enmOp == kIemNativeEmitMemOp_Store ? (uintptr_t)iemNativeHlpMemStoreDataU32
11086	: enmOp == kIemNativeEmitMemOp_Fetch ? (uintptr_t)iemNativeHlpMemFetchDataU32
11087	: enmOp == kIemNativeEmitMemOp_Fetch_Zx_U64 ? (uintptr_t)iemNativeHlpMemFetchDataU32
11088	: enmOp == kIemNativeEmitMemOp_Fetch_Sx_U64 ? (uintptr_t)iemNativeHlpMemFetchDataU32_Sx_U64
11089	: UINT64_C(0xc000b000a0009000) ));
11090	break;
11091	case 8:
11092	Assert( pfnFunction
11093	== ( enmOp == kIemNativeEmitMemOp_Store ? (uintptr_t)iemNativeHlpMemStoreDataU64
11094	: enmOp == kIemNativeEmitMemOp_Fetch ? (uintptr_t)iemNativeHlpMemFetchDataU64
11095	: UINT64_C(0xc000b000a0009000) ));
11096	break;
11097	}
11098	}
11099	#endif
11100
11101	#ifdef VBOX_STRICT
11102	/*
11103	* Check that the fExec flags we've got make sense.
11104	*/
11105	off = iemNativeEmitExecFlagsCheck(pReNative, off, pReNative->fExec);
11106	#endif
11107
11108	/*
11109	* To keep things simple we have to commit any pending writes first as we
11110	* may end up making calls.
11111	*/
11112	/** @todo we could postpone this till we make the call and reload the
11113	* registers after returning from the call. Not sure if that's sensible or
11114	* not, though. */
11115	off = iemNativeRegFlushPendingWrites(pReNative, off);
11116
11117	#ifdef IEMNATIVE_WITH_FREE_AND_FLUSH_VOLATILE_REGS_AT_TLB_LOOKUP
11118	/*
11119	* Move/spill/flush stuff out of call-volatile registers.
11120	* This is the easy way out. We could contain this to the tlb-miss branch
11121	* by saving and restoring active stuff here.
11122	*/
11123	off = iemNativeRegMoveAndFreeAndFlushAtCall(pReNative, off, 0 /* vacate all non-volatile regs */);
11124	#endif
11125
11126	/*
11127	* Define labels and allocate the result register (trying for the return
11128	* register if we can).
11129	*/
11130	uint16_t const uTlbSeqNo = pReNative->uTlbSeqNo++;
11131	uint8_t const idxRegValueFetch = enmOp == kIemNativeEmitMemOp_Store ? UINT8_MAX
11132	: !(pReNative->Core.bmHstRegs & RT_BIT_32(IEMNATIVE_CALL_RET_GREG))
11133	? iemNativeVarRegisterSetAndAcquire(pReNative, idxVarValue, IEMNATIVE_CALL_RET_GREG, &off)
11134	: iemNativeVarRegisterAcquire(pReNative, idxVarValue, &off);
11135	IEMNATIVEEMITTLBSTATE const TlbState(pReNative, &off, idxVarGCPtrMem, iSegReg, cbMem, offDisp);
11136	uint8_t const idxRegValueStore = !TlbState.fSkip
11137	&& enmOp == kIemNativeEmitMemOp_Store
11138	&& pReNative->Core.aVars[idxVarValue].enmKind != kIemNativeVarKind_Immediate
11139	? iemNativeVarRegisterAcquire(pReNative, idxVarValue, &off)
11140	: UINT8_MAX;
11141	uint32_t const idxRegMemResult = !TlbState.fSkip ? iemNativeRegAllocTmp(pReNative, &off) : UINT8_MAX;
11142	uint32_t const idxLabelTlbLookup = !TlbState.fSkip
11143	? iemNativeLabelCreate(pReNative, kIemNativeLabelType_TlbLookup, UINT32_MAX, uTlbSeqNo)
11144	: UINT32_MAX;
11145
11146	/*
11147	* Jump to the TLB lookup code.
11148	*/
11149	if (!TlbState.fSkip)
11150	off = iemNativeEmitJmpToLabel(pReNative, off, idxLabelTlbLookup); /** @todo short jump */
11151
11152	/*
11153	* TlbMiss:
11154	*
11155	* Call helper to do the fetching.
11156	* We flush all guest register shadow copies here.
11157	*/
11158	uint32_t const idxLabelTlbMiss = iemNativeLabelCreate(pReNative, kIemNativeLabelType_TlbMiss, off, uTlbSeqNo);
11159
11160	#ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
11161	off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr));
11162	#else
11163	RT_NOREF(idxInstr);
11164	#endif
11165
11166	#ifndef IEMNATIVE_WITH_FREE_AND_FLUSH_VOLATILE_REGS_AT_TLB_LOOKUP
11167	/* Save variables in volatile registers. */
11168	uint32_t const fHstRegsNotToSave = TlbState.getRegsNotToSave()
11169	\| (idxRegMemResult != UINT8_MAX ? RT_BIT_32(idxRegMemResult) : 0)
11170	\| (idxRegValueFetch != UINT8_MAX ? RT_BIT_32(idxRegValueFetch) : 0);
11171	off = iemNativeVarSaveVolatileRegsPreHlpCall(pReNative, off, fHstRegsNotToSave);
11172	#endif
11173
11174	/* IEMNATIVE_CALL_ARG2/3_GREG = uValue (idxVarValue) - if store */
11175	uint32_t fVolGregMask = IEMNATIVE_CALL_VOLATILE_GREG_MASK;
11176	if (enmOp == kIemNativeEmitMemOp_Store)
11177	{
11178	uint8_t const idxRegArgValue = iSegReg == UINT8_MAX ? IEMNATIVE_CALL_ARG2_GREG : IEMNATIVE_CALL_ARG3_GREG;
11179	off = iemNativeEmitLoadArgGregFromImmOrStackVar(pReNative, off, idxRegArgValue, idxVarValue, 0 /cbAppend/,
11180	#ifdef IEMNATIVE_WITH_FREE_AND_FLUSH_VOLATILE_REGS_AT_TLB_LOOKUP
11181	IEMNATIVE_CALL_VOLATILE_GREG_MASK);
11182	#else
11183	IEMNATIVE_CALL_VOLATILE_GREG_MASK, true /fSpilledVarsInvolatileRegs/);
11184	fVolGregMask &= ~RT_BIT_32(idxRegArgValue);
11185	#endif
11186	}
11187
11188	/* IEMNATIVE_CALL_ARG1_GREG = GCPtrMem */
11189	off = iemNativeEmitLoadArgGregFromImmOrStackVar(pReNative, off, IEMNATIVE_CALL_ARG1_GREG, idxVarGCPtrMem, offDisp /cbAppend/,
11190	#ifdef IEMNATIVE_WITH_FREE_AND_FLUSH_VOLATILE_REGS_AT_TLB_LOOKUP
11191	fVolGregMask);
11192	#else
11193	fVolGregMask, true /fSpilledVarsInvolatileRegs/);
11194	#endif
11195
11196	if (iSegReg != UINT8_MAX)
11197	{
11198	/* IEMNATIVE_CALL_ARG2_GREG = iSegReg */
11199	AssertStmt(iSegReg < 6, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_EMIT_BAD_SEG_REG_NO));
11200	off = iemNativeEmitLoadGpr8Imm(pReNative, off, IEMNATIVE_CALL_ARG2_GREG, iSegReg);
11201	}
11202
11203	/* IEMNATIVE_CALL_ARG0_GREG = pVCpu */
11204	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
11205
11206	/* Done setting up parameters, make the call. */
11207	off = iemNativeEmitCallImm(pReNative, off, pfnFunction);
11208
11209	/*
11210	* Put the result in the right register if this is a fetch.
11211	*/
11212	if (enmOp != kIemNativeEmitMemOp_Store)
11213	{
11214	Assert(idxRegValueFetch == pReNative->Core.aVars[idxVarValue].idxReg);
11215	if (idxRegValueFetch != IEMNATIVE_CALL_RET_GREG)
11216	off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxRegValueFetch, IEMNATIVE_CALL_RET_GREG);
11217	}
11218
11219	#ifndef IEMNATIVE_WITH_FREE_AND_FLUSH_VOLATILE_REGS_AT_TLB_LOOKUP
11220	/* Restore variables and guest shadow registers to volatile registers. */
11221	off = iemNativeVarRestoreVolatileRegsPostHlpCall(pReNative, off, fHstRegsNotToSave);
11222	off = iemNativeRegRestoreGuestShadowsInVolatileRegs(pReNative, off, TlbState.getActiveRegsWithShadows());
11223	#endif
11224
11225	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
11226	if (!TlbState.fSkip)
11227	{
11228	/* end of TlbMiss - Jump to the done label. */
11229	uint32_t const idxLabelTlbDone = iemNativeLabelCreate(pReNative, kIemNativeLabelType_TlbDone, UINT32_MAX, uTlbSeqNo);
11230	off = iemNativeEmitJmpToLabel(pReNative, off, idxLabelTlbDone);
11231
11232	/*
11233	* TlbLookup:
11234	*/
11235	off = iemNativeEmitTlbLookup<true>(pReNative, off, &TlbState, iSegReg, cbMem, fAlignMask,
11236	enmOp == kIemNativeEmitMemOp_Store ? IEM_ACCESS_TYPE_WRITE : IEM_ACCESS_TYPE_READ,
11237	idxLabelTlbLookup, idxLabelTlbMiss, idxRegMemResult, offDisp);
11238
11239	/*
11240	* Emit code to do the actual storing / fetching.
11241	*/
11242	PIEMNATIVEINSTR pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 64);
11243	# ifdef VBOX_WITH_STATISTICS
11244	off = iemNativeEmitIncStamCounterInVCpuEx(pCodeBuf, off, TlbState.idxReg1, TlbState.idxReg2,
11245	enmOp == kIemNativeEmitMemOp_Store
11246	? RT_UOFFSETOF(VMCPUCC, iem.s.StatNativeTlbHitsForFetch)
11247	: RT_UOFFSETOF(VMCPUCC, iem.s.StatNativeTlbHitsForStore));
11248	# endif
11249	switch (enmOp)
11250	{
11251	case kIemNativeEmitMemOp_Store:
11252	if (pReNative->Core.aVars[idxVarValue].enmKind != kIemNativeVarKind_Immediate)
11253	{
11254	switch (cbMem)
11255	{
11256	case 1:
11257	off = iemNativeEmitStoreGpr8ByGprEx(pCodeBuf, off, idxRegValueStore, idxRegMemResult);
11258	break;
11259	case 2:
11260	off = iemNativeEmitStoreGpr16ByGprEx(pCodeBuf, off, idxRegValueStore, idxRegMemResult);
11261	break;
11262	case 4:
11263	off = iemNativeEmitStoreGpr32ByGprEx(pCodeBuf, off, idxRegValueStore, idxRegMemResult);
11264	break;
11265	case 8:
11266	off = iemNativeEmitStoreGpr64ByGprEx(pCodeBuf, off, idxRegValueStore, idxRegMemResult);
11267	break;
11268	default:
11269	AssertFailed();
11270	}
11271	}
11272	else
11273	{
11274	switch (cbMem)
11275	{
11276	case 1:
11277	off = iemNativeEmitStoreImm8ByGprEx(pCodeBuf, off,
11278	(uint8_t)pReNative->Core.aVars[idxVarValue].u.uValue,
11279	idxRegMemResult, TlbState.idxReg1);
11280	break;
11281	case 2:
11282	off = iemNativeEmitStoreImm16ByGprEx(pCodeBuf, off,
11283	(uint16_t)pReNative->Core.aVars[idxVarValue].u.uValue,
11284	idxRegMemResult, TlbState.idxReg1);
11285	break;
11286	case 4:
11287	off = iemNativeEmitStoreImm32ByGprEx(pCodeBuf, off,
11288	(uint32_t)pReNative->Core.aVars[idxVarValue].u.uValue,
11289	idxRegMemResult, TlbState.idxReg1);
11290	break;
11291	case 8:
11292	off = iemNativeEmitStoreImm64ByGprEx(pCodeBuf, off, pReNative->Core.aVars[idxVarValue].u.uValue,
11293	idxRegMemResult, TlbState.idxReg1);
11294	break;
11295	default:
11296	AssertFailed();
11297	}
11298	}
11299	break;
11300
11301	case kIemNativeEmitMemOp_Fetch:
11302	case kIemNativeEmitMemOp_Fetch_Zx_U16:
11303	case kIemNativeEmitMemOp_Fetch_Zx_U32:
11304	case kIemNativeEmitMemOp_Fetch_Zx_U64:
11305	switch (cbMem)
11306	{
11307	case 1:
11308	off = iemNativeEmitLoadGprByGprU8Ex(pCodeBuf, off, idxRegValueFetch, idxRegMemResult);
11309	break;
11310	case 2:
11311	off = iemNativeEmitLoadGprByGprU16Ex(pCodeBuf, off, idxRegValueFetch, idxRegMemResult);
11312	break;
11313	case 4:
11314	off = iemNativeEmitLoadGprByGprU32Ex(pCodeBuf, off, idxRegValueFetch, idxRegMemResult);
11315	break;
11316	case 8:
11317	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, idxRegValueFetch, idxRegMemResult);
11318	break;
11319	default:
11320	AssertFailed();
11321	}
11322	break;
11323
11324	case kIemNativeEmitMemOp_Fetch_Sx_U16:
11325	Assert(cbMem == 1);
11326	off = iemNativeEmitLoadGprByGprU16SignExtendedFromS8Ex(pCodeBuf, off, idxRegValueFetch, idxRegMemResult);
11327	break;
11328
11329	case kIemNativeEmitMemOp_Fetch_Sx_U32:
11330	Assert(cbMem == 1 \|\| cbMem == 2);
11331	if (cbMem == 1)
11332	off = iemNativeEmitLoadGprByGprU32SignExtendedFromS8Ex(pCodeBuf, off, idxRegValueFetch, idxRegMemResult);
11333	else
11334	off = iemNativeEmitLoadGprByGprU32SignExtendedFromS16Ex(pCodeBuf, off, idxRegValueFetch, idxRegMemResult);
11335	break;
11336
11337	case kIemNativeEmitMemOp_Fetch_Sx_U64:
11338	switch (cbMem)
11339	{
11340	case 1:
11341	off = iemNativeEmitLoadGprByGprU64SignExtendedFromS8Ex(pCodeBuf, off, idxRegValueFetch, idxRegMemResult);
11342	break;
11343	case 2:
11344	off = iemNativeEmitLoadGprByGprU64SignExtendedFromS16Ex(pCodeBuf, off, idxRegValueFetch, idxRegMemResult);
11345	break;
11346	case 4:
11347	off = iemNativeEmitLoadGprByGprU64SignExtendedFromS32Ex(pCodeBuf, off, idxRegValueFetch, idxRegMemResult);
11348	break;
11349	default:
11350	AssertFailed();
11351	}
11352	break;
11353
11354	default:
11355	AssertFailed();
11356	}
11357
11358	iemNativeRegFreeTmp(pReNative, idxRegMemResult);
11359
11360	/*
11361	* TlbDone:
11362	*/
11363	iemNativeLabelDefine(pReNative, idxLabelTlbDone, off);
11364
11365	TlbState.freeRegsAndReleaseVars(pReNative, idxVarGCPtrMem);
11366
11367	# ifndef IEMNATIVE_WITH_FREE_AND_FLUSH_VOLATILE_REGS_AT_TLB_LOOKUP
11368	/* Temp Hack: Flush all guest shadows in volatile registers in case of TLB miss. */
11369	iemNativeRegFlushGuestShadowsByHostMask(pReNative, IEMNATIVE_CALL_VOLATILE_GREG_MASK);
11370	# endif
11371	}
11372	#else
11373	RT_NOREF(fAlignMask, idxLabelTlbMiss);
11374	#endif
11375
11376	if (idxRegValueFetch != UINT8_MAX \|\| idxRegValueStore != UINT8_MAX)
11377	iemNativeVarRegisterRelease(pReNative, idxVarValue);
11378	return off;
11379	}
11380
11381
11382
11383	/*********************************************************************************************************************************
11384	* Memory fetches (IEM_MEM_FETCH_XXX). *
11385	*********************************************************************************************************************************/
11386
11387	/* 8-bit segmented: */
11388	#define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
11389	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u8Dst, a_iSeg, a_GCPtrMem, \
11390	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch, \
11391	(uintptr_t)iemNativeHlpMemFetchDataU8, pCallEntry->idxInstr)
11392
11393	#define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
11394	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u16Dst, a_iSeg, a_GCPtrMem, \
11395	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch_Zx_U16, \
11396	(uintptr_t)iemNativeHlpMemFetchDataU8, pCallEntry->idxInstr)
11397
11398	#define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
11399	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Dst, a_iSeg, a_GCPtrMem, \
11400	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch_Zx_U32, \
11401	(uintptr_t)iemNativeHlpMemFetchDataU8, pCallEntry->idxInstr)
11402
11403	#define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
11404	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, a_iSeg, a_GCPtrMem, \
11405	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch_Zx_U64, \
11406	(uintptr_t)iemNativeHlpMemFetchDataU8, pCallEntry->idxInstr)
11407
11408	#define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
11409	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u16Dst, a_iSeg, a_GCPtrMem, \
11410	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch_Sx_U16, \
11411	(uintptr_t)iemNativeHlpMemFetchDataU8_Sx_U16, pCallEntry->idxInstr)
11412
11413	#define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
11414	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Dst, a_iSeg, a_GCPtrMem, \
11415	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch_Sx_U32, \
11416	(uintptr_t)iemNativeHlpMemFetchDataU8_Sx_U32, pCallEntry->idxInstr)
11417
11418	#define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
11419	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, a_iSeg, a_GCPtrMem, \
11420	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch_Sx_U64, \
11421	(uintptr_t)iemNativeHlpMemFetchDataU8_Sx_U64, pCallEntry->idxInstr)
11422
11423	/* 16-bit segmented: */
11424	#define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
11425	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u16Dst, a_iSeg, a_GCPtrMem, \
11426	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Fetch, \
11427	(uintptr_t)iemNativeHlpMemFetchDataU16, pCallEntry->idxInstr)
11428
11429	#define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
11430	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u16Dst, a_iSeg, a_GCPtrMem, \
11431	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Fetch, \
11432	(uintptr_t)iemNativeHlpMemFetchDataU16, pCallEntry->idxInstr, a_offDisp)
11433
11434	#define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
11435	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Dst, a_iSeg, a_GCPtrMem, \
11436	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Fetch_Zx_U32, \
11437	(uintptr_t)iemNativeHlpMemFetchDataU16, pCallEntry->idxInstr)
11438
11439	#define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
11440	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, a_iSeg, a_GCPtrMem, \
11441	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Fetch_Zx_U64, \
11442	(uintptr_t)iemNativeHlpMemFetchDataU16, pCallEntry->idxInstr)
11443
11444	#define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
11445	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Dst, a_iSeg, a_GCPtrMem, \
11446	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Fetch_Sx_U32, \
11447	(uintptr_t)iemNativeHlpMemFetchDataU16_Sx_U32, pCallEntry->idxInstr)
11448
11449	#define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
11450	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, a_iSeg, a_GCPtrMem, \
11451	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Fetch_Sx_U64, \
11452	(uintptr_t)iemNativeHlpMemFetchDataU16_Sx_U64, pCallEntry->idxInstr)
11453
11454
11455	/* 32-bit segmented: */
11456	#define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
11457	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Dst, a_iSeg, a_GCPtrMem, \
11458	sizeof(uint32_t), sizeof(uint32_t) - 1, kIemNativeEmitMemOp_Fetch, \
11459	(uintptr_t)iemNativeHlpMemFetchDataU32, pCallEntry->idxInstr)
11460
11461	#define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
11462	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Dst, a_iSeg, a_GCPtrMem, \
11463	sizeof(uint32_t), sizeof(uint32_t) - 1, kIemNativeEmitMemOp_Fetch, \
11464	(uintptr_t)iemNativeHlpMemFetchDataU32, pCallEntry->idxInstr, a_offDisp)
11465
11466	#define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
11467	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, a_iSeg, a_GCPtrMem, \
11468	sizeof(uint32_t), sizeof(uint32_t) - 1, kIemNativeEmitMemOp_Fetch_Zx_U64, \
11469	(uintptr_t)iemNativeHlpMemFetchDataU32, pCallEntry->idxInstr)
11470
11471	#define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
11472	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, a_iSeg, a_GCPtrMem, \
11473	sizeof(uint32_t), sizeof(uint32_t) - 1, kIemNativeEmitMemOp_Fetch_Sx_U64, \
11474	(uintptr_t)iemNativeHlpMemFetchDataU32_Sx_U64, pCallEntry->idxInstr)
11475
11476
11477	/* 64-bit segmented: */
11478	#define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
11479	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, a_iSeg, a_GCPtrMem, \
11480	sizeof(uint64_t), sizeof(uint64_t) - 1, kIemNativeEmitMemOp_Fetch, \
11481	(uintptr_t)iemNativeHlpMemFetchDataU64, pCallEntry->idxInstr)
11482
11483
11484
11485	/* 8-bit flat: */
11486	#define IEM_MC_FETCH_MEM_FLAT_U8(a_u8Dst, a_GCPtrMem) \
11487	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u8Dst, UINT8_MAX, a_GCPtrMem, \
11488	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch, \
11489	(uintptr_t)iemNativeHlpMemFlatFetchDataU8, pCallEntry->idxInstr)
11490
11491	#define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U16(a_u16Dst, a_GCPtrMem) \
11492	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u16Dst, UINT8_MAX, a_GCPtrMem, \
11493	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch_Zx_U16, \
11494	(uintptr_t)iemNativeHlpMemFlatFetchDataU8, pCallEntry->idxInstr)
11495
11496	#define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U32(a_u32Dst, a_GCPtrMem) \
11497	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Dst, UINT8_MAX, a_GCPtrMem, \
11498	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch_Zx_U32, \
11499	(uintptr_t)iemNativeHlpMemFlatFetchDataU8, pCallEntry->idxInstr)
11500
11501	#define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U64(a_u64Dst, a_GCPtrMem) \
11502	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, UINT8_MAX, a_GCPtrMem, \
11503	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch_Zx_U64, \
11504	(uintptr_t)iemNativeHlpMemFlatFetchDataU8, pCallEntry->idxInstr)
11505
11506	#define IEM_MC_FETCH_MEM_FLAT_U8_SX_U16(a_u16Dst, a_GCPtrMem) \
11507	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u16Dst, UINT8_MAX, a_GCPtrMem, \
11508	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch_Sx_U16, \
11509	(uintptr_t)iemNativeHlpMemFlatFetchDataU8_Sx_U16, pCallEntry->idxInstr)
11510
11511	#define IEM_MC_FETCH_MEM_FLAT_U8_SX_U32(a_u32Dst, a_GCPtrMem) \
11512	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Dst, UINT8_MAX, a_GCPtrMem, \
11513	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch_Sx_U32, \
11514	(uintptr_t)iemNativeHlpMemFlatFetchDataU8_Sx_U32, pCallEntry->idxInstr)
11515
11516	#define IEM_MC_FETCH_MEM_FLAT_U8_SX_U64(a_u64Dst, a_GCPtrMem) \
11517	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, UINT8_MAX, a_GCPtrMem, \
11518	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Fetch_Sx_U64, \
11519	(uintptr_t)iemNativeHlpMemFlatFetchDataU8_Sx_U64, pCallEntry->idxInstr)
11520
11521
11522	/* 16-bit flat: */
11523	#define IEM_MC_FETCH_MEM_FLAT_U16(a_u16Dst, a_GCPtrMem) \
11524	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u16Dst, UINT8_MAX, a_GCPtrMem, \
11525	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Fetch, \
11526	(uintptr_t)iemNativeHlpMemFlatFetchDataU16, pCallEntry->idxInstr)
11527
11528	#define IEM_MC_FETCH_MEM_FLAT_U16_DISP(a_u16Dst, a_GCPtrMem, a_offDisp) \
11529	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u16Dst, UINT8_MAX, a_GCPtrMem, \
11530	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Fetch, \
11531	(uintptr_t)iemNativeHlpMemFlatFetchDataU16, pCallEntry->idxInstr, a_offDisp)
11532
11533	#define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U32(a_u32Dst, a_GCPtrMem) \
11534	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Dst, UINT8_MAX, a_GCPtrMem, \
11535	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Fetch_Zx_U32, \
11536	(uintptr_t)iemNativeHlpMemFlatFetchDataU16, pCallEntry->idxInstr)
11537
11538	#define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U64(a_u64Dst, a_GCPtrMem) \
11539	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, UINT8_MAX, a_GCPtrMem, \
11540	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Fetch_Zx_U64, \
11541	(uintptr_t)iemNativeHlpMemFlatFetchDataU16, pCallEntry->idxInstr)
11542
11543	#define IEM_MC_FETCH_MEM_FLAT_U16_SX_U32(a_u32Dst, a_GCPtrMem) \
11544	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Dst, UINT8_MAX, a_GCPtrMem, \
11545	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Fetch_Sx_U32, \
11546	(uintptr_t)iemNativeHlpMemFlatFetchDataU16_Sx_U32, pCallEntry->idxInstr)
11547
11548	#define IEM_MC_FETCH_MEM_FLAT_U16_SX_U64(a_u64Dst, a_GCPtrMem) \
11549	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, UINT8_MAX, a_GCPtrMem, \
11550	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Fetch_Sx_U64, \
11551	(uintptr_t)iemNativeHlpMemFlatFetchDataU16_Sx_U64, pCallEntry->idxInstr)
11552
11553	/* 32-bit flat: */
11554	#define IEM_MC_FETCH_MEM_FLAT_U32(a_u32Dst, a_GCPtrMem) \
11555	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Dst, UINT8_MAX, a_GCPtrMem, \
11556	sizeof(uint32_t), sizeof(uint32_t) - 1, kIemNativeEmitMemOp_Fetch, \
11557	(uintptr_t)iemNativeHlpMemFlatFetchDataU32, pCallEntry->idxInstr)
11558
11559	#define IEM_MC_FETCH_MEM_FLAT_U32_DISP(a_u32Dst, a_GCPtrMem, a_offDisp) \
11560	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Dst, UINT8_MAX, a_GCPtrMem, \
11561	sizeof(uint32_t), sizeof(uint32_t) - 1, kIemNativeEmitMemOp_Fetch, \
11562	(uintptr_t)iemNativeHlpMemFlatFetchDataU32, pCallEntry->idxInstr, a_offDisp)
11563
11564	#define IEM_MC_FETCH_MEM_FLAT_U32_ZX_U64(a_u64Dst, a_GCPtrMem) \
11565	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, UINT8_MAX, a_GCPtrMem, \
11566	sizeof(uint32_t), sizeof(uint32_t) - 1, kIemNativeEmitMemOp_Fetch_Zx_U64, \
11567	(uintptr_t)iemNativeHlpMemFlatFetchDataU32, pCallEntry->idxInstr)
11568
11569	#define IEM_MC_FETCH_MEM_FLAT_U32_SX_U64(a_u64Dst, a_GCPtrMem) \
11570	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, UINT8_MAX, a_GCPtrMem, \
11571	sizeof(uint32_t), sizeof(uint32_t) - 1, kIemNativeEmitMemOp_Fetch_Sx_U64, \
11572	(uintptr_t)iemNativeHlpMemFlatFetchDataU32_Sx_U64, pCallEntry->idxInstr)
11573
11574	/* 64-bit flat: */
11575	#define IEM_MC_FETCH_MEM_FLAT_U64(a_u64Dst, a_GCPtrMem) \
11576	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Dst, UINT8_MAX, a_GCPtrMem, \
11577	sizeof(uint64_t), sizeof(uint64_t) - 1, kIemNativeEmitMemOp_Fetch, \
11578	(uintptr_t)iemNativeHlpMemFlatFetchDataU64, pCallEntry->idxInstr)
11579
11580
11581
11582	/*********************************************************************************************************************************
11583	* Memory stores (IEM_MEM_STORE_XXX). *
11584	*********************************************************************************************************************************/
11585
11586	#define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
11587	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u8Value, a_iSeg, a_GCPtrMem, \
11588	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Store, \
11589	(uintptr_t)iemNativeHlpMemStoreDataU8, pCallEntry->idxInstr)
11590
11591	#define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
11592	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u16Value, a_iSeg, a_GCPtrMem, \
11593	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Store, \
11594	(uintptr_t)iemNativeHlpMemStoreDataU16, pCallEntry->idxInstr)
11595
11596	#define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
11597	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Value, a_iSeg, a_GCPtrMem, \
11598	sizeof(uint32_t), sizeof(uint32_t) - 1, kIemNativeEmitMemOp_Store, \
11599	(uintptr_t)iemNativeHlpMemStoreDataU32, pCallEntry->idxInstr)
11600
11601	#define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
11602	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Value, a_iSeg, a_GCPtrMem, \
11603	sizeof(uint64_t), sizeof(uint64_t) - 1, kIemNativeEmitMemOp_Store, \
11604	(uintptr_t)iemNativeHlpMemStoreDataU64, pCallEntry->idxInstr)
11605
11606
11607	#define IEM_MC_STORE_MEM_FLAT_U8(a_GCPtrMem, a_u8Value) \
11608	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u8Value, UINT8_MAX, a_GCPtrMem, \
11609	sizeof(uint8_t), 0 /fAlignMask/, kIemNativeEmitMemOp_Store, \
11610	(uintptr_t)iemNativeHlpMemFlatStoreDataU8, pCallEntry->idxInstr)
11611
11612	#define IEM_MC_STORE_MEM_FLAT_U16(a_GCPtrMem, a_u16Value) \
11613	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u16Value, UINT8_MAX, a_GCPtrMem, \
11614	sizeof(uint16_t), sizeof(uint16_t) - 1, kIemNativeEmitMemOp_Store, \
11615	(uintptr_t)iemNativeHlpMemFlatStoreDataU16, pCallEntry->idxInstr)
11616
11617	#define IEM_MC_STORE_MEM_FLAT_U32(a_GCPtrMem, a_u32Value) \
11618	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u32Value, UINT8_MAX, a_GCPtrMem, \
11619	sizeof(uint32_t), sizeof(uint32_t) - 1, kIemNativeEmitMemOp_Store, \
11620	(uintptr_t)iemNativeHlpMemFlatStoreDataU32, pCallEntry->idxInstr)
11621
11622	#define IEM_MC_STORE_MEM_FLAT_U64(a_GCPtrMem, a_u64Value) \
11623	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u64Value, UINT8_MAX, a_GCPtrMem, \
11624	sizeof(uint64_t), sizeof(uint64_t) - 1, kIemNativeEmitMemOp_Store, \
11625	(uintptr_t)iemNativeHlpMemFlatStoreDataU64, pCallEntry->idxInstr)
11626
11627
11628	#define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8ConstValue) \
11629	off = iemNativeEmitMemStoreConstDataCommon(pReNative, off, a_u8ConstValue, a_iSeg, a_GCPtrMem, sizeof(uint8_t), \
11630	(uintptr_t)iemNativeHlpMemStoreDataU8, pCallEntry->idxInstr)
11631
11632	#define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16ConstValue) \
11633	off = iemNativeEmitMemStoreConstDataCommon(pReNative, off, a_u16ConstValue, a_iSeg, a_GCPtrMem, sizeof(uint16_t), \
11634	(uintptr_t)iemNativeHlpMemStoreDataU16, pCallEntry->idxInstr)
11635
11636	#define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32ConstValue) \
11637	off = iemNativeEmitMemStoreConstDataCommon(pReNative, off, a_u32ConstValue, a_iSeg, a_GCPtrMem, sizeof(uint32_t), \
11638	(uintptr_t)iemNativeHlpMemStoreDataU32, pCallEntry->idxInstr)
11639
11640	#define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64ConstValue) \
11641	off = iemNativeEmitMemStoreConstDataCommon(pReNative, off, a_u64ConstValue, a_iSeg, a_GCPtrMem, sizeof(uint64_t), \
11642	(uintptr_t)iemNativeHlpMemStoreDataU64, pCallEntry->idxInstr)
11643
11644
11645	#define IEM_MC_STORE_MEM_FLAT_U8_CONST(a_GCPtrMem, a_u8ConstValue) \
11646	off = iemNativeEmitMemStoreConstDataCommon(pReNative, off, a_u8ConstValue, UINT8_MAX, a_GCPtrMem, sizeof(uint8_t), \
11647	(uintptr_t)iemNativeHlpMemFlatStoreDataU8, pCallEntry->idxInstr)
11648
11649	#define IEM_MC_STORE_MEM_FLAT_U16_CONST(a_GCPtrMem, a_u16ConstValue) \
11650	off = iemNativeEmitMemStoreConstDataCommon(pReNative, off, a_u16ConstValue, UINT8_MAX, a_GCPtrMem, sizeof(uint16_t), \
11651	(uintptr_t)iemNativeHlpMemFlatStoreDataU16, pCallEntry->idxInstr)
11652
11653	#define IEM_MC_STORE_MEM_FLAT_U32_CONST(a_GCPtrMem, a_u32ConstValue) \
11654	off = iemNativeEmitMemStoreConstDataCommon(pReNative, off, a_u32ConstValue, UINT8_MAX, a_GCPtrMem, sizeof(uint32_t), \
11655	(uintptr_t)iemNativeHlpMemFlatStoreDataU32, pCallEntry->idxInstr)
11656
11657	#define IEM_MC_STORE_MEM_FLAT_U64_CONST(a_GCPtrMem, a_u64ConstValue) \
11658	off = iemNativeEmitMemStoreConstDataCommon(pReNative, off, a_u64ConstValue, UINT8_MAX, a_GCPtrMem, sizeof(uint64_t), \
11659	(uintptr_t)iemNativeHlpMemFlatStoreDataU64, pCallEntry->idxInstr)
11660
11661	/** Emits code for IEM_MC_STORE_MEM_U8/16/32/64_CONST and
11662	* IEM_MC_STORE_MEM_FLAT_U8/16/32/64_CONST (with iSegReg = UINT8_MAX). */
11663	DECL_INLINE_THROW(uint32_t)
11664	iemNativeEmitMemStoreConstDataCommon(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint64_t uValueConst, uint8_t iSegReg,
11665	uint8_t idxVarGCPtrMem, uint8_t cbMem, uintptr_t pfnFunction, uint8_t idxInstr)
11666	{
11667	/*
11668	* Create a temporary const variable and call iemNativeEmitMemFetchStoreDataCommon
11669	* to do the grunt work.
11670	*/
11671	uint8_t const idxVarConstValue = iemNativeVarAllocConst(pReNative, cbMem, uValueConst);
11672	off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, idxVarConstValue, iSegReg, idxVarGCPtrMem,
11673	cbMem, cbMem - 1, kIemNativeEmitMemOp_Store,
11674	pfnFunction, idxInstr);
11675	iemNativeVarFreeLocal(pReNative, idxVarConstValue);
11676	return off;
11677	}
11678
11679
11680
11681	/*********************************************************************************************************************************
11682	* Stack Accesses. *
11683	*********************************************************************************************************************************/
11684	/* RT_MAKE_U32_FROM_U8(cBitsVar, cBitsFlat, fSReg, 0) */
11685	#define IEM_MC_PUSH_U16(a_u16Value) \
11686	off = iemNativeEmitStackPush(pReNative, off, a_u16Value, RT_MAKE_U32_FROM_U8(16, 0, 0, 0), \
11687	(uintptr_t)iemNativeHlpStackStoreU16, pCallEntry->idxInstr)
11688	#define IEM_MC_PUSH_U32(a_u32Value) \
11689	off = iemNativeEmitStackPush(pReNative, off, a_u32Value, RT_MAKE_U32_FROM_U8(32, 0, 0, 0), \
11690	(uintptr_t)iemNativeHlpStackStoreU32, pCallEntry->idxInstr)
11691	#define IEM_MC_PUSH_U32_SREG(a_uSegVal) \
11692	off = iemNativeEmitStackPush(pReNative, off, a_uSegVal, RT_MAKE_U32_FROM_U8(32, 0, 1, 0), \
11693	(uintptr_t)iemNativeHlpStackStoreU32SReg, pCallEntry->idxInstr)
11694	#define IEM_MC_PUSH_U64(a_u64Value) \
11695	off = iemNativeEmitStackPush(pReNative, off, a_u64Value, RT_MAKE_U32_FROM_U8(64, 0, 0, 0), \
11696	(uintptr_t)iemNativeHlpStackStoreU64, pCallEntry->idxInstr)
11697
11698	#define IEM_MC_FLAT32_PUSH_U16(a_u16Value) \
11699	off = iemNativeEmitStackPush(pReNative, off, a_u16Value, RT_MAKE_U32_FROM_U8(16, 32, 0, 0), \
11700	(uintptr_t)iemNativeHlpStackFlatStoreU16, pCallEntry->idxInstr)
11701	#define IEM_MC_FLAT32_PUSH_U32(a_u32Value) \
11702	off = iemNativeEmitStackPush(pReNative, off, a_u32Value, RT_MAKE_U32_FROM_U8(32, 32, 0, 0), \
11703	(uintptr_t)iemNativeHlpStackFlatStoreU32, pCallEntry->idxInstr)
11704	#define IEM_MC_FLAT32_PUSH_U32_SREG(a_u32Value) \
11705	off = iemNativeEmitStackPush(pReNative, off, a_u32Value, RT_MAKE_U32_FROM_U8(32, 32, 1, 0), \
11706	(uintptr_t)iemNativeHlpStackFlatStoreU32SReg, pCallEntry->idxInstr)
11707
11708	#define IEM_MC_FLAT64_PUSH_U16(a_u16Value) \
11709	off = iemNativeEmitStackPush(pReNative, off, a_u16Value, RT_MAKE_U32_FROM_U8(16, 64, 0, 0), \
11710	(uintptr_t)iemNativeHlpStackFlatStoreU16, pCallEntry->idxInstr)
11711	#define IEM_MC_FLAT64_PUSH_U64(a_u64Value) \
11712	off = iemNativeEmitStackPush(pReNative, off, a_u64Value, RT_MAKE_U32_FROM_U8(64, 64, 0, 0), \
11713	(uintptr_t)iemNativeHlpStackFlatStoreU64, pCallEntry->idxInstr)
11714
11715
11716	DECL_FORCE_INLINE_THROW(uint32_t)
11717	iemNativeEmitStackPushUse16Sp(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t idxRegRsp, uint8_t idxRegEffSp, uint8_t cbMem)
11718	{
11719	/* Use16BitSp: */
11720	#ifdef RT_ARCH_AMD64
11721	off = iemNativeEmitSubGpr16ImmEx(pCodeBuf, off, idxRegRsp, cbMem); /* ASSUMES this does NOT modify bits [63:16]! */
11722	off = iemNativeEmitLoadGprFromGpr16Ex(pCodeBuf, off, idxRegEffSp, idxRegRsp);
11723	#else
11724	/* sub regeff, regrsp, #cbMem */
11725	pCodeBuf[off++] = Armv8A64MkInstrSubUImm12(idxRegEffSp, idxRegRsp, cbMem, false /f64Bit/);
11726	/* and regeff, regeff, #0xffff */
11727	Assert(Armv8A64ConvertImmRImmS2Mask32(15, 0) == 0xffff);
11728	pCodeBuf[off++] = Armv8A64MkInstrAndImm(idxRegEffSp, idxRegEffSp, 15, 0, false /f64Bit/);
11729	/* bfi regrsp, regeff, #0, #16 - moves bits 15:0 from idxVarReg to idxGstTmpReg bits 15:0. */
11730	pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegRsp, idxRegEffSp, 0, 16, false /f64Bit/);
11731	#endif
11732	return off;
11733	}
11734
11735
11736	DECL_FORCE_INLINE(uint32_t)
11737	iemNativeEmitStackPushUse32Sp(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t idxRegRsp, uint8_t idxRegEffSp, uint8_t cbMem)
11738	{
11739	/* Use32BitSp: */
11740	off = iemNativeEmitSubGpr32ImmEx(pCodeBuf, off, idxRegRsp, cbMem);
11741	off = iemNativeEmitLoadGprFromGpr32Ex(pCodeBuf, off, idxRegEffSp, idxRegRsp);
11742	return off;
11743	}
11744
11745
11746	/** IEM_MC[\|_FLAT32\|_FLAT64]_PUSH_U16/32/32_SREG/64 */
11747	DECL_INLINE_THROW(uint32_t)
11748	iemNativeEmitStackPush(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarValue,
11749	uint32_t cBitsVarAndFlat, uintptr_t pfnFunction, uint8_t idxInstr)
11750	{
11751	/*
11752	* Assert sanity.
11753	*/
11754	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarValue);
11755	#ifdef VBOX_STRICT
11756	if (RT_BYTE2(cBitsVarAndFlat) != 0)
11757	{
11758	Assert( (pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT
11759	\|\| (pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT
11760	\|\| (pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT);
11761	Assert( pfnFunction
11762	== ( cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(16, 32, 0, 0) ? (uintptr_t)iemNativeHlpStackFlatStoreU16
11763	: cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(32, 32, 0, 0) ? (uintptr_t)iemNativeHlpStackFlatStoreU32
11764	: cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(32, 32, 1, 0) ? (uintptr_t)iemNativeHlpStackFlatStoreU32SReg
11765	: cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(16, 64, 0, 0) ? (uintptr_t)iemNativeHlpStackFlatStoreU16
11766	: cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(64, 64, 0, 0) ? (uintptr_t)iemNativeHlpStackFlatStoreU64
11767	: UINT64_C(0xc000b000a0009000) ));
11768	}
11769	else
11770	Assert( pfnFunction
11771	== ( cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(16, 0, 0, 0) ? (uintptr_t)iemNativeHlpStackStoreU16
11772	: cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(32, 0, 0, 0) ? (uintptr_t)iemNativeHlpStackStoreU32
11773	: cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(32, 0, 1, 0) ? (uintptr_t)iemNativeHlpStackStoreU32SReg
11774	: cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(64, 0, 0, 0) ? (uintptr_t)iemNativeHlpStackStoreU64
11775	: UINT64_C(0xc000b000a0009000) ));
11776	#endif
11777
11778	#ifdef VBOX_STRICT
11779	/*
11780	* Check that the fExec flags we've got make sense.
11781	*/
11782	off = iemNativeEmitExecFlagsCheck(pReNative, off, pReNative->fExec);
11783	#endif
11784
11785	/*
11786	* To keep things simple we have to commit any pending writes first as we
11787	* may end up making calls.
11788	*/
11789	/** @todo we could postpone this till we make the call and reload the
11790	* registers after returning from the call. Not sure if that's sensible or
11791	* not, though. */
11792	off = iemNativeRegFlushPendingWrites(pReNative, off);
11793
11794	/*
11795	* First we calculate the new RSP and the effective stack pointer value.
11796	* For 64-bit mode and flat 32-bit these two are the same.
11797	* (Code structure is very similar to that of PUSH)
11798	*/
11799	uint8_t const cbMem = RT_BYTE1(cBitsVarAndFlat) / 8;
11800	bool const fIsSegReg = RT_BYTE3(cBitsVarAndFlat) != 0;
11801	bool const fIsIntelSeg = fIsSegReg && IEM_IS_GUEST_CPU_INTEL(pReNative->pVCpu);
11802	uint8_t const cbMemAccess = !fIsIntelSeg \|\| (pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_16BIT
11803	? cbMem : sizeof(uint16_t);
11804	uint8_t const cBitsFlat = RT_BYTE2(cBitsVarAndFlat); RT_NOREF(cBitsFlat);
11805	uint8_t const idxRegRsp = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(X86_GREG_xSP),
11806	kIemNativeGstRegUse_ForUpdate, true /fNoVolatileRegs/);
11807	uint8_t const idxRegEffSp = cBitsFlat != 0 ? idxRegRsp : iemNativeRegAllocTmp(pReNative, &off);
11808	uint32_t offFixupJumpToUseOtherBitSp = UINT32_MAX;
11809	if (cBitsFlat != 0)
11810	{
11811	Assert(idxRegEffSp == idxRegRsp);
11812	Assert(cBitsFlat == 32 \|\| cBitsFlat == 64);
11813	Assert(IEM_F_MODE_X86_IS_FLAT(pReNative->fExec));
11814	if (cBitsFlat == 64)
11815	off = iemNativeEmitSubGprImm(pReNative, off, idxRegRsp, cbMem);
11816	else
11817	off = iemNativeEmitSubGpr32Imm(pReNative, off, idxRegRsp, cbMem);
11818	}
11819	else /** @todo We can skip the test if we're targeting pre-386 CPUs. */
11820	{
11821	Assert(idxRegEffSp != idxRegRsp);
11822	uint8_t const idxRegSsAttr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_SEG_ATTRIB(X86_SREG_SS),
11823	kIemNativeGstRegUse_ReadOnly);
11824	#ifdef RT_ARCH_AMD64
11825	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 32);
11826	#else
11827	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 10);
11828	#endif
11829	off = iemNativeEmitTestAnyBitsInGpr32Ex(pCodeBuf, off, idxRegSsAttr, X86DESCATTR_D);
11830	iemNativeRegFreeTmp(pReNative, idxRegSsAttr);
11831	offFixupJumpToUseOtherBitSp = off;
11832	if ((pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT)
11833	{
11834	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, off /8-bit suffices/, kIemNativeInstrCond_e); /* jump if zero */
11835	off = iemNativeEmitStackPushUse32Sp(pCodeBuf, off, idxRegRsp, idxRegEffSp, cbMem);
11836	}
11837	else
11838	{
11839	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, off /8-bit suffices/, kIemNativeInstrCond_ne); /* jump if not zero */
11840	off = iemNativeEmitStackPushUse16Sp(pCodeBuf, off, idxRegRsp, idxRegEffSp, cbMem);
11841	}
11842	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
11843	}
11844	/* SpUpdateEnd: */
11845	uint32_t const offLabelSpUpdateEnd = off;
11846
11847	/*
11848	* Okay, now prepare for TLB lookup and jump to code (or the TlbMiss if
11849	* we're skipping lookup).
11850	*/
11851	uint8_t const iSegReg = cBitsFlat != 0 ? UINT8_MAX : X86_SREG_SS;
11852	IEMNATIVEEMITTLBSTATE const TlbState(pReNative, idxRegEffSp, &off, iSegReg, cbMemAccess);
11853	uint16_t const uTlbSeqNo = pReNative->uTlbSeqNo++;
11854	uint32_t const idxLabelTlbMiss = iemNativeLabelCreate(pReNative, kIemNativeLabelType_TlbMiss, UINT32_MAX, uTlbSeqNo);
11855	uint32_t const idxLabelTlbLookup = !TlbState.fSkip
11856	? iemNativeLabelCreate(pReNative, kIemNativeLabelType_TlbLookup, UINT32_MAX, uTlbSeqNo)
11857	: UINT32_MAX;
11858	uint8_t const idxRegValue = !TlbState.fSkip
11859	&& pReNative->Core.aVars[idxVarValue].enmKind != kIemNativeVarKind_Immediate
11860	? iemNativeVarRegisterAcquire(pReNative, idxVarValue, &off, true /fInitialized/,
11861	IEMNATIVE_CALL_ARG2_GREG /idxRegPref/)
11862	: UINT8_MAX;
11863	uint8_t const idxRegMemResult = !TlbState.fSkip ? iemNativeRegAllocTmp(pReNative, &off) : UINT8_MAX;
11864
11865
11866	if (!TlbState.fSkip)
11867	off = iemNativeEmitJmpToLabel(pReNative, off, idxLabelTlbLookup); /** @todo short jump */
11868	else
11869	off = iemNativeEmitJmpToLabel(pReNative, off, idxLabelTlbMiss); /** @todo short jump */
11870
11871	/*
11872	* Use16BitSp:
11873	*/
11874	if (cBitsFlat == 0)
11875	{
11876	#ifdef RT_ARCH_AMD64
11877	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 32);
11878	#else
11879	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 10);
11880	#endif
11881	iemNativeFixupFixedJump(pReNative, offFixupJumpToUseOtherBitSp, off);
11882	if ((pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT)
11883	off = iemNativeEmitStackPushUse16Sp(pCodeBuf, off, idxRegRsp, idxRegEffSp, cbMem);
11884	else
11885	off = iemNativeEmitStackPushUse32Sp(pCodeBuf, off, idxRegRsp, idxRegEffSp, cbMem);
11886	off = iemNativeEmitJmpToFixedEx(pCodeBuf, off, offLabelSpUpdateEnd);
11887	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
11888	}
11889
11890	/*
11891	* TlbMiss:
11892	*
11893	* Call helper to do the pushing.
11894	*/
11895	iemNativeLabelDefine(pReNative, idxLabelTlbMiss, off);
11896
11897	#ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
11898	off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr));
11899	#else
11900	RT_NOREF(idxInstr);
11901	#endif
11902
11903	/* Save variables in volatile registers. */
11904	uint32_t const fHstRegsNotToSave = TlbState.getRegsNotToSave()
11905	\| (idxRegMemResult < RT_ELEMENTS(pReNative->Core.aHstRegs) ? RT_BIT_32(idxRegMemResult) : 0)
11906	\| (idxRegEffSp != idxRegRsp ? RT_BIT_32(idxRegEffSp) : 0)
11907	\| (idxRegValue < RT_ELEMENTS(pReNative->Core.aHstRegs) ? RT_BIT_32(idxRegValue) : 0);
11908	off = iemNativeVarSaveVolatileRegsPreHlpCall(pReNative, off, fHstRegsNotToSave);
11909
11910	if ( idxRegValue == IEMNATIVE_CALL_ARG1_GREG
11911	&& idxRegEffSp == IEMNATIVE_CALL_ARG2_GREG)
11912	{
11913	/* Swap them using ARG0 as temp register: */
11914	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_CALL_ARG1_GREG);
11915	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG1_GREG, IEMNATIVE_CALL_ARG2_GREG);
11916	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG2_GREG, IEMNATIVE_CALL_ARG0_GREG);
11917	}
11918	else if (idxRegEffSp != IEMNATIVE_CALL_ARG2_GREG)
11919	{
11920	/* IEMNATIVE_CALL_ARG2_GREG = idxVarValue (first!) */
11921	off = iemNativeEmitLoadArgGregFromImmOrStackVar(pReNative, off, IEMNATIVE_CALL_ARG2_GREG, idxVarValue,
11922	0 /offAddend/, IEMNATIVE_CALL_VOLATILE_GREG_MASK);
11923
11924	/* IEMNATIVE_CALL_ARG1_GREG = idxRegEffSp */
11925	if (idxRegEffSp != IEMNATIVE_CALL_ARG1_GREG)
11926	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG1_GREG, idxRegEffSp);
11927	}
11928	else
11929	{
11930	/* IEMNATIVE_CALL_ARG1_GREG = idxRegEffSp (first!) */
11931	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG1_GREG, idxRegEffSp);
11932
11933	/* IEMNATIVE_CALL_ARG2_GREG = idxVarValue */
11934	off = iemNativeEmitLoadArgGregFromImmOrStackVar(pReNative, off, IEMNATIVE_CALL_ARG2_GREG, idxVarValue, 0 /offAddend/,
11935	IEMNATIVE_CALL_VOLATILE_GREG_MASK & ~IEMNATIVE_CALL_ARG1_GREG);
11936	}
11937
11938	/* IEMNATIVE_CALL_ARG0_GREG = pVCpu */
11939	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
11940
11941	/* Done setting up parameters, make the call. */
11942	off = iemNativeEmitCallImm(pReNative, off, pfnFunction);
11943
11944	/* Restore variables and guest shadow registers to volatile registers. */
11945	off = iemNativeVarRestoreVolatileRegsPostHlpCall(pReNative, off, fHstRegsNotToSave);
11946	off = iemNativeRegRestoreGuestShadowsInVolatileRegs(pReNative, off, TlbState.getActiveRegsWithShadows());
11947
11948	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
11949	if (!TlbState.fSkip)
11950	{
11951	/* end of TlbMiss - Jump to the done label. */
11952	uint32_t const idxLabelTlbDone = iemNativeLabelCreate(pReNative, kIemNativeLabelType_TlbDone, UINT32_MAX, uTlbSeqNo);
11953	off = iemNativeEmitJmpToLabel(pReNative, off, idxLabelTlbDone);
11954
11955	/*
11956	* TlbLookup:
11957	*/
11958	off = iemNativeEmitTlbLookup<true>(pReNative, off, &TlbState, iSegReg, cbMemAccess, cbMemAccess - 1,
11959	IEM_ACCESS_TYPE_WRITE, idxLabelTlbLookup, idxLabelTlbMiss, idxRegMemResult);
11960
11961	/*
11962	* Emit code to do the actual storing / fetching.
11963	*/
11964	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 64);
11965	# ifdef VBOX_WITH_STATISTICS
11966	off = iemNativeEmitIncStamCounterInVCpuEx(pCodeBuf, off, TlbState.idxReg1, TlbState.idxReg2,
11967	RT_UOFFSETOF(VMCPUCC, iem.s.StatNativeTlbHitsForStack));
11968	# endif
11969	if (idxRegValue != UINT8_MAX)
11970	{
11971	switch (cbMemAccess)
11972	{
11973	case 2:
11974	off = iemNativeEmitStoreGpr16ByGprEx(pCodeBuf, off, idxRegValue, idxRegMemResult);
11975	break;
11976	case 4:
11977	if (!fIsIntelSeg)
11978	off = iemNativeEmitStoreGpr32ByGprEx(pCodeBuf, off, idxRegValue, idxRegMemResult);
11979	else
11980	{
11981	/* intel real mode segment push. 10890XE adds the 2nd of half EFLAGS to a
11982	PUSH FS in real mode, so we have to try emulate that here.
11983	We borrow the now unused idxReg1 from the TLB lookup code here. */
11984	uint8_t idxRegEfl = iemNativeRegAllocTmpForGuestRegIfAlreadyPresent(pReNative, &off,
11985	kIemNativeGstReg_EFlags);
11986	if (idxRegEfl != UINT8_MAX)
11987	{
11988	#ifdef ARCH_AMD64
11989	off = iemNativeEmitLoadGprFromGpr32(pReNative, off, TlbState.idxReg1, idxRegEfl);
11990	off = iemNativeEmitAndGpr32ByImm(pReNative, off, TlbState.idxReg1,
11991	UINT32_C(0xffff0000) & ~X86_EFL_RAZ_MASK);
11992	#else
11993	off = iemNativeEmitGpr32EqGprAndImmEx(iemNativeInstrBufEnsure(pReNative, off, 3),
11994	off, TlbState.idxReg1, idxRegEfl,
11995	UINT32_C(0xffff0000) & ~X86_EFL_RAZ_MASK);
11996	#endif
11997	iemNativeRegFreeTmp(pReNative, idxRegEfl);
11998	}
11999	else
12000	{
12001	off = iemNativeEmitLoadGprFromVCpuU32(pReNative, off, TlbState.idxReg1,
12002	RT_UOFFSETOF(VMCPUCC, cpum.GstCtx.eflags));
12003	off = iemNativeEmitAndGpr32ByImm(pReNative, off, TlbState.idxReg1,
12004	UINT32_C(0xffff0000) & ~X86_EFL_RAZ_MASK);
12005	}
12006	/* ASSUMES the upper half of idxRegValue is ZERO. */
12007	off = iemNativeEmitOrGpr32ByGpr(pReNative, off, TlbState.idxReg1, idxRegValue);
12008	off = iemNativeEmitStoreGpr32ByGprEx(pCodeBuf, off, TlbState.idxReg1, idxRegMemResult);
12009	}
12010	break;
12011	case 8:
12012	off = iemNativeEmitStoreGpr64ByGprEx(pCodeBuf, off, idxRegValue, idxRegMemResult);
12013	break;
12014	default:
12015	AssertFailed();
12016	}
12017	}
12018	else
12019	{
12020	switch (cbMemAccess)
12021	{
12022	case 2:
12023	off = iemNativeEmitStoreImm16ByGprEx(pCodeBuf, off,
12024	(uint16_t)pReNative->Core.aVars[idxVarValue].u.uValue,
12025	idxRegMemResult, TlbState.idxReg1);
12026	break;
12027	case 4:
12028	Assert(!fIsSegReg);
12029	off = iemNativeEmitStoreImm32ByGprEx(pCodeBuf, off,
12030	(uint32_t)pReNative->Core.aVars[idxVarValue].u.uValue,
12031	idxRegMemResult, TlbState.idxReg1);
12032	break;
12033	case 8:
12034	off = iemNativeEmitStoreImm64ByGprEx(pCodeBuf, off, pReNative->Core.aVars[idxVarValue].u.uValue,
12035	idxRegMemResult, TlbState.idxReg1);
12036	break;
12037	default:
12038	AssertFailed();
12039	}
12040	}
12041
12042	iemNativeRegFreeTmp(pReNative, idxRegMemResult);
12043	TlbState.freeRegsAndReleaseVars(pReNative);
12044
12045	/*
12046	* TlbDone:
12047	*
12048	* Commit the new RSP value.
12049	*/
12050	iemNativeLabelDefine(pReNative, idxLabelTlbDone, off);
12051	}
12052	#endif /* IEMNATIVE_WITH_TLB_LOOKUP */
12053
12054	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxRegRsp, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.rsp));
12055	iemNativeRegFreeTmp(pReNative, idxRegRsp);
12056	if (idxRegEffSp != idxRegRsp)
12057	iemNativeRegFreeTmp(pReNative, idxRegEffSp);
12058
12059	/* The value variable is implictly flushed. */
12060	if (idxRegValue != UINT8_MAX)
12061	iemNativeVarRegisterRelease(pReNative, idxVarValue);
12062	iemNativeVarFreeLocal(pReNative, idxVarValue);
12063
12064	return off;
12065	}
12066
12067
12068
12069	/* RT_MAKE_U32_FROM_U8(cBitsVar, cBitsFlat, 0, 0) */
12070	#define IEM_MC_POP_GREG_U16(a_iGReg) \
12071	off = iemNativeEmitStackPopGReg(pReNative, off, a_iGReg, RT_MAKE_U32_FROM_U8(16, 0, 0, 0), \
12072	(uintptr_t)iemNativeHlpStackFetchU16, pCallEntry->idxInstr)
12073	#define IEM_MC_POP_GREG_U32(a_iGReg) \
12074	off = iemNativeEmitStackPopGReg(pReNative, off, a_iGReg, RT_MAKE_U32_FROM_U8(32, 0, 0, 0), \
12075	(uintptr_t)iemNativeHlpStackFetchU32, pCallEntry->idxInstr)
12076	#define IEM_MC_POP_GREG_U64(a_iGReg) \
12077	off = iemNativeEmitStackPopGReg(pReNative, off, a_iGReg, RT_MAKE_U32_FROM_U8(64, 0, 0, 0), \
12078	(uintptr_t)iemNativeHlpStackFetchU64, pCallEntry->idxInstr)
12079
12080	#define IEM_MC_FLAT32_POP_GREG_U16(a_iGReg) \
12081	off = iemNativeEmitStackPopGReg(pReNative, off, a_iGReg, RT_MAKE_U32_FROM_U8(16, 32, 0, 0), \
12082	(uintptr_t)iemNativeHlpStackFlatFetchU16, pCallEntry->idxInstr)
12083	#define IEM_MC_FLAT32_POP_GREG_U32(a_iGReg) \
12084	off = iemNativeEmitStackPopGReg(pReNative, off, a_iGReg, RT_MAKE_U32_FROM_U8(32, 32, 0, 0), \
12085	(uintptr_t)iemNativeHlpStackFlatFetchU32, pCallEntry->idxInstr)
12086
12087	#define IEM_MC_FLAT64_POP_GREG_U16(a_iGReg) \
12088	off = iemNativeEmitStackPopGReg(pReNative, off, a_iGReg, RT_MAKE_U32_FROM_U8(16, 64, 0, 0), \
12089	(uintptr_t)iemNativeHlpStackFlatFetchU16, pCallEntry->idxInstr)
12090	#define IEM_MC_FLAT64_POP_GREG_U64(a_iGReg) \
12091	off = iemNativeEmitStackPopGReg(pReNative, off, a_iGReg, RT_MAKE_U32_FROM_U8(64, 64, 0, 0), \
12092	(uintptr_t)iemNativeHlpStackFlatFetchU64, pCallEntry->idxInstr)
12093
12094
12095	DECL_FORCE_INLINE_THROW(uint32_t)
12096	iemNativeEmitStackPopUse16Sp(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t idxRegRsp, uint8_t idxRegEffSp, uint8_t cbMem,
12097	uint8_t idxRegTmp)
12098	{
12099	/* Use16BitSp: */
12100	#ifdef RT_ARCH_AMD64
12101	off = iemNativeEmitLoadGprFromGpr16Ex(pCodeBuf, off, idxRegEffSp, idxRegRsp);
12102	off = iemNativeEmitAddGpr16ImmEx(pCodeBuf, off, idxRegRsp, cbMem); /* ASSUMES this does NOT modify bits [63:16]! */
12103	RT_NOREF(idxRegTmp);
12104	#else
12105	/* ubfiz regeff, regrsp, #0, #16 - copies bits 15:0 from RSP to EffSp bits 15:0, zeroing bits 63:16. */
12106	pCodeBuf[off++] = Armv8A64MkInstrUbfiz(idxRegEffSp, idxRegRsp, 0, 16, false /f64Bit/);
12107	/* add tmp, regrsp, #cbMem */
12108	pCodeBuf[off++] = Armv8A64MkInstrAddUImm12(idxRegTmp, idxRegRsp, cbMem, false /f64Bit/);
12109	/* and tmp, tmp, #0xffff */
12110	Assert(Armv8A64ConvertImmRImmS2Mask32(15, 0) == 0xffff);
12111	pCodeBuf[off++] = Armv8A64MkInstrAndImm(idxRegTmp, idxRegTmp, 15, 0, false /f64Bit/);
12112	/* bfi regrsp, regeff, #0, #16 - moves bits 15:0 from tmp to RSP bits 15:0, keeping the other RSP bits as is. */
12113	pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegRsp, idxRegTmp, 0, 16, false /f64Bit/);
12114	#endif
12115	return off;
12116	}
12117
12118
12119	DECL_FORCE_INLINE(uint32_t)
12120	iemNativeEmitStackPopUse32Sp(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t idxRegRsp, uint8_t idxRegEffSp, uint8_t cbMem)
12121	{
12122	/* Use32BitSp: */
12123	off = iemNativeEmitLoadGprFromGpr32Ex(pCodeBuf, off, idxRegEffSp, idxRegRsp);
12124	off = iemNativeEmitAddGpr32ImmEx(pCodeBuf, off, idxRegRsp, cbMem);
12125	return off;
12126	}
12127
12128
12129	/** IEM_MC[\|_FLAT32\|_FLAT64]_POP_GREG_U16/32/64 */
12130	DECL_INLINE_THROW(uint32_t)
12131	iemNativeEmitStackPopGReg(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxGReg,
12132	uint32_t cBitsVarAndFlat, uintptr_t pfnFunction, uint8_t idxInstr)
12133	{
12134	/*
12135	* Assert sanity.
12136	*/
12137	Assert(idxGReg < 16);
12138	#ifdef VBOX_STRICT
12139	if (RT_BYTE2(cBitsVarAndFlat) != 0)
12140	{
12141	Assert( (pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT
12142	\|\| (pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT
12143	\|\| (pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT);
12144	Assert( pfnFunction
12145	== ( cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(16, 32, 0, 0) ? (uintptr_t)iemNativeHlpStackFlatFetchU16
12146	: cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(32, 32, 0, 0) ? (uintptr_t)iemNativeHlpStackFlatFetchU32
12147	: cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(16, 64, 0, 0) ? (uintptr_t)iemNativeHlpStackFlatFetchU16
12148	: cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(64, 64, 0, 0) ? (uintptr_t)iemNativeHlpStackFlatFetchU64
12149	: UINT64_C(0xc000b000a0009000) ));
12150	}
12151	else
12152	Assert( pfnFunction
12153	== ( cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(16, 0, 0, 0) ? (uintptr_t)iemNativeHlpStackFetchU16
12154	: cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(32, 0, 0, 0) ? (uintptr_t)iemNativeHlpStackFetchU32
12155	: cBitsVarAndFlat == RT_MAKE_U32_FROM_U8(64, 0, 0, 0) ? (uintptr_t)iemNativeHlpStackFetchU64
12156	: UINT64_C(0xc000b000a0009000) ));
12157	#endif
12158
12159	#ifdef VBOX_STRICT
12160	/*
12161	* Check that the fExec flags we've got make sense.
12162	*/
12163	off = iemNativeEmitExecFlagsCheck(pReNative, off, pReNative->fExec);
12164	#endif
12165
12166	/*
12167	* To keep things simple we have to commit any pending writes first as we
12168	* may end up making calls.
12169	*/
12170	off = iemNativeRegFlushPendingWrites(pReNative, off);
12171
12172	/*
12173	* Determine the effective stack pointer, for non-FLAT modes we also update RSP.
12174	* For FLAT modes we'll do this in TlbDone as we'll be using the incoming RSP
12175	* directly as the effective stack pointer.
12176	* (Code structure is very similar to that of PUSH)
12177	*/
12178	uint8_t const cbMem = RT_BYTE1(cBitsVarAndFlat) / 8;
12179	uint8_t const cBitsFlat = RT_BYTE2(cBitsVarAndFlat); RT_NOREF(cBitsFlat);
12180	uint8_t const idxRegRsp = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(X86_GREG_xSP),
12181	kIemNativeGstRegUse_ForUpdate, true /fNoVolatileRegs/);
12182	uint8_t const idxRegEffSp = cBitsFlat != 0 ? idxRegRsp : iemNativeRegAllocTmp(pReNative, &off);
12183	/** @todo can do a better job picking the register here. For cbMem >= 4 this
12184	* will be the resulting register value. */
12185	uint8_t const idxRegMemResult = iemNativeRegAllocTmp(pReNative, &off); /* pointer then value; arm64 SP += 2/4 helper too. */
12186
12187	uint32_t offFixupJumpToUseOtherBitSp = UINT32_MAX;
12188	if (cBitsFlat != 0)
12189	{
12190	Assert(idxRegEffSp == idxRegRsp);
12191	Assert(cBitsFlat == 32 \|\| cBitsFlat == 64);
12192	Assert(IEM_F_MODE_X86_IS_FLAT(pReNative->fExec));
12193	}
12194	else /** @todo We can skip the test if we're targeting pre-386 CPUs. */
12195	{
12196	Assert(idxRegEffSp != idxRegRsp);
12197	uint8_t const idxRegSsAttr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_SEG_ATTRIB(X86_SREG_SS),
12198	kIemNativeGstRegUse_ReadOnly);
12199	#ifdef RT_ARCH_AMD64
12200	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 32);
12201	#else
12202	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 10);
12203	#endif
12204	off = iemNativeEmitTestAnyBitsInGpr32Ex(pCodeBuf, off, idxRegSsAttr, X86DESCATTR_D);
12205	iemNativeRegFreeTmp(pReNative, idxRegSsAttr);
12206	offFixupJumpToUseOtherBitSp = off;
12207	if ((pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT)
12208	{
12209	/** @todo can skip idxRegRsp updating when popping ESP. */
12210	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, off /8-bit suffices/, kIemNativeInstrCond_e); /* jump if zero */
12211	off = iemNativeEmitStackPopUse32Sp(pCodeBuf, off, idxRegRsp, idxRegEffSp, cbMem);
12212	}
12213	else
12214	{
12215	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, off /8-bit suffices/, kIemNativeInstrCond_ne); /* jump if not zero */
12216	off = iemNativeEmitStackPopUse16Sp(pCodeBuf, off, idxRegRsp, idxRegEffSp, cbMem, idxRegMemResult);
12217	}
12218	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
12219	}
12220	/* SpUpdateEnd: */
12221	uint32_t const offLabelSpUpdateEnd = off;
12222
12223	/*
12224	* Okay, now prepare for TLB lookup and jump to code (or the TlbMiss if
12225	* we're skipping lookup).
12226	*/
12227	uint8_t const iSegReg = cBitsFlat != 0 ? UINT8_MAX : X86_SREG_SS;
12228	IEMNATIVEEMITTLBSTATE const TlbState(pReNative, idxRegEffSp, &off, iSegReg, cbMem);
12229	uint16_t const uTlbSeqNo = pReNative->uTlbSeqNo++;
12230	uint32_t const idxLabelTlbMiss = iemNativeLabelCreate(pReNative, kIemNativeLabelType_TlbMiss, UINT32_MAX, uTlbSeqNo);
12231	uint32_t const idxLabelTlbLookup = !TlbState.fSkip
12232	? iemNativeLabelCreate(pReNative, kIemNativeLabelType_TlbLookup, UINT32_MAX, uTlbSeqNo)
12233	: UINT32_MAX;
12234
12235	if (!TlbState.fSkip)
12236	off = iemNativeEmitJmpToLabel(pReNative, off, idxLabelTlbLookup); /** @todo short jump */
12237	else
12238	off = iemNativeEmitJmpToLabel(pReNative, off, idxLabelTlbMiss); /** @todo short jump */
12239
12240	/*
12241	* Use16BitSp:
12242	*/
12243	if (cBitsFlat == 0)
12244	{
12245	#ifdef RT_ARCH_AMD64
12246	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 32);
12247	#else
12248	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 10);
12249	#endif
12250	iemNativeFixupFixedJump(pReNative, offFixupJumpToUseOtherBitSp, off);
12251	if ((pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT)
12252	off = iemNativeEmitStackPopUse16Sp(pCodeBuf, off, idxRegRsp, idxRegEffSp, cbMem, idxRegMemResult);
12253	else
12254	off = iemNativeEmitStackPopUse32Sp(pCodeBuf, off, idxRegRsp, idxRegEffSp, cbMem);
12255	off = iemNativeEmitJmpToFixedEx(pCodeBuf, off, offLabelSpUpdateEnd);
12256	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
12257	}
12258
12259	/*
12260	* TlbMiss:
12261	*
12262	* Call helper to do the pushing.
12263	*/
12264	iemNativeLabelDefine(pReNative, idxLabelTlbMiss, off);
12265
12266	#ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
12267	off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr));
12268	#else
12269	RT_NOREF(idxInstr);
12270	#endif
12271
12272	uint32_t const fHstRegsNotToSave = TlbState.getRegsNotToSave()
12273	\| (idxRegMemResult < RT_ELEMENTS(pReNative->Core.aHstRegs) ? RT_BIT_32(idxRegMemResult) : 0)
12274	\| (idxRegEffSp != idxRegRsp ? RT_BIT_32(idxRegEffSp) : 0);
12275	off = iemNativeVarSaveVolatileRegsPreHlpCall(pReNative, off, fHstRegsNotToSave);
12276
12277
12278	/* IEMNATIVE_CALL_ARG1_GREG = EffSp/RSP */
12279	if (idxRegEffSp != IEMNATIVE_CALL_ARG1_GREG)
12280	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG1_GREG, idxRegEffSp);
12281
12282	/* IEMNATIVE_CALL_ARG0_GREG = pVCpu */
12283	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
12284
12285	/* Done setting up parameters, make the call. */
12286	off = iemNativeEmitCallImm(pReNative, off, pfnFunction);
12287
12288	/* Move the return register content to idxRegMemResult. */
12289	if (idxRegMemResult != IEMNATIVE_CALL_RET_GREG)
12290	off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxRegMemResult, IEMNATIVE_CALL_RET_GREG);
12291
12292	/* Restore variables and guest shadow registers to volatile registers. */
12293	off = iemNativeVarRestoreVolatileRegsPostHlpCall(pReNative, off, fHstRegsNotToSave);
12294	off = iemNativeRegRestoreGuestShadowsInVolatileRegs(pReNative, off, TlbState.getActiveRegsWithShadows());
12295
12296	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
12297	if (!TlbState.fSkip)
12298	{
12299	/* end of TlbMiss - Jump to the done label. */
12300	uint32_t const idxLabelTlbDone = iemNativeLabelCreate(pReNative, kIemNativeLabelType_TlbDone, UINT32_MAX, uTlbSeqNo);
12301	off = iemNativeEmitJmpToLabel(pReNative, off, idxLabelTlbDone);
12302
12303	/*
12304	* TlbLookup:
12305	*/
12306	off = iemNativeEmitTlbLookup<true>(pReNative, off, &TlbState, iSegReg, cbMem, cbMem - 1, IEM_ACCESS_TYPE_READ,
12307	idxLabelTlbLookup, idxLabelTlbMiss, idxRegMemResult);
12308
12309	/*
12310	* Emit code to load the value (from idxRegMemResult into idxRegMemResult).
12311	*/
12312	PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 32);
12313	# ifdef VBOX_WITH_STATISTICS
12314	off = iemNativeEmitIncStamCounterInVCpuEx(pCodeBuf, off, TlbState.idxReg1, TlbState.idxReg2,
12315	RT_UOFFSETOF(VMCPUCC, iem.s.StatNativeTlbHitsForStack));
12316	# endif
12317	switch (cbMem)
12318	{
12319	case 2:
12320	off = iemNativeEmitLoadGprByGprU16Ex(pCodeBuf, off, idxRegMemResult, idxRegMemResult);
12321	break;
12322	case 4:
12323	off = iemNativeEmitLoadGprByGprU32Ex(pCodeBuf, off, idxRegMemResult, idxRegMemResult);
12324	break;
12325	case 8:
12326	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, idxRegMemResult, idxRegMemResult);
12327	break;
12328	default:
12329	AssertFailed();
12330	}
12331
12332	TlbState.freeRegsAndReleaseVars(pReNative);
12333
12334	/*
12335	* TlbDone:
12336	*
12337	* Set the new RSP value (FLAT accesses needs to calculate it first) and
12338	* commit the popped register value.
12339	*/
12340	iemNativeLabelDefine(pReNative, idxLabelTlbDone, off);
12341	}
12342	#endif /* IEMNATIVE_WITH_TLB_LOOKUP */
12343
12344	if (idxGReg != X86_GREG_xSP)
12345	{
12346	/* Set the register. */
12347	if (cbMem >= sizeof(uint32_t))
12348	{
12349	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
12350	AssertMsg( pReNative->idxCurCall == 0
12351	\|\| IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(iemNativeLivenessGetPrevStateByGstReg(pReNative, IEMNATIVEGSTREG_GPR(idxGReg))),
12352	("%s - %u\n", g_aGstShadowInfo[idxGReg].pszName, iemNativeLivenessGetPrevStateByGstReg(pReNative, IEMNATIVEGSTREG_GPR(idxGReg))));
12353	#endif
12354	iemNativeRegClearAndMarkAsGstRegShadow(pReNative, idxRegMemResult, IEMNATIVEGSTREG_GPR(idxGReg), off);
12355	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxRegMemResult,
12356	RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[idxGReg]));
12357	}
12358	else
12359	{
12360	Assert(cbMem == sizeof(uint16_t));
12361	uint8_t const idxRegDst = iemNativeRegAllocTmpForGuestReg(pReNative, &off, IEMNATIVEGSTREG_GPR(idxGReg),
12362	kIemNativeGstRegUse_ForUpdate);
12363	off = iemNativeEmitGprMergeInGpr16(pReNative, off, idxRegDst, idxRegMemResult);
12364	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxRegDst, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.aGRegs[idxGReg]));
12365	iemNativeRegFreeTmp(pReNative, idxRegDst);
12366	}
12367
12368	/* Complete RSP calculation for FLAT mode. */
12369	if (idxRegEffSp == idxRegRsp)
12370	{
12371	if (cBitsFlat == 64)
12372	off = iemNativeEmitAddGprImm8(pReNative, off, idxRegRsp, sizeof(uint64_t));
12373	else
12374	off = iemNativeEmitAddGpr32Imm8(pReNative, off, idxRegRsp, sizeof(uint32_t));
12375	}
12376	}
12377	else
12378	{
12379	/* We're popping RSP, ESP or SP. Only the is a bit extra work, of course. */
12380	if (cbMem == sizeof(uint64_t))
12381	off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxRegRsp, idxRegMemResult);
12382	else if (cbMem == sizeof(uint32_t))
12383	off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxRegRsp, idxRegMemResult);
12384	else
12385	{
12386	if (idxRegEffSp == idxRegRsp)
12387	{
12388	if (cBitsFlat == 64)
12389	off = iemNativeEmitAddGprImm8(pReNative, off, idxRegRsp, sizeof(uint64_t));
12390	else
12391	off = iemNativeEmitAddGpr32Imm8(pReNative, off, idxRegRsp, sizeof(uint32_t));
12392	}
12393	off = iemNativeEmitGprMergeInGpr16(pReNative, off, idxRegRsp, idxRegMemResult);
12394	}
12395	}
12396	off = iemNativeEmitStoreGprToVCpuU64(pReNative, off, idxRegRsp, RT_UOFFSETOF(VMCPU, cpum.GstCtx.rsp));
12397
12398	iemNativeRegFreeTmp(pReNative, idxRegRsp);
12399	if (idxRegEffSp != idxRegRsp)
12400	iemNativeRegFreeTmp(pReNative, idxRegEffSp);
12401	iemNativeRegFreeTmp(pReNative, idxRegMemResult);
12402
12403	return off;
12404	}
12405
12406
12407
12408	/*********************************************************************************************************************************
12409	* Memory mapping (IEM_MEM_MAP_XXX, IEM_MEM_FLAT_MAP_XXX). *
12410	*********************************************************************************************************************************/
12411
12412	#define IEM_MC_MEM_MAP_U8_ATOMIC(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12413	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint8_t), \
12414	IEM_ACCESS_DATA_ATOMIC, 0 /fAlignMask/, \
12415	(uintptr_t)iemNativeHlpMemMapDataU8Atomic, pCallEntry->idxInstr)
12416
12417	#define IEM_MC_MEM_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12418	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint8_t), \
12419	IEM_ACCESS_DATA_RW, 0 /fAlignMask/, \
12420	(uintptr_t)iemNativeHlpMemMapDataU8Rw, pCallEntry->idxInstr)
12421
12422	#define IEM_MC_MEM_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12423	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint8_t), \
12424	IEM_ACCESS_DATA_W, 0 /fAlignMask/, \
12425	(uintptr_t)iemNativeHlpMemMapDataU8Wo, pCallEntry->idxInstr) \
12426
12427	#define IEM_MC_MEM_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12428	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint8_t), \
12429	IEM_ACCESS_DATA_R, 0 /fAlignMask/, \
12430	(uintptr_t)iemNativeHlpMemMapDataU8Ro, pCallEntry->idxInstr)
12431
12432
12433	#define IEM_MC_MEM_MAP_U16_ATOMIC(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12434	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint16_t), \
12435	IEM_ACCESS_DATA_ATOMIC, sizeof(uint16_t) - 1 /fAlignMask/, \
12436	(uintptr_t)iemNativeHlpMemMapDataU16Atomic, pCallEntry->idxInstr)
12437
12438	#define IEM_MC_MEM_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12439	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint16_t), \
12440	IEM_ACCESS_DATA_RW, sizeof(uint16_t) - 1 /fAlignMask/, \
12441	(uintptr_t)iemNativeHlpMemMapDataU16Rw, pCallEntry->idxInstr)
12442
12443	#define IEM_MC_MEM_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12444	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint16_t), \
12445	IEM_ACCESS_DATA_W, sizeof(uint16_t) - 1 /fAlignMask/, \
12446	(uintptr_t)iemNativeHlpMemMapDataU16Wo, pCallEntry->idxInstr) \
12447
12448	#define IEM_MC_MEM_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12449	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint16_t), \
12450	IEM_ACCESS_DATA_R, sizeof(uint16_t) - 1 /fAlignMask/, \
12451	(uintptr_t)iemNativeHlpMemMapDataU16Ro, pCallEntry->idxInstr)
12452
12453	#define IEM_MC_MEM_MAP_I16_WO(a_pi16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12454	off = iemNativeEmitMemMapCommon(pReNative, off, a_pi16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(int16_t), \
12455	IEM_ACCESS_DATA_W, sizeof(uint16_t) - 1 /fAlignMask/, \
12456	(uintptr_t)iemNativeHlpMemMapDataU16Wo, pCallEntry->idxInstr) \
12457
12458
12459	#define IEM_MC_MEM_MAP_U32_ATOMIC(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12460	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint32_t), \
12461	IEM_ACCESS_DATA_ATOMIC, sizeof(uint32_t) - 1 /fAlignMask/, \
12462	(uintptr_t)iemNativeHlpMemMapDataU32Atomic, pCallEntry->idxInstr)
12463
12464	#define IEM_MC_MEM_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12465	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint32_t), \
12466	IEM_ACCESS_DATA_RW, sizeof(uint32_t) - 1 /fAlignMask/, \
12467	(uintptr_t)iemNativeHlpMemMapDataU32Rw, pCallEntry->idxInstr)
12468
12469	#define IEM_MC_MEM_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12470	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint32_t), \
12471	IEM_ACCESS_DATA_W, sizeof(uint32_t) - 1 /fAlignMask/, \
12472	(uintptr_t)iemNativeHlpMemMapDataU32Wo, pCallEntry->idxInstr) \
12473
12474	#define IEM_MC_MEM_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12475	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint32_t), \
12476	IEM_ACCESS_DATA_R, sizeof(uint32_t) - 1 /fAlignMask/, \
12477	(uintptr_t)iemNativeHlpMemMapDataU32Ro, pCallEntry->idxInstr)
12478
12479	#define IEM_MC_MEM_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12480	off = iemNativeEmitMemMapCommon(pReNative, off, a_pi32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(int32_t), \
12481	IEM_ACCESS_DATA_W, sizeof(uint32_t) - 1 /fAlignMask/, \
12482	(uintptr_t)iemNativeHlpMemMapDataU32Wo, pCallEntry->idxInstr) \
12483
12484
12485	#define IEM_MC_MEM_MAP_U64_ATOMIC(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12486	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint64_t), \
12487	IEM_ACCESS_DATA_ATOMIC, sizeof(uint64_t) - 1 /fAlignMask/, \
12488	(uintptr_t)iemNativeHlpMemMapDataU64Atomic, pCallEntry->idxInstr)
12489
12490	#define IEM_MC_MEM_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12491	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint64_t), \
12492	IEM_ACCESS_DATA_RW, sizeof(uint64_t) - 1 /fAlignMask/, \
12493	(uintptr_t)iemNativeHlpMemMapDataU64Rw, pCallEntry->idxInstr)
12494	#define IEM_MC_MEM_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12495	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint64_t), \
12496	IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1 /fAlignMask/, \
12497	(uintptr_t)iemNativeHlpMemMapDataU64Wo, pCallEntry->idxInstr) \
12498
12499	#define IEM_MC_MEM_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12500	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(uint64_t), \
12501	IEM_ACCESS_DATA_R, sizeof(uint64_t) - 1 /fAlignMask/, \
12502	(uintptr_t)iemNativeHlpMemMapDataU64Ro, pCallEntry->idxInstr)
12503
12504	#define IEM_MC_MEM_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12505	off = iemNativeEmitMemMapCommon(pReNative, off, a_pi64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(int64_t), \
12506	IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1 /fAlignMask/, \
12507	(uintptr_t)iemNativeHlpMemMapDataU64Wo, pCallEntry->idxInstr) \
12508
12509
12510	#define IEM_MC_MEM_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12511	off = iemNativeEmitMemMapCommon(pReNative, off, a_pr80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(RTFLOAT80U), \
12512	IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1 /fAlignMask/, \
12513	(uintptr_t)iemNativeHlpMemMapDataR80Wo, pCallEntry->idxInstr) \
12514
12515	#define IEM_MC_MEM_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12516	off = iemNativeEmitMemMapCommon(pReNative, off, a_pd80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(RTFLOAT80U), \
12517	IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1 /fAlignMask/, /** @todo check BCD align */ \
12518	(uintptr_t)iemNativeHlpMemMapDataD80Wo, pCallEntry->idxInstr) \
12519
12520
12521	#define IEM_MC_MEM_MAP_U128_ATOMIC(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12522	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(RTUINT128U), \
12523	IEM_ACCESS_DATA_ATOMIC, sizeof(RTUINT128U) - 1 /fAlignMask/, \
12524	(uintptr_t)iemNativeHlpMemMapDataU128Atomic, pCallEntry->idxInstr)
12525
12526	#define IEM_MC_MEM_MAP_U128_RW(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12527	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(RTUINT128U), \
12528	IEM_ACCESS_DATA_RW, sizeof(RTUINT128U) - 1 /fAlignMask/, \
12529	(uintptr_t)iemNativeHlpMemMapDataU128Rw, pCallEntry->idxInstr)
12530
12531	#define IEM_MC_MEM_MAP_U128_WO(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12532	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(RTUINT128U), \
12533	IEM_ACCESS_DATA_W, sizeof(RTUINT128U) - 1 /fAlignMask/, \
12534	(uintptr_t)iemNativeHlpMemMapDataU128Wo, pCallEntry->idxInstr) \
12535
12536	#define IEM_MC_MEM_MAP_U128_RO(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
12537	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem, sizeof(RTUINT128U), \
12538	IEM_ACCESS_DATA_R, sizeof(RTUINT128U) - 1 /fAlignMask/, \
12539	(uintptr_t)iemNativeHlpMemMapDataU128Ro, pCallEntry->idxInstr)
12540
12541
12542
12543	#define IEM_MC_MEM_FLAT_MAP_U8_ATOMIC(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
12544	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu8Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint8_t), \
12545	IEM_ACCESS_DATA_ATOMIC, 0 /fAlignMask/, \
12546	(uintptr_t)iemNativeHlpMemFlatMapDataU8Atomic, pCallEntry->idxInstr)
12547
12548	#define IEM_MC_MEM_FLAT_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
12549	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu8Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint8_t), \
12550	IEM_ACCESS_DATA_RW, 0 /fAlignMask/, \
12551	(uintptr_t)iemNativeHlpMemFlatMapDataU8Rw, pCallEntry->idxInstr)
12552
12553	#define IEM_MC_MEM_FLAT_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
12554	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu8Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint8_t), \
12555	IEM_ACCESS_DATA_W, 0 /fAlignMask/, \
12556	(uintptr_t)iemNativeHlpMemFlatMapDataU8Wo, pCallEntry->idxInstr) \
12557
12558	#define IEM_MC_MEM_FLAT_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
12559	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu8Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint8_t), \
12560	IEM_ACCESS_DATA_R, 0 /fAlignMask/, \
12561	(uintptr_t)iemNativeHlpMemFlatMapDataU8Ro, pCallEntry->idxInstr)
12562
12563
12564	#define IEM_MC_MEM_FLAT_MAP_U16_ATOMIC(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
12565	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu16Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint16_t), \
12566	IEM_ACCESS_DATA_ATOMIC, sizeof(uint16_t) - 1 /fAlignMask/, \
12567	(uintptr_t)iemNativeHlpMemFlatMapDataU16Atomic, pCallEntry->idxInstr)
12568
12569	#define IEM_MC_MEM_FLAT_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
12570	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu16Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint16_t), \
12571	IEM_ACCESS_DATA_RW, sizeof(uint16_t) - 1 /fAlignMask/, \
12572	(uintptr_t)iemNativeHlpMemFlatMapDataU16Rw, pCallEntry->idxInstr)
12573
12574	#define IEM_MC_MEM_FLAT_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
12575	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu16Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint16_t), \
12576	IEM_ACCESS_DATA_W, sizeof(uint16_t) - 1 /fAlignMask/, \
12577	(uintptr_t)iemNativeHlpMemFlatMapDataU16Wo, pCallEntry->idxInstr) \
12578
12579	#define IEM_MC_MEM_FLAT_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
12580	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu16Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint16_t), \
12581	IEM_ACCESS_DATA_R, sizeof(uint16_t) - 1 /fAlignMask/, \
12582	(uintptr_t)iemNativeHlpMemFlatMapDataU16Ro, pCallEntry->idxInstr)
12583
12584	#define IEM_MC_MEM_FLAT_MAP_I16_WO(a_pi16Mem, a_bUnmapInfo, a_GCPtrMem) \
12585	off = iemNativeEmitMemMapCommon(pReNative, off, a_pi16Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(int16_t), \
12586	IEM_ACCESS_DATA_W, sizeof(uint16_t) - 1 /fAlignMask/, \
12587	(uintptr_t)iemNativeHlpMemFlatMapDataU16Wo, pCallEntry->idxInstr) \
12588
12589
12590	#define IEM_MC_MEM_FLAT_MAP_U32_ATOMIC(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
12591	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu32Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint32_t), \
12592	IEM_ACCESS_DATA_ATOMIC, sizeof(uint32_t) - 1 /fAlignMask/, \
12593	(uintptr_t)iemNativeHlpMemFlatMapDataU32Atomic, pCallEntry->idxInstr)
12594
12595	#define IEM_MC_MEM_FLAT_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
12596	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu32Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint32_t), \
12597	IEM_ACCESS_DATA_RW, sizeof(uint32_t) - 1 /fAlignMask/, \
12598	(uintptr_t)iemNativeHlpMemFlatMapDataU32Rw, pCallEntry->idxInstr)
12599
12600	#define IEM_MC_MEM_FLAT_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
12601	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu32Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint32_t), \
12602	IEM_ACCESS_DATA_W, sizeof(uint32_t) - 1 /fAlignMask/, \
12603	(uintptr_t)iemNativeHlpMemFlatMapDataU32Wo, pCallEntry->idxInstr) \
12604
12605	#define IEM_MC_MEM_FLAT_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
12606	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu32Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint32_t), \
12607	IEM_ACCESS_DATA_R, sizeof(uint32_t) - 1 /fAlignMask/, \
12608	(uintptr_t)iemNativeHlpMemFlatMapDataU32Ro, pCallEntry->idxInstr)
12609
12610	#define IEM_MC_MEM_FLAT_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_GCPtrMem) \
12611	off = iemNativeEmitMemMapCommon(pReNative, off, a_pi32Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(int32_t), \
12612	IEM_ACCESS_DATA_W, sizeof(uint32_t) - 1 /fAlignMask/, \
12613	(uintptr_t)iemNativeHlpMemFlatMapDataU32Wo, pCallEntry->idxInstr) \
12614
12615
12616	#define IEM_MC_MEM_FLAT_MAP_U64_ATOMIC(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
12617	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu64Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint64_t), \
12618	IEM_ACCESS_DATA_ATOMIC, sizeof(uint64_t) - 1 /fAlignMask/, \
12619	(uintptr_t)iemNativeHlpMemFlatMapDataU64Atomic, pCallEntry->idxInstr)
12620
12621	#define IEM_MC_MEM_FLAT_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
12622	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu64Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint64_t), \
12623	IEM_ACCESS_DATA_RW, sizeof(uint64_t) - 1 /fAlignMask/, \
12624	(uintptr_t)iemNativeHlpMemFlatMapDataU64Rw, pCallEntry->idxInstr)
12625
12626	#define IEM_MC_MEM_FLAT_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
12627	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu64Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint64_t), \
12628	IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1 /fAlignMask/, \
12629	(uintptr_t)iemNativeHlpMemFlatMapDataU64Wo, pCallEntry->idxInstr) \
12630
12631	#define IEM_MC_MEM_FLAT_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
12632	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu64Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(uint64_t), \
12633	IEM_ACCESS_DATA_R, sizeof(uint64_t) - 1 /fAlignMask/, \
12634	(uintptr_t)iemNativeHlpMemFlatMapDataU64Ro, pCallEntry->idxInstr)
12635
12636	#define IEM_MC_MEM_FLAT_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_GCPtrMem) \
12637	off = iemNativeEmitMemMapCommon(pReNative, off, a_pi64Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(int64_t), \
12638	IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1 /fAlignMask/, \
12639	(uintptr_t)iemNativeHlpMemFlatMapDataU64Wo, pCallEntry->idxInstr) \
12640
12641
12642	#define IEM_MC_MEM_FLAT_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_GCPtrMem) \
12643	off = iemNativeEmitMemMapCommon(pReNative, off, a_pr80Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(RTFLOAT80U), \
12644	IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1 /fAlignMask/, \
12645	(uintptr_t)iemNativeHlpMemFlatMapDataR80Wo, pCallEntry->idxInstr) \
12646
12647	#define IEM_MC_MEM_FLAT_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_GCPtrMem) \
12648	off = iemNativeEmitMemMapCommon(pReNative, off, a_pd80Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(RTFLOAT80U), \
12649	IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1 /fAlignMask/, /** @todo check BCD align */ \
12650	(uintptr_t)iemNativeHlpMemFlatMapDataD80Wo, pCallEntry->idxInstr) \
12651
12652
12653	#define IEM_MC_MEM_FLAT_MAP_U128_ATOMIC(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
12654	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu128Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(RTUINT128U), \
12655	IEM_ACCESS_DATA_ATOMIC, sizeof(RTUINT128U) - 1 /fAlignMask/, \
12656	(uintptr_t)iemNativeHlpMemFlatMapDataU128Atomic, pCallEntry->idxInstr)
12657
12658	#define IEM_MC_MEM_FLAT_MAP_U128_RW(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
12659	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu128Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(RTUINT128U), \
12660	IEM_ACCESS_DATA_RW, sizeof(RTUINT128U) - 1 /fAlignMask/, \
12661	(uintptr_t)iemNativeHlpMemFlatMapDataU128Rw, pCallEntry->idxInstr)
12662
12663	#define IEM_MC_MEM_FLAT_MAP_U128_WO(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
12664	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu128Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(RTUINT128U), \
12665	IEM_ACCESS_DATA_W, sizeof(RTUINT128U) - 1 /fAlignMask/, \
12666	(uintptr_t)iemNativeHlpMemFlatMapDataU128Wo, pCallEntry->idxInstr) \
12667
12668	#define IEM_MC_MEM_FLAT_MAP_U128_RO(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
12669	off = iemNativeEmitMemMapCommon(pReNative, off, a_pu128Mem, a_bUnmapInfo, UINT8_MAX, a_GCPtrMem, sizeof(RTUINT128U), \
12670	IEM_ACCESS_DATA_R, sizeof(RTUINT128U) - 1 /fAlignMask/, \
12671	(uintptr_t)iemNativeHlpMemFlatMapDataU128Ro, pCallEntry->idxInstr)
12672
12673
12674	DECL_INLINE_THROW(uint32_t)
12675	iemNativeEmitMemMapCommon(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarMem, uint8_t idxVarUnmapInfo,
12676	uint8_t iSegReg, uint8_t idxVarGCPtrMem, uint8_t cbMem, uint32_t fAccess, uint8_t fAlignMask,
12677	uintptr_t pfnFunction, uint8_t idxInstr)
12678	{
12679	/*
12680	* Assert sanity.
12681	*/
12682	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarMem);
12683	AssertStmt( pReNative->Core.aVars[idxVarMem].enmKind == kIemNativeVarKind_Invalid
12684	&& pReNative->Core.aVars[idxVarMem].cbVar == sizeof(void *),
12685	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_UNEXPECTED_KIND));
12686
12687	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarUnmapInfo);
12688	AssertStmt( pReNative->Core.aVars[idxVarUnmapInfo].enmKind == kIemNativeVarKind_Invalid
12689	&& pReNative->Core.aVars[idxVarUnmapInfo].cbVar == sizeof(uint8_t),
12690	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_UNEXPECTED_KIND));
12691
12692	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarGCPtrMem);
12693	AssertStmt( pReNative->Core.aVars[idxVarGCPtrMem].enmKind == kIemNativeVarKind_Immediate
12694	\|\| pReNative->Core.aVars[idxVarGCPtrMem].enmKind == kIemNativeVarKind_Stack,
12695	IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_VAR_UNEXPECTED_KIND));
12696
12697	Assert(iSegReg < 6 \|\| iSegReg == UINT8_MAX);
12698
12699	AssertCompile(IEMNATIVE_CALL_ARG_GREG_COUNT >= 4);
12700
12701	#ifdef VBOX_STRICT
12702	# define IEM_MAP_HLP_FN_NO_AT(a_fAccess, a_fnBase) \
12703	( ((a_fAccess) & (IEM_ACCESS_TYPE_MASK \| IEM_ACCESS_ATOMIC)) == (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_TYPE_READ) \
12704	? (uintptr_t)RT_CONCAT(a_fnBase,Rw) \
12705	: ((a_fAccess) & (IEM_ACCESS_TYPE_MASK \| IEM_ACCESS_ATOMIC)) == IEM_ACCESS_TYPE_READ \
12706	? (uintptr_t)RT_CONCAT(a_fnBase,Ro) : (uintptr_t)RT_CONCAT(a_fnBase,Wo) )
12707	# define IEM_MAP_HLP_FN(a_fAccess, a_fnBase) \
12708	( ((a_fAccess) & (IEM_ACCESS_TYPE_MASK \| IEM_ACCESS_ATOMIC)) == (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_TYPE_READ \| IEM_ACCESS_ATOMIC) \
12709	? (uintptr_t)RT_CONCAT(a_fnBase,Atomic) \
12710	: IEM_MAP_HLP_FN_NO_AT(a_fAccess, a_fnBase) )
12711
12712	if (iSegReg == UINT8_MAX)
12713	{
12714	Assert( (pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT
12715	\|\| (pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT
12716	\|\| (pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT);
12717	switch (cbMem)
12718	{
12719	case 1: Assert(pfnFunction == IEM_MAP_HLP_FN(fAccess, iemNativeHlpMemFlatMapDataU8)); break;
12720	case 2: Assert(pfnFunction == IEM_MAP_HLP_FN(fAccess, iemNativeHlpMemFlatMapDataU16)); break;
12721	case 4: Assert(pfnFunction == IEM_MAP_HLP_FN(fAccess, iemNativeHlpMemFlatMapDataU32)); break;
12722	case 8: Assert(pfnFunction == IEM_MAP_HLP_FN(fAccess, iemNativeHlpMemFlatMapDataU64)); break;
12723	case 10:
12724	Assert( pfnFunction == (uintptr_t)iemNativeHlpMemFlatMapDataR80Wo
12725	\|\| pfnFunction == (uintptr_t)iemNativeHlpMemFlatMapDataD80Wo);
12726	Assert((fAccess & IEM_ACCESS_TYPE_MASK) == IEM_ACCESS_TYPE_WRITE);
12727	break;
12728	case 16: Assert(pfnFunction == IEM_MAP_HLP_FN(fAccess, iemNativeHlpMemFlatMapDataU128)); break;
12729	# if 0
12730	case 32: Assert(pfnFunction == IEM_MAP_HLP_FN_NO_AT(fAccess, iemNativeHlpMemFlatMapDataU256)); break;
12731	case 64: Assert(pfnFunction == IEM_MAP_HLP_FN_NO_AT(fAccess, iemNativeHlpMemFlatMapDataU512)); break;
12732	# endif
12733	default: AssertFailed(); break;
12734	}
12735	}
12736	else
12737	{
12738	Assert(iSegReg < 6);
12739	switch (cbMem)
12740	{
12741	case 1: Assert(pfnFunction == IEM_MAP_HLP_FN(fAccess, iemNativeHlpMemMapDataU8)); break;
12742	case 2: Assert(pfnFunction == IEM_MAP_HLP_FN(fAccess, iemNativeHlpMemMapDataU16)); break;
12743	case 4: Assert(pfnFunction == IEM_MAP_HLP_FN(fAccess, iemNativeHlpMemMapDataU32)); break;
12744	case 8: Assert(pfnFunction == IEM_MAP_HLP_FN(fAccess, iemNativeHlpMemMapDataU64)); break;
12745	case 10:
12746	Assert( pfnFunction == (uintptr_t)iemNativeHlpMemMapDataR80Wo
12747	\|\| pfnFunction == (uintptr_t)iemNativeHlpMemMapDataD80Wo);
12748	Assert((fAccess & IEM_ACCESS_TYPE_MASK) == IEM_ACCESS_TYPE_WRITE);
12749	break;
12750	case 16: Assert(pfnFunction == IEM_MAP_HLP_FN(fAccess, iemNativeHlpMemMapDataU128)); break;
12751	# if 0
12752	case 32: Assert(pfnFunction == IEM_MAP_HLP_FN_NO_AT(fAccess, iemNativeHlpMemMapDataU256)); break;
12753	case 64: Assert(pfnFunction == IEM_MAP_HLP_FN_NO_AT(fAccess, iemNativeHlpMemMapDataU512)); break;
12754	# endif
12755	default: AssertFailed(); break;
12756	}
12757	}
12758	# undef IEM_MAP_HLP_FN
12759	# undef IEM_MAP_HLP_FN_NO_AT
12760	#endif
12761
12762	#ifdef VBOX_STRICT
12763	/*
12764	* Check that the fExec flags we've got make sense.
12765	*/
12766	off = iemNativeEmitExecFlagsCheck(pReNative, off, pReNative->fExec);
12767	#endif
12768
12769	/*
12770	* To keep things simple we have to commit any pending writes first as we
12771	* may end up making calls.
12772	*/
12773	off = iemNativeRegFlushPendingWrites(pReNative, off);
12774
12775	#ifdef IEMNATIVE_WITH_FREE_AND_FLUSH_VOLATILE_REGS_AT_TLB_LOOKUP
12776	/*
12777	* Move/spill/flush stuff out of call-volatile registers.
12778	* This is the easy way out. We could contain this to the tlb-miss branch
12779	* by saving and restoring active stuff here.
12780	*/
12781	/** @todo save+restore active registers and maybe guest shadows in tlb-miss. */
12782	off = iemNativeRegMoveAndFreeAndFlushAtCall(pReNative, off, 0 /* vacate all non-volatile regs */);
12783	#endif
12784
12785	/* The bUnmapInfo variable will get a register in the tlb-hit code path,
12786	while the tlb-miss codepath will temporarily put it on the stack.
12787	Set the the type to stack here so we don't need to do it twice below. */
12788	iemNativeVarSetKindToStack(pReNative, idxVarUnmapInfo);
12789	uint8_t const idxRegUnmapInfo = iemNativeVarRegisterAcquire(pReNative, idxVarUnmapInfo, &off);
12790	/** @todo use a tmp register from TlbState, since they'll be free after tlb
12791	* lookup is done. */
12792
12793	/*
12794	* Define labels and allocate the result register (trying for the return
12795	* register if we can).
12796	*/
12797	uint16_t const uTlbSeqNo = pReNative->uTlbSeqNo++;
12798	uint8_t const idxRegMemResult = !(pReNative->Core.bmHstRegs & RT_BIT_32(IEMNATIVE_CALL_RET_GREG))
12799	? iemNativeVarRegisterSetAndAcquire(pReNative, idxVarMem, IEMNATIVE_CALL_RET_GREG, &off)
12800	: iemNativeVarRegisterAcquire(pReNative, idxVarMem, &off);
12801	IEMNATIVEEMITTLBSTATE const TlbState(pReNative, &off, idxVarGCPtrMem, iSegReg, cbMem);
12802	uint32_t const idxLabelTlbLookup = !TlbState.fSkip
12803	? iemNativeLabelCreate(pReNative, kIemNativeLabelType_TlbLookup, UINT32_MAX, uTlbSeqNo)
12804	: UINT32_MAX;
12805	//off=iemNativeEmitBrk(pReNative, off, 0);
12806	/*
12807	* Jump to the TLB lookup code.
12808	*/
12809	if (!TlbState.fSkip)
12810	off = iemNativeEmitJmpToLabel(pReNative, off, idxLabelTlbLookup); /** @todo short jump */
12811
12812	/*
12813	* TlbMiss:
12814	*
12815	* Call helper to do the fetching.
12816	* We flush all guest register shadow copies here.
12817	*/
12818	uint32_t const idxLabelTlbMiss = iemNativeLabelCreate(pReNative, kIemNativeLabelType_TlbMiss, off, uTlbSeqNo);
12819
12820	#ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
12821	off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr));
12822	#else
12823	RT_NOREF(idxInstr);
12824	#endif
12825
12826	#ifndef IEMNATIVE_WITH_FREE_AND_FLUSH_VOLATILE_REGS_AT_TLB_LOOKUP
12827	/* Save variables in volatile registers. */
12828	uint32_t const fHstRegsNotToSave = TlbState.getRegsNotToSave() \| RT_BIT_32(idxRegMemResult) \| RT_BIT_32(idxRegUnmapInfo);
12829	off = iemNativeVarSaveVolatileRegsPreHlpCall(pReNative, off, fHstRegsNotToSave);
12830	#endif
12831
12832	/* IEMNATIVE_CALL_ARG2_GREG = GCPtrMem - load first as it is from a variable. */
12833	off = iemNativeEmitLoadArgGregFromImmOrStackVar(pReNative, off, IEMNATIVE_CALL_ARG2_GREG, idxVarGCPtrMem, 0 /cbAppend/,
12834	#ifndef IEMNATIVE_WITH_FREE_AND_FLUSH_VOLATILE_REGS_AT_TLB_LOOKUP
12835	IEMNATIVE_CALL_VOLATILE_GREG_MASK, true /fSpilledVarsInvolatileRegs/);
12836	#else
12837	IEMNATIVE_CALL_VOLATILE_GREG_MASK);
12838	#endif
12839
12840	/* IEMNATIVE_CALL_ARG3_GREG = iSegReg */
12841	if (iSegReg != UINT8_MAX)
12842	{
12843	AssertStmt(iSegReg < 6, IEMNATIVE_DO_LONGJMP(pReNative, VERR_IEM_EMIT_BAD_SEG_REG_NO));
12844	off = iemNativeEmitLoadGpr8Imm(pReNative, off, IEMNATIVE_CALL_ARG3_GREG, iSegReg);
12845	}
12846
12847	/* IEMNATIVE_CALL_ARG1_GREG = &idxVarUnmapInfo; stackslot address, load any register with result after the call. */
12848	int32_t const offBpDispVarUnmapInfo = iemNativeStackCalcBpDisp(iemNativeVarGetStackSlot(pReNative, idxVarUnmapInfo));
12849	off = iemNativeEmitLeaGprByBp(pReNative, off, IEMNATIVE_CALL_ARG1_GREG, offBpDispVarUnmapInfo);
12850
12851	/* IEMNATIVE_CALL_ARG0_GREG = pVCpu */
12852	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
12853
12854	/* Done setting up parameters, make the call. */
12855	off = iemNativeEmitCallImm(pReNative, off, pfnFunction);
12856
12857	/*
12858	* Put the output in the right registers.
12859	*/
12860	Assert(idxRegMemResult == pReNative->Core.aVars[idxVarMem].idxReg);
12861	if (idxRegMemResult != IEMNATIVE_CALL_RET_GREG)
12862	off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxRegMemResult, IEMNATIVE_CALL_RET_GREG);
12863
12864	#ifndef IEMNATIVE_WITH_FREE_AND_FLUSH_VOLATILE_REGS_AT_TLB_LOOKUP
12865	/* Restore variables and guest shadow registers to volatile registers. */
12866	off = iemNativeVarRestoreVolatileRegsPostHlpCall(pReNative, off, fHstRegsNotToSave);
12867	off = iemNativeRegRestoreGuestShadowsInVolatileRegs(pReNative, off, TlbState.getActiveRegsWithShadows());
12868	#endif
12869
12870	Assert(pReNative->Core.aVars[idxVarUnmapInfo].idxReg == idxRegUnmapInfo);
12871	off = iemNativeEmitLoadGprByBpU8(pReNative, off, idxRegUnmapInfo, offBpDispVarUnmapInfo);
12872
12873	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
12874	if (!TlbState.fSkip)
12875	{
12876	/* end of tlbsmiss - Jump to the done label. */
12877	uint32_t const idxLabelTlbDone = iemNativeLabelCreate(pReNative, kIemNativeLabelType_TlbDone, UINT32_MAX, uTlbSeqNo);
12878	off = iemNativeEmitJmpToLabel(pReNative, off, idxLabelTlbDone);
12879
12880	/*
12881	* TlbLookup:
12882	*/
12883	off = iemNativeEmitTlbLookup<true>(pReNative, off, &TlbState, iSegReg, cbMem, fAlignMask, fAccess,
12884	idxLabelTlbLookup, idxLabelTlbMiss, idxRegMemResult);
12885	# ifdef VBOX_WITH_STATISTICS
12886	off = iemNativeEmitIncStamCounterInVCpu(pReNative, off, TlbState.idxReg1, TlbState.idxReg2,
12887	RT_UOFFSETOF(VMCPUCC, iem.s.StatNativeTlbHitsForMapped));
12888	# endif
12889
12890	/* [idxVarUnmapInfo] = 0; */
12891	off = iemNativeEmitLoadGprImm32(pReNative, off, idxRegUnmapInfo, 0);
12892
12893	/*
12894	* TlbDone:
12895	*/
12896	iemNativeLabelDefine(pReNative, idxLabelTlbDone, off);
12897
12898	TlbState.freeRegsAndReleaseVars(pReNative, idxVarGCPtrMem);
12899
12900	# ifndef IEMNATIVE_WITH_FREE_AND_FLUSH_VOLATILE_REGS_AT_TLB_LOOKUP
12901	/* Temp Hack: Flush all guest shadows in volatile registers in case of TLB miss. */
12902	iemNativeRegFlushGuestShadowsByHostMask(pReNative, IEMNATIVE_CALL_VOLATILE_GREG_MASK);
12903	# endif
12904	}
12905	#else
12906	RT_NOREF(fAccess, fAlignMask, idxLabelTlbMiss);
12907	#endif
12908
12909	iemNativeVarRegisterRelease(pReNative, idxVarUnmapInfo);
12910	iemNativeVarRegisterRelease(pReNative, idxVarMem);
12911
12912	return off;
12913	}
12914
12915
12916	#define IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(a_bMapInfo) \
12917	off = iemNativeEmitMemCommitAndUnmap(pReNative, off, (a_bMapInfo), IEM_ACCESS_DATA_ATOMIC, \
12918	(uintptr_t)iemNativeHlpMemCommitAndUnmapAtomic, pCallEntry->idxInstr)
12919
12920	#define IEM_MC_MEM_COMMIT_AND_UNMAP_RW(a_bMapInfo) \
12921	off = iemNativeEmitMemCommitAndUnmap(pReNative, off, (a_bMapInfo), IEM_ACCESS_DATA_RW, \
12922	(uintptr_t)iemNativeHlpMemCommitAndUnmapRw, pCallEntry->idxInstr)
12923
12924	#define IEM_MC_MEM_COMMIT_AND_UNMAP_WO(a_bMapInfo) \
12925	off = iemNativeEmitMemCommitAndUnmap(pReNative, off, (a_bMapInfo), IEM_ACCESS_DATA_W, \
12926	(uintptr_t)iemNativeHlpMemCommitAndUnmapWo, pCallEntry->idxInstr)
12927
12928	#define IEM_MC_MEM_COMMIT_AND_UNMAP_RO(a_bMapInfo) \
12929	off = iemNativeEmitMemCommitAndUnmap(pReNative, off, (a_bMapInfo), IEM_ACCESS_DATA_R, \
12930	(uintptr_t)iemNativeHlpMemCommitAndUnmapRo, pCallEntry->idxInstr)
12931
12932	DECL_INLINE_THROW(uint32_t)
12933	iemNativeEmitMemCommitAndUnmap(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarUnmapInfo,
12934	uint32_t fAccess, uintptr_t pfnFunction, uint8_t idxInstr)
12935	{
12936	/*
12937	* Assert sanity.
12938	*/
12939	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarUnmapInfo);
12940	Assert(pReNative->Core.aVars[idxVarUnmapInfo].enmKind == kIemNativeVarKind_Stack);
12941	Assert( pReNative->Core.aVars[idxVarUnmapInfo].idxReg < RT_ELEMENTS(pReNative->Core.aHstRegs)
12942	\|\| pReNative->Core.aVars[idxVarUnmapInfo].idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS); /* must be initialized */
12943	#ifdef VBOX_STRICT
12944	switch (fAccess & (IEM_ACCESS_TYPE_MASK \| IEM_ACCESS_ATOMIC))
12945	{
12946	case IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_ATOMIC:
12947	Assert(pfnFunction == (uintptr_t)iemNativeHlpMemCommitAndUnmapAtomic); break;
12948	case IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE:
12949	Assert(pfnFunction == (uintptr_t)iemNativeHlpMemCommitAndUnmapRw); break;
12950	case IEM_ACCESS_TYPE_WRITE:
12951	Assert(pfnFunction == (uintptr_t)iemNativeHlpMemCommitAndUnmapWo); break;
12952	case IEM_ACCESS_TYPE_READ:
12953	Assert(pfnFunction == (uintptr_t)iemNativeHlpMemCommitAndUnmapRo); break;
12954	default: AssertFailed();
12955	}
12956	#else
12957	RT_NOREF(fAccess);
12958	#endif
12959
12960	/*
12961	* To keep things simple we have to commit any pending writes first as we
12962	* may end up making calls (there shouldn't be any at this point, so this
12963	* is just for consistency).
12964	*/
12965	/** @todo we could postpone this till we make the call and reload the
12966	* registers after returning from the call. Not sure if that's sensible or
12967	* not, though. */
12968	off = iemNativeRegFlushPendingWrites(pReNative, off);
12969
12970	/*
12971	* Move/spill/flush stuff out of call-volatile registers.
12972	*
12973	* We exclude any register holding the bUnmapInfo variable, as we'll be
12974	* checking it after returning from the call and will free it afterwards.
12975	*/
12976	/** @todo save+restore active registers and maybe guest shadows in miss
12977	* scenario. */
12978	off = iemNativeRegMoveAndFreeAndFlushAtCall(pReNative, off, 0 /* vacate all non-volatile regs */, RT_BIT_32(idxVarUnmapInfo));
12979
12980	/*
12981	* If idxVarUnmapInfo is zero, we can skip all this. Otherwise we'll have
12982	* to call the unmap helper function.
12983	*
12984	* The likelyhood of it being zero is higher than for the TLB hit when doing
12985	* the mapping, as a TLB miss for an well aligned and unproblematic memory
12986	* access should also end up with a mapping that won't need special unmapping.
12987	*/
12988	/** @todo Go over iemMemMapJmp and implement the no-unmap-needed case! That
12989	* should speed up things for the pure interpreter as well when TLBs
12990	* are enabled. */
12991	#ifdef RT_ARCH_AMD64
12992	if (pReNative->Core.aVars[idxVarUnmapInfo].idxReg == UINT8_MAX)
12993	{
12994	/* test byte [rbp - xxx], 0ffh */
12995	uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 7);
12996	pbCodeBuf[off++] = 0xf6;
12997	uint8_t const idxStackSlot = pReNative->Core.aVars[idxVarUnmapInfo].idxStackSlot;
12998	off = iemNativeEmitGprByBpDisp(pbCodeBuf, off, 0, iemNativeStackCalcBpDisp(idxStackSlot), pReNative);
12999	pbCodeBuf[off++] = 0xff;
13000	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
13001	}
13002	else
13003	#endif
13004	{
13005	uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxVarUnmapInfo, &off,
13006	true /fInitialized/, IEMNATIVE_CALL_ARG1_GREG /idxRegPref/);
13007	off = iemNativeEmitTestAnyBitsInGpr8(pReNative, off, idxVarReg, 0xff);
13008	iemNativeVarRegisterRelease(pReNative, idxVarUnmapInfo);
13009	}
13010	uint32_t const offJmpFixup = off;
13011	off = iemNativeEmitJzToFixed(pReNative, off, off /* ASSUME jz rel8 suffices*/);
13012
13013	/*
13014	* Call the unmap helper function.
13015	*/
13016	#ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING /** @todo This should be unnecessary, the mapping call will already have set it! */
13017	off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr));
13018	#else
13019	RT_NOREF(idxInstr);
13020	#endif
13021
13022	/* IEMNATIVE_CALL_ARG1_GREG = idxVarUnmapInfo (first!) */
13023	off = iemNativeEmitLoadArgGregFromStackVar(pReNative, off, IEMNATIVE_CALL_ARG1_GREG, idxVarUnmapInfo,
13024	0 /offAddend/, IEMNATIVE_CALL_VOLATILE_GREG_MASK);
13025
13026	/* IEMNATIVE_CALL_ARG0_GREG = pVCpu */
13027	off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU);
13028
13029	/* Done setting up parameters, make the call. */
13030	off = iemNativeEmitCallImm(pReNative, off, pfnFunction);
13031
13032	/* The bUnmapInfo variable is implictly free by these MCs. */
13033	iemNativeVarFreeLocal(pReNative, idxVarUnmapInfo);
13034
13035	/*
13036	* Done, just fixup the jump for the non-call case.
13037	*/
13038	iemNativeFixupFixedJump(pReNative, offJmpFixup, off);
13039
13040	return off;
13041	}
13042
13043
13044
13045	/*********************************************************************************************************************************
13046	* State and Exceptions *
13047	*********************************************************************************************************************************/
13048
13049	#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() off = iemNativeEmitPrepareFpuForUse(pReNative, off, true /fForChange/)
13050	#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() off = iemNativeEmitPrepareFpuForUse(pReNative, off, false /fForChange/)
13051
13052	#define IEM_MC_PREPARE_SSE_USAGE() off = iemNativeEmitPrepareFpuForUse(pReNative, off, true /fForChange/)
13053	#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() off = iemNativeEmitPrepareFpuForUse(pReNative, off, true /fForChange/)
13054	#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() off = iemNativeEmitPrepareFpuForUse(pReNative, off, false /fForChange/)
13055
13056	#define IEM_MC_PREPARE_AVX_USAGE() off = iemNativeEmitPrepareFpuForUse(pReNative, off, true /fForChange/)
13057	#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() off = iemNativeEmitPrepareFpuForUse(pReNative, off, true /fForChange/)
13058	#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() off = iemNativeEmitPrepareFpuForUse(pReNative, off, false /fForChange/)
13059
13060
13061	DECL_INLINE_THROW(uint32_t) iemNativeEmitPrepareFpuForUse(PIEMRECOMPILERSTATE pReNative, uint32_t off, bool fForChange)
13062	{
13063	/** @todo this needs a lot more work later. */
13064	RT_NOREF(pReNative, fForChange);
13065	return off;
13066	}
13067
13068
13069	/*********************************************************************************************************************************
13070	* The native code generator functions for each MC block. *
13071	*********************************************************************************************************************************/
13072
13073
13074	/*
13075	* Include g_apfnIemNativeRecompileFunctions and associated functions.
13076	*
13077	* This should probably live in it's own file later, but lets see what the
13078	* compile times turn out to be first.
13079	*/
13080	#include "IEMNativeFunctions.cpp.h"
13081
13082
13083
13084	/*********************************************************************************************************************************
13085	* Recompiler Core. *
13086	*********************************************************************************************************************************/
13087
13088
13089	/** @callback_method_impl{FNDISREADBYTES, Dummy.} */
13090	static DECLCALLBACK(int) iemNativeDisasReadBytesDummy(PDISSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
13091	{
13092	RT_BZERO(&pDis->Instr.ab[offInstr], cbMaxRead);
13093	pDis->cbCachedInstr += cbMaxRead;
13094	RT_NOREF(cbMinRead);
13095	return VERR_NO_DATA;
13096	}
13097
13098
13099	/**
13100	* Formats TB flags (IEM_F_XXX and IEMTB_F_XXX) to string.
13101	* @returns pszBuf.
13102	* @param fFlags The flags.
13103	* @param pszBuf The output buffer.
13104	* @param cbBuf The output buffer size. At least 32 bytes.
13105	*/
13106	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT
13107	{
13108	Assert(cbBuf >= 32);
13109	static RTSTRTUPLE const s_aModes[] =
13110	{
13111	/* [00] = */ { RT_STR_TUPLE("16BIT") },
13112	/* [01] = */ { RT_STR_TUPLE("32BIT") },
13113	/* [02] = */ { RT_STR_TUPLE("!2!") },
13114	/* [03] = */ { RT_STR_TUPLE("!3!") },
13115	/* [04] = */ { RT_STR_TUPLE("16BIT_PRE_386") },
13116	/* [05] = */ { RT_STR_TUPLE("32BIT_FLAT") },
13117	/* [06] = */ { RT_STR_TUPLE("!6!") },
13118	/* [07] = */ { RT_STR_TUPLE("!7!") },
13119	/* [08] = */ { RT_STR_TUPLE("16BIT_PROT") },
13120	/* [09] = */ { RT_STR_TUPLE("32BIT_PROT") },
13121	/* [0a] = */ { RT_STR_TUPLE("64BIT") },
13122	/* [0b] = */ { RT_STR_TUPLE("!b!") },
13123	/* [0c] = */ { RT_STR_TUPLE("16BIT_PROT_PRE_386") },
13124	/* [0d] = */ { RT_STR_TUPLE("32BIT_PROT_FLAT") },
13125	/* [0e] = */ { RT_STR_TUPLE("!e!") },
13126	/* [0f] = */ { RT_STR_TUPLE("!f!") },
13127	/* [10] = */ { RT_STR_TUPLE("!10!") },
13128	/* [11] = */ { RT_STR_TUPLE("!11!") },
13129	/* [12] = */ { RT_STR_TUPLE("!12!") },
13130	/* [13] = */ { RT_STR_TUPLE("!13!") },
13131	/* [14] = */ { RT_STR_TUPLE("!14!") },
13132	/* [15] = */ { RT_STR_TUPLE("!15!") },
13133	/* [16] = */ { RT_STR_TUPLE("!16!") },
13134	/* [17] = */ { RT_STR_TUPLE("!17!") },
13135	/* [18] = */ { RT_STR_TUPLE("16BIT_PROT_V86") },
13136	/* [19] = */ { RT_STR_TUPLE("32BIT_PROT_V86") },
13137	/* [1a] = */ { RT_STR_TUPLE("!1a!") },
13138	/* [1b] = */ { RT_STR_TUPLE("!1b!") },
13139	/* [1c] = */ { RT_STR_TUPLE("!1c!") },
13140	/* [1d] = */ { RT_STR_TUPLE("!1d!") },
13141	/* [1e] = */ { RT_STR_TUPLE("!1e!") },
13142	/* [1f] = */ { RT_STR_TUPLE("!1f!") },
13143	};
13144	AssertCompile(RT_ELEMENTS(s_aModes) == IEM_F_MODE_MASK + 1);
13145	memcpy(pszBuf, s_aModes[fFlags & IEM_F_MODE_MASK].psz, s_aModes[fFlags & IEM_F_MODE_MASK].cch);
13146	size_t off = s_aModes[fFlags & IEM_F_MODE_MASK].cch;
13147
13148	pszBuf[off++] = ' ';
13149	pszBuf[off++] = 'C';
13150	pszBuf[off++] = 'P';
13151	pszBuf[off++] = 'L';
13152	pszBuf[off++] = '0' + ((fFlags >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK);
13153	Assert(off < 32);
13154
13155	fFlags &= ~(IEM_F_MODE_MASK \| IEM_F_X86_CPL_SMASK);
13156
13157	static struct { const char *pszName; uint32_t cchName; uint32_t fFlag; } const s_aFlags[] =
13158	{
13159	{ RT_STR_TUPLE("BYPASS_HANDLERS"), IEM_F_BYPASS_HANDLERS },
13160	{ RT_STR_TUPLE("PENDING_BRK_INSTR"), IEM_F_PENDING_BRK_INSTR },
13161	{ RT_STR_TUPLE("PENDING_BRK_DATA"), IEM_F_PENDING_BRK_DATA },
13162	{ RT_STR_TUPLE("PENDING_BRK_X86_IO"), IEM_F_PENDING_BRK_X86_IO },
13163	{ RT_STR_TUPLE("X86_DISREGARD_LOCK"), IEM_F_X86_DISREGARD_LOCK },
13164	{ RT_STR_TUPLE("X86_CTX_VMX"), IEM_F_X86_CTX_VMX },
13165	{ RT_STR_TUPLE("X86_CTX_SVM"), IEM_F_X86_CTX_SVM },
13166	{ RT_STR_TUPLE("X86_CTX_IN_GUEST"), IEM_F_X86_CTX_IN_GUEST },
13167	{ RT_STR_TUPLE("X86_CTX_SMM"), IEM_F_X86_CTX_SMM },
13168	{ RT_STR_TUPLE("INHIBIT_SHADOW"), IEMTB_F_INHIBIT_SHADOW },
13169	{ RT_STR_TUPLE("INHIBIT_NMI"), IEMTB_F_INHIBIT_NMI },
13170	{ RT_STR_TUPLE("CS_LIM_CHECKS"), IEMTB_F_CS_LIM_CHECKS },
13171	{ RT_STR_TUPLE("TYPE_THREADED"), IEMTB_F_TYPE_THREADED },
13172	{ RT_STR_TUPLE("TYPE_NATIVE"), IEMTB_F_TYPE_NATIVE },
13173	};
13174	if (fFlags)
13175	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
13176	if (s_aFlags[i].fFlag & fFlags)
13177	{
13178	AssertReturnStmt(off + 1 + s_aFlags[i].cchName + 1 <= cbBuf, pszBuf[off] = '\0', pszBuf);
13179	pszBuf[off++] = ' ';
13180	memcpy(&pszBuf[off], s_aFlags[i].pszName, s_aFlags[i].cchName);
13181	off += s_aFlags[i].cchName;
13182	fFlags &= ~s_aFlags[i].fFlag;
13183	if (!fFlags)
13184	break;
13185	}
13186	pszBuf[off] = '\0';
13187
13188	return pszBuf;
13189	}
13190
13191
13192	DECLHIDDEN(void) iemNativeDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT
13193	{
13194	AssertReturnVoid((pTb->fFlags & IEMTB_F_TYPE_MASK) == IEMTB_F_TYPE_NATIVE);
13195	#if defined(RT_ARCH_AMD64)
13196	static const char * const a_apszMarkers[] =
13197	{
13198	/[0]=/ "unknown0", "CheckCsLim", "ConsiderLimChecking", "CheckOpcodes",
13199	/[4]=/ "PcAfterBranch", "LoadTlbForNewPage", "LoadTlbAfterBranch"
13200	};
13201	#endif
13202
13203	char szDisBuf[512];
13204	DISSTATE Dis;
13205	PCIEMNATIVEINSTR const paNative = pTb->Native.paInstructions;
13206	uint32_t const cNative = pTb->Native.cInstructions;
13207	uint32_t offNative = 0;
13208	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
13209	PCIEMTBDBG const pDbgInfo = pTb->pDbgInfo;
13210	#endif
13211	DISCPUMODE enmGstCpuMode = (pTb->fFlags & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT ? DISCPUMODE_16BIT
13212	: (pTb->fFlags & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT ? DISCPUMODE_32BIT
13213	: DISCPUMODE_64BIT;
13214	#if defined(RT_ARCH_AMD64) && !defined(VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER)
13215	DISCPUMODE const enmHstCpuMode = DISCPUMODE_64BIT;
13216	#elif defined(RT_ARCH_ARM64) && !defined(VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER)
13217	DISCPUMODE const enmHstCpuMode = DISCPUMODE_ARMV8_A64;
13218	#elif !defined(VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER)
13219	# error "Port me"
13220	#else
13221	csh hDisasm = ~(size_t)0;
13222	# if defined(RT_ARCH_AMD64)
13223	cs_err rcCs = cs_open(CS_ARCH_X86, CS_MODE_LITTLE_ENDIAN \| CS_MODE_64, &hDisasm);
13224	# elif defined(RT_ARCH_ARM64)
13225	cs_err rcCs = cs_open(CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, &hDisasm);
13226	# else
13227	# error "Port me"
13228	# endif
13229	AssertMsgReturnVoid(rcCs == CS_ERR_OK, ("%d (%#x)\n", rcCs, rcCs));
13230	#endif
13231
13232	/*
13233	* Print TB info.
13234	*/
13235	pHlp->pfnPrintf(pHlp,
13236	"pTb=%p: GCPhysPc=%RGp cInstructions=%u LB %#x cRanges=%u\n"
13237	"pTb=%p: cUsed=%u msLastUsed=%u fFlags=%#010x %s\n",
13238	pTb, pTb->GCPhysPc, pTb->cInstructions, pTb->cbOpcodes, pTb->cRanges,
13239	pTb, pTb->cUsed, pTb->msLastUsed, pTb->fFlags, iemTbFlagsToString(pTb->fFlags, szDisBuf, sizeof(szDisBuf)));
13240	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
13241	if (pDbgInfo && pDbgInfo->cEntries > 1)
13242	{
13243	Assert(pDbgInfo->aEntries[0].Gen.uType == kIemTbDbgEntryType_NativeOffset);
13244
13245	/*
13246	* This disassembly is driven by the debug info which follows the native
13247	* code and indicates when it starts with the next guest instructions,
13248	* where labels are and such things.
13249	*/
13250	uint32_t idxThreadedCall = 0;
13251	uint32_t fExec = pTb->fFlags & UINT32_C(0x00ffffff);
13252	uint8_t idxRange = UINT8_MAX;
13253	uint8_t const cRanges = RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges));
13254	uint32_t offRange = 0;
13255	uint32_t offOpcodes = 0;
13256	uint32_t const cbOpcodes = pTb->cbOpcodes;
13257	RTGCPHYS GCPhysPc = pTb->GCPhysPc;
13258	uint32_t const cDbgEntries = pDbgInfo->cEntries;
13259	uint32_t iDbgEntry = 1;
13260	uint32_t offDbgNativeNext = pDbgInfo->aEntries[0].NativeOffset.offNative;
13261
13262	while (offNative < cNative)
13263	{
13264	/* If we're at or have passed the point where the next chunk of debug
13265	info starts, process it. */
13266	if (offDbgNativeNext <= offNative)
13267	{
13268	offDbgNativeNext = UINT32_MAX;
13269	for (; iDbgEntry < cDbgEntries; iDbgEntry++)
13270	{
13271	switch (pDbgInfo->aEntries[iDbgEntry].Gen.uType)
13272	{
13273	case kIemTbDbgEntryType_GuestInstruction:
13274	{
13275	/* Did the exec flag change? */
13276	if (fExec != pDbgInfo->aEntries[iDbgEntry].GuestInstruction.fExec)
13277	{
13278	pHlp->pfnPrintf(pHlp,
13279	" fExec change %#08x -> %#08x %s\n",
13280	fExec, pDbgInfo->aEntries[iDbgEntry].GuestInstruction.fExec,
13281	iemTbFlagsToString(pDbgInfo->aEntries[iDbgEntry].GuestInstruction.fExec,
13282	szDisBuf, sizeof(szDisBuf)));
13283	fExec = pDbgInfo->aEntries[iDbgEntry].GuestInstruction.fExec;
13284	enmGstCpuMode = (fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT ? DISCPUMODE_16BIT
13285	: (fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT ? DISCPUMODE_32BIT
13286	: DISCPUMODE_64BIT;
13287	}
13288
13289	/* New opcode range? We need to fend up a spurious debug info entry here for cases
13290	where the compilation was aborted before the opcode was recorded and the actual
13291	instruction was translated to a threaded call. This may happen when we run out
13292	of ranges, or when some complicated interrupts/FFs are found to be pending or
13293	similar. So, we just deal with it here rather than in the compiler code as it
13294	is a lot simpler to do here. */
13295	if ( idxRange == UINT8_MAX
13296	\|\| idxRange >= cRanges
13297	\|\| offRange >= pTb->aRanges[idxRange].cbOpcodes)
13298	{
13299	idxRange += 1;
13300	if (idxRange < cRanges)
13301	offRange = !idxRange ? 0 : offRange - pTb->aRanges[idxRange - 1].cbOpcodes;
13302	else
13303	continue;
13304	Assert(offOpcodes == pTb->aRanges[idxRange].offOpcodes + offRange);
13305	GCPhysPc = pTb->aRanges[idxRange].offPhysPage
13306	+ (pTb->aRanges[idxRange].idxPhysPage == 0
13307	? pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK
13308	: pTb->aGCPhysPages[pTb->aRanges[idxRange].idxPhysPage - 1]);
13309	pHlp->pfnPrintf(pHlp, " Range #%u: GCPhysPc=%RGp LB %#x [idxPg=%d]\n",
13310	idxRange, GCPhysPc, pTb->aRanges[idxRange].cbOpcodes,
13311	pTb->aRanges[idxRange].idxPhysPage);
13312	GCPhysPc += offRange;
13313	}
13314
13315	/* Disassemble the instruction. */
13316	//uint8_t const cbInstrMax = RT_MIN(pTb->aRanges[idxRange].cbOpcodes - offRange, 15);
13317	uint8_t const cbInstrMax = RT_MIN(cbOpcodes - offOpcodes, 15);
13318	uint32_t cbInstr = 1;
13319	int rc = DISInstrWithPrefetchedBytes(GCPhysPc, enmGstCpuMode, DISOPTYPE_ALL,
13320	&pTb->pabOpcodes[offOpcodes], cbInstrMax,
13321	iemNativeDisasReadBytesDummy, NULL, &Dis, &cbInstr);
13322	if (RT_SUCCESS(rc))
13323	{
13324	size_t cch = DISFormatYasmEx(&Dis, szDisBuf, sizeof(szDisBuf),
13325	DIS_FMT_FLAGS_BYTES_WIDTH_MAKE(10) \| DIS_FMT_FLAGS_BYTES_LEFT
13326	\| DIS_FMT_FLAGS_RELATIVE_BRANCH \| DIS_FMT_FLAGS_C_HEX,
13327	NULL /pfnGetSymbol/, NULL /pvUser/);
13328
13329	static unsigned const s_offMarker = 55;
13330	static char const s_szMarker[] = " ; <--- guest";
13331	if (cch < s_offMarker)
13332	{
13333	memset(&szDisBuf[cch], ' ', s_offMarker - cch);
13334	cch = s_offMarker;
13335	}
13336	if (cch + sizeof(s_szMarker) <= sizeof(szDisBuf))
13337	memcpy(&szDisBuf[cch], s_szMarker, sizeof(s_szMarker));
13338
13339	pHlp->pfnPrintf(pHlp, " %%%%%RGp: %s\n", GCPhysPc, szDisBuf);
13340	}
13341	else
13342	{
13343	pHlp->pfnPrintf(pHlp, " %%%%%RGp: %.*Rhxs - guest disassembly failure %Rrc\n",
13344	GCPhysPc, cbInstrMax, &pTb->pabOpcodes[offOpcodes], rc);
13345	cbInstr = 1;
13346	}
13347	GCPhysPc += cbInstr;
13348	offOpcodes += cbInstr;
13349	offRange += cbInstr;
13350	continue;
13351	}
13352
13353	case kIemTbDbgEntryType_ThreadedCall:
13354	pHlp->pfnPrintf(pHlp,
13355	" Call #%u to %s (%u args) - %s\n",
13356	idxThreadedCall,
13357	g_apszIemThreadedFunctions[pDbgInfo->aEntries[iDbgEntry].ThreadedCall.enmCall],
13358	g_acIemThreadedFunctionUsedArgs[pDbgInfo->aEntries[iDbgEntry].ThreadedCall.enmCall],
13359	pDbgInfo->aEntries[iDbgEntry].ThreadedCall.fRecompiled ? "recompiled" : "todo");
13360	idxThreadedCall++;
13361	continue;
13362
13363	case kIemTbDbgEntryType_GuestRegShadowing:
13364	{
13365	PCIEMTBDBGENTRY const pEntry = &pDbgInfo->aEntries[iDbgEntry];
13366	const char * const pszGstReg = g_aGstShadowInfo[pEntry->GuestRegShadowing.idxGstReg].pszName;
13367	if (pEntry->GuestRegShadowing.idxHstReg == UINT8_MAX)
13368	pHlp->pfnPrintf(pHlp, " Guest register %s != host register %s\n", pszGstReg,
13369	g_apszIemNativeHstRegNames[pEntry->GuestRegShadowing.idxHstRegPrev]);
13370	else if (pEntry->GuestRegShadowing.idxHstRegPrev == UINT8_MAX)
13371	pHlp->pfnPrintf(pHlp, " Guest register %s == host register %s\n", pszGstReg,
13372	g_apszIemNativeHstRegNames[pEntry->GuestRegShadowing.idxHstReg]);
13373	else
13374	pHlp->pfnPrintf(pHlp, " Guest register %s == host register %s (previously in %s)\n", pszGstReg,
13375	g_apszIemNativeHstRegNames[pEntry->GuestRegShadowing.idxHstReg],
13376	g_apszIemNativeHstRegNames[pEntry->GuestRegShadowing.idxHstRegPrev]);
13377	continue;
13378	}
13379
13380	case kIemTbDbgEntryType_Label:
13381	{
13382	const char *pszName = "what_the_fudge";
13383	const char *pszComment = "";
13384	bool fNumbered = pDbgInfo->aEntries[iDbgEntry].Label.uData != 0;
13385	switch ((IEMNATIVELABELTYPE)pDbgInfo->aEntries[iDbgEntry].Label.enmLabel)
13386	{
13387	case kIemNativeLabelType_Return:
13388	pszName = "Return";
13389	break;
13390	case kIemNativeLabelType_ReturnBreak:
13391	pszName = "ReturnBreak";
13392	break;
13393	case kIemNativeLabelType_ReturnWithFlags:
13394	pszName = "ReturnWithFlags";
13395	break;
13396	case kIemNativeLabelType_NonZeroRetOrPassUp:
13397	pszName = "NonZeroRetOrPassUp";
13398	break;
13399	case kIemNativeLabelType_RaiseGp0:
13400	pszName = "RaiseGp0";
13401	break;
13402	case kIemNativeLabelType_ObsoleteTb:
13403	pszName = "ObsoleteTb";
13404	break;
13405	case kIemNativeLabelType_NeedCsLimChecking:
13406	pszName = "NeedCsLimChecking";
13407	break;
13408	case kIemNativeLabelType_CheckBranchMiss:
13409	pszName = "CheckBranchMiss";
13410	break;
13411	case kIemNativeLabelType_If:
13412	pszName = "If";
13413	fNumbered = true;
13414	break;
13415	case kIemNativeLabelType_Else:
13416	pszName = "Else";
13417	fNumbered = true;
13418	pszComment = " ; regs state restored pre-if-block";
13419	break;
13420	case kIemNativeLabelType_Endif:
13421	pszName = "Endif";
13422	fNumbered = true;
13423	break;
13424	case kIemNativeLabelType_CheckIrq:
13425	pszName = "CheckIrq_CheckVM";
13426	fNumbered = true;
13427	break;
13428	case kIemNativeLabelType_TlbLookup:
13429	pszName = "TlbLookup";
13430	fNumbered = true;
13431	break;
13432	case kIemNativeLabelType_TlbMiss:
13433	pszName = "TlbMiss";
13434	fNumbered = true;
13435	break;
13436	case kIemNativeLabelType_TlbDone:
13437	pszName = "TlbDone";
13438	fNumbered = true;
13439	break;
13440	case kIemNativeLabelType_Invalid:
13441	case kIemNativeLabelType_End:
13442	break;
13443	}
13444	if (fNumbered)
13445	pHlp->pfnPrintf(pHlp, " %s_%u:%s\n", pszName, pDbgInfo->aEntries[iDbgEntry].Label.uData, pszComment);
13446	else
13447	pHlp->pfnPrintf(pHlp, " %s:\n", pszName);
13448	continue;
13449	}
13450
13451	case kIemTbDbgEntryType_NativeOffset:
13452	offDbgNativeNext = pDbgInfo->aEntries[iDbgEntry].NativeOffset.offNative;
13453	Assert(offDbgNativeNext > offNative);
13454	break;
13455
13456	default:
13457	AssertFailed();
13458	}
13459	iDbgEntry++;
13460	break;
13461	}
13462	}
13463
13464	/*
13465	* Disassemble the next native instruction.
13466	*/
13467	PCIEMNATIVEINSTR const pNativeCur = &paNative[offNative];
13468	# ifndef VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER
13469	uint32_t cbInstr = sizeof(paNative[0]);
13470	int const rc = DISInstr(pNativeCur, enmHstCpuMode, &Dis, &cbInstr);
13471	if (RT_SUCCESS(rc))
13472	{
13473	# if defined(RT_ARCH_AMD64)
13474	if (Dis.pCurInstr->uOpcode == OP_NOP && cbInstr == 7) /* iemNativeEmitMarker */
13475	{
13476	uint32_t const uInfo = (uint32_t const )&Dis.Instr.ab[3];
13477	if (RT_HIWORD(uInfo) < kIemThreadedFunc_End)
13478	pHlp->pfnPrintf(pHlp, " %p: nop ; marker: call #%u to %s (%u args) - %s\n",
13479	pNativeCur, uInfo & 0x7fff, g_apszIemThreadedFunctions[RT_HIWORD(uInfo)],
13480	g_acIemThreadedFunctionUsedArgs[RT_HIWORD(uInfo)],
13481	uInfo & 0x8000 ? "recompiled" : "todo");
13482	else if ((uInfo & ~RT_BIT_32(31)) < RT_ELEMENTS(a_apszMarkers))
13483	pHlp->pfnPrintf(pHlp, " %p: nop ; marker: %s\n", pNativeCur, a_apszMarkers[uInfo & ~RT_BIT_32(31)]);
13484	else
13485	pHlp->pfnPrintf(pHlp, " %p: nop ; unknown marker: %#x (%d)\n", pNativeCur, uInfo, uInfo);
13486	}
13487	else
13488	# endif
13489	{
13490	# ifdef RT_ARCH_AMD64
13491	DISFormatYasmEx(&Dis, szDisBuf, sizeof(szDisBuf),
13492	DIS_FMT_FLAGS_BYTES_WIDTH_MAKE(10) \| DIS_FMT_FLAGS_BYTES_LEFT
13493	\| DIS_FMT_FLAGS_RELATIVE_BRANCH \| DIS_FMT_FLAGS_C_HEX,
13494	NULL /pfnGetSymbol/, NULL /pvUser/);
13495	# elif defined(RT_ARCH_ARM64)
13496	DISFormatArmV8Ex(&Dis, szDisBuf, sizeof(szDisBuf),
13497	DIS_FMT_FLAGS_BYTES_LEFT \| DIS_FMT_FLAGS_RELATIVE_BRANCH \| DIS_FMT_FLAGS_C_HEX,
13498	NULL /pfnGetSymbol/, NULL /pvUser/);
13499	# else
13500	# error "Port me"
13501	# endif
13502	pHlp->pfnPrintf(pHlp, " %p: %s\n", pNativeCur, szDisBuf);
13503	}
13504	}
13505	else
13506	{
13507	# if defined(RT_ARCH_AMD64)
13508	pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs - disassembly failure %Rrc\n",
13509	pNativeCur, RT_MIN(cNative - offNative, 16), pNativeCur, rc);
13510	# elif defined(RT_ARCH_ARM64)
13511	pHlp->pfnPrintf(pHlp, " %p: %#010RX32 - disassembly failure %Rrc\n", pNativeCur, *pNativeCur, rc);
13512	# else
13513	# error "Port me"
13514	# endif
13515	cbInstr = sizeof(paNative[0]);
13516	}
13517	offNative += cbInstr / sizeof(paNative[0]);
13518
13519	# else /* VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER */
13520	cs_insn *pInstr;
13521	size_t cInstrs = cs_disasm(hDisasm, (const uint8_t )pNativeCur, (cNative - offNative) sizeof(*pNativeCur),
13522	(uintptr_t)pNativeCur, 1, &pInstr);
13523	if (cInstrs > 0)
13524	{
13525	Assert(cInstrs == 1);
13526	# if defined(RT_ARCH_AMD64)
13527	pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs %-7s %s\n",
13528	pNativeCur, pInstr->size, pNativeCur, pInstr->mnemonic, pInstr->op_str);
13529	# else
13530	pHlp->pfnPrintf(pHlp, " %p: %#010RX32 %-7s %s\n",
13531	pNativeCur, *pNativeCur, pInstr->mnemonic, pInstr->op_str);
13532	# endif
13533	offNative += pInstr->size / sizeof(*pNativeCur);
13534	cs_free(pInstr, cInstrs);
13535	}
13536	else
13537	{
13538	# if defined(RT_ARCH_AMD64)
13539	pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs - disassembly failure %d\n",
13540	pNativeCur, RT_MIN(cNative - offNative, 16), pNativeCur, cs_errno(hDisasm)));
13541	# else
13542	pHlp->pfnPrintf(pHlp, " %p: %#010RX32 - disassembly failure %d\n", pNativeCur, *pNativeCur, cs_errno(hDisasm));
13543	# endif
13544	offNative++;
13545	}
13546	# endif /* VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER */
13547	}
13548	}
13549	else
13550	#endif /* IEMNATIVE_WITH_TB_DEBUG_INFO */
13551	{
13552	/*
13553	* No debug info, just disassemble the x86 code and then the native code.
13554	*
13555	* First the guest code:
13556	*/
13557	for (unsigned i = 0; i < pTb->cRanges; i++)
13558	{
13559	RTGCPHYS GCPhysPc = pTb->aRanges[i].offPhysPage
13560	+ (pTb->aRanges[i].idxPhysPage == 0
13561	? pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK
13562	: pTb->aGCPhysPages[pTb->aRanges[i].idxPhysPage - 1]);
13563	pHlp->pfnPrintf(pHlp, " Range #%u: GCPhysPc=%RGp LB %#x [idxPg=%d]\n",
13564	i, GCPhysPc, pTb->aRanges[i].cbOpcodes, pTb->aRanges[i].idxPhysPage);
13565	unsigned off = pTb->aRanges[i].offOpcodes;
13566	/** @todo this ain't working when crossing pages! */
13567	unsigned const cbOpcodes = pTb->aRanges[i].cbOpcodes + off;
13568	while (off < cbOpcodes)
13569	{
13570	uint32_t cbInstr = 1;
13571	int rc = DISInstrWithPrefetchedBytes(GCPhysPc, enmGstCpuMode, DISOPTYPE_ALL,
13572	&pTb->pabOpcodes[off], cbOpcodes - off,
13573	iemNativeDisasReadBytesDummy, NULL, &Dis, &cbInstr);
13574	if (RT_SUCCESS(rc))
13575	{
13576	DISFormatYasmEx(&Dis, szDisBuf, sizeof(szDisBuf),
13577	DIS_FMT_FLAGS_BYTES_WIDTH_MAKE(10) \| DIS_FMT_FLAGS_BYTES_LEFT
13578	\| DIS_FMT_FLAGS_RELATIVE_BRANCH \| DIS_FMT_FLAGS_C_HEX,
13579	NULL /pfnGetSymbol/, NULL /pvUser/);
13580	pHlp->pfnPrintf(pHlp, " %RGp: %s\n", GCPhysPc, szDisBuf);
13581	GCPhysPc += cbInstr;
13582	off += cbInstr;
13583	}
13584	else
13585	{
13586	pHlp->pfnPrintf(pHlp, " %RGp: %.*Rhxs - disassembly failure %Rrc\n",
13587	GCPhysPc, cbOpcodes - off, &pTb->pabOpcodes[off], rc);
13588	break;
13589	}
13590	}
13591	}
13592
13593	/*
13594	* Then the native code:
13595	*/
13596	pHlp->pfnPrintf(pHlp, " Native code %p L %#x\n", paNative, cNative);
13597	while (offNative < cNative)
13598	{
13599	PCIEMNATIVEINSTR const pNativeCur = &paNative[offNative];
13600	# ifndef VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER
13601	uint32_t cbInstr = sizeof(paNative[0]);
13602	int const rc = DISInstr(pNativeCur, enmHstCpuMode, &Dis, &cbInstr);
13603	if (RT_SUCCESS(rc))
13604	{
13605	# if defined(RT_ARCH_AMD64)
13606	if (Dis.pCurInstr->uOpcode == OP_NOP && cbInstr == 7) /* iemNativeEmitMarker */
13607	{
13608	uint32_t const uInfo = (uint32_t const )&Dis.Instr.ab[3];
13609	if (RT_HIWORD(uInfo) < kIemThreadedFunc_End)
13610	pHlp->pfnPrintf(pHlp, "\n %p: nop ; marker: call #%u to %s (%u args) - %s\n",
13611	pNativeCur, uInfo & 0x7fff, g_apszIemThreadedFunctions[RT_HIWORD(uInfo)],
13612	g_acIemThreadedFunctionUsedArgs[RT_HIWORD(uInfo)],
13613	uInfo & 0x8000 ? "recompiled" : "todo");
13614	else if ((uInfo & ~RT_BIT_32(31)) < RT_ELEMENTS(a_apszMarkers))
13615	pHlp->pfnPrintf(pHlp, " %p: nop ; marker: %s\n", pNativeCur, a_apszMarkers[uInfo & ~RT_BIT_32(31)]);
13616	else
13617	pHlp->pfnPrintf(pHlp, " %p: nop ; unknown marker: %#x (%d)\n", pNativeCur, uInfo, uInfo);
13618	}
13619	else
13620	# endif
13621	{
13622	# ifdef RT_ARCH_AMD64
13623	DISFormatYasmEx(&Dis, szDisBuf, sizeof(szDisBuf),
13624	DIS_FMT_FLAGS_BYTES_WIDTH_MAKE(10) \| DIS_FMT_FLAGS_BYTES_LEFT
13625	\| DIS_FMT_FLAGS_RELATIVE_BRANCH \| DIS_FMT_FLAGS_C_HEX,
13626	NULL /pfnGetSymbol/, NULL /pvUser/);
13627	# elif defined(RT_ARCH_ARM64)
13628	DISFormatArmV8Ex(&Dis, szDisBuf, sizeof(szDisBuf),
13629	DIS_FMT_FLAGS_BYTES_LEFT \| DIS_FMT_FLAGS_RELATIVE_BRANCH \| DIS_FMT_FLAGS_C_HEX,
13630	NULL /pfnGetSymbol/, NULL /pvUser/);
13631	# else
13632	# error "Port me"
13633	# endif
13634	pHlp->pfnPrintf(pHlp, " %p: %s\n", pNativeCur, szDisBuf);
13635	}
13636	}
13637	else
13638	{
13639	# if defined(RT_ARCH_AMD64)
13640	pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs - disassembly failure %Rrc\n",
13641	pNativeCur, RT_MIN(cNative - offNative, 16), pNativeCur, rc);
13642	# else
13643	pHlp->pfnPrintf(pHlp, " %p: %#010RX32 - disassembly failure %Rrc\n", pNativeCur, *pNativeCur, rc);
13644	# endif
13645	cbInstr = sizeof(paNative[0]);
13646	}
13647	offNative += cbInstr / sizeof(paNative[0]);
13648
13649	# else /* VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER */
13650	cs_insn *pInstr;
13651	size_t cInstrs = cs_disasm(hDisasm, (const uint8_t )pNativeCur, (cNative - offNative) sizeof(*pNativeCur),
13652	(uintptr_t)pNativeCur, 1, &pInstr);
13653	if (cInstrs > 0)
13654	{
13655	Assert(cInstrs == 1);
13656	# if defined(RT_ARCH_AMD64)
13657	pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs %-7s %s\n",
13658	pNativeCur, pInstr->size, pNativeCur, pInstr->mnemonic, pInstr->op_str);
13659	# else
13660	pHlp->pfnPrintf(pHlp, " %p: %#010RX32 %-7s %s\n",
13661	pNativeCur, *pNativeCur, pInstr->mnemonic, pInstr->op_str);
13662	# endif
13663	offNative += pInstr->size / sizeof(*pNativeCur);
13664	cs_free(pInstr, cInstrs);
13665	}
13666	else
13667	{
13668	# if defined(RT_ARCH_AMD64)
13669	pHlp->pfnPrintf(pHlp, " %p: %.*Rhxs - disassembly failure %d\n",
13670	pNativeCur, RT_MIN(cNative - offNative, 16), pNativeCur, cs_errno(hDisasm)));
13671	# else
13672	pHlp->pfnPrintf(pHlp, " %p: %#010RX32 - disassembly failure %d\n", pNativeCur, *pNativeCur, cs_errno(hDisasm));
13673	# endif
13674	offNative++;
13675	}
13676	# endif /* VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER */
13677	}
13678	}
13679
13680	#ifdef VBOX_WITH_IEM_USING_CAPSTONE_DISASSEMBLER
13681	/* Cleanup. */
13682	cs_close(&hDisasm);
13683	#endif
13684	}
13685
13686
13687	/**
13688	* Recompiles the given threaded TB into a native one.
13689	*
13690	* In case of failure the translation block will be returned as-is.
13691	*
13692	* @returns pTb.
13693	* @param pVCpu The cross context virtual CPU structure of the calling
13694	* thread.
13695	* @param pTb The threaded translation to recompile to native.
13696	*/
13697	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT
13698	{
13699	STAM_REL_PROFILE_START(&pVCpu->iem.s.StatNativeRecompilation, a);
13700
13701	/*
13702	* The first time thru, we allocate the recompiler state, the other times
13703	* we just need to reset it before using it again.
13704	*/
13705	PIEMRECOMPILERSTATE pReNative = pVCpu->iem.s.pNativeRecompilerStateR3;
13706	if (RT_LIKELY(pReNative))
13707	iemNativeReInit(pReNative, pTb);
13708	else
13709	{
13710	pReNative = iemNativeInit(pVCpu, pTb);
13711	AssertReturn(pReNative, pTb);
13712	}
13713
13714	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
13715	/*
13716	* First do liveness analysis. This is done backwards.
13717	*/
13718	{
13719	uint32_t idxCall = pTb->Thrd.cCalls;
13720	if (idxCall <= pReNative->cLivenessEntriesAlloc)
13721	{ /* likely */ }
13722	else
13723	{
13724	uint32_t cAlloc = RT_MAX(pReNative->cLivenessEntriesAlloc, _4K);
13725	while (idxCall > cAlloc)
13726	cAlloc *= 2;
13727	void pvNew = RTMemRealloc(pReNative->paLivenessEntries, sizeof(pReNative->paLivenessEntries[0]) cAlloc);
13728	AssertReturn(pvNew, pTb);
13729	pReNative->paLivenessEntries = (PIEMLIVENESSENTRY)pvNew;
13730	pReNative->cLivenessEntriesAlloc = cAlloc;
13731	}
13732	AssertReturn(idxCall > 0, pTb);
13733	PIEMLIVENESSENTRY const paLivenessEntries = pReNative->paLivenessEntries;
13734
13735	/* The initial (final) entry. */
13736	idxCall--;
13737	IEM_LIVENESS_RAW_INIT_AS_UNUSED(&paLivenessEntries[idxCall]);
13738
13739	/* Loop backwards thru the calls and fill in the other entries. */
13740	PCIEMTHRDEDCALLENTRY pCallEntry = &pTb->Thrd.paCalls[idxCall];
13741	while (idxCall > 0)
13742	{
13743	PFNIEMNATIVELIVENESSFUNC const pfnLiveness = g_apfnIemNativeLivenessFunctions[pCallEntry->enmFunction];
13744	if (pfnLiveness)
13745	pfnLiveness(pCallEntry, &paLivenessEntries[idxCall], &paLivenessEntries[idxCall - 1]);
13746	else
13747	IEM_LIVENESS_RAW_INIT_WITH_XCPT_OR_CALL(&paLivenessEntries[idxCall - 1], &paLivenessEntries[idxCall]);
13748	pCallEntry--;
13749	idxCall--;
13750	}
13751
13752	# ifdef VBOX_WITH_STATISTICS
13753	/* Check if there are any EFLAGS optimization to be had here. This requires someone settings them
13754	to 'clobbered' rather that 'input'. */
13755	/** @todo */
13756	# endif
13757	}
13758	#endif
13759
13760	/*
13761	* Recompiling and emitting code is done using try/throw/catch or setjmp/longjmp
13762	* for aborting if an error happens.
13763	*/
13764	uint32_t cCallsLeft = pTb->Thrd.cCalls;
13765	#ifdef LOG_ENABLED
13766	uint32_t const cCallsOrg = cCallsLeft;
13767	#endif
13768	uint32_t off = 0;
13769	int rc = VINF_SUCCESS;
13770	IEMNATIVE_TRY_SETJMP(pReNative, rc)
13771	{
13772	/*
13773	* Emit prolog code (fixed).
13774	*/
13775	off = iemNativeEmitProlog(pReNative, off);
13776
13777	/*
13778	* Convert the calls to native code.
13779	*/
13780	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
13781	int32_t iGstInstr = -1;
13782	#endif
13783	#ifndef VBOX_WITHOUT_RELEASE_STATISTICS
13784	uint32_t cThreadedCalls = 0;
13785	uint32_t cRecompiledCalls = 0;
13786	#endif
13787	#if defined(IEMNATIVE_WITH_LIVENESS_ANALYSIS) \|\| defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
13788	uint32_t idxCurCall = 0;
13789	#endif
13790	PCIEMTHRDEDCALLENTRY pCallEntry = pTb->Thrd.paCalls;
13791	pReNative->fExec = pTb->fFlags & IEMTB_F_IEM_F_MASK;
13792	while (cCallsLeft-- > 0)
13793	{
13794	PFNIEMNATIVERECOMPFUNC const pfnRecom = g_apfnIemNativeRecompileFunctions[pCallEntry->enmFunction];
13795	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
13796	pReNative->idxCurCall = idxCurCall;
13797	#endif
13798
13799	/*
13800	* Debug info, assembly markup and statistics.
13801	*/
13802	#if defined(IEMNATIVE_WITH_TB_DEBUG_INFO) \|\| !defined(IEMNATIVE_WITH_BLTIN_CHECKMODE)
13803	if (pCallEntry->enmFunction == kIemThreadedFunc_BltIn_CheckMode)
13804	pReNative->fExec = pCallEntry->auParams[0] & IEMTB_F_IEM_F_MASK;
13805	#endif
13806	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
13807	iemNativeDbgInfoAddNativeOffset(pReNative, off);
13808	if (iGstInstr < (int32_t)pCallEntry->idxInstr)
13809	{
13810	if (iGstInstr < (int32_t)pTb->cInstructions)
13811	iemNativeDbgInfoAddGuestInstruction(pReNative, pReNative->fExec);
13812	else
13813	Assert(iGstInstr == pTb->cInstructions);
13814	iGstInstr = pCallEntry->idxInstr;
13815	}
13816	iemNativeDbgInfoAddThreadedCall(pReNative, (IEMTHREADEDFUNCS)pCallEntry->enmFunction, pfnRecom != NULL);
13817	#endif
13818	#if defined(VBOX_STRICT)
13819	off = iemNativeEmitMarker(pReNative, off,
13820	RT_MAKE_U32(idxCurCall \| (pfnRecom ? 0x8000 : 0), pCallEntry->enmFunction));
13821	#endif
13822	#if defined(VBOX_STRICT)
13823	iemNativeRegAssertSanity(pReNative);
13824	#endif
13825	#ifdef VBOX_WITH_STATISTICS
13826	off = iemNativeEmitThreadCallStats(pReNative, off, pCallEntry);
13827	#endif
13828
13829	/*
13830	* Actual work.
13831	*/
13832	Log2(("%u[%u]: %s%s\n", idxCurCall, pCallEntry->idxInstr, g_apszIemThreadedFunctions[pCallEntry->enmFunction],
13833	pfnRecom ? "(recompiled)" : "(todo)"));
13834	if (pfnRecom) /** @todo stats on this. */
13835	{
13836	off = pfnRecom(pReNative, off, pCallEntry);
13837	STAM_REL_STATS({cRecompiledCalls++;});
13838	}
13839	else
13840	{
13841	off = iemNativeEmitThreadedCall(pReNative, off, pCallEntry);
13842	STAM_REL_STATS({cThreadedCalls++;});
13843	}
13844	Assert(off <= pReNative->cInstrBufAlloc);
13845	Assert(pReNative->cCondDepth == 0);
13846
13847	#if defined(LOG_ENABLED) && defined(IEMNATIVE_WITH_LIVENESS_ANALYSIS)
13848	if (LogIs2Enabled())
13849	{
13850	PCIEMLIVENESSENTRY pLivenessEntry = &pReNative->paLivenessEntries[idxCurCall];
13851	# ifndef IEMLIVENESS_EXTENDED_LAYOUT
13852	static const char s_achState[] = "CUXI";
13853	# else
13854	static const char s_achState[] = "UxRrWwMmCcQqKkNn";
13855	# endif
13856
13857	char szGpr[17];
13858	for (unsigned i = 0; i < 16; i++)
13859	szGpr[i] = s_achState[iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, i + kIemNativeGstReg_GprFirst)];
13860	szGpr[16] = '\0';
13861
13862	char szSegBase[X86_SREG_COUNT + 1];
13863	char szSegLimit[X86_SREG_COUNT + 1];
13864	char szSegAttrib[X86_SREG_COUNT + 1];
13865	char szSegSel[X86_SREG_COUNT + 1];
13866	for (unsigned i = 0; i < X86_SREG_COUNT; i++)
13867	{
13868	szSegBase[i] = s_achState[iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, i + kIemNativeGstReg_SegBaseFirst)];
13869	szSegAttrib[i] = s_achState[iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, i + kIemNativeGstReg_SegAttribFirst)];
13870	szSegLimit[i] = s_achState[iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, i + kIemNativeGstReg_SegLimitFirst)];
13871	szSegSel[i] = s_achState[iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, i + kIemNativeGstReg_SegSelFirst)];
13872	}
13873	szSegBase[X86_SREG_COUNT] = szSegAttrib[X86_SREG_COUNT] = szSegLimit[X86_SREG_COUNT]
13874	= szSegSel[X86_SREG_COUNT] = '\0';
13875
13876	char szEFlags[8];
13877	for (unsigned i = 0; i < 7; i++)
13878	szEFlags[i] = s_achState[iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, i + kIemNativeGstReg_EFlags)];
13879	szEFlags[7] = '\0';
13880
13881	Log2(("liveness: grp=%s segbase=%s segattr=%s seglim=%s segsel=%s efl=%s\n",
13882	szGpr, szSegBase, szSegAttrib, szSegLimit, szSegSel, szEFlags));
13883	}
13884	#endif
13885
13886	/*
13887	* Advance.
13888	*/
13889	pCallEntry++;
13890	#if defined(IEMNATIVE_WITH_LIVENESS_ANALYSIS) \|\| defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
13891	idxCurCall++;
13892	#endif
13893	}
13894
13895	STAM_REL_PROFILE_ADD_PERIOD(&pVCpu->iem.s.StatNativeCallsRecompiled, cRecompiledCalls);
13896	STAM_REL_PROFILE_ADD_PERIOD(&pVCpu->iem.s.StatNativeCallsThreaded, cThreadedCalls);
13897	if (!cThreadedCalls)
13898	STAM_REL_COUNTER_INC(&pVCpu->iem.s.StatNativeFullyRecompiledTbs);
13899
13900	/*
13901	* Emit the epilog code.
13902	*/
13903	uint32_t idxReturnLabel;
13904	off = iemNativeEmitEpilog(pReNative, off, &idxReturnLabel);
13905
13906	/*
13907	* Generate special jump labels.
13908	*/
13909	if (pReNative->bmLabelTypes & RT_BIT_64(kIemNativeLabelType_ReturnBreak))
13910	off = iemNativeEmitReturnBreak(pReNative, off, idxReturnLabel);
13911	if (pReNative->bmLabelTypes & RT_BIT_64(kIemNativeLabelType_ReturnWithFlags))
13912	off = iemNativeEmitReturnWithFlags(pReNative, off, idxReturnLabel);
13913	if (pReNative->bmLabelTypes & RT_BIT_64(kIemNativeLabelType_RaiseGp0))
13914	off = iemNativeEmitRaiseGp0(pReNative, off, idxReturnLabel);
13915	if (pReNative->bmLabelTypes & RT_BIT_64(kIemNativeLabelType_ObsoleteTb))
13916	off = iemNativeEmitObsoleteTb(pReNative, off, idxReturnLabel);
13917	if (pReNative->bmLabelTypes & RT_BIT_64(kIemNativeLabelType_NeedCsLimChecking))
13918	off = iemNativeEmitNeedCsLimChecking(pReNative, off, idxReturnLabel);
13919	if (pReNative->bmLabelTypes & RT_BIT_64(kIemNativeLabelType_CheckBranchMiss))
13920	off = iemNativeEmitCheckBranchMiss(pReNative, off, idxReturnLabel);
13921	}
13922	IEMNATIVE_CATCH_LONGJMP_BEGIN(pReNative, rc);
13923	{
13924	Log(("iemNativeRecompile: Caught %Rrc while recompiling!\n", rc));
13925	return pTb;
13926	}
13927	IEMNATIVE_CATCH_LONGJMP_END(pReNative);
13928	Assert(off <= pReNative->cInstrBufAlloc);
13929
13930	/*
13931	* Make sure all labels has been defined.
13932	*/
13933	PIEMNATIVELABEL const paLabels = pReNative->paLabels;
13934	#ifdef VBOX_STRICT
13935	uint32_t const cLabels = pReNative->cLabels;
13936	for (uint32_t i = 0; i < cLabels; i++)
13937	AssertMsgReturn(paLabels[i].off < off, ("i=%d enmType=%d\n", i, paLabels[i].enmType), pTb);
13938	#endif
13939
13940	/*
13941	* Allocate executable memory, copy over the code we've generated.
13942	*/
13943	PIEMTBALLOCATOR const pTbAllocator = pVCpu->iem.s.pTbAllocatorR3;
13944	if (pTbAllocator->pDelayedFreeHead)
13945	iemTbAllocatorProcessDelayedFrees(pVCpu, pVCpu->iem.s.pTbAllocatorR3);
13946
13947	PIEMNATIVEINSTR const paFinalInstrBuf = (PIEMNATIVEINSTR)iemExecMemAllocatorAlloc(pVCpu, off * sizeof(IEMNATIVEINSTR));
13948	AssertReturn(paFinalInstrBuf, pTb);
13949	memcpy(paFinalInstrBuf, pReNative->pInstrBuf, off * sizeof(paFinalInstrBuf[0]));
13950
13951	/*
13952	* Apply fixups.
13953	*/
13954	PIEMNATIVEFIXUP const paFixups = pReNative->paFixups;
13955	uint32_t const cFixups = pReNative->cFixups;
13956	for (uint32_t i = 0; i < cFixups; i++)
13957	{
13958	Assert(paFixups[i].off < off);
13959	Assert(paFixups[i].idxLabel < cLabels);
13960	AssertMsg(paLabels[paFixups[i].idxLabel].off < off,
13961	("idxLabel=%d enmType=%d off=%#x (max %#x)\n", paFixups[i].idxLabel,
13962	paLabels[paFixups[i].idxLabel].enmType, paLabels[paFixups[i].idxLabel].off, off));
13963	RTPTRUNION const Ptr = { &paFinalInstrBuf[paFixups[i].off] };
13964	switch (paFixups[i].enmType)
13965	{
13966	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
13967	case kIemNativeFixupType_Rel32:
13968	Assert(paFixups[i].off + 4 <= off);
13969	*Ptr.pi32 = paLabels[paFixups[i].idxLabel].off - paFixups[i].off + paFixups[i].offAddend;
13970	continue;
13971
13972	#elif defined(RT_ARCH_ARM64)
13973	case kIemNativeFixupType_RelImm26At0:
13974	{
13975	Assert(paFixups[i].off < off);
13976	int32_t const offDisp = paLabels[paFixups[i].idxLabel].off - paFixups[i].off + paFixups[i].offAddend;
13977	Assert(offDisp >= -262144 && offDisp < 262144);
13978	Ptr.pu32 = (Ptr.pu32 & UINT32_C(0xfc000000)) \| ((uint32_t)offDisp & UINT32_C(0x03ffffff));
13979	continue;
13980	}
13981
13982	case kIemNativeFixupType_RelImm19At5:
13983	{
13984	Assert(paFixups[i].off < off);
13985	int32_t const offDisp = paLabels[paFixups[i].idxLabel].off - paFixups[i].off + paFixups[i].offAddend;
13986	Assert(offDisp >= -262144 && offDisp < 262144);
13987	Ptr.pu32 = (Ptr.pu32 & UINT32_C(0xff00001f)) \| (((uint32_t)offDisp & UINT32_C(0x0007ffff)) << 5);
13988	continue;
13989	}
13990
13991	case kIemNativeFixupType_RelImm14At5:
13992	{
13993	Assert(paFixups[i].off < off);
13994	int32_t const offDisp = paLabels[paFixups[i].idxLabel].off - paFixups[i].off + paFixups[i].offAddend;
13995	Assert(offDisp >= -8192 && offDisp < 8192);
13996	Ptr.pu32 = (Ptr.pu32 & UINT32_C(0xfff8001f)) \| (((uint32_t)offDisp & UINT32_C(0x00003fff)) << 5);
13997	continue;
13998	}
13999
14000	#endif
14001	case kIemNativeFixupType_Invalid:
14002	case kIemNativeFixupType_End:
14003	break;
14004	}
14005	AssertFailed();
14006	}
14007
14008	iemExecMemAllocatorReadyForUse(pVCpu, paFinalInstrBuf, off * sizeof(IEMNATIVEINSTR));
14009	STAM_REL_PROFILE_ADD_PERIOD(&pVCpu->iem.s.StatTbNativeCode, off * sizeof(IEMNATIVEINSTR));
14010
14011	/*
14012	* Convert the translation block.
14013	*/
14014	RTMemFree(pTb->Thrd.paCalls);
14015	pTb->Native.paInstructions = paFinalInstrBuf;
14016	pTb->Native.cInstructions = off;
14017	pTb->fFlags = (pTb->fFlags & ~IEMTB_F_TYPE_MASK) \| IEMTB_F_TYPE_NATIVE;
14018	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
14019	pTb->pDbgInfo = (PIEMTBDBG)RTMemDup(pReNative->pDbgInfo, /* non-fatal, so not return check. */
14020	RT_UOFFSETOF_DYN(IEMTBDBG, aEntries[pReNative->pDbgInfo->cEntries]));
14021	#endif
14022
14023	Assert(pTbAllocator->cThreadedTbs > 0);
14024	pTbAllocator->cThreadedTbs -= 1;
14025	pTbAllocator->cNativeTbs += 1;
14026	Assert(pTbAllocator->cNativeTbs <= pTbAllocator->cTotalTbs);
14027
14028	#ifdef LOG_ENABLED
14029	/*
14030	* Disassemble to the log if enabled.
14031	*/
14032	if (LogIs3Enabled())
14033	{
14034	Log3(("----------------------------------------- %d calls ---------------------------------------\n", cCallsOrg));
14035	iemNativeDisassembleTb(pTb, DBGFR3InfoLogHlp());
14036	# ifdef DEBUG_bird
14037	RTLogFlush(NULL);
14038	# endif
14039	}
14040	#endif
14041	/iemNativeDisassembleTb(pTb, DBGFR3InfoLogRelHlp());/
14042
14043	STAM_REL_PROFILE_STOP(&pVCpu->iem.s.StatNativeRecompilation, a);
14044	return pTb;
14045	}
14046

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp@ 103528

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