IEMAllThrdFuncs.cpp@ 100765

Last change on this file since 100765 was 100732, checked in by vboxsync, 17 months ago
VMM/IEM: Renamed some source files. bugref:10369
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1	/* $Id: IEMAllThrdFuncs.cpp 100732 2023-07-28 22:35:30Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, Threaded Functions.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#ifndef LOG_GROUP /* defined when included by tstIEMCheckMc.cpp */
33	# define LOG_GROUP LOG_GROUP_IEM
34	#endif
35	#define VMCPU_INCL_CPUM_GST_CTX
36	#define IEM_WITH_OPAQUE_DECODER_STATE
37	#include <VBox/vmm/iem.h>
38	#include <VBox/vmm/cpum.h>
39	#include <VBox/vmm/apic.h>
40	#include <VBox/vmm/pdm.h>
41	#include <VBox/vmm/pgm.h>
42	#include <VBox/vmm/iom.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/hm.h>
45	#include <VBox/vmm/nem.h>
46	#include <VBox/vmm/gim.h>
47	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
48	# include <VBox/vmm/em.h>
49	# include <VBox/vmm/hm_svm.h>
50	#endif
51	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
52	# include <VBox/vmm/hmvmxinline.h>
53	#endif
54	#include <VBox/vmm/tm.h>
55	#include <VBox/vmm/dbgf.h>
56	#include <VBox/vmm/dbgftrace.h>
57	#include "IEMInternal.h"
58	#include <VBox/vmm/vmcc.h>
59	#include <VBox/log.h>
60	#include <VBox/err.h>
61	#include <VBox/param.h>
62	#include <VBox/dis.h>
63	#include <VBox/disopcode-x86-amd64.h>
64	#include <iprt/asm-math.h>
65	#include <iprt/assert.h>
66	#include <iprt/string.h>
67	#include <iprt/x86.h>
68
69	#include "IEMInline.h"
70	#include "IEMMc.h"
71
72	#include "IEMThreadedFunctions.h"
73
74
75	/*********************************************************************************************************************************
76	* Defined Constants And Macros *
77	*********************************************************************************************************************************/
78
79	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
80	* and only used when we're in 16-bit code on a pre-386 CPU. */
81	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16(a_cbInstr) \
82	return iemRegAddToIp16AndFinishingClearingRF(pVCpu, a_cbInstr)
83
84	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
85	* and used for 16-bit and 32-bit code on 386 and later CPUs. */
86	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32(a_cbInstr) \
87	return iemRegAddToEip32AndFinishingClearingRF(pVCpu, a_cbInstr)
88
89	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
90	* and only used when we're in 64-bit code. */
91	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64(a_cbInstr) \
92	return iemRegAddToRip64AndFinishingClearingRF(pVCpu, a_cbInstr)
93
94	#undef IEM_MC_ADVANCE_RIP_AND_FINISH
95
96
97	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length as extra
98	* parameter, for use in 16-bit code on a pre-386 CPU. */
99	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16(a_i8, a_cbInstr) \
100	return iemRegIp16RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8))
101
102	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
103	* size as extra parameters, for use in 16-bit and 32-bit code on 386 and
104	* later CPUs. */
105	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32(a_i8, a_cbInstr, a_enmEffOpSize) \
106	return iemRegEip32RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
107
108	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
109	* size as extra parameters, for use in 64-bit code. */
110	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64(a_i8, a_cbInstr, a_enmEffOpSize) \
111	return iemRegRip64RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
112
113	#undef IEM_MC_REL_JMP_S8_AND_FINISH
114
115
116	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
117	* param, for use in 16-bit code on a pre-386 CPU. */
118	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16(a_i16, a_cbInstr) \
119	return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
120
121	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
122	* param, for use in 16-bit and 32-bit code on 386 and later CPUs. */
123	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32(a_i16, a_cbInstr) \
124	return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
125
126	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
127	* param, for use in 64-bit code. */
128	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64(a_i16, a_cbInstr) \
129	return iemRegRip64RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
130
131	#undef IEM_MC_REL_JMP_S16_AND_FINISH
132
133
134	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
135	* an extra parameter - dummy for pre-386 variations not eliminated by the
136	* python script. */
137	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC16(a_i32, a_cbInstr) \
138	do { RT_NOREF(pVCpu, a_i32, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
139
140	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
141	* an extra parameter, for use in 16-bit and 32-bit code on 386+. */
142	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32(a_i32, a_cbInstr) \
143	return iemRegEip32RelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32))
144
145	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
146	* an extra parameter, for use in 64-bit code. */
147	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64(a_i32, a_cbInstr) \
148	return iemRegRip64RelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32))
149
150	#undef IEM_MC_REL_JMP_S32_AND_FINISH
151
152
153	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 16-bit. */
154	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp) \
155	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr16(pVCpu, a_bRm, a_u16Disp)
156
157	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, pre-386 16-bit. */
158	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16_PRE386(a_GCPtrEff, a_bRm, a_u16Disp) \
159	IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp)
160
161	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit with address prefix. */
162	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32_ADDR16(a_GCPtrEff, a_bRm, a_u16Disp) \
163	IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp)
164
165
166	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit. */
167	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32(a_GCPtrEff, a_bRm, a_uSibAndRspOffset, a_u32Disp) \
168	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_uSibAndRspOffset, a_u32Disp)
169
170	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit flat. */
171	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32_FLAT(a_GCPtrEff, a_bRm, a_uSibAndRspOffset, a_u32Disp) \
172	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_uSibAndRspOffset, a_u32Disp)
173
174	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 16-bit with address prefix. */
175	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16_ADDR32(a_GCPtrEff, a_bRm, a_uSibAndRspOffset, a_u32Disp) \
176	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_uSibAndRspOffset, a_u32Disp)
177
178
179	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
180	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
181	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm)
182
183	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters.
184	* @todo How did that address prefix thing work for 64-bit code again? */
185	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_ADDR32(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
186	(a_GCPtrEff) = (uint32_t)iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm)
187
188	#undef IEM_MC_CALC_RM_EFF_ADDR
189
190
191	/** Variant of IEM_MC_CALL_CIMPL_1 with explicit instruction length parameter. */
192	#define IEM_MC_CALL_CIMPL_1_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0) \
193	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0)
194	#undef IEM_MC_CALL_CIMPL_1
195
196	/** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */
197	#define IEM_MC_CALL_CIMPL_2_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1) \
198	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1)
199	#undef IEM_MC_CALL_CIMPL_2
200
201	/** Variant of IEM_MC_CALL_CIMPL_3 with explicit instruction length parameter. */
202	#define IEM_MC_CALL_CIMPL_3_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2) \
203	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2)
204	#undef IEM_MC_CALL_CIMPL_3
205
206	/** Variant of IEM_MC_CALL_CIMPL_4 with explicit instruction length parameter. */
207	#define IEM_MC_CALL_CIMPL_4_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2, a3) \
208	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3)
209	#undef IEM_MC_CALL_CIMPL_4
210
211	/** Variant of IEM_MC_CALL_CIMPL_5 with explicit instruction length parameter. */
212	#define IEM_MC_CALL_CIMPL_5_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2, a3, a4) \
213	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4)
214	#undef IEM_MC_CALL_CIMPL_5
215
216
217	/** Variant of IEM_MC_DEFER_TO_CIMPL_0_RET with explicit instruction
218	* length parameter. */
219	#define IEM_MC_DEFER_TO_CIMPL_0_RET_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl) \
220	return (a_pfnCImpl)(pVCpu, (a_cbInstr))
221	#undef IEM_MC_DEFER_TO_CIMPL_0_RET
222
223	/** Variant of IEM_MC_DEFER_TO_CIMPL_1_RET with explicit instruction
224	* length parameter. */
225	#define IEM_MC_DEFER_TO_CIMPL_1_RET_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0) \
226	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0)
227	#undef IEM_MC_DEFER_TO_CIMPL_1_RET
228
229	/** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */
230	#define IEM_MC_DEFER_TO_CIMPL_2_RET_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1) \
231	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1)
232	#undef IEM_MC_DEFER_TO_CIMPL_2_RET
233
234	/** Variant of IEM_MC_DEFER_TO_CIMPL_3 with explicit instruction length
235	* parameter. */
236	#define IEM_MC_DEFER_TO_CIMPL_3_RET_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2) \
237	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2)
238	#undef IEM_MC_DEFER_TO_CIMPL_3_RET
239
240	/** Variant of IEM_MC_DEFER_TO_CIMPL_4 with explicit instruction length
241	* parameter. */
242	#define IEM_MC_DEFER_TO_CIMPL_4_RET_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2, a3) \
243	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3)
244	#undef IEM_MC_DEFER_TO_CIMPL_4_RET
245
246	/** Variant of IEM_MC_DEFER_TO_CIMPL_5 with explicit instruction length
247	* parameter. */
248	#define IEM_MC_DEFER_TO_CIMPL_5_RET_THREADED(a_cbInstr, a_fFlags, a_pfnCImpl, a0, a1, a2, a3, a4) \
249	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4)
250	#undef IEM_MC_DEFER_TO_CIMPL_5_RET
251
252
253	/** Variant of IEM_MC_FETCH_GREG_U8 with extended (20) register index. */
254	#define IEM_MC_FETCH_GREG_U8_THREADED(a_u8Dst, a_iGRegEx) \
255	(a_u8Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
256
257	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U16 with extended (20) register index. */
258	#define IEM_MC_FETCH_GREG_U8_ZX_U16_THREADED(a_u16Dst, a_iGRegEx) \
259	(a_u16Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
260
261	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U32 with extended (20) register index. */
262	#define IEM_MC_FETCH_GREG_U8_ZX_U32_THREADED(a_u32Dst, a_iGRegEx) \
263	(a_u32Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
264
265	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U64 with extended (20) register index. */
266	#define IEM_MC_FETCH_GREG_U8_ZX_U64_THREADED(a_u64Dst, a_iGRegEx) \
267	(a_u64Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
268
269	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U16 with extended (20) register index. */
270	#define IEM_MC_FETCH_GREG_U8_SX_U16_THREADED(a_u16Dst, a_iGRegEx) \
271	(a_u16Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
272
273	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U32 with extended (20) register index. */
274	#define IEM_MC_FETCH_GREG_U8_SX_U32_THREADED(a_u32Dst, a_iGRegEx) \
275	(a_u32Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
276	#undef IEM_MC_FETCH_GREG_U8_SX_U32
277
278	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U64 with extended (20) register index. */
279	#define IEM_MC_FETCH_GREG_U8_SX_U64_THREADED(a_u64Dst, a_iGRegEx) \
280	(a_u64Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
281	#undef IEM_MC_FETCH_GREG_U8_SX_U64
282
283	/** Variant of IEM_MC_STORE_GREG_U8 with extended (20) register index. */
284	#define IEM_MC_STORE_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
285	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
286	#undef IEM_MC_STORE_GREG_U8
287
288	/** Variant of IEM_MC_STORE_GREG_U8 with extended (20) register index. */
289	#define IEM_MC_STORE_GREG_U8_CONST_THREADED(a_iGRegEx, a_u8Value) \
290	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
291	#undef IEM_MC_STORE_GREG_U8
292
293	/** Variant of IEM_MC_REF_GREG_U8 with extended (20) register index. */
294	#define IEM_MC_REF_GREG_U8_THREADED(a_pu8Dst, a_iGRegEx) \
295	(a_pu8Dst) = iemGRegRefU8Ex(pVCpu, (a_iGRegEx))
296	#undef IEM_MC_REF_GREG_U8
297
298	/** Variant of IEM_MC_ADD_GREG_U8 with extended (20) register index. */
299	#define IEM_MC_ADD_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
300	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) += (a_u8Value)
301	#undef IEM_MC_ADD_GREG_U8
302
303	/** Variant of IEM_MC_SUB_GREG_U8 with extended (20) register index. */
304	#define IEM_MC_SUB_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
305	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) -= (a_u8Value)
306	#undef IEM_MC_SUB_GREG_U8
307
308	/** Variant of IEM_MC_ADD_GREG_U8_TO_LOCAL with extended (20) register index. */
309	#define IEM_MC_ADD_GREG_U8_TO_LOCAL_THREADED(a_u8Value, a_iGRegEx) \
310	do { (a_u8Value) += iemGRegFetchU8Ex(pVCpu, (a_iGRegEx)); } while (0)
311	#undef IEM_MC_ADD_GREG_U8_TO_LOCAL
312
313	/** Variant of IEM_MC_AND_GREG_U8 with extended (20) register index. */
314	#define IEM_MC_AND_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
315	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) &= (a_u8Value)
316	#undef IEM_MC_AND_GREG_U8
317
318	/** Variant of IEM_MC_OR_GREG_U8 with extended (20) register index. */
319	#define IEM_MC_OR_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
320	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) \|= (a_u8Value)
321	#undef IEM_MC_OR_GREG_U8
322
323	/**
324	* Calculates the effective address of a ModR/M memory operand, 16-bit
325	* addressing variant.
326	*
327	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR16.
328	*
329	* @returns The effective address.
330	* @param pVCpu The cross context virtual CPU structure of the calling thread.
331	* @param bRm The ModRM byte.
332	* @param u16Disp The displacement byte/word, if any.
333	* RIP relative addressing.
334	*/
335	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr16(PVMCPUCC pVCpu, uint8_t bRm, uint16_t u16Disp) RT_NOEXCEPT
336	{
337	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: bRm=%#x u16Disp=%#x\n", bRm, u16Disp));
338	Assert(!IEM_IS_64BIT_CODE(pVCpu));
339
340	/* Handle the disp16 form with no registers first. */
341	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 6)
342	{
343	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16Disp));
344	return u16Disp;
345	}
346
347	/* Get the displacment. */
348	/** @todo we can eliminate this step by making u16Disp have this value
349	* already! */
350	uint16_t u16EffAddr;
351	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
352	{
353	case 0: u16EffAddr = 0; break;
354	case 1: u16EffAddr = (int16_t)(int8_t)u16Disp; break;
355	case 2: u16EffAddr = u16Disp; break;
356	default: AssertFailedStmt(u16EffAddr = 0);
357	}
358
359	/* Add the base and index registers to the disp. */
360	switch (bRm & X86_MODRM_RM_MASK)
361	{
362	case 0: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.si; break;
363	case 1: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.di; break;
364	case 2: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.si; break;
365	case 3: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.di; break;
366	case 4: u16EffAddr += pVCpu->cpum.GstCtx.si; break;
367	case 5: u16EffAddr += pVCpu->cpum.GstCtx.di; break;
368	case 6: u16EffAddr += pVCpu->cpum.GstCtx.bp; break;
369	case 7: u16EffAddr += pVCpu->cpum.GstCtx.bx; break;
370	}
371
372	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16EffAddr));
373	return u16EffAddr;
374	}
375
376
377	/**
378	* Calculates the effective address of a ModR/M memory operand, 32-bit
379	* addressing variant.
380	*
381	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32 and
382	* IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32FLAT.
383	*
384	* @returns The effective address.
385	* @param pVCpu The cross context virtual CPU structure of the
386	* calling thread.
387	* @param bRm The ModRM byte.
388	* @param uSibAndRspOffset Two parts:
389	* - The first 8 bits make up the SIB byte.
390	* - The next 8 bits are the fixed RSP/ESP offse
391	* in case of a pop [xSP].
392	* @param u32Disp The displacement byte/dword, if any.
393	*/
394	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr32(PVMCPUCC pVCpu, uint8_t bRm, uint32_t uSibAndRspOffset,
395	uint32_t u32Disp) RT_NOEXCEPT
396	{
397	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: bRm=%#x uSibAndRspOffset=%#x u32Disp=%#x\n", bRm, uSibAndRspOffset, u32Disp));
398
399	/* Handle the disp32 form with no registers first. */
400	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
401	{
402	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32Disp));
403	return u32Disp;
404	}
405
406	/* Get the register (or SIB) value. */
407	uint32_t u32EffAddr;
408	#ifdef _MSC_VER
409	u32EffAddr = 0;/* MSC uninitialized variable analysis is too simple, it seems. */
410	#endif
411	switch (bRm & X86_MODRM_RM_MASK)
412	{
413	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
414	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
415	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
416	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
417	case 4: /* SIB */
418	{
419	/* Get the index and scale it. */
420	switch ((uSibAndRspOffset >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
421	{
422	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
423	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
424	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
425	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
426	case 4: u32EffAddr = 0; /none / break;
427	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
428	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
429	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
430	}
431	u32EffAddr <<= (uSibAndRspOffset >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
432
433	/* add base */
434	switch (uSibAndRspOffset & X86_SIB_BASE_MASK)
435	{
436	case 0: u32EffAddr += pVCpu->cpum.GstCtx.eax; break;
437	case 1: u32EffAddr += pVCpu->cpum.GstCtx.ecx; break;
438	case 2: u32EffAddr += pVCpu->cpum.GstCtx.edx; break;
439	case 3: u32EffAddr += pVCpu->cpum.GstCtx.ebx; break;
440	case 4:
441	u32EffAddr += pVCpu->cpum.GstCtx.esp;
442	u32EffAddr += uSibAndRspOffset >> 8;
443	break;
444	case 5:
445	if ((bRm & X86_MODRM_MOD_MASK) != 0)
446	u32EffAddr += pVCpu->cpum.GstCtx.ebp;
447	else
448	u32EffAddr += u32Disp;
449	break;
450	case 6: u32EffAddr += pVCpu->cpum.GstCtx.esi; break;
451	case 7: u32EffAddr += pVCpu->cpum.GstCtx.edi; break;
452	}
453	break;
454	}
455	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
456	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
457	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
458	}
459
460	/* Get and add the displacement. */
461	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
462	{
463	case 0: break;
464	case 1: u32EffAddr += (int8_t)u32Disp; break;
465	case 2: u32EffAddr += u32Disp; break;
466	default: AssertFailed();
467	}
468
469	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32EffAddr));
470	return u32EffAddr;
471	}
472
473
474	/**
475	* Calculates the effective address of a ModR/M memory operand.
476	*
477	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR64.
478	*
479	* @returns The effective address.
480	* @param pVCpu The cross context virtual CPU structure of the
481	* calling thread.
482	* @param bRmEx The ModRM byte but with bit 3 set to REX.B and
483	* bit 4 to REX.X. The two bits are part of the
484	* REG sub-field, which isn't needed in this
485	* function.
486	* @param uSibAndRspOffset Two parts:
487	* - The first 8 bits make up the SIB byte.
488	* - The next 8 bits are the fixed RSP/ESP offse
489	* in case of a pop [xSP].
490	* @param u32Disp The displacement byte/word/dword, if any.
491	* @param cbInstr The size of the fully decoded instruction. Used
492	* for RIP relative addressing.
493	* @todo combine cbInstr and cbImm!
494	*/
495	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr64(PVMCPUCC pVCpu, uint8_t bRmEx, uint32_t uSibAndRspOffset,
496	uint32_t u32Disp, uint8_t cbInstr) RT_NOEXCEPT
497	{
498	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: bRmEx=%#x\n", bRmEx));
499	Assert(IEM_IS_64BIT_CODE(pVCpu));
500
501	uint64_t u64EffAddr;
502
503	/* Handle the rip+disp32 form with no registers first. */
504	if ((bRmEx & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
505	{
506	u64EffAddr = (int32_t)u32Disp;
507	u64EffAddr += pVCpu->cpum.GstCtx.rip + cbInstr;
508	}
509	else
510	{
511	/* Get the register (or SIB) value. */
512	#ifdef _MSC_VER
513	u64EffAddr = 0; /* MSC uninitialized variable analysis is too simple, it seems. */
514	#endif
515	switch (bRmEx & (X86_MODRM_RM_MASK \| 0x8)) /* bRmEx[bit 3] = REX.B */
516	{
517	default:
518	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
519	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
520	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
521	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
522	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
523	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
524	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
525	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
526	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
527	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
528	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
529	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
530	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
531	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
532	/* SIB */
533	case 4:
534	case 12:
535	{
536	/* Get the index and scale it. */
537	switch ( ((uSibAndRspOffset >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
538	\| ((bRmEx & 0x10) >> 1)) /* bRmEx[bit 4] = REX.X */
539	{
540	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
541	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
542	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
543	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
544	case 4: u64EffAddr = 0; /none / break;
545	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
546	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
547	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
548	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
549	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
550	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
551	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
552	case 12: u64EffAddr = pVCpu->cpum.GstCtx.r12; break;
553	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
554	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
555	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
556	}
557	u64EffAddr <<= (uSibAndRspOffset >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
558
559	/* add base */
560	switch ((uSibAndRspOffset & X86_SIB_BASE_MASK) \| (bRmEx & 0x8)) /* bRmEx[bit 3] = REX.B */
561	{
562	case 0: u64EffAddr += pVCpu->cpum.GstCtx.rax; break;
563	case 1: u64EffAddr += pVCpu->cpum.GstCtx.rcx; break;
564	case 2: u64EffAddr += pVCpu->cpum.GstCtx.rdx; break;
565	case 3: u64EffAddr += pVCpu->cpum.GstCtx.rbx; break;
566	case 4:
567	u64EffAddr += pVCpu->cpum.GstCtx.rsp;
568	u64EffAddr += uSibAndRspOffset >> 8;
569	break;
570	case 6: u64EffAddr += pVCpu->cpum.GstCtx.rsi; break;
571	case 7: u64EffAddr += pVCpu->cpum.GstCtx.rdi; break;
572	case 8: u64EffAddr += pVCpu->cpum.GstCtx.r8; break;
573	case 9: u64EffAddr += pVCpu->cpum.GstCtx.r9; break;
574	case 10: u64EffAddr += pVCpu->cpum.GstCtx.r10; break;
575	case 11: u64EffAddr += pVCpu->cpum.GstCtx.r11; break;
576	case 12: u64EffAddr += pVCpu->cpum.GstCtx.r12; break;
577	case 14: u64EffAddr += pVCpu->cpum.GstCtx.r14; break;
578	case 15: u64EffAddr += pVCpu->cpum.GstCtx.r15; break;
579	/* complicated encodings */
580	case 5:
581	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
582	u64EffAddr += pVCpu->cpum.GstCtx.rbp;
583	else
584	u64EffAddr += (int32_t)u32Disp;
585	break;
586	case 13:
587	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
588	u64EffAddr += pVCpu->cpum.GstCtx.r13;
589	else
590	u64EffAddr += (int32_t)u32Disp;
591	break;
592	}
593	break;
594	}
595	}
596
597	/* Get and add the displacement. */
598	switch ((bRmEx >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
599	{
600	case 0: break;
601	case 1: u64EffAddr += (int8_t)u32Disp; break;
602	case 2: u64EffAddr += (int32_t)u32Disp; break;
603	default: AssertFailed();
604	}
605	}
606
607	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: EffAddr=%#010RGv\n", u64EffAddr));
608	return u64EffAddr;
609	}
610
611
612	/*
613	* The threaded functions.
614	*/
615	#include "IEMThreadedFunctions.cpp.h"
616

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllThrdFuncs.cpp@ 100765

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