IEMAllThrdFuncs.cpp@ 102020

Last change on this file since 102020 was 102011, checked in by vboxsync, 13 months ago
VMM/IEM: Added a flush mask for guest register shadows to the IEM_MC_CALL_CIMPL_X macros to better manage register optimizations when recompiling to native code, replacing the IEM_MC_HINT_FLUSH_GUEST_SHADOW_GREG/SREG macros added earlier today. Added a IEM_MC_HINT_FLUSH_GUEST_SHADOW macro for debugging purposes. bugref:10371
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File size: 30.5 KB

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1	/* $Id: IEMAllThrdFuncs.cpp 102011 2023-11-08 22:10:48Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation, Threaded Functions.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#ifndef LOG_GROUP /* defined when included by tstIEMCheckMc.cpp */
33	# define LOG_GROUP LOG_GROUP_IEM
34	#endif
35	#define VMCPU_INCL_CPUM_GST_CTX
36	#define IEM_WITH_OPAQUE_DECODER_STATE
37	#include <VBox/vmm/iem.h>
38	#include <VBox/vmm/cpum.h>
39	#include <VBox/vmm/apic.h>
40	#include <VBox/vmm/pdm.h>
41	#include <VBox/vmm/pgm.h>
42	#include <VBox/vmm/iom.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/hm.h>
45	#include <VBox/vmm/nem.h>
46	#include <VBox/vmm/gim.h>
47	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
48	# include <VBox/vmm/em.h>
49	# include <VBox/vmm/hm_svm.h>
50	#endif
51	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
52	# include <VBox/vmm/hmvmxinline.h>
53	#endif
54	#include <VBox/vmm/tm.h>
55	#include <VBox/vmm/dbgf.h>
56	#include <VBox/vmm/dbgftrace.h>
57	#include "IEMInternal.h"
58	#include <VBox/vmm/vmcc.h>
59	#include <VBox/log.h>
60	#include <VBox/err.h>
61	#include <VBox/param.h>
62	#include <VBox/dis.h>
63	#include <VBox/disopcode-x86-amd64.h>
64	#include <iprt/asm-math.h>
65	#include <iprt/assert.h>
66	#include <iprt/string.h>
67	#include <iprt/x86.h>
68
69	#include "IEMInline.h"
70	#include "IEMMc.h"
71
72	#include "IEMThreadedFunctions.h"
73
74
75	/*********************************************************************************************************************************
76	* Defined Constants And Macros *
77	*********************************************************************************************************************************/
78
79	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
80	* and only used when we're in 16-bit code on a pre-386 CPU. */
81	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16(a_cbInstr) \
82	return iemRegAddToIp16AndFinishingNoFlags(pVCpu, a_cbInstr)
83
84	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
85	* and used for 16-bit and 32-bit code on 386 and later CPUs. */
86	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32(a_cbInstr) \
87	return iemRegAddToEip32AndFinishingNoFlags(pVCpu, a_cbInstr)
88
89	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
90	* and only used when we're in 64-bit code. */
91	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64(a_cbInstr) \
92	return iemRegAddToRip64AndFinishingNoFlags(pVCpu, a_cbInstr)
93
94
95	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
96	* and only used when we're in 16-bit code on a pre-386 CPU and we need to
97	* check and clear flags. */
98	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_cbInstr) \
99	return iemRegAddToIp16AndFinishingClearingRF(pVCpu, a_cbInstr)
100
101	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
102	* and used for 16-bit and 32-bit code on 386 and later CPUs and we need to
103	* check and clear flags. */
104	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_cbInstr) \
105	return iemRegAddToEip32AndFinishingClearingRF(pVCpu, a_cbInstr)
106
107	/** Variant of IEM_MC_ADVANCE_RIP_AND_FINISH with instruction length as param
108	* and only used when we're in 64-bit code and we need to check and clear
109	* flags. */
110	#define IEM_MC_ADVANCE_RIP_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_cbInstr) \
111	return iemRegAddToRip64AndFinishingClearingRF(pVCpu, a_cbInstr)
112
113	#undef IEM_MC_ADVANCE_RIP_AND_FINISH
114
115
116	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length as extra
117	* parameter, for use in 16-bit code on a pre-386 CPU. */
118	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16(a_i8, a_cbInstr) \
119	return iemRegIp16RelativeJumpS8AndFinishNoFlags(pVCpu, a_cbInstr, (a_i8))
120
121	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
122	* size as extra parameters, for use in 16-bit and 32-bit code on 386 and
123	* later CPUs. */
124	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32(a_i8, a_cbInstr, a_enmEffOpSize) \
125	return iemRegEip32RelativeJumpS8AndFinishNoFlags(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
126
127	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
128	* size as extra parameters, for use in 64-bit code. */
129	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64(a_i8, a_cbInstr, a_enmEffOpSize) \
130	return iemRegRip64RelativeJumpS8AndFinishNoFlags(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
131
132
133	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length as extra
134	* parameter, for use in 16-bit code on a pre-386 CPU and we need to check and
135	* clear flags. */
136	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i8, a_cbInstr) \
137	return iemRegIp16RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8))
138
139	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
140	* size as extra parameters, for use in 16-bit and 32-bit code on 386 and
141	* later CPUs and we need to check and clear flags. */
142	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i8, a_cbInstr, a_enmEffOpSize) \
143	return iemRegEip32RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
144
145	/** Variant of IEM_MC_REL_JMP_S8_AND_FINISH with instruction length and operand
146	* size as extra parameters, for use in 64-bit code and we need to check and
147	* clear flags. */
148	#define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i8, a_cbInstr, a_enmEffOpSize) \
149	return iemRegRip64RelativeJumpS8AndFinishClearingRF(pVCpu, a_cbInstr, (a_i8), a_enmEffOpSize)
150
151	#undef IEM_MC_REL_JMP_S8_AND_FINISH
152
153
154	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
155	* param, for use in 16-bit code on a pre-386 CPU. */
156	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16(a_i16, a_cbInstr) \
157	return iemRegEip32RelativeJumpS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16))
158
159	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
160	* param, for use in 16-bit and 32-bit code on 386 and later CPUs. */
161	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32(a_i16, a_cbInstr) \
162	return iemRegEip32RelativeJumpS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16))
163
164	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
165	* param, for use in 64-bit code. */
166	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64(a_i16, a_cbInstr) \
167	return iemRegRip64RelativeJumpS16AndFinishNoFlags(pVCpu, a_cbInstr, (a_i16))
168
169
170	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
171	* param, for use in 16-bit code on a pre-386 CPU and we need to check and
172	* clear flags. */
173	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i16, a_cbInstr) \
174	return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
175
176	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
177	* param, for use in 16-bit and 32-bit code on 386 and later CPUs and we need
178	* to check and clear flags. */
179	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i16, a_cbInstr) \
180	return iemRegEip32RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
181
182	/** Variant of IEM_MC_REL_JMP_S16_AND_FINISH with instruction length as
183	* param, for use in 64-bit code and we need to check and clear flags. */
184	#define IEM_MC_REL_JMP_S16_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i16, a_cbInstr) \
185	return iemRegRip64RelativeJumpS16AndFinishClearingRF(pVCpu, a_cbInstr, (a_i16))
186
187	#undef IEM_MC_REL_JMP_S16_AND_FINISH
188
189
190	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
191	* an extra parameter - dummy for pre-386 variations not eliminated by the
192	* python script. */
193	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC16(a_i32, a_cbInstr) \
194	do { RT_NOREF(pVCpu, a_i32, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
195
196	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
197	* an extra parameter, for use in 16-bit and 32-bit code on 386+. */
198	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32(a_i32, a_cbInstr) \
199	return iemRegEip32RelativeJumpS32AndFinishNoFlags(pVCpu, a_cbInstr, (a_i32))
200
201	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
202	* an extra parameter, for use in 64-bit code. */
203	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64(a_i32, a_cbInstr) \
204	return iemRegRip64RelativeJumpS32AndFinishNoFlags(pVCpu, a_cbInstr, (a_i32))
205
206
207	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
208	* an extra parameter - dummy for pre-386 variations not eliminated by the
209	* python script. */
210	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_i32, a_cbInstr) \
211	do { RT_NOREF(pVCpu, a_i32, a_cbInstr); AssertFailedReturn(VERR_IEM_IPE_9); } while (0)
212
213	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
214	* an extra parameter, for use in 16-bit and 32-bit code on 386+ and we need
215	* to check and clear flags. */
216	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_i32, a_cbInstr) \
217	return iemRegEip32RelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32))
218
219	/** Variant of IEM_MC_REL_JMP_S32_AND_FINISH with instruction length as
220	* an extra parameter, for use in 64-bit codeand we need to check and clear
221	* flags. */
222	#define IEM_MC_REL_JMP_S32_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_i32, a_cbInstr) \
223	return iemRegRip64RelativeJumpS32AndFinishClearingRF(pVCpu, a_cbInstr, (a_i32))
224
225	#undef IEM_MC_REL_JMP_S32_AND_FINISH
226
227
228	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 16-bit. */
229	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_16(a_GCPtrEff, a_bRm, a_u16Disp) \
230	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr16(pVCpu, a_bRm, a_u16Disp)
231
232	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters, 32-bit. */
233	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_32(a_GCPtrEff, a_bRm, a_uSibAndRspOffset, a_u32Disp) \
234	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr32(pVCpu, a_bRm, a_uSibAndRspOffset, a_u32Disp)
235
236	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
237	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
238	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm)
239
240	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters. */
241	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_FSGS(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
242	(a_GCPtrEff) = iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm)
243
244	/** Variant of IEM_MC_CALC_RM_EFF_ADDR with additional parameters.
245	* @todo How did that address prefix thing work for 64-bit code again? */
246	#define IEM_MC_CALC_RM_EFF_ADDR_THREADED_64_ADDR32(a_GCPtrEff, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm) \
247	(a_GCPtrEff) = (uint32_t)iemOpHlpCalcRmEffAddrThreadedAddr64(pVCpu, a_bRmEx, a_uSibAndRspOffset, a_u32Disp, a_cbImm)
248
249	#undef IEM_MC_CALC_RM_EFF_ADDR
250
251
252	/** Variant of IEM_MC_CALL_CIMPL_1 with explicit instruction length parameter. */
253	#define IEM_MC_CALL_CIMPL_1_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) \
254	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0)
255	#undef IEM_MC_CALL_CIMPL_1
256
257	/** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */
258	#define IEM_MC_CALL_CIMPL_2_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) \
259	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1)
260	#undef IEM_MC_CALL_CIMPL_2
261
262	/** Variant of IEM_MC_CALL_CIMPL_3 with explicit instruction length parameter. */
263	#define IEM_MC_CALL_CIMPL_3_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) \
264	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2)
265	#undef IEM_MC_CALL_CIMPL_3
266
267	/** Variant of IEM_MC_CALL_CIMPL_4 with explicit instruction length parameter. */
268	#define IEM_MC_CALL_CIMPL_4_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3) \
269	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3)
270	#undef IEM_MC_CALL_CIMPL_4
271
272	/** Variant of IEM_MC_CALL_CIMPL_5 with explicit instruction length parameter. */
273	#define IEM_MC_CALL_CIMPL_5_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3, a4) \
274	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4)
275	#undef IEM_MC_CALL_CIMPL_5
276
277
278	/** Variant of IEM_MC_DEFER_TO_CIMPL_0_RET with explicit instruction
279	* length parameter. */
280	#define IEM_MC_DEFER_TO_CIMPL_0_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl) \
281	return (a_pfnCImpl)(pVCpu, (a_cbInstr))
282	#undef IEM_MC_DEFER_TO_CIMPL_0_RET
283
284	/** Variant of IEM_MC_DEFER_TO_CIMPL_1_RET with explicit instruction
285	* length parameter. */
286	#define IEM_MC_DEFER_TO_CIMPL_1_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) \
287	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0)
288	#undef IEM_MC_DEFER_TO_CIMPL_1_RET
289
290	/** Variant of IEM_MC_CALL_CIMPL_2 with explicit instruction length parameter. */
291	#define IEM_MC_DEFER_TO_CIMPL_2_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) \
292	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1)
293	#undef IEM_MC_DEFER_TO_CIMPL_2_RET
294
295	/** Variant of IEM_MC_DEFER_TO_CIMPL_3 with explicit instruction length
296	* parameter. */
297	#define IEM_MC_DEFER_TO_CIMPL_3_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) \
298	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2)
299	#undef IEM_MC_DEFER_TO_CIMPL_3_RET
300
301	/** Variant of IEM_MC_DEFER_TO_CIMPL_4 with explicit instruction length
302	* parameter. */
303	#define IEM_MC_DEFER_TO_CIMPL_4_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3) \
304	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3)
305	#undef IEM_MC_DEFER_TO_CIMPL_4_RET
306
307	/** Variant of IEM_MC_DEFER_TO_CIMPL_5 with explicit instruction length
308	* parameter. */
309	#define IEM_MC_DEFER_TO_CIMPL_5_RET_THREADED(a_cbInstr, a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3, a4) \
310	return (a_pfnCImpl)(pVCpu, (a_cbInstr), a0, a1, a2, a3, a4)
311	#undef IEM_MC_DEFER_TO_CIMPL_5_RET
312
313
314	/** Variant of IEM_MC_FETCH_GREG_U8 with extended (20) register index. */
315	#define IEM_MC_FETCH_GREG_U8_THREADED(a_u8Dst, a_iGRegEx) \
316	(a_u8Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
317
318	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U16 with extended (20) register index. */
319	#define IEM_MC_FETCH_GREG_U8_ZX_U16_THREADED(a_u16Dst, a_iGRegEx) \
320	(a_u16Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
321
322	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U32 with extended (20) register index. */
323	#define IEM_MC_FETCH_GREG_U8_ZX_U32_THREADED(a_u32Dst, a_iGRegEx) \
324	(a_u32Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
325
326	/** Variant of IEM_MC_FETCH_GREG_U8_ZX_U64 with extended (20) register index. */
327	#define IEM_MC_FETCH_GREG_U8_ZX_U64_THREADED(a_u64Dst, a_iGRegEx) \
328	(a_u64Dst) = iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
329
330	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U16 with extended (20) register index. */
331	#define IEM_MC_FETCH_GREG_U8_SX_U16_THREADED(a_u16Dst, a_iGRegEx) \
332	(a_u16Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
333
334	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U32 with extended (20) register index. */
335	#define IEM_MC_FETCH_GREG_U8_SX_U32_THREADED(a_u32Dst, a_iGRegEx) \
336	(a_u32Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
337	#undef IEM_MC_FETCH_GREG_U8_SX_U32
338
339	/** Variant of IEM_MC_FETCH_GREG_U8_SX_U64 with extended (20) register index. */
340	#define IEM_MC_FETCH_GREG_U8_SX_U64_THREADED(a_u64Dst, a_iGRegEx) \
341	(a_u64Dst) = (int8_t)iemGRegFetchU8Ex(pVCpu, (a_iGRegEx))
342	#undef IEM_MC_FETCH_GREG_U8_SX_U64
343
344	/** Variant of IEM_MC_STORE_GREG_U8 with extended (20) register index. */
345	#define IEM_MC_STORE_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
346	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
347	#undef IEM_MC_STORE_GREG_U8
348
349	/** Variant of IEM_MC_STORE_GREG_U8_CONST with extended (20) register index. */
350	#define IEM_MC_STORE_GREG_U8_CONST_THREADED(a_iGRegEx, a_u8Value) \
351	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) = (a_u8Value)
352	#undef IEM_MC_STORE_GREG_U8
353
354	/** Variant of IEM_MC_REF_GREG_U8 with extended (20) register index. */
355	#define IEM_MC_REF_GREG_U8_THREADED(a_pu8Dst, a_iGRegEx) \
356	(a_pu8Dst) = iemGRegRefU8Ex(pVCpu, (a_iGRegEx))
357	#undef IEM_MC_REF_GREG_U8
358
359	/** Variant of IEM_MC_ADD_GREG_U8_TO_LOCAL with extended (20) register index. */
360	#define IEM_MC_ADD_GREG_U8_TO_LOCAL_THREADED(a_u8Value, a_iGRegEx) \
361	do { (a_u8Value) += iemGRegFetchU8Ex(pVCpu, (a_iGRegEx)); } while (0)
362	#undef IEM_MC_ADD_GREG_U8_TO_LOCAL
363
364	/** Variant of IEM_MC_AND_GREG_U8 with extended (20) register index. */
365	#define IEM_MC_AND_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
366	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) &= (a_u8Value)
367	#undef IEM_MC_AND_GREG_U8
368
369	/** Variant of IEM_MC_OR_GREG_U8 with extended (20) register index. */
370	#define IEM_MC_OR_GREG_U8_THREADED(a_iGRegEx, a_u8Value) \
371	*iemGRegRefU8Ex(pVCpu, (a_iGRegEx)) \|= (a_u8Value)
372	#undef IEM_MC_OR_GREG_U8
373
374	/**
375	* Calculates the effective address of a ModR/M memory operand, 16-bit
376	* addressing variant.
377	*
378	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR16.
379	*
380	* @returns The effective address.
381	* @param pVCpu The cross context virtual CPU structure of the calling thread.
382	* @param bRm The ModRM byte.
383	* @param u16Disp The displacement byte/word, if any.
384	* RIP relative addressing.
385	*/
386	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr16(PVMCPUCC pVCpu, uint8_t bRm, uint16_t u16Disp) RT_NOEXCEPT
387	{
388	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: bRm=%#x u16Disp=%#x\n", bRm, u16Disp));
389	Assert(!IEM_IS_64BIT_CODE(pVCpu));
390
391	/* Handle the disp16 form with no registers first. */
392	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 6)
393	{
394	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16Disp));
395	return u16Disp;
396	}
397
398	/* Get the displacment. */
399	/** @todo we can eliminate this step by making u16Disp have this value
400	* already! */
401	uint16_t u16EffAddr;
402	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
403	{
404	case 0: u16EffAddr = 0; break;
405	case 1: u16EffAddr = (int16_t)(int8_t)u16Disp; break;
406	case 2: u16EffAddr = u16Disp; break;
407	default: AssertFailedStmt(u16EffAddr = 0);
408	}
409
410	/* Add the base and index registers to the disp. */
411	switch (bRm & X86_MODRM_RM_MASK)
412	{
413	case 0: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.si; break;
414	case 1: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.di; break;
415	case 2: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.si; break;
416	case 3: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.di; break;
417	case 4: u16EffAddr += pVCpu->cpum.GstCtx.si; break;
418	case 5: u16EffAddr += pVCpu->cpum.GstCtx.di; break;
419	case 6: u16EffAddr += pVCpu->cpum.GstCtx.bp; break;
420	case 7: u16EffAddr += pVCpu->cpum.GstCtx.bx; break;
421	}
422
423	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr16: EffAddr=%#010RGv\n", (RTGCPTR)u16EffAddr));
424	return u16EffAddr;
425	}
426
427
428	/**
429	* Calculates the effective address of a ModR/M memory operand, 32-bit
430	* addressing variant.
431	*
432	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32 and
433	* IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR32FLAT.
434	*
435	* @returns The effective address.
436	* @param pVCpu The cross context virtual CPU structure of the
437	* calling thread.
438	* @param bRm The ModRM byte.
439	* @param uSibAndRspOffset Two parts:
440	* - The first 8 bits make up the SIB byte.
441	* - The next 8 bits are the fixed RSP/ESP offse
442	* in case of a pop [xSP].
443	* @param u32Disp The displacement byte/dword, if any.
444	*/
445	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr32(PVMCPUCC pVCpu, uint8_t bRm, uint32_t uSibAndRspOffset,
446	uint32_t u32Disp) RT_NOEXCEPT
447	{
448	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: bRm=%#x uSibAndRspOffset=%#x u32Disp=%#x\n", bRm, uSibAndRspOffset, u32Disp));
449
450	/* Handle the disp32 form with no registers first. */
451	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
452	{
453	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32Disp));
454	return u32Disp;
455	}
456
457	/* Get the register (or SIB) value. */
458	uint32_t u32EffAddr;
459	#ifdef _MSC_VER
460	u32EffAddr = 0;/* MSC uninitialized variable analysis is too simple, it seems. */
461	#endif
462	switch (bRm & X86_MODRM_RM_MASK)
463	{
464	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
465	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
466	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
467	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
468	case 4: /* SIB */
469	{
470	/* Get the index and scale it. */
471	switch ((uSibAndRspOffset >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
472	{
473	case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
474	case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
475	case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
476	case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
477	case 4: u32EffAddr = 0; /none / break;
478	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
479	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
480	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
481	}
482	u32EffAddr <<= (uSibAndRspOffset >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
483
484	/* add base */
485	switch (uSibAndRspOffset & X86_SIB_BASE_MASK)
486	{
487	case 0: u32EffAddr += pVCpu->cpum.GstCtx.eax; break;
488	case 1: u32EffAddr += pVCpu->cpum.GstCtx.ecx; break;
489	case 2: u32EffAddr += pVCpu->cpum.GstCtx.edx; break;
490	case 3: u32EffAddr += pVCpu->cpum.GstCtx.ebx; break;
491	case 4:
492	u32EffAddr += pVCpu->cpum.GstCtx.esp;
493	u32EffAddr += uSibAndRspOffset >> 8;
494	break;
495	case 5:
496	if ((bRm & X86_MODRM_MOD_MASK) != 0)
497	u32EffAddr += pVCpu->cpum.GstCtx.ebp;
498	else
499	u32EffAddr += u32Disp;
500	break;
501	case 6: u32EffAddr += pVCpu->cpum.GstCtx.esi; break;
502	case 7: u32EffAddr += pVCpu->cpum.GstCtx.edi; break;
503	}
504	break;
505	}
506	case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
507	case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
508	case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
509	}
510
511	/* Get and add the displacement. */
512	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
513	{
514	case 0: break;
515	case 1: u32EffAddr += (int8_t)u32Disp; break;
516	case 2: u32EffAddr += u32Disp; break;
517	default: AssertFailed();
518	}
519
520	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr32: EffAddr=%#010RGv\n", (RTGCPTR)u32EffAddr));
521	return u32EffAddr;
522	}
523
524
525	/**
526	* Calculates the effective address of a ModR/M memory operand.
527	*
528	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR_THREADED_ADDR64.
529	*
530	* @returns The effective address.
531	* @param pVCpu The cross context virtual CPU structure of the
532	* calling thread.
533	* @param bRmEx The ModRM byte but with bit 3 set to REX.B and
534	* bit 4 to REX.X. The two bits are part of the
535	* REG sub-field, which isn't needed in this
536	* function.
537	* @param uSibAndRspOffset Two parts:
538	* - The first 8 bits make up the SIB byte.
539	* - The next 8 bits are the fixed RSP/ESP offse
540	* in case of a pop [xSP].
541	* @param u32Disp The displacement byte/word/dword, if any.
542	* @param cbInstr The size of the fully decoded instruction. Used
543	* for RIP relative addressing.
544	* @todo combine cbInstr and cbImm!
545	*/
546	static RTGCPTR iemOpHlpCalcRmEffAddrThreadedAddr64(PVMCPUCC pVCpu, uint8_t bRmEx, uint32_t uSibAndRspOffset,
547	uint32_t u32Disp, uint8_t cbInstr) RT_NOEXCEPT
548	{
549	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: bRmEx=%#x\n", bRmEx));
550	Assert(IEM_IS_64BIT_CODE(pVCpu));
551
552	uint64_t u64EffAddr;
553
554	/* Handle the rip+disp32 form with no registers first. */
555	if ((bRmEx & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
556	{
557	u64EffAddr = (int32_t)u32Disp;
558	u64EffAddr += pVCpu->cpum.GstCtx.rip + cbInstr;
559	}
560	else
561	{
562	/* Get the register (or SIB) value. */
563	#ifdef _MSC_VER
564	u64EffAddr = 0; /* MSC uninitialized variable analysis is too simple, it seems. */
565	#endif
566	switch (bRmEx & (X86_MODRM_RM_MASK \| 0x8)) /* bRmEx[bit 3] = REX.B */
567	{
568	default:
569	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
570	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
571	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
572	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
573	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
574	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
575	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
576	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
577	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
578	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
579	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
580	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
581	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
582	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
583	/* SIB */
584	case 4:
585	case 12:
586	{
587	/* Get the index and scale it. */
588	switch ( ((uSibAndRspOffset >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
589	\| ((bRmEx & 0x10) >> 1)) /* bRmEx[bit 4] = REX.X */
590	{
591	case 0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
592	case 1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
593	case 2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
594	case 3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
595	case 4: u64EffAddr = 0; /none / break;
596	case 5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
597	case 6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
598	case 7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
599	case 8: u64EffAddr = pVCpu->cpum.GstCtx.r8; break;
600	case 9: u64EffAddr = pVCpu->cpum.GstCtx.r9; break;
601	case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
602	case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
603	case 12: u64EffAddr = pVCpu->cpum.GstCtx.r12; break;
604	case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
605	case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
606	case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
607	}
608	u64EffAddr <<= (uSibAndRspOffset >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
609
610	/* add base */
611	switch ((uSibAndRspOffset & X86_SIB_BASE_MASK) \| (bRmEx & 0x8)) /* bRmEx[bit 3] = REX.B */
612	{
613	case 0: u64EffAddr += pVCpu->cpum.GstCtx.rax; break;
614	case 1: u64EffAddr += pVCpu->cpum.GstCtx.rcx; break;
615	case 2: u64EffAddr += pVCpu->cpum.GstCtx.rdx; break;
616	case 3: u64EffAddr += pVCpu->cpum.GstCtx.rbx; break;
617	case 4:
618	u64EffAddr += pVCpu->cpum.GstCtx.rsp;
619	u64EffAddr += uSibAndRspOffset >> 8;
620	break;
621	case 6: u64EffAddr += pVCpu->cpum.GstCtx.rsi; break;
622	case 7: u64EffAddr += pVCpu->cpum.GstCtx.rdi; break;
623	case 8: u64EffAddr += pVCpu->cpum.GstCtx.r8; break;
624	case 9: u64EffAddr += pVCpu->cpum.GstCtx.r9; break;
625	case 10: u64EffAddr += pVCpu->cpum.GstCtx.r10; break;
626	case 11: u64EffAddr += pVCpu->cpum.GstCtx.r11; break;
627	case 12: u64EffAddr += pVCpu->cpum.GstCtx.r12; break;
628	case 14: u64EffAddr += pVCpu->cpum.GstCtx.r14; break;
629	case 15: u64EffAddr += pVCpu->cpum.GstCtx.r15; break;
630	/* complicated encodings */
631	case 5:
632	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
633	u64EffAddr += pVCpu->cpum.GstCtx.rbp;
634	else
635	u64EffAddr += (int32_t)u32Disp;
636	break;
637	case 13:
638	if ((bRmEx & X86_MODRM_MOD_MASK) != 0)
639	u64EffAddr += pVCpu->cpum.GstCtx.r13;
640	else
641	u64EffAddr += (int32_t)u32Disp;
642	break;
643	}
644	break;
645	}
646	}
647
648	/* Get and add the displacement. */
649	switch ((bRmEx >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
650	{
651	case 0: break;
652	case 1: u64EffAddr += (int8_t)u32Disp; break;
653	case 2: u64EffAddr += (int32_t)u32Disp; break;
654	default: AssertFailed();
655	}
656	}
657
658	Log5(("iemOpHlpCalcRmEffAddrThreadedAddr64: EffAddr=%#010RGv\n", u64EffAddr));
659	return u64EffAddr;
660	}
661
662
663	/*
664	* The threaded functions.
665	*/
666	#include "IEMThreadedFunctions.cpp.h"
667

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllThrdFuncs.cpp@ 102020

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