| 1 | /* $Id: IEMAllThrdTables.h 100761 2023-08-01 02:24:11Z vboxsync $ */
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| 2 | /** @file
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| 3 | * IEM - Instruction Decoding and Threaded Recompilation, Instruction Tables.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2011-2023 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 | #ifndef VMM_INCLUDED_SRC_VMMAll_IEMAllThrdTables_h
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| 29 | #define VMM_INCLUDED_SRC_VMMAll_IEMAllThrdTables_h
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| 30 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 31 | # pragma once
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| 32 | #endif
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| 33 |
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| 34 |
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| 35 | /*********************************************************************************************************************************
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| 36 | * Header Files *
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| 37 | *********************************************************************************************************************************/
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| 38 | #ifndef LOG_GROUP /* defined when included by tstIEMCheckMc.cpp */
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| 39 | # define LOG_GROUP LOG_GROUP_IEM_RE_THREADED
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| 40 | #endif
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| 41 | #define IEM_WITH_CODE_TLB_AND_OPCODE_BUF /* A bit hackish, but its all in IEMInline.h. */
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| 42 | #define VMCPU_INCL_CPUM_GST_CTX
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| 43 | #include <VBox/vmm/iem.h>
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| 44 | #include <VBox/vmm/cpum.h>
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| 45 | #include <VBox/vmm/apic.h>
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| 46 | #include <VBox/vmm/pdm.h>
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| 47 | #include <VBox/vmm/pgm.h>
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| 48 | #include <VBox/vmm/iom.h>
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| 49 | #include <VBox/vmm/em.h>
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| 50 | #include <VBox/vmm/hm.h>
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| 51 | #include <VBox/vmm/nem.h>
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| 52 | #include <VBox/vmm/gim.h>
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| 53 | #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
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| 54 | # include <VBox/vmm/em.h>
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| 55 | # include <VBox/vmm/hm_svm.h>
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| 56 | #endif
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| 57 | #ifdef VBOX_WITH_NESTED_HWVIRT_VMX
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| 58 | # include <VBox/vmm/hmvmxinline.h>
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| 59 | #endif
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| 60 | #include <VBox/vmm/tm.h>
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| 61 | #include <VBox/vmm/dbgf.h>
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| 62 | #include <VBox/vmm/dbgftrace.h>
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| 63 | #ifndef TST_IEM_CHECK_MC
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| 64 | # include "IEMInternal.h"
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| 65 | #endif
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| 66 | #include <VBox/vmm/vmcc.h>
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| 67 | #include <VBox/log.h>
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| 68 | #include <VBox/err.h>
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| 69 | #include <VBox/param.h>
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| 70 | #include <VBox/dis.h>
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| 71 | #include <VBox/disopcode-x86-amd64.h>
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| 72 | #include <iprt/asm-math.h>
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| 73 | #include <iprt/assert.h>
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| 74 | #include <iprt/mem.h>
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| 75 | #include <iprt/string.h>
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| 76 | #include <iprt/x86.h>
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| 77 |
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| 78 | #ifndef TST_IEM_CHECK_MC
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| 79 | # include "IEMInline.h"
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| 80 | # include "IEMOpHlp.h"
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| 81 | # include "IEMMc.h"
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| 82 | #endif
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| 83 |
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| 84 | #include "IEMThreadedFunctions.h"
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| 85 |
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| 86 |
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| 87 | /*
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| 88 | * Narrow down configs here to avoid wasting time on unused configs here.
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| 89 | */
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| 90 |
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| 91 | #ifndef IEM_WITH_CODE_TLB
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| 92 | # error The code TLB must be enabled for the recompiler.
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| 93 | #endif
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| 94 |
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| 95 | #ifndef IEM_WITH_DATA_TLB
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| 96 | # error The data TLB must be enabled for the recompiler.
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| 97 | #endif
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| 98 |
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| 99 | #ifndef IEM_WITH_SETJMP
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| 100 | # error The setjmp approach must be enabled for the recompiler.
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| 101 | #endif
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| 102 |
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| 103 |
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| 104 | /*********************************************************************************************************************************
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| 105 | * Defined Constants And Macros *
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| 106 | *********************************************************************************************************************************/
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| 107 | #define g_apfnOneByteMap g_apfnIemThreadedRecompilerOneByteMap
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| 108 | #define g_apfnTwoByteMap g_apfnIemThreadedRecompilerTwoByteMap
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| 109 | #define g_apfnThreeByte0f3a g_apfnIemThreadedRecompilerThreeByte0f3a
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| 110 | #define g_apfnThreeByte0f38 g_apfnIemThreadedRecompilerThreeByte0f38
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| 111 | #define g_apfnVexMap1 g_apfnIemThreadedRecompilerVecMap1
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| 112 | #define g_apfnVexMap2 g_apfnIemThreadedRecompilerVecMap2
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| 113 | #define g_apfnVexMap3 g_apfnIemThreadedRecompilerVecMap3
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| 114 |
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| 115 |
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| 116 | /*
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| 117 | * Override IEM_MC_CALC_RM_EFF_ADDR to use iemOpHlpCalcRmEffAddrJmpEx and produce uEffAddrInfo.
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| 118 | */
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| 119 | #undef IEM_MC_CALC_RM_EFF_ADDR
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| 120 | #ifndef IEM_WITH_SETJMP
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| 121 | # define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
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| 122 | uint64_t uEffAddrInfo; \
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| 123 | IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddrJmpEx(pVCpu, (a_bRm), (a_cbImmAndRspOffset), &(a_GCPtrEff), &uEffAddrInfo))
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| 124 | #else
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| 125 | # define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
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| 126 | uint64_t uEffAddrInfo; \
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| 127 | ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmpEx(pVCpu, (a_bRm), (a_cbImmAndRspOffset), &uEffAddrInfo))
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| 128 | #endif
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| 129 |
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| 130 | /*
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| 131 | * Likewise override IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES so we fetch all the opcodes.
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| 132 | */
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| 133 | #undef IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES
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| 134 | #define IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(a_bRm) do { \
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| 135 | uint64_t uEffAddrInfo; \
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| 136 | (void)iemOpHlpCalcRmEffAddrJmpEx(pVCpu, bRm, 0, &uEffAddrInfo); \
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| 137 | } while (0)
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| 138 |
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| 139 | /*
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| 140 | * Override the IEM_MC_REL_JMP_S*_AND_FINISH macros to check for zero byte jumps.
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| 141 | */
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| 142 | #undef IEM_MC_REL_JMP_S8_AND_FINISH
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| 143 | #define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) do { \
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| 144 | Assert(pVCpu->iem.s.fTbBranched != 0); \
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| 145 | if ((a_i8) == 0) \
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| 146 | pVCpu->iem.s.fTbBranched |= IEMBRANCHED_F_ZERO; \
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| 147 | return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize); \
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| 148 | } while (0)
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| 149 |
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| 150 | #undef IEM_MC_REL_JMP_S16_AND_FINISH
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| 151 | #define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) do { \
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| 152 | Assert(pVCpu->iem.s.fTbBranched != 0); \
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| 153 | if ((a_i16) == 0) \
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| 154 | pVCpu->iem.s.fTbBranched |= IEMBRANCHED_F_ZERO; \
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| 155 | return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16)); \
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| 156 | } while (0)
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| 157 |
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| 158 | #undef IEM_MC_REL_JMP_S32_AND_FINISH
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| 159 | #define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) do { \
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| 160 | Assert(pVCpu->iem.s.fTbBranched != 0); \
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| 161 | if ((a_i32) == 0) \
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| 162 | pVCpu->iem.s.fTbBranched |= IEMBRANCHED_F_ZERO; \
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| 163 | return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize); \
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| 164 | } while (0)
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| 165 |
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| 166 |
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| 167 | /*
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| 168 | * Emit call macros.
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| 169 | */
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| 170 | #define IEM_MC2_BEGIN_EMIT_CALLS() \
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| 171 | { \
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| 172 | PIEMTB const pTb = pVCpu->iem.s.pCurTbR3; \
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| 173 | uint8_t const cbInstrMc2 = IEM_GET_INSTR_LEN(pVCpu); \
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| 174 | AssertMsg(pVCpu->iem.s.offOpcode == cbInstrMc2, \
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| 175 | ("%u vs %u (%04x:%08RX64)\n", pVCpu->iem.s.offOpcode, cbInstrMc2, \
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| 176 | pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip)); \
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| 177 | \
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| 178 | /* No page crossing, right? */ \
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| 179 | uint16_t const offOpcodeMc2 = pTb->cbOpcodes; \
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| 180 | uint8_t const idxRangeMc2 = pTb->cRanges - 1; \
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| 181 | if ( !pVCpu->iem.s.fTbCrossedPage \
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| 182 | && !pVCpu->iem.s.fTbCheckOpcodes \
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| 183 | && !pVCpu->iem.s.fTbBranched \
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| 184 | && !(pTb->fFlags & IEMTB_F_CS_LIM_CHECKS)) \
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| 185 | { \
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| 186 | /** @todo Custom copy function, given range is 1 thru 15 bytes. */ \
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| 187 | memcpy(&pTb->pabOpcodes[offOpcodeMc2], pVCpu->iem.s.abOpcode, pVCpu->iem.s.offOpcode); \
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| 188 | pTb->cbOpcodes = offOpcodeMc2 + pVCpu->iem.s.offOpcode; \
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| 189 | pTb->aRanges[idxRangeMc2].cbOpcodes += cbInstrMc2; \
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| 190 | Assert(pTb->cbOpcodes <= pTb->cbOpcodesAllocated); \
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| 191 | } \
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| 192 | else if (iemThreadedCompileBeginEmitCallsComplications(pVCpu, pTb)) \
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| 193 | { /* likely */ } \
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| 194 | else \
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| 195 | return VINF_IEM_RECOMPILE_END_TB; \
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| 196 | \
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| 197 | do { } while (0)
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| 198 | #define IEM_MC2_EMIT_CALL_0(a_enmFunction) do { \
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| 199 | IEMTHREADEDFUNCS const enmFunctionCheck = a_enmFunction; RT_NOREF(enmFunctionCheck); \
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| 200 | \
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| 201 | PIEMTHRDEDCALLENTRY const pCall = &pTb->Thrd.paCalls[pTb->Thrd.cCalls++]; \
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| 202 | pCall->enmFunction = a_enmFunction; \
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| 203 | pCall->offOpcode = offOpcodeMc2; \
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| 204 | pCall->cbOpcode = cbInstrMc2; \
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| 205 | pCall->idxRange = idxRangeMc2; \
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| 206 | pCall->auParams[0] = 0; \
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| 207 | pCall->auParams[1] = 0; \
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| 208 | pCall->auParams[2] = 0; \
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| 209 | } while (0)
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| 210 | #define IEM_MC2_EMIT_CALL_1(a_enmFunction, a_uArg0) do { \
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| 211 | IEMTHREADEDFUNCS const enmFunctionCheck = a_enmFunction; RT_NOREF(enmFunctionCheck); \
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| 212 | uint64_t const uArg0Check = (a_uArg0); RT_NOREF(uArg0Check); \
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| 213 | \
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| 214 | PIEMTHRDEDCALLENTRY const pCall = &pTb->Thrd.paCalls[pTb->Thrd.cCalls++]; \
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| 215 | pCall->enmFunction = a_enmFunction; \
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| 216 | pCall->offOpcode = offOpcodeMc2; \
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| 217 | pCall->cbOpcode = cbInstrMc2; \
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| 218 | pCall->idxRange = idxRangeMc2; \
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| 219 | pCall->auParams[0] = a_uArg0; \
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| 220 | pCall->auParams[1] = 0; \
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| 221 | pCall->auParams[2] = 0; \
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| 222 | } while (0)
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| 223 | #define IEM_MC2_EMIT_CALL_2(a_enmFunction, a_uArg0, a_uArg1) do { \
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| 224 | IEMTHREADEDFUNCS const enmFunctionCheck = a_enmFunction; RT_NOREF(enmFunctionCheck); \
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| 225 | uint64_t const uArg0Check = (a_uArg0); RT_NOREF(uArg0Check); \
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| 226 | uint64_t const uArg1Check = (a_uArg1); RT_NOREF(uArg1Check); \
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| 227 | \
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| 228 | PIEMTHRDEDCALLENTRY const pCall = &pTb->Thrd.paCalls[pTb->Thrd.cCalls++]; \
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| 229 | pCall->enmFunction = a_enmFunction; \
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| 230 | pCall->offOpcode = offOpcodeMc2; \
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| 231 | pCall->cbOpcode = cbInstrMc2; \
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| 232 | pCall->idxRange = idxRangeMc2; \
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| 233 | pCall->auParams[0] = a_uArg0; \
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| 234 | pCall->auParams[1] = a_uArg1; \
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| 235 | pCall->auParams[2] = 0; \
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| 236 | } while (0)
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| 237 | #define IEM_MC2_EMIT_CALL_3(a_enmFunction, a_uArg0, a_uArg1, a_uArg2) do { \
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| 238 | IEMTHREADEDFUNCS const enmFunctionCheck = a_enmFunction; RT_NOREF(enmFunctionCheck); \
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| 239 | uint64_t const uArg0Check = (a_uArg0); RT_NOREF(uArg0Check); \
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| 240 | uint64_t const uArg1Check = (a_uArg1); RT_NOREF(uArg1Check); \
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| 241 | uint64_t const uArg2Check = (a_uArg2); RT_NOREF(uArg2Check); \
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| 242 | \
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| 243 | PIEMTHRDEDCALLENTRY const pCall = &pTb->Thrd.paCalls[pTb->Thrd.cCalls++]; \
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| 244 | pCall->enmFunction = a_enmFunction; \
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| 245 | pCall->offOpcode = offOpcodeMc2; \
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| 246 | pCall->cbOpcode = cbInstrMc2; \
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| 247 | pCall->idxRange = idxRangeMc2; \
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| 248 | pCall->auParams[0] = a_uArg0; \
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| 249 | pCall->auParams[1] = a_uArg1; \
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| 250 | pCall->auParams[2] = a_uArg2; \
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| 251 | } while (0)
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| 252 | #define IEM_MC2_END_EMIT_CALLS(a_fCImplFlags) \
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| 253 | Assert(pTb->cInstructions <= pTb->Thrd.cCalls); \
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| 254 | if (pTb->cInstructions < 255) \
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| 255 | pTb->cInstructions++; \
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| 256 | uint32_t const fCImplFlagsMc2 = (a_fCImplFlags); \
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| 257 | RT_NOREF(fCImplFlagsMc2); \
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| 258 | } while (0)
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| 259 |
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| 260 |
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| 261 | /*
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| 262 | * IEM_MC_DEFER_TO_CIMPL_0 is easily wrapped up.
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| 263 | *
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| 264 | * Doing so will also take care of IEMOP_RAISE_DIVIDE_ERROR, IEMOP_RAISE_INVALID_LOCK_PREFIX,
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| 265 | * IEMOP_RAISE_INVALID_OPCODE and their users.
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| 266 | */
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| 267 | #undef IEM_MC_DEFER_TO_CIMPL_0_RET
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| 268 | #define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_pfnCImpl) \
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| 269 | return iemThreadedRecompilerMcDeferToCImpl0(pVCpu, a_fFlags, a_pfnCImpl)
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| 270 |
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| 271 | DECLINLINE(VBOXSTRICTRC) iemThreadedRecompilerMcDeferToCImpl0(PVMCPUCC pVCpu, uint32_t fFlags, PFNIEMCIMPL0 pfnCImpl)
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| 272 | {
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| 273 | Log8(("CImpl0: %04x:%08RX64 LB %#x: %#x %p\n",
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| 274 | pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IEM_GET_INSTR_LEN(pVCpu), fFlags, pfnCImpl));
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| 275 |
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| 276 | IEM_MC2_BEGIN_EMIT_CALLS();
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| 277 | IEM_MC2_EMIT_CALL_2(kIemThreadedFunc_BltIn_DeferToCImpl0, (uintptr_t)pfnCImpl, IEM_GET_INSTR_LEN(pVCpu));
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| 278 | IEM_MC2_END_EMIT_CALLS(fFlags);
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| 279 |
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| 280 | /*
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| 281 | * We have to repeat work normally done by kdCImplFlags and
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| 282 | * ThreadedFunctionVariation.emitThreadedCallStmts here.
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| 283 | */
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| 284 | AssertCompile(IEM_CIMPL_F_BRANCH_DIRECT == IEMBRANCHED_F_DIRECT);
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| 285 | AssertCompile(IEM_CIMPL_F_BRANCH_INDIRECT == IEMBRANCHED_F_INDIRECT);
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| 286 | AssertCompile(IEM_CIMPL_F_BRANCH_RELATIVE == IEMBRANCHED_F_RELATIVE);
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| 287 | AssertCompile(IEM_CIMPL_F_BRANCH_CONDITIONAL == IEMBRANCHED_F_CONDITIONAL);
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| 288 | AssertCompile(IEM_CIMPL_F_BRANCH_FAR == IEMBRANCHED_F_FAR);
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| 289 |
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| 290 | if (fFlags & (IEM_CIMPL_F_END_TB | IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_REP))
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| 291 | pVCpu->iem.s.fEndTb = true;
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| 292 | else if (fFlags & IEM_CIMPL_F_BRANCH_ANY)
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| 293 | pVCpu->iem.s.fTbBranched = fFlags & (IEM_CIMPL_F_BRANCH_ANY | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_CONDITIONAL);
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| 294 |
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| 295 | if (fFlags & IEM_CIMPL_F_CHECK_IRQ)
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| 296 | pVCpu->iem.s.cInstrTillIrqCheck = 0;
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| 297 | else if (fFlags & IEM_CIMPL_F_CHECK_IRQ_DELAYED)
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| 298 | pVCpu->iem.s.cInstrTillIrqCheck = 1;
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| 299 |
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| 300 | return pfnCImpl(pVCpu, IEM_GET_INSTR_LEN(pVCpu));
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| 301 | }
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| 302 |
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| 303 |
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| 304 | /**
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| 305 | * Helper for indicating that we've branched.
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| 306 | */
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| 307 | DECL_FORCE_INLINE(void) iemThreadedSetBranched(PVMCPUCC pVCpu, uint8_t fTbBranched)
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| 308 | {
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| 309 | pVCpu->iem.s.fTbBranched = fTbBranched;
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| 310 | pVCpu->iem.s.GCPhysTbBranchSrcBuf = pVCpu->iem.s.GCPhysInstrBuf;
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| 311 | pVCpu->iem.s.GCVirtTbBranchSrcBuf = pVCpu->iem.s.uInstrBufPc;
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| 312 | }
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| 313 |
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| 314 |
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| 315 | #endif /* !VMM_INCLUDED_SRC_VMMAll_IEMAllThrdTables_h */
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