IEMAllThrdTables.h@ 100787

Last change on this file since 100787 was 100787, checked in by vboxsync, 16 months ago
VMM/IEM: Check for IRQs immediately after STI as well as after the following instruction. Also check before and after POPF. Ignore IEM_CIMPL_F_VMEXIT for now as it prevents sti+sti+cli and similar tests from forming a single TB, sabotaging testing of these changes. bugref:10369
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File size: 13.2 KB

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1	/* $Id: IEMAllThrdTables.h 100787 2023-08-03 21:53:28Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Threaded Recompilation, Instruction Tables.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License. 8
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_VMMAll_IEMAllThrdTables_h
29	#define VMM_INCLUDED_SRC_VMMAll_IEMAllThrdTables_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34
35	/*********************************************************************************************************************************
36	* Header Files *
37	*********************************************************************************************************************************/
38	#ifndef LOG_GROUP /* defined when included by tstIEMCheckMc.cpp */
39	# define LOG_GROUP LOG_GROUP_IEM_RE_THREADED
40	#endif
41	#define IEM_WITH_CODE_TLB_AND_OPCODE_BUF /* A bit hackish, but its all in IEMInline.h. */
42	#define VMCPU_INCL_CPUM_GST_CTX
43	#include <VBox/vmm/iem.h>
44	#include <VBox/vmm/cpum.h>
45	#include <VBox/vmm/apic.h>
46	#include <VBox/vmm/pdm.h>
47	#include <VBox/vmm/pgm.h>
48	#include <VBox/vmm/iom.h>
49	#include <VBox/vmm/em.h>
50	#include <VBox/vmm/hm.h>
51	#include <VBox/vmm/nem.h>
52	#include <VBox/vmm/gim.h>
53	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
54	# include <VBox/vmm/em.h>
55	# include <VBox/vmm/hm_svm.h>
56	#endif
57	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
58	# include <VBox/vmm/hmvmxinline.h>
59	#endif
60	#include <VBox/vmm/tm.h>
61	#include <VBox/vmm/dbgf.h>
62	#include <VBox/vmm/dbgftrace.h>
63	#ifndef TST_IEM_CHECK_MC
64	# include "IEMInternal.h"
65	#endif
66	#include <VBox/vmm/vmcc.h>
67	#include <VBox/log.h>
68	#include <VBox/err.h>
69	#include <VBox/param.h>
70	#include <VBox/dis.h>
71	#include <VBox/disopcode-x86-amd64.h>
72	#include <iprt/asm-math.h>
73	#include <iprt/assert.h>
74	#include <iprt/mem.h>
75	#include <iprt/string.h>
76	#include <iprt/x86.h>
77
78	#ifndef TST_IEM_CHECK_MC
79	# include "IEMInline.h"
80	# include "IEMOpHlp.h"
81	# include "IEMMc.h"
82	#endif
83
84	#include "IEMThreadedFunctions.h"
85
86
87	/*
88	* Narrow down configs here to avoid wasting time on unused configs here.
89	*/
90
91	#ifndef IEM_WITH_CODE_TLB
92	# error The code TLB must be enabled for the recompiler.
93	#endif
94
95	#ifndef IEM_WITH_DATA_TLB
96	# error The data TLB must be enabled for the recompiler.
97	#endif
98
99	#ifndef IEM_WITH_SETJMP
100	# error The setjmp approach must be enabled for the recompiler.
101	#endif
102
103
104	/*********************************************************************************************************************************
105	* Defined Constants And Macros *
106	*********************************************************************************************************************************/
107	#define g_apfnOneByteMap g_apfnIemThreadedRecompilerOneByteMap
108	#define g_apfnTwoByteMap g_apfnIemThreadedRecompilerTwoByteMap
109	#define g_apfnThreeByte0f3a g_apfnIemThreadedRecompilerThreeByte0f3a
110	#define g_apfnThreeByte0f38 g_apfnIemThreadedRecompilerThreeByte0f38
111	#define g_apfnVexMap1 g_apfnIemThreadedRecompilerVecMap1
112	#define g_apfnVexMap2 g_apfnIemThreadedRecompilerVecMap2
113	#define g_apfnVexMap3 g_apfnIemThreadedRecompilerVecMap3
114
115
116	/*
117	* Override IEM_MC_CALC_RM_EFF_ADDR to use iemOpHlpCalcRmEffAddrJmpEx and produce uEffAddrInfo.
118	*/
119	#undef IEM_MC_CALC_RM_EFF_ADDR
120	#ifndef IEM_WITH_SETJMP
121	# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
122	uint64_t uEffAddrInfo; \
123	IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddrJmpEx(pVCpu, (a_bRm), (a_cbImmAndRspOffset), &(a_GCPtrEff), &uEffAddrInfo))
124	#else
125	# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
126	uint64_t uEffAddrInfo; \
127	((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmpEx(pVCpu, (a_bRm), (a_cbImmAndRspOffset), &uEffAddrInfo))
128	#endif
129
130	/*
131	* Likewise override IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES so we fetch all the opcodes.
132	*/
133	#undef IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES
134	#define IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(a_bRm) do { \
135	uint64_t uEffAddrInfo; \
136	(void)iemOpHlpCalcRmEffAddrJmpEx(pVCpu, bRm, 0, &uEffAddrInfo); \
137	} while (0)
138
139	/*
140	* Override the IEM_MC_REL_JMP_S*_AND_FINISH macros to check for zero byte jumps.
141	*/
142	#undef IEM_MC_REL_JMP_S8_AND_FINISH
143	#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) do { \
144	Assert(pVCpu->iem.s.fTbBranched != 0); \
145	if ((a_i8) == 0) \
146	pVCpu->iem.s.fTbBranched \|= IEMBRANCHED_F_ZERO; \
147	return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize); \
148	} while (0)
149
150	#undef IEM_MC_REL_JMP_S16_AND_FINISH
151	#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) do { \
152	Assert(pVCpu->iem.s.fTbBranched != 0); \
153	if ((a_i16) == 0) \
154	pVCpu->iem.s.fTbBranched \|= IEMBRANCHED_F_ZERO; \
155	return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16)); \
156	} while (0)
157
158	#undef IEM_MC_REL_JMP_S32_AND_FINISH
159	#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) do { \
160	Assert(pVCpu->iem.s.fTbBranched != 0); \
161	if ((a_i32) == 0) \
162	pVCpu->iem.s.fTbBranched \|= IEMBRANCHED_F_ZERO; \
163	return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize); \
164	} while (0)
165
166
167	/*
168	* Emit call macros.
169	*/
170	#define IEM_MC2_BEGIN_EMIT_CALLS(a_fCheckIrqBefore) \
171	{ \
172	PIEMTB const pTb = pVCpu->iem.s.pCurTbR3; \
173	uint8_t const cbInstrMc2 = IEM_GET_INSTR_LEN(pVCpu); \
174	AssertMsg(pVCpu->iem.s.offOpcode == cbInstrMc2, \
175	("%u vs %u (%04x:%08RX64)\n", pVCpu->iem.s.offOpcode, cbInstrMc2, \
176	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip)); \
177	\
178	/* If we need to check for IRQs before the instruction, we do that before \
179	adding any opcodes as it may abort the instruction. \
180	Note! During compilation, we may swap IRQ and #PF exceptions here \
181	in a manner that a real CPU would not do. However it shouldn't \
182	be something that is easy (if at all possible) to observe in the \
183	guest, so fine. The unexpected end-of-tb below have the same \
184	potential "issue". */ \
185	if (!(a_fCheckIrqBefore) \|\| iemThreadedCompileEmitIrqCheckBefore(pVCpu, pTb)) \
186	{ /* likely */ } \
187	else \
188	return VINF_IEM_RECOMPILE_END_TB; \
189	\
190	/* No page crossing, right? */ \
191	uint16_t const offOpcodeMc2 = pTb->cbOpcodes; \
192	uint8_t const idxRangeMc2 = pTb->cRanges - 1; \
193	if ( !pVCpu->iem.s.fTbCrossedPage \
194	&& !pVCpu->iem.s.fTbCheckOpcodes \
195	&& !pVCpu->iem.s.fTbBranched \
196	&& !(pTb->fFlags & IEMTB_F_CS_LIM_CHECKS)) \
197	{ \
198	/** @todo Custom copy function, given range is 1 thru 15 bytes. */ \
199	memcpy(&pTb->pabOpcodes[offOpcodeMc2], pVCpu->iem.s.abOpcode, pVCpu->iem.s.offOpcode); \
200	pTb->cbOpcodes = offOpcodeMc2 + pVCpu->iem.s.offOpcode; \
201	pTb->aRanges[idxRangeMc2].cbOpcodes += cbInstrMc2; \
202	Assert(pTb->cbOpcodes <= pTb->cbOpcodesAllocated); \
203	} \
204	else if (iemThreadedCompileBeginEmitCallsComplications(pVCpu, pTb)) \
205	{ /* likely */ } \
206	else \
207	return VINF_IEM_RECOMPILE_END_TB; \
208	\
209	do { } while (0)
210	#define IEM_MC2_EMIT_CALL_0(a_enmFunction) do { \
211	IEMTHREADEDFUNCS const enmFunctionCheck = a_enmFunction; RT_NOREF(enmFunctionCheck); \
212	\
213	PIEMTHRDEDCALLENTRY const pCall = &pTb->Thrd.paCalls[pTb->Thrd.cCalls++]; \
214	pCall->enmFunction = a_enmFunction; \
215	pCall->offOpcode = offOpcodeMc2; \
216	pCall->cbOpcode = cbInstrMc2; \
217	pCall->idxRange = idxRangeMc2; \
218	pCall->auParams[0] = 0; \
219	pCall->auParams[1] = 0; \
220	pCall->auParams[2] = 0; \
221	} while (0)
222	#define IEM_MC2_EMIT_CALL_1(a_enmFunction, a_uArg0) do { \
223	IEMTHREADEDFUNCS const enmFunctionCheck = a_enmFunction; RT_NOREF(enmFunctionCheck); \
224	uint64_t const uArg0Check = (a_uArg0); RT_NOREF(uArg0Check); \
225	\
226	PIEMTHRDEDCALLENTRY const pCall = &pTb->Thrd.paCalls[pTb->Thrd.cCalls++]; \
227	pCall->enmFunction = a_enmFunction; \
228	pCall->offOpcode = offOpcodeMc2; \
229	pCall->cbOpcode = cbInstrMc2; \
230	pCall->idxRange = idxRangeMc2; \
231	pCall->auParams[0] = a_uArg0; \
232	pCall->auParams[1] = 0; \
233	pCall->auParams[2] = 0; \
234	} while (0)
235	#define IEM_MC2_EMIT_CALL_2(a_enmFunction, a_uArg0, a_uArg1) do { \
236	IEMTHREADEDFUNCS const enmFunctionCheck = a_enmFunction; RT_NOREF(enmFunctionCheck); \
237	uint64_t const uArg0Check = (a_uArg0); RT_NOREF(uArg0Check); \
238	uint64_t const uArg1Check = (a_uArg1); RT_NOREF(uArg1Check); \
239	\
240	PIEMTHRDEDCALLENTRY const pCall = &pTb->Thrd.paCalls[pTb->Thrd.cCalls++]; \
241	pCall->enmFunction = a_enmFunction; \
242	pCall->offOpcode = offOpcodeMc2; \
243	pCall->cbOpcode = cbInstrMc2; \
244	pCall->idxRange = idxRangeMc2; \
245	pCall->auParams[0] = a_uArg0; \
246	pCall->auParams[1] = a_uArg1; \
247	pCall->auParams[2] = 0; \
248	} while (0)
249	#define IEM_MC2_EMIT_CALL_3(a_enmFunction, a_uArg0, a_uArg1, a_uArg2) do { \
250	IEMTHREADEDFUNCS const enmFunctionCheck = a_enmFunction; RT_NOREF(enmFunctionCheck); \
251	uint64_t const uArg0Check = (a_uArg0); RT_NOREF(uArg0Check); \
252	uint64_t const uArg1Check = (a_uArg1); RT_NOREF(uArg1Check); \
253	uint64_t const uArg2Check = (a_uArg2); RT_NOREF(uArg2Check); \
254	\
255	PIEMTHRDEDCALLENTRY const pCall = &pTb->Thrd.paCalls[pTb->Thrd.cCalls++]; \
256	pCall->enmFunction = a_enmFunction; \
257	pCall->offOpcode = offOpcodeMc2; \
258	pCall->cbOpcode = cbInstrMc2; \
259	pCall->idxRange = idxRangeMc2; \
260	pCall->auParams[0] = a_uArg0; \
261	pCall->auParams[1] = a_uArg1; \
262	pCall->auParams[2] = a_uArg2; \
263	} while (0)
264	#define IEM_MC2_END_EMIT_CALLS(a_fCImplFlags) \
265	Assert(pTb->cInstructions <= pTb->Thrd.cCalls); \
266	if (pTb->cInstructions < 255) \
267	pTb->cInstructions++; \
268	uint32_t const fCImplFlagsMc2 = (a_fCImplFlags); \
269	RT_NOREF(fCImplFlagsMc2); \
270	} while (0)
271
272
273	/*
274	* IEM_MC_DEFER_TO_CIMPL_0 is easily wrapped up.
275	*
276	* Doing so will also take care of IEMOP_RAISE_DIVIDE_ERROR, IEMOP_RAISE_INVALID_LOCK_PREFIX,
277	* IEMOP_RAISE_INVALID_OPCODE and their users.
278	*/
279	#undef IEM_MC_DEFER_TO_CIMPL_0_RET
280	#define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_pfnCImpl) \
281	return iemThreadedRecompilerMcDeferToCImpl0(pVCpu, a_fFlags, a_pfnCImpl)
282
283	DECLINLINE(VBOXSTRICTRC) iemThreadedRecompilerMcDeferToCImpl0(PVMCPUCC pVCpu, uint32_t fFlags, PFNIEMCIMPL0 pfnCImpl)
284	{
285	Log8(("CImpl0: %04x:%08RX64 LB %#x: %#x %p\n",
286	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IEM_GET_INSTR_LEN(pVCpu), fFlags, pfnCImpl));
287
288	IEM_MC2_BEGIN_EMIT_CALLS(fFlags & IEM_CIMPL_F_CHECK_IRQ_BEFORE);
289	IEM_MC2_EMIT_CALL_2(kIemThreadedFunc_BltIn_DeferToCImpl0, (uintptr_t)pfnCImpl, IEM_GET_INSTR_LEN(pVCpu));
290	IEM_MC2_END_EMIT_CALLS(fFlags);
291
292	/*
293	* We have to repeat work normally done by kdCImplFlags and
294	* ThreadedFunctionVariation.emitThreadedCallStmts here.
295	*/
296	AssertCompile(IEM_CIMPL_F_BRANCH_DIRECT == IEMBRANCHED_F_DIRECT);
297	AssertCompile(IEM_CIMPL_F_BRANCH_INDIRECT == IEMBRANCHED_F_INDIRECT);
298	AssertCompile(IEM_CIMPL_F_BRANCH_RELATIVE == IEMBRANCHED_F_RELATIVE);
299	AssertCompile(IEM_CIMPL_F_BRANCH_CONDITIONAL == IEMBRANCHED_F_CONDITIONAL);
300	AssertCompile(IEM_CIMPL_F_BRANCH_FAR == IEMBRANCHED_F_FAR);
301
302	if (fFlags & (IEM_CIMPL_F_END_TB \| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_REP))
303	pVCpu->iem.s.fEndTb = true;
304	else if (fFlags & IEM_CIMPL_F_BRANCH_ANY)
305	pVCpu->iem.s.fTbBranched = fFlags & (IEM_CIMPL_F_BRANCH_ANY \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_CONDITIONAL);
306
307	if (fFlags & IEM_CIMPL_F_CHECK_IRQ_BEFORE)
308	pVCpu->iem.s.cInstrTillIrqCheck = 0;
309
310	return pfnCImpl(pVCpu, IEM_GET_INSTR_LEN(pVCpu));
311	}
312
313
314	/**
315	* Helper for indicating that we've branched.
316	*/
317	DECL_FORCE_INLINE(void) iemThreadedSetBranched(PVMCPUCC pVCpu, uint8_t fTbBranched)
318	{
319	pVCpu->iem.s.fTbBranched = fTbBranched;
320	pVCpu->iem.s.GCPhysTbBranchSrcBuf = pVCpu->iem.s.GCPhysInstrBuf;
321	pVCpu->iem.s.GCVirtTbBranchSrcBuf = pVCpu->iem.s.uInstrBufPc;
322	}
323
324
325	#endif /* !VMM_INCLUDED_SRC_VMMAll_IEMAllThrdTables_h */

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllThrdTables.h@ 100787

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